PowerPC hole tiles

These tiles are located inside the PowerPC holes, and serve a similar function to the terminator tiles.

`PPC_TERM_W`

This tile is located on the right of every interconnect row interrupted by the PowerPC hole. It reuses the bitstream tile of the rightmost INT.PPC tile of that row.

The interconnect signals prefixed with 0 refer to signals in the rightmost INT.PPC tile of the row. The interconnect signals prefixed with 1 refer to signals in the leftmost INT.PPC tile of the row.

Tile PPC_TERM_W

Cells: 2

Switchbox PPC_TERM_W

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[0]
Bits		Destination
MAIN[0][3]	MAIN[0][2]	CELL.HEX_E1[0]
		Source
0	0	FAR.HEX_E0[0]
0	1	CELL.HEX_W0[0]
1	0	CELL.LH[7]
1	1	CELL.LH[19]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[1]
Bits		Destination
MAIN[0][11]	MAIN[0][10]	CELL.HEX_E1[1]
		Source
0	0	FAR.HEX_E0[1]
0	1	CELL.HEX_W0[1]
1	0	CELL.LH[13]
1	1	CELL.LH[1]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[2]
Bits		Destination
MAIN[0][19]	MAIN[0][18]	CELL.HEX_E1[2]
		Source
0	0	FAR.HEX_E0[2]
0	1	CELL.HEX_W0[2]
1	0	CELL.LH[7]
1	1	CELL.LH[19]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[3]
Bits		Destination
MAIN[0][27]	MAIN[0][26]	CELL.HEX_E1[3]
		Source
0	0	FAR.HEX_E0[3]
0	1	CELL.HEX_W0[3]
1	0	CELL.LH[13]
1	1	CELL.LH[1]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[4]
Bits		Destination
MAIN[0][35]	MAIN[0][34]	CELL.HEX_E1[4]
		Source
0	0	FAR.HEX_E0[4]
0	1	CELL.HEX_W0[4]
1	0	CELL.LH[7]
1	1	CELL.LH[19]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[5]
Bits		Destination
MAIN[0][43]	MAIN[0][42]	CELL.HEX_E1[5]
		Source
0	0	FAR.HEX_E0[5]
0	1	CELL.HEX_W0[5]
1	0	CELL.LH[13]
1	1	CELL.LH[1]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[6]
Bits		Destination
MAIN[0][51]	MAIN[0][50]	CELL.HEX_E1[6]
		Source
0	0	FAR.HEX_E0[6]
0	1	CELL.HEX_W0[6]
1	0	CELL.LH[7]
1	1	CELL.LH[19]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[7]
Bits		Destination
MAIN[0][59]	MAIN[0][58]	CELL.HEX_E1[7]
		Source
0	0	FAR.HEX_E0[7]
0	1	CELL.HEX_W0[7]
1	0	CELL.LH[13]
1	1	CELL.LH[1]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[8]
Bits		Destination
MAIN[0][67]	MAIN[0][66]	CELL.HEX_E1[8]
		Source
0	0	FAR.HEX_E0[8]
0	1	CELL.HEX_W0[8]
1	0	CELL.LH[7]
1	1	CELL.LH[19]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E1[9]
Bits		Destination
MAIN[0][75]	MAIN[0][74]	CELL.HEX_E1[9]
		Source
0	0	FAR.HEX_E0[9]
0	1	CELL.HEX_W0[9]
1	0	CELL.LH[13]
1	1	CELL.LH[1]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[0]
Bits		Destination
MAIN[3][3]	MAIN[3][2]	CELL.HEX_E2[0]
		Source
0	0	FAR.HEX_E1[0]
0	1	CELL.HEX_W1[0]
1	0	CELL.LH[8]
1	1	CELL.LH[20]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[1]
Bits		Destination
MAIN[3][11]	MAIN[3][10]	CELL.HEX_E2[1]
		Source
0	0	FAR.HEX_E1[1]
0	1	CELL.HEX_W1[1]
1	0	CELL.LH[14]
1	1	CELL.LH[2]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[2]
Bits		Destination
MAIN[3][19]	MAIN[3][18]	CELL.HEX_E2[2]
		Source
0	0	FAR.HEX_E1[2]
0	1	CELL.HEX_W1[2]
1	0	CELL.LH[8]
1	1	CELL.LH[20]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[3]
Bits		Destination
MAIN[3][27]	MAIN[3][26]	CELL.HEX_E2[3]
		Source
0	0	FAR.HEX_E1[3]
0	1	CELL.HEX_W1[3]
1	0	CELL.LH[14]
1	1	CELL.LH[2]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[4]
Bits		Destination
MAIN[3][35]	MAIN[3][34]	CELL.HEX_E2[4]
		Source
0	0	FAR.HEX_E1[4]
0	1	CELL.HEX_W1[4]
1	0	CELL.LH[8]
1	1	CELL.LH[20]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[5]
Bits		Destination
MAIN[3][43]	MAIN[3][42]	CELL.HEX_E2[5]
		Source
0	0	FAR.HEX_E1[5]
0	1	CELL.HEX_W1[5]
1	0	CELL.LH[14]
1	1	CELL.LH[2]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[6]
Bits		Destination
MAIN[3][51]	MAIN[3][50]	CELL.HEX_E2[6]
		Source
0	0	FAR.HEX_E1[6]
0	1	CELL.HEX_W1[6]
1	0	CELL.LH[8]
1	1	CELL.LH[20]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[7]
Bits		Destination
MAIN[3][59]	MAIN[3][58]	CELL.HEX_E2[7]
		Source
0	0	FAR.HEX_E1[7]
0	1	CELL.HEX_W1[7]
1	0	CELL.LH[14]
1	1	CELL.LH[2]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[8]
Bits		Destination
MAIN[3][67]	MAIN[3][66]	CELL.HEX_E2[8]
		Source
0	0	FAR.HEX_E1[8]
0	1	CELL.HEX_W1[8]
1	0	CELL.LH[8]
1	1	CELL.LH[20]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E2[9]
Bits		Destination
MAIN[3][75]	MAIN[3][74]	CELL.HEX_E2[9]
		Source
0	0	FAR.HEX_E1[9]
0	1	CELL.HEX_W1[9]
1	0	CELL.LH[14]
1	1	CELL.LH[2]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[0]
Bits		Destination
MAIN[0][5]	MAIN[0][4]	CELL.HEX_E3[0]
		Source
0	0	FAR.HEX_E2[0]
0	1	CELL.HEX_W2[0]
1	0	CELL.LH[9]
1	1	CELL.LH[21]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[1]
Bits		Destination
MAIN[0][13]	MAIN[0][12]	CELL.HEX_E3[1]
		Source
0	0	FAR.HEX_E2[1]
0	1	CELL.HEX_W2[1]
1	0	CELL.LH[15]
1	1	CELL.LH[3]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[2]
Bits		Destination
MAIN[0][21]	MAIN[0][20]	CELL.HEX_E3[2]
		Source
0	0	FAR.HEX_E2[2]
0	1	CELL.HEX_W2[2]
1	0	CELL.LH[9]
1	1	CELL.LH[21]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[3]
Bits		Destination
MAIN[0][29]	MAIN[0][28]	CELL.HEX_E3[3]
		Source
0	0	FAR.HEX_E2[3]
0	1	CELL.HEX_W2[3]
1	0	CELL.LH[15]
1	1	CELL.LH[3]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[4]
Bits		Destination
MAIN[0][37]	MAIN[0][36]	CELL.HEX_E3[4]
		Source
0	0	FAR.HEX_E2[4]
0	1	CELL.HEX_W2[4]
1	0	CELL.LH[9]
1	1	CELL.LH[21]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[5]
Bits		Destination
MAIN[0][45]	MAIN[0][44]	CELL.HEX_E3[5]
		Source
0	0	FAR.HEX_E2[5]
0	1	CELL.HEX_W2[5]
1	0	CELL.LH[15]
1	1	CELL.LH[3]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[6]
Bits		Destination
MAIN[0][53]	MAIN[0][52]	CELL.HEX_E3[6]
		Source
0	0	FAR.HEX_E2[6]
0	1	CELL.HEX_W2[6]
1	0	CELL.LH[9]
1	1	CELL.LH[21]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[7]
Bits		Destination
MAIN[0][61]	MAIN[0][60]	CELL.HEX_E3[7]
		Source
0	0	FAR.HEX_E2[7]
0	1	CELL.HEX_W2[7]
1	0	CELL.LH[15]
1	1	CELL.LH[3]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[8]
Bits		Destination
MAIN[0][69]	MAIN[0][68]	CELL.HEX_E3[8]
		Source
0	0	FAR.HEX_E2[8]
0	1	CELL.HEX_W2[8]
1	0	CELL.LH[9]
1	1	CELL.LH[21]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E3[9]
Bits		Destination
MAIN[0][77]	MAIN[0][76]	CELL.HEX_E3[9]
		Source
0	0	FAR.HEX_E2[9]
0	1	CELL.HEX_W2[9]
1	0	CELL.LH[15]
1	1	CELL.LH[3]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[0]
Bits		Destination
MAIN[3][5]	MAIN[3][4]	CELL.HEX_E4[0]
		Source
0	0	FAR.HEX_E3[0]
0	1	CELL.HEX_W3[0]
1	0	CELL.LH[10]
1	1	CELL.LH[22]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[1]
Bits		Destination
MAIN[3][13]	MAIN[3][12]	CELL.HEX_E4[1]
		Source
0	0	FAR.HEX_E3[1]
0	1	CELL.HEX_W3[1]
1	0	CELL.LH[16]
1	1	CELL.LH[4]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[2]
Bits		Destination
MAIN[3][21]	MAIN[3][20]	CELL.HEX_E4[2]
		Source
0	0	FAR.HEX_E3[2]
0	1	CELL.HEX_W3[2]
1	0	CELL.LH[10]
1	1	CELL.LH[22]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[3]
Bits		Destination
MAIN[3][29]	MAIN[3][28]	CELL.HEX_E4[3]
		Source
0	0	FAR.HEX_E3[3]
0	1	CELL.HEX_W3[3]
1	0	CELL.LH[16]
1	1	CELL.LH[4]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[4]
Bits		Destination
MAIN[3][37]	MAIN[3][36]	CELL.HEX_E4[4]
		Source
0	0	FAR.HEX_E3[4]
0	1	CELL.HEX_W3[4]
1	0	CELL.LH[10]
1	1	CELL.LH[22]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[5]
Bits		Destination
MAIN[3][45]	MAIN[3][44]	CELL.HEX_E4[5]
		Source
0	0	FAR.HEX_E3[5]
0	1	CELL.HEX_W3[5]
1	0	CELL.LH[16]
1	1	CELL.LH[4]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[6]
Bits		Destination
MAIN[3][53]	MAIN[3][52]	CELL.HEX_E4[6]
		Source
0	0	FAR.HEX_E3[6]
0	1	CELL.HEX_W3[6]
1	0	CELL.LH[10]
1	1	CELL.LH[22]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[7]
Bits		Destination
MAIN[3][61]	MAIN[3][60]	CELL.HEX_E4[7]
		Source
0	0	FAR.HEX_E3[7]
0	1	CELL.HEX_W3[7]
1	0	CELL.LH[16]
1	1	CELL.LH[4]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[8]
Bits		Destination
MAIN[3][69]	MAIN[3][68]	CELL.HEX_E4[8]
		Source
0	0	FAR.HEX_E3[8]
0	1	CELL.HEX_W3[8]
1	0	CELL.LH[10]
1	1	CELL.LH[22]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E4[9]
Bits		Destination
MAIN[3][77]	MAIN[3][76]	CELL.HEX_E4[9]
		Source
0	0	FAR.HEX_E3[9]
0	1	CELL.HEX_W3[9]
1	0	CELL.LH[16]
1	1	CELL.LH[4]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[0]
Bits		Destination
MAIN[0][7]	MAIN[0][6]	CELL.HEX_E5[0]
		Source
0	0	FAR.HEX_E4[0]
0	1	CELL.HEX_W4[0]
1	0	CELL.LH[11]
1	1	CELL.LH[23]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[1]
Bits		Destination
MAIN[0][15]	MAIN[0][14]	CELL.HEX_E5[1]
		Source
0	0	FAR.HEX_E4[1]
0	1	CELL.HEX_W4[1]
1	0	CELL.LH[17]
1	1	CELL.LH[5]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[2]
Bits		Destination
MAIN[0][23]	MAIN[0][22]	CELL.HEX_E5[2]
		Source
0	0	FAR.HEX_E4[2]
0	1	CELL.HEX_W4[2]
1	0	CELL.LH[11]
1	1	CELL.LH[23]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[3]
Bits		Destination
MAIN[0][31]	MAIN[0][30]	CELL.HEX_E5[3]
		Source
0	0	FAR.HEX_E4[3]
0	1	CELL.HEX_W4[3]
1	0	CELL.LH[17]
1	1	CELL.LH[5]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[4]
Bits		Destination
MAIN[0][39]	MAIN[0][38]	CELL.HEX_E5[4]
		Source
0	0	FAR.HEX_E4[4]
0	1	CELL.HEX_W4[4]
1	0	CELL.LH[11]
1	1	CELL.LH[23]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[5]
Bits		Destination
MAIN[0][47]	MAIN[0][46]	CELL.HEX_E5[5]
		Source
0	0	FAR.HEX_E4[5]
0	1	CELL.HEX_W4[5]
1	0	CELL.LH[17]
1	1	CELL.LH[5]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[6]
Bits		Destination
MAIN[0][55]	MAIN[0][54]	CELL.HEX_E5[6]
		Source
0	0	FAR.HEX_E4[6]
0	1	CELL.HEX_W4[6]
1	0	CELL.LH[11]
1	1	CELL.LH[23]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[7]
Bits		Destination
MAIN[0][63]	MAIN[0][62]	CELL.HEX_E5[7]
		Source
0	0	FAR.HEX_E4[7]
0	1	CELL.HEX_W4[7]
1	0	CELL.LH[17]
1	1	CELL.LH[5]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[8]
Bits		Destination
MAIN[0][71]	MAIN[0][70]	CELL.HEX_E5[8]
		Source
0	0	FAR.HEX_E4[8]
0	1	CELL.HEX_W4[8]
1	0	CELL.LH[11]
1	1	CELL.LH[23]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E5[9]
Bits		Destination
MAIN[0][79]	MAIN[0][78]	CELL.HEX_E5[9]
		Source
0	0	FAR.HEX_E4[9]
0	1	CELL.HEX_W4[9]
1	0	CELL.LH[17]
1	1	CELL.LH[5]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[0]
Bits		Destination
MAIN[3][7]	MAIN[3][6]	CELL.HEX_E6[0]
		Source
0	0	FAR.HEX_E5[0]
0	1	CELL.HEX_W5[0]
1	0	CELL.LH[12]
1	1	CELL.LH[0]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[1]
Bits		Destination
MAIN[3][15]	MAIN[3][14]	CELL.HEX_E6[1]
		Source
0	0	FAR.HEX_E5[1]
0	1	CELL.HEX_W5[1]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[2]
Bits		Destination
MAIN[3][23]	MAIN[3][22]	CELL.HEX_E6[2]
		Source
0	0	FAR.HEX_E5[2]
0	1	CELL.HEX_W5[2]
1	0	CELL.LH[12]
1	1	CELL.LH[0]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[3]
Bits		Destination
MAIN[3][31]	MAIN[3][30]	CELL.HEX_E6[3]
		Source
0	0	FAR.HEX_E5[3]
0	1	CELL.HEX_W5[3]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[4]
Bits		Destination
MAIN[3][39]	MAIN[3][38]	CELL.HEX_E6[4]
		Source
0	0	FAR.HEX_E5[4]
0	1	CELL.HEX_W5[4]
1	0	CELL.LH[12]
1	1	CELL.LH[0]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[5]
Bits		Destination
MAIN[3][47]	MAIN[3][46]	CELL.HEX_E6[5]
		Source
0	0	FAR.HEX_E5[5]
0	1	CELL.HEX_W5[5]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[6]
Bits		Destination
MAIN[3][55]	MAIN[3][54]	CELL.HEX_E6[6]
		Source
0	0	FAR.HEX_E5[6]
0	1	CELL.HEX_W5[6]
1	0	CELL.LH[12]
1	1	CELL.LH[0]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[7]
Bits		Destination
MAIN[3][63]	MAIN[3][62]	CELL.HEX_E6[7]
		Source
0	0	FAR.HEX_E5[7]
0	1	CELL.HEX_W5[7]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[8]
Bits		Destination
MAIN[3][71]	MAIN[3][70]	CELL.HEX_E6[8]
		Source
0	0	FAR.HEX_E5[8]
0	1	CELL.HEX_W5[8]
1	0	CELL.LH[12]
1	1	CELL.LH[0]

virtex2 PPC_TERM_W switchbox PPC_TERM_W muxes HEX_E6[9]
Bits		Destination
MAIN[3][79]	MAIN[3][78]	CELL.HEX_E6[9]
		Source
0	0	FAR.HEX_E5[9]
0	1	CELL.HEX_W5[9]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

Bitstream

virtex2 PPC_TERM_W rect MAIN
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[9] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[9] bit 1
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[9] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[9] bit 0
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[9] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[9] bit 1
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[9] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[9] bit 0
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[9] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[9] bit 1
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[9] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[9] bit 0
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[8] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[8] bit 1
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[8] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[8] bit 0
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[8] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[8] bit 1
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[8] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[8] bit 0
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[8] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[8] bit 1
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[8] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[8] bit 0
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[7] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[7] bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[7] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[7] bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[7] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[7] bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[7] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[7] bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[7] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[7] bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[7] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[7] bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[6] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[6] bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[6] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[6] bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[6] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[6] bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[6] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[6] bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[6] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[6] bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[6] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[6] bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[5] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[5] bit 1
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[5] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[5] bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[5] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[5] bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[5] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[5] bit 0
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[5] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[5] bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[5] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[5] bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[4] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[4] bit 1
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[4] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[4] bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[4] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[4] bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[4] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[4] bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[4] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[4] bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[4] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[4] bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[3] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[3] bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[3] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[3] bit 0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[3] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[3] bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[3] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[3] bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[3] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[3] bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[3] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[3] bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[2] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[2] bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[2] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[2] bit 0
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[2] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[2] bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[2] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[2] bit 0
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[2] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[2] bit 1
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[2] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[2] bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[1] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[1] bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[1] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[1] bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[1] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[1] bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[1] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[1] bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[1] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[1] bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[1] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[1] bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[0] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E5[0] bit 1
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E6[0] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E5[0] bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[0] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E3[0] bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E4[0] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E3[0] bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[0] bit 1	-	-	PPC_TERM_W: mux CELL.HEX_E1[0] bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_W: mux CELL.HEX_E2[0] bit 0	-	-	PPC_TERM_W: mux CELL.HEX_E1[0] bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

`PPC_TERM_E`

This tile is located on the left of every interconnect row interrupted by the PowerPC hole. It reuses the bitstream tile of the leftmost INT.PPC tile of that row.

The interconnect signals prefixed with 0 refer to signals in the leftmost INT.PPC tile of the row. The interconnect signals prefixed with 1 refer to signals in the rightmost INT.PPC tile of the row.

Tile PPC_TERM_E

Cells: 2

Switchbox PPC_TERM_E

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[0]
Bits		Destination
MAIN[3][3]	MAIN[3][2]	CELL.HEX_W1[0]
		Source
0	0	FAR.HEX_W0[0]
0	1	CELL.HEX_E0[0]
1	0	CELL.LH[5]
1	1	CELL.LH[17]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[1]
Bits		Destination
MAIN[3][11]	MAIN[3][10]	CELL.HEX_W1[1]
		Source
0	0	FAR.HEX_W0[1]
0	1	CELL.HEX_E0[1]
1	0	CELL.LH[23]
1	1	CELL.LH[11]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[2]
Bits		Destination
MAIN[3][19]	MAIN[3][18]	CELL.HEX_W1[2]
		Source
0	0	FAR.HEX_W0[2]
0	1	CELL.HEX_E0[2]
1	0	CELL.LH[5]
1	1	CELL.LH[17]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[3]
Bits		Destination
MAIN[3][27]	MAIN[3][26]	CELL.HEX_W1[3]
		Source
0	0	FAR.HEX_W0[3]
0	1	CELL.HEX_E0[3]
1	0	CELL.LH[23]
1	1	CELL.LH[11]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[4]
Bits		Destination
MAIN[3][35]	MAIN[3][34]	CELL.HEX_W1[4]
		Source
0	0	FAR.HEX_W0[4]
0	1	CELL.HEX_E0[4]
1	0	CELL.LH[5]
1	1	CELL.LH[17]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[5]
Bits		Destination
MAIN[3][43]	MAIN[3][42]	CELL.HEX_W1[5]
		Source
0	0	FAR.HEX_W0[5]
0	1	CELL.HEX_E0[5]
1	0	CELL.LH[23]
1	1	CELL.LH[11]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[6]
Bits		Destination
MAIN[3][51]	MAIN[3][50]	CELL.HEX_W1[6]
		Source
0	0	FAR.HEX_W0[6]
0	1	CELL.HEX_E0[6]
1	0	CELL.LH[5]
1	1	CELL.LH[17]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[7]
Bits		Destination
MAIN[3][59]	MAIN[3][58]	CELL.HEX_W1[7]
		Source
0	0	FAR.HEX_W0[7]
0	1	CELL.HEX_E0[7]
1	0	CELL.LH[23]
1	1	CELL.LH[11]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[8]
Bits		Destination
MAIN[3][67]	MAIN[3][66]	CELL.HEX_W1[8]
		Source
0	0	FAR.HEX_W0[8]
0	1	CELL.HEX_E0[8]
1	0	CELL.LH[5]
1	1	CELL.LH[17]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W1[9]
Bits		Destination
MAIN[3][75]	MAIN[3][74]	CELL.HEX_W1[9]
		Source
0	0	FAR.HEX_W0[9]
0	1	CELL.HEX_E0[9]
1	0	CELL.LH[23]
1	1	CELL.LH[11]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[0]
Bits		Destination
MAIN[0][3]	MAIN[0][2]	CELL.HEX_W2[0]
		Source
0	0	FAR.HEX_W1[0]
0	1	CELL.HEX_E1[0]
1	0	CELL.LH[4]
1	1	CELL.LH[16]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[1]
Bits		Destination
MAIN[0][11]	MAIN[0][10]	CELL.HEX_W2[1]
		Source
0	0	FAR.HEX_W1[1]
0	1	CELL.HEX_E1[1]
1	0	CELL.LH[22]
1	1	CELL.LH[10]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[2]
Bits		Destination
MAIN[0][19]	MAIN[0][18]	CELL.HEX_W2[2]
		Source
0	0	FAR.HEX_W1[2]
0	1	CELL.HEX_E1[2]
1	0	CELL.LH[4]
1	1	CELL.LH[16]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[3]
Bits		Destination
MAIN[0][27]	MAIN[0][26]	CELL.HEX_W2[3]
		Source
0	0	FAR.HEX_W1[3]
0	1	CELL.HEX_E1[3]
1	0	CELL.LH[22]
1	1	CELL.LH[10]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[4]
Bits		Destination
MAIN[0][35]	MAIN[0][34]	CELL.HEX_W2[4]
		Source
0	0	FAR.HEX_W1[4]
0	1	CELL.HEX_E1[4]
1	0	CELL.LH[4]
1	1	CELL.LH[16]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[5]
Bits		Destination
MAIN[0][43]	MAIN[0][42]	CELL.HEX_W2[5]
		Source
0	0	FAR.HEX_W1[5]
0	1	CELL.HEX_E1[5]
1	0	CELL.LH[22]
1	1	CELL.LH[10]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[6]
Bits		Destination
MAIN[0][51]	MAIN[0][50]	CELL.HEX_W2[6]
		Source
0	0	FAR.HEX_W1[6]
0	1	CELL.HEX_E1[6]
1	0	CELL.LH[4]
1	1	CELL.LH[16]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[7]
Bits		Destination
MAIN[0][59]	MAIN[0][58]	CELL.HEX_W2[7]
		Source
0	0	FAR.HEX_W1[7]
0	1	CELL.HEX_E1[7]
1	0	CELL.LH[22]
1	1	CELL.LH[10]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[8]
Bits		Destination
MAIN[0][67]	MAIN[0][66]	CELL.HEX_W2[8]
		Source
0	0	FAR.HEX_W1[8]
0	1	CELL.HEX_E1[8]
1	0	CELL.LH[4]
1	1	CELL.LH[16]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W2[9]
Bits		Destination
MAIN[0][75]	MAIN[0][74]	CELL.HEX_W2[9]
		Source
0	0	FAR.HEX_W1[9]
0	1	CELL.HEX_E1[9]
1	0	CELL.LH[22]
1	1	CELL.LH[10]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[0]
Bits		Destination
MAIN[3][5]	MAIN[3][4]	CELL.HEX_W3[0]
		Source
0	0	FAR.HEX_W2[0]
0	1	CELL.HEX_E2[0]
1	0	CELL.LH[3]
1	1	CELL.LH[15]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[1]
Bits		Destination
MAIN[3][13]	MAIN[3][12]	CELL.HEX_W3[1]
		Source
0	0	FAR.HEX_W2[1]
0	1	CELL.HEX_E2[1]
1	0	CELL.LH[21]
1	1	CELL.LH[9]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[2]
Bits		Destination
MAIN[3][21]	MAIN[3][20]	CELL.HEX_W3[2]
		Source
0	0	FAR.HEX_W2[2]
0	1	CELL.HEX_E2[2]
1	0	CELL.LH[3]
1	1	CELL.LH[15]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[3]
Bits		Destination
MAIN[3][29]	MAIN[3][28]	CELL.HEX_W3[3]
		Source
0	0	FAR.HEX_W2[3]
0	1	CELL.HEX_E2[3]
1	0	CELL.LH[21]
1	1	CELL.LH[9]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[4]
Bits		Destination
MAIN[3][37]	MAIN[3][36]	CELL.HEX_W3[4]
		Source
0	0	FAR.HEX_W2[4]
0	1	CELL.HEX_E2[4]
1	0	CELL.LH[3]
1	1	CELL.LH[15]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[5]
Bits		Destination
MAIN[3][45]	MAIN[3][44]	CELL.HEX_W3[5]
		Source
0	0	FAR.HEX_W2[5]
0	1	CELL.HEX_E2[5]
1	0	CELL.LH[21]
1	1	CELL.LH[9]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[6]
Bits		Destination
MAIN[3][53]	MAIN[3][52]	CELL.HEX_W3[6]
		Source
0	0	FAR.HEX_W2[6]
0	1	CELL.HEX_E2[6]
1	0	CELL.LH[3]
1	1	CELL.LH[15]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[7]
Bits		Destination
MAIN[3][61]	MAIN[3][60]	CELL.HEX_W3[7]
		Source
0	0	FAR.HEX_W2[7]
0	1	CELL.HEX_E2[7]
1	0	CELL.LH[21]
1	1	CELL.LH[9]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[8]
Bits		Destination
MAIN[3][69]	MAIN[3][68]	CELL.HEX_W3[8]
		Source
0	0	FAR.HEX_W2[8]
0	1	CELL.HEX_E2[8]
1	0	CELL.LH[3]
1	1	CELL.LH[15]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W3[9]
Bits		Destination
MAIN[3][77]	MAIN[3][76]	CELL.HEX_W3[9]
		Source
0	0	FAR.HEX_W2[9]
0	1	CELL.HEX_E2[9]
1	0	CELL.LH[21]
1	1	CELL.LH[9]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[0]
Bits		Destination
MAIN[0][5]	MAIN[0][4]	CELL.HEX_W4[0]
		Source
0	0	FAR.HEX_W3[0]
0	1	CELL.HEX_E3[0]
1	0	CELL.LH[2]
1	1	CELL.LH[14]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[1]
Bits		Destination
MAIN[0][13]	MAIN[0][12]	CELL.HEX_W4[1]
		Source
0	0	FAR.HEX_W3[1]
0	1	CELL.HEX_E3[1]
1	0	CELL.LH[20]
1	1	CELL.LH[8]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[2]
Bits		Destination
MAIN[0][21]	MAIN[0][20]	CELL.HEX_W4[2]
		Source
0	0	FAR.HEX_W3[2]
0	1	CELL.HEX_E3[2]
1	0	CELL.LH[2]
1	1	CELL.LH[14]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[3]
Bits		Destination
MAIN[0][29]	MAIN[0][28]	CELL.HEX_W4[3]
		Source
0	0	FAR.HEX_W3[3]
0	1	CELL.HEX_E3[3]
1	0	CELL.LH[20]
1	1	CELL.LH[8]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[4]
Bits		Destination
MAIN[0][37]	MAIN[0][36]	CELL.HEX_W4[4]
		Source
0	0	FAR.HEX_W3[4]
0	1	CELL.HEX_E3[4]
1	0	CELL.LH[2]
1	1	CELL.LH[14]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[5]
Bits		Destination
MAIN[0][45]	MAIN[0][44]	CELL.HEX_W4[5]
		Source
0	0	FAR.HEX_W3[5]
0	1	CELL.HEX_E3[5]
1	0	CELL.LH[20]
1	1	CELL.LH[8]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[6]
Bits		Destination
MAIN[0][53]	MAIN[0][52]	CELL.HEX_W4[6]
		Source
0	0	FAR.HEX_W3[6]
0	1	CELL.HEX_E3[6]
1	0	CELL.LH[2]
1	1	CELL.LH[14]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[7]
Bits		Destination
MAIN[0][61]	MAIN[0][60]	CELL.HEX_W4[7]
		Source
0	0	FAR.HEX_W3[7]
0	1	CELL.HEX_E3[7]
1	0	CELL.LH[20]
1	1	CELL.LH[8]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[8]
Bits		Destination
MAIN[0][69]	MAIN[0][68]	CELL.HEX_W4[8]
		Source
0	0	FAR.HEX_W3[8]
0	1	CELL.HEX_E3[8]
1	0	CELL.LH[2]
1	1	CELL.LH[14]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W4[9]
Bits		Destination
MAIN[0][77]	MAIN[0][76]	CELL.HEX_W4[9]
		Source
0	0	FAR.HEX_W3[9]
0	1	CELL.HEX_E3[9]
1	0	CELL.LH[20]
1	1	CELL.LH[8]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[0]
Bits		Destination
MAIN[3][7]	MAIN[3][6]	CELL.HEX_W5[0]
		Source
0	0	FAR.HEX_W4[0]
0	1	CELL.HEX_E4[0]
1	0	CELL.LH[1]
1	1	CELL.LH[13]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[1]
Bits		Destination
MAIN[3][15]	MAIN[3][14]	CELL.HEX_W5[1]
		Source
0	0	FAR.HEX_W4[1]
0	1	CELL.HEX_E4[1]
1	0	CELL.LH[19]
1	1	CELL.LH[7]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[2]
Bits		Destination
MAIN[3][23]	MAIN[3][22]	CELL.HEX_W5[2]
		Source
0	0	FAR.HEX_W4[2]
0	1	CELL.HEX_E4[2]
1	0	CELL.LH[1]
1	1	CELL.LH[13]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[3]
Bits		Destination
MAIN[3][31]	MAIN[3][30]	CELL.HEX_W5[3]
		Source
0	0	FAR.HEX_W4[3]
0	1	CELL.HEX_E4[3]
1	0	CELL.LH[19]
1	1	CELL.LH[7]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[4]
Bits		Destination
MAIN[3][39]	MAIN[3][38]	CELL.HEX_W5[4]
		Source
0	0	FAR.HEX_W4[4]
0	1	CELL.HEX_E4[4]
1	0	CELL.LH[1]
1	1	CELL.LH[13]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[5]
Bits		Destination
MAIN[3][47]	MAIN[3][46]	CELL.HEX_W5[5]
		Source
0	0	FAR.HEX_W4[5]
0	1	CELL.HEX_E4[5]
1	0	CELL.LH[19]
1	1	CELL.LH[7]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[6]
Bits		Destination
MAIN[3][55]	MAIN[3][54]	CELL.HEX_W5[6]
		Source
0	0	FAR.HEX_W4[6]
0	1	CELL.HEX_E4[6]
1	0	CELL.LH[1]
1	1	CELL.LH[13]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[7]
Bits		Destination
MAIN[3][63]	MAIN[3][62]	CELL.HEX_W5[7]
		Source
0	0	FAR.HEX_W4[7]
0	1	CELL.HEX_E4[7]
1	0	CELL.LH[19]
1	1	CELL.LH[7]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[8]
Bits		Destination
MAIN[3][71]	MAIN[3][70]	CELL.HEX_W5[8]
		Source
0	0	FAR.HEX_W4[8]
0	1	CELL.HEX_E4[8]
1	0	CELL.LH[1]
1	1	CELL.LH[13]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W5[9]
Bits		Destination
MAIN[3][79]	MAIN[3][78]	CELL.HEX_W5[9]
		Source
0	0	FAR.HEX_W4[9]
0	1	CELL.HEX_E4[9]
1	0	CELL.LH[19]
1	1	CELL.LH[7]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[0]
Bits		Destination
MAIN[0][7]	MAIN[0][6]	CELL.HEX_W6[0]
		Source
0	0	FAR.HEX_W5[0]
0	1	CELL.HEX_E5[0]
1	0	CELL.LH[0]
1	1	CELL.LH[12]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[1]
Bits		Destination
MAIN[0][15]	MAIN[0][14]	CELL.HEX_W6[1]
		Source
0	0	FAR.HEX_W5[1]
0	1	CELL.HEX_E5[1]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[2]
Bits		Destination
MAIN[0][23]	MAIN[0][22]	CELL.HEX_W6[2]
		Source
0	0	FAR.HEX_W5[2]
0	1	CELL.HEX_E5[2]
1	0	CELL.LH[0]
1	1	CELL.LH[12]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[3]
Bits		Destination
MAIN[0][31]	MAIN[0][30]	CELL.HEX_W6[3]
		Source
0	0	FAR.HEX_W5[3]
0	1	CELL.HEX_E5[3]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[4]
Bits		Destination
MAIN[0][39]	MAIN[0][38]	CELL.HEX_W6[4]
		Source
0	0	FAR.HEX_W5[4]
0	1	CELL.HEX_E5[4]
1	0	CELL.LH[0]
1	1	CELL.LH[12]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[5]
Bits		Destination
MAIN[0][47]	MAIN[0][46]	CELL.HEX_W6[5]
		Source
0	0	FAR.HEX_W5[5]
0	1	CELL.HEX_E5[5]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[6]
Bits		Destination
MAIN[0][55]	MAIN[0][54]	CELL.HEX_W6[6]
		Source
0	0	FAR.HEX_W5[6]
0	1	CELL.HEX_E5[6]
1	0	CELL.LH[0]
1	1	CELL.LH[12]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[7]
Bits		Destination
MAIN[0][63]	MAIN[0][62]	CELL.HEX_W6[7]
		Source
0	0	FAR.HEX_W5[7]
0	1	CELL.HEX_E5[7]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[8]
Bits		Destination
MAIN[0][71]	MAIN[0][70]	CELL.HEX_W6[8]
		Source
0	0	FAR.HEX_W5[8]
0	1	CELL.HEX_E5[8]
1	0	CELL.LH[0]
1	1	CELL.LH[12]

virtex2 PPC_TERM_E switchbox PPC_TERM_E muxes HEX_W6[9]
Bits		Destination
MAIN[0][79]	MAIN[0][78]	CELL.HEX_W6[9]
		Source
0	0	FAR.HEX_W5[9]
0	1	CELL.HEX_E5[9]
1	0	CELL.LH[18]
1	1	CELL.LH[6]

Bitstream

virtex2 PPC_TERM_E rect MAIN
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[9] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[9] bit 1
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[9] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[9] bit 0
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[9] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[9] bit 1
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[9] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[9] bit 0
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[9] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[9] bit 1
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[9] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[9] bit 0
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[8] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[8] bit 1
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[8] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[8] bit 0
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[8] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[8] bit 1
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[8] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[8] bit 0
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[8] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[8] bit 1
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[8] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[8] bit 0
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[7] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[7] bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[7] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[7] bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[7] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[7] bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[7] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[7] bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[7] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[7] bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[7] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[7] bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[6] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[6] bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[6] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[6] bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[6] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[6] bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[6] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[6] bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[6] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[6] bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[6] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[6] bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[5] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[5] bit 1
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[5] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[5] bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[5] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[5] bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[5] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[5] bit 0
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[5] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[5] bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[5] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[5] bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[4] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[4] bit 1
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[4] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[4] bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[4] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[4] bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[4] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[4] bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[4] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[4] bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[4] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[4] bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[3] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[3] bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[3] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[3] bit 0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[3] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[3] bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[3] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[3] bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[3] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[3] bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[3] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[3] bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[2] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[2] bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[2] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[2] bit 0
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[2] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[2] bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[2] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[2] bit 0
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[2] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[2] bit 1
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[2] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[2] bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[1] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[1] bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[1] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[1] bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[1] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[1] bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[1] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[1] bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[1] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[1] bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[1] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[1] bit 0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[0] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W6[0] bit 1
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W5[0] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W6[0] bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[0] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W4[0] bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W3[0] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W4[0] bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[0] bit 1	-	-	PPC_TERM_E: mux CELL.HEX_W2[0] bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PPC_TERM_E: mux CELL.HEX_W1[0] bit 0	-	-	PPC_TERM_E: mux CELL.HEX_W2[0] bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

`PPC_TERM_S`

This tile is located on the top of every interconnect column interrupted by the PowerPC hole. It uses the bitstream tile corresponding to the interconnect tile below the topmost INT.PPC tile of the column (which is otherwise empty, as it doesn’t contain an INT.* tile).

The interconnect signals prefixed with 0 refer to signals in the topmost INT.PPC tile of the row. The interconnect signals prefixed with 1 refer to signals in the bottommost INT.PPC tile of the row.

Tile PPC_TERM_S

Cells: 2

Switchbox PPC_TERM_S

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[0]
Bits		Destination
MAIN[9][75]	MAIN[9][74]	CELL.HEX_N1[0]
		Source
0	0	FAR.HEX_N0[0]
0	1	CELL.HEX_S0[0]
1	0	CELL.LV[23]
1	1	CELL.LV[11]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[1]
Bits		Destination
MAIN[21][75]	MAIN[21][74]	CELL.HEX_N1[1]
		Source
0	0	FAR.HEX_N0[1]
0	1	CELL.HEX_S0[1]
1	0	CELL.LV[17]
1	1	CELL.LV[5]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[2]
Bits		Destination
MAIN[14][75]	MAIN[14][74]	CELL.HEX_N1[2]
		Source
0	0	FAR.HEX_N0[2]
0	1	CELL.HEX_S0[2]
1	0	CELL.LV[23]
1	1	CELL.LV[11]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[3]
Bits		Destination
MAIN[6][75]	MAIN[6][74]	CELL.HEX_N1[3]
		Source
0	0	FAR.HEX_N0[3]
0	1	CELL.HEX_S0[3]
1	0	CELL.LV[17]
1	1	CELL.LV[5]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[4]
Bits		Destination
MAIN[18][75]	MAIN[18][74]	CELL.HEX_N1[4]
		Source
0	0	FAR.HEX_N0[4]
0	1	CELL.HEX_S0[4]
1	0	CELL.LV[23]
1	1	CELL.LV[11]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[5]
Bits		Destination
MAIN[13][75]	MAIN[13][74]	CELL.HEX_N1[5]
		Source
0	0	FAR.HEX_N0[5]
0	1	CELL.HEX_S0[5]
1	0	CELL.LV[17]
1	1	CELL.LV[5]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[6]
Bits		Destination
MAIN[5][75]	MAIN[5][74]	CELL.HEX_N1[6]
		Source
0	0	FAR.HEX_N0[6]
0	1	CELL.HEX_S0[6]
1	0	CELL.LV[23]
1	1	CELL.LV[11]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[7]
Bits		Destination
MAIN[17][75]	MAIN[17][74]	CELL.HEX_N1[7]
		Source
0	0	FAR.HEX_N0[7]
0	1	CELL.HEX_S0[7]
1	0	CELL.LV[17]
1	1	CELL.LV[5]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[8]
Bits		Destination
MAIN[10][75]	MAIN[10][74]	CELL.HEX_N1[8]
		Source
0	0	FAR.HEX_N0[8]
0	1	CELL.HEX_S0[8]
1	0	CELL.LV[23]
1	1	CELL.LV[11]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N1[9]
Bits		Destination
MAIN[0][75]	MAIN[0][74]	CELL.HEX_N1[9]
		Source
0	0	FAR.HEX_N0[9]
0	1	CELL.HEX_S0[9]
1	0	CELL.LV[17]
1	1	CELL.LV[5]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[0]
Bits		Destination
MAIN[8][75]	MAIN[8][74]	CELL.HEX_N2[0]
		Source
0	0	FAR.HEX_N1[0]
0	1	CELL.HEX_S1[0]
1	0	CELL.LV[22]
1	1	CELL.LV[10]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[1]
Bits		Destination
MAIN[20][75]	MAIN[20][74]	CELL.HEX_N2[1]
		Source
0	0	FAR.HEX_N1[1]
0	1	CELL.HEX_S1[1]
1	0	CELL.LV[16]
1	1	CELL.LV[4]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[2]
Bits		Destination
MAIN[15][75]	MAIN[15][74]	CELL.HEX_N2[2]
		Source
0	0	FAR.HEX_N1[2]
0	1	CELL.HEX_S1[2]
1	0	CELL.LV[22]
1	1	CELL.LV[10]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[3]
Bits		Destination
MAIN[7][75]	MAIN[7][74]	CELL.HEX_N2[3]
		Source
0	0	FAR.HEX_N1[3]
0	1	CELL.HEX_S1[3]
1	0	CELL.LV[16]
1	1	CELL.LV[4]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[4]
Bits		Destination
MAIN[19][75]	MAIN[19][74]	CELL.HEX_N2[4]
		Source
0	0	FAR.HEX_N1[4]
0	1	CELL.HEX_S1[4]
1	0	CELL.LV[22]
1	1	CELL.LV[10]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[5]
Bits		Destination
MAIN[12][75]	MAIN[12][74]	CELL.HEX_N2[5]
		Source
0	0	FAR.HEX_N1[5]
0	1	CELL.HEX_S1[5]
1	0	CELL.LV[16]
1	1	CELL.LV[4]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[6]
Bits		Destination
MAIN[4][75]	MAIN[4][74]	CELL.HEX_N2[6]
		Source
0	0	FAR.HEX_N1[6]
0	1	CELL.HEX_S1[6]
1	0	CELL.LV[22]
1	1	CELL.LV[10]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[7]
Bits		Destination
MAIN[16][75]	MAIN[16][74]	CELL.HEX_N2[7]
		Source
0	0	FAR.HEX_N1[7]
0	1	CELL.HEX_S1[7]
1	0	CELL.LV[16]
1	1	CELL.LV[4]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[8]
Bits		Destination
MAIN[11][75]	MAIN[11][74]	CELL.HEX_N2[8]
		Source
0	0	FAR.HEX_N1[8]
0	1	CELL.HEX_S1[8]
1	0	CELL.LV[22]
1	1	CELL.LV[10]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N2[9]
Bits		Destination
MAIN[3][75]	MAIN[3][74]	CELL.HEX_N2[9]
		Source
0	0	FAR.HEX_N1[9]
0	1	CELL.HEX_S1[9]
1	0	CELL.LV[16]
1	1	CELL.LV[4]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[0]
Bits		Destination
MAIN[9][77]	MAIN[9][76]	CELL.HEX_N3[0]
		Source
0	0	FAR.HEX_N2[0]
0	1	CELL.HEX_S2[0]
1	0	CELL.LV[21]
1	1	CELL.LV[9]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[1]
Bits		Destination
MAIN[21][77]	MAIN[21][76]	CELL.HEX_N3[1]
		Source
0	0	FAR.HEX_N2[1]
0	1	CELL.HEX_S2[1]
1	0	CELL.LV[15]
1	1	CELL.LV[3]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[2]
Bits		Destination
MAIN[14][77]	MAIN[14][76]	CELL.HEX_N3[2]
		Source
0	0	FAR.HEX_N2[2]
0	1	CELL.HEX_S2[2]
1	0	CELL.LV[21]
1	1	CELL.LV[9]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[3]
Bits		Destination
MAIN[6][77]	MAIN[6][76]	CELL.HEX_N3[3]
		Source
0	0	FAR.HEX_N2[3]
0	1	CELL.HEX_S2[3]
1	0	CELL.LV[15]
1	1	CELL.LV[3]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[4]
Bits		Destination
MAIN[18][77]	MAIN[18][76]	CELL.HEX_N3[4]
		Source
0	0	FAR.HEX_N2[4]
0	1	CELL.HEX_S2[4]
1	0	CELL.LV[21]
1	1	CELL.LV[9]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[5]
Bits		Destination
MAIN[13][77]	MAIN[13][76]	CELL.HEX_N3[5]
		Source
0	0	FAR.HEX_N2[5]
0	1	CELL.HEX_S2[5]
1	0	CELL.LV[15]
1	1	CELL.LV[3]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[6]
Bits		Destination
MAIN[5][77]	MAIN[5][76]	CELL.HEX_N3[6]
		Source
0	0	FAR.HEX_N2[6]
0	1	CELL.HEX_S2[6]
1	0	CELL.LV[21]
1	1	CELL.LV[9]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[7]
Bits		Destination
MAIN[17][77]	MAIN[17][76]	CELL.HEX_N3[7]
		Source
0	0	FAR.HEX_N2[7]
0	1	CELL.HEX_S2[7]
1	0	CELL.LV[15]
1	1	CELL.LV[3]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[8]
Bits		Destination
MAIN[10][77]	MAIN[10][76]	CELL.HEX_N3[8]
		Source
0	0	FAR.HEX_N2[8]
0	1	CELL.HEX_S2[8]
1	0	CELL.LV[21]
1	1	CELL.LV[9]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N3[9]
Bits		Destination
MAIN[0][77]	MAIN[0][76]	CELL.HEX_N3[9]
		Source
0	0	FAR.HEX_N2[9]
0	1	CELL.HEX_S2[9]
1	0	CELL.LV[15]
1	1	CELL.LV[3]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[0]
Bits		Destination
MAIN[8][77]	MAIN[8][76]	CELL.HEX_N4[0]
		Source
0	0	FAR.HEX_N3[0]
0	1	CELL.HEX_S3[0]
1	0	CELL.LV[20]
1	1	CELL.LV[8]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[1]
Bits		Destination
MAIN[20][77]	MAIN[20][76]	CELL.HEX_N4[1]
		Source
0	0	FAR.HEX_N3[1]
0	1	CELL.HEX_S3[1]
1	0	CELL.LV[14]
1	1	CELL.LV[2]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[2]
Bits		Destination
MAIN[15][77]	MAIN[15][76]	CELL.HEX_N4[2]
		Source
0	0	FAR.HEX_N3[2]
0	1	CELL.HEX_S3[2]
1	0	CELL.LV[20]
1	1	CELL.LV[8]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[3]
Bits		Destination
MAIN[7][77]	MAIN[7][76]	CELL.HEX_N4[3]
		Source
0	0	FAR.HEX_N3[3]
0	1	CELL.HEX_S3[3]
1	0	CELL.LV[14]
1	1	CELL.LV[2]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[4]
Bits		Destination
MAIN[19][77]	MAIN[19][76]	CELL.HEX_N4[4]
		Source
0	0	FAR.HEX_N3[4]
0	1	CELL.HEX_S3[4]
1	0	CELL.LV[20]
1	1	CELL.LV[8]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[5]
Bits		Destination
MAIN[12][77]	MAIN[12][76]	CELL.HEX_N4[5]
		Source
0	0	FAR.HEX_N3[5]
0	1	CELL.HEX_S3[5]
1	0	CELL.LV[14]
1	1	CELL.LV[2]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[6]
Bits		Destination
MAIN[4][77]	MAIN[4][76]	CELL.HEX_N4[6]
		Source
0	0	FAR.HEX_N3[6]
0	1	CELL.HEX_S3[6]
1	0	CELL.LV[20]
1	1	CELL.LV[8]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[7]
Bits		Destination
MAIN[16][77]	MAIN[16][76]	CELL.HEX_N4[7]
		Source
0	0	FAR.HEX_N3[7]
0	1	CELL.HEX_S3[7]
1	0	CELL.LV[14]
1	1	CELL.LV[2]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[8]
Bits		Destination
MAIN[11][77]	MAIN[11][76]	CELL.HEX_N4[8]
		Source
0	0	FAR.HEX_N3[8]
0	1	CELL.HEX_S3[8]
1	0	CELL.LV[20]
1	1	CELL.LV[8]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N4[9]
Bits		Destination
MAIN[3][77]	MAIN[3][76]	CELL.HEX_N4[9]
		Source
0	0	FAR.HEX_N3[9]
0	1	CELL.HEX_S3[9]
1	0	CELL.LV[14]
1	1	CELL.LV[2]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[0]
Bits		Destination
MAIN[9][79]	MAIN[9][78]	CELL.HEX_N5[0]
		Source
0	0	FAR.HEX_N4[0]
0	1	CELL.HEX_S4[0]
1	0	CELL.LV[19]
1	1	CELL.LV[7]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[1]
Bits		Destination
MAIN[21][79]	MAIN[21][78]	CELL.HEX_N5[1]
		Source
0	0	FAR.HEX_N4[1]
0	1	CELL.HEX_S4[1]
1	0	CELL.LV[13]
1	1	CELL.LV[1]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[2]
Bits		Destination
MAIN[14][79]	MAIN[14][78]	CELL.HEX_N5[2]
		Source
0	0	FAR.HEX_N4[2]
0	1	CELL.HEX_S4[2]
1	0	CELL.LV[19]
1	1	CELL.LV[7]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[3]
Bits		Destination
MAIN[6][79]	MAIN[6][78]	CELL.HEX_N5[3]
		Source
0	0	FAR.HEX_N4[3]
0	1	CELL.HEX_S4[3]
1	0	CELL.LV[13]
1	1	CELL.LV[1]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[4]
Bits		Destination
MAIN[18][79]	MAIN[18][78]	CELL.HEX_N5[4]
		Source
0	0	FAR.HEX_N4[4]
0	1	CELL.HEX_S4[4]
1	0	CELL.LV[19]
1	1	CELL.LV[7]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[5]
Bits		Destination
MAIN[13][79]	MAIN[13][78]	CELL.HEX_N5[5]
		Source
0	0	FAR.HEX_N4[5]
0	1	CELL.HEX_S4[5]
1	0	CELL.LV[13]
1	1	CELL.LV[1]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[6]
Bits		Destination
MAIN[5][79]	MAIN[5][78]	CELL.HEX_N5[6]
		Source
0	0	FAR.HEX_N4[6]
0	1	CELL.HEX_S4[6]
1	0	CELL.LV[19]
1	1	CELL.LV[7]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[7]
Bits		Destination
MAIN[17][79]	MAIN[17][78]	CELL.HEX_N5[7]
		Source
0	0	FAR.HEX_N4[7]
0	1	CELL.HEX_S4[7]
1	0	CELL.LV[13]
1	1	CELL.LV[1]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[8]
Bits		Destination
MAIN[10][79]	MAIN[10][78]	CELL.HEX_N5[8]
		Source
0	0	FAR.HEX_N4[8]
0	1	CELL.HEX_S4[8]
1	0	CELL.LV[19]
1	1	CELL.LV[7]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N5[9]
Bits		Destination
MAIN[0][79]	MAIN[0][78]	CELL.HEX_N5[9]
		Source
0	0	FAR.HEX_N4[9]
0	1	CELL.HEX_S4[9]
1	0	CELL.LV[13]
1	1	CELL.LV[1]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[0]
Bits		Destination
MAIN[8][79]	MAIN[8][78]	CELL.HEX_N6[0]
		Source
0	0	FAR.HEX_N5[0]
0	1	CELL.HEX_S5[0]
1	0	CELL.LV[18]
1	1	CELL.LV[6]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[1]
Bits		Destination
MAIN[20][79]	MAIN[20][78]	CELL.HEX_N6[1]
		Source
0	0	FAR.HEX_N5[1]
0	1	CELL.HEX_S5[1]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[2]
Bits		Destination
MAIN[15][79]	MAIN[15][78]	CELL.HEX_N6[2]
		Source
0	0	FAR.HEX_N5[2]
0	1	CELL.HEX_S5[2]
1	0	CELL.LV[18]
1	1	CELL.LV[6]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[3]
Bits		Destination
MAIN[7][79]	MAIN[7][78]	CELL.HEX_N6[3]
		Source
0	0	FAR.HEX_N5[3]
0	1	CELL.HEX_S5[3]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[4]
Bits		Destination
MAIN[19][79]	MAIN[19][78]	CELL.HEX_N6[4]
		Source
0	0	FAR.HEX_N5[4]
0	1	CELL.HEX_S5[4]
1	0	CELL.LV[18]
1	1	CELL.LV[6]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[5]
Bits		Destination
MAIN[12][79]	MAIN[12][78]	CELL.HEX_N6[5]
		Source
0	0	FAR.HEX_N5[5]
0	1	CELL.HEX_S5[5]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[6]
Bits		Destination
MAIN[4][79]	MAIN[4][78]	CELL.HEX_N6[6]
		Source
0	0	FAR.HEX_N5[6]
0	1	CELL.HEX_S5[6]
1	0	CELL.LV[18]
1	1	CELL.LV[6]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[7]
Bits		Destination
MAIN[16][79]	MAIN[16][78]	CELL.HEX_N6[7]
		Source
0	0	FAR.HEX_N5[7]
0	1	CELL.HEX_S5[7]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[8]
Bits		Destination
MAIN[11][79]	MAIN[11][78]	CELL.HEX_N6[8]
		Source
0	0	FAR.HEX_N5[8]
0	1	CELL.HEX_S5[8]
1	0	CELL.LV[18]
1	1	CELL.LV[6]

virtex2 PPC_TERM_S switchbox PPC_TERM_S muxes HEX_N6[9]
Bits		Destination
MAIN[3][79]	MAIN[3][78]	CELL.HEX_N6[9]
		Source
0	0	FAR.HEX_N5[9]
0	1	CELL.HEX_S5[9]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

Bitstream

virtex2 PPC_TERM_S rect MAIN
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B79	PPC_TERM_S: mux CELL.HEX_N5[1] bit 1	PPC_TERM_S: mux CELL.HEX_N6[1] bit 1	PPC_TERM_S: mux CELL.HEX_N6[4] bit 1	PPC_TERM_S: mux CELL.HEX_N5[4] bit 1	PPC_TERM_S: mux CELL.HEX_N5[7] bit 1	PPC_TERM_S: mux CELL.HEX_N6[7] bit 1	PPC_TERM_S: mux CELL.HEX_N6[2] bit 1	PPC_TERM_S: mux CELL.HEX_N5[2] bit 1	PPC_TERM_S: mux CELL.HEX_N5[5] bit 1	PPC_TERM_S: mux CELL.HEX_N6[5] bit 1	PPC_TERM_S: mux CELL.HEX_N6[8] bit 1	PPC_TERM_S: mux CELL.HEX_N5[8] bit 1	PPC_TERM_S: mux CELL.HEX_N5[0] bit 1	PPC_TERM_S: mux CELL.HEX_N6[0] bit 1	PPC_TERM_S: mux CELL.HEX_N6[3] bit 1	PPC_TERM_S: mux CELL.HEX_N5[3] bit 1	PPC_TERM_S: mux CELL.HEX_N5[6] bit 1	PPC_TERM_S: mux CELL.HEX_N6[6] bit 1	PPC_TERM_S: mux CELL.HEX_N6[9] bit 1	-	-	PPC_TERM_S: mux CELL.HEX_N5[9] bit 1
B78	PPC_TERM_S: mux CELL.HEX_N5[1] bit 0	PPC_TERM_S: mux CELL.HEX_N6[1] bit 0	PPC_TERM_S: mux CELL.HEX_N6[4] bit 0	PPC_TERM_S: mux CELL.HEX_N5[4] bit 0	PPC_TERM_S: mux CELL.HEX_N5[7] bit 0	PPC_TERM_S: mux CELL.HEX_N6[7] bit 0	PPC_TERM_S: mux CELL.HEX_N6[2] bit 0	PPC_TERM_S: mux CELL.HEX_N5[2] bit 0	PPC_TERM_S: mux CELL.HEX_N5[5] bit 0	PPC_TERM_S: mux CELL.HEX_N6[5] bit 0	PPC_TERM_S: mux CELL.HEX_N6[8] bit 0	PPC_TERM_S: mux CELL.HEX_N5[8] bit 0	PPC_TERM_S: mux CELL.HEX_N5[0] bit 0	PPC_TERM_S: mux CELL.HEX_N6[0] bit 0	PPC_TERM_S: mux CELL.HEX_N6[3] bit 0	PPC_TERM_S: mux CELL.HEX_N5[3] bit 0	PPC_TERM_S: mux CELL.HEX_N5[6] bit 0	PPC_TERM_S: mux CELL.HEX_N6[6] bit 0	PPC_TERM_S: mux CELL.HEX_N6[9] bit 0	-	-	PPC_TERM_S: mux CELL.HEX_N5[9] bit 0
B77	PPC_TERM_S: mux CELL.HEX_N3[1] bit 1	PPC_TERM_S: mux CELL.HEX_N4[1] bit 1	PPC_TERM_S: mux CELL.HEX_N4[4] bit 1	PPC_TERM_S: mux CELL.HEX_N3[4] bit 1	PPC_TERM_S: mux CELL.HEX_N3[7] bit 1	PPC_TERM_S: mux CELL.HEX_N4[7] bit 1	PPC_TERM_S: mux CELL.HEX_N4[2] bit 1	PPC_TERM_S: mux CELL.HEX_N3[2] bit 1	PPC_TERM_S: mux CELL.HEX_N3[5] bit 1	PPC_TERM_S: mux CELL.HEX_N4[5] bit 1	PPC_TERM_S: mux CELL.HEX_N4[8] bit 1	PPC_TERM_S: mux CELL.HEX_N3[8] bit 1	PPC_TERM_S: mux CELL.HEX_N3[0] bit 1	PPC_TERM_S: mux CELL.HEX_N4[0] bit 1	PPC_TERM_S: mux CELL.HEX_N4[3] bit 1	PPC_TERM_S: mux CELL.HEX_N3[3] bit 1	PPC_TERM_S: mux CELL.HEX_N3[6] bit 1	PPC_TERM_S: mux CELL.HEX_N4[6] bit 1	PPC_TERM_S: mux CELL.HEX_N4[9] bit 1	-	-	PPC_TERM_S: mux CELL.HEX_N3[9] bit 1
B76	PPC_TERM_S: mux CELL.HEX_N3[1] bit 0	PPC_TERM_S: mux CELL.HEX_N4[1] bit 0	PPC_TERM_S: mux CELL.HEX_N4[4] bit 0	PPC_TERM_S: mux CELL.HEX_N3[4] bit 0	PPC_TERM_S: mux CELL.HEX_N3[7] bit 0	PPC_TERM_S: mux CELL.HEX_N4[7] bit 0	PPC_TERM_S: mux CELL.HEX_N4[2] bit 0	PPC_TERM_S: mux CELL.HEX_N3[2] bit 0	PPC_TERM_S: mux CELL.HEX_N3[5] bit 0	PPC_TERM_S: mux CELL.HEX_N4[5] bit 0	PPC_TERM_S: mux CELL.HEX_N4[8] bit 0	PPC_TERM_S: mux CELL.HEX_N3[8] bit 0	PPC_TERM_S: mux CELL.HEX_N3[0] bit 0	PPC_TERM_S: mux CELL.HEX_N4[0] bit 0	PPC_TERM_S: mux CELL.HEX_N4[3] bit 0	PPC_TERM_S: mux CELL.HEX_N3[3] bit 0	PPC_TERM_S: mux CELL.HEX_N3[6] bit 0	PPC_TERM_S: mux CELL.HEX_N4[6] bit 0	PPC_TERM_S: mux CELL.HEX_N4[9] bit 0	-	-	PPC_TERM_S: mux CELL.HEX_N3[9] bit 0
B75	PPC_TERM_S: mux CELL.HEX_N1[1] bit 1	PPC_TERM_S: mux CELL.HEX_N2[1] bit 1	PPC_TERM_S: mux CELL.HEX_N2[4] bit 1	PPC_TERM_S: mux CELL.HEX_N1[4] bit 1	PPC_TERM_S: mux CELL.HEX_N1[7] bit 1	PPC_TERM_S: mux CELL.HEX_N2[7] bit 1	PPC_TERM_S: mux CELL.HEX_N2[2] bit 1	PPC_TERM_S: mux CELL.HEX_N1[2] bit 1	PPC_TERM_S: mux CELL.HEX_N1[5] bit 1	PPC_TERM_S: mux CELL.HEX_N2[5] bit 1	PPC_TERM_S: mux CELL.HEX_N2[8] bit 1	PPC_TERM_S: mux CELL.HEX_N1[8] bit 1	PPC_TERM_S: mux CELL.HEX_N1[0] bit 1	PPC_TERM_S: mux CELL.HEX_N2[0] bit 1	PPC_TERM_S: mux CELL.HEX_N2[3] bit 1	PPC_TERM_S: mux CELL.HEX_N1[3] bit 1	PPC_TERM_S: mux CELL.HEX_N1[6] bit 1	PPC_TERM_S: mux CELL.HEX_N2[6] bit 1	PPC_TERM_S: mux CELL.HEX_N2[9] bit 1	-	-	PPC_TERM_S: mux CELL.HEX_N1[9] bit 1
B74	PPC_TERM_S: mux CELL.HEX_N1[1] bit 0	PPC_TERM_S: mux CELL.HEX_N2[1] bit 0	PPC_TERM_S: mux CELL.HEX_N2[4] bit 0	PPC_TERM_S: mux CELL.HEX_N1[4] bit 0	PPC_TERM_S: mux CELL.HEX_N1[7] bit 0	PPC_TERM_S: mux CELL.HEX_N2[7] bit 0	PPC_TERM_S: mux CELL.HEX_N2[2] bit 0	PPC_TERM_S: mux CELL.HEX_N1[2] bit 0	PPC_TERM_S: mux CELL.HEX_N1[5] bit 0	PPC_TERM_S: mux CELL.HEX_N2[5] bit 0	PPC_TERM_S: mux CELL.HEX_N2[8] bit 0	PPC_TERM_S: mux CELL.HEX_N1[8] bit 0	PPC_TERM_S: mux CELL.HEX_N1[0] bit 0	PPC_TERM_S: mux CELL.HEX_N2[0] bit 0	PPC_TERM_S: mux CELL.HEX_N2[3] bit 0	PPC_TERM_S: mux CELL.HEX_N1[3] bit 0	PPC_TERM_S: mux CELL.HEX_N1[6] bit 0	PPC_TERM_S: mux CELL.HEX_N2[6] bit 0	PPC_TERM_S: mux CELL.HEX_N2[9] bit 0	-	-	PPC_TERM_S: mux CELL.HEX_N1[9] bit 0
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

`PPC_TERM_N`

This tile is located on the bottom of every interconnect column interrupted by the PowerPC hole. It uses the bitstream tile corresponding to the interconnect tile above the bottommost INT.PPC tile of the column (which is otherwise empty, as it doesn’t contain an INT.* tile).

The interconnect signals prefixed with 0 refer to signals in the bottommost INT.PPC tile of the row. The interconnect signals prefixed with 1 refer to signals in the topmost INT.PPC tile of the row.

Tile PPC_TERM_N

Cells: 2

Switchbox PPC_TERM_N

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[0]
Bits		Destination
MAIN[9][4]	MAIN[9][5]	CELL.HEX_S1[0]
		Source
0	0	FAR.HEX_S0[0]
0	1	CELL.HEX_N0[0]
1	0	CELL.LV[1]
1	1	CELL.LV[13]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[1]
Bits		Destination
MAIN[21][4]	MAIN[21][5]	CELL.HEX_S1[1]
		Source
0	0	FAR.HEX_S0[1]
0	1	CELL.HEX_N0[1]
1	0	CELL.LV[7]
1	1	CELL.LV[19]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[2]
Bits		Destination
MAIN[14][4]	MAIN[14][5]	CELL.HEX_S1[2]
		Source
0	0	FAR.HEX_S0[2]
0	1	CELL.HEX_N0[2]
1	0	CELL.LV[1]
1	1	CELL.LV[13]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[3]
Bits		Destination
MAIN[6][4]	MAIN[6][5]	CELL.HEX_S1[3]
		Source
0	0	FAR.HEX_S0[3]
0	1	CELL.HEX_N0[3]
1	0	CELL.LV[7]
1	1	CELL.LV[19]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[4]
Bits		Destination
MAIN[18][4]	MAIN[18][5]	CELL.HEX_S1[4]
		Source
0	0	FAR.HEX_S0[4]
0	1	CELL.HEX_N0[4]
1	0	CELL.LV[1]
1	1	CELL.LV[13]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[5]
Bits		Destination
MAIN[13][4]	MAIN[13][5]	CELL.HEX_S1[5]
		Source
0	0	FAR.HEX_S0[5]
0	1	CELL.HEX_N0[5]
1	0	CELL.LV[7]
1	1	CELL.LV[19]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[6]
Bits		Destination
MAIN[5][4]	MAIN[5][5]	CELL.HEX_S1[6]
		Source
0	0	FAR.HEX_S0[6]
0	1	CELL.HEX_N0[6]
1	0	CELL.LV[1]
1	1	CELL.LV[13]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[7]
Bits		Destination
MAIN[17][4]	MAIN[17][5]	CELL.HEX_S1[7]
		Source
0	0	FAR.HEX_S0[7]
0	1	CELL.HEX_N0[7]
1	0	CELL.LV[7]
1	1	CELL.LV[19]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[8]
Bits		Destination
MAIN[10][4]	MAIN[10][5]	CELL.HEX_S1[8]
		Source
0	0	FAR.HEX_S0[8]
0	1	CELL.HEX_N0[8]
1	0	CELL.LV[1]
1	1	CELL.LV[13]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S1[9]
Bits		Destination
MAIN[0][4]	MAIN[0][5]	CELL.HEX_S1[9]
		Source
0	0	FAR.HEX_S0[9]
0	1	CELL.HEX_N0[9]
1	0	CELL.LV[7]
1	1	CELL.LV[19]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[0]
Bits		Destination
MAIN[8][4]	MAIN[8][5]	CELL.HEX_S2[0]
		Source
0	0	FAR.HEX_S1[0]
0	1	CELL.HEX_N1[0]
1	0	CELL.LV[2]
1	1	CELL.LV[14]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[1]
Bits		Destination
MAIN[20][4]	MAIN[20][5]	CELL.HEX_S2[1]
		Source
0	0	FAR.HEX_S1[1]
0	1	CELL.HEX_N1[1]
1	0	CELL.LV[8]
1	1	CELL.LV[20]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[2]
Bits		Destination
MAIN[15][4]	MAIN[15][5]	CELL.HEX_S2[2]
		Source
0	0	FAR.HEX_S1[2]
0	1	CELL.HEX_N1[2]
1	0	CELL.LV[2]
1	1	CELL.LV[14]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[3]
Bits		Destination
MAIN[7][4]	MAIN[7][5]	CELL.HEX_S2[3]
		Source
0	0	FAR.HEX_S1[3]
0	1	CELL.HEX_N1[3]
1	0	CELL.LV[8]
1	1	CELL.LV[20]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[4]
Bits		Destination
MAIN[19][4]	MAIN[19][5]	CELL.HEX_S2[4]
		Source
0	0	FAR.HEX_S1[4]
0	1	CELL.HEX_N1[4]
1	0	CELL.LV[2]
1	1	CELL.LV[14]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[5]
Bits		Destination
MAIN[12][4]	MAIN[12][5]	CELL.HEX_S2[5]
		Source
0	0	FAR.HEX_S1[5]
0	1	CELL.HEX_N1[5]
1	0	CELL.LV[8]
1	1	CELL.LV[20]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[6]
Bits		Destination
MAIN[4][4]	MAIN[4][5]	CELL.HEX_S2[6]
		Source
0	0	FAR.HEX_S1[6]
0	1	CELL.HEX_N1[6]
1	0	CELL.LV[2]
1	1	CELL.LV[14]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[7]
Bits		Destination
MAIN[16][4]	MAIN[16][5]	CELL.HEX_S2[7]
		Source
0	0	FAR.HEX_S1[7]
0	1	CELL.HEX_N1[7]
1	0	CELL.LV[8]
1	1	CELL.LV[20]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[8]
Bits		Destination
MAIN[11][4]	MAIN[11][5]	CELL.HEX_S2[8]
		Source
0	0	FAR.HEX_S1[8]
0	1	CELL.HEX_N1[8]
1	0	CELL.LV[2]
1	1	CELL.LV[14]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S2[9]
Bits		Destination
MAIN[3][4]	MAIN[3][5]	CELL.HEX_S2[9]
		Source
0	0	FAR.HEX_S1[9]
0	1	CELL.HEX_N1[9]
1	0	CELL.LV[8]
1	1	CELL.LV[20]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[0]
Bits		Destination
MAIN[9][2]	MAIN[9][3]	CELL.HEX_S3[0]
		Source
0	0	FAR.HEX_S2[0]
0	1	CELL.HEX_N2[0]
1	0	CELL.LV[3]
1	1	CELL.LV[15]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[1]
Bits		Destination
MAIN[21][2]	MAIN[21][3]	CELL.HEX_S3[1]
		Source
0	0	FAR.HEX_S2[1]
0	1	CELL.HEX_N2[1]
1	0	CELL.LV[9]
1	1	CELL.LV[21]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[2]
Bits		Destination
MAIN[14][2]	MAIN[14][3]	CELL.HEX_S3[2]
		Source
0	0	FAR.HEX_S2[2]
0	1	CELL.HEX_N2[2]
1	0	CELL.LV[3]
1	1	CELL.LV[15]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[3]
Bits		Destination
MAIN[6][2]	MAIN[6][3]	CELL.HEX_S3[3]
		Source
0	0	FAR.HEX_S2[3]
0	1	CELL.HEX_N2[3]
1	0	CELL.LV[9]
1	1	CELL.LV[21]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[4]
Bits		Destination
MAIN[18][2]	MAIN[18][3]	CELL.HEX_S3[4]
		Source
0	0	FAR.HEX_S2[4]
0	1	CELL.HEX_N2[4]
1	0	CELL.LV[3]
1	1	CELL.LV[15]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[5]
Bits		Destination
MAIN[13][2]	MAIN[13][3]	CELL.HEX_S3[5]
		Source
0	0	FAR.HEX_S2[5]
0	1	CELL.HEX_N2[5]
1	0	CELL.LV[9]
1	1	CELL.LV[21]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[6]
Bits		Destination
MAIN[5][2]	MAIN[5][3]	CELL.HEX_S3[6]
		Source
0	0	FAR.HEX_S2[6]
0	1	CELL.HEX_N2[6]
1	0	CELL.LV[3]
1	1	CELL.LV[15]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[7]
Bits		Destination
MAIN[17][2]	MAIN[17][3]	CELL.HEX_S3[7]
		Source
0	0	FAR.HEX_S2[7]
0	1	CELL.HEX_N2[7]
1	0	CELL.LV[9]
1	1	CELL.LV[21]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[8]
Bits		Destination
MAIN[10][2]	MAIN[10][3]	CELL.HEX_S3[8]
		Source
0	0	FAR.HEX_S2[8]
0	1	CELL.HEX_N2[8]
1	0	CELL.LV[3]
1	1	CELL.LV[15]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S3[9]
Bits		Destination
MAIN[0][2]	MAIN[0][3]	CELL.HEX_S3[9]
		Source
0	0	FAR.HEX_S2[9]
0	1	CELL.HEX_N2[9]
1	0	CELL.LV[9]
1	1	CELL.LV[21]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[0]
Bits		Destination
MAIN[8][2]	MAIN[8][3]	CELL.HEX_S4[0]
		Source
0	0	FAR.HEX_S3[0]
0	1	CELL.HEX_N3[0]
1	0	CELL.LV[4]
1	1	CELL.LV[16]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[1]
Bits		Destination
MAIN[20][2]	MAIN[20][3]	CELL.HEX_S4[1]
		Source
0	0	FAR.HEX_S3[1]
0	1	CELL.HEX_N3[1]
1	0	CELL.LV[10]
1	1	CELL.LV[22]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[2]
Bits		Destination
MAIN[15][2]	MAIN[15][3]	CELL.HEX_S4[2]
		Source
0	0	FAR.HEX_S3[2]
0	1	CELL.HEX_N3[2]
1	0	CELL.LV[4]
1	1	CELL.LV[16]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[3]
Bits		Destination
MAIN[7][2]	MAIN[7][3]	CELL.HEX_S4[3]
		Source
0	0	FAR.HEX_S3[3]
0	1	CELL.HEX_N3[3]
1	0	CELL.LV[10]
1	1	CELL.LV[22]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[4]
Bits		Destination
MAIN[19][2]	MAIN[19][3]	CELL.HEX_S4[4]
		Source
0	0	FAR.HEX_S3[4]
0	1	CELL.HEX_N3[4]
1	0	CELL.LV[4]
1	1	CELL.LV[16]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[5]
Bits		Destination
MAIN[12][2]	MAIN[12][3]	CELL.HEX_S4[5]
		Source
0	0	FAR.HEX_S3[5]
0	1	CELL.HEX_N3[5]
1	0	CELL.LV[10]
1	1	CELL.LV[22]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[6]
Bits		Destination
MAIN[4][2]	MAIN[4][3]	CELL.HEX_S4[6]
		Source
0	0	FAR.HEX_S3[6]
0	1	CELL.HEX_N3[6]
1	0	CELL.LV[4]
1	1	CELL.LV[16]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[7]
Bits		Destination
MAIN[16][2]	MAIN[16][3]	CELL.HEX_S4[7]
		Source
0	0	FAR.HEX_S3[7]
0	1	CELL.HEX_N3[7]
1	0	CELL.LV[10]
1	1	CELL.LV[22]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[8]
Bits		Destination
MAIN[11][2]	MAIN[11][3]	CELL.HEX_S4[8]
		Source
0	0	FAR.HEX_S3[8]
0	1	CELL.HEX_N3[8]
1	0	CELL.LV[4]
1	1	CELL.LV[16]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S4[9]
Bits		Destination
MAIN[3][2]	MAIN[3][3]	CELL.HEX_S4[9]
		Source
0	0	FAR.HEX_S3[9]
0	1	CELL.HEX_N3[9]
1	0	CELL.LV[10]
1	1	CELL.LV[22]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[0]
Bits		Destination
MAIN[9][0]	MAIN[9][1]	CELL.HEX_S5[0]
		Source
0	0	FAR.HEX_S4[0]
0	1	CELL.HEX_N4[0]
1	0	CELL.LV[5]
1	1	CELL.LV[17]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[1]
Bits		Destination
MAIN[21][0]	MAIN[21][1]	CELL.HEX_S5[1]
		Source
0	0	FAR.HEX_S4[1]
0	1	CELL.HEX_N4[1]
1	0	CELL.LV[11]
1	1	CELL.LV[23]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[2]
Bits		Destination
MAIN[14][0]	MAIN[14][1]	CELL.HEX_S5[2]
		Source
0	0	FAR.HEX_S4[2]
0	1	CELL.HEX_N4[2]
1	0	CELL.LV[5]
1	1	CELL.LV[17]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[3]
Bits		Destination
MAIN[6][0]	MAIN[6][1]	CELL.HEX_S5[3]
		Source
0	0	FAR.HEX_S4[3]
0	1	CELL.HEX_N4[3]
1	0	CELL.LV[11]
1	1	CELL.LV[23]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[4]
Bits		Destination
MAIN[18][0]	MAIN[18][1]	CELL.HEX_S5[4]
		Source
0	0	FAR.HEX_S4[4]
0	1	CELL.HEX_N4[4]
1	0	CELL.LV[5]
1	1	CELL.LV[17]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[5]
Bits		Destination
MAIN[13][0]	MAIN[13][1]	CELL.HEX_S5[5]
		Source
0	0	FAR.HEX_S4[5]
0	1	CELL.HEX_N4[5]
1	0	CELL.LV[11]
1	1	CELL.LV[23]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[6]
Bits		Destination
MAIN[5][0]	MAIN[5][1]	CELL.HEX_S5[6]
		Source
0	0	FAR.HEX_S4[6]
0	1	CELL.HEX_N4[6]
1	0	CELL.LV[5]
1	1	CELL.LV[17]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[7]
Bits		Destination
MAIN[17][0]	MAIN[17][1]	CELL.HEX_S5[7]
		Source
0	0	FAR.HEX_S4[7]
0	1	CELL.HEX_N4[7]
1	0	CELL.LV[11]
1	1	CELL.LV[23]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[8]
Bits		Destination
MAIN[10][0]	MAIN[10][1]	CELL.HEX_S5[8]
		Source
0	0	FAR.HEX_S4[8]
0	1	CELL.HEX_N4[8]
1	0	CELL.LV[5]
1	1	CELL.LV[17]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S5[9]
Bits		Destination
MAIN[0][0]	MAIN[0][1]	CELL.HEX_S5[9]
		Source
0	0	FAR.HEX_S4[9]
0	1	CELL.HEX_N4[9]
1	0	CELL.LV[11]
1	1	CELL.LV[23]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[0]
Bits		Destination
MAIN[8][0]	MAIN[8][1]	CELL.HEX_S6[0]
		Source
0	0	FAR.HEX_S5[0]
0	1	CELL.HEX_N5[0]
1	0	CELL.LV[6]
1	1	CELL.LV[18]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[1]
Bits		Destination
MAIN[20][0]	MAIN[20][1]	CELL.HEX_S6[1]
		Source
0	0	FAR.HEX_S5[1]
0	1	CELL.HEX_N5[1]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[2]
Bits		Destination
MAIN[15][0]	MAIN[15][1]	CELL.HEX_S6[2]
		Source
0	0	FAR.HEX_S5[2]
0	1	CELL.HEX_N5[2]
1	0	CELL.LV[6]
1	1	CELL.LV[18]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[3]
Bits		Destination
MAIN[7][0]	MAIN[7][1]	CELL.HEX_S6[3]
		Source
0	0	FAR.HEX_S5[3]
0	1	CELL.HEX_N5[3]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[4]
Bits		Destination
MAIN[19][0]	MAIN[19][1]	CELL.HEX_S6[4]
		Source
0	0	FAR.HEX_S5[4]
0	1	CELL.HEX_N5[4]
1	0	CELL.LV[6]
1	1	CELL.LV[18]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[5]
Bits		Destination
MAIN[12][0]	MAIN[12][1]	CELL.HEX_S6[5]
		Source
0	0	FAR.HEX_S5[5]
0	1	CELL.HEX_N5[5]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[6]
Bits		Destination
MAIN[4][0]	MAIN[4][1]	CELL.HEX_S6[6]
		Source
0	0	FAR.HEX_S5[6]
0	1	CELL.HEX_N5[6]
1	0	CELL.LV[6]
1	1	CELL.LV[18]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[7]
Bits		Destination
MAIN[16][0]	MAIN[16][1]	CELL.HEX_S6[7]
		Source
0	0	FAR.HEX_S5[7]
0	1	CELL.HEX_N5[7]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[8]
Bits		Destination
MAIN[11][0]	MAIN[11][1]	CELL.HEX_S6[8]
		Source
0	0	FAR.HEX_S5[8]
0	1	CELL.HEX_N5[8]
1	0	CELL.LV[6]
1	1	CELL.LV[18]

virtex2 PPC_TERM_N switchbox PPC_TERM_N muxes HEX_S6[9]
Bits		Destination
MAIN[3][0]	MAIN[3][1]	CELL.HEX_S6[9]
		Source
0	0	FAR.HEX_S5[9]
0	1	CELL.HEX_N5[9]
1	0	CELL.LV[12]
1	1	CELL.LV[0]

Bitstream

virtex2 PPC_TERM_N rect MAIN
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	PPC_TERM_N: mux CELL.HEX_S1[1] bit 0	PPC_TERM_N: mux CELL.HEX_S2[1] bit 0	PPC_TERM_N: mux CELL.HEX_S2[4] bit 0	PPC_TERM_N: mux CELL.HEX_S1[4] bit 0	PPC_TERM_N: mux CELL.HEX_S1[7] bit 0	PPC_TERM_N: mux CELL.HEX_S2[7] bit 0	PPC_TERM_N: mux CELL.HEX_S2[2] bit 0	PPC_TERM_N: mux CELL.HEX_S1[2] bit 0	PPC_TERM_N: mux CELL.HEX_S1[5] bit 0	PPC_TERM_N: mux CELL.HEX_S2[5] bit 0	PPC_TERM_N: mux CELL.HEX_S2[8] bit 0	PPC_TERM_N: mux CELL.HEX_S1[8] bit 0	PPC_TERM_N: mux CELL.HEX_S1[0] bit 0	PPC_TERM_N: mux CELL.HEX_S2[0] bit 0	PPC_TERM_N: mux CELL.HEX_S2[3] bit 0	PPC_TERM_N: mux CELL.HEX_S1[3] bit 0	PPC_TERM_N: mux CELL.HEX_S1[6] bit 0	PPC_TERM_N: mux CELL.HEX_S2[6] bit 0	PPC_TERM_N: mux CELL.HEX_S2[9] bit 0	-	-	PPC_TERM_N: mux CELL.HEX_S1[9] bit 0
B4	PPC_TERM_N: mux CELL.HEX_S1[1] bit 1	PPC_TERM_N: mux CELL.HEX_S2[1] bit 1	PPC_TERM_N: mux CELL.HEX_S2[4] bit 1	PPC_TERM_N: mux CELL.HEX_S1[4] bit 1	PPC_TERM_N: mux CELL.HEX_S1[7] bit 1	PPC_TERM_N: mux CELL.HEX_S2[7] bit 1	PPC_TERM_N: mux CELL.HEX_S2[2] bit 1	PPC_TERM_N: mux CELL.HEX_S1[2] bit 1	PPC_TERM_N: mux CELL.HEX_S1[5] bit 1	PPC_TERM_N: mux CELL.HEX_S2[5] bit 1	PPC_TERM_N: mux CELL.HEX_S2[8] bit 1	PPC_TERM_N: mux CELL.HEX_S1[8] bit 1	PPC_TERM_N: mux CELL.HEX_S1[0] bit 1	PPC_TERM_N: mux CELL.HEX_S2[0] bit 1	PPC_TERM_N: mux CELL.HEX_S2[3] bit 1	PPC_TERM_N: mux CELL.HEX_S1[3] bit 1	PPC_TERM_N: mux CELL.HEX_S1[6] bit 1	PPC_TERM_N: mux CELL.HEX_S2[6] bit 1	PPC_TERM_N: mux CELL.HEX_S2[9] bit 1	-	-	PPC_TERM_N: mux CELL.HEX_S1[9] bit 1
B3	PPC_TERM_N: mux CELL.HEX_S3[1] bit 0	PPC_TERM_N: mux CELL.HEX_S4[1] bit 0	PPC_TERM_N: mux CELL.HEX_S4[4] bit 0	PPC_TERM_N: mux CELL.HEX_S3[4] bit 0	PPC_TERM_N: mux CELL.HEX_S3[7] bit 0	PPC_TERM_N: mux CELL.HEX_S4[7] bit 0	PPC_TERM_N: mux CELL.HEX_S4[2] bit 0	PPC_TERM_N: mux CELL.HEX_S3[2] bit 0	PPC_TERM_N: mux CELL.HEX_S3[5] bit 0	PPC_TERM_N: mux CELL.HEX_S4[5] bit 0	PPC_TERM_N: mux CELL.HEX_S4[8] bit 0	PPC_TERM_N: mux CELL.HEX_S3[8] bit 0	PPC_TERM_N: mux CELL.HEX_S3[0] bit 0	PPC_TERM_N: mux CELL.HEX_S4[0] bit 0	PPC_TERM_N: mux CELL.HEX_S4[3] bit 0	PPC_TERM_N: mux CELL.HEX_S3[3] bit 0	PPC_TERM_N: mux CELL.HEX_S3[6] bit 0	PPC_TERM_N: mux CELL.HEX_S4[6] bit 0	PPC_TERM_N: mux CELL.HEX_S4[9] bit 0	-	-	PPC_TERM_N: mux CELL.HEX_S3[9] bit 0
B2	PPC_TERM_N: mux CELL.HEX_S3[1] bit 1	PPC_TERM_N: mux CELL.HEX_S4[1] bit 1	PPC_TERM_N: mux CELL.HEX_S4[4] bit 1	PPC_TERM_N: mux CELL.HEX_S3[4] bit 1	PPC_TERM_N: mux CELL.HEX_S3[7] bit 1	PPC_TERM_N: mux CELL.HEX_S4[7] bit 1	PPC_TERM_N: mux CELL.HEX_S4[2] bit 1	PPC_TERM_N: mux CELL.HEX_S3[2] bit 1	PPC_TERM_N: mux CELL.HEX_S3[5] bit 1	PPC_TERM_N: mux CELL.HEX_S4[5] bit 1	PPC_TERM_N: mux CELL.HEX_S4[8] bit 1	PPC_TERM_N: mux CELL.HEX_S3[8] bit 1	PPC_TERM_N: mux CELL.HEX_S3[0] bit 1	PPC_TERM_N: mux CELL.HEX_S4[0] bit 1	PPC_TERM_N: mux CELL.HEX_S4[3] bit 1	PPC_TERM_N: mux CELL.HEX_S3[3] bit 1	PPC_TERM_N: mux CELL.HEX_S3[6] bit 1	PPC_TERM_N: mux CELL.HEX_S4[6] bit 1	PPC_TERM_N: mux CELL.HEX_S4[9] bit 1	-	-	PPC_TERM_N: mux CELL.HEX_S3[9] bit 1
B1	PPC_TERM_N: mux CELL.HEX_S5[1] bit 0	PPC_TERM_N: mux CELL.HEX_S6[1] bit 0	PPC_TERM_N: mux CELL.HEX_S6[4] bit 0	PPC_TERM_N: mux CELL.HEX_S5[4] bit 0	PPC_TERM_N: mux CELL.HEX_S5[7] bit 0	PPC_TERM_N: mux CELL.HEX_S6[7] bit 0	PPC_TERM_N: mux CELL.HEX_S6[2] bit 0	PPC_TERM_N: mux CELL.HEX_S5[2] bit 0	PPC_TERM_N: mux CELL.HEX_S5[5] bit 0	PPC_TERM_N: mux CELL.HEX_S6[5] bit 0	PPC_TERM_N: mux CELL.HEX_S6[8] bit 0	PPC_TERM_N: mux CELL.HEX_S5[8] bit 0	PPC_TERM_N: mux CELL.HEX_S5[0] bit 0	PPC_TERM_N: mux CELL.HEX_S6[0] bit 0	PPC_TERM_N: mux CELL.HEX_S6[3] bit 0	PPC_TERM_N: mux CELL.HEX_S5[3] bit 0	PPC_TERM_N: mux CELL.HEX_S5[6] bit 0	PPC_TERM_N: mux CELL.HEX_S6[6] bit 0	PPC_TERM_N: mux CELL.HEX_S6[9] bit 0	-	-	PPC_TERM_N: mux CELL.HEX_S5[9] bit 0
B0	PPC_TERM_N: mux CELL.HEX_S5[1] bit 1	PPC_TERM_N: mux CELL.HEX_S6[1] bit 1	PPC_TERM_N: mux CELL.HEX_S6[4] bit 1	PPC_TERM_N: mux CELL.HEX_S5[4] bit 1	PPC_TERM_N: mux CELL.HEX_S5[7] bit 1	PPC_TERM_N: mux CELL.HEX_S6[7] bit 1	PPC_TERM_N: mux CELL.HEX_S6[2] bit 1	PPC_TERM_N: mux CELL.HEX_S5[2] bit 1	PPC_TERM_N: mux CELL.HEX_S5[5] bit 1	PPC_TERM_N: mux CELL.HEX_S6[5] bit 1	PPC_TERM_N: mux CELL.HEX_S6[8] bit 1	PPC_TERM_N: mux CELL.HEX_S5[8] bit 1	PPC_TERM_N: mux CELL.HEX_S5[0] bit 1	PPC_TERM_N: mux CELL.HEX_S6[0] bit 1	PPC_TERM_N: mux CELL.HEX_S6[3] bit 1	PPC_TERM_N: mux CELL.HEX_S5[3] bit 1	PPC_TERM_N: mux CELL.HEX_S5[6] bit 1	PPC_TERM_N: mux CELL.HEX_S6[6] bit 1	PPC_TERM_N: mux CELL.HEX_S6[9] bit 1	-	-	PPC_TERM_N: mux CELL.HEX_S5[9] bit 1

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