These tiles are placed at the edges of the device and deal with interconnect lines that go out-of-bounds. The associated bitstream tiles are shared with IOBS tiles and primitive data for corner tiles.
Located at the left edge of every interconnect row, this tile is 4×80 bits.
Cells: 1
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[0]
Bits Destination
HEX_E1[0] Source LH[19]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[1]
Bits Destination
HEX_E1[1] Source OUT_PCI[0]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[2]
Bits Destination
HEX_E1[2] Source LH[19]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[3]
Bits Destination
HEX_E1[3] Source LH[13]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[4]
Bits Destination
HEX_E1[4] Source LH[19]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[5]
Bits Destination
HEX_E1[5] Source LH[13]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[6]
Bits Destination
HEX_E1[6] Source LH[19]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[7]
Bits Destination
HEX_E1[7] Source LH[13]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[8]
Bits Destination
HEX_E1[8] Source LH[19]
virtex2 TERM_W switchbox TERM_W muxes HEX_E1[9]
Bits Destination
HEX_E1[9] Source LH[13]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[0]
Bits Destination
HEX_E2[0] Source LH[20]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[1]
Bits Destination
HEX_E2[1] Source OUT_PCI[1]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[2]
Bits Destination
HEX_E2[2] Source LH[20]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[3]
Bits Destination
HEX_E2[3] Source LH[14]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[4]
Bits Destination
HEX_E2[4] Source LH[20]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[5]
Bits Destination
HEX_E2[5] Source LH[14]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[6]
Bits Destination
HEX_E2[6] Source LH[20]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[7]
Bits Destination
HEX_E2[7] Source LH[14]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[8]
Bits Destination
HEX_E2[8] Source LH[20]
virtex2 TERM_W switchbox TERM_W muxes HEX_E2[9]
Bits Destination
HEX_E2[9] Source LH[14]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[0]
Bits Destination
HEX_E3[0] Source LH[21]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[1]
Bits Destination
HEX_E3[1] Source LH[15]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[2]
Bits Destination
HEX_E3[2] Source LH[21]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[3]
Bits Destination
HEX_E3[3] Source LH[15]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[4]
Bits Destination
HEX_E3[4] Source LH[21]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[5]
Bits Destination
HEX_E3[5] Source LH[15]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[6]
Bits Destination
HEX_E3[6] Source LH[21]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[7]
Bits Destination
HEX_E3[7] Source LH[15]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[8]
Bits Destination
HEX_E3[8] Source LH[21]
virtex2 TERM_W switchbox TERM_W muxes HEX_E3[9]
Bits Destination
HEX_E3[9] Source LH[15]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[0]
Bits Destination
HEX_E4[0] Source LH[22]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[1]
Bits Destination
HEX_E4[1] Source LH[16]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[2]
Bits Destination
HEX_E4[2] Source LH[22]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[3]
Bits Destination
HEX_E4[3] Source LH[16]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[4]
Bits Destination
HEX_E4[4] Source LH[22]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[5]
Bits Destination
HEX_E4[5] Source LH[16]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[6]
Bits Destination
HEX_E4[6] Source LH[22]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[7]
Bits Destination
HEX_E4[7] Source LH[16]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[8]
Bits Destination
HEX_E4[8] Source LH[22]
virtex2 TERM_W switchbox TERM_W muxes HEX_E4[9]
Bits Destination
HEX_E4[9] Source LH[16]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[0]
Bits Destination
HEX_E5[0] Source LH[23]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[1]
Bits Destination
HEX_E5[1] Source LH[17]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[2]
Bits Destination
HEX_E5[2] Source LH[23]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[3]
Bits Destination
HEX_E5[3] Source LH[17]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[4]
Bits Destination
HEX_E5[4] Source LH[23]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[5]
Bits Destination
HEX_E5[5] Source LH[17]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[6]
Bits Destination
HEX_E5[6] Source LH[23]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[7]
Bits Destination
HEX_E5[7] Source LH[17]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[8]
Bits Destination
HEX_E5[8] Source LH[23]
virtex2 TERM_W switchbox TERM_W muxes HEX_E5[9]
Bits Destination
HEX_E5[9] Source LH[17]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[0]
Bits Destination
HEX_E6[0] Source LH[12]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[1]
Bits Destination
HEX_E6[1] Source LH[18]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[2]
Bits Destination
HEX_E6[2] Source LH[12]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[3]
Bits Destination
HEX_E6[3] Source LH[18]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[4]
Bits Destination
HEX_E6[4] Source LH[12]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[5]
Bits Destination
HEX_E6[5] Source LH[18]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[6]
Bits Destination
HEX_E6[6] Source LH[12]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[7]
Bits Destination
HEX_E6[7] Source LH[18]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[8]
Bits Destination
HEX_E6[8] Source LH[12]
virtex2 TERM_W switchbox TERM_W muxes HEX_E6[9]
Bits Destination
HEX_E6[9] Source LH[18]
virtex2 TERM_W rect TERM
Bit Frame
F0
F1
F2
F3
B79
-
-
-
-
B78
-
-
-
-
B77
-
-
-
-
B76
-
-
-
-
B75
-
-
-
-
B74
-
-
-
-
B73
-
-
-
-
B72
-
-
-
-
B71
-
-
-
-
B70
-
-
-
-
B69
-
-
-
-
B68
-
-
-
-
B67
-
-
-
-
B66
-
-
-
-
B65
-
-
-
-
B64
-
-
-
-
B63
-
-
-
-
B62
-
-
-
-
B61
-
-
-
-
B60
-
-
-
-
B59
-
-
-
-
B58
-
-
-
-
B57
-
-
-
-
B56
-
-
-
-
B55
-
-
-
-
B54
-
-
-
-
B53
-
-
-
-
B52
-
-
-
-
B51
-
-
-
-
B50
-
-
-
-
B49
-
-
-
-
B48
-
-
-
-
B47
-
-
-
-
B46
-
-
-
-
B45
-
-
-
-
B44
-
-
-
-
B43
-
-
-
-
B42
-
-
-
-
B41
-
-
-
-
B40
-
-
-
-
B39
-
-
-
-
B38
-
-
-
-
B37
-
-
-
-
B36
-
-
-
-
B35
-
-
-
-
B34
-
-
-
-
B33
-
-
-
-
B32
-
-
-
-
B31
-
-
-
-
B30
-
-
-
-
B29
-
-
-
-
B28
-
-
-
-
B27
-
-
-
-
B26
-
-
-
-
B25
-
-
-
-
B24
-
-
-
-
B23
-
-
-
-
B22
-
-
-
-
B21
-
-
-
-
B20
-
-
-
-
B19
-
-
-
-
B18
-
-
-
-
B17
-
-
-
-
B16
-
-
-
-
B15
-
-
-
-
B14
-
-
-
-
B13
-
-
-
-
B12
-
-
-
-
B11
-
-
-
-
B10
-
-
-
-
B9
-
-
-
-
B8
-
-
-
-
B7
-
-
-
-
B6
-
-
-
-
B5
-
-
-
-
B4
-
-
-
-
B3
-
-
-
-
B2
-
-
-
-
B1
-
-
-
-
B0
-
-
-
-
### Bitstream
TERM_W:MUX.HEX_E1[0]
0.F1.B3
0.F1.B2
NONE
0
0
HEX_W0[0]
0
1
LH[7]
1
0
LH[19]
1
1
TERM_W:MUX.HEX_E1[1]
0.F1.B11
0.F1.B10
OUT_PCI[0]
0
0
HEX_W0[1]
0
1
LH[13]
1
0
LH[1]
1
1
TERM_W:MUX.HEX_E1[2]
0.F1.B19
0.F1.B18
NONE
0
0
HEX_W0[2]
0
1
LH[7]
1
0
LH[19]
1
1
TERM_W:MUX.HEX_E1[3]
0.F1.B27
0.F1.B26
NONE
0
0
HEX_W0[3]
0
1
LH[13]
1
0
LH[1]
1
1
TERM_W:MUX.HEX_E1[4]
0.F1.B35
0.F1.B34
NONE
0
0
HEX_W0[4]
0
1
LH[7]
1
0
LH[19]
1
1
TERM_W:MUX.HEX_E1[5]
0.F1.B43
0.F1.B42
NONE
0
0
HEX_W0[5]
0
1
LH[13]
1
0
LH[1]
1
1
TERM_W:MUX.HEX_E1[6]
0.F1.B51
0.F1.B50
NONE
0
0
HEX_W0[6]
0
1
LH[7]
1
0
LH[19]
1
1
TERM_W:MUX.HEX_E1[7]
0.F1.B59
0.F1.B58
NONE
0
0
HEX_W0[7]
0
1
LH[13]
1
0
LH[1]
1
1
TERM_W:MUX.HEX_E1[8]
0.F1.B67
0.F1.B66
NONE
0
0
HEX_W0[8]
0
1
LH[7]
1
0
LH[19]
1
1
TERM_W:MUX.HEX_E1[9]
0.F1.B75
0.F1.B74
NONE
0
0
HEX_W0[9]
0
1
LH[13]
1
0
LH[1]
1
1
TERM_W:MUX.HEX_E2[0]
0.F0.B3
0.F0.B2
NONE
0
0
HEX_W1[0]
0
1
LH[8]
1
0
LH[20]
1
1
TERM_W:MUX.HEX_E2[1]
0.F0.B11
0.F0.B10
OUT_PCI[1]
0
0
HEX_W1[1]
0
1
LH[14]
1
0
LH[2]
1
1
TERM_W:MUX.HEX_E2[2]
0.F0.B19
0.F0.B18
NONE
0
0
HEX_W1[2]
0
1
LH[8]
1
0
LH[20]
1
1
TERM_W:MUX.HEX_E2[3]
0.F0.B27
0.F0.B26
NONE
0
0
HEX_W1[3]
0
1
LH[14]
1
0
LH[2]
1
1
TERM_W:MUX.HEX_E2[4]
0.F0.B35
0.F0.B34
NONE
0
0
HEX_W1[4]
0
1
LH[8]
1
0
LH[20]
1
1
TERM_W:MUX.HEX_E2[5]
0.F0.B43
0.F0.B42
NONE
0
0
HEX_W1[5]
0
1
LH[14]
1
0
LH[2]
1
1
TERM_W:MUX.HEX_E2[6]
0.F0.B51
0.F0.B50
NONE
0
0
HEX_W1[6]
0
1
LH[8]
1
0
LH[20]
1
1
TERM_W:MUX.HEX_E2[7]
0.F0.B59
0.F0.B58
NONE
0
0
HEX_W1[7]
0
1
LH[14]
1
0
LH[2]
1
1
TERM_W:MUX.HEX_E2[8]
0.F0.B67
0.F0.B66
NONE
0
0
HEX_W1[8]
0
1
LH[8]
1
0
LH[20]
1
1
TERM_W:MUX.HEX_E2[9]
0.F0.B75
0.F0.B74
NONE
0
0
HEX_W1[9]
0
1
LH[14]
1
0
LH[2]
1
1
TERM_W:MUX.HEX_E3[0]
0.F1.B5
0.F1.B4
NONE
0
0
HEX_W2[0]
0
1
LH[9]
1
0
LH[21]
1
1
TERM_W:MUX.HEX_E3[1]
0.F1.B13
0.F1.B12
NONE
0
0
HEX_W2[1]
0
1
LH[15]
1
0
LH[3]
1
1
TERM_W:MUX.HEX_E3[2]
0.F1.B21
0.F1.B20
NONE
0
0
HEX_W2[2]
0
1
LH[9]
1
0
LH[21]
1
1
TERM_W:MUX.HEX_E3[3]
0.F1.B29
0.F1.B28
NONE
0
0
HEX_W2[3]
0
1
LH[15]
1
0
LH[3]
1
1
TERM_W:MUX.HEX_E3[4]
0.F1.B37
0.F1.B36
NONE
0
0
HEX_W2[4]
0
1
LH[9]
1
0
LH[21]
1
1
TERM_W:MUX.HEX_E3[5]
0.F1.B45
0.F1.B44
NONE
0
0
HEX_W2[5]
0
1
LH[15]
1
0
LH[3]
1
1
TERM_W:MUX.HEX_E3[6]
0.F1.B53
0.F1.B52
NONE
0
0
HEX_W2[6]
0
1
LH[9]
1
0
LH[21]
1
1
TERM_W:MUX.HEX_E3[7]
0.F1.B61
0.F1.B60
NONE
0
0
HEX_W2[7]
0
1
LH[15]
1
0
LH[3]
1
1
TERM_W:MUX.HEX_E3[8]
0.F1.B69
0.F1.B68
NONE
0
0
HEX_W2[8]
0
1
LH[9]
1
0
LH[21]
1
1
TERM_W:MUX.HEX_E3[9]
0.F1.B77
0.F1.B76
NONE
0
0
HEX_W2[9]
0
1
LH[15]
1
0
LH[3]
1
1
TERM_W:MUX.HEX_E4[0]
0.F0.B5
0.F0.B4
NONE
0
0
HEX_W3[0]
0
1
LH[10]
1
0
LH[22]
1
1
TERM_W:MUX.HEX_E4[1]
0.F0.B13
0.F0.B12
NONE
0
0
HEX_W3[1]
0
1
LH[16]
1
0
LH[4]
1
1
TERM_W:MUX.HEX_E4[2]
0.F0.B21
0.F0.B20
NONE
0
0
HEX_W3[2]
0
1
LH[10]
1
0
LH[22]
1
1
TERM_W:MUX.HEX_E4[3]
0.F0.B29
0.F0.B28
NONE
0
0
HEX_W3[3]
0
1
LH[16]
1
0
LH[4]
1
1
TERM_W:MUX.HEX_E4[4]
0.F0.B37
0.F0.B36
NONE
0
0
HEX_W3[4]
0
1
LH[10]
1
0
LH[22]
1
1
TERM_W:MUX.HEX_E4[5]
0.F0.B45
0.F0.B44
NONE
0
0
HEX_W3[5]
0
1
LH[16]
1
0
LH[4]
1
1
TERM_W:MUX.HEX_E4[6]
0.F0.B53
0.F0.B52
NONE
0
0
HEX_W3[6]
0
1
LH[10]
1
0
LH[22]
1
1
TERM_W:MUX.HEX_E4[7]
0.F0.B61
0.F0.B60
NONE
0
0
HEX_W3[7]
0
1
LH[16]
1
0
LH[4]
1
1
TERM_W:MUX.HEX_E4[8]
0.F0.B69
0.F0.B68
NONE
0
0
HEX_W3[8]
0
1
LH[10]
1
0
LH[22]
1
1
TERM_W:MUX.HEX_E4[9]
0.F0.B77
0.F0.B76
NONE
0
0
HEX_W3[9]
0
1
LH[16]
1
0
LH[4]
1
1
TERM_W:MUX.HEX_E5[0]
0.F1.B7
0.F1.B6
NONE
0
0
HEX_W4[0]
0
1
LH[11]
1
0
LH[23]
1
1
TERM_W:MUX.HEX_E5[1]
0.F1.B15
0.F1.B14
NONE
0
0
HEX_W4[1]
0
1
LH[17]
1
0
LH[5]
1
1
TERM_W:MUX.HEX_E5[2]
0.F1.B23
0.F1.B22
NONE
0
0
HEX_W4[2]
0
1
LH[11]
1
0
LH[23]
1
1
TERM_W:MUX.HEX_E5[3]
0.F1.B31
0.F1.B30
NONE
0
0
HEX_W4[3]
0
1
LH[17]
1
0
LH[5]
1
1
TERM_W:MUX.HEX_E5[4]
0.F1.B39
0.F1.B38
NONE
0
0
HEX_W4[4]
0
1
LH[11]
1
0
LH[23]
1
1
TERM_W:MUX.HEX_E5[5]
0.F1.B47
0.F1.B46
NONE
0
0
HEX_W4[5]
0
1
LH[17]
1
0
LH[5]
1
1
TERM_W:MUX.HEX_E5[6]
0.F1.B55
0.F1.B54
NONE
0
0
HEX_W4[6]
0
1
LH[11]
1
0
LH[23]
1
1
TERM_W:MUX.HEX_E5[7]
0.F1.B63
0.F1.B62
NONE
0
0
HEX_W4[7]
0
1
LH[17]
1
0
LH[5]
1
1
TERM_W:MUX.HEX_E5[8]
0.F1.B71
0.F1.B70
NONE
0
0
HEX_W4[8]
0
1
LH[11]
1
0
LH[23]
1
1
TERM_W:MUX.HEX_E5[9]
0.F1.B79
0.F1.B78
NONE
0
0
HEX_W4[9]
0
1
LH[17]
1
0
LH[5]
1
1
TERM_W:MUX.HEX_E6[0]
0.F0.B7
0.F0.B6
NONE
0
0
HEX_W5[0]
0
1
LH[12]
1
0
LH[0]
1
1
TERM_W:MUX.HEX_E6[1]
0.F0.B15
0.F0.B14
NONE
0
0
HEX_W5[1]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_W:MUX.HEX_E6[2]
0.F0.B23
0.F0.B22
NONE
0
0
HEX_W5[2]
0
1
LH[12]
1
0
LH[0]
1
1
TERM_W:MUX.HEX_E6[3]
0.F0.B31
0.F0.B30
NONE
0
0
HEX_W5[3]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_W:MUX.HEX_E6[4]
0.F0.B39
0.F0.B38
NONE
0
0
HEX_W5[4]
0
1
LH[12]
1
0
LH[0]
1
1
TERM_W:MUX.HEX_E6[5]
0.F0.B47
0.F0.B46
NONE
0
0
HEX_W5[5]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_W:MUX.HEX_E6[6]
0.F0.B55
0.F0.B54
NONE
0
0
HEX_W5[6]
0
1
LH[12]
1
0
LH[0]
1
1
TERM_W:MUX.HEX_E6[7]
0.F0.B63
0.F0.B62
NONE
0
0
HEX_W5[7]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_W:MUX.HEX_E6[8]
0.F0.B71
0.F0.B70
NONE
0
0
HEX_W5[8]
0
1
LH[12]
1
0
LH[0]
1
1
TERM_W:MUX.HEX_E6[9]
0.F0.B79
0.F0.B78
NONE
0
0
HEX_W5[9]
0
1
LH[18]
1
0
LH[6]
1
1
Located at the right edge of every interconnect row, this tile is 4×80 bits.
Cells: 1
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[0]
Bits Destination
HEX_W1[0] Source LH[17]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[1]
Bits Destination
HEX_W1[1] Source LH[23]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[2]
Bits Destination
HEX_W1[2] Source LH[17]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[3]
Bits Destination
HEX_W1[3] Source LH[23]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[4]
Bits Destination
HEX_W1[4] Source LH[17]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[5]
Bits Destination
HEX_W1[5] Source LH[23]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[6]
Bits Destination
HEX_W1[6] Source LH[17]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[7]
Bits Destination
HEX_W1[7] Source OUT_PCI[0]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[8]
Bits Destination
HEX_W1[8] Source LH[17]
virtex2 TERM_E switchbox TERM_E muxes HEX_W1[9]
Bits Destination
HEX_W1[9] Source LH[23]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[0]
Bits Destination
HEX_W2[0] Source LH[16]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[1]
Bits Destination
HEX_W2[1] Source LH[22]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[2]
Bits Destination
HEX_W2[2] Source LH[16]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[3]
Bits Destination
HEX_W2[3] Source LH[22]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[4]
Bits Destination
HEX_W2[4] Source LH[16]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[5]
Bits Destination
HEX_W2[5] Source LH[22]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[6]
Bits Destination
HEX_W2[6] Source LH[16]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[7]
Bits Destination
HEX_W2[7] Source OUT_PCI[1]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[8]
Bits Destination
HEX_W2[8] Source LH[16]
virtex2 TERM_E switchbox TERM_E muxes HEX_W2[9]
Bits Destination
HEX_W2[9] Source LH[22]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[0]
Bits Destination
HEX_W3[0] Source LH[15]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[1]
Bits Destination
HEX_W3[1] Source LH[21]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[2]
Bits Destination
HEX_W3[2] Source LH[15]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[3]
Bits Destination
HEX_W3[3] Source LH[21]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[4]
Bits Destination
HEX_W3[4] Source LH[15]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[5]
Bits Destination
HEX_W3[5] Source LH[21]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[6]
Bits Destination
HEX_W3[6] Source LH[15]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[7]
Bits Destination
HEX_W3[7] Source LH[21]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[8]
Bits Destination
HEX_W3[8] Source LH[15]
virtex2 TERM_E switchbox TERM_E muxes HEX_W3[9]
Bits Destination
HEX_W3[9] Source LH[21]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[0]
Bits Destination
HEX_W4[0] Source LH[14]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[1]
Bits Destination
HEX_W4[1] Source LH[20]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[2]
Bits Destination
HEX_W4[2] Source LH[14]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[3]
Bits Destination
HEX_W4[3] Source LH[20]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[4]
Bits Destination
HEX_W4[4] Source LH[14]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[5]
Bits Destination
HEX_W4[5] Source LH[20]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[6]
Bits Destination
HEX_W4[6] Source LH[14]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[7]
Bits Destination
HEX_W4[7] Source LH[20]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[8]
Bits Destination
HEX_W4[8] Source LH[14]
virtex2 TERM_E switchbox TERM_E muxes HEX_W4[9]
Bits Destination
HEX_W4[9] Source LH[20]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[0]
Bits Destination
HEX_W5[0] Source LH[13]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[1]
Bits Destination
HEX_W5[1] Source LH[19]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[2]
Bits Destination
HEX_W5[2] Source LH[13]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[3]
Bits Destination
HEX_W5[3] Source LH[19]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[4]
Bits Destination
HEX_W5[4] Source LH[13]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[5]
Bits Destination
HEX_W5[5] Source LH[19]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[6]
Bits Destination
HEX_W5[6] Source LH[13]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[7]
Bits Destination
HEX_W5[7] Source LH[19]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[8]
Bits Destination
HEX_W5[8] Source LH[13]
virtex2 TERM_E switchbox TERM_E muxes HEX_W5[9]
Bits Destination
HEX_W5[9] Source LH[19]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[0]
Bits Destination
HEX_W6[0] Source LH[12]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[1]
Bits Destination
HEX_W6[1] Source LH[18]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[2]
Bits Destination
HEX_W6[2] Source LH[12]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[3]
Bits Destination
HEX_W6[3] Source LH[18]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[4]
Bits Destination
HEX_W6[4] Source LH[12]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[5]
Bits Destination
HEX_W6[5] Source LH[18]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[6]
Bits Destination
HEX_W6[6] Source LH[12]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[7]
Bits Destination
HEX_W6[7] Source LH[18]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[8]
Bits Destination
HEX_W6[8] Source LH[12]
virtex2 TERM_E switchbox TERM_E muxes HEX_W6[9]
Bits Destination
HEX_W6[9] Source LH[18]
virtex2 TERM_E rect TERM
Bit Frame
F0
F1
F2
F3
B79
-
-
-
-
B78
-
-
-
-
B77
-
-
-
-
B76
-
-
-
-
B75
-
-
-
-
B74
-
-
-
-
B73
-
-
-
-
B72
-
-
-
-
B71
-
-
-
-
B70
-
-
-
-
B69
-
-
-
-
B68
-
-
-
-
B67
-
-
-
-
B66
-
-
-
-
B65
-
-
-
-
B64
-
-
-
-
B63
-
-
-
-
B62
-
-
-
-
B61
-
-
-
-
B60
-
-
-
-
B59
-
-
-
-
B58
-
-
-
-
B57
-
-
-
-
B56
-
-
-
-
B55
-
-
-
-
B54
-
-
-
-
B53
-
-
-
-
B52
-
-
-
-
B51
-
-
-
-
B50
-
-
-
-
B49
-
-
-
-
B48
-
-
-
-
B47
-
-
-
-
B46
-
-
-
-
B45
-
-
-
-
B44
-
-
-
-
B43
-
-
-
-
B42
-
-
-
-
B41
-
-
-
-
B40
-
-
-
-
B39
-
-
-
-
B38
-
-
-
-
B37
-
-
-
-
B36
-
-
-
-
B35
-
-
-
-
B34
-
-
-
-
B33
-
-
-
-
B32
-
-
-
-
B31
-
-
-
-
B30
-
-
-
-
B29
-
-
-
-
B28
-
-
-
-
B27
-
-
-
-
B26
-
-
-
-
B25
-
-
-
-
B24
-
-
-
-
B23
-
-
-
-
B22
-
-
-
-
B21
-
-
-
-
B20
-
-
-
-
B19
-
-
-
-
B18
-
-
-
-
B17
-
-
-
-
B16
-
-
-
-
B15
-
-
-
-
B14
-
-
-
-
B13
-
-
-
-
B12
-
-
-
-
B11
-
-
-
-
B10
-
-
-
-
B9
-
-
-
-
B8
-
-
-
-
B7
-
-
-
-
B6
-
-
-
-
B5
-
-
-
-
B4
-
-
-
-
B3
-
-
-
-
B2
-
-
-
-
B1
-
-
-
-
B0
-
-
-
-
### Bitstream
TERM_E:MUX.HEX_W1[0]
0.F1.B3
0.F1.B2
NONE
0
0
HEX_E0[0]
0
1
LH[5]
1
0
LH[17]
1
1
TERM_E:MUX.HEX_W1[1]
0.F1.B11
0.F1.B10
NONE
0
0
HEX_E0[1]
0
1
LH[23]
1
0
LH[11]
1
1
TERM_E:MUX.HEX_W1[2]
0.F1.B19
0.F1.B18
NONE
0
0
HEX_E0[2]
0
1
LH[5]
1
0
LH[17]
1
1
TERM_E:MUX.HEX_W1[3]
0.F1.B27
0.F1.B26
NONE
0
0
HEX_E0[3]
0
1
LH[23]
1
0
LH[11]
1
1
TERM_E:MUX.HEX_W1[4]
0.F1.B35
0.F1.B34
NONE
0
0
HEX_E0[4]
0
1
LH[5]
1
0
LH[17]
1
1
TERM_E:MUX.HEX_W1[5]
0.F1.B43
0.F1.B42
NONE
0
0
HEX_E0[5]
0
1
LH[23]
1
0
LH[11]
1
1
TERM_E:MUX.HEX_W1[6]
0.F1.B51
0.F1.B50
NONE
0
0
HEX_E0[6]
0
1
LH[5]
1
0
LH[17]
1
1
TERM_E:MUX.HEX_W1[7]
0.F1.B59
0.F1.B58
OUT_PCI[0]
0
0
HEX_E0[7]
0
1
LH[23]
1
0
LH[11]
1
1
TERM_E:MUX.HEX_W1[8]
0.F1.B67
0.F1.B66
NONE
0
0
HEX_E0[8]
0
1
LH[5]
1
0
LH[17]
1
1
TERM_E:MUX.HEX_W1[9]
0.F1.B75
0.F1.B74
NONE
0
0
HEX_E0[9]
0
1
LH[23]
1
0
LH[11]
1
1
TERM_E:MUX.HEX_W2[0]
0.F0.B3
0.F0.B2
NONE
0
0
HEX_E1[0]
0
1
LH[4]
1
0
LH[16]
1
1
TERM_E:MUX.HEX_W2[1]
0.F0.B11
0.F0.B10
NONE
0
0
HEX_E1[1]
0
1
LH[22]
1
0
LH[10]
1
1
TERM_E:MUX.HEX_W2[2]
0.F0.B19
0.F0.B18
NONE
0
0
HEX_E1[2]
0
1
LH[4]
1
0
LH[16]
1
1
TERM_E:MUX.HEX_W2[3]
0.F0.B27
0.F0.B26
NONE
0
0
HEX_E1[3]
0
1
LH[22]
1
0
LH[10]
1
1
TERM_E:MUX.HEX_W2[4]
0.F0.B35
0.F0.B34
NONE
0
0
HEX_E1[4]
0
1
LH[4]
1
0
LH[16]
1
1
TERM_E:MUX.HEX_W2[5]
0.F0.B43
0.F0.B42
NONE
0
0
HEX_E1[5]
0
1
LH[22]
1
0
LH[10]
1
1
TERM_E:MUX.HEX_W2[6]
0.F0.B51
0.F0.B50
NONE
0
0
HEX_E1[6]
0
1
LH[4]
1
0
LH[16]
1
1
TERM_E:MUX.HEX_W2[7]
0.F0.B59
0.F0.B58
OUT_PCI[1]
0
0
HEX_E1[7]
0
1
LH[22]
1
0
LH[10]
1
1
TERM_E:MUX.HEX_W2[8]
0.F0.B67
0.F0.B66
NONE
0
0
HEX_E1[8]
0
1
LH[4]
1
0
LH[16]
1
1
TERM_E:MUX.HEX_W2[9]
0.F0.B75
0.F0.B74
NONE
0
0
HEX_E1[9]
0
1
LH[22]
1
0
LH[10]
1
1
TERM_E:MUX.HEX_W3[0]
0.F1.B5
0.F1.B4
NONE
0
0
HEX_E2[0]
0
1
LH[3]
1
0
LH[15]
1
1
TERM_E:MUX.HEX_W3[1]
0.F1.B13
0.F1.B12
NONE
0
0
HEX_E2[1]
0
1
LH[21]
1
0
LH[9]
1
1
TERM_E:MUX.HEX_W3[2]
0.F1.B21
0.F1.B20
NONE
0
0
HEX_E2[2]
0
1
LH[3]
1
0
LH[15]
1
1
TERM_E:MUX.HEX_W3[3]
0.F1.B29
0.F1.B28
NONE
0
0
HEX_E2[3]
0
1
LH[21]
1
0
LH[9]
1
1
TERM_E:MUX.HEX_W3[4]
0.F1.B37
0.F1.B36
NONE
0
0
HEX_E2[4]
0
1
LH[3]
1
0
LH[15]
1
1
TERM_E:MUX.HEX_W3[5]
0.F1.B45
0.F1.B44
NONE
0
0
HEX_E2[5]
0
1
LH[21]
1
0
LH[9]
1
1
TERM_E:MUX.HEX_W3[6]
0.F1.B53
0.F1.B52
NONE
0
0
HEX_E2[6]
0
1
LH[3]
1
0
LH[15]
1
1
TERM_E:MUX.HEX_W3[7]
0.F1.B61
0.F1.B60
NONE
0
0
HEX_E2[7]
0
1
LH[21]
1
0
LH[9]
1
1
TERM_E:MUX.HEX_W3[8]
0.F1.B69
0.F1.B68
NONE
0
0
HEX_E2[8]
0
1
LH[3]
1
0
LH[15]
1
1
TERM_E:MUX.HEX_W3[9]
0.F1.B77
0.F1.B76
NONE
0
0
HEX_E2[9]
0
1
LH[21]
1
0
LH[9]
1
1
TERM_E:MUX.HEX_W4[0]
0.F0.B5
0.F0.B4
NONE
0
0
HEX_E3[0]
0
1
LH[2]
1
0
LH[14]
1
1
TERM_E:MUX.HEX_W4[1]
0.F0.B13
0.F0.B12
NONE
0
0
HEX_E3[1]
0
1
LH[20]
1
0
LH[8]
1
1
TERM_E:MUX.HEX_W4[2]
0.F0.B21
0.F0.B20
NONE
0
0
HEX_E3[2]
0
1
LH[2]
1
0
LH[14]
1
1
TERM_E:MUX.HEX_W4[3]
0.F0.B29
0.F0.B28
NONE
0
0
HEX_E3[3]
0
1
LH[20]
1
0
LH[8]
1
1
TERM_E:MUX.HEX_W4[4]
0.F0.B37
0.F0.B36
NONE
0
0
HEX_E3[4]
0
1
LH[2]
1
0
LH[14]
1
1
TERM_E:MUX.HEX_W4[5]
0.F0.B45
0.F0.B44
NONE
0
0
HEX_E3[5]
0
1
LH[20]
1
0
LH[8]
1
1
TERM_E:MUX.HEX_W4[6]
0.F0.B53
0.F0.B52
NONE
0
0
HEX_E3[6]
0
1
LH[2]
1
0
LH[14]
1
1
TERM_E:MUX.HEX_W4[7]
0.F0.B61
0.F0.B60
NONE
0
0
HEX_E3[7]
0
1
LH[20]
1
0
LH[8]
1
1
TERM_E:MUX.HEX_W4[8]
0.F0.B69
0.F0.B68
NONE
0
0
HEX_E3[8]
0
1
LH[2]
1
0
LH[14]
1
1
TERM_E:MUX.HEX_W4[9]
0.F0.B77
0.F0.B76
NONE
0
0
HEX_E3[9]
0
1
LH[20]
1
0
LH[8]
1
1
TERM_E:MUX.HEX_W5[0]
0.F1.B7
0.F1.B6
NONE
0
0
HEX_E4[0]
0
1
LH[1]
1
0
LH[13]
1
1
TERM_E:MUX.HEX_W5[1]
0.F1.B15
0.F1.B14
NONE
0
0
HEX_E4[1]
0
1
LH[19]
1
0
LH[7]
1
1
TERM_E:MUX.HEX_W5[2]
0.F1.B23
0.F1.B22
NONE
0
0
HEX_E4[2]
0
1
LH[1]
1
0
LH[13]
1
1
TERM_E:MUX.HEX_W5[3]
0.F1.B31
0.F1.B30
NONE
0
0
HEX_E4[3]
0
1
LH[19]
1
0
LH[7]
1
1
TERM_E:MUX.HEX_W5[4]
0.F1.B39
0.F1.B38
NONE
0
0
HEX_E4[4]
0
1
LH[1]
1
0
LH[13]
1
1
TERM_E:MUX.HEX_W5[5]
0.F1.B47
0.F1.B46
NONE
0
0
HEX_E4[5]
0
1
LH[19]
1
0
LH[7]
1
1
TERM_E:MUX.HEX_W5[6]
0.F1.B55
0.F1.B54
NONE
0
0
HEX_E4[6]
0
1
LH[1]
1
0
LH[13]
1
1
TERM_E:MUX.HEX_W5[7]
0.F1.B63
0.F1.B62
NONE
0
0
HEX_E4[7]
0
1
LH[19]
1
0
LH[7]
1
1
TERM_E:MUX.HEX_W5[8]
0.F1.B71
0.F1.B70
NONE
0
0
HEX_E4[8]
0
1
LH[1]
1
0
LH[13]
1
1
TERM_E:MUX.HEX_W5[9]
0.F1.B79
0.F1.B78
NONE
0
0
HEX_E4[9]
0
1
LH[19]
1
0
LH[7]
1
1
TERM_E:MUX.HEX_W6[0]
0.F0.B7
0.F0.B6
NONE
0
0
HEX_E5[0]
0
1
LH[0]
1
0
LH[12]
1
1
TERM_E:MUX.HEX_W6[1]
0.F0.B15
0.F0.B14
NONE
0
0
HEX_E5[1]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_E:MUX.HEX_W6[2]
0.F0.B23
0.F0.B22
NONE
0
0
HEX_E5[2]
0
1
LH[0]
1
0
LH[12]
1
1
TERM_E:MUX.HEX_W6[3]
0.F0.B31
0.F0.B30
NONE
0
0
HEX_E5[3]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_E:MUX.HEX_W6[4]
0.F0.B39
0.F0.B38
NONE
0
0
HEX_E5[4]
0
1
LH[0]
1
0
LH[12]
1
1
TERM_E:MUX.HEX_W6[5]
0.F0.B47
0.F0.B46
NONE
0
0
HEX_E5[5]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_E:MUX.HEX_W6[6]
0.F0.B55
0.F0.B54
NONE
0
0
HEX_E5[6]
0
1
LH[0]
1
0
LH[12]
1
1
TERM_E:MUX.HEX_W6[7]
0.F0.B63
0.F0.B62
NONE
0
0
HEX_E5[7]
0
1
LH[18]
1
0
LH[6]
1
1
TERM_E:MUX.HEX_W6[8]
0.F0.B71
0.F0.B70
NONE
0
0
HEX_E5[8]
0
1
LH[0]
1
0
LH[12]
1
1
TERM_E:MUX.HEX_W6[9]
0.F0.B79
0.F0.B78
NONE
0
0
HEX_E5[9]
0
1
LH[18]
1
0
LH[6]
1
1
Located at the bottom edge of every interconnect column, this tile is 22×12 bits.
Cells: 1
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[0]
Bits Destination
HEX_N1[0] Source LV[23]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[1]
Bits Destination
HEX_N1[1] Source LV[17]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[2]
Bits Destination
HEX_N1[2] Source LV[23]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[3]
Bits Destination
HEX_N1[3] Source LV[17]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[4]
Bits Destination
HEX_N1[4] Source LV[23]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[5]
Bits Destination
HEX_N1[5] Source LV[17]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[6]
Bits Destination
HEX_N1[6] Source LV[23]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[7]
Bits Destination
HEX_N1[7] Source LV[17]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[8]
Bits Destination
HEX_N1[8] Source LV[23]
virtex2 TERM_S switchbox TERM_S muxes HEX_N1[9]
Bits Destination
HEX_N1[9] Source LV[17]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[0]
Bits Destination
HEX_N2[0] Source LV[22]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[1]
Bits Destination
HEX_N2[1] Source LV[16]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[2]
Bits Destination
HEX_N2[2] Source LV[22]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[3]
Bits Destination
HEX_N2[3] Source LV[16]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[4]
Bits Destination
HEX_N2[4] Source LV[22]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[5]
Bits Destination
HEX_N2[5] Source LV[16]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[6]
Bits Destination
HEX_N2[6] Source LV[22]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[7]
Bits Destination
HEX_N2[7] Source LV[16]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[8]
Bits Destination
HEX_N2[8] Source LV[22]
virtex2 TERM_S switchbox TERM_S muxes HEX_N2[9]
Bits Destination
HEX_N2[9] Source LV[16]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[0]
Bits Destination
HEX_N3[0] Source LV[21]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[1]
Bits Destination
HEX_N3[1] Source LV[15]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[2]
Bits Destination
HEX_N3[2] Source LV[21]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[3]
Bits Destination
HEX_N3[3] Source LV[15]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[4]
Bits Destination
HEX_N3[4] Source LV[21]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[5]
Bits Destination
HEX_N3[5] Source LV[15]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[6]
Bits Destination
HEX_N3[6] Source LV[21]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[7]
Bits Destination
HEX_N3[7] Source LV[15]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[8]
Bits Destination
HEX_N3[8] Source LV[21]
virtex2 TERM_S switchbox TERM_S muxes HEX_N3[9]
Bits Destination
HEX_N3[9] Source LV[15]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[0]
Bits Destination
HEX_N4[0] Source LV[20]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[1]
Bits Destination
HEX_N4[1] Source LV[14]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[2]
Bits Destination
HEX_N4[2] Source LV[20]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[3]
Bits Destination
HEX_N4[3] Source LV[14]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[4]
Bits Destination
HEX_N4[4] Source LV[20]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[5]
Bits Destination
HEX_N4[5] Source LV[14]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[6]
Bits Destination
HEX_N4[6] Source LV[20]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[7]
Bits Destination
HEX_N4[7] Source LV[14]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[8]
Bits Destination
HEX_N4[8] Source LV[20]
virtex2 TERM_S switchbox TERM_S muxes HEX_N4[9]
Bits Destination
HEX_N4[9] Source LV[14]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[0]
Bits Destination
HEX_N5[0] Source LV[19]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[1]
Bits Destination
HEX_N5[1] Source LV[13]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[2]
Bits Destination
HEX_N5[2] Source LV[19]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[3]
Bits Destination
HEX_N5[3] Source LV[13]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[4]
Bits Destination
HEX_N5[4] Source LV[19]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[5]
Bits Destination
HEX_N5[5] Source LV[13]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[6]
Bits Destination
HEX_N5[6] Source LV[19]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[7]
Bits Destination
HEX_N5[7] Source LV[13]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[8]
Bits Destination
HEX_N5[8] Source LV[19]
virtex2 TERM_S switchbox TERM_S muxes HEX_N5[9]
Bits Destination
HEX_N5[9] Source LV[13]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[0]
Bits Destination
HEX_N6[0] Source LV[18]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[1]
Bits Destination
HEX_N6[1] Source LV[12]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[2]
Bits Destination
HEX_N6[2] Source LV[18]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[3]
Bits Destination
HEX_N6[3] Source LV[12]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[4]
Bits Destination
HEX_N6[4] Source LV[18]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[5]
Bits Destination
HEX_N6[5] Source LV[12]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[6]
Bits Destination
HEX_N6[6] Source LV[18]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[7]
Bits Destination
HEX_N6[7] Source LV[12]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[8]
Bits Destination
HEX_N6[8] Source LV[18]
virtex2 TERM_S switchbox TERM_S muxes HEX_N6[9]
Bits Destination
HEX_N6[9] Source LV[12]
virtex2 TERM_S rect TERM
Bit Frame
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
B11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
### Bitstream
TERM_S:MUX.HEX_N1[0]
0.F9.B4
0.F9.B5
NONE
0
0
HEX_S0[0]
0
1
LV[23]
1
0
LV[11]
1
1
TERM_S:MUX.HEX_N1[1]
0.F21.B4
0.F21.B5
NONE
0
0
HEX_S0[1]
0
1
LV[17]
1
0
LV[5]
1
1
TERM_S:MUX.HEX_N1[2]
0.F14.B4
0.F14.B5
NONE
0
0
HEX_S0[2]
0
1
LV[23]
1
0
LV[11]
1
1
TERM_S:MUX.HEX_N1[3]
0.F6.B4
0.F6.B5
NONE
0
0
HEX_S0[3]
0
1
LV[17]
1
0
LV[5]
1
1
TERM_S:MUX.HEX_N1[4]
0.F18.B4
0.F18.B5
NONE
0
0
HEX_S0[4]
0
1
LV[23]
1
0
LV[11]
1
1
TERM_S:MUX.HEX_N1[5]
0.F13.B4
0.F13.B5
NONE
0
0
HEX_S0[5]
0
1
LV[17]
1
0
LV[5]
1
1
TERM_S:MUX.HEX_N1[6]
0.F5.B4
0.F5.B5
NONE
0
0
HEX_S0[6]
0
1
LV[23]
1
0
LV[11]
1
1
TERM_S:MUX.HEX_N1[7]
0.F17.B4
0.F17.B5
NONE
0
0
HEX_S0[7]
0
1
LV[17]
1
0
LV[5]
1
1
TERM_S:MUX.HEX_N1[8]
0.F10.B4
0.F10.B5
NONE
0
0
HEX_S0[8]
0
1
LV[23]
1
0
LV[11]
1
1
TERM_S:MUX.HEX_N1[9]
0.F0.B4
0.F0.B5
NONE
0
0
HEX_S0[9]
0
1
LV[17]
1
0
LV[5]
1
1
TERM_S:MUX.HEX_N2[0]
0.F8.B4
0.F8.B5
NONE
0
0
HEX_S1[0]
0
1
LV[22]
1
0
LV[10]
1
1
TERM_S:MUX.HEX_N2[1]
0.F20.B4
0.F20.B5
NONE
0
0
HEX_S1[1]
0
1
LV[16]
1
0
LV[4]
1
1
TERM_S:MUX.HEX_N2[2]
0.F15.B4
0.F15.B5
NONE
0
0
HEX_S1[2]
0
1
LV[22]
1
0
LV[10]
1
1
TERM_S:MUX.HEX_N2[3]
0.F7.B4
0.F7.B5
NONE
0
0
HEX_S1[3]
0
1
LV[16]
1
0
LV[4]
1
1
TERM_S:MUX.HEX_N2[4]
0.F19.B4
0.F19.B5
NONE
0
0
HEX_S1[4]
0
1
LV[22]
1
0
LV[10]
1
1
TERM_S:MUX.HEX_N2[5]
0.F12.B4
0.F12.B5
NONE
0
0
HEX_S1[5]
0
1
LV[16]
1
0
LV[4]
1
1
TERM_S:MUX.HEX_N2[6]
0.F4.B4
0.F4.B5
NONE
0
0
HEX_S1[6]
0
1
LV[22]
1
0
LV[10]
1
1
TERM_S:MUX.HEX_N2[7]
0.F16.B4
0.F16.B5
NONE
0
0
HEX_S1[7]
0
1
LV[16]
1
0
LV[4]
1
1
TERM_S:MUX.HEX_N2[8]
0.F11.B4
0.F11.B5
NONE
0
0
HEX_S1[8]
0
1
LV[22]
1
0
LV[10]
1
1
TERM_S:MUX.HEX_N2[9]
0.F3.B4
0.F3.B5
NONE
0
0
HEX_S1[9]
0
1
LV[16]
1
0
LV[4]
1
1
TERM_S:MUX.HEX_N3[0]
0.F9.B2
0.F9.B3
NONE
0
0
HEX_S2[0]
0
1
LV[21]
1
0
LV[9]
1
1
TERM_S:MUX.HEX_N3[1]
0.F21.B2
0.F21.B3
NONE
0
0
HEX_S2[1]
0
1
LV[15]
1
0
LV[3]
1
1
TERM_S:MUX.HEX_N3[2]
0.F14.B2
0.F14.B3
NONE
0
0
HEX_S2[2]
0
1
LV[21]
1
0
LV[9]
1
1
TERM_S:MUX.HEX_N3[3]
0.F6.B2
0.F6.B3
NONE
0
0
HEX_S2[3]
0
1
LV[15]
1
0
LV[3]
1
1
TERM_S:MUX.HEX_N3[4]
0.F18.B2
0.F18.B3
NONE
0
0
HEX_S2[4]
0
1
LV[21]
1
0
LV[9]
1
1
TERM_S:MUX.HEX_N3[5]
0.F13.B2
0.F13.B3
NONE
0
0
HEX_S2[5]
0
1
LV[15]
1
0
LV[3]
1
1
TERM_S:MUX.HEX_N3[6]
0.F5.B2
0.F5.B3
NONE
0
0
HEX_S2[6]
0
1
LV[21]
1
0
LV[9]
1
1
TERM_S:MUX.HEX_N3[7]
0.F17.B2
0.F17.B3
NONE
0
0
HEX_S2[7]
0
1
LV[15]
1
0
LV[3]
1
1
TERM_S:MUX.HEX_N3[8]
0.F10.B2
0.F10.B3
NONE
0
0
HEX_S2[8]
0
1
LV[21]
1
0
LV[9]
1
1
TERM_S:MUX.HEX_N3[9]
0.F0.B2
0.F0.B3
NONE
0
0
HEX_S2[9]
0
1
LV[15]
1
0
LV[3]
1
1
TERM_S:MUX.HEX_N4[0]
0.F8.B2
0.F8.B3
NONE
0
0
HEX_S3[0]
0
1
LV[20]
1
0
LV[8]
1
1
TERM_S:MUX.HEX_N4[1]
0.F20.B2
0.F20.B3
NONE
0
0
HEX_S3[1]
0
1
LV[14]
1
0
LV[2]
1
1
TERM_S:MUX.HEX_N4[2]
0.F15.B2
0.F15.B3
NONE
0
0
HEX_S3[2]
0
1
LV[20]
1
0
LV[8]
1
1
TERM_S:MUX.HEX_N4[3]
0.F7.B2
0.F7.B3
NONE
0
0
HEX_S3[3]
0
1
LV[14]
1
0
LV[2]
1
1
TERM_S:MUX.HEX_N4[4]
0.F19.B2
0.F19.B3
NONE
0
0
HEX_S3[4]
0
1
LV[20]
1
0
LV[8]
1
1
TERM_S:MUX.HEX_N4[5]
0.F12.B2
0.F12.B3
NONE
0
0
HEX_S3[5]
0
1
LV[14]
1
0
LV[2]
1
1
TERM_S:MUX.HEX_N4[6]
0.F4.B2
0.F4.B3
NONE
0
0
HEX_S3[6]
0
1
LV[20]
1
0
LV[8]
1
1
TERM_S:MUX.HEX_N4[7]
0.F16.B2
0.F16.B3
NONE
0
0
HEX_S3[7]
0
1
LV[14]
1
0
LV[2]
1
1
TERM_S:MUX.HEX_N4[8]
0.F11.B2
0.F11.B3
NONE
0
0
HEX_S3[8]
0
1
LV[20]
1
0
LV[8]
1
1
TERM_S:MUX.HEX_N4[9]
0.F3.B2
0.F3.B3
NONE
0
0
HEX_S3[9]
0
1
LV[14]
1
0
LV[2]
1
1
TERM_S:MUX.HEX_N5[0]
0.F9.B0
0.F9.B1
NONE
0
0
HEX_S4[0]
0
1
LV[19]
1
0
LV[7]
1
1
TERM_S:MUX.HEX_N5[1]
0.F21.B0
0.F21.B1
NONE
0
0
HEX_S4[1]
0
1
LV[13]
1
0
LV[1]
1
1
TERM_S:MUX.HEX_N5[2]
0.F14.B0
0.F14.B1
NONE
0
0
HEX_S4[2]
0
1
LV[19]
1
0
LV[7]
1
1
TERM_S:MUX.HEX_N5[3]
0.F6.B0
0.F6.B1
NONE
0
0
HEX_S4[3]
0
1
LV[13]
1
0
LV[1]
1
1
TERM_S:MUX.HEX_N5[4]
0.F18.B0
0.F18.B1
NONE
0
0
HEX_S4[4]
0
1
LV[19]
1
0
LV[7]
1
1
TERM_S:MUX.HEX_N5[5]
0.F13.B0
0.F13.B1
NONE
0
0
HEX_S4[5]
0
1
LV[13]
1
0
LV[1]
1
1
TERM_S:MUX.HEX_N5[6]
0.F5.B0
0.F5.B1
NONE
0
0
HEX_S4[6]
0
1
LV[19]
1
0
LV[7]
1
1
TERM_S:MUX.HEX_N5[7]
0.F17.B0
0.F17.B1
NONE
0
0
HEX_S4[7]
0
1
LV[13]
1
0
LV[1]
1
1
TERM_S:MUX.HEX_N5[8]
0.F10.B0
0.F10.B1
NONE
0
0
HEX_S4[8]
0
1
LV[19]
1
0
LV[7]
1
1
TERM_S:MUX.HEX_N5[9]
0.F0.B0
0.F0.B1
NONE
0
0
HEX_S4[9]
0
1
LV[13]
1
0
LV[1]
1
1
TERM_S:MUX.HEX_N6[0]
0.F8.B0
0.F8.B1
NONE
0
0
HEX_S5[0]
0
1
LV[18]
1
0
LV[6]
1
1
TERM_S:MUX.HEX_N6[1]
0.F20.B0
0.F20.B1
NONE
0
0
HEX_S5[1]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_S:MUX.HEX_N6[2]
0.F15.B0
0.F15.B1
NONE
0
0
HEX_S5[2]
0
1
LV[18]
1
0
LV[6]
1
1
TERM_S:MUX.HEX_N6[3]
0.F7.B0
0.F7.B1
NONE
0
0
HEX_S5[3]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_S:MUX.HEX_N6[4]
0.F19.B0
0.F19.B1
NONE
0
0
HEX_S5[4]
0
1
LV[18]
1
0
LV[6]
1
1
TERM_S:MUX.HEX_N6[5]
0.F12.B0
0.F12.B1
NONE
0
0
HEX_S5[5]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_S:MUX.HEX_N6[6]
0.F4.B0
0.F4.B1
NONE
0
0
HEX_S5[6]
0
1
LV[18]
1
0
LV[6]
1
1
TERM_S:MUX.HEX_N6[7]
0.F16.B0
0.F16.B1
NONE
0
0
HEX_S5[7]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_S:MUX.HEX_N6[8]
0.F11.B0
0.F11.B1
NONE
0
0
HEX_S5[8]
0
1
LV[18]
1
0
LV[6]
1
1
TERM_S:MUX.HEX_N6[9]
0.F3.B0
0.F3.B1
NONE
0
0
HEX_S5[9]
0
1
LV[12]
1
0
LV[0]
1
1
Located at the top edge of every interconnect column, this tile is 22×12 bits.
Cells: 1
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[0]
Bits Destination
HEX_S1[0] Source LV[13]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[1]
Bits Destination
HEX_S1[1] Source LV[19]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[2]
Bits Destination
HEX_S1[2] Source LV[13]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[3]
Bits Destination
HEX_S1[3] Source LV[19]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[4]
Bits Destination
HEX_S1[4] Source LV[13]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[5]
Bits Destination
HEX_S1[5] Source LV[19]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[6]
Bits Destination
HEX_S1[6] Source LV[13]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[7]
Bits Destination
HEX_S1[7] Source LV[19]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[8]
Bits Destination
HEX_S1[8] Source LV[13]
virtex2 TERM_N switchbox TERM_N muxes HEX_S1[9]
Bits Destination
HEX_S1[9] Source LV[19]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[0]
Bits Destination
HEX_S2[0] Source LV[14]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[1]
Bits Destination
HEX_S2[1] Source LV[20]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[2]
Bits Destination
HEX_S2[2] Source LV[14]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[3]
Bits Destination
HEX_S2[3] Source LV[20]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[4]
Bits Destination
HEX_S2[4] Source LV[14]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[5]
Bits Destination
HEX_S2[5] Source LV[20]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[6]
Bits Destination
HEX_S2[6] Source LV[14]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[7]
Bits Destination
HEX_S2[7] Source LV[20]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[8]
Bits Destination
HEX_S2[8] Source LV[14]
virtex2 TERM_N switchbox TERM_N muxes HEX_S2[9]
Bits Destination
HEX_S2[9] Source LV[20]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[0]
Bits Destination
HEX_S3[0] Source LV[15]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[1]
Bits Destination
HEX_S3[1] Source LV[21]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[2]
Bits Destination
HEX_S3[2] Source LV[15]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[3]
Bits Destination
HEX_S3[3] Source LV[21]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[4]
Bits Destination
HEX_S3[4] Source LV[15]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[5]
Bits Destination
HEX_S3[5] Source LV[21]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[6]
Bits Destination
HEX_S3[6] Source LV[15]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[7]
Bits Destination
HEX_S3[7] Source LV[21]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[8]
Bits Destination
HEX_S3[8] Source LV[15]
virtex2 TERM_N switchbox TERM_N muxes HEX_S3[9]
Bits Destination
HEX_S3[9] Source LV[21]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[0]
Bits Destination
HEX_S4[0] Source LV[16]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[1]
Bits Destination
HEX_S4[1] Source LV[22]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[2]
Bits Destination
HEX_S4[2] Source LV[16]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[3]
Bits Destination
HEX_S4[3] Source LV[22]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[4]
Bits Destination
HEX_S4[4] Source LV[16]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[5]
Bits Destination
HEX_S4[5] Source LV[22]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[6]
Bits Destination
HEX_S4[6] Source LV[16]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[7]
Bits Destination
HEX_S4[7] Source LV[22]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[8]
Bits Destination
HEX_S4[8] Source LV[16]
virtex2 TERM_N switchbox TERM_N muxes HEX_S4[9]
Bits Destination
HEX_S4[9] Source LV[22]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[0]
Bits Destination
HEX_S5[0] Source LV[17]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[1]
Bits Destination
HEX_S5[1] Source LV[23]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[2]
Bits Destination
HEX_S5[2] Source LV[17]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[3]
Bits Destination
HEX_S5[3] Source LV[23]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[4]
Bits Destination
HEX_S5[4] Source LV[17]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[5]
Bits Destination
HEX_S5[5] Source LV[23]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[6]
Bits Destination
HEX_S5[6] Source LV[17]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[7]
Bits Destination
HEX_S5[7] Source LV[23]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[8]
Bits Destination
HEX_S5[8] Source LV[17]
virtex2 TERM_N switchbox TERM_N muxes HEX_S5[9]
Bits Destination
HEX_S5[9] Source LV[23]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[0]
Bits Destination
HEX_S6[0] Source LV[18]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[1]
Bits Destination
HEX_S6[1] Source LV[12]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[2]
Bits Destination
HEX_S6[2] Source LV[18]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[3]
Bits Destination
HEX_S6[3] Source LV[12]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[4]
Bits Destination
HEX_S6[4] Source LV[18]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[5]
Bits Destination
HEX_S6[5] Source LV[12]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[6]
Bits Destination
HEX_S6[6] Source LV[18]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[7]
Bits Destination
HEX_S6[7] Source LV[12]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[8]
Bits Destination
HEX_S6[8] Source LV[18]
virtex2 TERM_N switchbox TERM_N muxes HEX_S6[9]
Bits Destination
HEX_S6[9] Source LV[12]
virtex2 TERM_N rect TERM
Bit Frame
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
B11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
### Bitstream
TERM_N:MUX.HEX_S1[0]
0.F9.B4
0.F9.B5
NONE
0
0
HEX_N0[0]
0
1
LV[1]
1
0
LV[13]
1
1
TERM_N:MUX.HEX_S1[1]
0.F21.B4
0.F21.B5
NONE
0
0
HEX_N0[1]
0
1
LV[7]
1
0
LV[19]
1
1
TERM_N:MUX.HEX_S1[2]
0.F14.B4
0.F14.B5
NONE
0
0
HEX_N0[2]
0
1
LV[1]
1
0
LV[13]
1
1
TERM_N:MUX.HEX_S1[3]
0.F6.B4
0.F6.B5
NONE
0
0
HEX_N0[3]
0
1
LV[7]
1
0
LV[19]
1
1
TERM_N:MUX.HEX_S1[4]
0.F18.B4
0.F18.B5
NONE
0
0
HEX_N0[4]
0
1
LV[1]
1
0
LV[13]
1
1
TERM_N:MUX.HEX_S1[5]
0.F13.B4
0.F13.B5
NONE
0
0
HEX_N0[5]
0
1
LV[7]
1
0
LV[19]
1
1
TERM_N:MUX.HEX_S1[6]
0.F5.B4
0.F5.B5
NONE
0
0
HEX_N0[6]
0
1
LV[1]
1
0
LV[13]
1
1
TERM_N:MUX.HEX_S1[7]
0.F17.B4
0.F17.B5
NONE
0
0
HEX_N0[7]
0
1
LV[7]
1
0
LV[19]
1
1
TERM_N:MUX.HEX_S1[8]
0.F10.B4
0.F10.B5
NONE
0
0
HEX_N0[8]
0
1
LV[1]
1
0
LV[13]
1
1
TERM_N:MUX.HEX_S1[9]
0.F0.B4
0.F0.B5
NONE
0
0
HEX_N0[9]
0
1
LV[7]
1
0
LV[19]
1
1
TERM_N:MUX.HEX_S2[0]
0.F8.B4
0.F8.B5
NONE
0
0
HEX_N1[0]
0
1
LV[2]
1
0
LV[14]
1
1
TERM_N:MUX.HEX_S2[1]
0.F20.B4
0.F20.B5
NONE
0
0
HEX_N1[1]
0
1
LV[8]
1
0
LV[20]
1
1
TERM_N:MUX.HEX_S2[2]
0.F15.B4
0.F15.B5
NONE
0
0
HEX_N1[2]
0
1
LV[2]
1
0
LV[14]
1
1
TERM_N:MUX.HEX_S2[3]
0.F7.B4
0.F7.B5
NONE
0
0
HEX_N1[3]
0
1
LV[8]
1
0
LV[20]
1
1
TERM_N:MUX.HEX_S2[4]
0.F19.B4
0.F19.B5
NONE
0
0
HEX_N1[4]
0
1
LV[2]
1
0
LV[14]
1
1
TERM_N:MUX.HEX_S2[5]
0.F12.B4
0.F12.B5
NONE
0
0
HEX_N1[5]
0
1
LV[8]
1
0
LV[20]
1
1
TERM_N:MUX.HEX_S2[6]
0.F4.B4
0.F4.B5
NONE
0
0
HEX_N1[6]
0
1
LV[2]
1
0
LV[14]
1
1
TERM_N:MUX.HEX_S2[7]
0.F16.B4
0.F16.B5
NONE
0
0
HEX_N1[7]
0
1
LV[8]
1
0
LV[20]
1
1
TERM_N:MUX.HEX_S2[8]
0.F11.B4
0.F11.B5
NONE
0
0
HEX_N1[8]
0
1
LV[2]
1
0
LV[14]
1
1
TERM_N:MUX.HEX_S2[9]
0.F3.B4
0.F3.B5
NONE
0
0
HEX_N1[9]
0
1
LV[8]
1
0
LV[20]
1
1
TERM_N:MUX.HEX_S3[0]
0.F9.B2
0.F9.B3
NONE
0
0
HEX_N2[0]
0
1
LV[3]
1
0
LV[15]
1
1
TERM_N:MUX.HEX_S3[1]
0.F21.B2
0.F21.B3
NONE
0
0
HEX_N2[1]
0
1
LV[9]
1
0
LV[21]
1
1
TERM_N:MUX.HEX_S3[2]
0.F14.B2
0.F14.B3
NONE
0
0
HEX_N2[2]
0
1
LV[3]
1
0
LV[15]
1
1
TERM_N:MUX.HEX_S3[3]
0.F6.B2
0.F6.B3
NONE
0
0
HEX_N2[3]
0
1
LV[9]
1
0
LV[21]
1
1
TERM_N:MUX.HEX_S3[4]
0.F18.B2
0.F18.B3
NONE
0
0
HEX_N2[4]
0
1
LV[3]
1
0
LV[15]
1
1
TERM_N:MUX.HEX_S3[5]
0.F13.B2
0.F13.B3
NONE
0
0
HEX_N2[5]
0
1
LV[9]
1
0
LV[21]
1
1
TERM_N:MUX.HEX_S3[6]
0.F5.B2
0.F5.B3
NONE
0
0
HEX_N2[6]
0
1
LV[3]
1
0
LV[15]
1
1
TERM_N:MUX.HEX_S3[7]
0.F17.B2
0.F17.B3
NONE
0
0
HEX_N2[7]
0
1
LV[9]
1
0
LV[21]
1
1
TERM_N:MUX.HEX_S3[8]
0.F10.B2
0.F10.B3
NONE
0
0
HEX_N2[8]
0
1
LV[3]
1
0
LV[15]
1
1
TERM_N:MUX.HEX_S3[9]
0.F0.B2
0.F0.B3
NONE
0
0
HEX_N2[9]
0
1
LV[9]
1
0
LV[21]
1
1
TERM_N:MUX.HEX_S4[0]
0.F8.B2
0.F8.B3
NONE
0
0
HEX_N3[0]
0
1
LV[4]
1
0
LV[16]
1
1
TERM_N:MUX.HEX_S4[1]
0.F20.B2
0.F20.B3
NONE
0
0
HEX_N3[1]
0
1
LV[10]
1
0
LV[22]
1
1
TERM_N:MUX.HEX_S4[2]
0.F15.B2
0.F15.B3
NONE
0
0
HEX_N3[2]
0
1
LV[4]
1
0
LV[16]
1
1
TERM_N:MUX.HEX_S4[3]
0.F7.B2
0.F7.B3
NONE
0
0
HEX_N3[3]
0
1
LV[10]
1
0
LV[22]
1
1
TERM_N:MUX.HEX_S4[4]
0.F19.B2
0.F19.B3
NONE
0
0
HEX_N3[4]
0
1
LV[4]
1
0
LV[16]
1
1
TERM_N:MUX.HEX_S4[5]
0.F12.B2
0.F12.B3
NONE
0
0
HEX_N3[5]
0
1
LV[10]
1
0
LV[22]
1
1
TERM_N:MUX.HEX_S4[6]
0.F4.B2
0.F4.B3
NONE
0
0
HEX_N3[6]
0
1
LV[4]
1
0
LV[16]
1
1
TERM_N:MUX.HEX_S4[7]
0.F16.B2
0.F16.B3
NONE
0
0
HEX_N3[7]
0
1
LV[10]
1
0
LV[22]
1
1
TERM_N:MUX.HEX_S4[8]
0.F11.B2
0.F11.B3
NONE
0
0
HEX_N3[8]
0
1
LV[4]
1
0
LV[16]
1
1
TERM_N:MUX.HEX_S4[9]
0.F3.B2
0.F3.B3
NONE
0
0
HEX_N3[9]
0
1
LV[10]
1
0
LV[22]
1
1
TERM_N:MUX.HEX_S5[0]
0.F9.B0
0.F9.B1
NONE
0
0
HEX_N4[0]
0
1
LV[5]
1
0
LV[17]
1
1
TERM_N:MUX.HEX_S5[1]
0.F21.B0
0.F21.B1
NONE
0
0
HEX_N4[1]
0
1
LV[11]
1
0
LV[23]
1
1
TERM_N:MUX.HEX_S5[2]
0.F14.B0
0.F14.B1
NONE
0
0
HEX_N4[2]
0
1
LV[5]
1
0
LV[17]
1
1
TERM_N:MUX.HEX_S5[3]
0.F6.B0
0.F6.B1
NONE
0
0
HEX_N4[3]
0
1
LV[11]
1
0
LV[23]
1
1
TERM_N:MUX.HEX_S5[4]
0.F18.B0
0.F18.B1
NONE
0
0
HEX_N4[4]
0
1
LV[5]
1
0
LV[17]
1
1
TERM_N:MUX.HEX_S5[5]
0.F13.B0
0.F13.B1
NONE
0
0
HEX_N4[5]
0
1
LV[11]
1
0
LV[23]
1
1
TERM_N:MUX.HEX_S5[6]
0.F5.B0
0.F5.B1
NONE
0
0
HEX_N4[6]
0
1
LV[5]
1
0
LV[17]
1
1
TERM_N:MUX.HEX_S5[7]
0.F17.B0
0.F17.B1
NONE
0
0
HEX_N4[7]
0
1
LV[11]
1
0
LV[23]
1
1
TERM_N:MUX.HEX_S5[8]
0.F10.B0
0.F10.B1
NONE
0
0
HEX_N4[8]
0
1
LV[5]
1
0
LV[17]
1
1
TERM_N:MUX.HEX_S5[9]
0.F0.B0
0.F0.B1
NONE
0
0
HEX_N4[9]
0
1
LV[11]
1
0
LV[23]
1
1
TERM_N:MUX.HEX_S6[0]
0.F8.B0
0.F8.B1
NONE
0
0
HEX_N5[0]
0
1
LV[6]
1
0
LV[18]
1
1
TERM_N:MUX.HEX_S6[1]
0.F20.B0
0.F20.B1
NONE
0
0
HEX_N5[1]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_N:MUX.HEX_S6[2]
0.F15.B0
0.F15.B1
NONE
0
0
HEX_N5[2]
0
1
LV[6]
1
0
LV[18]
1
1
TERM_N:MUX.HEX_S6[3]
0.F7.B0
0.F7.B1
NONE
0
0
HEX_N5[3]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_N:MUX.HEX_S6[4]
0.F19.B0
0.F19.B1
NONE
0
0
HEX_N5[4]
0
1
LV[6]
1
0
LV[18]
1
1
TERM_N:MUX.HEX_S6[5]
0.F12.B0
0.F12.B1
NONE
0
0
HEX_N5[5]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_N:MUX.HEX_S6[6]
0.F4.B0
0.F4.B1
NONE
0
0
HEX_N5[6]
0
1
LV[6]
1
0
LV[18]
1
1
TERM_N:MUX.HEX_S6[7]
0.F16.B0
0.F16.B1
NONE
0
0
HEX_N5[7]
0
1
LV[12]
1
0
LV[0]
1
1
TERM_N:MUX.HEX_S6[8]
0.F11.B0
0.F11.B1
NONE
0
0
HEX_N5[8]
0
1
LV[6]
1
0
LV[18]
1
1
TERM_N:MUX.HEX_S6[9]
0.F3.B0
0.F3.B1
NONE
0
0
HEX_N5[9]
0
1
LV[12]
1
0
LV[0]
1
1