Terminator tiles

These tiles are placed at the edges of the device and deal with interconnect lines that go out-of-bounds. The associated bitstream tiles are shared with IOBS tiles and primitive data for corner tiles.

`TERM_W`

Located at the left edge of every interconnect row, this tile is 4×80 bits.

Tile TERM_W

Cells: 1

Switchbox TERM_W

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[0]
Bits		Destination
TERM[1][3]	TERM[1][2]	HEX_E1[0]
		Source
0	0	off
0	1	HEX_W0[0]
1	0	LH[7]
1	1	LH[19]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[1]
Bits		Destination
TERM[1][11]	TERM[1][10]	HEX_E1[1]
		Source
0	0	OUT_PCI[0]
0	1	HEX_W0[1]
1	0	LH[13]
1	1	LH[1]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[2]
Bits		Destination
TERM[1][19]	TERM[1][18]	HEX_E1[2]
		Source
0	0	off
0	1	HEX_W0[2]
1	0	LH[7]
1	1	LH[19]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[3]
Bits		Destination
TERM[1][27]	TERM[1][26]	HEX_E1[3]
		Source
0	0	off
0	1	HEX_W0[3]
1	0	LH[13]
1	1	LH[1]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[4]
Bits		Destination
TERM[1][35]	TERM[1][34]	HEX_E1[4]
		Source
0	0	off
0	1	HEX_W0[4]
1	0	LH[7]
1	1	LH[19]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[5]
Bits		Destination
TERM[1][43]	TERM[1][42]	HEX_E1[5]
		Source
0	0	off
0	1	HEX_W0[5]
1	0	LH[13]
1	1	LH[1]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[6]
Bits		Destination
TERM[1][51]	TERM[1][50]	HEX_E1[6]
		Source
0	0	off
0	1	HEX_W0[6]
1	0	LH[7]
1	1	LH[19]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[7]
Bits		Destination
TERM[1][59]	TERM[1][58]	HEX_E1[7]
		Source
0	0	off
0	1	HEX_W0[7]
1	0	LH[13]
1	1	LH[1]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[8]
Bits		Destination
TERM[1][67]	TERM[1][66]	HEX_E1[8]
		Source
0	0	off
0	1	HEX_W0[8]
1	0	LH[7]
1	1	LH[19]

virtex2 TERM_W switchbox TERM_W muxes HEX_E1[9]
Bits		Destination
TERM[1][75]	TERM[1][74]	HEX_E1[9]
		Source
0	0	off
0	1	HEX_W0[9]
1	0	LH[13]
1	1	LH[1]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[0]
Bits		Destination
TERM[0][3]	TERM[0][2]	HEX_E2[0]
		Source
0	0	off
0	1	HEX_W1[0]
1	0	LH[8]
1	1	LH[20]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[1]
Bits		Destination
TERM[0][11]	TERM[0][10]	HEX_E2[1]
		Source
0	0	OUT_PCI[1]
0	1	HEX_W1[1]
1	0	LH[14]
1	1	LH[2]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[2]
Bits		Destination
TERM[0][19]	TERM[0][18]	HEX_E2[2]
		Source
0	0	off
0	1	HEX_W1[2]
1	0	LH[8]
1	1	LH[20]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[3]
Bits		Destination
TERM[0][27]	TERM[0][26]	HEX_E2[3]
		Source
0	0	off
0	1	HEX_W1[3]
1	0	LH[14]
1	1	LH[2]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[4]
Bits		Destination
TERM[0][35]	TERM[0][34]	HEX_E2[4]
		Source
0	0	off
0	1	HEX_W1[4]
1	0	LH[8]
1	1	LH[20]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[5]
Bits		Destination
TERM[0][43]	TERM[0][42]	HEX_E2[5]
		Source
0	0	off
0	1	HEX_W1[5]
1	0	LH[14]
1	1	LH[2]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[6]
Bits		Destination
TERM[0][51]	TERM[0][50]	HEX_E2[6]
		Source
0	0	off
0	1	HEX_W1[6]
1	0	LH[8]
1	1	LH[20]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[7]
Bits		Destination
TERM[0][59]	TERM[0][58]	HEX_E2[7]
		Source
0	0	off
0	1	HEX_W1[7]
1	0	LH[14]
1	1	LH[2]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[8]
Bits		Destination
TERM[0][67]	TERM[0][66]	HEX_E2[8]
		Source
0	0	off
0	1	HEX_W1[8]
1	0	LH[8]
1	1	LH[20]

virtex2 TERM_W switchbox TERM_W muxes HEX_E2[9]
Bits		Destination
TERM[0][75]	TERM[0][74]	HEX_E2[9]
		Source
0	0	off
0	1	HEX_W1[9]
1	0	LH[14]
1	1	LH[2]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[0]
Bits		Destination
TERM[1][5]	TERM[1][4]	HEX_E3[0]
		Source
0	0	off
0	1	HEX_W2[0]
1	0	LH[9]
1	1	LH[21]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[1]
Bits		Destination
TERM[1][13]	TERM[1][12]	HEX_E3[1]
		Source
0	0	off
0	1	HEX_W2[1]
1	0	LH[15]
1	1	LH[3]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[2]
Bits		Destination
TERM[1][21]	TERM[1][20]	HEX_E3[2]
		Source
0	0	off
0	1	HEX_W2[2]
1	0	LH[9]
1	1	LH[21]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[3]
Bits		Destination
TERM[1][29]	TERM[1][28]	HEX_E3[3]
		Source
0	0	off
0	1	HEX_W2[3]
1	0	LH[15]
1	1	LH[3]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[4]
Bits		Destination
TERM[1][37]	TERM[1][36]	HEX_E3[4]
		Source
0	0	off
0	1	HEX_W2[4]
1	0	LH[9]
1	1	LH[21]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[5]
Bits		Destination
TERM[1][45]	TERM[1][44]	HEX_E3[5]
		Source
0	0	off
0	1	HEX_W2[5]
1	0	LH[15]
1	1	LH[3]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[6]
Bits		Destination
TERM[1][53]	TERM[1][52]	HEX_E3[6]
		Source
0	0	off
0	1	HEX_W2[6]
1	0	LH[9]
1	1	LH[21]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[7]
Bits		Destination
TERM[1][61]	TERM[1][60]	HEX_E3[7]
		Source
0	0	off
0	1	HEX_W2[7]
1	0	LH[15]
1	1	LH[3]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[8]
Bits		Destination
TERM[1][69]	TERM[1][68]	HEX_E3[8]
		Source
0	0	off
0	1	HEX_W2[8]
1	0	LH[9]
1	1	LH[21]

virtex2 TERM_W switchbox TERM_W muxes HEX_E3[9]
Bits		Destination
TERM[1][77]	TERM[1][76]	HEX_E3[9]
		Source
0	0	off
0	1	HEX_W2[9]
1	0	LH[15]
1	1	LH[3]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[0]
Bits		Destination
TERM[0][5]	TERM[0][4]	HEX_E4[0]
		Source
0	0	off
0	1	HEX_W3[0]
1	0	LH[10]
1	1	LH[22]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[1]
Bits		Destination
TERM[0][13]	TERM[0][12]	HEX_E4[1]
		Source
0	0	off
0	1	HEX_W3[1]
1	0	LH[16]
1	1	LH[4]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[2]
Bits		Destination
TERM[0][21]	TERM[0][20]	HEX_E4[2]
		Source
0	0	off
0	1	HEX_W3[2]
1	0	LH[10]
1	1	LH[22]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[3]
Bits		Destination
TERM[0][29]	TERM[0][28]	HEX_E4[3]
		Source
0	0	off
0	1	HEX_W3[3]
1	0	LH[16]
1	1	LH[4]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[4]
Bits		Destination
TERM[0][37]	TERM[0][36]	HEX_E4[4]
		Source
0	0	off
0	1	HEX_W3[4]
1	0	LH[10]
1	1	LH[22]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[5]
Bits		Destination
TERM[0][45]	TERM[0][44]	HEX_E4[5]
		Source
0	0	off
0	1	HEX_W3[5]
1	0	LH[16]
1	1	LH[4]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[6]
Bits		Destination
TERM[0][53]	TERM[0][52]	HEX_E4[6]
		Source
0	0	off
0	1	HEX_W3[6]
1	0	LH[10]
1	1	LH[22]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[7]
Bits		Destination
TERM[0][61]	TERM[0][60]	HEX_E4[7]
		Source
0	0	off
0	1	HEX_W3[7]
1	0	LH[16]
1	1	LH[4]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[8]
Bits		Destination
TERM[0][69]	TERM[0][68]	HEX_E4[8]
		Source
0	0	off
0	1	HEX_W3[8]
1	0	LH[10]
1	1	LH[22]

virtex2 TERM_W switchbox TERM_W muxes HEX_E4[9]
Bits		Destination
TERM[0][77]	TERM[0][76]	HEX_E4[9]
		Source
0	0	off
0	1	HEX_W3[9]
1	0	LH[16]
1	1	LH[4]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[0]
Bits		Destination
TERM[1][7]	TERM[1][6]	HEX_E5[0]
		Source
0	0	off
0	1	HEX_W4[0]
1	0	LH[11]
1	1	LH[23]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[1]
Bits		Destination
TERM[1][15]	TERM[1][14]	HEX_E5[1]
		Source
0	0	off
0	1	HEX_W4[1]
1	0	LH[17]
1	1	LH[5]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[2]
Bits		Destination
TERM[1][23]	TERM[1][22]	HEX_E5[2]
		Source
0	0	off
0	1	HEX_W4[2]
1	0	LH[11]
1	1	LH[23]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[3]
Bits		Destination
TERM[1][31]	TERM[1][30]	HEX_E5[3]
		Source
0	0	off
0	1	HEX_W4[3]
1	0	LH[17]
1	1	LH[5]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[4]
Bits		Destination
TERM[1][39]	TERM[1][38]	HEX_E5[4]
		Source
0	0	off
0	1	HEX_W4[4]
1	0	LH[11]
1	1	LH[23]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[5]
Bits		Destination
TERM[1][47]	TERM[1][46]	HEX_E5[5]
		Source
0	0	off
0	1	HEX_W4[5]
1	0	LH[17]
1	1	LH[5]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[6]
Bits		Destination
TERM[1][55]	TERM[1][54]	HEX_E5[6]
		Source
0	0	off
0	1	HEX_W4[6]
1	0	LH[11]
1	1	LH[23]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[7]
Bits		Destination
TERM[1][63]	TERM[1][62]	HEX_E5[7]
		Source
0	0	off
0	1	HEX_W4[7]
1	0	LH[17]
1	1	LH[5]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[8]
Bits		Destination
TERM[1][71]	TERM[1][70]	HEX_E5[8]
		Source
0	0	off
0	1	HEX_W4[8]
1	0	LH[11]
1	1	LH[23]

virtex2 TERM_W switchbox TERM_W muxes HEX_E5[9]
Bits		Destination
TERM[1][79]	TERM[1][78]	HEX_E5[9]
		Source
0	0	off
0	1	HEX_W4[9]
1	0	LH[17]
1	1	LH[5]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[0]
Bits		Destination
TERM[0][7]	TERM[0][6]	HEX_E6[0]
		Source
0	0	off
0	1	HEX_W5[0]
1	0	LH[12]
1	1	LH[0]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[1]
Bits		Destination
TERM[0][15]	TERM[0][14]	HEX_E6[1]
		Source
0	0	off
0	1	HEX_W5[1]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[2]
Bits		Destination
TERM[0][23]	TERM[0][22]	HEX_E6[2]
		Source
0	0	off
0	1	HEX_W5[2]
1	0	LH[12]
1	1	LH[0]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[3]
Bits		Destination
TERM[0][31]	TERM[0][30]	HEX_E6[3]
		Source
0	0	off
0	1	HEX_W5[3]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[4]
Bits		Destination
TERM[0][39]	TERM[0][38]	HEX_E6[4]
		Source
0	0	off
0	1	HEX_W5[4]
1	0	LH[12]
1	1	LH[0]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[5]
Bits		Destination
TERM[0][47]	TERM[0][46]	HEX_E6[5]
		Source
0	0	off
0	1	HEX_W5[5]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[6]
Bits		Destination
TERM[0][55]	TERM[0][54]	HEX_E6[6]
		Source
0	0	off
0	1	HEX_W5[6]
1	0	LH[12]
1	1	LH[0]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[7]
Bits		Destination
TERM[0][63]	TERM[0][62]	HEX_E6[7]
		Source
0	0	off
0	1	HEX_W5[7]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[8]
Bits		Destination
TERM[0][71]	TERM[0][70]	HEX_E6[8]
		Source
0	0	off
0	1	HEX_W5[8]
1	0	LH[12]
1	1	LH[0]

virtex2 TERM_W switchbox TERM_W muxes HEX_E6[9]
Bits		Destination
TERM[0][79]	TERM[0][78]	HEX_E6[9]
		Source
0	0	off
0	1	HEX_W5[9]
1	0	LH[18]
1	1	LH[6]

Bitstream

virtex2 TERM_W rect TERM
Bit	Frame
Bit	F3	F2	F1	F0
B79	-	-	TERM_W: mux HEX_E5[9] bit 1	TERM_W: mux HEX_E6[9] bit 1
B78	-	-	TERM_W: mux HEX_E5[9] bit 0	TERM_W: mux HEX_E6[9] bit 0
B77	-	-	TERM_W: mux HEX_E3[9] bit 1	TERM_W: mux HEX_E4[9] bit 1
B76	-	-	TERM_W: mux HEX_E3[9] bit 0	TERM_W: mux HEX_E4[9] bit 0
B75	-	-	TERM_W: mux HEX_E1[9] bit 1	TERM_W: mux HEX_E2[9] bit 1
B74	-	-	TERM_W: mux HEX_E1[9] bit 0	TERM_W: mux HEX_E2[9] bit 0
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	TERM_W: mux HEX_E5[8] bit 1	TERM_W: mux HEX_E6[8] bit 1
B70	-	-	TERM_W: mux HEX_E5[8] bit 0	TERM_W: mux HEX_E6[8] bit 0
B69	-	-	TERM_W: mux HEX_E3[8] bit 1	TERM_W: mux HEX_E4[8] bit 1
B68	-	-	TERM_W: mux HEX_E3[8] bit 0	TERM_W: mux HEX_E4[8] bit 0
B67	-	-	TERM_W: mux HEX_E1[8] bit 1	TERM_W: mux HEX_E2[8] bit 1
B66	-	-	TERM_W: mux HEX_E1[8] bit 0	TERM_W: mux HEX_E2[8] bit 0
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	TERM_W: mux HEX_E5[7] bit 1	TERM_W: mux HEX_E6[7] bit 1
B62	-	-	TERM_W: mux HEX_E5[7] bit 0	TERM_W: mux HEX_E6[7] bit 0
B61	-	-	TERM_W: mux HEX_E3[7] bit 1	TERM_W: mux HEX_E4[7] bit 1
B60	-	-	TERM_W: mux HEX_E3[7] bit 0	TERM_W: mux HEX_E4[7] bit 0
B59	-	-	TERM_W: mux HEX_E1[7] bit 1	TERM_W: mux HEX_E2[7] bit 1
B58	-	-	TERM_W: mux HEX_E1[7] bit 0	TERM_W: mux HEX_E2[7] bit 0
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	TERM_W: mux HEX_E5[6] bit 1	TERM_W: mux HEX_E6[6] bit 1
B54	-	-	TERM_W: mux HEX_E5[6] bit 0	TERM_W: mux HEX_E6[6] bit 0
B53	-	-	TERM_W: mux HEX_E3[6] bit 1	TERM_W: mux HEX_E4[6] bit 1
B52	-	-	TERM_W: mux HEX_E3[6] bit 0	TERM_W: mux HEX_E4[6] bit 0
B51	-	-	TERM_W: mux HEX_E1[6] bit 1	TERM_W: mux HEX_E2[6] bit 1
B50	-	-	TERM_W: mux HEX_E1[6] bit 0	TERM_W: mux HEX_E2[6] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	TERM_W: mux HEX_E5[5] bit 1	TERM_W: mux HEX_E6[5] bit 1
B46	-	-	TERM_W: mux HEX_E5[5] bit 0	TERM_W: mux HEX_E6[5] bit 0
B45	-	-	TERM_W: mux HEX_E3[5] bit 1	TERM_W: mux HEX_E4[5] bit 1
B44	-	-	TERM_W: mux HEX_E3[5] bit 0	TERM_W: mux HEX_E4[5] bit 0
B43	-	-	TERM_W: mux HEX_E1[5] bit 1	TERM_W: mux HEX_E2[5] bit 1
B42	-	-	TERM_W: mux HEX_E1[5] bit 0	TERM_W: mux HEX_E2[5] bit 0
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	TERM_W: mux HEX_E5[4] bit 1	TERM_W: mux HEX_E6[4] bit 1
B38	-	-	TERM_W: mux HEX_E5[4] bit 0	TERM_W: mux HEX_E6[4] bit 0
B37	-	-	TERM_W: mux HEX_E3[4] bit 1	TERM_W: mux HEX_E4[4] bit 1
B36	-	-	TERM_W: mux HEX_E3[4] bit 0	TERM_W: mux HEX_E4[4] bit 0
B35	-	-	TERM_W: mux HEX_E1[4] bit 1	TERM_W: mux HEX_E2[4] bit 1
B34	-	-	TERM_W: mux HEX_E1[4] bit 0	TERM_W: mux HEX_E2[4] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	TERM_W: mux HEX_E5[3] bit 1	TERM_W: mux HEX_E6[3] bit 1
B30	-	-	TERM_W: mux HEX_E5[3] bit 0	TERM_W: mux HEX_E6[3] bit 0
B29	-	-	TERM_W: mux HEX_E3[3] bit 1	TERM_W: mux HEX_E4[3] bit 1
B28	-	-	TERM_W: mux HEX_E3[3] bit 0	TERM_W: mux HEX_E4[3] bit 0
B27	-	-	TERM_W: mux HEX_E1[3] bit 1	TERM_W: mux HEX_E2[3] bit 1
B26	-	-	TERM_W: mux HEX_E1[3] bit 0	TERM_W: mux HEX_E2[3] bit 0
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	TERM_W: mux HEX_E5[2] bit 1	TERM_W: mux HEX_E6[2] bit 1
B22	-	-	TERM_W: mux HEX_E5[2] bit 0	TERM_W: mux HEX_E6[2] bit 0
B21	-	-	TERM_W: mux HEX_E3[2] bit 1	TERM_W: mux HEX_E4[2] bit 1
B20	-	-	TERM_W: mux HEX_E3[2] bit 0	TERM_W: mux HEX_E4[2] bit 0
B19	-	-	TERM_W: mux HEX_E1[2] bit 1	TERM_W: mux HEX_E2[2] bit 1
B18	-	-	TERM_W: mux HEX_E1[2] bit 0	TERM_W: mux HEX_E2[2] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	TERM_W: mux HEX_E5[1] bit 1	TERM_W: mux HEX_E6[1] bit 1
B14	-	-	TERM_W: mux HEX_E5[1] bit 0	TERM_W: mux HEX_E6[1] bit 0
B13	-	-	TERM_W: mux HEX_E3[1] bit 1	TERM_W: mux HEX_E4[1] bit 1
B12	-	-	TERM_W: mux HEX_E3[1] bit 0	TERM_W: mux HEX_E4[1] bit 0
B11	-	-	TERM_W: mux HEX_E1[1] bit 1	TERM_W: mux HEX_E2[1] bit 1
B10	-	-	TERM_W: mux HEX_E1[1] bit 0	TERM_W: mux HEX_E2[1] bit 0
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	TERM_W: mux HEX_E5[0] bit 1	TERM_W: mux HEX_E6[0] bit 1
B6	-	-	TERM_W: mux HEX_E5[0] bit 0	TERM_W: mux HEX_E6[0] bit 0
B5	-	-	TERM_W: mux HEX_E3[0] bit 1	TERM_W: mux HEX_E4[0] bit 1
B4	-	-	TERM_W: mux HEX_E3[0] bit 0	TERM_W: mux HEX_E4[0] bit 0
B3	-	-	TERM_W: mux HEX_E1[0] bit 1	TERM_W: mux HEX_E2[0] bit 1
B2	-	-	TERM_W: mux HEX_E1[0] bit 0	TERM_W: mux HEX_E2[0] bit 0
B1	-	-	-	-
B0	-	-	-	-

`TERM_E`

Located at the right edge of every interconnect row, this tile is 4×80 bits.

Tile TERM_E

Cells: 1

Switchbox TERM_E

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[0]
Bits		Destination
TERM[1][3]	TERM[1][2]	HEX_W1[0]
		Source
0	0	off
0	1	HEX_E0[0]
1	0	LH[5]
1	1	LH[17]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[1]
Bits		Destination
TERM[1][11]	TERM[1][10]	HEX_W1[1]
		Source
0	0	off
0	1	HEX_E0[1]
1	0	LH[23]
1	1	LH[11]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[2]
Bits		Destination
TERM[1][19]	TERM[1][18]	HEX_W1[2]
		Source
0	0	off
0	1	HEX_E0[2]
1	0	LH[5]
1	1	LH[17]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[3]
Bits		Destination
TERM[1][27]	TERM[1][26]	HEX_W1[3]
		Source
0	0	off
0	1	HEX_E0[3]
1	0	LH[23]
1	1	LH[11]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[4]
Bits		Destination
TERM[1][35]	TERM[1][34]	HEX_W1[4]
		Source
0	0	off
0	1	HEX_E0[4]
1	0	LH[5]
1	1	LH[17]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[5]
Bits		Destination
TERM[1][43]	TERM[1][42]	HEX_W1[5]
		Source
0	0	off
0	1	HEX_E0[5]
1	0	LH[23]
1	1	LH[11]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[6]
Bits		Destination
TERM[1][51]	TERM[1][50]	HEX_W1[6]
		Source
0	0	off
0	1	HEX_E0[6]
1	0	LH[5]
1	1	LH[17]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[7]
Bits		Destination
TERM[1][59]	TERM[1][58]	HEX_W1[7]
		Source
0	0	OUT_PCI[0]
0	1	HEX_E0[7]
1	0	LH[23]
1	1	LH[11]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[8]
Bits		Destination
TERM[1][67]	TERM[1][66]	HEX_W1[8]
		Source
0	0	off
0	1	HEX_E0[8]
1	0	LH[5]
1	1	LH[17]

virtex2 TERM_E switchbox TERM_E muxes HEX_W1[9]
Bits		Destination
TERM[1][75]	TERM[1][74]	HEX_W1[9]
		Source
0	0	off
0	1	HEX_E0[9]
1	0	LH[23]
1	1	LH[11]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[0]
Bits		Destination
TERM[0][3]	TERM[0][2]	HEX_W2[0]
		Source
0	0	off
0	1	HEX_E1[0]
1	0	LH[4]
1	1	LH[16]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[1]
Bits		Destination
TERM[0][11]	TERM[0][10]	HEX_W2[1]
		Source
0	0	off
0	1	HEX_E1[1]
1	0	LH[22]
1	1	LH[10]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[2]
Bits		Destination
TERM[0][19]	TERM[0][18]	HEX_W2[2]
		Source
0	0	off
0	1	HEX_E1[2]
1	0	LH[4]
1	1	LH[16]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[3]
Bits		Destination
TERM[0][27]	TERM[0][26]	HEX_W2[3]
		Source
0	0	off
0	1	HEX_E1[3]
1	0	LH[22]
1	1	LH[10]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[4]
Bits		Destination
TERM[0][35]	TERM[0][34]	HEX_W2[4]
		Source
0	0	off
0	1	HEX_E1[4]
1	0	LH[4]
1	1	LH[16]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[5]
Bits		Destination
TERM[0][43]	TERM[0][42]	HEX_W2[5]
		Source
0	0	off
0	1	HEX_E1[5]
1	0	LH[22]
1	1	LH[10]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[6]
Bits		Destination
TERM[0][51]	TERM[0][50]	HEX_W2[6]
		Source
0	0	off
0	1	HEX_E1[6]
1	0	LH[4]
1	1	LH[16]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[7]
Bits		Destination
TERM[0][59]	TERM[0][58]	HEX_W2[7]
		Source
0	0	OUT_PCI[1]
0	1	HEX_E1[7]
1	0	LH[22]
1	1	LH[10]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[8]
Bits		Destination
TERM[0][67]	TERM[0][66]	HEX_W2[8]
		Source
0	0	off
0	1	HEX_E1[8]
1	0	LH[4]
1	1	LH[16]

virtex2 TERM_E switchbox TERM_E muxes HEX_W2[9]
Bits		Destination
TERM[0][75]	TERM[0][74]	HEX_W2[9]
		Source
0	0	off
0	1	HEX_E1[9]
1	0	LH[22]
1	1	LH[10]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[0]
Bits		Destination
TERM[1][5]	TERM[1][4]	HEX_W3[0]
		Source
0	0	off
0	1	HEX_E2[0]
1	0	LH[3]
1	1	LH[15]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[1]
Bits		Destination
TERM[1][13]	TERM[1][12]	HEX_W3[1]
		Source
0	0	off
0	1	HEX_E2[1]
1	0	LH[21]
1	1	LH[9]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[2]
Bits		Destination
TERM[1][21]	TERM[1][20]	HEX_W3[2]
		Source
0	0	off
0	1	HEX_E2[2]
1	0	LH[3]
1	1	LH[15]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[3]
Bits		Destination
TERM[1][29]	TERM[1][28]	HEX_W3[3]
		Source
0	0	off
0	1	HEX_E2[3]
1	0	LH[21]
1	1	LH[9]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[4]
Bits		Destination
TERM[1][37]	TERM[1][36]	HEX_W3[4]
		Source
0	0	off
0	1	HEX_E2[4]
1	0	LH[3]
1	1	LH[15]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[5]
Bits		Destination
TERM[1][45]	TERM[1][44]	HEX_W3[5]
		Source
0	0	off
0	1	HEX_E2[5]
1	0	LH[21]
1	1	LH[9]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[6]
Bits		Destination
TERM[1][53]	TERM[1][52]	HEX_W3[6]
		Source
0	0	off
0	1	HEX_E2[6]
1	0	LH[3]
1	1	LH[15]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[7]
Bits		Destination
TERM[1][61]	TERM[1][60]	HEX_W3[7]
		Source
0	0	off
0	1	HEX_E2[7]
1	0	LH[21]
1	1	LH[9]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[8]
Bits		Destination
TERM[1][69]	TERM[1][68]	HEX_W3[8]
		Source
0	0	off
0	1	HEX_E2[8]
1	0	LH[3]
1	1	LH[15]

virtex2 TERM_E switchbox TERM_E muxes HEX_W3[9]
Bits		Destination
TERM[1][77]	TERM[1][76]	HEX_W3[9]
		Source
0	0	off
0	1	HEX_E2[9]
1	0	LH[21]
1	1	LH[9]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[0]
Bits		Destination
TERM[0][5]	TERM[0][4]	HEX_W4[0]
		Source
0	0	off
0	1	HEX_E3[0]
1	0	LH[2]
1	1	LH[14]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[1]
Bits		Destination
TERM[0][13]	TERM[0][12]	HEX_W4[1]
		Source
0	0	off
0	1	HEX_E3[1]
1	0	LH[20]
1	1	LH[8]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[2]
Bits		Destination
TERM[0][21]	TERM[0][20]	HEX_W4[2]
		Source
0	0	off
0	1	HEX_E3[2]
1	0	LH[2]
1	1	LH[14]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[3]
Bits		Destination
TERM[0][29]	TERM[0][28]	HEX_W4[3]
		Source
0	0	off
0	1	HEX_E3[3]
1	0	LH[20]
1	1	LH[8]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[4]
Bits		Destination
TERM[0][37]	TERM[0][36]	HEX_W4[4]
		Source
0	0	off
0	1	HEX_E3[4]
1	0	LH[2]
1	1	LH[14]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[5]
Bits		Destination
TERM[0][45]	TERM[0][44]	HEX_W4[5]
		Source
0	0	off
0	1	HEX_E3[5]
1	0	LH[20]
1	1	LH[8]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[6]
Bits		Destination
TERM[0][53]	TERM[0][52]	HEX_W4[6]
		Source
0	0	off
0	1	HEX_E3[6]
1	0	LH[2]
1	1	LH[14]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[7]
Bits		Destination
TERM[0][61]	TERM[0][60]	HEX_W4[7]
		Source
0	0	off
0	1	HEX_E3[7]
1	0	LH[20]
1	1	LH[8]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[8]
Bits		Destination
TERM[0][69]	TERM[0][68]	HEX_W4[8]
		Source
0	0	off
0	1	HEX_E3[8]
1	0	LH[2]
1	1	LH[14]

virtex2 TERM_E switchbox TERM_E muxes HEX_W4[9]
Bits		Destination
TERM[0][77]	TERM[0][76]	HEX_W4[9]
		Source
0	0	off
0	1	HEX_E3[9]
1	0	LH[20]
1	1	LH[8]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[0]
Bits		Destination
TERM[1][7]	TERM[1][6]	HEX_W5[0]
		Source
0	0	off
0	1	HEX_E4[0]
1	0	LH[1]
1	1	LH[13]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[1]
Bits		Destination
TERM[1][15]	TERM[1][14]	HEX_W5[1]
		Source
0	0	off
0	1	HEX_E4[1]
1	0	LH[19]
1	1	LH[7]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[2]
Bits		Destination
TERM[1][23]	TERM[1][22]	HEX_W5[2]
		Source
0	0	off
0	1	HEX_E4[2]
1	0	LH[1]
1	1	LH[13]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[3]
Bits		Destination
TERM[1][31]	TERM[1][30]	HEX_W5[3]
		Source
0	0	off
0	1	HEX_E4[3]
1	0	LH[19]
1	1	LH[7]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[4]
Bits		Destination
TERM[1][39]	TERM[1][38]	HEX_W5[4]
		Source
0	0	off
0	1	HEX_E4[4]
1	0	LH[1]
1	1	LH[13]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[5]
Bits		Destination
TERM[1][47]	TERM[1][46]	HEX_W5[5]
		Source
0	0	off
0	1	HEX_E4[5]
1	0	LH[19]
1	1	LH[7]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[6]
Bits		Destination
TERM[1][55]	TERM[1][54]	HEX_W5[6]
		Source
0	0	off
0	1	HEX_E4[6]
1	0	LH[1]
1	1	LH[13]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[7]
Bits		Destination
TERM[1][63]	TERM[1][62]	HEX_W5[7]
		Source
0	0	off
0	1	HEX_E4[7]
1	0	LH[19]
1	1	LH[7]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[8]
Bits		Destination
TERM[1][71]	TERM[1][70]	HEX_W5[8]
		Source
0	0	off
0	1	HEX_E4[8]
1	0	LH[1]
1	1	LH[13]

virtex2 TERM_E switchbox TERM_E muxes HEX_W5[9]
Bits		Destination
TERM[1][79]	TERM[1][78]	HEX_W5[9]
		Source
0	0	off
0	1	HEX_E4[9]
1	0	LH[19]
1	1	LH[7]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[0]
Bits		Destination
TERM[0][7]	TERM[0][6]	HEX_W6[0]
		Source
0	0	off
0	1	HEX_E5[0]
1	0	LH[0]
1	1	LH[12]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[1]
Bits		Destination
TERM[0][15]	TERM[0][14]	HEX_W6[1]
		Source
0	0	off
0	1	HEX_E5[1]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[2]
Bits		Destination
TERM[0][23]	TERM[0][22]	HEX_W6[2]
		Source
0	0	off
0	1	HEX_E5[2]
1	0	LH[0]
1	1	LH[12]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[3]
Bits		Destination
TERM[0][31]	TERM[0][30]	HEX_W6[3]
		Source
0	0	off
0	1	HEX_E5[3]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[4]
Bits		Destination
TERM[0][39]	TERM[0][38]	HEX_W6[4]
		Source
0	0	off
0	1	HEX_E5[4]
1	0	LH[0]
1	1	LH[12]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[5]
Bits		Destination
TERM[0][47]	TERM[0][46]	HEX_W6[5]
		Source
0	0	off
0	1	HEX_E5[5]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[6]
Bits		Destination
TERM[0][55]	TERM[0][54]	HEX_W6[6]
		Source
0	0	off
0	1	HEX_E5[6]
1	0	LH[0]
1	1	LH[12]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[7]
Bits		Destination
TERM[0][63]	TERM[0][62]	HEX_W6[7]
		Source
0	0	off
0	1	HEX_E5[7]
1	0	LH[18]
1	1	LH[6]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[8]
Bits		Destination
TERM[0][71]	TERM[0][70]	HEX_W6[8]
		Source
0	0	off
0	1	HEX_E5[8]
1	0	LH[0]
1	1	LH[12]

virtex2 TERM_E switchbox TERM_E muxes HEX_W6[9]
Bits		Destination
TERM[0][79]	TERM[0][78]	HEX_W6[9]
		Source
0	0	off
0	1	HEX_E5[9]
1	0	LH[18]
1	1	LH[6]

Bitstream

virtex2 TERM_E rect TERM
Bit	Frame
Bit	F3	F2	F1	F0
B79	-	-	TERM_E: mux HEX_W5[9] bit 1	TERM_E: mux HEX_W6[9] bit 1
B78	-	-	TERM_E: mux HEX_W5[9] bit 0	TERM_E: mux HEX_W6[9] bit 0
B77	-	-	TERM_E: mux HEX_W3[9] bit 1	TERM_E: mux HEX_W4[9] bit 1
B76	-	-	TERM_E: mux HEX_W3[9] bit 0	TERM_E: mux HEX_W4[9] bit 0
B75	-	-	TERM_E: mux HEX_W1[9] bit 1	TERM_E: mux HEX_W2[9] bit 1
B74	-	-	TERM_E: mux HEX_W1[9] bit 0	TERM_E: mux HEX_W2[9] bit 0
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	TERM_E: mux HEX_W5[8] bit 1	TERM_E: mux HEX_W6[8] bit 1
B70	-	-	TERM_E: mux HEX_W5[8] bit 0	TERM_E: mux HEX_W6[8] bit 0
B69	-	-	TERM_E: mux HEX_W3[8] bit 1	TERM_E: mux HEX_W4[8] bit 1
B68	-	-	TERM_E: mux HEX_W3[8] bit 0	TERM_E: mux HEX_W4[8] bit 0
B67	-	-	TERM_E: mux HEX_W1[8] bit 1	TERM_E: mux HEX_W2[8] bit 1
B66	-	-	TERM_E: mux HEX_W1[8] bit 0	TERM_E: mux HEX_W2[8] bit 0
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	TERM_E: mux HEX_W5[7] bit 1	TERM_E: mux HEX_W6[7] bit 1
B62	-	-	TERM_E: mux HEX_W5[7] bit 0	TERM_E: mux HEX_W6[7] bit 0
B61	-	-	TERM_E: mux HEX_W3[7] bit 1	TERM_E: mux HEX_W4[7] bit 1
B60	-	-	TERM_E: mux HEX_W3[7] bit 0	TERM_E: mux HEX_W4[7] bit 0
B59	-	-	TERM_E: mux HEX_W1[7] bit 1	TERM_E: mux HEX_W2[7] bit 1
B58	-	-	TERM_E: mux HEX_W1[7] bit 0	TERM_E: mux HEX_W2[7] bit 0
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	TERM_E: mux HEX_W5[6] bit 1	TERM_E: mux HEX_W6[6] bit 1
B54	-	-	TERM_E: mux HEX_W5[6] bit 0	TERM_E: mux HEX_W6[6] bit 0
B53	-	-	TERM_E: mux HEX_W3[6] bit 1	TERM_E: mux HEX_W4[6] bit 1
B52	-	-	TERM_E: mux HEX_W3[6] bit 0	TERM_E: mux HEX_W4[6] bit 0
B51	-	-	TERM_E: mux HEX_W1[6] bit 1	TERM_E: mux HEX_W2[6] bit 1
B50	-	-	TERM_E: mux HEX_W1[6] bit 0	TERM_E: mux HEX_W2[6] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	TERM_E: mux HEX_W5[5] bit 1	TERM_E: mux HEX_W6[5] bit 1
B46	-	-	TERM_E: mux HEX_W5[5] bit 0	TERM_E: mux HEX_W6[5] bit 0
B45	-	-	TERM_E: mux HEX_W3[5] bit 1	TERM_E: mux HEX_W4[5] bit 1
B44	-	-	TERM_E: mux HEX_W3[5] bit 0	TERM_E: mux HEX_W4[5] bit 0
B43	-	-	TERM_E: mux HEX_W1[5] bit 1	TERM_E: mux HEX_W2[5] bit 1
B42	-	-	TERM_E: mux HEX_W1[5] bit 0	TERM_E: mux HEX_W2[5] bit 0
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	TERM_E: mux HEX_W5[4] bit 1	TERM_E: mux HEX_W6[4] bit 1
B38	-	-	TERM_E: mux HEX_W5[4] bit 0	TERM_E: mux HEX_W6[4] bit 0
B37	-	-	TERM_E: mux HEX_W3[4] bit 1	TERM_E: mux HEX_W4[4] bit 1
B36	-	-	TERM_E: mux HEX_W3[4] bit 0	TERM_E: mux HEX_W4[4] bit 0
B35	-	-	TERM_E: mux HEX_W1[4] bit 1	TERM_E: mux HEX_W2[4] bit 1
B34	-	-	TERM_E: mux HEX_W1[4] bit 0	TERM_E: mux HEX_W2[4] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	TERM_E: mux HEX_W5[3] bit 1	TERM_E: mux HEX_W6[3] bit 1
B30	-	-	TERM_E: mux HEX_W5[3] bit 0	TERM_E: mux HEX_W6[3] bit 0
B29	-	-	TERM_E: mux HEX_W3[3] bit 1	TERM_E: mux HEX_W4[3] bit 1
B28	-	-	TERM_E: mux HEX_W3[3] bit 0	TERM_E: mux HEX_W4[3] bit 0
B27	-	-	TERM_E: mux HEX_W1[3] bit 1	TERM_E: mux HEX_W2[3] bit 1
B26	-	-	TERM_E: mux HEX_W1[3] bit 0	TERM_E: mux HEX_W2[3] bit 0
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	TERM_E: mux HEX_W5[2] bit 1	TERM_E: mux HEX_W6[2] bit 1
B22	-	-	TERM_E: mux HEX_W5[2] bit 0	TERM_E: mux HEX_W6[2] bit 0
B21	-	-	TERM_E: mux HEX_W3[2] bit 1	TERM_E: mux HEX_W4[2] bit 1
B20	-	-	TERM_E: mux HEX_W3[2] bit 0	TERM_E: mux HEX_W4[2] bit 0
B19	-	-	TERM_E: mux HEX_W1[2] bit 1	TERM_E: mux HEX_W2[2] bit 1
B18	-	-	TERM_E: mux HEX_W1[2] bit 0	TERM_E: mux HEX_W2[2] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	TERM_E: mux HEX_W5[1] bit 1	TERM_E: mux HEX_W6[1] bit 1
B14	-	-	TERM_E: mux HEX_W5[1] bit 0	TERM_E: mux HEX_W6[1] bit 0
B13	-	-	TERM_E: mux HEX_W3[1] bit 1	TERM_E: mux HEX_W4[1] bit 1
B12	-	-	TERM_E: mux HEX_W3[1] bit 0	TERM_E: mux HEX_W4[1] bit 0
B11	-	-	TERM_E: mux HEX_W1[1] bit 1	TERM_E: mux HEX_W2[1] bit 1
B10	-	-	TERM_E: mux HEX_W1[1] bit 0	TERM_E: mux HEX_W2[1] bit 0
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	TERM_E: mux HEX_W5[0] bit 1	TERM_E: mux HEX_W6[0] bit 1
B6	-	-	TERM_E: mux HEX_W5[0] bit 0	TERM_E: mux HEX_W6[0] bit 0
B5	-	-	TERM_E: mux HEX_W3[0] bit 1	TERM_E: mux HEX_W4[0] bit 1
B4	-	-	TERM_E: mux HEX_W3[0] bit 0	TERM_E: mux HEX_W4[0] bit 0
B3	-	-	TERM_E: mux HEX_W1[0] bit 1	TERM_E: mux HEX_W2[0] bit 1
B2	-	-	TERM_E: mux HEX_W1[0] bit 0	TERM_E: mux HEX_W2[0] bit 0
B1	-	-	-	-
B0	-	-	-	-

`TERM_S`

Located at the bottom edge of every interconnect column, this tile is 22×12 bits.

Tile TERM_S

Cells: 1

Switchbox TERM_S

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[0]
Bits		Destination
TERM[9][4]	TERM[9][5]	HEX_N1[0]
		Source
0	0	off
0	1	HEX_S0[0]
1	0	LV[23]
1	1	LV[11]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[1]
Bits		Destination
TERM[21][4]	TERM[21][5]	HEX_N1[1]
		Source
0	0	off
0	1	HEX_S0[1]
1	0	LV[17]
1	1	LV[5]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[2]
Bits		Destination
TERM[14][4]	TERM[14][5]	HEX_N1[2]
		Source
0	0	off
0	1	HEX_S0[2]
1	0	LV[23]
1	1	LV[11]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[3]
Bits		Destination
TERM[6][4]	TERM[6][5]	HEX_N1[3]
		Source
0	0	off
0	1	HEX_S0[3]
1	0	LV[17]
1	1	LV[5]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[4]
Bits		Destination
TERM[18][4]	TERM[18][5]	HEX_N1[4]
		Source
0	0	off
0	1	HEX_S0[4]
1	0	LV[23]
1	1	LV[11]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[5]
Bits		Destination
TERM[13][4]	TERM[13][5]	HEX_N1[5]
		Source
0	0	off
0	1	HEX_S0[5]
1	0	LV[17]
1	1	LV[5]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[6]
Bits		Destination
TERM[5][4]	TERM[5][5]	HEX_N1[6]
		Source
0	0	off
0	1	HEX_S0[6]
1	0	LV[23]
1	1	LV[11]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[7]
Bits		Destination
TERM[17][4]	TERM[17][5]	HEX_N1[7]
		Source
0	0	off
0	1	HEX_S0[7]
1	0	LV[17]
1	1	LV[5]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[8]
Bits		Destination
TERM[10][4]	TERM[10][5]	HEX_N1[8]
		Source
0	0	off
0	1	HEX_S0[8]
1	0	LV[23]
1	1	LV[11]

virtex2 TERM_S switchbox TERM_S muxes HEX_N1[9]
Bits		Destination
TERM[0][4]	TERM[0][5]	HEX_N1[9]
		Source
0	0	off
0	1	HEX_S0[9]
1	0	LV[17]
1	1	LV[5]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[0]
Bits		Destination
TERM[8][4]	TERM[8][5]	HEX_N2[0]
		Source
0	0	off
0	1	HEX_S1[0]
1	0	LV[22]
1	1	LV[10]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[1]
Bits		Destination
TERM[20][4]	TERM[20][5]	HEX_N2[1]
		Source
0	0	off
0	1	HEX_S1[1]
1	0	LV[16]
1	1	LV[4]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[2]
Bits		Destination
TERM[15][4]	TERM[15][5]	HEX_N2[2]
		Source
0	0	off
0	1	HEX_S1[2]
1	0	LV[22]
1	1	LV[10]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[3]
Bits		Destination
TERM[7][4]	TERM[7][5]	HEX_N2[3]
		Source
0	0	off
0	1	HEX_S1[3]
1	0	LV[16]
1	1	LV[4]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[4]
Bits		Destination
TERM[19][4]	TERM[19][5]	HEX_N2[4]
		Source
0	0	off
0	1	HEX_S1[4]
1	0	LV[22]
1	1	LV[10]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[5]
Bits		Destination
TERM[12][4]	TERM[12][5]	HEX_N2[5]
		Source
0	0	off
0	1	HEX_S1[5]
1	0	LV[16]
1	1	LV[4]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[6]
Bits		Destination
TERM[4][4]	TERM[4][5]	HEX_N2[6]
		Source
0	0	off
0	1	HEX_S1[6]
1	0	LV[22]
1	1	LV[10]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[7]
Bits		Destination
TERM[16][4]	TERM[16][5]	HEX_N2[7]
		Source
0	0	off
0	1	HEX_S1[7]
1	0	LV[16]
1	1	LV[4]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[8]
Bits		Destination
TERM[11][4]	TERM[11][5]	HEX_N2[8]
		Source
0	0	off
0	1	HEX_S1[8]
1	0	LV[22]
1	1	LV[10]

virtex2 TERM_S switchbox TERM_S muxes HEX_N2[9]
Bits		Destination
TERM[3][4]	TERM[3][5]	HEX_N2[9]
		Source
0	0	off
0	1	HEX_S1[9]
1	0	LV[16]
1	1	LV[4]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[0]
Bits		Destination
TERM[9][2]	TERM[9][3]	HEX_N3[0]
		Source
0	0	off
0	1	HEX_S2[0]
1	0	LV[21]
1	1	LV[9]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[1]
Bits		Destination
TERM[21][2]	TERM[21][3]	HEX_N3[1]
		Source
0	0	off
0	1	HEX_S2[1]
1	0	LV[15]
1	1	LV[3]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[2]
Bits		Destination
TERM[14][2]	TERM[14][3]	HEX_N3[2]
		Source
0	0	off
0	1	HEX_S2[2]
1	0	LV[21]
1	1	LV[9]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[3]
Bits		Destination
TERM[6][2]	TERM[6][3]	HEX_N3[3]
		Source
0	0	off
0	1	HEX_S2[3]
1	0	LV[15]
1	1	LV[3]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[4]
Bits		Destination
TERM[18][2]	TERM[18][3]	HEX_N3[4]
		Source
0	0	off
0	1	HEX_S2[4]
1	0	LV[21]
1	1	LV[9]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[5]
Bits		Destination
TERM[13][2]	TERM[13][3]	HEX_N3[5]
		Source
0	0	off
0	1	HEX_S2[5]
1	0	LV[15]
1	1	LV[3]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[6]
Bits		Destination
TERM[5][2]	TERM[5][3]	HEX_N3[6]
		Source
0	0	off
0	1	HEX_S2[6]
1	0	LV[21]
1	1	LV[9]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[7]
Bits		Destination
TERM[17][2]	TERM[17][3]	HEX_N3[7]
		Source
0	0	off
0	1	HEX_S2[7]
1	0	LV[15]
1	1	LV[3]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[8]
Bits		Destination
TERM[10][2]	TERM[10][3]	HEX_N3[8]
		Source
0	0	off
0	1	HEX_S2[8]
1	0	LV[21]
1	1	LV[9]

virtex2 TERM_S switchbox TERM_S muxes HEX_N3[9]
Bits		Destination
TERM[0][2]	TERM[0][3]	HEX_N3[9]
		Source
0	0	off
0	1	HEX_S2[9]
1	0	LV[15]
1	1	LV[3]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[0]
Bits		Destination
TERM[8][2]	TERM[8][3]	HEX_N4[0]
		Source
0	0	off
0	1	HEX_S3[0]
1	0	LV[20]
1	1	LV[8]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[1]
Bits		Destination
TERM[20][2]	TERM[20][3]	HEX_N4[1]
		Source
0	0	off
0	1	HEX_S3[1]
1	0	LV[14]
1	1	LV[2]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[2]
Bits		Destination
TERM[15][2]	TERM[15][3]	HEX_N4[2]
		Source
0	0	off
0	1	HEX_S3[2]
1	0	LV[20]
1	1	LV[8]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[3]
Bits		Destination
TERM[7][2]	TERM[7][3]	HEX_N4[3]
		Source
0	0	off
0	1	HEX_S3[3]
1	0	LV[14]
1	1	LV[2]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[4]
Bits		Destination
TERM[19][2]	TERM[19][3]	HEX_N4[4]
		Source
0	0	off
0	1	HEX_S3[4]
1	0	LV[20]
1	1	LV[8]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[5]
Bits		Destination
TERM[12][2]	TERM[12][3]	HEX_N4[5]
		Source
0	0	off
0	1	HEX_S3[5]
1	0	LV[14]
1	1	LV[2]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[6]
Bits		Destination
TERM[4][2]	TERM[4][3]	HEX_N4[6]
		Source
0	0	off
0	1	HEX_S3[6]
1	0	LV[20]
1	1	LV[8]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[7]
Bits		Destination
TERM[16][2]	TERM[16][3]	HEX_N4[7]
		Source
0	0	off
0	1	HEX_S3[7]
1	0	LV[14]
1	1	LV[2]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[8]
Bits		Destination
TERM[11][2]	TERM[11][3]	HEX_N4[8]
		Source
0	0	off
0	1	HEX_S3[8]
1	0	LV[20]
1	1	LV[8]

virtex2 TERM_S switchbox TERM_S muxes HEX_N4[9]
Bits		Destination
TERM[3][2]	TERM[3][3]	HEX_N4[9]
		Source
0	0	off
0	1	HEX_S3[9]
1	0	LV[14]
1	1	LV[2]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[0]
Bits		Destination
TERM[9][0]	TERM[9][1]	HEX_N5[0]
		Source
0	0	off
0	1	HEX_S4[0]
1	0	LV[19]
1	1	LV[7]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[1]
Bits		Destination
TERM[21][0]	TERM[21][1]	HEX_N5[1]
		Source
0	0	off
0	1	HEX_S4[1]
1	0	LV[13]
1	1	LV[1]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[2]
Bits		Destination
TERM[14][0]	TERM[14][1]	HEX_N5[2]
		Source
0	0	off
0	1	HEX_S4[2]
1	0	LV[19]
1	1	LV[7]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[3]
Bits		Destination
TERM[6][0]	TERM[6][1]	HEX_N5[3]
		Source
0	0	off
0	1	HEX_S4[3]
1	0	LV[13]
1	1	LV[1]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[4]
Bits		Destination
TERM[18][0]	TERM[18][1]	HEX_N5[4]
		Source
0	0	off
0	1	HEX_S4[4]
1	0	LV[19]
1	1	LV[7]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[5]
Bits		Destination
TERM[13][0]	TERM[13][1]	HEX_N5[5]
		Source
0	0	off
0	1	HEX_S4[5]
1	0	LV[13]
1	1	LV[1]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[6]
Bits		Destination
TERM[5][0]	TERM[5][1]	HEX_N5[6]
		Source
0	0	off
0	1	HEX_S4[6]
1	0	LV[19]
1	1	LV[7]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[7]
Bits		Destination
TERM[17][0]	TERM[17][1]	HEX_N5[7]
		Source
0	0	off
0	1	HEX_S4[7]
1	0	LV[13]
1	1	LV[1]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[8]
Bits		Destination
TERM[10][0]	TERM[10][1]	HEX_N5[8]
		Source
0	0	off
0	1	HEX_S4[8]
1	0	LV[19]
1	1	LV[7]

virtex2 TERM_S switchbox TERM_S muxes HEX_N5[9]
Bits		Destination
TERM[0][0]	TERM[0][1]	HEX_N5[9]
		Source
0	0	off
0	1	HEX_S4[9]
1	0	LV[13]
1	1	LV[1]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[0]
Bits		Destination
TERM[8][0]	TERM[8][1]	HEX_N6[0]
		Source
0	0	off
0	1	HEX_S5[0]
1	0	LV[18]
1	1	LV[6]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[1]
Bits		Destination
TERM[20][0]	TERM[20][1]	HEX_N6[1]
		Source
0	0	off
0	1	HEX_S5[1]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[2]
Bits		Destination
TERM[15][0]	TERM[15][1]	HEX_N6[2]
		Source
0	0	off
0	1	HEX_S5[2]
1	0	LV[18]
1	1	LV[6]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[3]
Bits		Destination
TERM[7][0]	TERM[7][1]	HEX_N6[3]
		Source
0	0	off
0	1	HEX_S5[3]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[4]
Bits		Destination
TERM[19][0]	TERM[19][1]	HEX_N6[4]
		Source
0	0	off
0	1	HEX_S5[4]
1	0	LV[18]
1	1	LV[6]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[5]
Bits		Destination
TERM[12][0]	TERM[12][1]	HEX_N6[5]
		Source
0	0	off
0	1	HEX_S5[5]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[6]
Bits		Destination
TERM[4][0]	TERM[4][1]	HEX_N6[6]
		Source
0	0	off
0	1	HEX_S5[6]
1	0	LV[18]
1	1	LV[6]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[7]
Bits		Destination
TERM[16][0]	TERM[16][1]	HEX_N6[7]
		Source
0	0	off
0	1	HEX_S5[7]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[8]
Bits		Destination
TERM[11][0]	TERM[11][1]	HEX_N6[8]
		Source
0	0	off
0	1	HEX_S5[8]
1	0	LV[18]
1	1	LV[6]

virtex2 TERM_S switchbox TERM_S muxes HEX_N6[9]
Bits		Destination
TERM[3][0]	TERM[3][1]	HEX_N6[9]
		Source
0	0	off
0	1	HEX_S5[9]
1	0	LV[12]
1	1	LV[0]

Bitstream

virtex2 TERM_S rect TERM
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	TERM_S: mux HEX_N1[1] bit 0	TERM_S: mux HEX_N2[1] bit 0	TERM_S: mux HEX_N2[4] bit 0	TERM_S: mux HEX_N1[4] bit 0	TERM_S: mux HEX_N1[7] bit 0	TERM_S: mux HEX_N2[7] bit 0	TERM_S: mux HEX_N2[2] bit 0	TERM_S: mux HEX_N1[2] bit 0	TERM_S: mux HEX_N1[5] bit 0	TERM_S: mux HEX_N2[5] bit 0	TERM_S: mux HEX_N2[8] bit 0	TERM_S: mux HEX_N1[8] bit 0	TERM_S: mux HEX_N1[0] bit 0	TERM_S: mux HEX_N2[0] bit 0	TERM_S: mux HEX_N2[3] bit 0	TERM_S: mux HEX_N1[3] bit 0	TERM_S: mux HEX_N1[6] bit 0	TERM_S: mux HEX_N2[6] bit 0	TERM_S: mux HEX_N2[9] bit 0	-	-	TERM_S: mux HEX_N1[9] bit 0
B4	TERM_S: mux HEX_N1[1] bit 1	TERM_S: mux HEX_N2[1] bit 1	TERM_S: mux HEX_N2[4] bit 1	TERM_S: mux HEX_N1[4] bit 1	TERM_S: mux HEX_N1[7] bit 1	TERM_S: mux HEX_N2[7] bit 1	TERM_S: mux HEX_N2[2] bit 1	TERM_S: mux HEX_N1[2] bit 1	TERM_S: mux HEX_N1[5] bit 1	TERM_S: mux HEX_N2[5] bit 1	TERM_S: mux HEX_N2[8] bit 1	TERM_S: mux HEX_N1[8] bit 1	TERM_S: mux HEX_N1[0] bit 1	TERM_S: mux HEX_N2[0] bit 1	TERM_S: mux HEX_N2[3] bit 1	TERM_S: mux HEX_N1[3] bit 1	TERM_S: mux HEX_N1[6] bit 1	TERM_S: mux HEX_N2[6] bit 1	TERM_S: mux HEX_N2[9] bit 1	-	-	TERM_S: mux HEX_N1[9] bit 1
B3	TERM_S: mux HEX_N3[1] bit 0	TERM_S: mux HEX_N4[1] bit 0	TERM_S: mux HEX_N4[4] bit 0	TERM_S: mux HEX_N3[4] bit 0	TERM_S: mux HEX_N3[7] bit 0	TERM_S: mux HEX_N4[7] bit 0	TERM_S: mux HEX_N4[2] bit 0	TERM_S: mux HEX_N3[2] bit 0	TERM_S: mux HEX_N3[5] bit 0	TERM_S: mux HEX_N4[5] bit 0	TERM_S: mux HEX_N4[8] bit 0	TERM_S: mux HEX_N3[8] bit 0	TERM_S: mux HEX_N3[0] bit 0	TERM_S: mux HEX_N4[0] bit 0	TERM_S: mux HEX_N4[3] bit 0	TERM_S: mux HEX_N3[3] bit 0	TERM_S: mux HEX_N3[6] bit 0	TERM_S: mux HEX_N4[6] bit 0	TERM_S: mux HEX_N4[9] bit 0	-	-	TERM_S: mux HEX_N3[9] bit 0
B2	TERM_S: mux HEX_N3[1] bit 1	TERM_S: mux HEX_N4[1] bit 1	TERM_S: mux HEX_N4[4] bit 1	TERM_S: mux HEX_N3[4] bit 1	TERM_S: mux HEX_N3[7] bit 1	TERM_S: mux HEX_N4[7] bit 1	TERM_S: mux HEX_N4[2] bit 1	TERM_S: mux HEX_N3[2] bit 1	TERM_S: mux HEX_N3[5] bit 1	TERM_S: mux HEX_N4[5] bit 1	TERM_S: mux HEX_N4[8] bit 1	TERM_S: mux HEX_N3[8] bit 1	TERM_S: mux HEX_N3[0] bit 1	TERM_S: mux HEX_N4[0] bit 1	TERM_S: mux HEX_N4[3] bit 1	TERM_S: mux HEX_N3[3] bit 1	TERM_S: mux HEX_N3[6] bit 1	TERM_S: mux HEX_N4[6] bit 1	TERM_S: mux HEX_N4[9] bit 1	-	-	TERM_S: mux HEX_N3[9] bit 1
B1	TERM_S: mux HEX_N5[1] bit 0	TERM_S: mux HEX_N6[1] bit 0	TERM_S: mux HEX_N6[4] bit 0	TERM_S: mux HEX_N5[4] bit 0	TERM_S: mux HEX_N5[7] bit 0	TERM_S: mux HEX_N6[7] bit 0	TERM_S: mux HEX_N6[2] bit 0	TERM_S: mux HEX_N5[2] bit 0	TERM_S: mux HEX_N5[5] bit 0	TERM_S: mux HEX_N6[5] bit 0	TERM_S: mux HEX_N6[8] bit 0	TERM_S: mux HEX_N5[8] bit 0	TERM_S: mux HEX_N5[0] bit 0	TERM_S: mux HEX_N6[0] bit 0	TERM_S: mux HEX_N6[3] bit 0	TERM_S: mux HEX_N5[3] bit 0	TERM_S: mux HEX_N5[6] bit 0	TERM_S: mux HEX_N6[6] bit 0	TERM_S: mux HEX_N6[9] bit 0	-	-	TERM_S: mux HEX_N5[9] bit 0
B0	TERM_S: mux HEX_N5[1] bit 1	TERM_S: mux HEX_N6[1] bit 1	TERM_S: mux HEX_N6[4] bit 1	TERM_S: mux HEX_N5[4] bit 1	TERM_S: mux HEX_N5[7] bit 1	TERM_S: mux HEX_N6[7] bit 1	TERM_S: mux HEX_N6[2] bit 1	TERM_S: mux HEX_N5[2] bit 1	TERM_S: mux HEX_N5[5] bit 1	TERM_S: mux HEX_N6[5] bit 1	TERM_S: mux HEX_N6[8] bit 1	TERM_S: mux HEX_N5[8] bit 1	TERM_S: mux HEX_N5[0] bit 1	TERM_S: mux HEX_N6[0] bit 1	TERM_S: mux HEX_N6[3] bit 1	TERM_S: mux HEX_N5[3] bit 1	TERM_S: mux HEX_N5[6] bit 1	TERM_S: mux HEX_N6[6] bit 1	TERM_S: mux HEX_N6[9] bit 1	-	-	TERM_S: mux HEX_N5[9] bit 1

`TERM_N`

Located at the top edge of every interconnect column, this tile is 22×12 bits.

Tile TERM_N

Cells: 1

Switchbox TERM_N

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[0]
Bits		Destination
TERM[9][4]	TERM[9][5]	HEX_S1[0]
		Source
0	0	off
0	1	HEX_N0[0]
1	0	LV[1]
1	1	LV[13]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[1]
Bits		Destination
TERM[21][4]	TERM[21][5]	HEX_S1[1]
		Source
0	0	off
0	1	HEX_N0[1]
1	0	LV[7]
1	1	LV[19]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[2]
Bits		Destination
TERM[14][4]	TERM[14][5]	HEX_S1[2]
		Source
0	0	off
0	1	HEX_N0[2]
1	0	LV[1]
1	1	LV[13]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[3]
Bits		Destination
TERM[6][4]	TERM[6][5]	HEX_S1[3]
		Source
0	0	off
0	1	HEX_N0[3]
1	0	LV[7]
1	1	LV[19]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[4]
Bits		Destination
TERM[18][4]	TERM[18][5]	HEX_S1[4]
		Source
0	0	off
0	1	HEX_N0[4]
1	0	LV[1]
1	1	LV[13]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[5]
Bits		Destination
TERM[13][4]	TERM[13][5]	HEX_S1[5]
		Source
0	0	off
0	1	HEX_N0[5]
1	0	LV[7]
1	1	LV[19]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[6]
Bits		Destination
TERM[5][4]	TERM[5][5]	HEX_S1[6]
		Source
0	0	off
0	1	HEX_N0[6]
1	0	LV[1]
1	1	LV[13]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[7]
Bits		Destination
TERM[17][4]	TERM[17][5]	HEX_S1[7]
		Source
0	0	off
0	1	HEX_N0[7]
1	0	LV[7]
1	1	LV[19]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[8]
Bits		Destination
TERM[10][4]	TERM[10][5]	HEX_S1[8]
		Source
0	0	off
0	1	HEX_N0[8]
1	0	LV[1]
1	1	LV[13]

virtex2 TERM_N switchbox TERM_N muxes HEX_S1[9]
Bits		Destination
TERM[0][4]	TERM[0][5]	HEX_S1[9]
		Source
0	0	off
0	1	HEX_N0[9]
1	0	LV[7]
1	1	LV[19]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[0]
Bits		Destination
TERM[8][4]	TERM[8][5]	HEX_S2[0]
		Source
0	0	off
0	1	HEX_N1[0]
1	0	LV[2]
1	1	LV[14]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[1]
Bits		Destination
TERM[20][4]	TERM[20][5]	HEX_S2[1]
		Source
0	0	off
0	1	HEX_N1[1]
1	0	LV[8]
1	1	LV[20]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[2]
Bits		Destination
TERM[15][4]	TERM[15][5]	HEX_S2[2]
		Source
0	0	off
0	1	HEX_N1[2]
1	0	LV[2]
1	1	LV[14]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[3]
Bits		Destination
TERM[7][4]	TERM[7][5]	HEX_S2[3]
		Source
0	0	off
0	1	HEX_N1[3]
1	0	LV[8]
1	1	LV[20]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[4]
Bits		Destination
TERM[19][4]	TERM[19][5]	HEX_S2[4]
		Source
0	0	off
0	1	HEX_N1[4]
1	0	LV[2]
1	1	LV[14]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[5]
Bits		Destination
TERM[12][4]	TERM[12][5]	HEX_S2[5]
		Source
0	0	off
0	1	HEX_N1[5]
1	0	LV[8]
1	1	LV[20]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[6]
Bits		Destination
TERM[4][4]	TERM[4][5]	HEX_S2[6]
		Source
0	0	off
0	1	HEX_N1[6]
1	0	LV[2]
1	1	LV[14]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[7]
Bits		Destination
TERM[16][4]	TERM[16][5]	HEX_S2[7]
		Source
0	0	off
0	1	HEX_N1[7]
1	0	LV[8]
1	1	LV[20]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[8]
Bits		Destination
TERM[11][4]	TERM[11][5]	HEX_S2[8]
		Source
0	0	off
0	1	HEX_N1[8]
1	0	LV[2]
1	1	LV[14]

virtex2 TERM_N switchbox TERM_N muxes HEX_S2[9]
Bits		Destination
TERM[3][4]	TERM[3][5]	HEX_S2[9]
		Source
0	0	off
0	1	HEX_N1[9]
1	0	LV[8]
1	1	LV[20]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[0]
Bits		Destination
TERM[9][2]	TERM[9][3]	HEX_S3[0]
		Source
0	0	off
0	1	HEX_N2[0]
1	0	LV[3]
1	1	LV[15]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[1]
Bits		Destination
TERM[21][2]	TERM[21][3]	HEX_S3[1]
		Source
0	0	off
0	1	HEX_N2[1]
1	0	LV[9]
1	1	LV[21]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[2]
Bits		Destination
TERM[14][2]	TERM[14][3]	HEX_S3[2]
		Source
0	0	off
0	1	HEX_N2[2]
1	0	LV[3]
1	1	LV[15]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[3]
Bits		Destination
TERM[6][2]	TERM[6][3]	HEX_S3[3]
		Source
0	0	off
0	1	HEX_N2[3]
1	0	LV[9]
1	1	LV[21]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[4]
Bits		Destination
TERM[18][2]	TERM[18][3]	HEX_S3[4]
		Source
0	0	off
0	1	HEX_N2[4]
1	0	LV[3]
1	1	LV[15]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[5]
Bits		Destination
TERM[13][2]	TERM[13][3]	HEX_S3[5]
		Source
0	0	off
0	1	HEX_N2[5]
1	0	LV[9]
1	1	LV[21]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[6]
Bits		Destination
TERM[5][2]	TERM[5][3]	HEX_S3[6]
		Source
0	0	off
0	1	HEX_N2[6]
1	0	LV[3]
1	1	LV[15]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[7]
Bits		Destination
TERM[17][2]	TERM[17][3]	HEX_S3[7]
		Source
0	0	off
0	1	HEX_N2[7]
1	0	LV[9]
1	1	LV[21]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[8]
Bits		Destination
TERM[10][2]	TERM[10][3]	HEX_S3[8]
		Source
0	0	off
0	1	HEX_N2[8]
1	0	LV[3]
1	1	LV[15]

virtex2 TERM_N switchbox TERM_N muxes HEX_S3[9]
Bits		Destination
TERM[0][2]	TERM[0][3]	HEX_S3[9]
		Source
0	0	off
0	1	HEX_N2[9]
1	0	LV[9]
1	1	LV[21]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[0]
Bits		Destination
TERM[8][2]	TERM[8][3]	HEX_S4[0]
		Source
0	0	off
0	1	HEX_N3[0]
1	0	LV[4]
1	1	LV[16]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[1]
Bits		Destination
TERM[20][2]	TERM[20][3]	HEX_S4[1]
		Source
0	0	off
0	1	HEX_N3[1]
1	0	LV[10]
1	1	LV[22]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[2]
Bits		Destination
TERM[15][2]	TERM[15][3]	HEX_S4[2]
		Source
0	0	off
0	1	HEX_N3[2]
1	0	LV[4]
1	1	LV[16]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[3]
Bits		Destination
TERM[7][2]	TERM[7][3]	HEX_S4[3]
		Source
0	0	off
0	1	HEX_N3[3]
1	0	LV[10]
1	1	LV[22]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[4]
Bits		Destination
TERM[19][2]	TERM[19][3]	HEX_S4[4]
		Source
0	0	off
0	1	HEX_N3[4]
1	0	LV[4]
1	1	LV[16]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[5]
Bits		Destination
TERM[12][2]	TERM[12][3]	HEX_S4[5]
		Source
0	0	off
0	1	HEX_N3[5]
1	0	LV[10]
1	1	LV[22]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[6]
Bits		Destination
TERM[4][2]	TERM[4][3]	HEX_S4[6]
		Source
0	0	off
0	1	HEX_N3[6]
1	0	LV[4]
1	1	LV[16]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[7]
Bits		Destination
TERM[16][2]	TERM[16][3]	HEX_S4[7]
		Source
0	0	off
0	1	HEX_N3[7]
1	0	LV[10]
1	1	LV[22]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[8]
Bits		Destination
TERM[11][2]	TERM[11][3]	HEX_S4[8]
		Source
0	0	off
0	1	HEX_N3[8]
1	0	LV[4]
1	1	LV[16]

virtex2 TERM_N switchbox TERM_N muxes HEX_S4[9]
Bits		Destination
TERM[3][2]	TERM[3][3]	HEX_S4[9]
		Source
0	0	off
0	1	HEX_N3[9]
1	0	LV[10]
1	1	LV[22]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[0]
Bits		Destination
TERM[9][0]	TERM[9][1]	HEX_S5[0]
		Source
0	0	off
0	1	HEX_N4[0]
1	0	LV[5]
1	1	LV[17]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[1]
Bits		Destination
TERM[21][0]	TERM[21][1]	HEX_S5[1]
		Source
0	0	off
0	1	HEX_N4[1]
1	0	LV[11]
1	1	LV[23]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[2]
Bits		Destination
TERM[14][0]	TERM[14][1]	HEX_S5[2]
		Source
0	0	off
0	1	HEX_N4[2]
1	0	LV[5]
1	1	LV[17]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[3]
Bits		Destination
TERM[6][0]	TERM[6][1]	HEX_S5[3]
		Source
0	0	off
0	1	HEX_N4[3]
1	0	LV[11]
1	1	LV[23]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[4]
Bits		Destination
TERM[18][0]	TERM[18][1]	HEX_S5[4]
		Source
0	0	off
0	1	HEX_N4[4]
1	0	LV[5]
1	1	LV[17]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[5]
Bits		Destination
TERM[13][0]	TERM[13][1]	HEX_S5[5]
		Source
0	0	off
0	1	HEX_N4[5]
1	0	LV[11]
1	1	LV[23]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[6]
Bits		Destination
TERM[5][0]	TERM[5][1]	HEX_S5[6]
		Source
0	0	off
0	1	HEX_N4[6]
1	0	LV[5]
1	1	LV[17]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[7]
Bits		Destination
TERM[17][0]	TERM[17][1]	HEX_S5[7]
		Source
0	0	off
0	1	HEX_N4[7]
1	0	LV[11]
1	1	LV[23]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[8]
Bits		Destination
TERM[10][0]	TERM[10][1]	HEX_S5[8]
		Source
0	0	off
0	1	HEX_N4[8]
1	0	LV[5]
1	1	LV[17]

virtex2 TERM_N switchbox TERM_N muxes HEX_S5[9]
Bits		Destination
TERM[0][0]	TERM[0][1]	HEX_S5[9]
		Source
0	0	off
0	1	HEX_N4[9]
1	0	LV[11]
1	1	LV[23]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[0]
Bits		Destination
TERM[8][0]	TERM[8][1]	HEX_S6[0]
		Source
0	0	off
0	1	HEX_N5[0]
1	0	LV[6]
1	1	LV[18]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[1]
Bits		Destination
TERM[20][0]	TERM[20][1]	HEX_S6[1]
		Source
0	0	off
0	1	HEX_N5[1]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[2]
Bits		Destination
TERM[15][0]	TERM[15][1]	HEX_S6[2]
		Source
0	0	off
0	1	HEX_N5[2]
1	0	LV[6]
1	1	LV[18]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[3]
Bits		Destination
TERM[7][0]	TERM[7][1]	HEX_S6[3]
		Source
0	0	off
0	1	HEX_N5[3]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[4]
Bits		Destination
TERM[19][0]	TERM[19][1]	HEX_S6[4]
		Source
0	0	off
0	1	HEX_N5[4]
1	0	LV[6]
1	1	LV[18]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[5]
Bits		Destination
TERM[12][0]	TERM[12][1]	HEX_S6[5]
		Source
0	0	off
0	1	HEX_N5[5]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[6]
Bits		Destination
TERM[4][0]	TERM[4][1]	HEX_S6[6]
		Source
0	0	off
0	1	HEX_N5[6]
1	0	LV[6]
1	1	LV[18]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[7]
Bits		Destination
TERM[16][0]	TERM[16][1]	HEX_S6[7]
		Source
0	0	off
0	1	HEX_N5[7]
1	0	LV[12]
1	1	LV[0]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[8]
Bits		Destination
TERM[11][0]	TERM[11][1]	HEX_S6[8]
		Source
0	0	off
0	1	HEX_N5[8]
1	0	LV[6]
1	1	LV[18]

virtex2 TERM_N switchbox TERM_N muxes HEX_S6[9]
Bits		Destination
TERM[3][0]	TERM[3][1]	HEX_S6[9]
		Source
0	0	off
0	1	HEX_N5[9]
1	0	LV[12]
1	1	LV[0]

Bitstream

virtex2 TERM_N rect TERM
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	TERM_N: mux HEX_S1[1] bit 0	TERM_N: mux HEX_S2[1] bit 0	TERM_N: mux HEX_S2[4] bit 0	TERM_N: mux HEX_S1[4] bit 0	TERM_N: mux HEX_S1[7] bit 0	TERM_N: mux HEX_S2[7] bit 0	TERM_N: mux HEX_S2[2] bit 0	TERM_N: mux HEX_S1[2] bit 0	TERM_N: mux HEX_S1[5] bit 0	TERM_N: mux HEX_S2[5] bit 0	TERM_N: mux HEX_S2[8] bit 0	TERM_N: mux HEX_S1[8] bit 0	TERM_N: mux HEX_S1[0] bit 0	TERM_N: mux HEX_S2[0] bit 0	TERM_N: mux HEX_S2[3] bit 0	TERM_N: mux HEX_S1[3] bit 0	TERM_N: mux HEX_S1[6] bit 0	TERM_N: mux HEX_S2[6] bit 0	TERM_N: mux HEX_S2[9] bit 0	-	-	TERM_N: mux HEX_S1[9] bit 0
B4	TERM_N: mux HEX_S1[1] bit 1	TERM_N: mux HEX_S2[1] bit 1	TERM_N: mux HEX_S2[4] bit 1	TERM_N: mux HEX_S1[4] bit 1	TERM_N: mux HEX_S1[7] bit 1	TERM_N: mux HEX_S2[7] bit 1	TERM_N: mux HEX_S2[2] bit 1	TERM_N: mux HEX_S1[2] bit 1	TERM_N: mux HEX_S1[5] bit 1	TERM_N: mux HEX_S2[5] bit 1	TERM_N: mux HEX_S2[8] bit 1	TERM_N: mux HEX_S1[8] bit 1	TERM_N: mux HEX_S1[0] bit 1	TERM_N: mux HEX_S2[0] bit 1	TERM_N: mux HEX_S2[3] bit 1	TERM_N: mux HEX_S1[3] bit 1	TERM_N: mux HEX_S1[6] bit 1	TERM_N: mux HEX_S2[6] bit 1	TERM_N: mux HEX_S2[9] bit 1	-	-	TERM_N: mux HEX_S1[9] bit 1
B3	TERM_N: mux HEX_S3[1] bit 0	TERM_N: mux HEX_S4[1] bit 0	TERM_N: mux HEX_S4[4] bit 0	TERM_N: mux HEX_S3[4] bit 0	TERM_N: mux HEX_S3[7] bit 0	TERM_N: mux HEX_S4[7] bit 0	TERM_N: mux HEX_S4[2] bit 0	TERM_N: mux HEX_S3[2] bit 0	TERM_N: mux HEX_S3[5] bit 0	TERM_N: mux HEX_S4[5] bit 0	TERM_N: mux HEX_S4[8] bit 0	TERM_N: mux HEX_S3[8] bit 0	TERM_N: mux HEX_S3[0] bit 0	TERM_N: mux HEX_S4[0] bit 0	TERM_N: mux HEX_S4[3] bit 0	TERM_N: mux HEX_S3[3] bit 0	TERM_N: mux HEX_S3[6] bit 0	TERM_N: mux HEX_S4[6] bit 0	TERM_N: mux HEX_S4[9] bit 0	-	-	TERM_N: mux HEX_S3[9] bit 0
B2	TERM_N: mux HEX_S3[1] bit 1	TERM_N: mux HEX_S4[1] bit 1	TERM_N: mux HEX_S4[4] bit 1	TERM_N: mux HEX_S3[4] bit 1	TERM_N: mux HEX_S3[7] bit 1	TERM_N: mux HEX_S4[7] bit 1	TERM_N: mux HEX_S4[2] bit 1	TERM_N: mux HEX_S3[2] bit 1	TERM_N: mux HEX_S3[5] bit 1	TERM_N: mux HEX_S4[5] bit 1	TERM_N: mux HEX_S4[8] bit 1	TERM_N: mux HEX_S3[8] bit 1	TERM_N: mux HEX_S3[0] bit 1	TERM_N: mux HEX_S4[0] bit 1	TERM_N: mux HEX_S4[3] bit 1	TERM_N: mux HEX_S3[3] bit 1	TERM_N: mux HEX_S3[6] bit 1	TERM_N: mux HEX_S4[6] bit 1	TERM_N: mux HEX_S4[9] bit 1	-	-	TERM_N: mux HEX_S3[9] bit 1
B1	TERM_N: mux HEX_S5[1] bit 0	TERM_N: mux HEX_S6[1] bit 0	TERM_N: mux HEX_S6[4] bit 0	TERM_N: mux HEX_S5[4] bit 0	TERM_N: mux HEX_S5[7] bit 0	TERM_N: mux HEX_S6[7] bit 0	TERM_N: mux HEX_S6[2] bit 0	TERM_N: mux HEX_S5[2] bit 0	TERM_N: mux HEX_S5[5] bit 0	TERM_N: mux HEX_S6[5] bit 0	TERM_N: mux HEX_S6[8] bit 0	TERM_N: mux HEX_S5[8] bit 0	TERM_N: mux HEX_S5[0] bit 0	TERM_N: mux HEX_S6[0] bit 0	TERM_N: mux HEX_S6[3] bit 0	TERM_N: mux HEX_S5[3] bit 0	TERM_N: mux HEX_S5[6] bit 0	TERM_N: mux HEX_S6[6] bit 0	TERM_N: mux HEX_S6[9] bit 0	-	-	TERM_N: mux HEX_S5[9] bit 0
B0	TERM_N: mux HEX_S5[1] bit 1	TERM_N: mux HEX_S6[1] bit 1	TERM_N: mux HEX_S6[4] bit 1	TERM_N: mux HEX_S5[4] bit 1	TERM_N: mux HEX_S5[7] bit 1	TERM_N: mux HEX_S6[7] bit 1	TERM_N: mux HEX_S6[2] bit 1	TERM_N: mux HEX_S5[2] bit 1	TERM_N: mux HEX_S5[5] bit 1	TERM_N: mux HEX_S6[5] bit 1	TERM_N: mux HEX_S6[8] bit 1	TERM_N: mux HEX_S5[8] bit 1	TERM_N: mux HEX_S5[0] bit 1	TERM_N: mux HEX_S6[0] bit 1	TERM_N: mux HEX_S6[3] bit 1	TERM_N: mux HEX_S5[3] bit 1	TERM_N: mux HEX_S5[6] bit 1	TERM_N: mux HEX_S6[6] bit 1	TERM_N: mux HEX_S6[9] bit 1	-	-	TERM_N: mux HEX_S5[9] bit 1

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