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Clock Companion Modules

Tile CCM

Cells: 4

Switchbox SPEC_INT

virtex4 CCM switchbox SPEC_INT permanent buffers
DestinationSource
CELL[0].OUT_SEC_TMIN[0]CELL[0].OUT_DCM[0]
CELL[0].OUT_SEC_TMIN[1]CELL[0].OUT_DCM[1]
CELL[0].OUT_SEC_TMIN[2]CELL[0].OUT_DCM[2]
CELL[0].OUT_SEC_TMIN[3]CELL[0].OUT_DCM[3]
CELL[1].OUT_SEC_TMIN[0]CELL[0].OUT_DCM[4]
CELL[1].OUT_SEC_TMIN[1]CELL[0].OUT_DCM[5]
CELL[1].OUT_SEC_TMIN[2]CELL[0].OUT_DCM[6]
CELL[1].OUT_SEC_TMIN[3]CELL[0].OUT_DCM[7]
CELL[2].OUT_SEC_TMIN[0]CELL[0].OUT_DCM[8]
CELL[2].OUT_SEC_TMIN[1]CELL[0].OUT_DCM[9]
CELL[2].OUT_SEC_TMIN[2]CELL[0].OUT_DCM[10]
CELL[2].OUT_SEC_TMIN[3]CELL[0].OUT_DCM[11]
virtex4 CCM switchbox SPEC_INT muxes IMUX_SPEC[0]
BitsDestination
MAIN[0][21][28]MAIN[0][21][23]MAIN[0][21][22]MAIN[0][21][21]MAIN[0][21][20]MAIN[0][21][26]MAIN[0][21][25]MAIN[0][21][24]MAIN[0][21][27]MAIN[0][21][17]MAIN[0][21][19]MAIN[0][21][18]MAIN[0][21][16]CELL[0].IMUX_SPEC[0]---
MAIN[2][21][25]MAIN[2][21][20]MAIN[2][21][19]MAIN[2][21][18]MAIN[2][21][17]MAIN[2][21][16]MAIN[2][21][15]MAIN[2][21][14]MAIN[2][21][13]MAIN[2][21][23]MAIN[2][21][22]MAIN[2][21][21]MAIN[2][21][24]-CELL[1].IMUX_SPEC[0]--
MAIN[1][21][25]MAIN[1][21][20]MAIN[1][21][19]MAIN[1][21][18]MAIN[1][21][17]MAIN[1][21][16]MAIN[1][21][15]MAIN[1][21][14]MAIN[1][21][13]MAIN[1][21][23]MAIN[1][21][22]MAIN[1][21][21]MAIN[1][21][24]--CELL[2].IMUX_SPEC[0]-
MAIN[2][21][51]MAIN[2][21][46]MAIN[2][21][45]MAIN[2][21][44]MAIN[2][21][43]MAIN[2][21][42]MAIN[2][21][41]MAIN[2][21][40]MAIN[2][21][39]MAIN[2][21][49]MAIN[2][21][48]MAIN[2][21][47]MAIN[2][21][50]---CELL[3].IMUX_SPEC[0]
Source
0000000000000CELL[0].IMUX_IMUX[8]CELL[2].IMUX_IMUX[10]CELL[1].IMUX_IMUX[10]CELL[2].IMUX_IMUX[8]
0000000000011CELL[0].IMUX_CLK_OPTINV[0]CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]
0000000000101CELL[0].IMUX_CLK_OPTINV[1]CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]
0000000001001CELL[0].IMUX_IMUX[9]CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]
0000000110000CELL[0].HCLK_DCM[0]CELL[2].IMUX_IMUX[11]CELL[1].IMUX_IMUX[11]CELL[2].IMUX_IMUX[9]
0000000110011CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]
0000000110101CELL[0].GIOB_DCM[1]CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]
0000000111001CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]
0000001010000CELL[0].HCLK_DCM[1]CELL[2].IMUX_CLK_OPTINV[2]CELL[1].IMUX_CLK_OPTINV[2]CELL[2].IMUX_CLK_OPTINV[0]
0000001010011CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]
0000001010101CELL[0].GIOB_DCM[2]CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]
0000001011001CELL[0].HCLK_DCM[4]CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]
0000010010000CELL[0].HCLK_DCM[2]CELL[2].IMUX_CLK_OPTINV[3]CELL[1].IMUX_CLK_OPTINV[3]CELL[2].IMUX_CLK_OPTINV[1]
0000010010011CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]
0000010010101CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]
0000010011001CELL[0].HCLK_DCM[5]CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]
0000100010011-CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]
0000100010101-CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]
0000100011001-CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]
0000100110001CELL[0].GIOB_DCM[4]---
0000101010001CELL[0].GIOB_DCM[5]---
0000110010001CELL[0].GIOB_DCM[6]---
0001000010011-CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]
0001000010101-CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]
0001000011001-CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]
0001000110001CELL[0].GIOB_DCM[7]---
0001001010001CELL[0].GIOB_DCM[8]---
0001010010001CELL[0].GIOB_DCM[9]---
0010000010011-CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]
0010000010101-CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]
0010000011001-CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]
0010000110001CELL[0].GIOB_DCM[10]---
0010001010001CELL[0].GIOB_DCM[11]---
0010010010001CELL[0].GIOB_DCM[12]---
0100000010011-CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]
0100000010101-CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]
0100000011001-CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]
0100000110001CELL[0].GIOB_DCM[13]---
0100001010001CELL[0].GIOB_DCM[14]---
0100010010001CELL[0].GIOB_DCM[15]---
1000000000000CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]
1000000000011CELL[0].MGT_DCM[1]CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]
1000000000101CELL[0].MGT_DCM[2]CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]
1000000001001-CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]
1000000110000CELL[0].DCM_DCM_I[0]---
1000000110011CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]
1000000110101CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]
1000000111001CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]
1000001010000CELL[0].DCM_DCM_I[1]CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]
1000001010011CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]
1000001010101CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]
1000001011001CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]
1000010010000CELL[0].DCM_DCM_I[2]CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]
1000010010011CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]
1000010010101CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]
1000010011001CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]
1000100000001CELL[0].MGT_DCM[3]---
1000100010000-CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]
1000100010011-CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]
1000100010101-CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]
1000100011001-CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]
1000100110001CELL[0].DCM_DCM_I[12]---
1000101010001CELL[0].DCM_DCM_I[13]---
1000110010001CELL[0].DCM_DCM_I[14]---
1001000010011-CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]
1001000010101-CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]
1001000011001-CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]
1001000110001CELL[0].DCM_DCM_I[15]---
1001001010001CELL[0].DCM_DCM_I[16]---
1001010010001CELL[0].DCM_DCM_I[17]---
1010000010000-CELL[0].OUT_CCM_CLKA1D8[1]-CELL[0].OUT_CCM_CLKA1D8[1]
1010000010011-CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]
1010000010101-CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]
1010000011001-CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]
1010000110001CELL[0].DCM_DCM_I[18]---
1010001010001CELL[0].DCM_DCM_I[19]---
1010010010001CELL[0].DCM_DCM_I[20]---
1100000010011-CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]
1100000010101-CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]
1100000011001-CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]
1100000110001CELL[0].DCM_DCM_I[21]---
1100001010001CELL[0].DCM_DCM_I[22]---
1100010010001CELL[0].DCM_DCM_I[23]---
virtex4 CCM switchbox SPEC_INT muxes IMUX_SPEC[2]
BitsDestination
MAIN[1][21][51]MAIN[1][21][46]MAIN[1][21][45]MAIN[1][21][44]MAIN[1][21][43]MAIN[1][21][42]MAIN[1][21][41]MAIN[1][21][40]MAIN[1][21][39]MAIN[1][21][49]MAIN[1][21][48]MAIN[1][21][47]MAIN[1][21][50]CELL[0].IMUX_SPEC[2]--
MAIN[3][21][25]MAIN[3][21][20]MAIN[3][21][19]MAIN[3][21][18]MAIN[3][21][17]MAIN[3][21][16]MAIN[3][21][15]MAIN[3][21][14]MAIN[3][21][13]MAIN[3][21][23]MAIN[3][21][22]MAIN[3][21][21]MAIN[3][21][24]-CELL[1].IMUX_SPEC[2]-
MAIN[3][21][51]MAIN[3][21][46]MAIN[3][21][45]MAIN[3][21][44]MAIN[3][21][43]MAIN[3][21][42]MAIN[3][21][41]MAIN[3][21][40]MAIN[3][21][39]MAIN[3][21][49]MAIN[3][21][48]MAIN[3][21][47]MAIN[3][21][50]--CELL[3].IMUX_SPEC[2]
Source
0000000000000CELL[1].IMUX_IMUX[8]CELL[3].IMUX_IMUX[10]CELL[3].IMUX_IMUX[8]
0000000000011CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]
0000000000101CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]
0000000001001CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]
0000000110000CELL[1].IMUX_IMUX[9]CELL[3].IMUX_IMUX[11]CELL[3].IMUX_IMUX[9]
0000000110011CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]
0000000110101CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]
0000000111001CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]
0000001010000CELL[1].IMUX_CLK_OPTINV[0]CELL[3].IMUX_CLK_OPTINV[2]CELL[3].IMUX_CLK_OPTINV[0]
0000001010011CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]
0000001010101CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]
0000001011001CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]
0000010010000CELL[1].IMUX_CLK_OPTINV[1]CELL[3].IMUX_CLK_OPTINV[3]CELL[3].IMUX_CLK_OPTINV[1]
0000010010011CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]
0000010010101CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]
0000010011001CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]
0000100010011CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]
0000100010101CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]
0000100011001CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]
0001000010011CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]
0001000010101CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]
0001000011001CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]
0010000010011CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]
0010000010101CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]
0010000011001CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]
0100000010011CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]
0100000010101CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]
0100000011001CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]
1000000000000CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]
1000000000011CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]
1000000000101CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]
1000000001001CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]
1000000110011CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]
1000000110101CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]
1000000111001CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]
1000001010000CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]
1000001010011CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]
1000001010101CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]
1000001011001CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]
1000010010000CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]
1000010010011CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]
1000010010101CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]
1000010011001CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]
1000100010000CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]
1000100010011CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]
1000100010101CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]
1000100011001CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]
1001000010011CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]
1001000010101CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]
1001000011001CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]
1010000010000-CELL[0].OUT_CCM_CLKA1D8[0]CELL[0].OUT_CCM_CLKA1D8[0]
1010000010011CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]
1010000010101CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]
1010000011001CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]
1100000010011CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]
1100000010101CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]
1100000011001CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]
virtex4 CCM switchbox SPEC_INT muxes IMUX_SPEC[3]
BitsDestination
MAIN[1][21][38]MAIN[1][21][33]MAIN[1][21][32]MAIN[1][21][31]MAIN[1][21][30]MAIN[1][21][29]MAIN[1][21][28]MAIN[1][21][27]MAIN[1][21][26]MAIN[1][21][36]MAIN[1][21][35]MAIN[1][21][34]MAIN[1][21][37]CELL[0].IMUX_SPEC[3]--
MAIN[3][21][12]MAIN[3][21][7]MAIN[3][21][6]MAIN[3][21][5]MAIN[3][21][4]MAIN[3][21][3]MAIN[3][21][2]MAIN[3][21][1]MAIN[3][21][0]MAIN[3][21][10]MAIN[3][21][9]MAIN[3][21][8]MAIN[3][21][11]-CELL[1].IMUX_SPEC[3]-
MAIN[3][21][38]MAIN[3][21][33]MAIN[3][21][32]MAIN[3][21][31]MAIN[3][21][30]MAIN[3][21][29]MAIN[3][21][28]MAIN[3][21][27]MAIN[3][21][26]MAIN[3][21][36]MAIN[3][21][35]MAIN[3][21][34]MAIN[3][21][37]--CELL[3].IMUX_SPEC[3]
Source
0000000000000CELL[1].IMUX_IMUX[8]CELL[3].IMUX_IMUX[10]CELL[3].IMUX_IMUX[8]
0000000000011CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]
0000000000101CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]
0000000001001CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]
0000000110000CELL[1].IMUX_IMUX[9]CELL[3].IMUX_IMUX[11]CELL[3].IMUX_IMUX[9]
0000000110011CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]
0000000110101CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]
0000000111001CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]
0000001010000CELL[1].IMUX_CLK_OPTINV[0]CELL[3].IMUX_CLK_OPTINV[2]CELL[3].IMUX_CLK_OPTINV[0]
0000001010011CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]
0000001010101CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]
0000001011001CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]
0000010010000CELL[1].IMUX_CLK_OPTINV[1]CELL[3].IMUX_CLK_OPTINV[3]CELL[3].IMUX_CLK_OPTINV[1]
0000010010011CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]
0000010010101CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]
0000010011001CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]
0000100010011CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]
0000100010101CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]
0000100011001CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]
0001000010011CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]
0001000010101CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]
0001000011001CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]
0010000010011CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]
0010000010101CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]
0010000011001CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]
0100000010011CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]
0100000010101CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]
0100000011001CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]
1000000000000CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]
1000000000011CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]
1000000000101CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]
1000000001001CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]
1000000110011CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]
1000000110101CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]
1000000111001CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]
1000001010000CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]
1000001010011CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]
1000001010101CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]
1000001011001CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]
1000010010000CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]
1000010010011CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]
1000010010101CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]
1000010011001CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]
1000100010000CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]
1000100010011CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]
1000100010101CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]
1000100011001CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]
1001000010011CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]
1001000010101CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]
1001000011001CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]
1010000010000-CELL[0].OUT_CCM_CLKA1D8[0]CELL[0].OUT_CCM_CLKA1D8[0]
1010000010011CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]
1010000010101CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]
1010000011001CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]
1100000010011CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]
1100000010101CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]
1100000011001CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[0]
BitsDestination
MAIN[0][20][25]MAIN[0][20][23]MAIN[0][20][24]MAIN[0][20][22]MAIN[0][20][18]MAIN[0][20][16]MAIN[0][20][17]MAIN[0][20][20]MAIN[0][20][19]MAIN[0][20][21]CELL[0].OUT_DCM[0]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[1]
BitsDestination
MAIN[0][20][35]MAIN[0][20][33]MAIN[0][20][34]MAIN[0][20][32]MAIN[0][20][28]MAIN[0][20][26]MAIN[0][20][27]MAIN[0][20][30]MAIN[0][20][29]MAIN[0][20][31]CELL[0].OUT_DCM[1]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[2]
BitsDestination
MAIN[0][20][45]MAIN[0][20][43]MAIN[0][20][44]MAIN[0][20][42]MAIN[0][20][38]MAIN[0][20][36]MAIN[0][20][37]MAIN[0][20][40]MAIN[0][20][39]MAIN[0][20][41]CELL[0].OUT_DCM[2]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[3]
BitsDestination
MAIN[0][20][55]MAIN[0][20][53]MAIN[0][20][54]MAIN[0][20][52]MAIN[0][20][48]MAIN[0][20][46]MAIN[0][20][47]MAIN[0][20][50]MAIN[0][20][49]MAIN[0][20][51]CELL[0].OUT_DCM[3]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[4]
BitsDestination
MAIN[1][20][9]MAIN[1][20][7]MAIN[1][20][8]MAIN[1][20][6]MAIN[1][20][2]MAIN[1][20][0]MAIN[1][20][1]MAIN[1][20][4]MAIN[1][20][3]MAIN[1][20][5]CELL[0].OUT_DCM[4]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[5]
BitsDestination
MAIN[1][20][19]MAIN[1][20][17]MAIN[1][20][18]MAIN[1][20][16]MAIN[1][20][12]MAIN[1][20][10]MAIN[1][20][11]MAIN[1][20][14]MAIN[1][20][13]MAIN[1][20][15]CELL[0].OUT_DCM[5]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[6]
BitsDestination
MAIN[1][20][29]MAIN[1][20][27]MAIN[1][20][28]MAIN[1][20][26]MAIN[1][20][22]MAIN[1][20][20]MAIN[1][20][21]MAIN[1][20][24]MAIN[1][20][23]MAIN[1][20][25]CELL[0].OUT_DCM[6]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[7]
BitsDestination
MAIN[1][20][39]MAIN[1][20][37]MAIN[1][20][38]MAIN[1][20][36]MAIN[1][20][32]MAIN[1][20][30]MAIN[1][20][31]MAIN[1][20][34]MAIN[1][20][33]MAIN[1][20][35]CELL[0].OUT_DCM[7]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[8]
BitsDestination
MAIN[2][20][9]MAIN[2][20][7]MAIN[2][20][8]MAIN[2][20][6]MAIN[2][20][2]MAIN[2][20][0]MAIN[2][20][1]MAIN[2][20][4]MAIN[2][20][3]MAIN[2][20][5]CELL[0].OUT_DCM[8]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[9]
BitsDestination
MAIN[2][20][19]MAIN[2][20][17]MAIN[2][20][18]MAIN[2][20][16]MAIN[2][20][12]MAIN[2][20][10]MAIN[2][20][11]MAIN[2][20][14]MAIN[2][20][13]MAIN[2][20][15]CELL[0].OUT_DCM[9]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[10]
BitsDestination
MAIN[2][20][29]MAIN[2][20][27]MAIN[2][20][28]MAIN[2][20][26]MAIN[2][20][22]MAIN[2][20][20]MAIN[2][20][21]MAIN[2][20][24]MAIN[2][20][23]MAIN[2][20][25]CELL[0].OUT_DCM[10]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes OUT_DCM[11]
BitsDestination
MAIN[2][20][39]MAIN[2][20][37]MAIN[2][20][38]MAIN[2][20][36]MAIN[2][20][32]MAIN[2][20][30]MAIN[2][20][31]MAIN[2][20][34]MAIN[2][20][33]MAIN[2][20][35]CELL[0].OUT_DCM[11]
Source
0000000000off
0001000001CELL[0].OUT_CCM_CLKA1[0]
0001000010CELL[0].OUT_CCM_OSCOUT2
0001000100CELL[0].OUT_CCM_OSCOUT1
0001010000CELL[0].OUT_CCM_REFCLKOUT
0010000001CELL[0].OUT_CCM_CLKA1D4[1]
0010000010CELL[0].OUT_CCM_CLKA1[1]
0010000100CELL[0].OUT_CCM_CLKA1D2[1]
0010001000CELL[0].OUT_CCM_CLKA1D8[0]
0010010000CELL[0].OUT_CCM_CLKD1[1]
0010100000CELL[0].OUT_CCM_CLKB1[1]
0100000001CELL[0].OUT_CCM_CLKC1[1]
0100000010CELL[0].OUT_CCM_CLKA1D2[0]
0100000100CELL[0].OUT_CCM_CLKA1D4[0]
0100001000CELL[0].OUT_CCM_CLKC1[0]
0100010000CELL[0].OUT_CCM_CLKB1[0]
0100100000CELL[0].OUT_CCM_CLKD1[0]
1000001000CELL[3].IMUX_IMUX[8]
1000010000CELL[0].OUT_CCM_CLKA1D8[1]
virtex4 CCM switchbox SPEC_INT muxes IMUX_CCM_REL[0]
BitsDestination
MAIN[3][20][20]CELL[0].IMUX_CCM_REL[0]
Source
0CELL[0].IMUX_SPEC[3]
1CELL[0].IMUX_IMUX[0]
virtex4 CCM switchbox SPEC_INT muxes IMUX_CCM_REL[1]
BitsDestination
MAIN[3][20][21]CELL[0].IMUX_CCM_REL[1]
Source
0CELL[0].IMUX_SPEC[2]
1CELL[1].IMUX_IMUX[0]
virtex4 CCM switchbox SPEC_INT muxes IMUX_SPEC[1]
BitsDestination
MAIN[2][21][12]MAIN[2][21][7]MAIN[2][21][6]MAIN[2][21][5]MAIN[2][21][4]MAIN[2][21][3]MAIN[2][21][2]MAIN[2][21][1]MAIN[2][21][0]MAIN[2][21][10]MAIN[2][21][9]MAIN[2][21][8]MAIN[2][21][11]CELL[1].IMUX_SPEC[1]--
MAIN[1][21][12]MAIN[1][21][7]MAIN[1][21][6]MAIN[1][21][5]MAIN[1][21][4]MAIN[1][21][3]MAIN[1][21][2]MAIN[1][21][1]MAIN[1][21][0]MAIN[1][21][10]MAIN[1][21][9]MAIN[1][21][8]MAIN[1][21][11]-CELL[2].IMUX_SPEC[1]-
MAIN[2][21][38]MAIN[2][21][33]MAIN[2][21][32]MAIN[2][21][31]MAIN[2][21][30]MAIN[2][21][29]MAIN[2][21][28]MAIN[2][21][27]MAIN[2][21][26]MAIN[2][21][36]MAIN[2][21][35]MAIN[2][21][34]MAIN[2][21][37]--CELL[3].IMUX_SPEC[1]
Source
0000000000000CELL[2].IMUX_IMUX[10]CELL[1].IMUX_IMUX[10]CELL[2].IMUX_IMUX[8]
0000000000011CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]CELL[0].HCLK_DCM[0]
0000000000101CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]CELL[0].HCLK_DCM[1]
0000000001001CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]CELL[0].HCLK_DCM[2]
0000000110000CELL[2].IMUX_IMUX[11]CELL[1].IMUX_IMUX[11]CELL[2].IMUX_IMUX[9]
0000000110011CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]CELL[0].HCLK_DCM[3]
0000000110101CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]CELL[0].HCLK_DCM[4]
0000000111001CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]CELL[0].HCLK_DCM[5]
0000001010000CELL[2].IMUX_CLK_OPTINV[2]CELL[1].IMUX_CLK_OPTINV[2]CELL[2].IMUX_CLK_OPTINV[0]
0000001010011CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]CELL[0].HCLK_DCM[6]
0000001010101CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]CELL[0].HCLK_DCM[7]
0000001011001CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]CELL[0].GIOB_DCM[0]
0000010010000CELL[2].IMUX_CLK_OPTINV[3]CELL[1].IMUX_CLK_OPTINV[3]CELL[2].IMUX_CLK_OPTINV[1]
0000010010011CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]CELL[0].GIOB_DCM[1]
0000010010101CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]CELL[0].GIOB_DCM[2]
0000010011001CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]CELL[0].GIOB_DCM[3]
0000100010011CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]CELL[0].GIOB_DCM[4]
0000100010101CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]CELL[0].GIOB_DCM[5]
0000100011001CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]CELL[0].GIOB_DCM[6]
0001000010011CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]CELL[0].GIOB_DCM[7]
0001000010101CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]CELL[0].GIOB_DCM[8]
0001000011001CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]CELL[0].GIOB_DCM[9]
0010000010011CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]CELL[0].GIOB_DCM[10]
0010000010101CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]CELL[0].GIOB_DCM[11]
0010000011001CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]CELL[0].GIOB_DCM[12]
0100000010011CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]CELL[0].GIOB_DCM[13]
0100000010101CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]CELL[0].GIOB_DCM[14]
0100000011001CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]CELL[0].GIOB_DCM[15]
1000000000000CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]CELL[0].MGT_DCM[0]
1000000000011CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]CELL[0].DCM_DCM_I[0]
1000000000101CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]CELL[0].DCM_DCM_I[1]
1000000001001CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]CELL[0].DCM_DCM_I[2]
1000000110011CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]CELL[0].DCM_DCM_I[3]
1000000110101CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]CELL[0].DCM_DCM_I[4]
1000000111001CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]CELL[0].DCM_DCM_I[5]
1000001010000CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]CELL[0].MGT_DCM[1]
1000001010011CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]CELL[0].DCM_DCM_I[6]
1000001010101CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]CELL[0].DCM_DCM_I[7]
1000001011001CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]CELL[0].DCM_DCM_I[8]
1000010010000CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]CELL[0].MGT_DCM[2]
1000010010011CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]CELL[0].DCM_DCM_I[9]
1000010010101CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]CELL[0].DCM_DCM_I[10]
1000010011001CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]CELL[0].DCM_DCM_I[11]
1000100010000CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]CELL[0].MGT_DCM[3]
1000100010011CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]CELL[0].DCM_DCM_I[12]
1000100010101CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]CELL[0].DCM_DCM_I[13]
1000100011001CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]CELL[0].DCM_DCM_I[14]
1001000010011CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]CELL[0].DCM_DCM_I[15]
1001000010101CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]CELL[0].DCM_DCM_I[16]
1001000011001CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]CELL[0].DCM_DCM_I[17]
1010000010000CELL[0].OUT_CCM_CLKA1D8[1]-CELL[0].OUT_CCM_CLKA1D8[1]
1010000010011CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]CELL[0].DCM_DCM_I[18]
1010000010101CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]CELL[0].DCM_DCM_I[19]
1010000011001CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]CELL[0].DCM_DCM_I[20]
1100000010011CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]CELL[0].DCM_DCM_I[21]
1100000010101CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]CELL[0].DCM_DCM_I[22]
1100000011001CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]CELL[0].DCM_DCM_I[23]
virtex4 CCM wire support CELL[0].HCLK_DCM[0]
Bit
MAIN[0][21][45]
virtex4 CCM wire support CELL[0].HCLK_DCM[1]
Bit
MAIN[0][21][46]
virtex4 CCM wire support CELL[0].HCLK_DCM[2]
Bit
MAIN[0][21][47]
virtex4 CCM wire support CELL[0].HCLK_DCM[3]
Bit
MAIN[0][21][48]
virtex4 CCM wire support CELL[0].HCLK_DCM[4]
Bit
MAIN[0][21][49]
virtex4 CCM wire support CELL[0].HCLK_DCM[5]
Bit
MAIN[0][21][50]
virtex4 CCM wire support CELL[0].HCLK_DCM[6]
Bit
MAIN[0][21][51]
virtex4 CCM wire support CELL[0].HCLK_DCM[7]
Bit
MAIN[0][21][52]
virtex4 CCM wire support CELL[0].GIOB_DCM[0]
Bit
MAIN[0][21][29]
virtex4 CCM wire support CELL[0].GIOB_DCM[1]
Bit
MAIN[0][21][30]
virtex4 CCM wire support CELL[0].GIOB_DCM[2]
Bit
MAIN[0][21][31]
virtex4 CCM wire support CELL[0].GIOB_DCM[3]
Bit
MAIN[0][21][32]
virtex4 CCM wire support CELL[0].GIOB_DCM[4]
Bit
MAIN[0][21][33]
virtex4 CCM wire support CELL[0].GIOB_DCM[5]
Bit
MAIN[0][21][34]
virtex4 CCM wire support CELL[0].GIOB_DCM[6]
Bit
MAIN[0][21][35]
virtex4 CCM wire support CELL[0].GIOB_DCM[7]
Bit
MAIN[0][21][36]
virtex4 CCM wire support CELL[0].GIOB_DCM[8]
Bit
MAIN[0][21][37]
virtex4 CCM wire support CELL[0].GIOB_DCM[9]
Bit
MAIN[0][21][38]
virtex4 CCM wire support CELL[0].GIOB_DCM[10]
Bit
MAIN[0][21][39]
virtex4 CCM wire support CELL[0].GIOB_DCM[11]
Bit
MAIN[0][21][40]
virtex4 CCM wire support CELL[0].GIOB_DCM[12]
Bit
MAIN[0][21][41]
virtex4 CCM wire support CELL[0].GIOB_DCM[13]
Bit
MAIN[0][21][42]
virtex4 CCM wire support CELL[0].GIOB_DCM[14]
Bit
MAIN[0][21][43]
virtex4 CCM wire support CELL[0].GIOB_DCM[15]
Bit
MAIN[0][21][44]
virtex4 CCM wire support CELL[0].MGT_DCM[0]
Bit
MAIN[0][21][53]
virtex4 CCM wire support CELL[0].MGT_DCM[1]
Bit
MAIN[0][21][54]
virtex4 CCM wire support CELL[0].MGT_DCM[2]
Bit
MAIN[0][21][55]
virtex4 CCM wire support CELL[0].MGT_DCM[3]
Bit
MAIN[0][21][56]

Bels CCM

virtex4 CCM bel CCM pins
PinDirectionCCM
virtex4 CCM bel CCM attribute bits
AttributeCCM
VREG_ENABLEMAIN[3][20][28]
VBG_SEL bit 0MAIN[3][20][22]
VBG_SEL bit 1MAIN[3][20][23]
VBG_SEL bit 2MAIN[3][20][24]
VBG_SEL bit 3MAIN[3][20][25]
VBG_PD bit 0MAIN[3][20][26]
VBG_PD bit 1MAIN[3][20][27]
VREG_PHASE_MARGIN bit 0MAIN[3][20][29]
VREG_PHASE_MARGIN bit 1MAIN[3][20][30]
VREG_PHASE_MARGIN bit 2MAIN[3][20][31]

Bels PMCD

virtex4 CCM bel PMCD pins
PinDirectionPMCD[0]PMCD[1]
CLKAinCELL[1].IMUX_SPEC[1]CELL[1].IMUX_SPEC[3]
CLKBinCELL[1].IMUX_SPEC[0]CELL[1].IMUX_SPEC[2]
CLKCinCELL[3].IMUX_SPEC[1]CELL[3].IMUX_SPEC[3]
CLKDinCELL[3].IMUX_SPEC[0]CELL[3].IMUX_SPEC[2]
RELinCELL[0].IMUX_CCM_REL[0] invert by !MAIN[0][18][19]CELL[0].IMUX_CCM_REL[1] invert by !MAIN[1][18][19]
RSTinCELL[0].IMUX_SR_OPTINV[0]CELL[1].IMUX_SR_OPTINV[0]
CLKA1outCELL[0].OUT_CCM_CLKA1[0]CELL[0].OUT_CCM_CLKA1[1]
CLKA1D2outCELL[0].OUT_CCM_CLKA1D2[0]CELL[0].OUT_CCM_CLKA1D2[1]
CLKA1D4outCELL[0].OUT_CCM_CLKA1D4[0]CELL[0].OUT_CCM_CLKA1D4[1]
CLKA1D8outCELL[0].OUT_CCM_CLKA1D8[0]CELL[0].OUT_CCM_CLKA1D8[1]
CLKB1outCELL[0].OUT_CCM_CLKB1[0]CELL[0].OUT_CCM_CLKB1[1]
CLKC1outCELL[0].OUT_CCM_CLKC1[0]CELL[0].OUT_CCM_CLKC1[1]
CLKD1outCELL[0].OUT_CCM_CLKD1[0]CELL[0].OUT_CCM_CLKD1[1]
virtex4 CCM bel PMCD attribute bits
AttributePMCD[0]PMCD[1]
CLKA_ENABLE bit 0MAIN[3][20][0]MAIN[3][20][10]
CLKA_ENABLE bit 1MAIN[3][20][1]MAIN[3][20][11]
CLKA_ENABLE bit 2MAIN[3][20][2]MAIN[3][20][12]
CLKA_ENABLE bit 3MAIN[3][20][3]MAIN[3][20][13]
CLKB_ENABLEMAIN[3][20][4]MAIN[3][20][14]
CLKC_ENABLEMAIN[3][20][5]MAIN[3][20][15]
CLKD_ENABLEMAIN[3][20][6]MAIN[3][20][16]
EN_RELMAIN[3][20][7]MAIN[3][20][17]
RST_DEASSERT_CLK[enum: PMCD_RST_DEASSERT_CLK][enum: PMCD_RST_DEASSERT_CLK]
virtex4 CCM enum PMCD_RST_DEASSERT_CLK
PMCD[0].RST_DEASSERT_CLKMAIN[3][20][9]MAIN[3][20][8]
PMCD[1].RST_DEASSERT_CLKMAIN[3][20][19]MAIN[3][20][18]
CLKA00
CLKB01
CLKC10
CLKD11

Bels DPM

virtex4 CCM bel DPM pins
PinDirectionDPM
REFCLKinCELL[0].IMUX_SPEC[0]
TESTCLK1inCELL[2].IMUX_SPEC[0]
TESTCLK2inCELL[2].IMUX_SPEC[1]
RSTinCELL[0].IMUX_SR_OPTINV[1]
SELSKEWinCELL[1].IMUX_IMUX[4] invert by !MAIN[1][18][22]
ENOSC[0]inCELL[0].IMUX_IMUX[2] invert by !MAIN[0][18][18]
ENOSC[1]inCELL[0].IMUX_IMUX[3] invert by !MAIN[0][18][57]
ENOSC[2]inCELL[0].IMUX_IMUX[4] invert by !MAIN[0][18][22]
FREEZEinCELL[0].IMUX_IMUX[1] invert by !MAIN[0][18][58]
HFSEL[0]inCELL[1].IMUX_IMUX[1] invert by !MAIN[1][18][58]
HFSEL[1]inCELL[1].IMUX_IMUX[2] invert by !MAIN[1][18][18]
HFSEL[2]inCELL[1].IMUX_IMUX[3] invert by !MAIN[1][18][57]
OUTSEL[0]inCELL[0].IMUX_IMUX[5] invert by !MAIN[0][18][61]
OUTSEL[1]inCELL[0].IMUX_IMUX[6] invert by !MAIN[0][18][21]
OUTSEL[2]inCELL[0].IMUX_IMUX[7] invert by !MAIN[0][18][60]
REFCLKOUToutCELL[0].OUT_CCM_REFCLKOUT
OSCOUT1outCELL[0].OUT_CCM_OSCOUT1
OSCOUT2outCELL[0].OUT_CCM_OSCOUT2
CENTERoutCELL[0].OUT_BEST_TMIN[0]
DOUT[0]outCELL[1].OUT_BEST_TMIN[0]
DOUT[1]outCELL[1].OUT_BEST_TMIN[1]
DOUT[2]outCELL[1].OUT_BEST_TMIN[2]
DOUT[3]outCELL[1].OUT_BEST_TMIN[3]
DOUT[4]outCELL[1].OUT_BEST_TMIN[4]
DOUT[5]outCELL[1].OUT_BEST_TMIN[5]
DOUT[6]outCELL[1].OUT_BEST_TMIN[6]
DOUT[7]outCELL[1].OUT_BEST_TMIN[7]
VALIDoutCELL[0].OUT_BEST_TMIN[1]

Bel wires

virtex4 CCM bel wires
WirePins
CELL[0].IMUX_SR_OPTINV[0]PMCD[0].RST
CELL[0].IMUX_SR_OPTINV[1]DPM.RST
CELL[0].IMUX_IMUX[1]DPM.FREEZE
CELL[0].IMUX_IMUX[2]DPM.ENOSC[0]
CELL[0].IMUX_IMUX[3]DPM.ENOSC[1]
CELL[0].IMUX_IMUX[4]DPM.ENOSC[2]
CELL[0].IMUX_IMUX[5]DPM.OUTSEL[0]
CELL[0].IMUX_IMUX[6]DPM.OUTSEL[1]
CELL[0].IMUX_IMUX[7]DPM.OUTSEL[2]
CELL[0].OUT_BEST_TMIN[0]DPM.CENTER
CELL[0].OUT_BEST_TMIN[1]DPM.VALID
CELL[0].IMUX_SPEC[0]DPM.REFCLK
CELL[0].IMUX_CCM_REL[0]PMCD[0].REL
CELL[0].IMUX_CCM_REL[1]PMCD[1].REL
CELL[0].OUT_CCM_CLKA1[0]PMCD[0].CLKA1
CELL[0].OUT_CCM_CLKA1[1]PMCD[1].CLKA1
CELL[0].OUT_CCM_CLKA1D2[0]PMCD[0].CLKA1D2
CELL[0].OUT_CCM_CLKA1D2[1]PMCD[1].CLKA1D2
CELL[0].OUT_CCM_CLKA1D4[0]PMCD[0].CLKA1D4
CELL[0].OUT_CCM_CLKA1D4[1]PMCD[1].CLKA1D4
CELL[0].OUT_CCM_CLKA1D8[0]PMCD[0].CLKA1D8
CELL[0].OUT_CCM_CLKA1D8[1]PMCD[1].CLKA1D8
CELL[0].OUT_CCM_CLKB1[0]PMCD[0].CLKB1
CELL[0].OUT_CCM_CLKB1[1]PMCD[1].CLKB1
CELL[0].OUT_CCM_CLKC1[0]PMCD[0].CLKC1
CELL[0].OUT_CCM_CLKC1[1]PMCD[1].CLKC1
CELL[0].OUT_CCM_CLKD1[0]PMCD[0].CLKD1
CELL[0].OUT_CCM_CLKD1[1]PMCD[1].CLKD1
CELL[0].OUT_CCM_REFCLKOUTDPM.REFCLKOUT
CELL[0].OUT_CCM_OSCOUT1DPM.OSCOUT1
CELL[0].OUT_CCM_OSCOUT2DPM.OSCOUT2
CELL[1].IMUX_SR_OPTINV[0]PMCD[1].RST
CELL[1].IMUX_IMUX[1]DPM.HFSEL[0]
CELL[1].IMUX_IMUX[2]DPM.HFSEL[1]
CELL[1].IMUX_IMUX[3]DPM.HFSEL[2]
CELL[1].IMUX_IMUX[4]DPM.SELSKEW
CELL[1].OUT_BEST_TMIN[0]DPM.DOUT[0]
CELL[1].OUT_BEST_TMIN[1]DPM.DOUT[1]
CELL[1].OUT_BEST_TMIN[2]DPM.DOUT[2]
CELL[1].OUT_BEST_TMIN[3]DPM.DOUT[3]
CELL[1].OUT_BEST_TMIN[4]DPM.DOUT[4]
CELL[1].OUT_BEST_TMIN[5]DPM.DOUT[5]
CELL[1].OUT_BEST_TMIN[6]DPM.DOUT[6]
CELL[1].OUT_BEST_TMIN[7]DPM.DOUT[7]
CELL[1].IMUX_SPEC[0]PMCD[0].CLKB
CELL[1].IMUX_SPEC[1]PMCD[0].CLKA
CELL[1].IMUX_SPEC[2]PMCD[1].CLKB
CELL[1].IMUX_SPEC[3]PMCD[1].CLKA
CELL[2].IMUX_SPEC[0]DPM.TESTCLK1
CELL[2].IMUX_SPEC[1]DPM.TESTCLK2
CELL[3].IMUX_SPEC[0]PMCD[0].CLKD
CELL[3].IMUX_SPEC[1]PMCD[0].CLKC
CELL[3].IMUX_SPEC[2]PMCD[1].CLKD
CELL[3].IMUX_SPEC[3]PMCD[1].CLKC

Bitstream

virtex4 CCM rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B79 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B76 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B73 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B70 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B68 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B65 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - DPM: !invert OUTSEL[0] - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - DPM: !invert OUTSEL[2] - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - DPM: !invert FREEZE - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - DPM: !invert ENOSC[1] - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[0].MGT_DCM[3]) bit 0 - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 9 SPEC_INT: wire support (CELL[0].MGT_DCM[2]) bit 0 - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 7 SPEC_INT: wire support (CELL[0].MGT_DCM[1]) bit 0 - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 8 SPEC_INT: wire support (CELL[0].MGT_DCM[0]) bit 0 - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 6 SPEC_INT: wire support (CELL[0].HCLK_DCM[7]) bit 0 - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 0 SPEC_INT: wire support (CELL[0].HCLK_DCM[6]) bit 0 - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 2 SPEC_INT: wire support (CELL[0].HCLK_DCM[5]) bit 0 - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 1 SPEC_INT: wire support (CELL[0].HCLK_DCM[4]) bit 0 - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 5 SPEC_INT: wire support (CELL[0].HCLK_DCM[3]) bit 0 - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 3 SPEC_INT: wire support (CELL[0].HCLK_DCM[2]) bit 0 - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[3] bit 4 SPEC_INT: wire support (CELL[0].HCLK_DCM[1]) bit 0 - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 9 SPEC_INT: wire support (CELL[0].HCLK_DCM[0]) bit 0 - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 7 SPEC_INT: wire support (CELL[0].GIOB_DCM[15]) bit 0 - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 8 SPEC_INT: wire support (CELL[0].GIOB_DCM[14]) bit 0 - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 6 SPEC_INT: wire support (CELL[0].GIOB_DCM[13]) bit 0 - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 0 SPEC_INT: wire support (CELL[0].GIOB_DCM[12]) bit 0 - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 2 SPEC_INT: wire support (CELL[0].GIOB_DCM[11]) bit 0 - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 1 SPEC_INT: wire support (CELL[0].GIOB_DCM[10]) bit 0 - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 5 SPEC_INT: wire support (CELL[0].GIOB_DCM[9]) bit 0 - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 3 SPEC_INT: wire support (CELL[0].GIOB_DCM[8]) bit 0 - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[2] bit 4 SPEC_INT: wire support (CELL[0].GIOB_DCM[7]) bit 0 - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 9 SPEC_INT: wire support (CELL[0].GIOB_DCM[6]) bit 0 - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 7 SPEC_INT: wire support (CELL[0].GIOB_DCM[5]) bit 0 - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 8 SPEC_INT: wire support (CELL[0].GIOB_DCM[4]) bit 0 - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 6 SPEC_INT: wire support (CELL[0].GIOB_DCM[3]) bit 0 - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 0 SPEC_INT: wire support (CELL[0].GIOB_DCM[2]) bit 0 - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 2 SPEC_INT: wire support (CELL[0].GIOB_DCM[1]) bit 0 - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 1 SPEC_INT: wire support (CELL[0].GIOB_DCM[0]) bit 0 - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 5 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 12 - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 3 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 4 - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[1] bit 4 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 7 - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 9 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 6 - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 7 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 5 - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 8 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 11 - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - DPM: !invert ENOSC[2] - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 6 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 10 - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - DPM: !invert OUTSEL[1] - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 0 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 9 - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 2 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 8 - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - PMCD[0]: !invert REL - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 1 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 2 - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - DPM: !invert ENOSC[0] - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 5 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 1 - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 3 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 3 - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[0] bit 4 SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 0 - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex4 CCM rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B79 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B76 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B73 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B70 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B68 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B65 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - DPM: !invert HFSEL[0] - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - DPM: !invert HFSEL[2] - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 12 - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 0 - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 3 - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 2 - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 1 - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 11 - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 10 - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 9 - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 8 - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 7 - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 6 - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 5 - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 9 SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 4 - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 7 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 12 - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 8 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 0 - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 6 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 3 - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 0 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 2 - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 2 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 1 - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 1 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 11 - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 5 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 10 - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 3 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 9 - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[7] bit 4 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 8 - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 9 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 7 - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 7 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 6 - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 8 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 5 - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 6 SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 4 - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 0 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 12 - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 2 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 0 - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 1 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 3 - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - DPM: !invert SELSKEW - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 5 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 2 - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 3 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 1 - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[6] bit 4 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 11 - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - PMCD[1]: !invert REL - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 9 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 10 - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - DPM: !invert HFSEL[1] - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 7 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 9 - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 8 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 8 - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 6 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 7 - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 0 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 6 - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 2 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 5 - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 1 SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 4 - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 5 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 12 - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 3 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 0 - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[5] bit 4 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 3 - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 9 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 2 - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 7 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 1 - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 8 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 11 - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 6 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 10 - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 0 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 9 - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 2 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 8 - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 1 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 7 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 5 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 6 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 3 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 5 - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[4] bit 4 SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 4 - - - - - - - -
virtex4 CCM rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B79 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B76 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B73 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B70 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B68 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B65 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 12 - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 0 - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 3 - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 2 - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 1 - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 11 - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 10 - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 9 - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 8 - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 7 - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 6 - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 5 - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 9 SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 4 - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 7 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 12 - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 8 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 0 - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 6 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 3 - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 0 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 2 - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 2 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 1 - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 1 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 11 - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 5 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 10 - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 3 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 9 - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[11] bit 4 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 8 - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 9 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 7 - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 7 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 6 - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 8 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 5 - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 6 SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 4 - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 12 - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 0 - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 3 - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 5 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 2 - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 1 - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[10] bit 4 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 11 - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 9 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 10 - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 7 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 9 - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 8 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 8 - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 6 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 7 - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 6 - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 5 - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 4 - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 5 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 12 - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 0 - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[9] bit 4 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 3 - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 9 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 2 - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 7 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 1 - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 8 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 11 - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 6 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 10 - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 9 - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 8 - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 7 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 5 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 6 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 5 - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].OUT_DCM[8] bit 4 SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 4 - - - - - - - -
virtex4 CCM rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B79 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B76 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B73 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B70 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B68 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B65 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 12 - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 0 - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 3 - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 2 - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 1 - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 11 - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 10 - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 9 - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 8 - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 7 - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 6 - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 5 - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 4 - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 12 - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 0 - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 3 - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 2 - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 1 - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 11 - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 10 - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - CCM: VREG_PHASE_MARGIN bit 2 SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 9 - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - CCM: VREG_PHASE_MARGIN bit 1 SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 8 - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - CCM: VREG_PHASE_MARGIN bit 0 SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 7 - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - CCM: VREG_ENABLE SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 6 - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - CCM: VBG_PD bit 1 SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 5 - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - CCM: VBG_PD bit 0 SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 4 - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - CCM: VBG_SEL bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 12 - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - CCM: VBG_SEL bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 0 - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - CCM: VBG_SEL bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 3 - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - CCM: VBG_SEL bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 2 - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_CCM_REL[1] bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 1 - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_CCM_REL[0] bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 11 - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - PMCD[1]: RST_DEASSERT_CLK bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 10 - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - PMCD[1]: RST_DEASSERT_CLK bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 9 - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - PMCD[1]: EN_REL SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 8 - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKD_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 7 - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKC_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 6 - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKB_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 5 - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKA_ENABLE bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 4 - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKA_ENABLE bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 12 - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKA_ENABLE bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 0 - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - PMCD[1]: CLKA_ENABLE bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 3 - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - PMCD[0]: RST_DEASSERT_CLK bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 2 - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - PMCD[0]: RST_DEASSERT_CLK bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 1 - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - PMCD[0]: EN_REL SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 11 - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKD_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 10 - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKC_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 9 - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKB_ENABLE SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 8 - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKA_ENABLE bit 3 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 7 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKA_ENABLE bit 2 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 6 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKA_ENABLE bit 1 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 5 - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - PMCD[0]: CLKA_ENABLE bit 0 SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 4 - - - - - - - -