Digital Clock Managers

Tile DCM

Cells: 4

Switchbox SPEC_INT

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[0]
Bits								Destination
MAIN[0][21][60]	MAIN[0][21][58]	MAIN[0][21][59]	MAIN[0][21][57]	MAIN[0][21][55]	MAIN[0][21][54]	MAIN[0][21][56]	MAIN[3][21][24]	CELL[0].DCM_DCM_O[0]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[0]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[1]
Bits								Destination
MAIN[0][21][67]	MAIN[0][21][65]	MAIN[0][21][66]	MAIN[0][21][64]	MAIN[0][21][62]	MAIN[0][21][61]	MAIN[0][21][63]	MAIN[3][21][25]	CELL[0].DCM_DCM_O[1]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[1]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[2]
Bits								Destination
MAIN[0][21][74]	MAIN[0][21][72]	MAIN[0][21][73]	MAIN[0][21][71]	MAIN[0][21][69]	MAIN[0][21][68]	MAIN[0][21][70]	MAIN[3][21][26]	CELL[0].DCM_DCM_O[2]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[2]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[3]
Bits								Destination
MAIN[1][21][3]	MAIN[1][21][1]	MAIN[1][21][2]	MAIN[1][21][0]	MAIN[0][21][76]	MAIN[0][21][75]	MAIN[0][21][77]	MAIN[3][21][27]	CELL[0].DCM_DCM_O[3]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[3]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[4]
Bits								Destination
MAIN[1][21][10]	MAIN[1][21][8]	MAIN[1][21][9]	MAIN[1][21][7]	MAIN[1][21][5]	MAIN[1][21][4]	MAIN[1][21][6]	MAIN[3][21][28]	CELL[0].DCM_DCM_O[4]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[4]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[5]
Bits								Destination
MAIN[1][21][17]	MAIN[1][21][15]	MAIN[1][21][16]	MAIN[1][21][14]	MAIN[1][21][12]	MAIN[1][21][11]	MAIN[1][21][13]	MAIN[3][21][29]	CELL[0].DCM_DCM_O[5]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[5]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[6]
Bits								Destination
MAIN[1][21][24]	MAIN[1][21][22]	MAIN[1][21][23]	MAIN[1][21][21]	MAIN[1][21][19]	MAIN[1][21][18]	MAIN[1][21][20]	MAIN[3][21][30]	CELL[0].DCM_DCM_O[6]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[6]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[7]
Bits								Destination
MAIN[1][21][31]	MAIN[1][21][29]	MAIN[1][21][30]	MAIN[1][21][28]	MAIN[1][21][26]	MAIN[1][21][25]	MAIN[1][21][27]	MAIN[3][21][31]	CELL[0].DCM_DCM_O[7]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[7]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[8]
Bits								Destination
MAIN[1][21][38]	MAIN[1][21][36]	MAIN[1][21][37]	MAIN[1][21][35]	MAIN[1][21][33]	MAIN[1][21][32]	MAIN[1][21][34]	MAIN[3][21][32]	CELL[0].DCM_DCM_O[8]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[8]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[9]
Bits								Destination
MAIN[1][21][45]	MAIN[1][21][43]	MAIN[1][21][44]	MAIN[1][21][42]	MAIN[1][21][40]	MAIN[1][21][39]	MAIN[1][21][41]	MAIN[3][21][33]	CELL[0].DCM_DCM_O[9]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[9]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[10]
Bits								Destination
MAIN[1][21][52]	MAIN[1][21][50]	MAIN[1][21][51]	MAIN[1][21][49]	MAIN[1][21][47]	MAIN[1][21][46]	MAIN[1][21][48]	MAIN[3][21][34]	CELL[0].DCM_DCM_O[10]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[10]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[11]
Bits								Destination
MAIN[1][21][59]	MAIN[1][21][57]	MAIN[1][21][58]	MAIN[1][21][56]	MAIN[1][21][54]	MAIN[1][21][53]	MAIN[1][21][55]	MAIN[3][21][35]	CELL[0].DCM_DCM_O[11]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[11]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[12]
Bits								Destination
MAIN[1][21][66]	MAIN[1][21][64]	MAIN[1][21][65]	MAIN[1][21][63]	MAIN[1][21][61]	MAIN[1][21][60]	MAIN[1][21][62]	MAIN[3][21][36]	CELL[0].DCM_DCM_O[12]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[12]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[13]
Bits								Destination
MAIN[2][21][1]	MAIN[1][21][71]	MAIN[2][21][0]	MAIN[1][21][70]	MAIN[1][21][68]	MAIN[1][21][67]	MAIN[1][21][69]	MAIN[3][21][37]	CELL[0].DCM_DCM_O[13]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[13]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[14]
Bits								Destination
MAIN[2][21][8]	MAIN[2][21][6]	MAIN[2][21][7]	MAIN[2][21][5]	MAIN[2][21][3]	MAIN[2][21][2]	MAIN[2][21][4]	MAIN[3][21][38]	CELL[0].DCM_DCM_O[14]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[14]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[15]
Bits								Destination
MAIN[2][21][15]	MAIN[2][21][13]	MAIN[2][21][14]	MAIN[2][21][12]	MAIN[2][21][10]	MAIN[2][21][9]	MAIN[2][21][11]	MAIN[3][21][39]	CELL[0].DCM_DCM_O[15]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[15]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[16]
Bits								Destination
MAIN[2][21][22]	MAIN[2][21][20]	MAIN[2][21][21]	MAIN[2][21][19]	MAIN[2][21][17]	MAIN[2][21][16]	MAIN[2][21][18]	MAIN[3][21][40]	CELL[0].DCM_DCM_O[16]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[16]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[17]
Bits								Destination
MAIN[2][21][29]	MAIN[2][21][27]	MAIN[2][21][28]	MAIN[2][21][26]	MAIN[2][21][24]	MAIN[2][21][23]	MAIN[2][21][25]	MAIN[3][21][41]	CELL[0].DCM_DCM_O[17]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[17]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[18]
Bits								Destination
MAIN[2][21][36]	MAIN[2][21][34]	MAIN[2][21][35]	MAIN[2][21][33]	MAIN[2][21][31]	MAIN[2][21][30]	MAIN[2][21][32]	MAIN[3][21][42]	CELL[0].DCM_DCM_O[18]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[18]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[19]
Bits								Destination
MAIN[2][21][43]	MAIN[2][21][41]	MAIN[2][21][42]	MAIN[2][21][40]	MAIN[2][21][38]	MAIN[2][21][37]	MAIN[2][21][39]	MAIN[3][21][43]	CELL[0].DCM_DCM_O[19]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[19]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[20]
Bits								Destination
MAIN[3][21][2]	MAIN[3][21][0]	MAIN[3][21][1]	MAIN[2][21][47]	MAIN[2][21][45]	MAIN[2][21][44]	MAIN[2][21][46]	MAIN[3][21][44]	CELL[0].DCM_DCM_O[20]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[20]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[21]
Bits								Destination
MAIN[3][21][9]	MAIN[3][21][7]	MAIN[3][21][8]	MAIN[3][21][6]	MAIN[3][21][4]	MAIN[3][21][3]	MAIN[3][21][5]	MAIN[3][21][45]	CELL[0].DCM_DCM_O[21]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[21]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[22]
Bits								Destination
MAIN[3][21][16]	MAIN[3][21][14]	MAIN[3][21][15]	MAIN[3][21][13]	MAIN[3][21][11]	MAIN[3][21][10]	MAIN[3][21][12]	MAIN[3][21][46]	CELL[0].DCM_DCM_O[22]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[22]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes DCM_DCM_O[23]
Bits								Destination
MAIN[3][21][23]	MAIN[3][21][21]	MAIN[3][21][22]	MAIN[3][21][20]	MAIN[3][21][18]	MAIN[3][21][17]	MAIN[3][21][19]	MAIN[3][21][47]	CELL[0].DCM_DCM_O[23]
								Source
0	0	0	0	0	0	0	0	CELL[0].DCM_DCM_I[23]
0	0	1	0	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	1	0	0	1	0	1	CELL[0].OUT_DCM[5]
0	0	1	0	1	0	0	1	CELL[0].OUT_DCM_LOCKED
0	0	1	1	0	0	0	1	CELL[0].OUT_DCM[6]
0	1	0	0	0	0	1	1	CELL[0].OUT_DCM[3]
0	1	0	0	0	1	0	1	CELL[0].OUT_DCM[1]
0	1	0	0	1	0	0	1	CELL[0].OUT_DCM[2]
0	1	0	1	0	0	0	1	CELL[0].OUT_DCM[4]
1	0	0	0	0	0	1	1	CELL[0].OUT_DCM[9]
1	0	0	0	0	1	0	1	CELL[0].OUT_DCM[7]
1	0	0	0	1	0	0	1	CELL[0].OUT_DCM[8]
1	0	0	1	0	0	0	1	CELL[0].OUT_DCM[10]

virtex4 DCM switchbox SPEC_INT muxes IMUX_SPEC[0]
Bits											Destination
MAIN[0][21][14]	MAIN[0][21][16]	MAIN[0][21][15]	MAIN[0][21][13]	MAIN[0][21][12]	MAIN[0][21][11]	MAIN[0][21][18]	MAIN[0][21][19]	MAIN[0][21][20]	MAIN[0][21][17]	MAIN[0][21][21]	CELL[2].IMUX_SPEC[0]
MAIN[0][21][3]	MAIN[0][21][5]	MAIN[0][21][4]	MAIN[0][21][2]	MAIN[0][21][1]	MAIN[0][21][0]	MAIN[0][21][7]	MAIN[0][21][8]	MAIN[0][21][9]	MAIN[0][21][6]	MAIN[0][21][10]	CELL[3].IMUX_SPEC[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	CELL[0].HCLK_DCM[0]
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_CLK_OPTINV[3]
0	0	0	0	0	0	0	0	1	1	0	CELL[0].HCLK_DCM[3]
0	0	0	0	0	0	0	0	1	1	1	CELL[0].IMUX_CLK_OPTINV[0]
0	0	0	0	0	0	0	1	0	1	0	CELL[0].HCLK_DCM[2]
0	0	0	0	0	0	0	1	0	1	1	CELL[0].IMUX_CLK_OPTINV[1]
0	0	0	0	0	0	1	0	0	1	0	CELL[0].HCLK_DCM[1]
0	0	0	0	0	0	1	0	0	1	1	CELL[0].IMUX_CLK_OPTINV[2]
0	0	0	0	1	1	0	0	0	0	0	CELL[0].HCLK_DCM[4]
0	0	0	0	1	1	0	0	1	1	0	CELL[0].HCLK_DCM[7]
0	0	0	0	1	1	0	1	0	1	0	CELL[0].HCLK_DCM[6]
0	0	0	0	1	1	1	0	0	1	0	CELL[0].HCLK_DCM[5]
0	0	0	1	0	1	0	0	0	0	0	CELL[0].GIOB_DCM[0]
0	0	0	1	0	1	0	0	0	0	1	CELL[0].MGT_DCM[3]
0	0	0	1	0	1	0	0	1	1	0	CELL[0].GIOB_DCM[3]
0	0	0	1	0	1	0	1	0	1	0	CELL[0].GIOB_DCM[2]
0	0	0	1	0	1	1	0	0	1	0	CELL[0].GIOB_DCM[1]
0	0	0	1	0	1	1	0	0	1	1	CELL[0].MGT_DCM[2]
0	0	1	0	0	1	0	0	0	0	1	CELL[0].MGT_DCM[0]
0	0	1	0	0	1	0	0	1	1	0	CELL[0].GIOB_DCM[6]
0	0	1	0	0	1	0	0	1	1	1	CELL[0].GIOB_DCM[15]
0	0	1	0	0	1	0	1	0	1	0	CELL[0].GIOB_DCM[5]
0	0	1	0	0	1	0	1	0	1	1	CELL[0].DCM_DCM_O[0]
0	0	1	0	0	1	1	0	0	1	0	CELL[0].GIOB_DCM[4]
0	0	1	0	0	1	1	0	0	1	1	CELL[0].DCM_DCM_O[1]
0	1	0	0	0	1	0	0	0	0	0	CELL[0].GIOB_DCM[7]
0	1	0	0	0	1	0	0	0	0	1	CELL[0].GIOB_DCM[14]
0	1	0	0	0	1	0	0	1	1	0	CELL[0].GIOB_DCM[10]
0	1	0	0	0	1	0	0	1	1	1	CELL[0].GIOB_DCM[11]
0	1	0	0	0	1	0	1	0	1	0	CELL[0].GIOB_DCM[9]
0	1	0	0	0	1	0	1	0	1	1	CELL[0].GIOB_DCM[12]
0	1	0	0	0	1	1	0	0	1	0	CELL[0].GIOB_DCM[8]
0	1	0	0	0	1	1	0	0	1	1	CELL[0].GIOB_DCM[13]
1	0	0	0	0	1	0	0	1	1	1	CELL[0].MGT_DCM[1]

virtex4 DCM wire support CELL[0].HCLK_DCM[0]
Bit
MAIN[0][21][22]

virtex4 DCM wire support CELL[0].HCLK_DCM[1]
Bit
MAIN[0][21][23]

virtex4 DCM wire support CELL[0].HCLK_DCM[2]
Bit
MAIN[0][21][24]

virtex4 DCM wire support CELL[0].HCLK_DCM[3]
Bit
MAIN[0][21][25]

virtex4 DCM wire support CELL[0].HCLK_DCM[4]
Bit
MAIN[0][21][26]

virtex4 DCM wire support CELL[0].HCLK_DCM[5]
Bit
MAIN[0][21][27]

virtex4 DCM wire support CELL[0].HCLK_DCM[6]
Bit
MAIN[0][21][28]

virtex4 DCM wire support CELL[0].HCLK_DCM[7]
Bit
MAIN[0][21][29]

virtex4 DCM wire support CELL[0].GIOB_DCM[0]
Bit
MAIN[0][21][30]

virtex4 DCM wire support CELL[0].GIOB_DCM[1]
Bit
MAIN[0][21][31]

virtex4 DCM wire support CELL[0].GIOB_DCM[2]
Bit
MAIN[0][21][32]

virtex4 DCM wire support CELL[0].GIOB_DCM[3]
Bit
MAIN[0][21][33]

virtex4 DCM wire support CELL[0].GIOB_DCM[4]
Bit
MAIN[0][21][34]

virtex4 DCM wire support CELL[0].GIOB_DCM[5]
Bit
MAIN[0][21][35]

virtex4 DCM wire support CELL[0].GIOB_DCM[6]
Bit
MAIN[0][21][36]

virtex4 DCM wire support CELL[0].GIOB_DCM[7]
Bit
MAIN[0][21][37]

virtex4 DCM wire support CELL[0].GIOB_DCM[8]
Bit
MAIN[0][21][38]

virtex4 DCM wire support CELL[0].GIOB_DCM[9]
Bit
MAIN[0][21][39]

virtex4 DCM wire support CELL[0].GIOB_DCM[10]
Bit
MAIN[0][21][40]

virtex4 DCM wire support CELL[0].GIOB_DCM[11]
Bit
MAIN[0][21][41]

virtex4 DCM wire support CELL[0].GIOB_DCM[12]
Bit
MAIN[0][21][42]

virtex4 DCM wire support CELL[0].GIOB_DCM[13]
Bit
MAIN[0][21][43]

virtex4 DCM wire support CELL[0].GIOB_DCM[14]
Bit
MAIN[0][21][44]

virtex4 DCM wire support CELL[0].GIOB_DCM[15]
Bit
MAIN[0][21][45]

virtex4 DCM wire support CELL[0].MGT_DCM[0]
Bit
MAIN[0][21][46]

virtex4 DCM wire support CELL[0].MGT_DCM[1]
Bit
MAIN[0][21][47]

virtex4 DCM wire support CELL[0].MGT_DCM[2]
Bit
MAIN[0][21][48]

virtex4 DCM wire support CELL[0].MGT_DCM[3]
Bit
MAIN[0][21][49]

Bels DCM_V4

virtex4 DCM bel DCM_V4 pins
Pin	Direction	DCM[0]
CLKIN	in	CELL[3].IMUX_SPEC[0]
CLKFB	in	CELL[2].IMUX_SPEC[0]
RST	in	CELL[3].IMUX_SR_OPTINV[0]
PSCLK	in	CELL[2].IMUX_CLK_OPTINV[1]
PSEN	in	CELL[0].IMUX_IMUX[4] invert by !MAIN[0][18][22]
PSINCDEC	in	CELL[0].IMUX_IMUX[3] invert by !MAIN[0][18][57]
DCLK	in	CELL[2].IMUX_CLK_OPTINV[0]
DEN	in	CELL[2].IMUX_CE_OPTINV[1]
DWE	in	CELL[2].IMUX_CE_OPTINV[0]
DADDR[0]	in	CELL[3].IMUX_IMUX[0] invert by !MAIN[3][18][19]
DADDR[1]	in	CELL[3].IMUX_IMUX[1] invert by !MAIN[3][18][58]
DADDR[2]	in	CELL[3].IMUX_IMUX[2] invert by !MAIN[3][18][18]
DADDR[3]	in	CELL[3].IMUX_IMUX[3] invert by !MAIN[3][18][57]
DADDR[4]	in	CELL[3].IMUX_IMUX[4] invert by !MAIN[3][18][22]
DADDR[5]	in	CELL[3].IMUX_IMUX[5] invert by !MAIN[3][18][61]
DADDR[6]	in	CELL[3].IMUX_IMUX[6] invert by !MAIN[3][18][21]
DI[0]	in	CELL[2].IMUX_IMUX[0] invert by !MAIN[2][18][19]
DI[1]	in	CELL[2].IMUX_IMUX[1] invert by !MAIN[2][18][58]
DI[2]	in	CELL[2].IMUX_IMUX[2] invert by !MAIN[2][18][18]
DI[3]	in	CELL[2].IMUX_IMUX[3] invert by !MAIN[2][18][57]
DI[4]	in	CELL[2].IMUX_IMUX[4] invert by !MAIN[2][18][22]
DI[5]	in	CELL[2].IMUX_IMUX[5] invert by !MAIN[2][18][61]
DI[6]	in	CELL[2].IMUX_IMUX[6] invert by !MAIN[2][18][21]
DI[7]	in	CELL[2].IMUX_IMUX[7] invert by !MAIN[2][18][60]
DI[8]	in	CELL[1].IMUX_IMUX[0] invert by !MAIN[1][18][19]
DI[9]	in	CELL[1].IMUX_IMUX[1] invert by !MAIN[1][18][58]
DI[10]	in	CELL[1].IMUX_IMUX[2] invert by !MAIN[1][18][18]
DI[11]	in	CELL[1].IMUX_IMUX[3] invert by !MAIN[1][18][57]
DI[12]	in	CELL[1].IMUX_IMUX[4] invert by !MAIN[1][18][22]
DI[13]	in	CELL[1].IMUX_IMUX[5] invert by !MAIN[1][18][61]
DI[14]	in	CELL[1].IMUX_IMUX[6] invert by !MAIN[1][18][21]
DI[15]	in	CELL[1].IMUX_IMUX[7] invert by !MAIN[1][18][60]
FREEZE_DLL	in	CELL[1].IMUX_SR_OPTINV[0]
FREEZE_DFS	in	CELL[1].IMUX_SR_OPTINV[1]
CTLMODE	in	CELL[0].IMUX_CE_OPTINV[0]
CTLGO	in	CELL[0].IMUX_IMUX[7] invert by !MAIN[0][18][60]
CTLOSC1	in	CELL[0].IMUX_IMUX[5] invert by !MAIN[0][18][61]
CTLOSC2	in	CELL[0].IMUX_IMUX[6] invert by !MAIN[0][18][21]
CTLSEL[0]	in	CELL[0].IMUX_IMUX[0] invert by !MAIN[0][18][19]
CTLSEL[1]	in	CELL[0].IMUX_IMUX[1] invert by !MAIN[0][18][58]
CTLSEL[2]	in	CELL[0].IMUX_IMUX[2] invert by !MAIN[0][18][18]
CLK0	out	CELL[0].OUT_DCM[4], CELL[2].OUT_BEST_TMIN[0]
CLK90	out	CELL[0].OUT_DCM[6], CELL[2].OUT_BEST_TMIN[2]
CLK180	out	CELL[0].OUT_DCM[5], CELL[2].OUT_BEST_TMIN[1]
CLK270	out	CELL[0].OUT_DCM[7], CELL[1].OUT_BEST_TMIN[0]
CLK2X	out	CELL[0].OUT_DCM[9], CELL[1].OUT_BEST_TMIN[2]
CLK2X180	out	CELL[0].OUT_DCM[8], CELL[1].OUT_BEST_TMIN[1]
CLKDV	out	CELL[0].OUT_BEST_TMIN[0], CELL[0].OUT_DCM[10]
CLKFX	out	CELL[0].OUT_DCM[2], CELL[3].OUT_BEST_TMIN[1]
CLKFX180	out	CELL[0].OUT_DCM[3], CELL[3].OUT_BEST_TMIN[2]
CONCUR	out	CELL[0].OUT_DCM[1], CELL[3].OUT_BEST_TMIN[0]
LOCKED	out	CELL[0].OUT_DCM_LOCKED, CELL[3].OUT_SEC_TMIN[0]
PSDONE	out	CELL[3].OUT_SEC_TMIN[1]
DRDY	out	CELL[3].OUT_SEC_TMIN[2]
DO[0]	out	CELL[3].OUT_BEST_TMIN[4]
DO[1]	out	CELL[3].OUT_BEST_TMIN[5]
DO[2]	out	CELL[3].OUT_BEST_TMIN[6]
DO[3]	out	CELL[3].OUT_BEST_TMIN[7]
DO[4]	out	CELL[2].OUT_BEST_TMIN[4]
DO[5]	out	CELL[2].OUT_BEST_TMIN[5]
DO[6]	out	CELL[2].OUT_BEST_TMIN[6]
DO[7]	out	CELL[2].OUT_BEST_TMIN[7]
DO[8]	out	CELL[1].OUT_BEST_TMIN[4]
DO[9]	out	CELL[1].OUT_BEST_TMIN[5]
DO[10]	out	CELL[1].OUT_BEST_TMIN[6]
DO[11]	out	CELL[1].OUT_BEST_TMIN[7]
DO[12]	out	CELL[0].OUT_BEST_TMIN[4]
DO[13]	out	CELL[0].OUT_BEST_TMIN[5]
DO[14]	out	CELL[0].OUT_BEST_TMIN[6]
DO[15]	out	CELL[0].OUT_BEST_TMIN[7]

virtex4 DCM bel DCM_V4 attribute bits
Attribute	DCM[0]
DRP[0] bit 0	MAIN[0][20][1]
DRP[0] bit 1	MAIN[0][20][2]
DRP[0] bit 2	MAIN[0][20][3]
DRP[0] bit 3	MAIN[0][20][4]
DRP[0] bit 4	MAIN[0][20][5]
DRP[0] bit 5	MAIN[0][20][6]
DRP[0] bit 6	MAIN[0][20][7]
DRP[0] bit 7	MAIN[0][20][8]
DRP[0] bit 8	MAIN[0][20][9]
DRP[0] bit 9	MAIN[0][20][10]
DRP[0] bit 10	MAIN[0][20][11]
DRP[0] bit 11	MAIN[0][20][12]
DRP[0] bit 12	MAIN[0][20][13]
DRP[0] bit 13	MAIN[0][20][14]
DRP[0] bit 14	MAIN[0][20][15]
DRP[0] bit 15	MAIN[0][20][16]
DRP[1] bit 0	MAIN[0][20][21]
DRP[1] bit 1	MAIN[0][20][22]
DRP[1] bit 2	MAIN[0][20][23]
DRP[1] bit 3	MAIN[0][20][24]
DRP[1] bit 4	MAIN[0][20][25]
DRP[1] bit 5	MAIN[0][20][26]
DRP[1] bit 6	MAIN[0][20][27]
DRP[1] bit 7	MAIN[0][20][28]
DRP[1] bit 8	MAIN[0][20][29]
DRP[1] bit 9	MAIN[0][20][30]
DRP[1] bit 10	MAIN[0][20][31]
DRP[1] bit 11	MAIN[0][20][32]
DRP[1] bit 12	MAIN[0][20][33]
DRP[1] bit 13	MAIN[0][20][34]
DRP[1] bit 14	MAIN[0][20][35]
DRP[1] bit 15	MAIN[0][20][36]
DRP[2] bit 0	MAIN[0][20][41]
DRP[2] bit 1	MAIN[0][20][42]
DRP[2] bit 2	MAIN[0][20][43]
DRP[2] bit 3	MAIN[0][20][44]
DRP[2] bit 4	MAIN[0][20][45]
DRP[2] bit 5	MAIN[0][20][46]
DRP[2] bit 6	MAIN[0][20][47]
DRP[2] bit 7	MAIN[0][20][48]
DRP[2] bit 8	MAIN[0][20][49]
DRP[2] bit 9	MAIN[0][20][50]
DRP[2] bit 10	MAIN[0][20][51]
DRP[2] bit 11	MAIN[0][20][52]
DRP[2] bit 12	MAIN[0][20][53]
DRP[2] bit 13	MAIN[0][20][54]
DRP[2] bit 14	MAIN[0][20][55]
DRP[2] bit 15	MAIN[0][20][56]
DRP[3] bit 0	MAIN[0][20][61]
DRP[3] bit 1	MAIN[0][20][62]
DRP[3] bit 2	MAIN[0][20][63]
DRP[3] bit 3	MAIN[0][20][64]
DRP[3] bit 4	MAIN[0][20][65]
DRP[3] bit 5	MAIN[0][20][66]
DRP[3] bit 6	MAIN[0][20][67]
DRP[3] bit 7	MAIN[0][20][68]
DRP[3] bit 8	MAIN[0][20][69]
DRP[3] bit 9	MAIN[0][20][70]
DRP[3] bit 10	MAIN[0][20][71]
DRP[3] bit 11	MAIN[0][20][72]
DRP[3] bit 12	MAIN[0][20][73]
DRP[3] bit 13	MAIN[0][20][74]
DRP[3] bit 14	MAIN[0][20][75]
DRP[3] bit 15	MAIN[0][20][76]
DRP[4] bit 0	MAIN[1][20][1]
DRP[4] bit 1	MAIN[1][20][2]
DRP[4] bit 2	MAIN[1][20][3]
DRP[4] bit 3	MAIN[1][20][4]
DRP[4] bit 4	MAIN[1][20][5]
DRP[4] bit 5	MAIN[1][20][6]
DRP[4] bit 6	MAIN[1][20][7]
DRP[4] bit 7	MAIN[1][20][8]
DRP[4] bit 8	MAIN[1][20][9]
DRP[4] bit 9	MAIN[1][20][10]
DRP[4] bit 10	MAIN[1][20][11]
DRP[4] bit 11	MAIN[1][20][12]
DRP[4] bit 12	MAIN[1][20][13]
DRP[4] bit 13	MAIN[1][20][14]
DRP[4] bit 14	MAIN[1][20][15]
DRP[4] bit 15	MAIN[1][20][16]
DRP[5] bit 0	MAIN[1][20][21]
DRP[5] bit 1	MAIN[1][20][22]
DRP[5] bit 2	MAIN[1][20][23]
DRP[5] bit 3	MAIN[1][20][24]
DRP[5] bit 4	MAIN[1][20][25]
DRP[5] bit 5	MAIN[1][20][26]
DRP[5] bit 6	MAIN[1][20][27]
DRP[5] bit 7	MAIN[1][20][28]
DRP[5] bit 8	MAIN[1][20][29]
DRP[5] bit 9	MAIN[1][20][30]
DRP[5] bit 10	MAIN[1][20][31]
DRP[5] bit 11	MAIN[1][20][32]
DRP[5] bit 12	MAIN[1][20][33]
DRP[5] bit 13	MAIN[1][20][34]
DRP[5] bit 14	MAIN[1][20][35]
DRP[5] bit 15	MAIN[1][20][36]
DRP[6] bit 0	MAIN[1][20][41]
DRP[6] bit 1	MAIN[1][20][42]
DRP[6] bit 2	MAIN[1][20][43]
DRP[6] bit 3	MAIN[1][20][44]
DRP[6] bit 4	MAIN[1][20][45]
DRP[6] bit 5	MAIN[1][20][46]
DRP[6] bit 6	MAIN[1][20][47]
DRP[6] bit 7	MAIN[1][20][48]
DRP[6] bit 8	MAIN[1][20][49]
DRP[6] bit 9	MAIN[1][20][50]
DRP[6] bit 10	MAIN[1][20][51]
DRP[6] bit 11	MAIN[1][20][52]
DRP[6] bit 12	MAIN[1][20][53]
DRP[6] bit 13	MAIN[1][20][54]
DRP[6] bit 14	MAIN[1][20][55]
DRP[6] bit 15	MAIN[1][20][56]
DRP[7] bit 0	MAIN[1][20][61]
DRP[7] bit 1	MAIN[1][20][62]
DRP[7] bit 2	MAIN[1][20][63]
DRP[7] bit 3	MAIN[1][20][64]
DRP[7] bit 4	MAIN[1][20][65]
DRP[7] bit 5	MAIN[1][20][66]
DRP[7] bit 6	MAIN[1][20][67]
DRP[7] bit 7	MAIN[1][20][68]
DRP[7] bit 8	MAIN[1][20][69]
DRP[7] bit 9	MAIN[1][20][70]
DRP[7] bit 10	MAIN[1][20][71]
DRP[7] bit 11	MAIN[1][20][72]
DRP[7] bit 12	MAIN[1][20][73]
DRP[7] bit 13	MAIN[1][20][74]
DRP[7] bit 14	MAIN[1][20][75]
DRP[7] bit 15	MAIN[1][20][76]
DRP[8] bit 0	MAIN[2][20][1]
DRP[8] bit 1	MAIN[2][20][2]
DRP[8] bit 2	MAIN[2][20][3]
DRP[8] bit 3	MAIN[2][20][4]
DRP[8] bit 4	MAIN[2][20][5]
DRP[8] bit 5	MAIN[2][20][6]
DRP[8] bit 6	MAIN[2][20][7]
DRP[8] bit 7	MAIN[2][20][8]
DRP[8] bit 8	MAIN[2][20][9]
DRP[8] bit 9	MAIN[2][20][10]
DRP[8] bit 10	MAIN[2][20][11]
DRP[8] bit 11	MAIN[2][20][12]
DRP[8] bit 12	MAIN[2][20][13]
DRP[8] bit 13	MAIN[2][20][14]
DRP[8] bit 14	MAIN[2][20][15]
DRP[8] bit 15	MAIN[2][20][16]
DRP[9] bit 0	MAIN[2][20][21]
DRP[9] bit 1	MAIN[2][20][22]
DRP[9] bit 2	MAIN[2][20][23]
DRP[9] bit 3	MAIN[2][20][24]
DRP[9] bit 4	MAIN[2][20][25]
DRP[9] bit 5	MAIN[2][20][26]
DRP[9] bit 6	MAIN[2][20][27]
DRP[9] bit 7	MAIN[2][20][28]
DRP[9] bit 8	MAIN[2][20][29]
DRP[9] bit 9	MAIN[2][20][30]
DRP[9] bit 10	MAIN[2][20][31]
DRP[9] bit 11	MAIN[2][20][32]
DRP[9] bit 12	MAIN[2][20][33]
DRP[9] bit 13	MAIN[2][20][34]
DRP[9] bit 14	MAIN[2][20][35]
DRP[9] bit 15	MAIN[2][20][36]
DRP[10] bit 0	MAIN[2][20][41]
DRP[10] bit 1	MAIN[2][20][42]
DRP[10] bit 2	MAIN[2][20][43]
DRP[10] bit 3	MAIN[2][20][44]
DRP[10] bit 4	MAIN[2][20][45]
DRP[10] bit 5	MAIN[2][20][46]
DRP[10] bit 6	MAIN[2][20][47]
DRP[10] bit 7	MAIN[2][20][48]
DRP[10] bit 8	MAIN[2][20][49]
DRP[10] bit 9	MAIN[2][20][50]
DRP[10] bit 10	MAIN[2][20][51]
DRP[10] bit 11	MAIN[2][20][52]
DRP[10] bit 12	MAIN[2][20][53]
DRP[10] bit 13	MAIN[2][20][54]
DRP[10] bit 14	MAIN[2][20][55]
DRP[10] bit 15	MAIN[2][20][56]
DRP[11] bit 0	MAIN[2][20][61]
DRP[11] bit 1	MAIN[2][20][62]
DRP[11] bit 2	MAIN[2][20][63]
DRP[11] bit 3	MAIN[2][20][64]
DRP[11] bit 4	MAIN[2][20][65]
DRP[11] bit 5	MAIN[2][20][66]
DRP[11] bit 6	MAIN[2][20][67]
DRP[11] bit 7	MAIN[2][20][68]
DRP[11] bit 8	MAIN[2][20][69]
DRP[11] bit 9	MAIN[2][20][70]
DRP[11] bit 10	MAIN[2][20][71]
DRP[11] bit 11	MAIN[2][20][72]
DRP[11] bit 12	MAIN[2][20][73]
DRP[11] bit 13	MAIN[2][20][74]
DRP[11] bit 14	MAIN[2][20][75]
DRP[11] bit 15	MAIN[2][20][76]
DRP[12] bit 0	MAIN[3][20][1]
DRP[12] bit 1	MAIN[3][20][2]
DRP[12] bit 2	MAIN[3][20][3]
DRP[12] bit 3	MAIN[3][20][4]
DRP[12] bit 4	MAIN[3][20][5]
DRP[12] bit 5	MAIN[3][20][6]
DRP[12] bit 6	MAIN[3][20][7]
DRP[12] bit 7	MAIN[3][20][8]
DRP[12] bit 8	MAIN[3][20][9]
DRP[12] bit 9	MAIN[3][20][10]
DRP[12] bit 10	MAIN[3][20][11]
DRP[12] bit 11	MAIN[3][20][12]
DRP[12] bit 12	MAIN[3][20][13]
DRP[12] bit 13	MAIN[3][20][14]
DRP[12] bit 14	MAIN[3][20][15]
DRP[12] bit 15	MAIN[3][20][16]
DRP[13] bit 0	MAIN[3][20][21]
DRP[13] bit 1	MAIN[3][20][22]
DRP[13] bit 2	MAIN[3][20][23]
DRP[13] bit 3	MAIN[3][20][24]
DRP[13] bit 4	MAIN[3][20][25]
DRP[13] bit 5	MAIN[3][20][26]
DRP[13] bit 6	MAIN[3][20][27]
DRP[13] bit 7	MAIN[3][20][28]
DRP[13] bit 8	MAIN[3][20][29]
DRP[13] bit 9	MAIN[3][20][30]
DRP[13] bit 10	MAIN[3][20][31]
DRP[13] bit 11	MAIN[3][20][32]
DRP[13] bit 12	MAIN[3][20][33]
DRP[13] bit 13	MAIN[3][20][34]
DRP[13] bit 14	MAIN[3][20][35]
DRP[13] bit 15	MAIN[3][20][36]
DRP[14] bit 0	MAIN[3][20][41]
DRP[14] bit 1	MAIN[3][20][42]
DRP[14] bit 2	MAIN[3][20][43]
DRP[14] bit 3	MAIN[3][20][44]
DRP[14] bit 4	MAIN[3][20][45]
DRP[14] bit 5	MAIN[3][20][46]
DRP[14] bit 6	MAIN[3][20][47]
DRP[14] bit 7	MAIN[3][20][48]
DRP[14] bit 8	MAIN[3][20][49]
DRP[14] bit 9	MAIN[3][20][50]
DRP[14] bit 10	MAIN[3][20][51]
DRP[14] bit 11	MAIN[3][20][52]
DRP[14] bit 12	MAIN[3][20][53]
DRP[14] bit 13	MAIN[3][20][54]
DRP[14] bit 14	MAIN[3][20][55]
DRP[14] bit 15	MAIN[3][20][56]
DRP[15] bit 0	MAIN[3][20][61]
DRP[15] bit 1	MAIN[3][20][62]
DRP[15] bit 2	MAIN[3][20][63]
DRP[15] bit 3	MAIN[3][20][64]
DRP[15] bit 4	MAIN[3][20][65]
DRP[15] bit 5	MAIN[3][20][66]
DRP[15] bit 6	MAIN[3][20][67]
DRP[15] bit 7	MAIN[3][20][68]
DRP[15] bit 8	MAIN[3][20][69]
DRP[15] bit 9	MAIN[3][20][70]
DRP[15] bit 10	MAIN[3][20][71]
DRP[15] bit 11	MAIN[3][20][72]
DRP[15] bit 12	MAIN[3][20][73]
DRP[15] bit 13	MAIN[3][20][74]
DRP[15] bit 14	MAIN[3][20][75]
DRP[15] bit 15	MAIN[3][20][76]
DRP[16] bit 0	MAIN[0][19][1]
DRP[16] bit 1	MAIN[0][19][2]
DRP[16] bit 2	MAIN[0][19][3]
DRP[16] bit 3	MAIN[0][19][4]
DRP[16] bit 4	MAIN[0][19][5]
DRP[16] bit 5	MAIN[0][19][6]
DRP[16] bit 6	MAIN[0][19][7]
DRP[16] bit 7	MAIN[0][19][8]
DRP[16] bit 8	MAIN[0][19][9]
DRP[16] bit 9	MAIN[0][19][10]
DRP[16] bit 10	MAIN[0][19][11]
DRP[16] bit 11	MAIN[0][19][12]
DRP[16] bit 12	MAIN[0][19][13]
DRP[16] bit 13	MAIN[0][19][14]
DRP[16] bit 14	MAIN[0][19][15]
DRP[16] bit 15	MAIN[0][19][16]
DRP[17] bit 0	MAIN[0][19][21]
DRP[17] bit 1	MAIN[0][19][22]
DRP[17] bit 2	MAIN[0][19][23]
DRP[17] bit 3	MAIN[0][19][24]
DRP[17] bit 4	MAIN[0][19][25]
DRP[17] bit 5	MAIN[0][19][26]
DRP[17] bit 6	MAIN[0][19][27]
DRP[17] bit 7	MAIN[0][19][28]
DRP[17] bit 8	MAIN[0][19][29]
DRP[17] bit 9	MAIN[0][19][30]
DRP[17] bit 10	MAIN[0][19][31]
DRP[17] bit 11	MAIN[0][19][32]
DRP[17] bit 12	MAIN[0][19][33]
DRP[17] bit 13	MAIN[0][19][34]
DRP[17] bit 14	MAIN[0][19][35]
DRP[17] bit 15	MAIN[0][19][36]
DRP[18] bit 0	MAIN[0][19][41]
DRP[18] bit 1	MAIN[0][19][42]
DRP[18] bit 2	MAIN[0][19][43]
DRP[18] bit 3	MAIN[0][19][44]
DRP[18] bit 4	MAIN[0][19][45]
DRP[18] bit 5	MAIN[0][19][46]
DRP[18] bit 6	MAIN[0][19][47]
DRP[18] bit 7	MAIN[0][19][48]
DRP[18] bit 8	MAIN[0][19][49]
DRP[18] bit 9	MAIN[0][19][50]
DRP[18] bit 10	MAIN[0][19][51]
DRP[18] bit 11	MAIN[0][19][52]
DRP[18] bit 12	MAIN[0][19][53]
DRP[18] bit 13	MAIN[0][19][54]
DRP[18] bit 14	MAIN[0][19][55]
DRP[18] bit 15	MAIN[0][19][56]
DRP[19] bit 0	MAIN[0][19][61]
DRP[19] bit 1	MAIN[0][19][62]
DRP[19] bit 2	MAIN[0][19][63]
DRP[19] bit 3	MAIN[0][19][64]
DRP[19] bit 4	MAIN[0][19][65]
DRP[19] bit 5	MAIN[0][19][66]
DRP[19] bit 6	MAIN[0][19][67]
DRP[19] bit 7	MAIN[0][19][68]
DRP[19] bit 8	MAIN[0][19][69]
DRP[19] bit 9	MAIN[0][19][70]
DRP[19] bit 10	MAIN[0][19][71]
DRP[19] bit 11	MAIN[0][19][72]
DRP[19] bit 12	MAIN[0][19][73]
DRP[19] bit 13	MAIN[0][19][74]
DRP[19] bit 14	MAIN[0][19][75]
DRP[19] bit 15	MAIN[0][19][76]
DRP[20] bit 0	MAIN[1][19][1]
DRP[20] bit 1	MAIN[1][19][2]
DRP[20] bit 2	MAIN[1][19][3]
DRP[20] bit 3	MAIN[1][19][4]
DRP[20] bit 4	MAIN[1][19][5]
DRP[20] bit 5	MAIN[1][19][6]
DRP[20] bit 6	MAIN[1][19][7]
DRP[20] bit 7	MAIN[1][19][8]
DRP[20] bit 8	MAIN[1][19][9]
DRP[20] bit 9	MAIN[1][19][10]
DRP[20] bit 10	MAIN[1][19][11]
DRP[20] bit 11	MAIN[1][19][12]
DRP[20] bit 12	MAIN[1][19][13]
DRP[20] bit 13	MAIN[1][19][14]
DRP[20] bit 14	MAIN[1][19][15]
DRP[20] bit 15	MAIN[1][19][16]
DRP[21] bit 0	MAIN[1][19][21]
DRP[21] bit 1	MAIN[1][19][22]
DRP[21] bit 2	MAIN[1][19][23]
DRP[21] bit 3	MAIN[1][19][24]
DRP[21] bit 4	MAIN[1][19][25]
DRP[21] bit 5	MAIN[1][19][26]
DRP[21] bit 6	MAIN[1][19][27]
DRP[21] bit 7	MAIN[1][19][28]
DRP[21] bit 8	MAIN[1][19][29]
DRP[21] bit 9	MAIN[1][19][30]
DRP[21] bit 10	MAIN[1][19][31]
DRP[21] bit 11	MAIN[1][19][32]
DRP[21] bit 12	MAIN[1][19][33]
DRP[21] bit 13	MAIN[1][19][34]
DRP[21] bit 14	MAIN[1][19][35]
DRP[21] bit 15	MAIN[1][19][36]
DRP[22] bit 0	MAIN[1][19][41]
DRP[22] bit 1	MAIN[1][19][42]
DRP[22] bit 2	MAIN[1][19][43]
DRP[22] bit 3	MAIN[1][19][44]
DRP[22] bit 4	MAIN[1][19][45]
DRP[22] bit 5	MAIN[1][19][46]
DRP[22] bit 6	MAIN[1][19][47]
DRP[22] bit 7	MAIN[1][19][48]
DRP[22] bit 8	MAIN[1][19][49]
DRP[22] bit 9	MAIN[1][19][50]
DRP[22] bit 10	MAIN[1][19][51]
DRP[22] bit 11	MAIN[1][19][52]
DRP[22] bit 12	MAIN[1][19][53]
DRP[22] bit 13	MAIN[1][19][54]
DRP[22] bit 14	MAIN[1][19][55]
DRP[22] bit 15	MAIN[1][19][56]
DRP[23] bit 0	MAIN[1][19][61]
DRP[23] bit 1	MAIN[1][19][62]
DRP[23] bit 2	MAIN[1][19][63]
DRP[23] bit 3	MAIN[1][19][64]
DRP[23] bit 4	MAIN[1][19][65]
DRP[23] bit 5	MAIN[1][19][66]
DRP[23] bit 6	MAIN[1][19][67]
DRP[23] bit 7	MAIN[1][19][68]
DRP[23] bit 8	MAIN[1][19][69]
DRP[23] bit 9	MAIN[1][19][70]
DRP[23] bit 10	MAIN[1][19][71]
DRP[23] bit 11	MAIN[1][19][72]
DRP[23] bit 12	MAIN[1][19][73]
DRP[23] bit 13	MAIN[1][19][74]
DRP[23] bit 14	MAIN[1][19][75]
DRP[23] bit 15	MAIN[1][19][76]
DRP[24] bit 0	MAIN[2][19][1]
DRP[24] bit 1	MAIN[2][19][2]
DRP[24] bit 2	MAIN[2][19][3]
DRP[24] bit 3	MAIN[2][19][4]
DRP[24] bit 4	MAIN[2][19][5]
DRP[24] bit 5	MAIN[2][19][6]
DRP[24] bit 6	MAIN[2][19][7]
DRP[24] bit 7	MAIN[2][19][8]
DRP[24] bit 8	MAIN[2][19][9]
DRP[24] bit 9	MAIN[2][19][10]
DRP[24] bit 10	MAIN[2][19][11]
DRP[24] bit 11	MAIN[2][19][12]
DRP[24] bit 12	MAIN[2][19][13]
DRP[24] bit 13	MAIN[2][19][14]
DRP[24] bit 14	MAIN[2][19][15]
DRP[24] bit 15	MAIN[2][19][16]
DRP[25] bit 0	MAIN[2][19][21]
DRP[25] bit 1	MAIN[2][19][22]
DRP[25] bit 2	MAIN[2][19][23]
DRP[25] bit 3	MAIN[2][19][24]
DRP[25] bit 4	MAIN[2][19][25]
DRP[25] bit 5	MAIN[2][19][26]
DRP[25] bit 6	MAIN[2][19][27]
DRP[25] bit 7	MAIN[2][19][28]
DRP[25] bit 8	MAIN[2][19][29]
DRP[25] bit 9	MAIN[2][19][30]
DRP[25] bit 10	MAIN[2][19][31]
DRP[25] bit 11	MAIN[2][19][32]
DRP[25] bit 12	MAIN[2][19][33]
DRP[25] bit 13	MAIN[2][19][34]
DRP[25] bit 14	MAIN[2][19][35]
DRP[25] bit 15	MAIN[2][19][36]
DRP[26] bit 0	MAIN[2][19][41]
DRP[26] bit 1	MAIN[2][19][42]
DRP[26] bit 2	MAIN[2][19][43]
DRP[26] bit 3	MAIN[2][19][44]
DRP[26] bit 4	MAIN[2][19][45]
DRP[26] bit 5	MAIN[2][19][46]
DRP[26] bit 6	MAIN[2][19][47]
DRP[26] bit 7	MAIN[2][19][48]
DRP[26] bit 8	MAIN[2][19][49]
DRP[26] bit 9	MAIN[2][19][50]
DRP[26] bit 10	MAIN[2][19][51]
DRP[26] bit 11	MAIN[2][19][52]
DRP[26] bit 12	MAIN[2][19][53]
DRP[26] bit 13	MAIN[2][19][54]
DRP[26] bit 14	MAIN[2][19][55]
DRP[26] bit 15	MAIN[2][19][56]
DRP[27] bit 0	MAIN[2][19][61]
DRP[27] bit 1	MAIN[2][19][62]
DRP[27] bit 2	MAIN[2][19][63]
DRP[27] bit 3	MAIN[2][19][64]
DRP[27] bit 4	MAIN[2][19][65]
DRP[27] bit 5	MAIN[2][19][66]
DRP[27] bit 6	MAIN[2][19][67]
DRP[27] bit 7	MAIN[2][19][68]
DRP[27] bit 8	MAIN[2][19][69]
DRP[27] bit 9	MAIN[2][19][70]
DRP[27] bit 10	MAIN[2][19][71]
DRP[27] bit 11	MAIN[2][19][72]
DRP[27] bit 12	MAIN[2][19][73]
DRP[27] bit 13	MAIN[2][19][74]
DRP[27] bit 14	MAIN[2][19][75]
DRP[27] bit 15	MAIN[2][19][76]
DRP[28] bit 0	MAIN[3][19][1]
DRP[28] bit 1	MAIN[3][19][2]
DRP[28] bit 2	MAIN[3][19][3]
DRP[28] bit 3	MAIN[3][19][4]
DRP[28] bit 4	MAIN[3][19][5]
DRP[28] bit 5	MAIN[3][19][6]
DRP[28] bit 6	MAIN[3][19][7]
DRP[28] bit 7	MAIN[3][19][8]
DRP[28] bit 8	MAIN[3][19][9]
DRP[28] bit 9	MAIN[3][19][10]
DRP[28] bit 10	MAIN[3][19][11]
DRP[28] bit 11	MAIN[3][19][12]
DRP[28] bit 12	MAIN[3][19][13]
DRP[28] bit 13	MAIN[3][19][14]
DRP[28] bit 14	MAIN[3][19][15]
DRP[28] bit 15	MAIN[3][19][16]
DRP[29] bit 0	MAIN[3][19][21]
DRP[29] bit 1	MAIN[3][19][22]
DRP[29] bit 2	MAIN[3][19][23]
DRP[29] bit 3	MAIN[3][19][24]
DRP[29] bit 4	MAIN[3][19][25]
DRP[29] bit 5	MAIN[3][19][26]
DRP[29] bit 6	MAIN[3][19][27]
DRP[29] bit 7	MAIN[3][19][28]
DRP[29] bit 8	MAIN[3][19][29]
DRP[29] bit 9	MAIN[3][19][30]
DRP[29] bit 10	MAIN[3][19][31]
DRP[29] bit 11	MAIN[3][19][32]
DRP[29] bit 12	MAIN[3][19][33]
DRP[29] bit 13	MAIN[3][19][34]
DRP[29] bit 14	MAIN[3][19][35]
DRP[29] bit 15	MAIN[3][19][36]
DRP[30] bit 0	MAIN[3][19][41]
DRP[30] bit 1	MAIN[3][19][42]
DRP[30] bit 2	MAIN[3][19][43]
DRP[30] bit 3	MAIN[3][19][44]
DRP[30] bit 4	MAIN[3][19][45]
DRP[30] bit 5	MAIN[3][19][46]
DRP[30] bit 6	MAIN[3][19][47]
DRP[30] bit 7	MAIN[3][19][48]
DRP[30] bit 8	MAIN[3][19][49]
DRP[30] bit 9	MAIN[3][19][50]
DRP[30] bit 10	MAIN[3][19][51]
DRP[30] bit 11	MAIN[3][19][52]
DRP[30] bit 12	MAIN[3][19][53]
DRP[30] bit 13	MAIN[3][19][54]
DRP[30] bit 14	MAIN[3][19][55]
DRP[30] bit 15	MAIN[3][19][56]
DRP[31] bit 0	MAIN[3][19][61]
DRP[31] bit 1	MAIN[3][19][62]
DRP[31] bit 2	MAIN[3][19][63]
DRP[31] bit 3	MAIN[3][19][64]
DRP[31] bit 4	MAIN[3][19][65]
DRP[31] bit 5	MAIN[3][19][66]
DRP[31] bit 6	MAIN[3][19][67]
DRP[31] bit 7	MAIN[3][19][68]
DRP[31] bit 8	MAIN[3][19][69]
DRP[31] bit 9	MAIN[3][19][70]
DRP[31] bit 10	MAIN[3][19][71]
DRP[31] bit 11	MAIN[3][19][72]
DRP[31] bit 12	MAIN[3][19][73]
DRP[31] bit 13	MAIN[3][19][74]
DRP[31] bit 14	MAIN[3][19][75]
DRP[31] bit 15	MAIN[3][19][76]
DRP_MASK bit 0	MAIN[0][20][18]
DRP_MASK bit 1	MAIN[0][20][38]
DRP_MASK bit 2	MAIN[0][20][58]
DRP_MASK bit 3	MAIN[0][20][78]
DRP_MASK bit 4	MAIN[1][20][18]
DRP_MASK bit 5	MAIN[1][20][38]
DRP_MASK bit 6	MAIN[1][20][58]
DRP_MASK bit 7	MAIN[1][20][78]
DRP_MASK bit 8	MAIN[2][20][18]
DRP_MASK bit 9	MAIN[2][20][38]
DRP_MASK bit 10	MAIN[2][20][58]
DRP_MASK bit 11	MAIN[2][20][78]
DRP_MASK bit 12	MAIN[3][20][18]
DRP_MASK bit 13	MAIN[3][20][38]
DRP_MASK bit 14	MAIN[3][20][58]
DRP_MASK bit 15	MAIN[3][20][78]
DRP_MASK bit 16	MAIN[0][19][18]
DRP_MASK bit 17	MAIN[0][19][38]
DRP_MASK bit 18	MAIN[0][19][58]
DRP_MASK bit 19	MAIN[0][19][78]
DRP_MASK bit 20	MAIN[1][19][18]
DRP_MASK bit 21	MAIN[1][19][38]
DRP_MASK bit 22	MAIN[1][19][58]
DRP_MASK bit 23	MAIN[1][19][78]
DRP_MASK bit 24	MAIN[2][19][18]
DRP_MASK bit 25	MAIN[2][19][38]
DRP_MASK bit 26	MAIN[2][19][58]
DRP_MASK bit 27	MAIN[2][19][78]
DRP_MASK bit 28	MAIN[3][19][18]
DRP_MASK bit 29	MAIN[3][19][38]
DRP_MASK bit 30	MAIN[3][19][58]
DRP_MASK bit 31	MAIN[3][19][78]
OUT_CLK0_ENABLE	MAIN[3][20][41]
OUT_CLK90_ENABLE	MAIN[3][20][42]
OUT_CLK180_ENABLE	MAIN[3][20][43]
OUT_CLK270_ENABLE	MAIN[3][20][44]
OUT_CLK2X_ENABLE	MAIN[3][20][45]
OUT_CLK2X180_ENABLE	MAIN[3][20][46]
OUT_CLKDV_ENABLE	MAIN[3][20][47]
OUT_CLKFX_ENABLE	MAIN[0][19][30]
OUT_CLKFX180_ENABLE	MAIN[0][19][29]
OUT_CONCUR_ENABLE	MAIN[0][19][31]
CLKDV_COUNT_MAX bit 0	MAIN[3][20][25]
CLKDV_COUNT_MAX bit 1	MAIN[3][20][26]
CLKDV_COUNT_MAX bit 2	MAIN[3][20][27]
CLKDV_COUNT_MAX bit 3	MAIN[3][20][28]
CLKDV_COUNT_FALL bit 0	MAIN[3][20][33]
CLKDV_COUNT_FALL bit 1	MAIN[3][20][34]
CLKDV_COUNT_FALL bit 2	MAIN[3][20][35]
CLKDV_COUNT_FALL bit 3	MAIN[3][20][36]
CLKDV_COUNT_FALL_2 bit 0	MAIN[3][20][29]
CLKDV_COUNT_FALL_2 bit 1	MAIN[3][20][30]
CLKDV_COUNT_FALL_2 bit 2	MAIN[3][20][31]
CLKDV_COUNT_FALL_2 bit 3	MAIN[3][20][32]
CLKDV_PHASE_RISE bit 0	MAIN[3][20][23]
CLKDV_PHASE_RISE bit 1	MAIN[3][20][24]
CLKDV_PHASE_FALL bit 0	MAIN[3][20][21]
CLKDV_PHASE_FALL bit 1	MAIN[3][20][22]
CLKDV_MODE	[enum: DCM_CLKDV_MODE]
STARTUP_WAIT	MAIN[0][19][75]
UNK_ALWAYS_SET	MAIN[1][19][50]
DESKEW_ADJUST bit 0	MAIN[0][20][41]
DESKEW_ADJUST bit 1	MAIN[0][20][42]
DESKEW_ADJUST bit 2	MAIN[0][20][43]
DESKEW_ADJUST bit 3	MAIN[0][20][44]
DESKEW_ADJUST bit 4	MAIN[0][20][45]
CLKIN_ENABLE	MAIN[0][19][25]
CLKIN_IOB	MAIN[0][20][47]
CLKFB_ENABLE	MAIN[0][19][73]
CLKFB_IOB	MAIN[0][20][46]
CLKFB_FEEDBACK	MAIN[2][19][5]
CLKIN_DIVIDE_BY_2	MAIN[0][19][24]
CLK_FEEDBACK	[enum: DCM_CLK_FEEDBACK]
CLKFX_MULTIPLY bit 0	MAIN[0][19][1]
CLKFX_MULTIPLY bit 1	MAIN[0][19][2]
CLKFX_MULTIPLY bit 2	MAIN[0][19][3]
CLKFX_MULTIPLY bit 3	MAIN[0][19][4]
CLKFX_MULTIPLY bit 4	MAIN[0][19][5]
CLKFX_DIVIDE bit 0	MAIN[0][19][41]
CLKFX_DIVIDE bit 1	MAIN[0][19][42]
CLKFX_DIVIDE bit 2	MAIN[0][19][43]
CLKFX_DIVIDE bit 3	MAIN[0][19][44]
CLKFX_DIVIDE bit 4	MAIN[0][19][45]
DUTY_CYCLE_CORRECTION bit 0	MAIN[3][20][53]
DUTY_CYCLE_CORRECTION bit 1	MAIN[3][20][54]
DUTY_CYCLE_CORRECTION bit 2	MAIN[3][20][55]
DUTY_CYCLE_CORRECTION bit 3	MAIN[3][20][56]
FACTORY_JF bit 0	MAIN[2][19][21]
FACTORY_JF bit 1	MAIN[2][19][22]
FACTORY_JF bit 2	MAIN[2][19][23]
FACTORY_JF bit 3	MAIN[2][19][24]
FACTORY_JF bit 4	MAIN[2][19][25]
FACTORY_JF bit 5	MAIN[2][19][26]
FACTORY_JF bit 6	MAIN[2][19][27]
FACTORY_JF bit 7	MAIN[2][19][28]
FACTORY_JF bit 8	MAIN[2][19][29]
FACTORY_JF bit 9	MAIN[2][19][30]
FACTORY_JF bit 10	MAIN[2][19][31]
FACTORY_JF bit 11	MAIN[2][19][32]
FACTORY_JF bit 12	MAIN[2][19][33]
FACTORY_JF bit 13	MAIN[2][19][34]
FACTORY_JF bit 14	MAIN[2][19][35]
FACTORY_JF bit 15	MAIN[2][19][36]
PHASE_SHIFT bit 0	MAIN[1][19][21]
PHASE_SHIFT bit 1	MAIN[1][19][22]
PHASE_SHIFT bit 2	MAIN[1][19][23]
PHASE_SHIFT bit 3	MAIN[1][19][24]
PHASE_SHIFT bit 4	MAIN[1][19][25]
PHASE_SHIFT bit 5	MAIN[1][19][26]
PHASE_SHIFT bit 6	MAIN[1][19][27]
PHASE_SHIFT bit 7	MAIN[1][19][28]
PHASE_SHIFT bit 8	MAIN[1][19][29]
PHASE_SHIFT bit 9	MAIN[1][19][30]
PHASE_SHIFT_NEGATIVE	MAIN[1][19][31]
PMCD_SYNC	MAIN[3][20][68]
PS_CENTERED	MAIN[1][19][42]
PS_DIRECT	MAIN[1][19][41]
PS_ENABLE	MAIN[1][19][44]
PS_MODE	[enum: DCM_PS_MODE]
DCM_CLKDV_CLKFX_ALIGNMENT	MAIN[0][19][66]
DCM_EXT_FB_EN	MAIN[0][20][27]
DCM_LOCK_HIGH	!MAIN[2][19][10]
DCM_PERFORMANCE_MODE	[enum: DCM_PERFORMANCE_MODE]
DCM_PULSE_WIDTH_CORRECTION_LOW bit 0	MAIN[1][20][1]
DCM_PULSE_WIDTH_CORRECTION_LOW bit 1	MAIN[1][20][2]
DCM_PULSE_WIDTH_CORRECTION_LOW bit 2	MAIN[1][20][3]
DCM_PULSE_WIDTH_CORRECTION_LOW bit 3	MAIN[1][20][4]
DCM_PULSE_WIDTH_CORRECTION_LOW bit 4	MAIN[1][20][5]
DCM_PULSE_WIDTH_CORRECTION_HIGH bit 0	MAIN[1][20][6]
DCM_PULSE_WIDTH_CORRECTION_HIGH bit 1	MAIN[1][20][7]
DCM_PULSE_WIDTH_CORRECTION_HIGH bit 2	MAIN[1][20][8]
DCM_PULSE_WIDTH_CORRECTION_HIGH bit 3	MAIN[1][20][9]
DCM_PULSE_WIDTH_CORRECTION_HIGH bit 4	MAIN[1][20][10]
DCM_UNUSED_TAPS_POWERDOWN	MAIN[1][19][55]
DCM_VREG_ENABLE	MAIN[2][19][45]
DCM_VBG_PD bit 0	MAIN[2][19][50]
DCM_VBG_PD bit 1	MAIN[2][19][51]
DCM_VBG_SEL bit 0	MAIN[2][19][46]
DCM_VBG_SEL bit 1	MAIN[2][19][47]
DCM_VBG_SEL bit 2	MAIN[2][19][48]
DCM_VBG_SEL bit 3	MAIN[2][19][49]
DCM_VREF_SOURCE	[enum: DCM_VREF_SOURCE]
DCM_VREG_PHASE_MARGIN bit 0	MAIN[2][19][52]
DCM_VREG_PHASE_MARGIN bit 1	MAIN[2][19][53]
DCM_VREG_PHASE_MARGIN bit 2	MAIN[2][19][54]
DLL_CONTROL_CLOCK_SPEED	[enum: DCM_DLL_CONTROL_CLOCK_SPEED]
DLL_CTL_SEL_CLKIN_DIV2	MAIN[0][19][65]
DLL_DEAD_TIME bit 0	MAIN[3][19][29]
DLL_DEAD_TIME bit 1	MAIN[3][19][30]
DLL_DEAD_TIME bit 2	MAIN[3][19][31]
DLL_DEAD_TIME bit 3	MAIN[3][19][32]
DLL_DEAD_TIME bit 4	MAIN[3][19][33]
DLL_DEAD_TIME bit 5	MAIN[3][19][34]
DLL_DEAD_TIME bit 6	MAIN[3][19][35]
DLL_DEAD_TIME bit 7	MAIN[3][19][36]
DLL_DESKEW_LOCK_BY1	MAIN[2][19][2]
DLL_DESKEW_MAXTAP bit 0	MAIN[2][19][69]
DLL_DESKEW_MAXTAP bit 1	MAIN[2][19][70]
DLL_DESKEW_MAXTAP bit 2	MAIN[2][19][71]
DLL_DESKEW_MAXTAP bit 3	MAIN[2][19][72]
DLL_DESKEW_MAXTAP bit 4	MAIN[2][19][73]
DLL_DESKEW_MAXTAP bit 5	MAIN[2][19][74]
DLL_DESKEW_MAXTAP bit 6	MAIN[2][19][75]
DLL_DESKEW_MAXTAP bit 7	MAIN[2][19][76]
DLL_DESKEW_MINTAP bit 0	MAIN[2][19][61]
DLL_DESKEW_MINTAP bit 1	MAIN[2][19][62]
DLL_DESKEW_MINTAP bit 2	MAIN[2][19][63]
DLL_DESKEW_MINTAP bit 3	MAIN[2][19][64]
DLL_DESKEW_MINTAP bit 4	MAIN[2][19][65]
DLL_DESKEW_MINTAP bit 5	MAIN[2][19][66]
DLL_DESKEW_MINTAP bit 6	MAIN[2][19][67]
DLL_DESKEW_MINTAP bit 7	MAIN[2][19][68]
DLL_FREQUENCY_MODE	[enum: DCM_DLL_FREQUENCY_MODE]
DLL_LIVE_TIME bit 0	MAIN[3][19][21]
DLL_LIVE_TIME bit 1	MAIN[3][19][22]
DLL_LIVE_TIME bit 2	MAIN[3][19][23]
DLL_LIVE_TIME bit 3	MAIN[3][19][24]
DLL_LIVE_TIME bit 4	MAIN[3][19][25]
DLL_LIVE_TIME bit 5	MAIN[3][19][26]
DLL_LIVE_TIME bit 6	MAIN[3][19][27]
DLL_LIVE_TIME bit 7	MAIN[3][19][28]
DLL_PD_DLY_SEL bit 0	MAIN[3][20][69]
DLL_PD_DLY_SEL bit 1	MAIN[3][20][70]
DLL_PD_DLY_SEL bit 2	MAIN[3][20][71]
DLL_PERIOD_LOCK_BY1	MAIN[2][19][1]
DLL_PHASE_DETECTOR_AUTO_RESET	MAIN[0][19][74]
DLL_PHASE_DETECTOR_MODE	[enum: DCM_DLL_PHASE_DETECTOR_MODE]
DLL_PHASE_SHIFT_CALIBRATION	[enum: DCM_DLL_PHASE_SHIFT_CALIBRATION]
DLL_PHASE_SHIFT_HFC bit 0	MAIN[1][19][69]
DLL_PHASE_SHIFT_HFC bit 1	MAIN[1][19][70]
DLL_PHASE_SHIFT_HFC bit 2	MAIN[1][19][71]
DLL_PHASE_SHIFT_HFC bit 3	MAIN[1][19][72]
DLL_PHASE_SHIFT_HFC bit 4	MAIN[1][19][73]
DLL_PHASE_SHIFT_HFC bit 5	MAIN[1][19][74]
DLL_PHASE_SHIFT_HFC bit 6	MAIN[1][19][75]
DLL_PHASE_SHIFT_HFC bit 7	MAIN[1][19][76]
DLL_PHASE_SHIFT_LFC bit 0	MAIN[1][19][61]
DLL_PHASE_SHIFT_LFC bit 1	MAIN[1][19][62]
DLL_PHASE_SHIFT_LFC bit 2	MAIN[1][19][63]
DLL_PHASE_SHIFT_LFC bit 3	MAIN[1][19][64]
DLL_PHASE_SHIFT_LFC bit 4	MAIN[1][19][65]
DLL_PHASE_SHIFT_LFC bit 5	MAIN[1][19][66]
DLL_PHASE_SHIFT_LFC bit 6	MAIN[1][19][67]
DLL_PHASE_SHIFT_LFC bit 7	MAIN[1][19][68]
DLL_PHASE_SHIFT_LOCK_BY1	MAIN[1][19][48]
DLL_SETTLE_TIME bit 0	MAIN[3][19][41]
DLL_SETTLE_TIME bit 1	MAIN[3][19][42]
DLL_SETTLE_TIME bit 2	MAIN[3][19][43]
DLL_SETTLE_TIME bit 3	MAIN[3][19][44]
DLL_SETTLE_TIME bit 4	MAIN[3][19][45]
DLL_SETTLE_TIME bit 5	MAIN[3][19][46]
DLL_SETTLE_TIME bit 6	MAIN[3][19][47]
DLL_SETTLE_TIME bit 7	MAIN[3][19][48]
DLL_TEST_MUX_SEL bit 0	MAIN[3][20][49]
DLL_TEST_MUX_SEL bit 1	MAIN[3][20][50]
DLL_ZD2_EN	MAIN[2][19][6]
DLL_SPARE bit 0	MAIN[2][20][1]
DLL_SPARE bit 1	MAIN[2][20][2]
DLL_SPARE bit 2	MAIN[2][20][3]
DLL_SPARE bit 3	MAIN[2][20][4]
DLL_SPARE bit 4	MAIN[2][20][5]
DLL_SPARE bit 5	MAIN[2][20][6]
DLL_SPARE bit 6	MAIN[2][20][7]
DLL_SPARE bit 7	MAIN[2][20][8]
DLL_SPARE bit 8	MAIN[2][20][9]
DLL_SPARE bit 9	MAIN[2][20][10]
DLL_SPARE bit 10	MAIN[2][20][11]
DLL_SPARE bit 11	MAIN[2][20][12]
DLL_SPARE bit 12	MAIN[2][20][13]
DLL_SPARE bit 13	MAIN[2][20][14]
DLL_SPARE bit 14	MAIN[2][20][15]
DLL_SPARE bit 15	MAIN[2][20][16]
DFS_AVE_FREQ_ADJ_INTERVAL bit 0	MAIN[1][19][4]
DFS_AVE_FREQ_ADJ_INTERVAL bit 1	MAIN[1][19][5]
DFS_AVE_FREQ_ADJ_INTERVAL bit 2	MAIN[1][19][6]
DFS_AVE_FREQ_ADJ_INTERVAL bit 3	MAIN[1][19][7]
DFS_AVE_FREQ_GAIN	[enum: DCM_DFS_AVE_FREQ_GAIN]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 0	MAIN[1][19][1]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 1	MAIN[1][19][2]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 2	MAIN[1][19][3]
DFS_COARSE_SEL	[enum: DCM_DFS_SEL]
DFS_COIN_WINDOW bit 0	MAIN[1][19][14]
DFS_COIN_WINDOW bit 1	MAIN[1][19][15]
DFS_EARLY_LOCK	MAIN[0][19][70]
DFS_ENABLE	MAIN[0][19][69]
DFS_EN_RELRST	!MAIN[0][19][23]
DFS_EXTEND_FLUSH_TIME	MAIN[1][19][11]
DFS_EXTEND_HALT_TIME	MAIN[1][19][13]
DFS_EXTEND_RUN_TIME	MAIN[1][19][12]
DFS_FEEDBACK	MAIN[0][20][23]
DFS_FINE_SEL	[enum: DCM_DFS_SEL]
DFS_FREQUENCY_MODE	[enum: DCM_DFS_FREQUENCY_MODE]
DFS_HARDSYNC bit 0	MAIN[0][19][67]
DFS_HARDSYNC bit 1	MAIN[0][19][68]
DFS_NON_STOP	MAIN[0][20][25]
DFS_OSCILLATOR_MODE	[enum: DCM_DFS_OSCILLATOR_MODE]
DFS_SKIP_FINE	MAIN[0][20][24]
DFS_SPARE bit 0	MAIN[0][20][1]
DFS_SPARE bit 1	MAIN[0][20][2]
DFS_SPARE bit 2	MAIN[0][20][3]
DFS_SPARE bit 3	MAIN[0][20][4]
DFS_SPARE bit 4	MAIN[0][20][5]
DFS_SPARE bit 5	MAIN[0][20][6]
DFS_SPARE bit 6	MAIN[0][20][7]
DFS_SPARE bit 7	MAIN[0][20][8]
DFS_SPARE bit 8	MAIN[0][20][9]
DFS_SPARE bit 9	MAIN[0][20][10]
DFS_SPARE bit 10	MAIN[0][20][11]
DFS_SPARE bit 11	MAIN[0][20][12]
DFS_SPARE bit 12	MAIN[0][20][13]
DFS_SPARE bit 13	MAIN[0][20][14]
DFS_SPARE bit 14	MAIN[0][20][15]
DFS_SPARE bit 15	MAIN[0][20][16]
DFS_TP_SEL	[enum: DCM_DFS_SEL]
DFS_TRACKMODE	MAIN[0][19][26]
BGM_CONFIG_REF_SEL	[enum: DCM_BGM_CONFIG_REF_SEL]
BGM_LDLY bit 0	MAIN[3][20][10]
BGM_LDLY bit 1	MAIN[3][20][11]
BGM_LDLY bit 2	MAIN[3][20][12]
BGM_MODE	[enum: DCM_BGM_MODE]
BGM_MULTIPLY bit 0	MAIN[3][19][61]
BGM_MULTIPLY bit 1	MAIN[3][19][62]
BGM_MULTIPLY bit 2	MAIN[3][19][63]
BGM_MULTIPLY bit 3	MAIN[3][19][64]
BGM_MULTIPLY bit 4	MAIN[3][19][65]
BGM_MULTIPLY bit 5	MAIN[3][19][66]
BGM_DIVIDE bit 0	MAIN[3][19][69]
BGM_DIVIDE bit 1	MAIN[3][19][70]
BGM_DIVIDE bit 2	MAIN[3][19][71]
BGM_DIVIDE bit 3	MAIN[3][19][72]
BGM_DIVIDE bit 4	MAIN[3][19][73]
BGM_DIVIDE bit 5	MAIN[3][19][74]
BGM_SAMPLE_LEN bit 0	MAIN[3][19][7]
BGM_SAMPLE_LEN bit 1	MAIN[3][19][8]
BGM_SAMPLE_LEN bit 2	MAIN[3][19][9]
BGM_SDLY bit 0	MAIN[3][20][7]
BGM_SDLY bit 1	MAIN[3][20][8]
BGM_SDLY bit 2	MAIN[3][20][9]
BGM_VADJ bit 0	MAIN[3][19][3]
BGM_VADJ bit 1	MAIN[3][19][4]
BGM_VADJ bit 2	MAIN[3][19][5]
BGM_VADJ bit 3	MAIN[3][19][6]
BGM_VLDLY bit 0	MAIN[3][20][4]
BGM_VLDLY bit 1	MAIN[3][20][5]
BGM_VLDLY bit 2	MAIN[3][20][6]
BGM_VSDLY bit 0	MAIN[3][20][1]
BGM_VSDLY bit 1	MAIN[3][20][2]
BGM_VSDLY bit 2	MAIN[3][20][3]

virtex4 DCM enum DCM_CLKDV_MODE
DCM[0].CLKDV_MODE	MAIN[3][20][16]
HALF	0
INT	1

virtex4 DCM enum DCM_CLK_FEEDBACK
DCM[0].CLK_FEEDBACK	MAIN[0][20][22]	MAIN[0][20][21]
_1X	0	0
_2X	0	1
NONE	1	0

virtex4 DCM enum DCM_PS_MODE
DCM[0].PS_MODE	MAIN[1][19][43]
CLKIN	1
CLKFB	0

virtex4 DCM enum DCM_PERFORMANCE_MODE
DCM[0].DCM_PERFORMANCE_MODE	MAIN[2][19][41]
MAX_RANGE	0
MAX_SPEED	1

virtex4 DCM enum DCM_VREF_SOURCE
DCM[0].DCM_VREF_SOURCE	MAIN[2][19][44]	MAIN[2][19][43]	MAIN[2][19][42]
VDD_VBG	0	0	0
BGM_SNAP	1	0	0
BGM_ABS_SNAP	1	1	0
BGM_ABS_REF	1	1	1

virtex4 DCM enum DCM_DLL_CONTROL_CLOCK_SPEED
DCM[0].DLL_CONTROL_CLOCK_SPEED	MAIN[0][19][76]
HALF	0
QUARTER	1

virtex4 DCM enum DCM_DLL_FREQUENCY_MODE
DCM[0].DLL_FREQUENCY_MODE	MAIN[2][19][8]	MAIN[2][19][7]
LOW	0	0
HIGH_SER	0	1
HIGH	1	1

virtex4 DCM enum DCM_DLL_PHASE_DETECTOR_MODE
DCM[0].DLL_PHASE_DETECTOR_MODE	MAIN[2][19][9]
LEVEL	0
ENHANCED	1

virtex4 DCM enum DCM_DLL_PHASE_SHIFT_CALIBRATION
DCM[0].DLL_PHASE_SHIFT_CALIBRATION	MAIN[1][19][46]	MAIN[1][19][45]
AUTO_DPS	0	0
CONFIG	0	1
MASK	1	0
AUTO_ZD2	1	1

virtex4 DCM enum DCM_DFS_AVE_FREQ_GAIN
DCM[0].DFS_AVE_FREQ_GAIN	MAIN[1][19][10]	MAIN[1][19][9]	MAIN[1][19][8]
NONE	0	0	0
_0P5	0	0	1
_0P25	0	1	0
_0P125	0	1	1
_1P0	1	0	0
_2P0	1	0	1
_4P0	1	1	0
_8P0	1	1	1

virtex4 DCM enum DCM_DFS_SEL
DCM[0].DFS_COARSE_SEL	MAIN[0][19][71]
DCM[0].DFS_FINE_SEL	MAIN[0][19][72]
DCM[0].DFS_TP_SEL	MAIN[0][19][62]
LEVEL	0
LEGACY	1

virtex4 DCM enum DCM_DFS_FREQUENCY_MODE
DCM[0].DFS_FREQUENCY_MODE	MAIN[0][20][26]
LOW	0
HIGH	1

virtex4 DCM enum DCM_DFS_OSCILLATOR_MODE
DCM[0].DFS_OSCILLATOR_MODE	MAIN[0][19][64]	MAIN[0][19][63]
PHASE_FREQ_LOCK	0	0
FREQ_LOCK	0	1
AVE_FREQ_LOCK	1	0

virtex4 DCM enum DCM_BGM_CONFIG_REF_SEL
DCM[0].BGM_CONFIG_REF_SEL	MAIN[3][20][15]
DCLK	0
CLKIN	1

virtex4 DCM enum DCM_BGM_MODE
DCM[0].BGM_MODE	MAIN[3][19][2]	MAIN[3][19][1]
BG_SNAPSHOT	0	0
ABS_FREQ_SNAPSHOT	1	0
ABS_FREQ_REF	1	1

Bel wires

virtex4 DCM bel wires
Wire	Pins
CELL[0].IMUX_CE_OPTINV[0]	DCM[0].CTLMODE
CELL[0].IMUX_IMUX[0]	DCM[0].CTLSEL[0]
CELL[0].IMUX_IMUX[1]	DCM[0].CTLSEL[1]
CELL[0].IMUX_IMUX[2]	DCM[0].CTLSEL[2]
CELL[0].IMUX_IMUX[3]	DCM[0].PSINCDEC
CELL[0].IMUX_IMUX[4]	DCM[0].PSEN
CELL[0].IMUX_IMUX[5]	DCM[0].CTLOSC1
CELL[0].IMUX_IMUX[6]	DCM[0].CTLOSC2
CELL[0].IMUX_IMUX[7]	DCM[0].CTLGO
CELL[0].OUT_BEST_TMIN[0]	DCM[0].CLKDV
CELL[0].OUT_BEST_TMIN[4]	DCM[0].DO[12]
CELL[0].OUT_BEST_TMIN[5]	DCM[0].DO[13]
CELL[0].OUT_BEST_TMIN[6]	DCM[0].DO[14]
CELL[0].OUT_BEST_TMIN[7]	DCM[0].DO[15]
CELL[0].OUT_DCM[1]	DCM[0].CONCUR
CELL[0].OUT_DCM[2]	DCM[0].CLKFX
CELL[0].OUT_DCM[3]	DCM[0].CLKFX180
CELL[0].OUT_DCM[4]	DCM[0].CLK0
CELL[0].OUT_DCM[5]	DCM[0].CLK180
CELL[0].OUT_DCM[6]	DCM[0].CLK90
CELL[0].OUT_DCM[7]	DCM[0].CLK270
CELL[0].OUT_DCM[8]	DCM[0].CLK2X180
CELL[0].OUT_DCM[9]	DCM[0].CLK2X
CELL[0].OUT_DCM[10]	DCM[0].CLKDV
CELL[0].OUT_DCM_LOCKED	DCM[0].LOCKED
CELL[1].IMUX_SR_OPTINV[0]	DCM[0].FREEZE_DLL
CELL[1].IMUX_SR_OPTINV[1]	DCM[0].FREEZE_DFS
CELL[1].IMUX_IMUX[0]	DCM[0].DI[8]
CELL[1].IMUX_IMUX[1]	DCM[0].DI[9]
CELL[1].IMUX_IMUX[2]	DCM[0].DI[10]
CELL[1].IMUX_IMUX[3]	DCM[0].DI[11]
CELL[1].IMUX_IMUX[4]	DCM[0].DI[12]
CELL[1].IMUX_IMUX[5]	DCM[0].DI[13]
CELL[1].IMUX_IMUX[6]	DCM[0].DI[14]
CELL[1].IMUX_IMUX[7]	DCM[0].DI[15]
CELL[1].OUT_BEST_TMIN[0]	DCM[0].CLK270
CELL[1].OUT_BEST_TMIN[1]	DCM[0].CLK2X180
CELL[1].OUT_BEST_TMIN[2]	DCM[0].CLK2X
CELL[1].OUT_BEST_TMIN[4]	DCM[0].DO[8]
CELL[1].OUT_BEST_TMIN[5]	DCM[0].DO[9]
CELL[1].OUT_BEST_TMIN[6]	DCM[0].DO[10]
CELL[1].OUT_BEST_TMIN[7]	DCM[0].DO[11]
CELL[2].IMUX_CLK_OPTINV[0]	DCM[0].DCLK
CELL[2].IMUX_CLK_OPTINV[1]	DCM[0].PSCLK
CELL[2].IMUX_CE_OPTINV[0]	DCM[0].DWE
CELL[2].IMUX_CE_OPTINV[1]	DCM[0].DEN
CELL[2].IMUX_IMUX[0]	DCM[0].DI[0]
CELL[2].IMUX_IMUX[1]	DCM[0].DI[1]
CELL[2].IMUX_IMUX[2]	DCM[0].DI[2]
CELL[2].IMUX_IMUX[3]	DCM[0].DI[3]
CELL[2].IMUX_IMUX[4]	DCM[0].DI[4]
CELL[2].IMUX_IMUX[5]	DCM[0].DI[5]
CELL[2].IMUX_IMUX[6]	DCM[0].DI[6]
CELL[2].IMUX_IMUX[7]	DCM[0].DI[7]
CELL[2].OUT_BEST_TMIN[0]	DCM[0].CLK0
CELL[2].OUT_BEST_TMIN[1]	DCM[0].CLK180
CELL[2].OUT_BEST_TMIN[2]	DCM[0].CLK90
CELL[2].OUT_BEST_TMIN[4]	DCM[0].DO[4]
CELL[2].OUT_BEST_TMIN[5]	DCM[0].DO[5]
CELL[2].OUT_BEST_TMIN[6]	DCM[0].DO[6]
CELL[2].OUT_BEST_TMIN[7]	DCM[0].DO[7]
CELL[2].IMUX_SPEC[0]	DCM[0].CLKFB
CELL[3].IMUX_SR_OPTINV[0]	DCM[0].RST
CELL[3].IMUX_IMUX[0]	DCM[0].DADDR[0]
CELL[3].IMUX_IMUX[1]	DCM[0].DADDR[1]
CELL[3].IMUX_IMUX[2]	DCM[0].DADDR[2]
CELL[3].IMUX_IMUX[3]	DCM[0].DADDR[3]
CELL[3].IMUX_IMUX[4]	DCM[0].DADDR[4]
CELL[3].IMUX_IMUX[5]	DCM[0].DADDR[5]
CELL[3].IMUX_IMUX[6]	DCM[0].DADDR[6]
CELL[3].OUT_BEST_TMIN[0]	DCM[0].CONCUR
CELL[3].OUT_BEST_TMIN[1]	DCM[0].CLKFX
CELL[3].OUT_BEST_TMIN[2]	DCM[0].CLKFX180
CELL[3].OUT_BEST_TMIN[4]	DCM[0].DO[0]
CELL[3].OUT_BEST_TMIN[5]	DCM[0].DO[1]
CELL[3].OUT_BEST_TMIN[6]	DCM[0].DO[2]
CELL[3].OUT_BEST_TMIN[7]	DCM[0].DO[3]
CELL[3].OUT_SEC_TMIN[0]	DCM[0].LOCKED
CELL[3].OUT_SEC_TMIN[1]	DCM[0].PSDONE
CELL[3].OUT_SEC_TMIN[2]	DCM[0].DRDY
CELL[3].IMUX_SPEC[0]	DCM[0].CLKIN

Bitstream

virtex4 DCM rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 19	DCM[0]: DRP_MASK bit 3	-	-	-	-	-	-	-	-	-
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 1	-	-	-	-	-	-	-	-
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 15 DCM[0]: DLL_CONTROL_CLOCK_SPEED bit 0	DCM[0]: DRP[3] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 3	-	-	-	-	-	-	-	-
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 14 DCM[0]: STARTUP_WAIT	DCM[0]: DRP[3] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 2	-	-	-	-	-	-	-	-
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 13 DCM[0]: DLL_PHASE_DETECTOR_AUTO_RESET	DCM[0]: DRP[3] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 7	-	-	-	-	-	-	-	-
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 12 DCM[0]: CLKFB_ENABLE	DCM[0]: DRP[3] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 5	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 11 DCM[0]: DFS_FINE_SEL bit 0	DCM[0]: DRP[3] bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 6	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 10 DCM[0]: DFS_COARSE_SEL bit 0	DCM[0]: DRP[3] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 4	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 9 DCM[0]: DFS_EARLY_LOCK	DCM[0]: DRP[3] bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 1	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 8 DCM[0]: DFS_ENABLE	DCM[0]: DRP[3] bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 3	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 7 DCM[0]: DFS_HARDSYNC bit 1	DCM[0]: DRP[3] bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 2	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 6 DCM[0]: DFS_HARDSYNC bit 0	DCM[0]: DRP[3] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 7	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 5 DCM[0]: DCM_CLKDV_CLKFX_ALIGNMENT	DCM[0]: DRP[3] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 5	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 4 DCM[0]: DLL_CTL_SEL_CLKIN_DIV2	DCM[0]: DRP[3] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 6	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 3 DCM[0]: DFS_OSCILLATOR_MODE bit 1	DCM[0]: DRP[3] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 4	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 2 DCM[0]: DFS_OSCILLATOR_MODE bit 0	DCM[0]: DRP[3] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 1	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 1 DCM[0]: DFS_TP_SEL bit 0	DCM[0]: DRP[3] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 3	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLOSC1	DCM[0]: DRP[19] bit 0	DCM[0]: DRP[3] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 2	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLGO	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 7	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 5	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLSEL[1]	DCM[0]: DRP_MASK bit 18	DCM[0]: DRP_MASK bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 6	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert PSINCDEC	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 4	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 15	DCM[0]: DRP[2] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 1	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 14	DCM[0]: DRP[2] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 3	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 13	DCM[0]: DRP[2] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 2	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 12	DCM[0]: DRP[2] bit 12	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 11	DCM[0]: DRP[2] bit 11	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 10	DCM[0]: DRP[2] bit 10	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 9	DCM[0]: DRP[2] bit 9	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 8	DCM[0]: DRP[2] bit 8	SPEC_INT: wire support (CELL[0].MGT_DCM[3]) bit 0	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 7	DCM[0]: DRP[2] bit 7	SPEC_INT: wire support (CELL[0].MGT_DCM[2]) bit 0	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 6	DCM[0]: DRP[2] bit 6 DCM[0]: CLKIN_IOB	SPEC_INT: wire support (CELL[0].MGT_DCM[1]) bit 0	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 5	DCM[0]: DRP[2] bit 5 DCM[0]: CLKFB_IOB	SPEC_INT: wire support (CELL[0].MGT_DCM[0]) bit 0	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 4 DCM[0]: CLKFX_DIVIDE bit 4	DCM[0]: DRP[2] bit 4 DCM[0]: DESKEW_ADJUST bit 4	SPEC_INT: wire support (CELL[0].GIOB_DCM[15]) bit 0	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 3 DCM[0]: CLKFX_DIVIDE bit 3	DCM[0]: DRP[2] bit 3 DCM[0]: DESKEW_ADJUST bit 3	SPEC_INT: wire support (CELL[0].GIOB_DCM[14]) bit 0	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 2 DCM[0]: CLKFX_DIVIDE bit 2	DCM[0]: DRP[2] bit 2 DCM[0]: DESKEW_ADJUST bit 2	SPEC_INT: wire support (CELL[0].GIOB_DCM[13]) bit 0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 1 DCM[0]: CLKFX_DIVIDE bit 1	DCM[0]: DRP[2] bit 1 DCM[0]: DESKEW_ADJUST bit 1	SPEC_INT: wire support (CELL[0].GIOB_DCM[12]) bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 0 DCM[0]: CLKFX_DIVIDE bit 0	DCM[0]: DRP[2] bit 0 DCM[0]: DESKEW_ADJUST bit 0	SPEC_INT: wire support (CELL[0].GIOB_DCM[11]) bit 0	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: wire support (CELL[0].GIOB_DCM[10]) bit 0	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: wire support (CELL[0].GIOB_DCM[9]) bit 0	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 17	DCM[0]: DRP_MASK bit 1	SPEC_INT: wire support (CELL[0].GIOB_DCM[8]) bit 0	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: wire support (CELL[0].GIOB_DCM[7]) bit 0	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 15	DCM[0]: DRP[1] bit 15	SPEC_INT: wire support (CELL[0].GIOB_DCM[6]) bit 0	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 14	DCM[0]: DRP[1] bit 14	SPEC_INT: wire support (CELL[0].GIOB_DCM[5]) bit 0	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 13	DCM[0]: DRP[1] bit 13	SPEC_INT: wire support (CELL[0].GIOB_DCM[4]) bit 0	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 12	DCM[0]: DRP[1] bit 12	SPEC_INT: wire support (CELL[0].GIOB_DCM[3]) bit 0	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 11	DCM[0]: DRP[1] bit 11	SPEC_INT: wire support (CELL[0].GIOB_DCM[2]) bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 10 DCM[0]: OUT_CONCUR_ENABLE	DCM[0]: DRP[1] bit 10	SPEC_INT: wire support (CELL[0].GIOB_DCM[1]) bit 0	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 9 DCM[0]: OUT_CLKFX_ENABLE	DCM[0]: DRP[1] bit 9	SPEC_INT: wire support (CELL[0].GIOB_DCM[0]) bit 0	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 8 DCM[0]: OUT_CLKFX180_ENABLE	DCM[0]: DRP[1] bit 8	SPEC_INT: wire support (CELL[0].HCLK_DCM[7]) bit 0	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 7	DCM[0]: DRP[1] bit 7	SPEC_INT: wire support (CELL[0].HCLK_DCM[6]) bit 0	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 6	DCM[0]: DRP[1] bit 6 DCM[0]: DCM_EXT_FB_EN	SPEC_INT: wire support (CELL[0].HCLK_DCM[5]) bit 0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 5 DCM[0]: DFS_TRACKMODE	DCM[0]: DRP[1] bit 5 DCM[0]: DFS_FREQUENCY_MODE bit 0	SPEC_INT: wire support (CELL[0].HCLK_DCM[4]) bit 0	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 4 DCM[0]: CLKIN_ENABLE	DCM[0]: DRP[1] bit 4 DCM[0]: DFS_NON_STOP	SPEC_INT: wire support (CELL[0].HCLK_DCM[3]) bit 0	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 3 DCM[0]: CLKIN_DIVIDE_BY_2	DCM[0]: DRP[1] bit 3 DCM[0]: DFS_SKIP_FINE	SPEC_INT: wire support (CELL[0].HCLK_DCM[2]) bit 0	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 2 DCM[0]: ! DFS_EN_RELRST	DCM[0]: DRP[1] bit 2 DCM[0]: DFS_FEEDBACK	SPEC_INT: wire support (CELL[0].HCLK_DCM[1]) bit 0	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert PSEN	DCM[0]: DRP[17] bit 1	DCM[0]: DRP[1] bit 1 DCM[0]: CLK_FEEDBACK bit 1	SPEC_INT: wire support (CELL[0].HCLK_DCM[0]) bit 0	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLOSC2	DCM[0]: DRP[17] bit 0	DCM[0]: DRP[1] bit 0 DCM[0]: CLK_FEEDBACK bit 0	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 0	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 2	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLSEL[0]	-	-	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 3	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert CTLSEL[2]	DCM[0]: DRP_MASK bit 16	DCM[0]: DRP_MASK bit 0	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 4	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 1	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 15	DCM[0]: DRP[0] bit 15 DCM[0]: DFS_SPARE bit 15	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 9	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 14	DCM[0]: DRP[0] bit 14 DCM[0]: DFS_SPARE bit 14	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 8	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 13	DCM[0]: DRP[0] bit 13 DCM[0]: DFS_SPARE bit 13	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 10	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 12	DCM[0]: DRP[0] bit 12 DCM[0]: DFS_SPARE bit 12	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 7	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 11	DCM[0]: DRP[0] bit 11 DCM[0]: DFS_SPARE bit 11	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 6	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 10	DCM[0]: DRP[0] bit 10 DCM[0]: DFS_SPARE bit 10	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 5	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 9	DCM[0]: DRP[0] bit 9 DCM[0]: DFS_SPARE bit 9	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 0	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 8	DCM[0]: DRP[0] bit 8 DCM[0]: DFS_SPARE bit 8	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 2	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 7	DCM[0]: DRP[0] bit 7 DCM[0]: DFS_SPARE bit 7	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 3	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 6	DCM[0]: DRP[0] bit 6 DCM[0]: DFS_SPARE bit 6	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 4	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 5	DCM[0]: DRP[0] bit 5 DCM[0]: DFS_SPARE bit 5	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 1	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 4 DCM[0]: CLKFX_MULTIPLY bit 4	DCM[0]: DRP[0] bit 4 DCM[0]: DFS_SPARE bit 4	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 9	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 3 DCM[0]: CLKFX_MULTIPLY bit 3	DCM[0]: DRP[0] bit 3 DCM[0]: DFS_SPARE bit 3	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 8	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 2 DCM[0]: CLKFX_MULTIPLY bit 2	DCM[0]: DRP[0] bit 2 DCM[0]: DFS_SPARE bit 2	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 10	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 1 DCM[0]: CLKFX_MULTIPLY bit 1	DCM[0]: DRP[0] bit 1 DCM[0]: DFS_SPARE bit 1	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 7	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 0 DCM[0]: CLKFX_MULTIPLY bit 0	DCM[0]: DRP[0] bit 0 DCM[0]: DFS_SPARE bit 0	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 6	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 5	-	-	-	-	-	-	-	-

virtex4 DCM rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 23	DCM[0]: DRP_MASK bit 7	-	-	-	-	-	-	-	-	-
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 15 DCM[0]: DLL_PHASE_SHIFT_HFC bit 7	DCM[0]: DRP[7] bit 15	-	-	-	-	-	-	-	-	-
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 14 DCM[0]: DLL_PHASE_SHIFT_HFC bit 6	DCM[0]: DRP[7] bit 14	-	-	-	-	-	-	-	-	-
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 13 DCM[0]: DLL_PHASE_SHIFT_HFC bit 5	DCM[0]: DRP[7] bit 13	-	-	-	-	-	-	-	-	-
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 12 DCM[0]: DLL_PHASE_SHIFT_HFC bit 4	DCM[0]: DRP[7] bit 12	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 11 DCM[0]: DLL_PHASE_SHIFT_HFC bit 3	DCM[0]: DRP[7] bit 11	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 10 DCM[0]: DLL_PHASE_SHIFT_HFC bit 2	DCM[0]: DRP[7] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 6	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 9 DCM[0]: DLL_PHASE_SHIFT_HFC bit 1	DCM[0]: DRP[7] bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 4	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 8 DCM[0]: DLL_PHASE_SHIFT_HFC bit 0	DCM[0]: DRP[7] bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 1	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 7 DCM[0]: DLL_PHASE_SHIFT_LFC bit 7	DCM[0]: DRP[7] bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 3	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 6 DCM[0]: DLL_PHASE_SHIFT_LFC bit 6	DCM[0]: DRP[7] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 2	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 5 DCM[0]: DLL_PHASE_SHIFT_LFC bit 5	DCM[0]: DRP[7] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 7	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 4 DCM[0]: DLL_PHASE_SHIFT_LFC bit 4	DCM[0]: DRP[7] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 5	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 3 DCM[0]: DLL_PHASE_SHIFT_LFC bit 3	DCM[0]: DRP[7] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 6	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 2 DCM[0]: DLL_PHASE_SHIFT_LFC bit 2	DCM[0]: DRP[7] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 4	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 1 DCM[0]: DLL_PHASE_SHIFT_LFC bit 1	DCM[0]: DRP[7] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 1	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[13]	DCM[0]: DRP[23] bit 0 DCM[0]: DLL_PHASE_SHIFT_LFC bit 0	DCM[0]: DRP[7] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 3	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[15]	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 2	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 7	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[9]	DCM[0]: DRP_MASK bit 22	DCM[0]: DRP_MASK bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 5	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[11]	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 6	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 15	DCM[0]: DRP[6] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 4	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 14 DCM[0]: DCM_UNUSED_TAPS_POWERDOWN	DCM[0]: DRP[6] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 1	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 13	DCM[0]: DRP[6] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 3	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 12	DCM[0]: DRP[6] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 2	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 11	DCM[0]: DRP[6] bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 7	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 10	DCM[0]: DRP[6] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 5	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 9 DCM[0]: UNK_ALWAYS_SET	DCM[0]: DRP[6] bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 6	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 8	DCM[0]: DRP[6] bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 4	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 7 DCM[0]: DLL_PHASE_SHIFT_LOCK_BY1	DCM[0]: DRP[6] bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 1	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 6	DCM[0]: DRP[6] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 3	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 5 DCM[0]: DLL_PHASE_SHIFT_CALIBRATION bit 1	DCM[0]: DRP[6] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 2	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 4 DCM[0]: DLL_PHASE_SHIFT_CALIBRATION bit 0	DCM[0]: DRP[6] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 7	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 3 DCM[0]: PS_ENABLE	DCM[0]: DRP[6] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 5	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 2 DCM[0]: PS_MODE bit 0	DCM[0]: DRP[6] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 6	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 1 DCM[0]: PS_CENTERED	DCM[0]: DRP[6] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 4	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 0 DCM[0]: PS_DIRECT	DCM[0]: DRP[6] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 1	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 3	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 2	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 21	DCM[0]: DRP_MASK bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 7	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 5	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 15	DCM[0]: DRP[5] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 6	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 14	DCM[0]: DRP[5] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 4	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 13	DCM[0]: DRP[5] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 1	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 12	DCM[0]: DRP[5] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 3	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 11	DCM[0]: DRP[5] bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 2	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 10 DCM[0]: PHASE_SHIFT_NEGATIVE	DCM[0]: DRP[5] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 7	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 9 DCM[0]: PHASE_SHIFT bit 9	DCM[0]: DRP[5] bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 5	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 8 DCM[0]: PHASE_SHIFT bit 8	DCM[0]: DRP[5] bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 6	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 7 DCM[0]: PHASE_SHIFT bit 7	DCM[0]: DRP[5] bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 4	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 6 DCM[0]: PHASE_SHIFT bit 6	DCM[0]: DRP[5] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 1	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 5 DCM[0]: PHASE_SHIFT bit 5	DCM[0]: DRP[5] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 3	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 4 DCM[0]: PHASE_SHIFT bit 4	DCM[0]: DRP[5] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 2	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 3 DCM[0]: PHASE_SHIFT bit 3	DCM[0]: DRP[5] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 7	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 2 DCM[0]: PHASE_SHIFT bit 2	DCM[0]: DRP[5] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 5	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[12]	DCM[0]: DRP[21] bit 1 DCM[0]: PHASE_SHIFT bit 1	DCM[0]: DRP[5] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 6	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[14]	DCM[0]: DRP[21] bit 0 DCM[0]: PHASE_SHIFT bit 0	DCM[0]: DRP[5] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 4	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 1	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[8]	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 3	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[10]	DCM[0]: DRP_MASK bit 20	DCM[0]: DRP_MASK bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 2	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 7	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 15	DCM[0]: DRP[4] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 5	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 14 DCM[0]: DFS_COIN_WINDOW bit 1	DCM[0]: DRP[4] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 6	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 13 DCM[0]: DFS_COIN_WINDOW bit 0	DCM[0]: DRP[4] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 4	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 12 DCM[0]: DFS_EXTEND_HALT_TIME	DCM[0]: DRP[4] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 1	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 11 DCM[0]: DFS_EXTEND_RUN_TIME	DCM[0]: DRP[4] bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 3	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 10 DCM[0]: DFS_EXTEND_FLUSH_TIME	DCM[0]: DRP[4] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 2	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 9 DCM[0]: DFS_AVE_FREQ_GAIN bit 2	DCM[0]: DRP[4] bit 9 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_HIGH bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 7	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 8 DCM[0]: DFS_AVE_FREQ_GAIN bit 1	DCM[0]: DRP[4] bit 8 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_HIGH bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 5	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 7 DCM[0]: DFS_AVE_FREQ_GAIN bit 0	DCM[0]: DRP[4] bit 7 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_HIGH bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 6	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 6 DCM[0]: DFS_AVE_FREQ_ADJ_INTERVAL bit 3	DCM[0]: DRP[4] bit 6 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_HIGH bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 4	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 5 DCM[0]: DFS_AVE_FREQ_ADJ_INTERVAL bit 2	DCM[0]: DRP[4] bit 5 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_HIGH bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 1	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 4 DCM[0]: DFS_AVE_FREQ_ADJ_INTERVAL bit 1	DCM[0]: DRP[4] bit 4 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_LOW bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 3	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 3 DCM[0]: DFS_AVE_FREQ_ADJ_INTERVAL bit 0	DCM[0]: DRP[4] bit 3 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_LOW bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 2	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 2 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 2	DCM[0]: DRP[4] bit 2 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_LOW bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 7	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 1 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 1	DCM[0]: DRP[4] bit 1 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_LOW bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 5	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 0 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 0	DCM[0]: DRP[4] bit 0 DCM[0]: DCM_PULSE_WIDTH_CORRECTION_LOW bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 6	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 4	-	-	-	-	-	-	-	-

virtex4 DCM rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 27	DCM[0]: DRP_MASK bit 11	-	-	-	-	-	-	-	-	-
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 15 DCM[0]: DLL_DESKEW_MAXTAP bit 7	DCM[0]: DRP[11] bit 15	-	-	-	-	-	-	-	-	-
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 14 DCM[0]: DLL_DESKEW_MAXTAP bit 6	DCM[0]: DRP[11] bit 14	-	-	-	-	-	-	-	-	-
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 13 DCM[0]: DLL_DESKEW_MAXTAP bit 5	DCM[0]: DRP[11] bit 13	-	-	-	-	-	-	-	-	-
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 12 DCM[0]: DLL_DESKEW_MAXTAP bit 4	DCM[0]: DRP[11] bit 12	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 11 DCM[0]: DLL_DESKEW_MAXTAP bit 3	DCM[0]: DRP[11] bit 11	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 10 DCM[0]: DLL_DESKEW_MAXTAP bit 2	DCM[0]: DRP[11] bit 10	-	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 9 DCM[0]: DLL_DESKEW_MAXTAP bit 1	DCM[0]: DRP[11] bit 9	-	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 8 DCM[0]: DLL_DESKEW_MAXTAP bit 0	DCM[0]: DRP[11] bit 8	-	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 7 DCM[0]: DLL_DESKEW_MINTAP bit 7	DCM[0]: DRP[11] bit 7	-	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 6 DCM[0]: DLL_DESKEW_MINTAP bit 6	DCM[0]: DRP[11] bit 6	-	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 5 DCM[0]: DLL_DESKEW_MINTAP bit 5	DCM[0]: DRP[11] bit 5	-	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 4 DCM[0]: DLL_DESKEW_MINTAP bit 4	DCM[0]: DRP[11] bit 4	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 3 DCM[0]: DLL_DESKEW_MINTAP bit 3	DCM[0]: DRP[11] bit 3	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 2 DCM[0]: DLL_DESKEW_MINTAP bit 2	DCM[0]: DRP[11] bit 2	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[27] bit 1 DCM[0]: DLL_DESKEW_MINTAP bit 1	DCM[0]: DRP[11] bit 1	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[5]	DCM[0]: DRP[27] bit 0 DCM[0]: DLL_DESKEW_MINTAP bit 0	DCM[0]: DRP[11] bit 0	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[7]	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[1]	DCM[0]: DRP_MASK bit 26	DCM[0]: DRP_MASK bit 10	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[3]	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 15	DCM[0]: DRP[10] bit 15	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 14	DCM[0]: DRP[10] bit 14	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 13 DCM[0]: DCM_VREG_PHASE_MARGIN bit 2	DCM[0]: DRP[10] bit 13	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 12 DCM[0]: DCM_VREG_PHASE_MARGIN bit 1	DCM[0]: DRP[10] bit 12	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 11 DCM[0]: DCM_VREG_PHASE_MARGIN bit 0	DCM[0]: DRP[10] bit 11	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 10 DCM[0]: DCM_VBG_PD bit 1	DCM[0]: DRP[10] bit 10	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 9 DCM[0]: DCM_VBG_PD bit 0	DCM[0]: DRP[10] bit 9	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 8 DCM[0]: DCM_VBG_SEL bit 3	DCM[0]: DRP[10] bit 8	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 7 DCM[0]: DCM_VBG_SEL bit 2	DCM[0]: DRP[10] bit 7	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 6 DCM[0]: DCM_VBG_SEL bit 1	DCM[0]: DRP[10] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 4	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 5 DCM[0]: DCM_VBG_SEL bit 0	DCM[0]: DRP[10] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 1	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 4 DCM[0]: DCM_VREG_ENABLE	DCM[0]: DRP[10] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 3	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 3 DCM[0]: DCM_VREF_SOURCE bit 2	DCM[0]: DRP[10] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 2	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 2 DCM[0]: DCM_VREF_SOURCE bit 1	DCM[0]: DRP[10] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 7	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 1 DCM[0]: DCM_VREF_SOURCE bit 0	DCM[0]: DRP[10] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 5	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[26] bit 0 DCM[0]: DCM_PERFORMANCE_MODE bit 0	DCM[0]: DRP[10] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 6	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 4	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 1	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 25	DCM[0]: DRP_MASK bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 3	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 2	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 15 DCM[0]: FACTORY_JF bit 15	DCM[0]: DRP[9] bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 7	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 14 DCM[0]: FACTORY_JF bit 14	DCM[0]: DRP[9] bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 5	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 13 DCM[0]: FACTORY_JF bit 13	DCM[0]: DRP[9] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 6	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 12 DCM[0]: FACTORY_JF bit 12	DCM[0]: DRP[9] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 4	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 11 DCM[0]: FACTORY_JF bit 11	DCM[0]: DRP[9] bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 1	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 10 DCM[0]: FACTORY_JF bit 10	DCM[0]: DRP[9] bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 3	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 9 DCM[0]: FACTORY_JF bit 9	DCM[0]: DRP[9] bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 2	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 8 DCM[0]: FACTORY_JF bit 8	DCM[0]: DRP[9] bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 7	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 7 DCM[0]: FACTORY_JF bit 7	DCM[0]: DRP[9] bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 5	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 6 DCM[0]: FACTORY_JF bit 6	DCM[0]: DRP[9] bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 6	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 5 DCM[0]: FACTORY_JF bit 5	DCM[0]: DRP[9] bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 4	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 4 DCM[0]: FACTORY_JF bit 4	DCM[0]: DRP[9] bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 1	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 3 DCM[0]: FACTORY_JF bit 3	DCM[0]: DRP[9] bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 3	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[25] bit 2 DCM[0]: FACTORY_JF bit 2	DCM[0]: DRP[9] bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 2	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[4]	DCM[0]: DRP[25] bit 1 DCM[0]: FACTORY_JF bit 1	DCM[0]: DRP[9] bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 7	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[6]	DCM[0]: DRP[25] bit 0 DCM[0]: FACTORY_JF bit 0	DCM[0]: DRP[9] bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 5	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 6	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[0]	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 4	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DI[2]	DCM[0]: DRP_MASK bit 24	DCM[0]: DRP_MASK bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 1	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 3	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 15	DCM[0]: DRP[8] bit 15 DCM[0]: DLL_SPARE bit 15	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 2	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 14	DCM[0]: DRP[8] bit 14 DCM[0]: DLL_SPARE bit 14	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 7	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 13	DCM[0]: DRP[8] bit 13 DCM[0]: DLL_SPARE bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 5	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 12	DCM[0]: DRP[8] bit 12 DCM[0]: DLL_SPARE bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 6	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 11	DCM[0]: DRP[8] bit 11 DCM[0]: DLL_SPARE bit 11	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 4	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 10	DCM[0]: DRP[8] bit 10 DCM[0]: DLL_SPARE bit 10	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 1	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 9 DCM[0]: ! DCM_LOCK_HIGH	DCM[0]: DRP[8] bit 9 DCM[0]: DLL_SPARE bit 9	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 3	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 8 DCM[0]: DLL_PHASE_DETECTOR_MODE bit 0	DCM[0]: DRP[8] bit 8 DCM[0]: DLL_SPARE bit 8	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 2	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 7 DCM[0]: DLL_FREQUENCY_MODE bit 1	DCM[0]: DRP[8] bit 7 DCM[0]: DLL_SPARE bit 7	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 7	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 6 DCM[0]: DLL_FREQUENCY_MODE bit 0	DCM[0]: DRP[8] bit 6 DCM[0]: DLL_SPARE bit 6	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 5	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 5 DCM[0]: DLL_ZD2_EN	DCM[0]: DRP[8] bit 5 DCM[0]: DLL_SPARE bit 5	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 6	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 4 DCM[0]: CLKFB_FEEDBACK	DCM[0]: DRP[8] bit 4 DCM[0]: DLL_SPARE bit 4	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 4	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 3	DCM[0]: DRP[8] bit 3 DCM[0]: DLL_SPARE bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 1	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 2	DCM[0]: DRP[8] bit 2 DCM[0]: DLL_SPARE bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 3	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 1 DCM[0]: DLL_DESKEW_LOCK_BY1	DCM[0]: DRP[8] bit 1 DCM[0]: DLL_SPARE bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 2	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[24] bit 0 DCM[0]: DLL_PERIOD_LOCK_BY1	DCM[0]: DRP[8] bit 0 DCM[0]: DLL_SPARE bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 7	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 5	-	-	-	-	-	-	-	-

virtex4 DCM rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 31	DCM[0]: DRP_MASK bit 15	-	-	-	-	-	-	-	-	-
B77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 15	DCM[0]: DRP[15] bit 15	-	-	-	-	-	-	-	-	-
B75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 14	DCM[0]: DRP[15] bit 14	-	-	-	-	-	-	-	-	-
B74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 13 DCM[0]: BGM_DIVIDE bit 5	DCM[0]: DRP[15] bit 13	-	-	-	-	-	-	-	-	-
B73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 12 DCM[0]: BGM_DIVIDE bit 4	DCM[0]: DRP[15] bit 12	-	-	-	-	-	-	-	-	-
B72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 11 DCM[0]: BGM_DIVIDE bit 3	DCM[0]: DRP[15] bit 11	-	-	-	-	-	-	-	-	-
B71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 10 DCM[0]: BGM_DIVIDE bit 2	DCM[0]: DRP[15] bit 10 DCM[0]: DLL_PD_DLY_SEL bit 2	-	-	-	-	-	-	-	-	-
B70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 9 DCM[0]: BGM_DIVIDE bit 1	DCM[0]: DRP[15] bit 9 DCM[0]: DLL_PD_DLY_SEL bit 1	-	-	-	-	-	-	-	-	-
B69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 8 DCM[0]: BGM_DIVIDE bit 0	DCM[0]: DRP[15] bit 8 DCM[0]: DLL_PD_DLY_SEL bit 0	-	-	-	-	-	-	-	-	-
B68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 7	DCM[0]: DRP[15] bit 7 DCM[0]: PMCD_SYNC	-	-	-	-	-	-	-	-	-
B67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 6	DCM[0]: DRP[15] bit 6	-	-	-	-	-	-	-	-	-
B66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 5 DCM[0]: BGM_MULTIPLY bit 5	DCM[0]: DRP[15] bit 5	-	-	-	-	-	-	-	-	-
B65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 4 DCM[0]: BGM_MULTIPLY bit 4	DCM[0]: DRP[15] bit 4	-	-	-	-	-	-	-	-	-
B64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 3 DCM[0]: BGM_MULTIPLY bit 3	DCM[0]: DRP[15] bit 3	-	-	-	-	-	-	-	-	-
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 2 DCM[0]: BGM_MULTIPLY bit 2	DCM[0]: DRP[15] bit 2	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[31] bit 1 DCM[0]: BGM_MULTIPLY bit 1	DCM[0]: DRP[15] bit 1	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[5]	DCM[0]: DRP[31] bit 0 DCM[0]: BGM_MULTIPLY bit 0	DCM[0]: DRP[15] bit 0	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[1]	DCM[0]: DRP_MASK bit 30	DCM[0]: DRP_MASK bit 14	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[3]	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 15	DCM[0]: DRP[14] bit 15 DCM[0]: DUTY_CYCLE_CORRECTION bit 3	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 14	DCM[0]: DRP[14] bit 14 DCM[0]: DUTY_CYCLE_CORRECTION bit 2	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 13	DCM[0]: DRP[14] bit 13 DCM[0]: DUTY_CYCLE_CORRECTION bit 1	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 12	DCM[0]: DRP[14] bit 12 DCM[0]: DUTY_CYCLE_CORRECTION bit 0	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 11	DCM[0]: DRP[14] bit 11	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 10	DCM[0]: DRP[14] bit 10	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 9	DCM[0]: DRP[14] bit 9 DCM[0]: DLL_TEST_MUX_SEL bit 1	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 8	DCM[0]: DRP[14] bit 8 DCM[0]: DLL_TEST_MUX_SEL bit 0	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 7 DCM[0]: DLL_SETTLE_TIME bit 7	DCM[0]: DRP[14] bit 7	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 6 DCM[0]: DLL_SETTLE_TIME bit 6	DCM[0]: DRP[14] bit 6 DCM[0]: OUT_CLKDV_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 0	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 5 DCM[0]: DLL_SETTLE_TIME bit 5	DCM[0]: DRP[14] bit 5 DCM[0]: OUT_CLK2X180_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 0	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 4 DCM[0]: DLL_SETTLE_TIME bit 4	DCM[0]: DRP[14] bit 4 DCM[0]: OUT_CLK2X_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 0	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 3 DCM[0]: DLL_SETTLE_TIME bit 3	DCM[0]: DRP[14] bit 3 DCM[0]: OUT_CLK270_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 0	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 2 DCM[0]: DLL_SETTLE_TIME bit 2	DCM[0]: DRP[14] bit 2 DCM[0]: OUT_CLK180_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[19] bit 0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 1 DCM[0]: DLL_SETTLE_TIME bit 1	DCM[0]: DRP[14] bit 1 DCM[0]: OUT_CLK90_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[18] bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[30] bit 0 DCM[0]: DLL_SETTLE_TIME bit 0	DCM[0]: DRP[14] bit 0 DCM[0]: OUT_CLK0_ENABLE	SPEC_INT: mux CELL[0].DCM_DCM_O[17] bit 0	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[16] bit 0	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[15] bit 0	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP_MASK bit 29	DCM[0]: DRP_MASK bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[14] bit 0	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[13] bit 0	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 15 DCM[0]: DLL_DEAD_TIME bit 7	DCM[0]: DRP[13] bit 15 DCM[0]: CLKDV_COUNT_FALL bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[12] bit 0	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 14 DCM[0]: DLL_DEAD_TIME bit 6	DCM[0]: DRP[13] bit 14 DCM[0]: CLKDV_COUNT_FALL bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[11] bit 0	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 13 DCM[0]: DLL_DEAD_TIME bit 5	DCM[0]: DRP[13] bit 13 DCM[0]: CLKDV_COUNT_FALL bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[10] bit 0	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 12 DCM[0]: DLL_DEAD_TIME bit 4	DCM[0]: DRP[13] bit 12 DCM[0]: CLKDV_COUNT_FALL bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[9] bit 0	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 11 DCM[0]: DLL_DEAD_TIME bit 3	DCM[0]: DRP[13] bit 11 DCM[0]: CLKDV_COUNT_FALL_2 bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[8] bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 10 DCM[0]: DLL_DEAD_TIME bit 2	DCM[0]: DRP[13] bit 10 DCM[0]: CLKDV_COUNT_FALL_2 bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[7] bit 0	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 9 DCM[0]: DLL_DEAD_TIME bit 1	DCM[0]: DRP[13] bit 9 DCM[0]: CLKDV_COUNT_FALL_2 bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[6] bit 0	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 8 DCM[0]: DLL_DEAD_TIME bit 0	DCM[0]: DRP[13] bit 8 DCM[0]: CLKDV_COUNT_FALL_2 bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[5] bit 0	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 7 DCM[0]: DLL_LIVE_TIME bit 7	DCM[0]: DRP[13] bit 7 DCM[0]: CLKDV_COUNT_MAX bit 3	SPEC_INT: mux CELL[0].DCM_DCM_O[4] bit 0	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 6 DCM[0]: DLL_LIVE_TIME bit 6	DCM[0]: DRP[13] bit 6 DCM[0]: CLKDV_COUNT_MAX bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[3] bit 0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 5 DCM[0]: DLL_LIVE_TIME bit 5	DCM[0]: DRP[13] bit 5 DCM[0]: CLKDV_COUNT_MAX bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[2] bit 0	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 4 DCM[0]: DLL_LIVE_TIME bit 4	DCM[0]: DRP[13] bit 4 DCM[0]: CLKDV_COUNT_MAX bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[1] bit 0	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 3 DCM[0]: DLL_LIVE_TIME bit 3	DCM[0]: DRP[13] bit 3 DCM[0]: CLKDV_PHASE_RISE bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[0] bit 0	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[29] bit 2 DCM[0]: DLL_LIVE_TIME bit 2	DCM[0]: DRP[13] bit 2 DCM[0]: CLKDV_PHASE_RISE bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 7	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[4]	DCM[0]: DRP[29] bit 1 DCM[0]: DLL_LIVE_TIME bit 1	DCM[0]: DRP[13] bit 1 DCM[0]: CLKDV_PHASE_FALL bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 5	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[6]	DCM[0]: DRP[29] bit 0 DCM[0]: DLL_LIVE_TIME bit 0	DCM[0]: DRP[13] bit 0 DCM[0]: CLKDV_PHASE_FALL bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 6	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 4	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[0]	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 1	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: !invert DADDR[2]	DCM[0]: DRP_MASK bit 28	DCM[0]: DRP_MASK bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 3	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[23] bit 2	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 15	DCM[0]: DRP[12] bit 15 DCM[0]: CLKDV_MODE bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 7	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 14	DCM[0]: DRP[12] bit 14 DCM[0]: BGM_CONFIG_REF_SEL bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 5	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 13	DCM[0]: DRP[12] bit 13	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 6	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 12	DCM[0]: DRP[12] bit 12	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 4	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 11	DCM[0]: DRP[12] bit 11 DCM[0]: BGM_LDLY bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 1	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 10	DCM[0]: DRP[12] bit 10 DCM[0]: BGM_LDLY bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 3	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 9	DCM[0]: DRP[12] bit 9 DCM[0]: BGM_LDLY bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[22] bit 2	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 8 DCM[0]: BGM_SAMPLE_LEN bit 2	DCM[0]: DRP[12] bit 8 DCM[0]: BGM_SDLY bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 7	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 7 DCM[0]: BGM_SAMPLE_LEN bit 1	DCM[0]: DRP[12] bit 7 DCM[0]: BGM_SDLY bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 5	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 6 DCM[0]: BGM_SAMPLE_LEN bit 0	DCM[0]: DRP[12] bit 6 DCM[0]: BGM_SDLY bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 6	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 5 DCM[0]: BGM_VADJ bit 3	DCM[0]: DRP[12] bit 5 DCM[0]: BGM_VLDLY bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 4	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 4 DCM[0]: BGM_VADJ bit 2	DCM[0]: DRP[12] bit 4 DCM[0]: BGM_VLDLY bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 1	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 3 DCM[0]: BGM_VADJ bit 1	DCM[0]: DRP[12] bit 3 DCM[0]: BGM_VLDLY bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 3	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 2 DCM[0]: BGM_VADJ bit 0	DCM[0]: DRP[12] bit 2 DCM[0]: BGM_VSDLY bit 2	SPEC_INT: mux CELL[0].DCM_DCM_O[21] bit 2	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 1 DCM[0]: BGM_MODE bit 1	DCM[0]: DRP[12] bit 1 DCM[0]: BGM_VSDLY bit 1	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 7	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[28] bit 0 DCM[0]: BGM_MODE bit 0	DCM[0]: DRP[12] bit 0 DCM[0]: BGM_VSDLY bit 0	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 5	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].DCM_DCM_O[20] bit 6	-	-	-	-	-	-	-	-

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