Configuration Center

TODO: document

Tile CFG

Cells: 16

Bel BUFGCTRL0

virtex4 CFG bel BUFGCTRL0
Pin	Direction	Wires
CE0	input	TCELL1:IMUX.IMUX1
CE1	input	TCELL1:IMUX.IMUX9
CKINT0	input	TCELL1:IMUX.IMUX3
CKINT1	input	TCELL1:IMUX.IMUX11
I0MUX	output	TCELL0:TEST1
I1MUX	output	TCELL0:TEST0
IGNORE0	input	TCELL1:IMUX.IMUX2
IGNORE1	input	TCELL1:IMUX.IMUX10
S0	input	TCELL1:IMUX.IMUX0
S1	input	TCELL1:IMUX.IMUX8

Bel BUFGCTRL1

virtex4 CFG bel BUFGCTRL1
Pin	Direction	Wires
CE0	input	TCELL1:IMUX.IMUX5
CE1	input	TCELL1:IMUX.IMUX13
CKINT0	input	TCELL1:IMUX.IMUX7
CKINT1	input	TCELL1:IMUX.IMUX15
I0MUX	output	TCELL0:TEST3
I1MUX	output	TCELL0:TEST2
IGNORE0	input	TCELL1:IMUX.IMUX6
IGNORE1	input	TCELL1:IMUX.IMUX14
S0	input	TCELL1:IMUX.IMUX4
S1	input	TCELL1:IMUX.IMUX12

Bel BUFGCTRL2

virtex4 CFG bel BUFGCTRL2
Pin	Direction	Wires
CE0	input	TCELL1:IMUX.IMUX17
CE1	input	TCELL1:IMUX.IMUX25
CKINT0	input	TCELL1:IMUX.IMUX19
CKINT1	input	TCELL1:IMUX.IMUX27
I0MUX	output	TCELL1:TEST1
I1MUX	output	TCELL1:TEST0
IGNORE0	input	TCELL1:IMUX.IMUX18
IGNORE1	input	TCELL1:IMUX.IMUX26
S0	input	TCELL1:IMUX.IMUX16
S1	input	TCELL1:IMUX.IMUX24

Bel BUFGCTRL3

virtex4 CFG bel BUFGCTRL3
Pin	Direction	Wires
CE0	input	TCELL1:IMUX.IMUX21
CE1	input	TCELL1:IMUX.IMUX29
CKINT0	input	TCELL1:IMUX.IMUX23
CKINT1	input	TCELL1:IMUX.IMUX31
I0MUX	output	TCELL1:TEST3
I1MUX	output	TCELL1:TEST2
IGNORE0	input	TCELL1:IMUX.IMUX22
IGNORE1	input	TCELL1:IMUX.IMUX30
S0	input	TCELL1:IMUX.IMUX20
S1	input	TCELL1:IMUX.IMUX28

Bel BUFGCTRL4

virtex4 CFG bel BUFGCTRL4
Pin	Direction	Wires
CE0	input	TCELL2:IMUX.IMUX1
CE1	input	TCELL2:IMUX.IMUX9
CKINT0	input	TCELL2:IMUX.IMUX3
CKINT1	input	TCELL2:IMUX.IMUX11
I0MUX	output	TCELL2:TEST1
I1MUX	output	TCELL2:TEST0
IGNORE0	input	TCELL2:IMUX.IMUX2
IGNORE1	input	TCELL2:IMUX.IMUX10
S0	input	TCELL2:IMUX.IMUX0
S1	input	TCELL2:IMUX.IMUX8

Bel BUFGCTRL5

virtex4 CFG bel BUFGCTRL5
Pin	Direction	Wires
CE0	input	TCELL2:IMUX.IMUX5
CE1	input	TCELL2:IMUX.IMUX13
CKINT0	input	TCELL2:IMUX.IMUX7
CKINT1	input	TCELL2:IMUX.IMUX15
I0MUX	output	TCELL2:TEST3
I1MUX	output	TCELL2:TEST2
IGNORE0	input	TCELL2:IMUX.IMUX6
IGNORE1	input	TCELL2:IMUX.IMUX14
S0	input	TCELL2:IMUX.IMUX4
S1	input	TCELL2:IMUX.IMUX12

Bel BUFGCTRL6

virtex4 CFG bel BUFGCTRL6
Pin	Direction	Wires
CE0	input	TCELL2:IMUX.IMUX17
CE1	input	TCELL2:IMUX.IMUX25
CKINT0	input	TCELL2:IMUX.IMUX19
CKINT1	input	TCELL2:IMUX.IMUX27
I0MUX	output	TCELL3:TEST1
I1MUX	output	TCELL3:TEST0
IGNORE0	input	TCELL2:IMUX.IMUX18
IGNORE1	input	TCELL2:IMUX.IMUX26
S0	input	TCELL2:IMUX.IMUX16
S1	input	TCELL2:IMUX.IMUX24

Bel BUFGCTRL7

virtex4 CFG bel BUFGCTRL7
Pin	Direction	Wires
CE0	input	TCELL2:IMUX.IMUX21
CE1	input	TCELL2:IMUX.IMUX29
CKINT0	input	TCELL2:IMUX.IMUX23
CKINT1	input	TCELL2:IMUX.IMUX31
I0MUX	output	TCELL3:TEST3
I1MUX	output	TCELL3:TEST2
IGNORE0	input	TCELL2:IMUX.IMUX22
IGNORE1	input	TCELL2:IMUX.IMUX30
S0	input	TCELL2:IMUX.IMUX20
S1	input	TCELL2:IMUX.IMUX28

Bel BUFGCTRL8

virtex4 CFG bel BUFGCTRL8
Pin	Direction	Wires
CE0	input	TCELL3:IMUX.IMUX1
CE1	input	TCELL3:IMUX.IMUX9
CKINT0	input	TCELL3:IMUX.IMUX3
CKINT1	input	TCELL3:IMUX.IMUX11
I0MUX	output	TCELL4:TEST1
I1MUX	output	TCELL4:TEST0
IGNORE0	input	TCELL3:IMUX.IMUX2
IGNORE1	input	TCELL3:IMUX.IMUX10
S0	input	TCELL3:IMUX.IMUX0
S1	input	TCELL3:IMUX.IMUX8

Bel BUFGCTRL9

virtex4 CFG bel BUFGCTRL9
Pin	Direction	Wires
CE0	input	TCELL3:IMUX.IMUX5
CE1	input	TCELL3:IMUX.IMUX13
CKINT0	input	TCELL3:IMUX.IMUX7
CKINT1	input	TCELL3:IMUX.IMUX15
I0MUX	output	TCELL4:TEST3
I1MUX	output	TCELL4:TEST2
IGNORE0	input	TCELL3:IMUX.IMUX6
IGNORE1	input	TCELL3:IMUX.IMUX14
S0	input	TCELL3:IMUX.IMUX4
S1	input	TCELL3:IMUX.IMUX12

Bel BUFGCTRL10

virtex4 CFG bel BUFGCTRL10
Pin	Direction	Wires
CE0	input	TCELL3:IMUX.IMUX17
CE1	input	TCELL3:IMUX.IMUX25
CKINT0	input	TCELL3:IMUX.IMUX19
CKINT1	input	TCELL3:IMUX.IMUX27
I0MUX	output	TCELL5:TEST1
I1MUX	output	TCELL5:TEST0
IGNORE0	input	TCELL3:IMUX.IMUX18
IGNORE1	input	TCELL3:IMUX.IMUX26
S0	input	TCELL3:IMUX.IMUX16
S1	input	TCELL3:IMUX.IMUX24

Bel BUFGCTRL11

virtex4 CFG bel BUFGCTRL11
Pin	Direction	Wires
CE0	input	TCELL3:IMUX.IMUX21
CE1	input	TCELL3:IMUX.IMUX29
CKINT0	input	TCELL3:IMUX.IMUX23
CKINT1	input	TCELL3:IMUX.IMUX31
I0MUX	output	TCELL5:TEST3
I1MUX	output	TCELL5:TEST2
IGNORE0	input	TCELL3:IMUX.IMUX22
IGNORE1	input	TCELL3:IMUX.IMUX30
S0	input	TCELL3:IMUX.IMUX20
S1	input	TCELL3:IMUX.IMUX28

Bel BUFGCTRL12

virtex4 CFG bel BUFGCTRL12
Pin	Direction	Wires
CE0	input	TCELL4:IMUX.IMUX1
CE1	input	TCELL4:IMUX.IMUX9
CKINT0	input	TCELL4:IMUX.IMUX3
CKINT1	input	TCELL4:IMUX.IMUX11
I0MUX	output	TCELL6:TEST1
I1MUX	output	TCELL6:TEST0
IGNORE0	input	TCELL4:IMUX.IMUX2
IGNORE1	input	TCELL4:IMUX.IMUX10
S0	input	TCELL4:IMUX.IMUX0
S1	input	TCELL4:IMUX.IMUX8

Bel BUFGCTRL13

virtex4 CFG bel BUFGCTRL13
Pin	Direction	Wires
CE0	input	TCELL4:IMUX.IMUX5
CE1	input	TCELL4:IMUX.IMUX13
CKINT0	input	TCELL4:IMUX.IMUX7
CKINT1	input	TCELL4:IMUX.IMUX15
I0MUX	output	TCELL6:TEST3
I1MUX	output	TCELL6:TEST2
IGNORE0	input	TCELL4:IMUX.IMUX6
IGNORE1	input	TCELL4:IMUX.IMUX14
S0	input	TCELL4:IMUX.IMUX4
S1	input	TCELL4:IMUX.IMUX12

Bel BUFGCTRL14

virtex4 CFG bel BUFGCTRL14
Pin	Direction	Wires
CE0	input	TCELL4:IMUX.IMUX17
CE1	input	TCELL4:IMUX.IMUX25
CKINT0	input	TCELL4:IMUX.IMUX19
CKINT1	input	TCELL4:IMUX.IMUX27
I0MUX	output	TCELL7:TEST1
I1MUX	output	TCELL7:TEST0
IGNORE0	input	TCELL4:IMUX.IMUX18
IGNORE1	input	TCELL4:IMUX.IMUX26
S0	input	TCELL4:IMUX.IMUX16
S1	input	TCELL4:IMUX.IMUX24

Bel BUFGCTRL15

virtex4 CFG bel BUFGCTRL15
Pin	Direction	Wires
CE0	input	TCELL4:IMUX.IMUX21
CE1	input	TCELL4:IMUX.IMUX29
CKINT0	input	TCELL4:IMUX.IMUX23
CKINT1	input	TCELL4:IMUX.IMUX31
I0MUX	output	TCELL7:TEST3
I1MUX	output	TCELL7:TEST2
IGNORE0	input	TCELL4:IMUX.IMUX22
IGNORE1	input	TCELL4:IMUX.IMUX30
S0	input	TCELL4:IMUX.IMUX20
S1	input	TCELL4:IMUX.IMUX28

Bel BUFGCTRL16

virtex4 CFG bel BUFGCTRL16
Pin	Direction	Wires
CE0	input	TCELL14:IMUX.IMUX21
CE1	input	TCELL14:IMUX.IMUX29
CKINT0	input	TCELL14:IMUX.IMUX23
CKINT1	input	TCELL14:IMUX.IMUX31
I0MUX	output	TCELL15:TEST3
I1MUX	output	TCELL15:TEST2
IGNORE0	input	TCELL14:IMUX.IMUX22
IGNORE1	input	TCELL14:IMUX.IMUX30
S0	input	TCELL14:IMUX.IMUX20
S1	input	TCELL14:IMUX.IMUX28

Bel BUFGCTRL17

virtex4 CFG bel BUFGCTRL17
Pin	Direction	Wires
CE0	input	TCELL14:IMUX.IMUX17
CE1	input	TCELL14:IMUX.IMUX25
CKINT0	input	TCELL14:IMUX.IMUX19
CKINT1	input	TCELL14:IMUX.IMUX27
I0MUX	output	TCELL15:TEST1
I1MUX	output	TCELL15:TEST0
IGNORE0	input	TCELL14:IMUX.IMUX18
IGNORE1	input	TCELL14:IMUX.IMUX26
S0	input	TCELL14:IMUX.IMUX16
S1	input	TCELL14:IMUX.IMUX24

Bel BUFGCTRL18

virtex4 CFG bel BUFGCTRL18
Pin	Direction	Wires
CE0	input	TCELL14:IMUX.IMUX5
CE1	input	TCELL14:IMUX.IMUX13
CKINT0	input	TCELL14:IMUX.IMUX7
CKINT1	input	TCELL14:IMUX.IMUX15
I0MUX	output	TCELL14:TEST3
I1MUX	output	TCELL14:TEST2
IGNORE0	input	TCELL14:IMUX.IMUX6
IGNORE1	input	TCELL14:IMUX.IMUX14
S0	input	TCELL14:IMUX.IMUX4
S1	input	TCELL14:IMUX.IMUX12

Bel BUFGCTRL19

virtex4 CFG bel BUFGCTRL19
Pin	Direction	Wires
CE0	input	TCELL14:IMUX.IMUX1
CE1	input	TCELL14:IMUX.IMUX9
CKINT0	input	TCELL14:IMUX.IMUX3
CKINT1	input	TCELL14:IMUX.IMUX11
I0MUX	output	TCELL14:TEST1
I1MUX	output	TCELL14:TEST0
IGNORE0	input	TCELL14:IMUX.IMUX2
IGNORE1	input	TCELL14:IMUX.IMUX10
S0	input	TCELL14:IMUX.IMUX0
S1	input	TCELL14:IMUX.IMUX8

Bel BUFGCTRL20

virtex4 CFG bel BUFGCTRL20
Pin	Direction	Wires
CE0	input	TCELL13:IMUX.IMUX21
CE1	input	TCELL13:IMUX.IMUX29
CKINT0	input	TCELL13:IMUX.IMUX23
CKINT1	input	TCELL13:IMUX.IMUX31
I0MUX	output	TCELL13:TEST3
I1MUX	output	TCELL13:TEST2
IGNORE0	input	TCELL13:IMUX.IMUX22
IGNORE1	input	TCELL13:IMUX.IMUX30
S0	input	TCELL13:IMUX.IMUX20
S1	input	TCELL13:IMUX.IMUX28

Bel BUFGCTRL21

virtex4 CFG bel BUFGCTRL21
Pin	Direction	Wires
CE0	input	TCELL13:IMUX.IMUX17
CE1	input	TCELL13:IMUX.IMUX25
CKINT0	input	TCELL13:IMUX.IMUX19
CKINT1	input	TCELL13:IMUX.IMUX27
I0MUX	output	TCELL13:TEST1
I1MUX	output	TCELL13:TEST0
IGNORE0	input	TCELL13:IMUX.IMUX18
IGNORE1	input	TCELL13:IMUX.IMUX26
S0	input	TCELL13:IMUX.IMUX16
S1	input	TCELL13:IMUX.IMUX24

Bel BUFGCTRL22

virtex4 CFG bel BUFGCTRL22
Pin	Direction	Wires
CE0	input	TCELL13:IMUX.IMUX5
CE1	input	TCELL13:IMUX.IMUX13
CKINT0	input	TCELL13:IMUX.IMUX7
CKINT1	input	TCELL13:IMUX.IMUX15
I0MUX	output	TCELL12:TEST3
I1MUX	output	TCELL12:TEST2
IGNORE0	input	TCELL13:IMUX.IMUX6
IGNORE1	input	TCELL13:IMUX.IMUX14
S0	input	TCELL13:IMUX.IMUX4
S1	input	TCELL13:IMUX.IMUX12

Bel BUFGCTRL23

virtex4 CFG bel BUFGCTRL23
Pin	Direction	Wires
CE0	input	TCELL13:IMUX.IMUX1
CE1	input	TCELL13:IMUX.IMUX9
CKINT0	input	TCELL13:IMUX.IMUX3
CKINT1	input	TCELL13:IMUX.IMUX11
I0MUX	output	TCELL12:TEST1
I1MUX	output	TCELL12:TEST0
IGNORE0	input	TCELL13:IMUX.IMUX2
IGNORE1	input	TCELL13:IMUX.IMUX10
S0	input	TCELL13:IMUX.IMUX0
S1	input	TCELL13:IMUX.IMUX8

Bel BUFGCTRL24

virtex4 CFG bel BUFGCTRL24
Pin	Direction	Wires
CE0	input	TCELL12:IMUX.IMUX21
CE1	input	TCELL12:IMUX.IMUX29
CKINT0	input	TCELL12:IMUX.IMUX23
CKINT1	input	TCELL12:IMUX.IMUX31
I0MUX	output	TCELL11:TEST3
I1MUX	output	TCELL11:TEST2
IGNORE0	input	TCELL12:IMUX.IMUX22
IGNORE1	input	TCELL12:IMUX.IMUX30
S0	input	TCELL12:IMUX.IMUX20
S1	input	TCELL12:IMUX.IMUX28

Bel BUFGCTRL25

virtex4 CFG bel BUFGCTRL25
Pin	Direction	Wires
CE0	input	TCELL12:IMUX.IMUX17
CE1	input	TCELL12:IMUX.IMUX25
CKINT0	input	TCELL12:IMUX.IMUX19
CKINT1	input	TCELL12:IMUX.IMUX27
I0MUX	output	TCELL11:TEST1
I1MUX	output	TCELL11:TEST0
IGNORE0	input	TCELL12:IMUX.IMUX18
IGNORE1	input	TCELL12:IMUX.IMUX26
S0	input	TCELL12:IMUX.IMUX16
S1	input	TCELL12:IMUX.IMUX24

Bel BUFGCTRL26

virtex4 CFG bel BUFGCTRL26
Pin	Direction	Wires
CE0	input	TCELL12:IMUX.IMUX5
CE1	input	TCELL12:IMUX.IMUX13
CKINT0	input	TCELL12:IMUX.IMUX7
CKINT1	input	TCELL12:IMUX.IMUX15
I0MUX	output	TCELL10:TEST3
I1MUX	output	TCELL10:TEST2
IGNORE0	input	TCELL12:IMUX.IMUX6
IGNORE1	input	TCELL12:IMUX.IMUX14
S0	input	TCELL12:IMUX.IMUX4
S1	input	TCELL12:IMUX.IMUX12

Bel BUFGCTRL27

virtex4 CFG bel BUFGCTRL27
Pin	Direction	Wires
CE0	input	TCELL12:IMUX.IMUX1
CE1	input	TCELL12:IMUX.IMUX9
CKINT0	input	TCELL12:IMUX.IMUX3
CKINT1	input	TCELL12:IMUX.IMUX11
I0MUX	output	TCELL10:TEST1
I1MUX	output	TCELL10:TEST0
IGNORE0	input	TCELL12:IMUX.IMUX2
IGNORE1	input	TCELL12:IMUX.IMUX10
S0	input	TCELL12:IMUX.IMUX0
S1	input	TCELL12:IMUX.IMUX8

Bel BUFGCTRL28

virtex4 CFG bel BUFGCTRL28
Pin	Direction	Wires
CE0	input	TCELL11:IMUX.IMUX21
CE1	input	TCELL11:IMUX.IMUX29
CKINT0	input	TCELL11:IMUX.IMUX23
CKINT1	input	TCELL11:IMUX.IMUX31
I0MUX	output	TCELL9:TEST3
I1MUX	output	TCELL9:TEST2
IGNORE0	input	TCELL11:IMUX.IMUX22
IGNORE1	input	TCELL11:IMUX.IMUX30
S0	input	TCELL11:IMUX.IMUX20
S1	input	TCELL11:IMUX.IMUX28

Bel BUFGCTRL29

virtex4 CFG bel BUFGCTRL29
Pin	Direction	Wires
CE0	input	TCELL11:IMUX.IMUX17
CE1	input	TCELL11:IMUX.IMUX25
CKINT0	input	TCELL11:IMUX.IMUX19
CKINT1	input	TCELL11:IMUX.IMUX27
I0MUX	output	TCELL9:TEST1
I1MUX	output	TCELL9:TEST0
IGNORE0	input	TCELL11:IMUX.IMUX18
IGNORE1	input	TCELL11:IMUX.IMUX26
S0	input	TCELL11:IMUX.IMUX16
S1	input	TCELL11:IMUX.IMUX24

Bel BUFGCTRL30

virtex4 CFG bel BUFGCTRL30
Pin	Direction	Wires
CE0	input	TCELL11:IMUX.IMUX5
CE1	input	TCELL11:IMUX.IMUX13
CKINT0	input	TCELL11:IMUX.IMUX7
CKINT1	input	TCELL11:IMUX.IMUX15
I0MUX	output	TCELL8:TEST3
I1MUX	output	TCELL8:TEST2
IGNORE0	input	TCELL11:IMUX.IMUX6
IGNORE1	input	TCELL11:IMUX.IMUX14
S0	input	TCELL11:IMUX.IMUX4
S1	input	TCELL11:IMUX.IMUX12

Bel BUFGCTRL31

virtex4 CFG bel BUFGCTRL31
Pin	Direction	Wires
CE0	input	TCELL11:IMUX.IMUX1
CE1	input	TCELL11:IMUX.IMUX9
CKINT0	input	TCELL11:IMUX.IMUX3
CKINT1	input	TCELL11:IMUX.IMUX11
I0MUX	output	TCELL8:TEST1
I1MUX	output	TCELL8:TEST0
IGNORE0	input	TCELL11:IMUX.IMUX2
IGNORE1	input	TCELL11:IMUX.IMUX10
S0	input	TCELL11:IMUX.IMUX0
S1	input	TCELL11:IMUX.IMUX8

Bel BUFG_MGTCLK_S

virtex4 CFG bel BUFG_MGTCLK_S
Pin	Direction	Wires

Bel BUFG_MGTCLK_N

virtex4 CFG bel BUFG_MGTCLK_N
Pin	Direction	Wires

Bel BUFG_MGTCLK_S_HROW

virtex4 CFG bel BUFG_MGTCLK_S_HROW
Pin	Direction	Wires

Bel BUFG_MGTCLK_N_HROW

virtex4 CFG bel BUFG_MGTCLK_N_HROW
Pin	Direction	Wires

Bel BUFG_MGTCLK_S_HCLK

virtex4 CFG bel BUFG_MGTCLK_S_HCLK
Pin	Direction	Wires

Bel BUFG_MGTCLK_N_HCLK

virtex4 CFG bel BUFG_MGTCLK_N_HCLK
Pin	Direction	Wires

Bel BSCAN0

virtex4 CFG bel BSCAN0
Pin	Direction	Wires
CAPTURE	output	TCELL0:OUT.BEST6.TMIN
DRCK	output	TCELL0:OUT.BEST5.TMIN
RESET	output	TCELL0:OUT.BEST2.TMIN
SEL	output	TCELL0:OUT.BEST0.TMIN
SHIFT	output	TCELL0:OUT.BEST4.TMIN
TDI	output	TCELL0:OUT.BEST3.TMIN
TDO	input	TCELL0:IMUX.IMUX0
UPDATE	output	TCELL0:OUT.BEST1.TMIN

Bel BSCAN1

virtex4 CFG bel BSCAN1
Pin	Direction	Wires
CAPTURE	output	TCELL5:OUT.BEST6.TMIN
DRCK	output	TCELL5:OUT.BEST5.TMIN
RESET	output	TCELL5:OUT.BEST2.TMIN
SEL	output	TCELL5:OUT.BEST0.TMIN
SHIFT	output	TCELL5:OUT.BEST4.TMIN
TDI	output	TCELL5:OUT.BEST3.TMIN
TDO	input	TCELL5:IMUX.IMUX0
UPDATE	output	TCELL5:OUT.BEST1.TMIN

Bel BSCAN2

virtex4 CFG bel BSCAN2
Pin	Direction	Wires
CAPTURE	output	TCELL10:OUT.BEST6.TMIN
DRCK	output	TCELL10:OUT.BEST5.TMIN
RESET	output	TCELL10:OUT.BEST2.TMIN
SEL	output	TCELL10:OUT.BEST0.TMIN
SHIFT	output	TCELL10:OUT.BEST4.TMIN
TDI	output	TCELL10:OUT.BEST3.TMIN
TDO	input	TCELL10:IMUX.IMUX0
UPDATE	output	TCELL10:OUT.BEST1.TMIN

Bel BSCAN3

virtex4 CFG bel BSCAN3
Pin	Direction	Wires
CAPTURE	output	TCELL15:OUT.BEST6.TMIN
DRCK	output	TCELL15:OUT.BEST5.TMIN
RESET	output	TCELL15:OUT.BEST2.TMIN
SEL	output	TCELL15:OUT.BEST0.TMIN
SHIFT	output	TCELL15:OUT.BEST4.TMIN
TDI	output	TCELL15:OUT.BEST3.TMIN
TDO	input	TCELL15:IMUX.IMUX0
UPDATE	output	TCELL15:OUT.BEST1.TMIN

Bel ICAP0

virtex4 CFG bel ICAP0
Pin	Direction	Wires
BUSY	output	TCELL7:OUT.BEST0.TMIN
CE	input	TCELL5:IMUX.CE1
CLK	input	TCELL5:IMUX.CLK0
I0	input	TCELL6:IMUX.IMUX0
I1	input	TCELL6:IMUX.IMUX1
I10	input	TCELL6:IMUX.IMUX10
I11	input	TCELL6:IMUX.IMUX11
I12	input	TCELL6:IMUX.IMUX12
I13	input	TCELL6:IMUX.IMUX13
I14	input	TCELL6:IMUX.IMUX14
I15	input	TCELL6:IMUX.IMUX15
I16	input	TCELL7:IMUX.IMUX0
I17	input	TCELL7:IMUX.IMUX1
I18	input	TCELL7:IMUX.IMUX2
I19	input	TCELL7:IMUX.IMUX3
I2	input	TCELL6:IMUX.IMUX2
I20	input	TCELL7:IMUX.IMUX4
I21	input	TCELL7:IMUX.IMUX5
I22	input	TCELL7:IMUX.IMUX6
I23	input	TCELL7:IMUX.IMUX7
I24	input	TCELL7:IMUX.IMUX8
I25	input	TCELL7:IMUX.IMUX9
I26	input	TCELL7:IMUX.IMUX10
I27	input	TCELL7:IMUX.IMUX11
I28	input	TCELL7:IMUX.IMUX12
I29	input	TCELL7:IMUX.IMUX13
I3	input	TCELL6:IMUX.IMUX3
I30	input	TCELL7:IMUX.IMUX14
I31	input	TCELL7:IMUX.IMUX15
I4	input	TCELL6:IMUX.IMUX4
I5	input	TCELL6:IMUX.IMUX5
I6	input	TCELL6:IMUX.IMUX6
I7	input	TCELL6:IMUX.IMUX7
I8	input	TCELL6:IMUX.IMUX8
I9	input	TCELL6:IMUX.IMUX9
O0	output	TCELL1:OUT.BEST0.TMIN
O1	output	TCELL1:OUT.BEST1.TMIN
O10	output	TCELL2:OUT.BEST2.TMIN
O11	output	TCELL2:OUT.BEST3.TMIN
O12	output	TCELL2:OUT.BEST4.TMIN
O13	output	TCELL2:OUT.BEST5.TMIN
O14	output	TCELL2:OUT.BEST6.TMIN
O15	output	TCELL2:OUT.BEST7.TMIN
O16	output	TCELL3:OUT.BEST0.TMIN
O17	output	TCELL3:OUT.BEST1.TMIN
O18	output	TCELL3:OUT.BEST2.TMIN
O19	output	TCELL3:OUT.BEST3.TMIN
O2	output	TCELL1:OUT.BEST2.TMIN
O20	output	TCELL3:OUT.BEST4.TMIN
O21	output	TCELL3:OUT.BEST5.TMIN
O22	output	TCELL3:OUT.BEST6.TMIN
O23	output	TCELL3:OUT.BEST7.TMIN
O24	output	TCELL4:OUT.BEST0.TMIN
O25	output	TCELL4:OUT.BEST1.TMIN
O26	output	TCELL4:OUT.BEST2.TMIN
O27	output	TCELL4:OUT.BEST3.TMIN
O28	output	TCELL4:OUT.BEST4.TMIN
O29	output	TCELL4:OUT.BEST5.TMIN
O3	output	TCELL1:OUT.BEST3.TMIN
O30	output	TCELL4:OUT.BEST6.TMIN
O31	output	TCELL4:OUT.BEST7.TMIN
O4	output	TCELL1:OUT.BEST4.TMIN
O5	output	TCELL1:OUT.BEST5.TMIN
O6	output	TCELL1:OUT.BEST6.TMIN
O7	output	TCELL1:OUT.BEST7.TMIN
O8	output	TCELL2:OUT.BEST0.TMIN
O9	output	TCELL2:OUT.BEST1.TMIN
WRITE	input	TCELL5:IMUX.CE0

Bel ICAP1

virtex4 CFG bel ICAP1
Pin	Direction	Wires
BUSY	output	TCELL8:OUT.BEST0.TMIN
CE	input	TCELL10:IMUX.CE1
CLK	input	TCELL10:IMUX.CLK0
I0	input	TCELL9:IMUX.IMUX0
I1	input	TCELL9:IMUX.IMUX1
I10	input	TCELL9:IMUX.IMUX10
I11	input	TCELL9:IMUX.IMUX11
I12	input	TCELL9:IMUX.IMUX12
I13	input	TCELL9:IMUX.IMUX13
I14	input	TCELL9:IMUX.IMUX14
I15	input	TCELL9:IMUX.IMUX15
I16	input	TCELL8:IMUX.IMUX0
I17	input	TCELL8:IMUX.IMUX1
I18	input	TCELL8:IMUX.IMUX2
I19	input	TCELL8:IMUX.IMUX3
I2	input	TCELL9:IMUX.IMUX2
I20	input	TCELL8:IMUX.IMUX4
I21	input	TCELL8:IMUX.IMUX5
I22	input	TCELL8:IMUX.IMUX6
I23	input	TCELL8:IMUX.IMUX7
I24	input	TCELL8:IMUX.IMUX8
I25	input	TCELL8:IMUX.IMUX9
I26	input	TCELL8:IMUX.IMUX10
I27	input	TCELL8:IMUX.IMUX11
I28	input	TCELL8:IMUX.IMUX12
I29	input	TCELL8:IMUX.IMUX13
I3	input	TCELL9:IMUX.IMUX3
I30	input	TCELL8:IMUX.IMUX14
I31	input	TCELL8:IMUX.IMUX15
I4	input	TCELL9:IMUX.IMUX4
I5	input	TCELL9:IMUX.IMUX5
I6	input	TCELL9:IMUX.IMUX6
I7	input	TCELL9:IMUX.IMUX7
I8	input	TCELL9:IMUX.IMUX8
I9	input	TCELL9:IMUX.IMUX9
O0	output	TCELL14:OUT.BEST0.TMIN
O1	output	TCELL14:OUT.BEST1.TMIN
O10	output	TCELL13:OUT.BEST2.TMIN
O11	output	TCELL13:OUT.BEST3.TMIN
O12	output	TCELL13:OUT.BEST4.TMIN
O13	output	TCELL13:OUT.BEST5.TMIN
O14	output	TCELL13:OUT.BEST6.TMIN
O15	output	TCELL13:OUT.BEST7.TMIN
O16	output	TCELL12:OUT.BEST0.TMIN
O17	output	TCELL12:OUT.BEST1.TMIN
O18	output	TCELL12:OUT.BEST2.TMIN
O19	output	TCELL12:OUT.BEST3.TMIN
O2	output	TCELL14:OUT.BEST2.TMIN
O20	output	TCELL12:OUT.BEST4.TMIN
O21	output	TCELL12:OUT.BEST5.TMIN
O22	output	TCELL12:OUT.BEST6.TMIN
O23	output	TCELL12:OUT.BEST7.TMIN
O24	output	TCELL11:OUT.BEST0.TMIN
O25	output	TCELL11:OUT.BEST1.TMIN
O26	output	TCELL11:OUT.BEST2.TMIN
O27	output	TCELL11:OUT.BEST3.TMIN
O28	output	TCELL11:OUT.BEST4.TMIN
O29	output	TCELL11:OUT.BEST5.TMIN
O3	output	TCELL14:OUT.BEST3.TMIN
O30	output	TCELL11:OUT.BEST6.TMIN
O31	output	TCELL11:OUT.BEST7.TMIN
O4	output	TCELL14:OUT.BEST4.TMIN
O5	output	TCELL14:OUT.BEST5.TMIN
O6	output	TCELL14:OUT.BEST6.TMIN
O7	output	TCELL14:OUT.BEST7.TMIN
O8	output	TCELL13:OUT.BEST0.TMIN
O9	output	TCELL13:OUT.BEST1.TMIN
WRITE	input	TCELL10:IMUX.CE0

Bel STARTUP

virtex4 CFG bel STARTUP
Pin	Direction	Wires
CLK	input	TCELL0:IMUX.CLK0
EOS	output	TCELL0:OUT.BEST7.TMIN
GSR	input	TCELL0:IMUX.SR0
GTS	input	TCELL0:IMUX.CE0
USRCCLKO	input	TCELL5:IMUX.CLK1
USRCCLKTS	input	TCELL5:IMUX.SR2
USRDONEO	input	TCELL5:IMUX.SR1
USRDONETS	input	TCELL5:IMUX.SR0

Bel CAPTURE

virtex4 CFG bel CAPTURE
Pin	Direction	Wires
CAP	input	TCELL5:IMUX.CE2
CLK	input	TCELL10:IMUX.CE2

Bel JTAGPPC

virtex4 CFG bel JTAGPPC
Pin	Direction	Wires
TCK	output	TCELL6:OUT.BEST0.TMIN
TDIPPC	output	TCELL6:OUT.BEST2.TMIN
TDOPPC	input	TCELL0:IMUX.IMUX1
TMS	output	TCELL6:OUT.BEST1.TMIN

Bel PMV0

virtex4 CFG bel PMV0
Pin	Direction	Wires
A0	input	TCELL0:IMUX.IMUX3
A1	input	TCELL0:IMUX.IMUX4
A2	input	TCELL0:IMUX.IMUX5
A3	input	TCELL0:IMUX.IMUX6
A4	input	TCELL0:IMUX.IMUX7
A5	input	TCELL0:IMUX.IMUX8
EN	input	TCELL0:IMUX.IMUX2
O	output	TCELL3:OUT.SEC0.TMIN
ODIV2	output	TCELL3:OUT.SEC1.TMIN
ODIV4	output	TCELL3:OUT.SEC2.TMIN

Bel DCIRESET

virtex4 CFG bel DCIRESET
Pin	Direction	Wires
LOCKED	output	TCELL10:OUT.BEST7.TMIN
RST	input	TCELL10:IMUX.IMUX1

Bel FRAME_ECC

virtex4 CFG bel FRAME_ECC
Pin	Direction	Wires
ERROR	output	TCELL8:OUT.BEST1.TMIN
SYNDROME0	output	TCELL7:OUT.BEST1.TMIN
SYNDROME1	output	TCELL7:OUT.BEST2.TMIN
SYNDROME10	output	TCELL8:OUT.BEST6.TMIN
SYNDROME11	output	TCELL8:OUT.BEST7.TMIN
SYNDROME2	output	TCELL7:OUT.BEST3.TMIN
SYNDROME3	output	TCELL7:OUT.BEST4.TMIN
SYNDROME4	output	TCELL7:OUT.BEST5.TMIN
SYNDROME5	output	TCELL7:OUT.BEST6.TMIN
SYNDROME6	output	TCELL8:OUT.BEST2.TMIN
SYNDROME7	output	TCELL8:OUT.BEST3.TMIN
SYNDROME8	output	TCELL8:OUT.BEST4.TMIN
SYNDROME9	output	TCELL8:OUT.BEST5.TMIN
SYNDROMEVALID	output	TCELL7:OUT.BEST7.TMIN

Bel USR_ACCESS

virtex4 CFG bel USR_ACCESS
Pin	Direction	Wires
DATA0	output	TCELL14:OUT.SEC0.TMIN
DATA1	output	TCELL14:OUT.SEC1.TMIN
DATA10	output	TCELL13:OUT.SEC2.TMIN
DATA11	output	TCELL13:OUT.SEC3.TMIN
DATA12	output	TCELL13:OUT.SEC4.TMIN
DATA13	output	TCELL13:OUT.SEC5.TMIN
DATA14	output	TCELL13:OUT.SEC6.TMIN
DATA15	output	TCELL13:OUT.SEC7.TMIN
DATA16	output	TCELL12:OUT.SEC0.TMIN
DATA17	output	TCELL12:OUT.SEC1.TMIN
DATA18	output	TCELL12:OUT.SEC2.TMIN
DATA19	output	TCELL12:OUT.SEC3.TMIN
DATA2	output	TCELL14:OUT.SEC2.TMIN
DATA20	output	TCELL12:OUT.SEC4.TMIN
DATA21	output	TCELL12:OUT.SEC5.TMIN
DATA22	output	TCELL12:OUT.SEC6.TMIN
DATA23	output	TCELL12:OUT.SEC7.TMIN
DATA24	output	TCELL11:OUT.SEC0.TMIN
DATA25	output	TCELL11:OUT.SEC1.TMIN
DATA26	output	TCELL11:OUT.SEC2.TMIN
DATA27	output	TCELL11:OUT.SEC3.TMIN
DATA28	output	TCELL11:OUT.SEC4.TMIN
DATA29	output	TCELL11:OUT.SEC5.TMIN
DATA3	output	TCELL14:OUT.SEC3.TMIN
DATA30	output	TCELL11:OUT.SEC6.TMIN
DATA31	output	TCELL11:OUT.SEC7.TMIN
DATA4	output	TCELL14:OUT.SEC4.TMIN
DATA5	output	TCELL14:OUT.SEC5.TMIN
DATA6	output	TCELL14:OUT.SEC6.TMIN
DATA7	output	TCELL14:OUT.SEC7.TMIN
DATA8	output	TCELL13:OUT.SEC0.TMIN
DATA9	output	TCELL13:OUT.SEC1.TMIN
DATAVALID	output	TCELL15:OUT.SEC0.TMIN

Bel wires

virtex4 CFG bel wires
Wire	Pins
TCELL0:IMUX.SR0	STARTUP.GSR
TCELL0:IMUX.CLK0	STARTUP.CLK
TCELL0:IMUX.CE0	STARTUP.GTS
TCELL0:IMUX.IMUX0	BSCAN0.TDO
TCELL0:IMUX.IMUX1	JTAGPPC.TDOPPC
TCELL0:IMUX.IMUX2	PMV0.EN
TCELL0:IMUX.IMUX3	PMV0.A0
TCELL0:IMUX.IMUX4	PMV0.A1
TCELL0:IMUX.IMUX5	PMV0.A2
TCELL0:IMUX.IMUX6	PMV0.A3
TCELL0:IMUX.IMUX7	PMV0.A4
TCELL0:IMUX.IMUX8	PMV0.A5
TCELL0:OUT.BEST0.TMIN	BSCAN0.SEL
TCELL0:OUT.BEST1.TMIN	BSCAN0.UPDATE
TCELL0:OUT.BEST2.TMIN	BSCAN0.RESET
TCELL0:OUT.BEST3.TMIN	BSCAN0.TDI
TCELL0:OUT.BEST4.TMIN	BSCAN0.SHIFT
TCELL0:OUT.BEST5.TMIN	BSCAN0.DRCK
TCELL0:OUT.BEST6.TMIN	BSCAN0.CAPTURE
TCELL0:OUT.BEST7.TMIN	STARTUP.EOS
TCELL0:TEST0	BUFGCTRL0.I1MUX
TCELL0:TEST1	BUFGCTRL0.I0MUX
TCELL0:TEST2	BUFGCTRL1.I1MUX
TCELL0:TEST3	BUFGCTRL1.I0MUX
TCELL1:IMUX.IMUX0	BUFGCTRL0.S0
TCELL1:IMUX.IMUX1	BUFGCTRL0.CE0
TCELL1:IMUX.IMUX2	BUFGCTRL0.IGNORE0
TCELL1:IMUX.IMUX3	BUFGCTRL0.CKINT0
TCELL1:IMUX.IMUX4	BUFGCTRL1.S0
TCELL1:IMUX.IMUX5	BUFGCTRL1.CE0
TCELL1:IMUX.IMUX6	BUFGCTRL1.IGNORE0
TCELL1:IMUX.IMUX7	BUFGCTRL1.CKINT0
TCELL1:IMUX.IMUX8	BUFGCTRL0.S1
TCELL1:IMUX.IMUX9	BUFGCTRL0.CE1
TCELL1:IMUX.IMUX10	BUFGCTRL0.IGNORE1
TCELL1:IMUX.IMUX11	BUFGCTRL0.CKINT1
TCELL1:IMUX.IMUX12	BUFGCTRL1.S1
TCELL1:IMUX.IMUX13	BUFGCTRL1.CE1
TCELL1:IMUX.IMUX14	BUFGCTRL1.IGNORE1
TCELL1:IMUX.IMUX15	BUFGCTRL1.CKINT1
TCELL1:IMUX.IMUX16	BUFGCTRL2.S0
TCELL1:IMUX.IMUX17	BUFGCTRL2.CE0
TCELL1:IMUX.IMUX18	BUFGCTRL2.IGNORE0
TCELL1:IMUX.IMUX19	BUFGCTRL2.CKINT0
TCELL1:IMUX.IMUX20	BUFGCTRL3.S0
TCELL1:IMUX.IMUX21	BUFGCTRL3.CE0
TCELL1:IMUX.IMUX22	BUFGCTRL3.IGNORE0
TCELL1:IMUX.IMUX23	BUFGCTRL3.CKINT0
TCELL1:IMUX.IMUX24	BUFGCTRL2.S1
TCELL1:IMUX.IMUX25	BUFGCTRL2.CE1
TCELL1:IMUX.IMUX26	BUFGCTRL2.IGNORE1
TCELL1:IMUX.IMUX27	BUFGCTRL2.CKINT1
TCELL1:IMUX.IMUX28	BUFGCTRL3.S1
TCELL1:IMUX.IMUX29	BUFGCTRL3.CE1
TCELL1:IMUX.IMUX30	BUFGCTRL3.IGNORE1
TCELL1:IMUX.IMUX31	BUFGCTRL3.CKINT1
TCELL1:OUT.BEST0.TMIN	ICAP0.O0
TCELL1:OUT.BEST1.TMIN	ICAP0.O1
TCELL1:OUT.BEST2.TMIN	ICAP0.O2
TCELL1:OUT.BEST3.TMIN	ICAP0.O3
TCELL1:OUT.BEST4.TMIN	ICAP0.O4
TCELL1:OUT.BEST5.TMIN	ICAP0.O5
TCELL1:OUT.BEST6.TMIN	ICAP0.O6
TCELL1:OUT.BEST7.TMIN	ICAP0.O7
TCELL1:TEST0	BUFGCTRL2.I1MUX
TCELL1:TEST1	BUFGCTRL2.I0MUX
TCELL1:TEST2	BUFGCTRL3.I1MUX
TCELL1:TEST3	BUFGCTRL3.I0MUX
TCELL2:IMUX.IMUX0	BUFGCTRL4.S0
TCELL2:IMUX.IMUX1	BUFGCTRL4.CE0
TCELL2:IMUX.IMUX2	BUFGCTRL4.IGNORE0
TCELL2:IMUX.IMUX3	BUFGCTRL4.CKINT0
TCELL2:IMUX.IMUX4	BUFGCTRL5.S0
TCELL2:IMUX.IMUX5	BUFGCTRL5.CE0
TCELL2:IMUX.IMUX6	BUFGCTRL5.IGNORE0
TCELL2:IMUX.IMUX7	BUFGCTRL5.CKINT0
TCELL2:IMUX.IMUX8	BUFGCTRL4.S1
TCELL2:IMUX.IMUX9	BUFGCTRL4.CE1
TCELL2:IMUX.IMUX10	BUFGCTRL4.IGNORE1
TCELL2:IMUX.IMUX11	BUFGCTRL4.CKINT1
TCELL2:IMUX.IMUX12	BUFGCTRL5.S1
TCELL2:IMUX.IMUX13	BUFGCTRL5.CE1
TCELL2:IMUX.IMUX14	BUFGCTRL5.IGNORE1
TCELL2:IMUX.IMUX15	BUFGCTRL5.CKINT1
TCELL2:IMUX.IMUX16	BUFGCTRL6.S0
TCELL2:IMUX.IMUX17	BUFGCTRL6.CE0
TCELL2:IMUX.IMUX18	BUFGCTRL6.IGNORE0
TCELL2:IMUX.IMUX19	BUFGCTRL6.CKINT0
TCELL2:IMUX.IMUX20	BUFGCTRL7.S0
TCELL2:IMUX.IMUX21	BUFGCTRL7.CE0
TCELL2:IMUX.IMUX22	BUFGCTRL7.IGNORE0
TCELL2:IMUX.IMUX23	BUFGCTRL7.CKINT0
TCELL2:IMUX.IMUX24	BUFGCTRL6.S1
TCELL2:IMUX.IMUX25	BUFGCTRL6.CE1
TCELL2:IMUX.IMUX26	BUFGCTRL6.IGNORE1
TCELL2:IMUX.IMUX27	BUFGCTRL6.CKINT1
TCELL2:IMUX.IMUX28	BUFGCTRL7.S1
TCELL2:IMUX.IMUX29	BUFGCTRL7.CE1
TCELL2:IMUX.IMUX30	BUFGCTRL7.IGNORE1
TCELL2:IMUX.IMUX31	BUFGCTRL7.CKINT1
TCELL2:OUT.BEST0.TMIN	ICAP0.O8
TCELL2:OUT.BEST1.TMIN	ICAP0.O9
TCELL2:OUT.BEST2.TMIN	ICAP0.O10
TCELL2:OUT.BEST3.TMIN	ICAP0.O11
TCELL2:OUT.BEST4.TMIN	ICAP0.O12
TCELL2:OUT.BEST5.TMIN	ICAP0.O13
TCELL2:OUT.BEST6.TMIN	ICAP0.O14
TCELL2:OUT.BEST7.TMIN	ICAP0.O15
TCELL2:TEST0	BUFGCTRL4.I1MUX
TCELL2:TEST1	BUFGCTRL4.I0MUX
TCELL2:TEST2	BUFGCTRL5.I1MUX
TCELL2:TEST3	BUFGCTRL5.I0MUX
TCELL3:IMUX.IMUX0	BUFGCTRL8.S0
TCELL3:IMUX.IMUX1	BUFGCTRL8.CE0
TCELL3:IMUX.IMUX2	BUFGCTRL8.IGNORE0
TCELL3:IMUX.IMUX3	BUFGCTRL8.CKINT0
TCELL3:IMUX.IMUX4	BUFGCTRL9.S0
TCELL3:IMUX.IMUX5	BUFGCTRL9.CE0
TCELL3:IMUX.IMUX6	BUFGCTRL9.IGNORE0
TCELL3:IMUX.IMUX7	BUFGCTRL9.CKINT0
TCELL3:IMUX.IMUX8	BUFGCTRL8.S1
TCELL3:IMUX.IMUX9	BUFGCTRL8.CE1
TCELL3:IMUX.IMUX10	BUFGCTRL8.IGNORE1
TCELL3:IMUX.IMUX11	BUFGCTRL8.CKINT1
TCELL3:IMUX.IMUX12	BUFGCTRL9.S1
TCELL3:IMUX.IMUX13	BUFGCTRL9.CE1
TCELL3:IMUX.IMUX14	BUFGCTRL9.IGNORE1
TCELL3:IMUX.IMUX15	BUFGCTRL9.CKINT1
TCELL3:IMUX.IMUX16	BUFGCTRL10.S0
TCELL3:IMUX.IMUX17	BUFGCTRL10.CE0
TCELL3:IMUX.IMUX18	BUFGCTRL10.IGNORE0
TCELL3:IMUX.IMUX19	BUFGCTRL10.CKINT0
TCELL3:IMUX.IMUX20	BUFGCTRL11.S0
TCELL3:IMUX.IMUX21	BUFGCTRL11.CE0
TCELL3:IMUX.IMUX22	BUFGCTRL11.IGNORE0
TCELL3:IMUX.IMUX23	BUFGCTRL11.CKINT0
TCELL3:IMUX.IMUX24	BUFGCTRL10.S1
TCELL3:IMUX.IMUX25	BUFGCTRL10.CE1
TCELL3:IMUX.IMUX26	BUFGCTRL10.IGNORE1
TCELL3:IMUX.IMUX27	BUFGCTRL10.CKINT1
TCELL3:IMUX.IMUX28	BUFGCTRL11.S1
TCELL3:IMUX.IMUX29	BUFGCTRL11.CE1
TCELL3:IMUX.IMUX30	BUFGCTRL11.IGNORE1
TCELL3:IMUX.IMUX31	BUFGCTRL11.CKINT1
TCELL3:OUT.BEST0.TMIN	ICAP0.O16
TCELL3:OUT.BEST1.TMIN	ICAP0.O17
TCELL3:OUT.BEST2.TMIN	ICAP0.O18
TCELL3:OUT.BEST3.TMIN	ICAP0.O19
TCELL3:OUT.BEST4.TMIN	ICAP0.O20
TCELL3:OUT.BEST5.TMIN	ICAP0.O21
TCELL3:OUT.BEST6.TMIN	ICAP0.O22
TCELL3:OUT.BEST7.TMIN	ICAP0.O23
TCELL3:OUT.SEC0.TMIN	PMV0.O
TCELL3:OUT.SEC1.TMIN	PMV0.ODIV2
TCELL3:OUT.SEC2.TMIN	PMV0.ODIV4
TCELL3:TEST0	BUFGCTRL6.I1MUX
TCELL3:TEST1	BUFGCTRL6.I0MUX
TCELL3:TEST2	BUFGCTRL7.I1MUX
TCELL3:TEST3	BUFGCTRL7.I0MUX
TCELL4:IMUX.IMUX0	BUFGCTRL12.S0
TCELL4:IMUX.IMUX1	BUFGCTRL12.CE0
TCELL4:IMUX.IMUX2	BUFGCTRL12.IGNORE0
TCELL4:IMUX.IMUX3	BUFGCTRL12.CKINT0
TCELL4:IMUX.IMUX4	BUFGCTRL13.S0
TCELL4:IMUX.IMUX5	BUFGCTRL13.CE0
TCELL4:IMUX.IMUX6	BUFGCTRL13.IGNORE0
TCELL4:IMUX.IMUX7	BUFGCTRL13.CKINT0
TCELL4:IMUX.IMUX8	BUFGCTRL12.S1
TCELL4:IMUX.IMUX9	BUFGCTRL12.CE1
TCELL4:IMUX.IMUX10	BUFGCTRL12.IGNORE1
TCELL4:IMUX.IMUX11	BUFGCTRL12.CKINT1
TCELL4:IMUX.IMUX12	BUFGCTRL13.S1
TCELL4:IMUX.IMUX13	BUFGCTRL13.CE1
TCELL4:IMUX.IMUX14	BUFGCTRL13.IGNORE1
TCELL4:IMUX.IMUX15	BUFGCTRL13.CKINT1
TCELL4:IMUX.IMUX16	BUFGCTRL14.S0
TCELL4:IMUX.IMUX17	BUFGCTRL14.CE0
TCELL4:IMUX.IMUX18	BUFGCTRL14.IGNORE0
TCELL4:IMUX.IMUX19	BUFGCTRL14.CKINT0
TCELL4:IMUX.IMUX20	BUFGCTRL15.S0
TCELL4:IMUX.IMUX21	BUFGCTRL15.CE0
TCELL4:IMUX.IMUX22	BUFGCTRL15.IGNORE0
TCELL4:IMUX.IMUX23	BUFGCTRL15.CKINT0
TCELL4:IMUX.IMUX24	BUFGCTRL14.S1
TCELL4:IMUX.IMUX25	BUFGCTRL14.CE1
TCELL4:IMUX.IMUX26	BUFGCTRL14.IGNORE1
TCELL4:IMUX.IMUX27	BUFGCTRL14.CKINT1
TCELL4:IMUX.IMUX28	BUFGCTRL15.S1
TCELL4:IMUX.IMUX29	BUFGCTRL15.CE1
TCELL4:IMUX.IMUX30	BUFGCTRL15.IGNORE1
TCELL4:IMUX.IMUX31	BUFGCTRL15.CKINT1
TCELL4:OUT.BEST0.TMIN	ICAP0.O24
TCELL4:OUT.BEST1.TMIN	ICAP0.O25
TCELL4:OUT.BEST2.TMIN	ICAP0.O26
TCELL4:OUT.BEST3.TMIN	ICAP0.O27
TCELL4:OUT.BEST4.TMIN	ICAP0.O28
TCELL4:OUT.BEST5.TMIN	ICAP0.O29
TCELL4:OUT.BEST6.TMIN	ICAP0.O30
TCELL4:OUT.BEST7.TMIN	ICAP0.O31
TCELL4:TEST0	BUFGCTRL8.I1MUX
TCELL4:TEST1	BUFGCTRL8.I0MUX
TCELL4:TEST2	BUFGCTRL9.I1MUX
TCELL4:TEST3	BUFGCTRL9.I0MUX
TCELL5:IMUX.SR0	STARTUP.USRDONETS
TCELL5:IMUX.SR1	STARTUP.USRDONEO
TCELL5:IMUX.SR2	STARTUP.USRCCLKTS
TCELL5:IMUX.CLK0	ICAP0.CLK
TCELL5:IMUX.CLK1	STARTUP.USRCCLKO
TCELL5:IMUX.CE0	ICAP0.WRITE
TCELL5:IMUX.CE1	ICAP0.CE
TCELL5:IMUX.CE2	CAPTURE.CAP
TCELL5:IMUX.IMUX0	BSCAN1.TDO
TCELL5:OUT.BEST0.TMIN	BSCAN1.SEL
TCELL5:OUT.BEST1.TMIN	BSCAN1.UPDATE
TCELL5:OUT.BEST2.TMIN	BSCAN1.RESET
TCELL5:OUT.BEST3.TMIN	BSCAN1.TDI
TCELL5:OUT.BEST4.TMIN	BSCAN1.SHIFT
TCELL5:OUT.BEST5.TMIN	BSCAN1.DRCK
TCELL5:OUT.BEST6.TMIN	BSCAN1.CAPTURE
TCELL5:TEST0	BUFGCTRL10.I1MUX
TCELL5:TEST1	BUFGCTRL10.I0MUX
TCELL5:TEST2	BUFGCTRL11.I1MUX
TCELL5:TEST3	BUFGCTRL11.I0MUX
TCELL6:IMUX.IMUX0	ICAP0.I0
TCELL6:IMUX.IMUX1	ICAP0.I1
TCELL6:IMUX.IMUX2	ICAP0.I2
TCELL6:IMUX.IMUX3	ICAP0.I3
TCELL6:IMUX.IMUX4	ICAP0.I4
TCELL6:IMUX.IMUX5	ICAP0.I5
TCELL6:IMUX.IMUX6	ICAP0.I6
TCELL6:IMUX.IMUX7	ICAP0.I7
TCELL6:IMUX.IMUX8	ICAP0.I8
TCELL6:IMUX.IMUX9	ICAP0.I9
TCELL6:IMUX.IMUX10	ICAP0.I10
TCELL6:IMUX.IMUX11	ICAP0.I11
TCELL6:IMUX.IMUX12	ICAP0.I12
TCELL6:IMUX.IMUX13	ICAP0.I13
TCELL6:IMUX.IMUX14	ICAP0.I14
TCELL6:IMUX.IMUX15	ICAP0.I15
TCELL6:OUT.BEST0.TMIN	JTAGPPC.TCK
TCELL6:OUT.BEST1.TMIN	JTAGPPC.TMS
TCELL6:OUT.BEST2.TMIN	JTAGPPC.TDIPPC
TCELL6:TEST0	BUFGCTRL12.I1MUX
TCELL6:TEST1	BUFGCTRL12.I0MUX
TCELL6:TEST2	BUFGCTRL13.I1MUX
TCELL6:TEST3	BUFGCTRL13.I0MUX
TCELL7:IMUX.IMUX0	ICAP0.I16
TCELL7:IMUX.IMUX1	ICAP0.I17
TCELL7:IMUX.IMUX2	ICAP0.I18
TCELL7:IMUX.IMUX3	ICAP0.I19
TCELL7:IMUX.IMUX4	ICAP0.I20
TCELL7:IMUX.IMUX5	ICAP0.I21
TCELL7:IMUX.IMUX6	ICAP0.I22
TCELL7:IMUX.IMUX7	ICAP0.I23
TCELL7:IMUX.IMUX8	ICAP0.I24
TCELL7:IMUX.IMUX9	ICAP0.I25
TCELL7:IMUX.IMUX10	ICAP0.I26
TCELL7:IMUX.IMUX11	ICAP0.I27
TCELL7:IMUX.IMUX12	ICAP0.I28
TCELL7:IMUX.IMUX13	ICAP0.I29
TCELL7:IMUX.IMUX14	ICAP0.I30
TCELL7:IMUX.IMUX15	ICAP0.I31
TCELL7:OUT.BEST0.TMIN	ICAP0.BUSY
TCELL7:OUT.BEST1.TMIN	FRAME_ECC.SYNDROME0
TCELL7:OUT.BEST2.TMIN	FRAME_ECC.SYNDROME1
TCELL7:OUT.BEST3.TMIN	FRAME_ECC.SYNDROME2
TCELL7:OUT.BEST4.TMIN	FRAME_ECC.SYNDROME3
TCELL7:OUT.BEST5.TMIN	FRAME_ECC.SYNDROME4
TCELL7:OUT.BEST6.TMIN	FRAME_ECC.SYNDROME5
TCELL7:OUT.BEST7.TMIN	FRAME_ECC.SYNDROMEVALID
TCELL7:TEST0	BUFGCTRL14.I1MUX
TCELL7:TEST1	BUFGCTRL14.I0MUX
TCELL7:TEST2	BUFGCTRL15.I1MUX
TCELL7:TEST3	BUFGCTRL15.I0MUX
TCELL8:IMUX.IMUX0	ICAP1.I16
TCELL8:IMUX.IMUX1	ICAP1.I17
TCELL8:IMUX.IMUX2	ICAP1.I18
TCELL8:IMUX.IMUX3	ICAP1.I19
TCELL8:IMUX.IMUX4	ICAP1.I20
TCELL8:IMUX.IMUX5	ICAP1.I21
TCELL8:IMUX.IMUX6	ICAP1.I22
TCELL8:IMUX.IMUX7	ICAP1.I23
TCELL8:IMUX.IMUX8	ICAP1.I24
TCELL8:IMUX.IMUX9	ICAP1.I25
TCELL8:IMUX.IMUX10	ICAP1.I26
TCELL8:IMUX.IMUX11	ICAP1.I27
TCELL8:IMUX.IMUX12	ICAP1.I28
TCELL8:IMUX.IMUX13	ICAP1.I29
TCELL8:IMUX.IMUX14	ICAP1.I30
TCELL8:IMUX.IMUX15	ICAP1.I31
TCELL8:OUT.BEST0.TMIN	ICAP1.BUSY
TCELL8:OUT.BEST1.TMIN	FRAME_ECC.ERROR
TCELL8:OUT.BEST2.TMIN	FRAME_ECC.SYNDROME6
TCELL8:OUT.BEST3.TMIN	FRAME_ECC.SYNDROME7
TCELL8:OUT.BEST4.TMIN	FRAME_ECC.SYNDROME8
TCELL8:OUT.BEST5.TMIN	FRAME_ECC.SYNDROME9
TCELL8:OUT.BEST6.TMIN	FRAME_ECC.SYNDROME10
TCELL8:OUT.BEST7.TMIN	FRAME_ECC.SYNDROME11
TCELL8:TEST0	BUFGCTRL31.I1MUX
TCELL8:TEST1	BUFGCTRL31.I0MUX
TCELL8:TEST2	BUFGCTRL30.I1MUX
TCELL8:TEST3	BUFGCTRL30.I0MUX
TCELL9:IMUX.IMUX0	ICAP1.I0
TCELL9:IMUX.IMUX1	ICAP1.I1
TCELL9:IMUX.IMUX2	ICAP1.I2
TCELL9:IMUX.IMUX3	ICAP1.I3
TCELL9:IMUX.IMUX4	ICAP1.I4
TCELL9:IMUX.IMUX5	ICAP1.I5
TCELL9:IMUX.IMUX6	ICAP1.I6
TCELL9:IMUX.IMUX7	ICAP1.I7
TCELL9:IMUX.IMUX8	ICAP1.I8
TCELL9:IMUX.IMUX9	ICAP1.I9
TCELL9:IMUX.IMUX10	ICAP1.I10
TCELL9:IMUX.IMUX11	ICAP1.I11
TCELL9:IMUX.IMUX12	ICAP1.I12
TCELL9:IMUX.IMUX13	ICAP1.I13
TCELL9:IMUX.IMUX14	ICAP1.I14
TCELL9:IMUX.IMUX15	ICAP1.I15
TCELL9:TEST0	BUFGCTRL29.I1MUX
TCELL9:TEST1	BUFGCTRL29.I0MUX
TCELL9:TEST2	BUFGCTRL28.I1MUX
TCELL9:TEST3	BUFGCTRL28.I0MUX
TCELL10:IMUX.CLK0	ICAP1.CLK
TCELL10:IMUX.CE0	ICAP1.WRITE
TCELL10:IMUX.CE1	ICAP1.CE
TCELL10:IMUX.CE2	CAPTURE.CLK
TCELL10:IMUX.IMUX0	BSCAN2.TDO
TCELL10:IMUX.IMUX1	DCIRESET.RST
TCELL10:OUT.BEST0.TMIN	BSCAN2.SEL
TCELL10:OUT.BEST1.TMIN	BSCAN2.UPDATE
TCELL10:OUT.BEST2.TMIN	BSCAN2.RESET
TCELL10:OUT.BEST3.TMIN	BSCAN2.TDI
TCELL10:OUT.BEST4.TMIN	BSCAN2.SHIFT
TCELL10:OUT.BEST5.TMIN	BSCAN2.DRCK
TCELL10:OUT.BEST6.TMIN	BSCAN2.CAPTURE
TCELL10:OUT.BEST7.TMIN	DCIRESET.LOCKED
TCELL10:TEST0	BUFGCTRL27.I1MUX
TCELL10:TEST1	BUFGCTRL27.I0MUX
TCELL10:TEST2	BUFGCTRL26.I1MUX
TCELL10:TEST3	BUFGCTRL26.I0MUX
TCELL11:IMUX.IMUX0	BUFGCTRL31.S0
TCELL11:IMUX.IMUX1	BUFGCTRL31.CE0
TCELL11:IMUX.IMUX2	BUFGCTRL31.IGNORE0
TCELL11:IMUX.IMUX3	BUFGCTRL31.CKINT0
TCELL11:IMUX.IMUX4	BUFGCTRL30.S0
TCELL11:IMUX.IMUX5	BUFGCTRL30.CE0
TCELL11:IMUX.IMUX6	BUFGCTRL30.IGNORE0
TCELL11:IMUX.IMUX7	BUFGCTRL30.CKINT0
TCELL11:IMUX.IMUX8	BUFGCTRL31.S1
TCELL11:IMUX.IMUX9	BUFGCTRL31.CE1
TCELL11:IMUX.IMUX10	BUFGCTRL31.IGNORE1
TCELL11:IMUX.IMUX11	BUFGCTRL31.CKINT1
TCELL11:IMUX.IMUX12	BUFGCTRL30.S1
TCELL11:IMUX.IMUX13	BUFGCTRL30.CE1
TCELL11:IMUX.IMUX14	BUFGCTRL30.IGNORE1
TCELL11:IMUX.IMUX15	BUFGCTRL30.CKINT1
TCELL11:IMUX.IMUX16	BUFGCTRL29.S0
TCELL11:IMUX.IMUX17	BUFGCTRL29.CE0
TCELL11:IMUX.IMUX18	BUFGCTRL29.IGNORE0
TCELL11:IMUX.IMUX19	BUFGCTRL29.CKINT0
TCELL11:IMUX.IMUX20	BUFGCTRL28.S0
TCELL11:IMUX.IMUX21	BUFGCTRL28.CE0
TCELL11:IMUX.IMUX22	BUFGCTRL28.IGNORE0
TCELL11:IMUX.IMUX23	BUFGCTRL28.CKINT0
TCELL11:IMUX.IMUX24	BUFGCTRL29.S1
TCELL11:IMUX.IMUX25	BUFGCTRL29.CE1
TCELL11:IMUX.IMUX26	BUFGCTRL29.IGNORE1
TCELL11:IMUX.IMUX27	BUFGCTRL29.CKINT1
TCELL11:IMUX.IMUX28	BUFGCTRL28.S1
TCELL11:IMUX.IMUX29	BUFGCTRL28.CE1
TCELL11:IMUX.IMUX30	BUFGCTRL28.IGNORE1
TCELL11:IMUX.IMUX31	BUFGCTRL28.CKINT1
TCELL11:OUT.BEST0.TMIN	ICAP1.O24
TCELL11:OUT.BEST1.TMIN	ICAP1.O25
TCELL11:OUT.BEST2.TMIN	ICAP1.O26
TCELL11:OUT.BEST3.TMIN	ICAP1.O27
TCELL11:OUT.BEST4.TMIN	ICAP1.O28
TCELL11:OUT.BEST5.TMIN	ICAP1.O29
TCELL11:OUT.BEST6.TMIN	ICAP1.O30
TCELL11:OUT.BEST7.TMIN	ICAP1.O31
TCELL11:OUT.SEC0.TMIN	USR_ACCESS.DATA24
TCELL11:OUT.SEC1.TMIN	USR_ACCESS.DATA25
TCELL11:OUT.SEC2.TMIN	USR_ACCESS.DATA26
TCELL11:OUT.SEC3.TMIN	USR_ACCESS.DATA27
TCELL11:OUT.SEC4.TMIN	USR_ACCESS.DATA28
TCELL11:OUT.SEC5.TMIN	USR_ACCESS.DATA29
TCELL11:OUT.SEC6.TMIN	USR_ACCESS.DATA30
TCELL11:OUT.SEC7.TMIN	USR_ACCESS.DATA31
TCELL11:TEST0	BUFGCTRL25.I1MUX
TCELL11:TEST1	BUFGCTRL25.I0MUX
TCELL11:TEST2	BUFGCTRL24.I1MUX
TCELL11:TEST3	BUFGCTRL24.I0MUX
TCELL12:IMUX.IMUX0	BUFGCTRL27.S0
TCELL12:IMUX.IMUX1	BUFGCTRL27.CE0
TCELL12:IMUX.IMUX2	BUFGCTRL27.IGNORE0
TCELL12:IMUX.IMUX3	BUFGCTRL27.CKINT0
TCELL12:IMUX.IMUX4	BUFGCTRL26.S0
TCELL12:IMUX.IMUX5	BUFGCTRL26.CE0
TCELL12:IMUX.IMUX6	BUFGCTRL26.IGNORE0
TCELL12:IMUX.IMUX7	BUFGCTRL26.CKINT0
TCELL12:IMUX.IMUX8	BUFGCTRL27.S1
TCELL12:IMUX.IMUX9	BUFGCTRL27.CE1
TCELL12:IMUX.IMUX10	BUFGCTRL27.IGNORE1
TCELL12:IMUX.IMUX11	BUFGCTRL27.CKINT1
TCELL12:IMUX.IMUX12	BUFGCTRL26.S1
TCELL12:IMUX.IMUX13	BUFGCTRL26.CE1
TCELL12:IMUX.IMUX14	BUFGCTRL26.IGNORE1
TCELL12:IMUX.IMUX15	BUFGCTRL26.CKINT1
TCELL12:IMUX.IMUX16	BUFGCTRL25.S0
TCELL12:IMUX.IMUX17	BUFGCTRL25.CE0
TCELL12:IMUX.IMUX18	BUFGCTRL25.IGNORE0
TCELL12:IMUX.IMUX19	BUFGCTRL25.CKINT0
TCELL12:IMUX.IMUX20	BUFGCTRL24.S0
TCELL12:IMUX.IMUX21	BUFGCTRL24.CE0
TCELL12:IMUX.IMUX22	BUFGCTRL24.IGNORE0
TCELL12:IMUX.IMUX23	BUFGCTRL24.CKINT0
TCELL12:IMUX.IMUX24	BUFGCTRL25.S1
TCELL12:IMUX.IMUX25	BUFGCTRL25.CE1
TCELL12:IMUX.IMUX26	BUFGCTRL25.IGNORE1
TCELL12:IMUX.IMUX27	BUFGCTRL25.CKINT1
TCELL12:IMUX.IMUX28	BUFGCTRL24.S1
TCELL12:IMUX.IMUX29	BUFGCTRL24.CE1
TCELL12:IMUX.IMUX30	BUFGCTRL24.IGNORE1
TCELL12:IMUX.IMUX31	BUFGCTRL24.CKINT1
TCELL12:OUT.BEST0.TMIN	ICAP1.O16
TCELL12:OUT.BEST1.TMIN	ICAP1.O17
TCELL12:OUT.BEST2.TMIN	ICAP1.O18
TCELL12:OUT.BEST3.TMIN	ICAP1.O19
TCELL12:OUT.BEST4.TMIN	ICAP1.O20
TCELL12:OUT.BEST5.TMIN	ICAP1.O21
TCELL12:OUT.BEST6.TMIN	ICAP1.O22
TCELL12:OUT.BEST7.TMIN	ICAP1.O23
TCELL12:OUT.SEC0.TMIN	USR_ACCESS.DATA16
TCELL12:OUT.SEC1.TMIN	USR_ACCESS.DATA17
TCELL12:OUT.SEC2.TMIN	USR_ACCESS.DATA18
TCELL12:OUT.SEC3.TMIN	USR_ACCESS.DATA19
TCELL12:OUT.SEC4.TMIN	USR_ACCESS.DATA20
TCELL12:OUT.SEC5.TMIN	USR_ACCESS.DATA21
TCELL12:OUT.SEC6.TMIN	USR_ACCESS.DATA22
TCELL12:OUT.SEC7.TMIN	USR_ACCESS.DATA23
TCELL12:TEST0	BUFGCTRL23.I1MUX
TCELL12:TEST1	BUFGCTRL23.I0MUX
TCELL12:TEST2	BUFGCTRL22.I1MUX
TCELL12:TEST3	BUFGCTRL22.I0MUX
TCELL13:IMUX.IMUX0	BUFGCTRL23.S0
TCELL13:IMUX.IMUX1	BUFGCTRL23.CE0
TCELL13:IMUX.IMUX2	BUFGCTRL23.IGNORE0
TCELL13:IMUX.IMUX3	BUFGCTRL23.CKINT0
TCELL13:IMUX.IMUX4	BUFGCTRL22.S0
TCELL13:IMUX.IMUX5	BUFGCTRL22.CE0
TCELL13:IMUX.IMUX6	BUFGCTRL22.IGNORE0
TCELL13:IMUX.IMUX7	BUFGCTRL22.CKINT0
TCELL13:IMUX.IMUX8	BUFGCTRL23.S1
TCELL13:IMUX.IMUX9	BUFGCTRL23.CE1
TCELL13:IMUX.IMUX10	BUFGCTRL23.IGNORE1
TCELL13:IMUX.IMUX11	BUFGCTRL23.CKINT1
TCELL13:IMUX.IMUX12	BUFGCTRL22.S1
TCELL13:IMUX.IMUX13	BUFGCTRL22.CE1
TCELL13:IMUX.IMUX14	BUFGCTRL22.IGNORE1
TCELL13:IMUX.IMUX15	BUFGCTRL22.CKINT1
TCELL13:IMUX.IMUX16	BUFGCTRL21.S0
TCELL13:IMUX.IMUX17	BUFGCTRL21.CE0
TCELL13:IMUX.IMUX18	BUFGCTRL21.IGNORE0
TCELL13:IMUX.IMUX19	BUFGCTRL21.CKINT0
TCELL13:IMUX.IMUX20	BUFGCTRL20.S0
TCELL13:IMUX.IMUX21	BUFGCTRL20.CE0
TCELL13:IMUX.IMUX22	BUFGCTRL20.IGNORE0
TCELL13:IMUX.IMUX23	BUFGCTRL20.CKINT0
TCELL13:IMUX.IMUX24	BUFGCTRL21.S1
TCELL13:IMUX.IMUX25	BUFGCTRL21.CE1
TCELL13:IMUX.IMUX26	BUFGCTRL21.IGNORE1
TCELL13:IMUX.IMUX27	BUFGCTRL21.CKINT1
TCELL13:IMUX.IMUX28	BUFGCTRL20.S1
TCELL13:IMUX.IMUX29	BUFGCTRL20.CE1
TCELL13:IMUX.IMUX30	BUFGCTRL20.IGNORE1
TCELL13:IMUX.IMUX31	BUFGCTRL20.CKINT1
TCELL13:OUT.BEST0.TMIN	ICAP1.O8
TCELL13:OUT.BEST1.TMIN	ICAP1.O9
TCELL13:OUT.BEST2.TMIN	ICAP1.O10
TCELL13:OUT.BEST3.TMIN	ICAP1.O11
TCELL13:OUT.BEST4.TMIN	ICAP1.O12
TCELL13:OUT.BEST5.TMIN	ICAP1.O13
TCELL13:OUT.BEST6.TMIN	ICAP1.O14
TCELL13:OUT.BEST7.TMIN	ICAP1.O15
TCELL13:OUT.SEC0.TMIN	USR_ACCESS.DATA8
TCELL13:OUT.SEC1.TMIN	USR_ACCESS.DATA9
TCELL13:OUT.SEC2.TMIN	USR_ACCESS.DATA10
TCELL13:OUT.SEC3.TMIN	USR_ACCESS.DATA11
TCELL13:OUT.SEC4.TMIN	USR_ACCESS.DATA12
TCELL13:OUT.SEC5.TMIN	USR_ACCESS.DATA13
TCELL13:OUT.SEC6.TMIN	USR_ACCESS.DATA14
TCELL13:OUT.SEC7.TMIN	USR_ACCESS.DATA15
TCELL13:TEST0	BUFGCTRL21.I1MUX
TCELL13:TEST1	BUFGCTRL21.I0MUX
TCELL13:TEST2	BUFGCTRL20.I1MUX
TCELL13:TEST3	BUFGCTRL20.I0MUX
TCELL14:IMUX.IMUX0	BUFGCTRL19.S0
TCELL14:IMUX.IMUX1	BUFGCTRL19.CE0
TCELL14:IMUX.IMUX2	BUFGCTRL19.IGNORE0
TCELL14:IMUX.IMUX3	BUFGCTRL19.CKINT0
TCELL14:IMUX.IMUX4	BUFGCTRL18.S0
TCELL14:IMUX.IMUX5	BUFGCTRL18.CE0
TCELL14:IMUX.IMUX6	BUFGCTRL18.IGNORE0
TCELL14:IMUX.IMUX7	BUFGCTRL18.CKINT0
TCELL14:IMUX.IMUX8	BUFGCTRL19.S1
TCELL14:IMUX.IMUX9	BUFGCTRL19.CE1
TCELL14:IMUX.IMUX10	BUFGCTRL19.IGNORE1
TCELL14:IMUX.IMUX11	BUFGCTRL19.CKINT1
TCELL14:IMUX.IMUX12	BUFGCTRL18.S1
TCELL14:IMUX.IMUX13	BUFGCTRL18.CE1
TCELL14:IMUX.IMUX14	BUFGCTRL18.IGNORE1
TCELL14:IMUX.IMUX15	BUFGCTRL18.CKINT1
TCELL14:IMUX.IMUX16	BUFGCTRL17.S0
TCELL14:IMUX.IMUX17	BUFGCTRL17.CE0
TCELL14:IMUX.IMUX18	BUFGCTRL17.IGNORE0
TCELL14:IMUX.IMUX19	BUFGCTRL17.CKINT0
TCELL14:IMUX.IMUX20	BUFGCTRL16.S0
TCELL14:IMUX.IMUX21	BUFGCTRL16.CE0
TCELL14:IMUX.IMUX22	BUFGCTRL16.IGNORE0
TCELL14:IMUX.IMUX23	BUFGCTRL16.CKINT0
TCELL14:IMUX.IMUX24	BUFGCTRL17.S1
TCELL14:IMUX.IMUX25	BUFGCTRL17.CE1
TCELL14:IMUX.IMUX26	BUFGCTRL17.IGNORE1
TCELL14:IMUX.IMUX27	BUFGCTRL17.CKINT1
TCELL14:IMUX.IMUX28	BUFGCTRL16.S1
TCELL14:IMUX.IMUX29	BUFGCTRL16.CE1
TCELL14:IMUX.IMUX30	BUFGCTRL16.IGNORE1
TCELL14:IMUX.IMUX31	BUFGCTRL16.CKINT1
TCELL14:OUT.BEST0.TMIN	ICAP1.O0
TCELL14:OUT.BEST1.TMIN	ICAP1.O1
TCELL14:OUT.BEST2.TMIN	ICAP1.O2
TCELL14:OUT.BEST3.TMIN	ICAP1.O3
TCELL14:OUT.BEST4.TMIN	ICAP1.O4
TCELL14:OUT.BEST5.TMIN	ICAP1.O5
TCELL14:OUT.BEST6.TMIN	ICAP1.O6
TCELL14:OUT.BEST7.TMIN	ICAP1.O7
TCELL14:OUT.SEC0.TMIN	USR_ACCESS.DATA0
TCELL14:OUT.SEC1.TMIN	USR_ACCESS.DATA1
TCELL14:OUT.SEC2.TMIN	USR_ACCESS.DATA2
TCELL14:OUT.SEC3.TMIN	USR_ACCESS.DATA3
TCELL14:OUT.SEC4.TMIN	USR_ACCESS.DATA4
TCELL14:OUT.SEC5.TMIN	USR_ACCESS.DATA5
TCELL14:OUT.SEC6.TMIN	USR_ACCESS.DATA6
TCELL14:OUT.SEC7.TMIN	USR_ACCESS.DATA7
TCELL14:TEST0	BUFGCTRL19.I1MUX
TCELL14:TEST1	BUFGCTRL19.I0MUX
TCELL14:TEST2	BUFGCTRL18.I1MUX
TCELL14:TEST3	BUFGCTRL18.I0MUX
TCELL15:IMUX.IMUX0	BSCAN3.TDO
TCELL15:OUT.BEST0.TMIN	BSCAN3.SEL
TCELL15:OUT.BEST1.TMIN	BSCAN3.UPDATE
TCELL15:OUT.BEST2.TMIN	BSCAN3.RESET
TCELL15:OUT.BEST3.TMIN	BSCAN3.TDI
TCELL15:OUT.BEST4.TMIN	BSCAN3.SHIFT
TCELL15:OUT.BEST5.TMIN	BSCAN3.DRCK
TCELL15:OUT.BEST6.TMIN	BSCAN3.CAPTURE
TCELL15:OUT.SEC0.TMIN	USR_ACCESS.DATAVALID
TCELL15:TEST0	BUFGCTRL17.I1MUX
TCELL15:TEST1	BUFGCTRL17.I0MUX
TCELL15:TEST2	BUFGCTRL16.I1MUX
TCELL15:TEST3	BUFGCTRL16.I0MUX

Bitstream

virtex4 CFG bittile 0
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TCKPIN[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TCKPIN[0]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TMSPIN[1]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TMSPIN[0]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TDIPIN[1]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TDIPIN[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TDOPIN[0]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:TDOPIN[1]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:BUSYPIN[1]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:BUSYPIN[0]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:POWERDOWNPIN[0]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M2PIN[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M2PIN[1]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M1PIN[0]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M1PIN[1]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M0PIN[0]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:M0PIN[1]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:GTS_GSR_ENABLE
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BSCAN0:ENABLE
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 1
Bit	Frame
Bit

virtex4 CFG bittile 2
Bit	Frame
Bit

virtex4 CFG bittile 3
Bit	Frame
Bit

virtex4 CFG bittile 4
Bit	Frame
Bit

virtex4 CFG bittile 5
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BSCAN1:ENABLE
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 6
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:DCI_CLK_ENABLE[1]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:DCI_CLK_ENABLE[0]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:USRCCLK_ENABLE
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 7
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:GTS_SYNC
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	JTAGPPC:ENABLE
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ICAP_COMMON:ICAP_WIDTH[0]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ICAP0:ENABLE
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[15]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[14]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[13]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[12]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[11]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[10]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[9]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[8]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[7]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[6]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[5]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[4]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[0]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 8
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:GSR_SYNC
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:GWE_SYNC
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ICAP1:ENABLE
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[31]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[30]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[29]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[28]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[27]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[26]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[25]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[24]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[23]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[22]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[21]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[20]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[19]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[18]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[17]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~BSCAN_COMMON:USERID[16]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 9
Bit	Frame
Bit

virtex4 CFG bittile 10
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCIRESET:ENABLE
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BSCAN2:ENABLE
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 11
Bit	Frame
Bit

virtex4 CFG bittile 12
Bit	Frame
Bit

virtex4 CFG bittile 13
Bit	Frame
Bit

virtex4 CFG bittile 14
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:PROBESEL[3]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:PROBESEL[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:PROBESEL[1]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:PROBESEL[0]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 15
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:HSWAPENPIN[0]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:HSWAPENPIN[1]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:PROGPIN[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:INITPIN[0]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:DONEPIN[0]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:CCLKPIN[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:DINPIN[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:DINPIN[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:CSPIN[0]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:CSPIN[1]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:RDWRPIN[0]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:RDWRPIN[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BSCAN3:ENABLE
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 CFG bittile 16
Bit	Frame
Bit

virtex4 CFG bittile 17
Bit	Frame
Bit	0	1
79	BUFGCTRL3:MUX.I1[6]	BUFGCTRL3:MUX.I0[6]
78	BUFGCTRL3:MUX.I1[11]	BUFGCTRL3:MUX.I0[11]
77	BUFGCTRL3:MUX.I0[7]	BUFGCTRL3:MUX.I1[7]
76	BUFGCTRL3:MUX.I0[8]	BUFGCTRL3:MUX.I1[8]
75	BUFGCTRL3:MUX.I0[9]	BUFGCTRL3:MUX.I1[9]
74	BUFGCTRL3:MUX.I0[10]	BUFGCTRL3:MUX.I1[10]
73	BUFGCTRL3:MUX.I0[0]	BUFGCTRL3:MUX.I1[0]
72	BUFGCTRL3:MUX.I0[1]	BUFGCTRL3:MUX.I1[1]
71	BUFGCTRL3:MUX.I0[2]	BUFGCTRL3:MUX.I1[2]
70	BUFGCTRL3:MUX.I0[3]	BUFGCTRL3:MUX.I1[3]
69	BUFGCTRL3:MUX.I0[4]	BUFGCTRL3:MUX.I1[4]
68	BUFGCTRL3:MUX.I0[5]	BUFGCTRL3:MUX.I1[5]
67	-	BUFGCTRL3:IMUX_ENABLE
66	-	-
65	-	-
64	-	-
63	BUFGCTRL2:MUX.I1[6]	BUFGCTRL2:MUX.I0[6]
62	BUFGCTRL2:MUX.I1[11]	BUFGCTRL2:MUX.I0[11]
61	BUFGCTRL2:MUX.I0[7]	BUFGCTRL2:MUX.I1[7]
60	BUFGCTRL2:MUX.I0[8]	BUFGCTRL2:MUX.I1[8]
59	BUFGCTRL2:MUX.I0[9]	BUFGCTRL2:MUX.I1[9]
58	BUFGCTRL2:MUX.I0[10]	BUFGCTRL2:MUX.I1[10]
57	BUFGCTRL2:MUX.I0[0]	BUFGCTRL2:MUX.I1[0]
56	BUFGCTRL2:MUX.I0[1]	BUFGCTRL2:MUX.I1[1]
55	BUFGCTRL2:MUX.I0[2]	BUFGCTRL2:MUX.I1[2]
54	BUFGCTRL2:MUX.I0[3]	BUFGCTRL2:MUX.I1[3]
53	BUFGCTRL2:MUX.I0[4]	BUFGCTRL2:MUX.I1[4]
52	BUFGCTRL2:MUX.I0[5]	BUFGCTRL2:MUX.I1[5]
51	-	BUFGCTRL2:IMUX_ENABLE
50	-	-
49	-	-
48	-	-
47	BUFGCTRL1:MUX.I1[6]	BUFGCTRL1:MUX.I0[6]
46	BUFGCTRL1:MUX.I1[11]	BUFGCTRL1:MUX.I0[11]
45	BUFGCTRL1:MUX.I0[7]	BUFGCTRL1:MUX.I1[7]
44	BUFGCTRL1:MUX.I0[8]	BUFGCTRL1:MUX.I1[8]
43	BUFGCTRL1:MUX.I0[9]	BUFGCTRL1:MUX.I1[9]
42	BUFGCTRL1:MUX.I0[10]	BUFGCTRL1:MUX.I1[10]
41	BUFGCTRL1:MUX.I0[0]	BUFGCTRL1:MUX.I1[0]
40	BUFGCTRL1:MUX.I0[1]	BUFGCTRL1:MUX.I1[1]
39	BUFGCTRL1:MUX.I0[2]	BUFGCTRL1:MUX.I1[2]
38	BUFGCTRL1:MUX.I0[3]	BUFGCTRL1:MUX.I1[3]
37	BUFGCTRL1:MUX.I0[4]	BUFGCTRL1:MUX.I1[4]
36	BUFGCTRL1:MUX.I0[5]	BUFGCTRL1:MUX.I1[5]
35	-	BUFGCTRL1:IMUX_ENABLE
34	-	-
33	-	-
32	-	-
31	BUFGCTRL0:MUX.I1[6]	BUFGCTRL0:MUX.I0[6]
30	BUFGCTRL0:MUX.I1[11]	BUFGCTRL0:MUX.I0[11]
29	BUFGCTRL0:MUX.I0[7]	BUFGCTRL0:MUX.I1[7]
28	BUFGCTRL0:MUX.I0[8]	BUFGCTRL0:MUX.I1[8]
27	BUFGCTRL0:MUX.I0[9]	BUFGCTRL0:MUX.I1[9]
26	BUFGCTRL0:MUX.I0[10]	BUFGCTRL0:MUX.I1[10]
25	BUFGCTRL0:MUX.I0[0]	BUFGCTRL0:MUX.I1[0]
24	BUFGCTRL0:MUX.I0[1]	BUFGCTRL0:MUX.I1[1]
23	BUFGCTRL0:MUX.I0[2]	BUFGCTRL0:MUX.I1[2]
22	BUFGCTRL0:MUX.I0[3]	BUFGCTRL0:MUX.I1[3]
21	BUFGCTRL0:MUX.I0[4]	BUFGCTRL0:MUX.I1[4]
20	BUFGCTRL0:MUX.I0[5]	BUFGCTRL0:MUX.I1[5]
19	-	BUFGCTRL0:IMUX_ENABLE
18	-	-
17	BUFG_MGTCLK_S:BUF.MGT_R0	-
16	BUFG_MGTCLK_S:BUF.MGT_R1	-
15	BUFG_MGTCLK_S:BUF.MGT_L0	-
14	BUFG_MGTCLK_S:BUF.MGT_L1	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 18
Bit	Frame
Bit	0	1
79	BUFGCTRL7:MUX.I1[6]	BUFGCTRL7:MUX.I0[6]
78	BUFGCTRL7:MUX.I1[11]	BUFGCTRL7:MUX.I0[11]
77	BUFGCTRL7:MUX.I0[7]	BUFGCTRL7:MUX.I1[7]
76	BUFGCTRL7:MUX.I0[8]	BUFGCTRL7:MUX.I1[8]
75	BUFGCTRL7:MUX.I0[9]	BUFGCTRL7:MUX.I1[9]
74	BUFGCTRL7:MUX.I0[10]	BUFGCTRL7:MUX.I1[10]
73	BUFGCTRL7:MUX.I0[0]	BUFGCTRL7:MUX.I1[0]
72	BUFGCTRL7:MUX.I0[1]	BUFGCTRL7:MUX.I1[1]
71	BUFGCTRL7:MUX.I0[2]	BUFGCTRL7:MUX.I1[2]
70	BUFGCTRL7:MUX.I0[3]	BUFGCTRL7:MUX.I1[3]
69	BUFGCTRL7:MUX.I0[4]	BUFGCTRL7:MUX.I1[4]
68	BUFGCTRL7:MUX.I0[5]	BUFGCTRL7:MUX.I1[5]
67	-	BUFGCTRL7:IMUX_ENABLE
66	-	-
65	-	-
64	-	-
63	BUFGCTRL6:MUX.I1[6]	BUFGCTRL6:MUX.I0[6]
62	BUFGCTRL6:MUX.I1[11]	BUFGCTRL6:MUX.I0[11]
61	BUFGCTRL6:MUX.I0[7]	BUFGCTRL6:MUX.I1[7]
60	BUFGCTRL6:MUX.I0[8]	BUFGCTRL6:MUX.I1[8]
59	BUFGCTRL6:MUX.I0[9]	BUFGCTRL6:MUX.I1[9]
58	BUFGCTRL6:MUX.I0[10]	BUFGCTRL6:MUX.I1[10]
57	BUFGCTRL6:MUX.I0[0]	BUFGCTRL6:MUX.I1[0]
56	BUFGCTRL6:MUX.I0[1]	BUFGCTRL6:MUX.I1[1]
55	BUFGCTRL6:MUX.I0[2]	BUFGCTRL6:MUX.I1[2]
54	BUFGCTRL6:MUX.I0[3]	BUFGCTRL6:MUX.I1[3]
53	BUFGCTRL6:MUX.I0[4]	BUFGCTRL6:MUX.I1[4]
52	BUFGCTRL6:MUX.I0[5]	BUFGCTRL6:MUX.I1[5]
51	-	BUFGCTRL6:IMUX_ENABLE
50	-	-
49	-	-
48	-	-
47	BUFGCTRL5:MUX.I1[6]	BUFGCTRL5:MUX.I0[6]
46	BUFGCTRL5:MUX.I1[11]	BUFGCTRL5:MUX.I0[11]
45	BUFGCTRL5:MUX.I0[7]	BUFGCTRL5:MUX.I1[7]
44	BUFGCTRL5:MUX.I0[8]	BUFGCTRL5:MUX.I1[8]
43	BUFGCTRL5:MUX.I0[9]	BUFGCTRL5:MUX.I1[9]
42	BUFGCTRL5:MUX.I0[10]	BUFGCTRL5:MUX.I1[10]
41	BUFGCTRL5:MUX.I0[0]	BUFGCTRL5:MUX.I1[0]
40	BUFGCTRL5:MUX.I0[1]	BUFGCTRL5:MUX.I1[1]
39	BUFGCTRL5:MUX.I0[2]	BUFGCTRL5:MUX.I1[2]
38	BUFGCTRL5:MUX.I0[3]	BUFGCTRL5:MUX.I1[3]
37	BUFGCTRL5:MUX.I0[4]	BUFGCTRL5:MUX.I1[4]
36	BUFGCTRL5:MUX.I0[5]	BUFGCTRL5:MUX.I1[5]
35	-	BUFGCTRL5:IMUX_ENABLE
34	-	-
33	-	-
32	-	-
31	BUFGCTRL4:MUX.I1[6]	BUFGCTRL4:MUX.I0[6]
30	BUFGCTRL4:MUX.I1[11]	BUFGCTRL4:MUX.I0[11]
29	BUFGCTRL4:MUX.I0[7]	BUFGCTRL4:MUX.I1[7]
28	BUFGCTRL4:MUX.I0[8]	BUFGCTRL4:MUX.I1[8]
27	BUFGCTRL4:MUX.I0[9]	BUFGCTRL4:MUX.I1[9]
26	BUFGCTRL4:MUX.I0[10]	BUFGCTRL4:MUX.I1[10]
25	BUFGCTRL4:MUX.I0[0]	BUFGCTRL4:MUX.I1[0]
24	BUFGCTRL4:MUX.I0[1]	BUFGCTRL4:MUX.I1[1]
23	BUFGCTRL4:MUX.I0[2]	BUFGCTRL4:MUX.I1[2]
22	BUFGCTRL4:MUX.I0[3]	BUFGCTRL4:MUX.I1[3]
21	BUFGCTRL4:MUX.I0[4]	BUFGCTRL4:MUX.I1[4]
20	BUFGCTRL4:MUX.I0[5]	BUFGCTRL4:MUX.I1[5]
19	-	BUFGCTRL4:IMUX_ENABLE
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 19
Bit	Frame
Bit	0	1
79	BUFGCTRL11:MUX.I1[6]	BUFGCTRL11:MUX.I0[6]
78	BUFGCTRL11:MUX.I1[11]	BUFGCTRL11:MUX.I0[11]
77	BUFGCTRL11:MUX.I0[7]	BUFGCTRL11:MUX.I1[7]
76	BUFGCTRL11:MUX.I0[8]	BUFGCTRL11:MUX.I1[8]
75	BUFGCTRL11:MUX.I0[9]	BUFGCTRL11:MUX.I1[9]
74	BUFGCTRL11:MUX.I0[10]	BUFGCTRL11:MUX.I1[10]
73	BUFGCTRL11:MUX.I0[0]	BUFGCTRL11:MUX.I1[0]
72	BUFGCTRL11:MUX.I0[1]	BUFGCTRL11:MUX.I1[1]
71	BUFGCTRL11:MUX.I0[2]	BUFGCTRL11:MUX.I1[2]
70	BUFGCTRL11:MUX.I0[3]	BUFGCTRL11:MUX.I1[3]
69	BUFGCTRL11:MUX.I0[4]	BUFGCTRL11:MUX.I1[4]
68	BUFGCTRL11:MUX.I0[5]	BUFGCTRL11:MUX.I1[5]
67	-	BUFGCTRL11:IMUX_ENABLE
66	-	-
65	-	-
64	-	-
63	BUFGCTRL10:MUX.I1[6]	BUFGCTRL10:MUX.I0[6]
62	BUFGCTRL10:MUX.I1[11]	BUFGCTRL10:MUX.I0[11]
61	BUFGCTRL10:MUX.I0[7]	BUFGCTRL10:MUX.I1[7]
60	BUFGCTRL10:MUX.I0[8]	BUFGCTRL10:MUX.I1[8]
59	BUFGCTRL10:MUX.I0[9]	BUFGCTRL10:MUX.I1[9]
58	BUFGCTRL10:MUX.I0[10]	BUFGCTRL10:MUX.I1[10]
57	BUFGCTRL10:MUX.I0[0]	BUFGCTRL10:MUX.I1[0]
56	BUFGCTRL10:MUX.I0[1]	BUFGCTRL10:MUX.I1[1]
55	BUFGCTRL10:MUX.I0[2]	BUFGCTRL10:MUX.I1[2]
54	BUFGCTRL10:MUX.I0[3]	BUFGCTRL10:MUX.I1[3]
53	BUFGCTRL10:MUX.I0[4]	BUFGCTRL10:MUX.I1[4]
52	BUFGCTRL10:MUX.I0[5]	BUFGCTRL10:MUX.I1[5]
51	-	BUFGCTRL10:IMUX_ENABLE
50	-	-
49	-	-
48	-	-
47	BUFGCTRL9:MUX.I1[6]	BUFGCTRL9:MUX.I0[6]
46	BUFGCTRL9:MUX.I1[11]	BUFGCTRL9:MUX.I0[11]
45	BUFGCTRL9:MUX.I0[7]	BUFGCTRL9:MUX.I1[7]
44	BUFGCTRL9:MUX.I0[8]	BUFGCTRL9:MUX.I1[8]
43	BUFGCTRL9:MUX.I0[9]	BUFGCTRL9:MUX.I1[9]
42	BUFGCTRL9:MUX.I0[10]	BUFGCTRL9:MUX.I1[10]
41	BUFGCTRL9:MUX.I0[0]	BUFGCTRL9:MUX.I1[0]
40	BUFGCTRL9:MUX.I0[1]	BUFGCTRL9:MUX.I1[1]
39	BUFGCTRL9:MUX.I0[2]	BUFGCTRL9:MUX.I1[2]
38	BUFGCTRL9:MUX.I0[3]	BUFGCTRL9:MUX.I1[3]
37	BUFGCTRL9:MUX.I0[4]	BUFGCTRL9:MUX.I1[4]
36	BUFGCTRL9:MUX.I0[5]	BUFGCTRL9:MUX.I1[5]
35	-	BUFGCTRL9:IMUX_ENABLE
34	-	-
33	-	-
32	-	-
31	BUFGCTRL8:MUX.I1[6]	BUFGCTRL8:MUX.I0[6]
30	BUFGCTRL8:MUX.I1[11]	BUFGCTRL8:MUX.I0[11]
29	BUFGCTRL8:MUX.I0[7]	BUFGCTRL8:MUX.I1[7]
28	BUFGCTRL8:MUX.I0[8]	BUFGCTRL8:MUX.I1[8]
27	BUFGCTRL8:MUX.I0[9]	BUFGCTRL8:MUX.I1[9]
26	BUFGCTRL8:MUX.I0[10]	BUFGCTRL8:MUX.I1[10]
25	BUFGCTRL8:MUX.I0[0]	BUFGCTRL8:MUX.I1[0]
24	BUFGCTRL8:MUX.I0[1]	BUFGCTRL8:MUX.I1[1]
23	BUFGCTRL8:MUX.I0[2]	BUFGCTRL8:MUX.I1[2]
22	BUFGCTRL8:MUX.I0[3]	BUFGCTRL8:MUX.I1[3]
21	BUFGCTRL8:MUX.I0[4]	BUFGCTRL8:MUX.I1[4]
20	BUFGCTRL8:MUX.I0[5]	BUFGCTRL8:MUX.I1[5]
19	-	BUFGCTRL8:IMUX_ENABLE
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 20
Bit	Frame
Bit	0	1
79	BUFGCTRL15:MUX.I1[6]	BUFGCTRL15:MUX.I0[6]
78	BUFGCTRL15:MUX.I1[11]	BUFGCTRL15:MUX.I0[11]
77	BUFGCTRL15:MUX.I0[7]	BUFGCTRL15:MUX.I1[7]
76	BUFGCTRL15:MUX.I0[8]	BUFGCTRL15:MUX.I1[8]
75	BUFGCTRL15:MUX.I0[9]	BUFGCTRL15:MUX.I1[9]
74	BUFGCTRL15:MUX.I0[10]	BUFGCTRL15:MUX.I1[10]
73	BUFGCTRL15:MUX.I0[0]	BUFGCTRL15:MUX.I1[0]
72	BUFGCTRL15:MUX.I0[1]	BUFGCTRL15:MUX.I1[1]
71	BUFGCTRL15:MUX.I0[2]	BUFGCTRL15:MUX.I1[2]
70	BUFGCTRL15:MUX.I0[3]	BUFGCTRL15:MUX.I1[3]
69	BUFGCTRL15:MUX.I0[4]	BUFGCTRL15:MUX.I1[4]
68	BUFGCTRL15:MUX.I0[5]	BUFGCTRL15:MUX.I1[5]
67	-	BUFGCTRL15:IMUX_ENABLE
66	-	-
65	-	-
64	-	-
63	BUFGCTRL14:MUX.I1[6]	BUFGCTRL14:MUX.I0[6]
62	BUFGCTRL14:MUX.I1[11]	BUFGCTRL14:MUX.I0[11]
61	BUFGCTRL14:MUX.I0[7]	BUFGCTRL14:MUX.I1[7]
60	BUFGCTRL14:MUX.I0[8]	BUFGCTRL14:MUX.I1[8]
59	BUFGCTRL14:MUX.I0[9]	BUFGCTRL14:MUX.I1[9]
58	BUFGCTRL14:MUX.I0[10]	BUFGCTRL14:MUX.I1[10]
57	BUFGCTRL14:MUX.I0[0]	BUFGCTRL14:MUX.I1[0]
56	BUFGCTRL14:MUX.I0[1]	BUFGCTRL14:MUX.I1[1]
55	BUFGCTRL14:MUX.I0[2]	BUFGCTRL14:MUX.I1[2]
54	BUFGCTRL14:MUX.I0[3]	BUFGCTRL14:MUX.I1[3]
53	BUFGCTRL14:MUX.I0[4]	BUFGCTRL14:MUX.I1[4]
52	BUFGCTRL14:MUX.I0[5]	BUFGCTRL14:MUX.I1[5]
51	-	BUFGCTRL14:IMUX_ENABLE
50	-	-
49	-	-
48	-	-
47	BUFGCTRL13:MUX.I1[6]	BUFGCTRL13:MUX.I0[6]
46	BUFGCTRL13:MUX.I1[11]	BUFGCTRL13:MUX.I0[11]
45	BUFGCTRL13:MUX.I0[7]	BUFGCTRL13:MUX.I1[7]
44	BUFGCTRL13:MUX.I0[8]	BUFGCTRL13:MUX.I1[8]
43	BUFGCTRL13:MUX.I0[9]	BUFGCTRL13:MUX.I1[9]
42	BUFGCTRL13:MUX.I0[10]	BUFGCTRL13:MUX.I1[10]
41	BUFGCTRL13:MUX.I0[0]	BUFGCTRL13:MUX.I1[0]
40	BUFGCTRL13:MUX.I0[1]	BUFGCTRL13:MUX.I1[1]
39	BUFGCTRL13:MUX.I0[2]	BUFGCTRL13:MUX.I1[2]
38	BUFGCTRL13:MUX.I0[3]	BUFGCTRL13:MUX.I1[3]
37	BUFGCTRL13:MUX.I0[4]	BUFGCTRL13:MUX.I1[4]
36	BUFGCTRL13:MUX.I0[5]	BUFGCTRL13:MUX.I1[5]
35	-	BUFGCTRL13:IMUX_ENABLE
34	-	-
33	-	-
32	-	-
31	BUFGCTRL12:MUX.I1[6]	BUFGCTRL12:MUX.I0[6]
30	BUFGCTRL12:MUX.I1[11]	BUFGCTRL12:MUX.I0[11]
29	BUFGCTRL12:MUX.I0[7]	BUFGCTRL12:MUX.I1[7]
28	BUFGCTRL12:MUX.I0[8]	BUFGCTRL12:MUX.I1[8]
27	BUFGCTRL12:MUX.I0[9]	BUFGCTRL12:MUX.I1[9]
26	BUFGCTRL12:MUX.I0[10]	BUFGCTRL12:MUX.I1[10]
25	BUFGCTRL12:MUX.I0[0]	BUFGCTRL12:MUX.I1[0]
24	BUFGCTRL12:MUX.I0[1]	BUFGCTRL12:MUX.I1[1]
23	BUFGCTRL12:MUX.I0[2]	BUFGCTRL12:MUX.I1[2]
22	BUFGCTRL12:MUX.I0[3]	BUFGCTRL12:MUX.I1[3]
21	BUFGCTRL12:MUX.I0[4]	BUFGCTRL12:MUX.I1[4]
20	BUFGCTRL12:MUX.I0[5]	BUFGCTRL12:MUX.I1[5]
19	-	BUFGCTRL12:IMUX_ENABLE
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 21
Bit	Frame
Bit	0	1
79	~BUFGCTRL14:INV.S0	~BUFGCTRL14:INV.CE0
78	BUFGCTRL14:INIT_OUT	BUFGCTRL14:PRESELECT_I0
77	~BUFGCTRL14:INV.IGNORE1	~BUFGCTRL14:INV.IGNORE0
76	~BUFGCTRL14:CREATE_EDGE	BUFGCTRL14:PRESELECT_I1
75	~BUFGCTRL14:INV.S1	~BUFGCTRL14:INV.CE1
74	~BUFGCTRL15:INV.S0	~BUFGCTRL15:INV.CE0
73	BUFGCTRL15:INIT_OUT	BUFGCTRL15:PRESELECT_I0
72	~BUFGCTRL15:INV.IGNORE1	~BUFGCTRL15:INV.IGNORE0
71	~BUFGCTRL15:CREATE_EDGE	BUFGCTRL15:PRESELECT_I1
70	~BUFGCTRL15:INV.S1	~BUFGCTRL15:INV.CE1
69	~BUFGCTRL12:INV.S0	~BUFGCTRL12:INV.CE0
68	BUFGCTRL12:INIT_OUT	BUFGCTRL12:PRESELECT_I0
67	~BUFGCTRL12:INV.IGNORE1	~BUFGCTRL12:INV.IGNORE0
66	~BUFGCTRL12:CREATE_EDGE	BUFGCTRL12:PRESELECT_I1
65	~BUFGCTRL12:INV.S1	~BUFGCTRL12:INV.CE1
64	~BUFGCTRL13:INV.S0	~BUFGCTRL13:INV.CE0
63	BUFGCTRL13:INIT_OUT	BUFGCTRL13:PRESELECT_I0
62	~BUFGCTRL13:INV.IGNORE1	~BUFGCTRL13:INV.IGNORE0
61	~BUFGCTRL13:CREATE_EDGE	BUFGCTRL13:PRESELECT_I1
60	~BUFGCTRL13:INV.S1	~BUFGCTRL13:INV.CE1
59	~BUFGCTRL10:INV.S0	~BUFGCTRL10:INV.CE0
58	BUFGCTRL10:INIT_OUT	BUFGCTRL10:PRESELECT_I0
57	~BUFGCTRL10:INV.IGNORE1	~BUFGCTRL10:INV.IGNORE0
56	~BUFGCTRL10:CREATE_EDGE	BUFGCTRL10:PRESELECT_I1
55	~BUFGCTRL10:INV.S1	~BUFGCTRL10:INV.CE1
54	~BUFGCTRL11:INV.S0	~BUFGCTRL11:INV.CE0
53	BUFGCTRL11:INIT_OUT	BUFGCTRL11:PRESELECT_I0
52	~BUFGCTRL11:INV.IGNORE1	~BUFGCTRL11:INV.IGNORE0
51	~BUFGCTRL11:CREATE_EDGE	BUFGCTRL11:PRESELECT_I1
50	~BUFGCTRL11:INV.S1	~BUFGCTRL11:INV.CE1
49	~BUFGCTRL8:INV.S0	~BUFGCTRL8:INV.CE0
48	BUFGCTRL8:INIT_OUT	BUFGCTRL8:PRESELECT_I0
47	~BUFGCTRL8:INV.IGNORE1	~BUFGCTRL8:INV.IGNORE0
46	~BUFGCTRL8:CREATE_EDGE	BUFGCTRL8:PRESELECT_I1
45	~BUFGCTRL8:INV.S1	~BUFGCTRL8:INV.CE1
44	~BUFGCTRL9:INV.S0	~BUFGCTRL9:INV.CE0
43	BUFGCTRL9:INIT_OUT	BUFGCTRL9:PRESELECT_I0
42	~BUFGCTRL9:INV.IGNORE1	~BUFGCTRL9:INV.IGNORE0
41	~BUFGCTRL9:CREATE_EDGE	BUFGCTRL9:PRESELECT_I1
40	~BUFGCTRL9:INV.S1	~BUFGCTRL9:INV.CE1
39	~BUFGCTRL6:INV.S0	~BUFGCTRL6:INV.CE0
38	BUFGCTRL6:INIT_OUT	BUFGCTRL6:PRESELECT_I0
37	~BUFGCTRL6:INV.IGNORE1	~BUFGCTRL6:INV.IGNORE0
36	~BUFGCTRL6:CREATE_EDGE	BUFGCTRL6:PRESELECT_I1
35	~BUFGCTRL6:INV.S1	~BUFGCTRL6:INV.CE1
34	~BUFGCTRL7:INV.S0	~BUFGCTRL7:INV.CE0
33	BUFGCTRL7:INIT_OUT	BUFGCTRL7:PRESELECT_I0
32	~BUFGCTRL7:INV.IGNORE1	~BUFGCTRL7:INV.IGNORE0
31	~BUFGCTRL7:CREATE_EDGE	BUFGCTRL7:PRESELECT_I1
30	~BUFGCTRL7:INV.S1	~BUFGCTRL7:INV.CE1
29	~BUFGCTRL4:INV.S0	~BUFGCTRL4:INV.CE0
28	BUFGCTRL4:INIT_OUT	BUFGCTRL4:PRESELECT_I0
27	~BUFGCTRL4:INV.IGNORE1	~BUFGCTRL4:INV.IGNORE0
26	~BUFGCTRL4:CREATE_EDGE	BUFGCTRL4:PRESELECT_I1
25	~BUFGCTRL4:INV.S1	~BUFGCTRL4:INV.CE1
24	~BUFGCTRL5:INV.S0	~BUFGCTRL5:INV.CE0
23	BUFGCTRL5:INIT_OUT	BUFGCTRL5:PRESELECT_I0
22	~BUFGCTRL5:INV.IGNORE1	~BUFGCTRL5:INV.IGNORE0
21	~BUFGCTRL5:CREATE_EDGE	BUFGCTRL5:PRESELECT_I1
20	~BUFGCTRL5:INV.S1	~BUFGCTRL5:INV.CE1
19	~BUFGCTRL2:INV.S0	~BUFGCTRL2:INV.CE0
18	BUFGCTRL2:INIT_OUT	BUFGCTRL2:PRESELECT_I0
17	~BUFGCTRL2:INV.IGNORE1	~BUFGCTRL2:INV.IGNORE0
16	~BUFGCTRL2:CREATE_EDGE	BUFGCTRL2:PRESELECT_I1
15	~BUFGCTRL2:INV.S1	~BUFGCTRL2:INV.CE1
14	~BUFGCTRL3:INV.S0	~BUFGCTRL3:INV.CE0
13	BUFGCTRL3:INIT_OUT	BUFGCTRL3:PRESELECT_I0
12	~BUFGCTRL3:INV.IGNORE1	~BUFGCTRL3:INV.IGNORE0
11	~BUFGCTRL3:CREATE_EDGE	BUFGCTRL3:PRESELECT_I1
10	~BUFGCTRL3:INV.S1	~BUFGCTRL3:INV.CE1
9	~BUFGCTRL0:INV.S0	~BUFGCTRL0:INV.CE0
8	BUFGCTRL0:INIT_OUT	BUFGCTRL0:PRESELECT_I0
7	~BUFGCTRL0:INV.IGNORE1	~BUFGCTRL0:INV.IGNORE0
6	~BUFGCTRL0:CREATE_EDGE	BUFGCTRL0:PRESELECT_I1
5	~BUFGCTRL0:INV.S1	~BUFGCTRL0:INV.CE1
4	~BUFGCTRL1:INV.S0	~BUFGCTRL1:INV.CE0
3	BUFGCTRL1:INIT_OUT	BUFGCTRL1:PRESELECT_I0
2	~BUFGCTRL1:INV.IGNORE1	~BUFGCTRL1:INV.IGNORE0
1	~BUFGCTRL1:CREATE_EDGE	BUFGCTRL1:PRESELECT_I1
0	~BUFGCTRL1:INV.S1	~BUFGCTRL1:INV.CE1

virtex4 CFG bittile 22
Bit	Frame
Bit	0	1
79	-	BUFGCTRL7:ENABLE[4]
78	-	BUFGCTRL7:ENABLE[3]
77	BUFGCTRL7:ENABLE[0]	BUFGCTRL7:ENABLE[2]
76	-	BUFGCTRL7:ENABLE[1]
75	-	-
74	-	-
73	-	-
72	-	-
71	-	-
70	-	-
69	-	BUFGCTRL6:ENABLE[4]
68	-	BUFGCTRL6:ENABLE[3]
67	BUFGCTRL6:ENABLE[0]	BUFGCTRL6:ENABLE[2]
66	-	BUFGCTRL6:ENABLE[1]
65	-	-
64	-	-
63	-	-
62	-	-
61	-	-
60	-	-
59	-	BUFGCTRL5:ENABLE[4]
58	-	BUFGCTRL5:ENABLE[3]
57	BUFGCTRL5:ENABLE[0]	BUFGCTRL5:ENABLE[2]
56	-	BUFGCTRL5:ENABLE[1]
55	-	-
54	-	-
53	-	-
52	-	-
51	-	-
50	-	-
49	-	BUFGCTRL4:ENABLE[4]
48	-	BUFGCTRL4:ENABLE[3]
47	BUFGCTRL4:ENABLE[0]	BUFGCTRL4:ENABLE[2]
46	-	BUFGCTRL4:ENABLE[1]
45	-	-
44	-	-
43	-	-
42	-	-
41	-	-
40	-	-
39	-	BUFGCTRL3:ENABLE[4]
38	-	BUFGCTRL3:ENABLE[3]
37	BUFGCTRL3:ENABLE[0]	BUFGCTRL3:ENABLE[2]
36	-	BUFGCTRL3:ENABLE[1]
35	-	-
34	-	-
33	-	-
32	-	-
31	-	-
30	-	-
29	-	BUFGCTRL2:ENABLE[4]
28	-	BUFGCTRL2:ENABLE[3]
27	BUFGCTRL2:ENABLE[0]	BUFGCTRL2:ENABLE[2]
26	-	BUFGCTRL2:ENABLE[1]
25	-	-
24	-	-
23	-	-
22	-	-
21	-	-
20	-	-
19	-	BUFGCTRL1:ENABLE[4]
18	-	BUFGCTRL1:ENABLE[3]
17	BUFGCTRL1:ENABLE[0]	BUFGCTRL1:ENABLE[2]
16	-	BUFGCTRL1:ENABLE[1]
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	BUFGCTRL0:ENABLE[4]
8	-	BUFGCTRL0:ENABLE[3]
7	BUFGCTRL0:ENABLE[0]	BUFGCTRL0:ENABLE[2]
6	-	BUFGCTRL0:ENABLE[1]
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 23
Bit	Frame
Bit	0	1
79	-	BUFGCTRL15:ENABLE[4]
78	-	BUFGCTRL15:ENABLE[3]
77	BUFGCTRL15:ENABLE[0]	BUFGCTRL15:ENABLE[2]
76	-	BUFGCTRL15:ENABLE[1]
75	-	-
74	-	-
73	-	-
72	-	-
71	-	-
70	-	-
69	-	BUFGCTRL14:ENABLE[4]
68	-	BUFGCTRL14:ENABLE[3]
67	BUFGCTRL14:ENABLE[0]	BUFGCTRL14:ENABLE[2]
66	-	BUFGCTRL14:ENABLE[1]
65	-	-
64	-	-
63	-	-
62	-	-
61	-	-
60	-	-
59	-	BUFGCTRL13:ENABLE[4]
58	-	BUFGCTRL13:ENABLE[3]
57	BUFGCTRL13:ENABLE[0]	BUFGCTRL13:ENABLE[2]
56	-	BUFGCTRL13:ENABLE[1]
55	-	-
54	-	-
53	-	-
52	-	-
51	-	-
50	-	-
49	-	BUFGCTRL12:ENABLE[4]
48	-	BUFGCTRL12:ENABLE[3]
47	BUFGCTRL12:ENABLE[0]	BUFGCTRL12:ENABLE[2]
46	-	BUFGCTRL12:ENABLE[1]
45	-	-
44	-	-
43	-	-
42	-	-
41	-	-
40	-	-
39	-	BUFGCTRL11:ENABLE[4]
38	-	BUFGCTRL11:ENABLE[3]
37	BUFGCTRL11:ENABLE[0]	BUFGCTRL11:ENABLE[2]
36	-	BUFGCTRL11:ENABLE[1]
35	-	-
34	-	-
33	-	-
32	-	-
31	-	-
30	-	-
29	-	BUFGCTRL10:ENABLE[4]
28	-	BUFGCTRL10:ENABLE[3]
27	BUFGCTRL10:ENABLE[0]	BUFGCTRL10:ENABLE[2]
26	-	BUFGCTRL10:ENABLE[1]
25	-	-
24	-	-
23	-	-
22	-	-
21	-	-
20	-	-
19	-	BUFGCTRL9:ENABLE[4]
18	-	BUFGCTRL9:ENABLE[3]
17	BUFGCTRL9:ENABLE[0]	BUFGCTRL9:ENABLE[2]
16	-	BUFGCTRL9:ENABLE[1]
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	BUFGCTRL8:ENABLE[4]
8	-	BUFGCTRL8:ENABLE[3]
7	BUFGCTRL8:ENABLE[0]	BUFGCTRL8:ENABLE[2]
6	-	BUFGCTRL8:ENABLE[1]
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

virtex4 CFG bittile 24
Bit	Frame
Bit	0	1
73	-	BUFGCTRL24:ENABLE[4]
72	BUFGCTRL24:ENABLE[0]	BUFGCTRL24:ENABLE[3]
71	-	BUFGCTRL24:ENABLE[2]
70	-	BUFGCTRL24:ENABLE[1]
69	-	-
68	-	-
67	-	-
66	-	-
65	-	-
64	-	-
63	-	BUFGCTRL25:ENABLE[4]
62	BUFGCTRL25:ENABLE[0]	BUFGCTRL25:ENABLE[3]
61	-	BUFGCTRL25:ENABLE[2]
60	-	BUFGCTRL25:ENABLE[1]
59	-	-
58	-	-
57	-	-
56	-	-
55	-	-
54	-	-
53	-	BUFGCTRL26:ENABLE[4]
52	BUFGCTRL26:ENABLE[0]	BUFGCTRL26:ENABLE[3]
51	-	BUFGCTRL26:ENABLE[2]
50	-	BUFGCTRL26:ENABLE[1]
49	-	-
48	-	-
47	-	-
46	-	-
45	-	-
44	-	-
43	-	BUFGCTRL27:ENABLE[4]
42	BUFGCTRL27:ENABLE[0]	BUFGCTRL27:ENABLE[3]
41	-	BUFGCTRL27:ENABLE[2]
40	-	BUFGCTRL27:ENABLE[1]
39	-	-
38	-	-
37	-	-
36	-	-
35	-	-
34	-	-
33	-	BUFGCTRL28:ENABLE[4]
32	BUFGCTRL28:ENABLE[0]	BUFGCTRL28:ENABLE[3]
31	-	BUFGCTRL28:ENABLE[2]
30	-	BUFGCTRL28:ENABLE[1]
29	-	-
28	-	-
27	-	-
26	-	-
25	-	-
24	-	-
23	-	BUFGCTRL29:ENABLE[4]
22	BUFGCTRL29:ENABLE[0]	BUFGCTRL29:ENABLE[3]
21	-	BUFGCTRL29:ENABLE[2]
20	-	BUFGCTRL29:ENABLE[1]
19	-	-
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	BUFGCTRL30:ENABLE[4]
12	BUFGCTRL30:ENABLE[0]	BUFGCTRL30:ENABLE[3]
11	-	BUFGCTRL30:ENABLE[2]
10	-	BUFGCTRL30:ENABLE[1]
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	BUFGCTRL31:ENABLE[4]
2	BUFGCTRL31:ENABLE[0]	BUFGCTRL31:ENABLE[3]
1	-	BUFGCTRL31:ENABLE[2]
0	-	BUFGCTRL31:ENABLE[1]

virtex4 CFG bittile 25
Bit	Frame
Bit	0	1
73	-	BUFGCTRL16:ENABLE[4]
72	BUFGCTRL16:ENABLE[0]	BUFGCTRL16:ENABLE[3]
71	-	BUFGCTRL16:ENABLE[2]
70	-	BUFGCTRL16:ENABLE[1]
69	-	-
68	-	-
67	-	-
66	-	-
65	-	-
64	-	-
63	-	BUFGCTRL17:ENABLE[4]
62	BUFGCTRL17:ENABLE[0]	BUFGCTRL17:ENABLE[3]
61	-	BUFGCTRL17:ENABLE[2]
60	-	BUFGCTRL17:ENABLE[1]
59	-	-
58	-	-
57	-	-
56	-	-
55	-	-
54	-	-
53	-	BUFGCTRL18:ENABLE[4]
52	BUFGCTRL18:ENABLE[0]	BUFGCTRL18:ENABLE[3]
51	-	BUFGCTRL18:ENABLE[2]
50	-	BUFGCTRL18:ENABLE[1]
49	-	-
48	-	-
47	-	-
46	-	-
45	-	-
44	-	-
43	-	BUFGCTRL19:ENABLE[4]
42	BUFGCTRL19:ENABLE[0]	BUFGCTRL19:ENABLE[3]
41	-	BUFGCTRL19:ENABLE[2]
40	-	BUFGCTRL19:ENABLE[1]
39	-	-
38	-	-
37	-	-
36	-	-
35	-	-
34	-	-
33	-	BUFGCTRL20:ENABLE[4]
32	BUFGCTRL20:ENABLE[0]	BUFGCTRL20:ENABLE[3]
31	-	BUFGCTRL20:ENABLE[2]
30	-	BUFGCTRL20:ENABLE[1]
29	-	-
28	-	-
27	-	-
26	-	-
25	-	-
24	-	-
23	-	BUFGCTRL21:ENABLE[4]
22	BUFGCTRL21:ENABLE[0]	BUFGCTRL21:ENABLE[3]
21	-	BUFGCTRL21:ENABLE[2]
20	-	BUFGCTRL21:ENABLE[1]
19	-	-
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	BUFGCTRL22:ENABLE[4]
12	BUFGCTRL22:ENABLE[0]	BUFGCTRL22:ENABLE[3]
11	-	BUFGCTRL22:ENABLE[2]
10	-	BUFGCTRL22:ENABLE[1]
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	BUFGCTRL23:ENABLE[4]
2	BUFGCTRL23:ENABLE[0]	BUFGCTRL23:ENABLE[3]
1	-	BUFGCTRL23:ENABLE[2]
0	-	BUFGCTRL23:ENABLE[1]

virtex4 CFG bittile 26
Bit	Frame
Bit	0	1
79	~BUFGCTRL17:INV.S1	~BUFGCTRL17:INV.CE1
78	~BUFGCTRL17:CREATE_EDGE	BUFGCTRL17:PRESELECT_I1
77	~BUFGCTRL17:INV.IGNORE1	~BUFGCTRL17:INV.IGNORE0
76	BUFGCTRL17:INIT_OUT	BUFGCTRL17:PRESELECT_I0
75	~BUFGCTRL17:INV.S0	~BUFGCTRL17:INV.CE0
74	~BUFGCTRL16:INV.S1	~BUFGCTRL16:INV.CE1
73	~BUFGCTRL16:CREATE_EDGE	BUFGCTRL16:PRESELECT_I1
72	~BUFGCTRL16:INV.IGNORE1	~BUFGCTRL16:INV.IGNORE0
71	BUFGCTRL16:INIT_OUT	BUFGCTRL16:PRESELECT_I0
70	~BUFGCTRL16:INV.S0	~BUFGCTRL16:INV.CE0
69	~BUFGCTRL19:INV.S1	~BUFGCTRL19:INV.CE1
68	~BUFGCTRL19:CREATE_EDGE	BUFGCTRL19:PRESELECT_I1
67	~BUFGCTRL19:INV.IGNORE1	~BUFGCTRL19:INV.IGNORE0
66	BUFGCTRL19:INIT_OUT	BUFGCTRL19:PRESELECT_I0
65	~BUFGCTRL19:INV.S0	~BUFGCTRL19:INV.CE0
64	~BUFGCTRL18:INV.S1	~BUFGCTRL18:INV.CE1
63	~BUFGCTRL18:CREATE_EDGE	BUFGCTRL18:PRESELECT_I1
62	~BUFGCTRL18:INV.IGNORE1	~BUFGCTRL18:INV.IGNORE0
61	BUFGCTRL18:INIT_OUT	BUFGCTRL18:PRESELECT_I0
60	~BUFGCTRL18:INV.S0	~BUFGCTRL18:INV.CE0
59	~BUFGCTRL21:INV.S1	~BUFGCTRL21:INV.CE1
58	~BUFGCTRL21:CREATE_EDGE	BUFGCTRL21:PRESELECT_I1
57	~BUFGCTRL21:INV.IGNORE1	~BUFGCTRL21:INV.IGNORE0
56	BUFGCTRL21:INIT_OUT	BUFGCTRL21:PRESELECT_I0
55	~BUFGCTRL21:INV.S0	~BUFGCTRL21:INV.CE0
54	~BUFGCTRL20:INV.S1	~BUFGCTRL20:INV.CE1
53	~BUFGCTRL20:CREATE_EDGE	BUFGCTRL20:PRESELECT_I1
52	~BUFGCTRL20:INV.IGNORE1	~BUFGCTRL20:INV.IGNORE0
51	BUFGCTRL20:INIT_OUT	BUFGCTRL20:PRESELECT_I0
50	~BUFGCTRL20:INV.S0	~BUFGCTRL20:INV.CE0
49	~BUFGCTRL23:INV.S1	~BUFGCTRL23:INV.CE1
48	~BUFGCTRL23:CREATE_EDGE	BUFGCTRL23:PRESELECT_I1
47	~BUFGCTRL23:INV.IGNORE1	~BUFGCTRL23:INV.IGNORE0
46	BUFGCTRL23:INIT_OUT	BUFGCTRL23:PRESELECT_I0
45	~BUFGCTRL23:INV.S0	~BUFGCTRL23:INV.CE0
44	~BUFGCTRL22:INV.S1	~BUFGCTRL22:INV.CE1
43	~BUFGCTRL22:CREATE_EDGE	BUFGCTRL22:PRESELECT_I1
42	~BUFGCTRL22:INV.IGNORE1	~BUFGCTRL22:INV.IGNORE0
41	BUFGCTRL22:INIT_OUT	BUFGCTRL22:PRESELECT_I0
40	~BUFGCTRL22:INV.S0	~BUFGCTRL22:INV.CE0
39	~BUFGCTRL25:INV.S1	~BUFGCTRL25:INV.CE1
38	~BUFGCTRL25:CREATE_EDGE	BUFGCTRL25:PRESELECT_I1
37	~BUFGCTRL25:INV.IGNORE1	~BUFGCTRL25:INV.IGNORE0
36	BUFGCTRL25:INIT_OUT	BUFGCTRL25:PRESELECT_I0
35	~BUFGCTRL25:INV.S0	~BUFGCTRL25:INV.CE0
34	~BUFGCTRL24:INV.S1	~BUFGCTRL24:INV.CE1
33	~BUFGCTRL24:CREATE_EDGE	BUFGCTRL24:PRESELECT_I1
32	~BUFGCTRL24:INV.IGNORE1	~BUFGCTRL24:INV.IGNORE0
31	BUFGCTRL24:INIT_OUT	BUFGCTRL24:PRESELECT_I0
30	~BUFGCTRL24:INV.S0	~BUFGCTRL24:INV.CE0
29	~BUFGCTRL27:INV.S1	~BUFGCTRL27:INV.CE1
28	~BUFGCTRL27:CREATE_EDGE	BUFGCTRL27:PRESELECT_I1
27	~BUFGCTRL27:INV.IGNORE1	~BUFGCTRL27:INV.IGNORE0
26	BUFGCTRL27:INIT_OUT	BUFGCTRL27:PRESELECT_I0
25	~BUFGCTRL27:INV.S0	~BUFGCTRL27:INV.CE0
24	~BUFGCTRL26:INV.S1	~BUFGCTRL26:INV.CE1
23	~BUFGCTRL26:CREATE_EDGE	BUFGCTRL26:PRESELECT_I1
22	~BUFGCTRL26:INV.IGNORE1	~BUFGCTRL26:INV.IGNORE0
21	BUFGCTRL26:INIT_OUT	BUFGCTRL26:PRESELECT_I0
20	~BUFGCTRL26:INV.S0	~BUFGCTRL26:INV.CE0
19	~BUFGCTRL29:INV.S1	~BUFGCTRL29:INV.CE1
18	~BUFGCTRL29:CREATE_EDGE	BUFGCTRL29:PRESELECT_I1
17	~BUFGCTRL29:INV.IGNORE1	~BUFGCTRL29:INV.IGNORE0
16	BUFGCTRL29:INIT_OUT	BUFGCTRL29:PRESELECT_I0
15	~BUFGCTRL29:INV.S0	~BUFGCTRL29:INV.CE0
14	~BUFGCTRL28:INV.S1	~BUFGCTRL28:INV.CE1
13	~BUFGCTRL28:CREATE_EDGE	BUFGCTRL28:PRESELECT_I1
12	~BUFGCTRL28:INV.IGNORE1	~BUFGCTRL28:INV.IGNORE0
11	BUFGCTRL28:INIT_OUT	BUFGCTRL28:PRESELECT_I0
10	~BUFGCTRL28:INV.S0	~BUFGCTRL28:INV.CE0
9	~BUFGCTRL31:INV.S1	~BUFGCTRL31:INV.CE1
8	~BUFGCTRL31:CREATE_EDGE	BUFGCTRL31:PRESELECT_I1
7	~BUFGCTRL31:INV.IGNORE1	~BUFGCTRL31:INV.IGNORE0
6	BUFGCTRL31:INIT_OUT	BUFGCTRL31:PRESELECT_I0
5	~BUFGCTRL31:INV.S0	~BUFGCTRL31:INV.CE0
4	~BUFGCTRL30:INV.S1	~BUFGCTRL30:INV.CE1
3	~BUFGCTRL30:CREATE_EDGE	BUFGCTRL30:PRESELECT_I1
2	~BUFGCTRL30:INV.IGNORE1	~BUFGCTRL30:INV.IGNORE0
1	BUFGCTRL30:INIT_OUT	BUFGCTRL30:PRESELECT_I0
0	~BUFGCTRL30:INV.S0	~BUFGCTRL30:INV.CE0

virtex4 CFG bittile 27
Bit	Frame
Bit	0	1
60	-	BUFGCTRL28:IMUX_ENABLE
59	BUFGCTRL28:MUX.I0[5]	BUFGCTRL28:MUX.I1[5]
58	BUFGCTRL28:MUX.I0[4]	BUFGCTRL28:MUX.I1[4]
57	BUFGCTRL28:MUX.I0[3]	BUFGCTRL28:MUX.I1[3]
56	BUFGCTRL28:MUX.I0[2]	BUFGCTRL28:MUX.I1[2]
55	BUFGCTRL28:MUX.I0[1]	BUFGCTRL28:MUX.I1[1]
54	BUFGCTRL28:MUX.I0[0]	BUFGCTRL28:MUX.I1[0]
53	BUFGCTRL28:MUX.I0[10]	BUFGCTRL28:MUX.I1[10]
52	BUFGCTRL28:MUX.I0[9]	BUFGCTRL28:MUX.I1[9]
51	BUFGCTRL28:MUX.I0[8]	BUFGCTRL28:MUX.I1[8]
50	BUFGCTRL28:MUX.I0[7]	BUFGCTRL28:MUX.I1[7]
49	BUFGCTRL28:MUX.I1[6]	BUFGCTRL28:MUX.I0[6]
48	BUFGCTRL28:MUX.I1[11]	BUFGCTRL28:MUX.I0[11]
47	-	-
46	-	-
45	-	-
44	-	BUFGCTRL29:IMUX_ENABLE
43	BUFGCTRL29:MUX.I0[5]	BUFGCTRL29:MUX.I1[5]
42	BUFGCTRL29:MUX.I0[4]	BUFGCTRL29:MUX.I1[4]
41	BUFGCTRL29:MUX.I0[3]	BUFGCTRL29:MUX.I1[3]
40	BUFGCTRL29:MUX.I0[2]	BUFGCTRL29:MUX.I1[2]
39	BUFGCTRL29:MUX.I0[1]	BUFGCTRL29:MUX.I1[1]
38	BUFGCTRL29:MUX.I0[0]	BUFGCTRL29:MUX.I1[0]
37	BUFGCTRL29:MUX.I0[10]	BUFGCTRL29:MUX.I1[10]
36	BUFGCTRL29:MUX.I0[9]	BUFGCTRL29:MUX.I1[9]
35	BUFGCTRL29:MUX.I0[8]	BUFGCTRL29:MUX.I1[8]
34	BUFGCTRL29:MUX.I0[7]	BUFGCTRL29:MUX.I1[7]
33	BUFGCTRL29:MUX.I1[6]	BUFGCTRL29:MUX.I0[6]
32	BUFGCTRL29:MUX.I1[11]	BUFGCTRL29:MUX.I0[11]
31	-	-
30	-	-
29	-	-
28	-	BUFGCTRL30:IMUX_ENABLE
27	BUFGCTRL30:MUX.I0[5]	BUFGCTRL30:MUX.I1[5]
26	BUFGCTRL30:MUX.I0[4]	BUFGCTRL30:MUX.I1[4]
25	BUFGCTRL30:MUX.I0[3]	BUFGCTRL30:MUX.I1[3]
24	BUFGCTRL30:MUX.I0[2]	BUFGCTRL30:MUX.I1[2]
23	BUFGCTRL30:MUX.I0[1]	BUFGCTRL30:MUX.I1[1]
22	BUFGCTRL30:MUX.I0[0]	BUFGCTRL30:MUX.I1[0]
21	BUFGCTRL30:MUX.I0[10]	BUFGCTRL30:MUX.I1[10]
20	BUFGCTRL30:MUX.I0[9]	BUFGCTRL30:MUX.I1[9]
19	BUFGCTRL30:MUX.I0[8]	BUFGCTRL30:MUX.I1[8]
18	BUFGCTRL30:MUX.I0[7]	BUFGCTRL30:MUX.I1[7]
17	BUFGCTRL30:MUX.I1[6]	BUFGCTRL30:MUX.I0[6]
16	BUFGCTRL30:MUX.I1[11]	BUFGCTRL30:MUX.I0[11]
15	-	-
14	-	-
13	-	-
12	-	BUFGCTRL31:IMUX_ENABLE
11	BUFGCTRL31:MUX.I0[5]	BUFGCTRL31:MUX.I1[5]
10	BUFGCTRL31:MUX.I0[4]	BUFGCTRL31:MUX.I1[4]
9	BUFGCTRL31:MUX.I0[3]	BUFGCTRL31:MUX.I1[3]
8	BUFGCTRL31:MUX.I0[2]	BUFGCTRL31:MUX.I1[2]
7	BUFGCTRL31:MUX.I0[1]	BUFGCTRL31:MUX.I1[1]
6	BUFGCTRL31:MUX.I0[0]	BUFGCTRL31:MUX.I1[0]
5	BUFGCTRL31:MUX.I0[10]	BUFGCTRL31:MUX.I1[10]
4	BUFGCTRL31:MUX.I0[9]	BUFGCTRL31:MUX.I1[9]
3	BUFGCTRL31:MUX.I0[8]	BUFGCTRL31:MUX.I1[8]
2	BUFGCTRL31:MUX.I0[7]	BUFGCTRL31:MUX.I1[7]
1	BUFGCTRL31:MUX.I1[6]	BUFGCTRL31:MUX.I0[6]
0	BUFGCTRL31:MUX.I1[11]	BUFGCTRL31:MUX.I0[11]

virtex4 CFG bittile 28
Bit	Frame
Bit	0	1
60	-	BUFGCTRL24:IMUX_ENABLE
59	BUFGCTRL24:MUX.I0[5]	BUFGCTRL24:MUX.I1[5]
58	BUFGCTRL24:MUX.I0[4]	BUFGCTRL24:MUX.I1[4]
57	BUFGCTRL24:MUX.I0[3]	BUFGCTRL24:MUX.I1[3]
56	BUFGCTRL24:MUX.I0[2]	BUFGCTRL24:MUX.I1[2]
55	BUFGCTRL24:MUX.I0[1]	BUFGCTRL24:MUX.I1[1]
54	BUFGCTRL24:MUX.I0[0]	BUFGCTRL24:MUX.I1[0]
53	BUFGCTRL24:MUX.I0[10]	BUFGCTRL24:MUX.I1[10]
52	BUFGCTRL24:MUX.I0[9]	BUFGCTRL24:MUX.I1[9]
51	BUFGCTRL24:MUX.I0[8]	BUFGCTRL24:MUX.I1[8]
50	BUFGCTRL24:MUX.I0[7]	BUFGCTRL24:MUX.I1[7]
49	BUFGCTRL24:MUX.I1[6]	BUFGCTRL24:MUX.I0[6]
48	BUFGCTRL24:MUX.I1[11]	BUFGCTRL24:MUX.I0[11]
47	-	-
46	-	-
45	-	-
44	-	BUFGCTRL25:IMUX_ENABLE
43	BUFGCTRL25:MUX.I0[5]	BUFGCTRL25:MUX.I1[5]
42	BUFGCTRL25:MUX.I0[4]	BUFGCTRL25:MUX.I1[4]
41	BUFGCTRL25:MUX.I0[3]	BUFGCTRL25:MUX.I1[3]
40	BUFGCTRL25:MUX.I0[2]	BUFGCTRL25:MUX.I1[2]
39	BUFGCTRL25:MUX.I0[1]	BUFGCTRL25:MUX.I1[1]
38	BUFGCTRL25:MUX.I0[0]	BUFGCTRL25:MUX.I1[0]
37	BUFGCTRL25:MUX.I0[10]	BUFGCTRL25:MUX.I1[10]
36	BUFGCTRL25:MUX.I0[9]	BUFGCTRL25:MUX.I1[9]
35	BUFGCTRL25:MUX.I0[8]	BUFGCTRL25:MUX.I1[8]
34	BUFGCTRL25:MUX.I0[7]	BUFGCTRL25:MUX.I1[7]
33	BUFGCTRL25:MUX.I1[6]	BUFGCTRL25:MUX.I0[6]
32	BUFGCTRL25:MUX.I1[11]	BUFGCTRL25:MUX.I0[11]
31	-	-
30	-	-
29	-	-
28	-	BUFGCTRL26:IMUX_ENABLE
27	BUFGCTRL26:MUX.I0[5]	BUFGCTRL26:MUX.I1[5]
26	BUFGCTRL26:MUX.I0[4]	BUFGCTRL26:MUX.I1[4]
25	BUFGCTRL26:MUX.I0[3]	BUFGCTRL26:MUX.I1[3]
24	BUFGCTRL26:MUX.I0[2]	BUFGCTRL26:MUX.I1[2]
23	BUFGCTRL26:MUX.I0[1]	BUFGCTRL26:MUX.I1[1]
22	BUFGCTRL26:MUX.I0[0]	BUFGCTRL26:MUX.I1[0]
21	BUFGCTRL26:MUX.I0[10]	BUFGCTRL26:MUX.I1[10]
20	BUFGCTRL26:MUX.I0[9]	BUFGCTRL26:MUX.I1[9]
19	BUFGCTRL26:MUX.I0[8]	BUFGCTRL26:MUX.I1[8]
18	BUFGCTRL26:MUX.I0[7]	BUFGCTRL26:MUX.I1[7]
17	BUFGCTRL26:MUX.I1[6]	BUFGCTRL26:MUX.I0[6]
16	BUFGCTRL26:MUX.I1[11]	BUFGCTRL26:MUX.I0[11]
15	-	-
14	-	-
13	-	-
12	-	BUFGCTRL27:IMUX_ENABLE
11	BUFGCTRL27:MUX.I0[5]	BUFGCTRL27:MUX.I1[5]
10	BUFGCTRL27:MUX.I0[4]	BUFGCTRL27:MUX.I1[4]
9	BUFGCTRL27:MUX.I0[3]	BUFGCTRL27:MUX.I1[3]
8	BUFGCTRL27:MUX.I0[2]	BUFGCTRL27:MUX.I1[2]
7	BUFGCTRL27:MUX.I0[1]	BUFGCTRL27:MUX.I1[1]
6	BUFGCTRL27:MUX.I0[0]	BUFGCTRL27:MUX.I1[0]
5	BUFGCTRL27:MUX.I0[10]	BUFGCTRL27:MUX.I1[10]
4	BUFGCTRL27:MUX.I0[9]	BUFGCTRL27:MUX.I1[9]
3	BUFGCTRL27:MUX.I0[8]	BUFGCTRL27:MUX.I1[8]
2	BUFGCTRL27:MUX.I0[7]	BUFGCTRL27:MUX.I1[7]
1	BUFGCTRL27:MUX.I1[6]	BUFGCTRL27:MUX.I0[6]
0	BUFGCTRL27:MUX.I1[11]	BUFGCTRL27:MUX.I0[11]

virtex4 CFG bittile 29
Bit	Frame
Bit	0	1
60	-	BUFGCTRL20:IMUX_ENABLE
59	BUFGCTRL20:MUX.I0[5]	BUFGCTRL20:MUX.I1[5]
58	BUFGCTRL20:MUX.I0[4]	BUFGCTRL20:MUX.I1[4]
57	BUFGCTRL20:MUX.I0[3]	BUFGCTRL20:MUX.I1[3]
56	BUFGCTRL20:MUX.I0[2]	BUFGCTRL20:MUX.I1[2]
55	BUFGCTRL20:MUX.I0[1]	BUFGCTRL20:MUX.I1[1]
54	BUFGCTRL20:MUX.I0[0]	BUFGCTRL20:MUX.I1[0]
53	BUFGCTRL20:MUX.I0[10]	BUFGCTRL20:MUX.I1[10]
52	BUFGCTRL20:MUX.I0[9]	BUFGCTRL20:MUX.I1[9]
51	BUFGCTRL20:MUX.I0[8]	BUFGCTRL20:MUX.I1[8]
50	BUFGCTRL20:MUX.I0[7]	BUFGCTRL20:MUX.I1[7]
49	BUFGCTRL20:MUX.I1[6]	BUFGCTRL20:MUX.I0[6]
48	BUFGCTRL20:MUX.I1[11]	BUFGCTRL20:MUX.I0[11]
47	-	-
46	-	-
45	-	-
44	-	BUFGCTRL21:IMUX_ENABLE
43	BUFGCTRL21:MUX.I0[5]	BUFGCTRL21:MUX.I1[5]
42	BUFGCTRL21:MUX.I0[4]	BUFGCTRL21:MUX.I1[4]
41	BUFGCTRL21:MUX.I0[3]	BUFGCTRL21:MUX.I1[3]
40	BUFGCTRL21:MUX.I0[2]	BUFGCTRL21:MUX.I1[2]
39	BUFGCTRL21:MUX.I0[1]	BUFGCTRL21:MUX.I1[1]
38	BUFGCTRL21:MUX.I0[0]	BUFGCTRL21:MUX.I1[0]
37	BUFGCTRL21:MUX.I0[10]	BUFGCTRL21:MUX.I1[10]
36	BUFGCTRL21:MUX.I0[9]	BUFGCTRL21:MUX.I1[9]
35	BUFGCTRL21:MUX.I0[8]	BUFGCTRL21:MUX.I1[8]
34	BUFGCTRL21:MUX.I0[7]	BUFGCTRL21:MUX.I1[7]
33	BUFGCTRL21:MUX.I1[6]	BUFGCTRL21:MUX.I0[6]
32	BUFGCTRL21:MUX.I1[11]	BUFGCTRL21:MUX.I0[11]
31	-	-
30	-	-
29	-	-
28	-	BUFGCTRL22:IMUX_ENABLE
27	BUFGCTRL22:MUX.I0[5]	BUFGCTRL22:MUX.I1[5]
26	BUFGCTRL22:MUX.I0[4]	BUFGCTRL22:MUX.I1[4]
25	BUFGCTRL22:MUX.I0[3]	BUFGCTRL22:MUX.I1[3]
24	BUFGCTRL22:MUX.I0[2]	BUFGCTRL22:MUX.I1[2]
23	BUFGCTRL22:MUX.I0[1]	BUFGCTRL22:MUX.I1[1]
22	BUFGCTRL22:MUX.I0[0]	BUFGCTRL22:MUX.I1[0]
21	BUFGCTRL22:MUX.I0[10]	BUFGCTRL22:MUX.I1[10]
20	BUFGCTRL22:MUX.I0[9]	BUFGCTRL22:MUX.I1[9]
19	BUFGCTRL22:MUX.I0[8]	BUFGCTRL22:MUX.I1[8]
18	BUFGCTRL22:MUX.I0[7]	BUFGCTRL22:MUX.I1[7]
17	BUFGCTRL22:MUX.I1[6]	BUFGCTRL22:MUX.I0[6]
16	BUFGCTRL22:MUX.I1[11]	BUFGCTRL22:MUX.I0[11]
15	-	-
14	-	-
13	-	-
12	-	BUFGCTRL23:IMUX_ENABLE
11	BUFGCTRL23:MUX.I0[5]	BUFGCTRL23:MUX.I1[5]
10	BUFGCTRL23:MUX.I0[4]	BUFGCTRL23:MUX.I1[4]
9	BUFGCTRL23:MUX.I0[3]	BUFGCTRL23:MUX.I1[3]
8	BUFGCTRL23:MUX.I0[2]	BUFGCTRL23:MUX.I1[2]
7	BUFGCTRL23:MUX.I0[1]	BUFGCTRL23:MUX.I1[1]
6	BUFGCTRL23:MUX.I0[0]	BUFGCTRL23:MUX.I1[0]
5	BUFGCTRL23:MUX.I0[10]	BUFGCTRL23:MUX.I1[10]
4	BUFGCTRL23:MUX.I0[9]	BUFGCTRL23:MUX.I1[9]
3	BUFGCTRL23:MUX.I0[8]	BUFGCTRL23:MUX.I1[8]
2	BUFGCTRL23:MUX.I0[7]	BUFGCTRL23:MUX.I1[7]
1	BUFGCTRL23:MUX.I1[6]	BUFGCTRL23:MUX.I0[6]
0	BUFGCTRL23:MUX.I1[11]	BUFGCTRL23:MUX.I0[11]

virtex4 CFG bittile 30
Bit	Frame
Bit	0	1
65	BUFG_MGTCLK_N:BUF.MGT_L1	-
64	BUFG_MGTCLK_N:BUF.MGT_L0	-
63	BUFG_MGTCLK_N:BUF.MGT_R1	-
62	BUFG_MGTCLK_N:BUF.MGT_R0	-
61	-	-
60	-	BUFGCTRL16:IMUX_ENABLE
59	BUFGCTRL16:MUX.I0[5]	BUFGCTRL16:MUX.I1[5]
58	BUFGCTRL16:MUX.I0[4]	BUFGCTRL16:MUX.I1[4]
57	BUFGCTRL16:MUX.I0[3]	BUFGCTRL16:MUX.I1[3]
56	BUFGCTRL16:MUX.I0[2]	BUFGCTRL16:MUX.I1[2]
55	BUFGCTRL16:MUX.I0[1]	BUFGCTRL16:MUX.I1[1]
54	BUFGCTRL16:MUX.I0[0]	BUFGCTRL16:MUX.I1[0]
53	BUFGCTRL16:MUX.I0[10]	BUFGCTRL16:MUX.I1[10]
52	BUFGCTRL16:MUX.I0[9]	BUFGCTRL16:MUX.I1[9]
51	BUFGCTRL16:MUX.I0[8]	BUFGCTRL16:MUX.I1[8]
50	BUFGCTRL16:MUX.I0[7]	BUFGCTRL16:MUX.I1[7]
49	BUFGCTRL16:MUX.I1[6]	BUFGCTRL16:MUX.I0[6]
48	BUFGCTRL16:MUX.I1[11]	BUFGCTRL16:MUX.I0[11]
47	-	-
46	-	-
45	-	-
44	-	BUFGCTRL17:IMUX_ENABLE
43	BUFGCTRL17:MUX.I0[5]	BUFGCTRL17:MUX.I1[5]
42	BUFGCTRL17:MUX.I0[4]	BUFGCTRL17:MUX.I1[4]
41	BUFGCTRL17:MUX.I0[3]	BUFGCTRL17:MUX.I1[3]
40	BUFGCTRL17:MUX.I0[2]	BUFGCTRL17:MUX.I1[2]
39	BUFGCTRL17:MUX.I0[1]	BUFGCTRL17:MUX.I1[1]
38	BUFGCTRL17:MUX.I0[0]	BUFGCTRL17:MUX.I1[0]
37	BUFGCTRL17:MUX.I0[10]	BUFGCTRL17:MUX.I1[10]
36	BUFGCTRL17:MUX.I0[9]	BUFGCTRL17:MUX.I1[9]
35	BUFGCTRL17:MUX.I0[8]	BUFGCTRL17:MUX.I1[8]
34	BUFGCTRL17:MUX.I0[7]	BUFGCTRL17:MUX.I1[7]
33	BUFGCTRL17:MUX.I1[6]	BUFGCTRL17:MUX.I0[6]
32	BUFGCTRL17:MUX.I1[11]	BUFGCTRL17:MUX.I0[11]
31	-	-
30	-	-
29	-	-
28	-	BUFGCTRL18:IMUX_ENABLE
27	BUFGCTRL18:MUX.I0[5]	BUFGCTRL18:MUX.I1[5]
26	BUFGCTRL18:MUX.I0[4]	BUFGCTRL18:MUX.I1[4]
25	BUFGCTRL18:MUX.I0[3]	BUFGCTRL18:MUX.I1[3]
24	BUFGCTRL18:MUX.I0[2]	BUFGCTRL18:MUX.I1[2]
23	BUFGCTRL18:MUX.I0[1]	BUFGCTRL18:MUX.I1[1]
22	BUFGCTRL18:MUX.I0[0]	BUFGCTRL18:MUX.I1[0]
21	BUFGCTRL18:MUX.I0[10]	BUFGCTRL18:MUX.I1[10]
20	BUFGCTRL18:MUX.I0[9]	BUFGCTRL18:MUX.I1[9]
19	BUFGCTRL18:MUX.I0[8]	BUFGCTRL18:MUX.I1[8]
18	BUFGCTRL18:MUX.I0[7]	BUFGCTRL18:MUX.I1[7]
17	BUFGCTRL18:MUX.I1[6]	BUFGCTRL18:MUX.I0[6]
16	BUFGCTRL18:MUX.I1[11]	BUFGCTRL18:MUX.I0[11]
15	-	-
14	-	-
13	-	-
12	-	BUFGCTRL19:IMUX_ENABLE
11	BUFGCTRL19:MUX.I0[5]	BUFGCTRL19:MUX.I1[5]
10	BUFGCTRL19:MUX.I0[4]	BUFGCTRL19:MUX.I1[4]
9	BUFGCTRL19:MUX.I0[3]	BUFGCTRL19:MUX.I1[3]
8	BUFGCTRL19:MUX.I0[2]	BUFGCTRL19:MUX.I1[2]
7	BUFGCTRL19:MUX.I0[1]	BUFGCTRL19:MUX.I1[1]
6	BUFGCTRL19:MUX.I0[0]	BUFGCTRL19:MUX.I1[0]
5	BUFGCTRL19:MUX.I0[10]	BUFGCTRL19:MUX.I1[10]
4	BUFGCTRL19:MUX.I0[9]	BUFGCTRL19:MUX.I1[9]
3	BUFGCTRL19:MUX.I0[8]	BUFGCTRL19:MUX.I1[8]
2	BUFGCTRL19:MUX.I0[7]	BUFGCTRL19:MUX.I1[7]
1	BUFGCTRL19:MUX.I1[6]	BUFGCTRL19:MUX.I0[6]
0	BUFGCTRL19:MUX.I1[11]	BUFGCTRL19:MUX.I0[11]

BSCAN0:ENABLE	0.18.5
BSCAN1:ENABLE	5.18.5
BSCAN2:ENABLE	10.18.5
BSCAN3:ENABLE	15.18.5
BUFGCTRL0:IMUX_ENABLE	17.1.19
BUFGCTRL0:INIT_OUT	21.0.8
BUFGCTRL0:PRESELECT_I0	21.1.8
BUFGCTRL0:PRESELECT_I1	21.1.6
BUFGCTRL10:IMUX_ENABLE	19.1.51
BUFGCTRL10:INIT_OUT	21.0.58
BUFGCTRL10:PRESELECT_I0	21.1.58
BUFGCTRL10:PRESELECT_I1	21.1.56
BUFGCTRL11:IMUX_ENABLE	19.1.67
BUFGCTRL11:INIT_OUT	21.0.53
BUFGCTRL11:PRESELECT_I0	21.1.53
BUFGCTRL11:PRESELECT_I1	21.1.51
BUFGCTRL12:IMUX_ENABLE	20.1.19
BUFGCTRL12:INIT_OUT	21.0.68
BUFGCTRL12:PRESELECT_I0	21.1.68
BUFGCTRL12:PRESELECT_I1	21.1.66
BUFGCTRL13:IMUX_ENABLE	20.1.35
BUFGCTRL13:INIT_OUT	21.0.63
BUFGCTRL13:PRESELECT_I0	21.1.63
BUFGCTRL13:PRESELECT_I1	21.1.61
BUFGCTRL14:IMUX_ENABLE	20.1.51
BUFGCTRL14:INIT_OUT	21.0.78
BUFGCTRL14:PRESELECT_I0	21.1.78
BUFGCTRL14:PRESELECT_I1	21.1.76
BUFGCTRL15:IMUX_ENABLE	20.1.67
BUFGCTRL15:INIT_OUT	21.0.73
BUFGCTRL15:PRESELECT_I0	21.1.73
BUFGCTRL15:PRESELECT_I1	21.1.71
BUFGCTRL16:IMUX_ENABLE	30.1.60
BUFGCTRL16:INIT_OUT	26.0.71
BUFGCTRL16:PRESELECT_I0	26.1.71
BUFGCTRL16:PRESELECT_I1	26.1.73
BUFGCTRL17:IMUX_ENABLE	30.1.44
BUFGCTRL17:INIT_OUT	26.0.76
BUFGCTRL17:PRESELECT_I0	26.1.76
BUFGCTRL17:PRESELECT_I1	26.1.78
BUFGCTRL18:IMUX_ENABLE	30.1.28
BUFGCTRL18:INIT_OUT	26.0.61
BUFGCTRL18:PRESELECT_I0	26.1.61
BUFGCTRL18:PRESELECT_I1	26.1.63
BUFGCTRL19:IMUX_ENABLE	30.1.12
BUFGCTRL19:INIT_OUT	26.0.66
BUFGCTRL19:PRESELECT_I0	26.1.66
BUFGCTRL19:PRESELECT_I1	26.1.68
BUFGCTRL1:IMUX_ENABLE	17.1.35
BUFGCTRL1:INIT_OUT	21.0.3
BUFGCTRL1:PRESELECT_I0	21.1.3
BUFGCTRL1:PRESELECT_I1	21.1.1
BUFGCTRL20:IMUX_ENABLE	29.1.60
BUFGCTRL20:INIT_OUT	26.0.51
BUFGCTRL20:PRESELECT_I0	26.1.51
BUFGCTRL20:PRESELECT_I1	26.1.53
BUFGCTRL21:IMUX_ENABLE	29.1.44
BUFGCTRL21:INIT_OUT	26.0.56
BUFGCTRL21:PRESELECT_I0	26.1.56
BUFGCTRL21:PRESELECT_I1	26.1.58
BUFGCTRL22:IMUX_ENABLE	29.1.28
BUFGCTRL22:INIT_OUT	26.0.41
BUFGCTRL22:PRESELECT_I0	26.1.41
BUFGCTRL22:PRESELECT_I1	26.1.43
BUFGCTRL23:IMUX_ENABLE	29.1.12
BUFGCTRL23:INIT_OUT	26.0.46
BUFGCTRL23:PRESELECT_I0	26.1.46
BUFGCTRL23:PRESELECT_I1	26.1.48
BUFGCTRL24:IMUX_ENABLE	28.1.60
BUFGCTRL24:INIT_OUT	26.0.31
BUFGCTRL24:PRESELECT_I0	26.1.31
BUFGCTRL24:PRESELECT_I1	26.1.33
BUFGCTRL25:IMUX_ENABLE	28.1.44
BUFGCTRL25:INIT_OUT	26.0.36
BUFGCTRL25:PRESELECT_I0	26.1.36
BUFGCTRL25:PRESELECT_I1	26.1.38
BUFGCTRL26:IMUX_ENABLE	28.1.28
BUFGCTRL26:INIT_OUT	26.0.21
BUFGCTRL26:PRESELECT_I0	26.1.21
BUFGCTRL26:PRESELECT_I1	26.1.23
BUFGCTRL27:IMUX_ENABLE	28.1.12
BUFGCTRL27:INIT_OUT	26.0.26
BUFGCTRL27:PRESELECT_I0	26.1.26
BUFGCTRL27:PRESELECT_I1	26.1.28
BUFGCTRL28:IMUX_ENABLE	27.1.60
BUFGCTRL28:INIT_OUT	26.0.11
BUFGCTRL28:PRESELECT_I0	26.1.11
BUFGCTRL28:PRESELECT_I1	26.1.13
BUFGCTRL29:IMUX_ENABLE	27.1.44
BUFGCTRL29:INIT_OUT	26.0.16
BUFGCTRL29:PRESELECT_I0	26.1.16
BUFGCTRL29:PRESELECT_I1	26.1.18
BUFGCTRL2:IMUX_ENABLE	17.1.51
BUFGCTRL2:INIT_OUT	21.0.18
BUFGCTRL2:PRESELECT_I0	21.1.18
BUFGCTRL2:PRESELECT_I1	21.1.16
BUFGCTRL30:IMUX_ENABLE	27.1.28
BUFGCTRL30:INIT_OUT	26.0.1
BUFGCTRL30:PRESELECT_I0	26.1.1
BUFGCTRL30:PRESELECT_I1	26.1.3
BUFGCTRL31:IMUX_ENABLE	27.1.12
BUFGCTRL31:INIT_OUT	26.0.6
BUFGCTRL31:PRESELECT_I0	26.1.6
BUFGCTRL31:PRESELECT_I1	26.1.8
BUFGCTRL3:IMUX_ENABLE	17.1.67
BUFGCTRL3:INIT_OUT	21.0.13
BUFGCTRL3:PRESELECT_I0	21.1.13
BUFGCTRL3:PRESELECT_I1	21.1.11
BUFGCTRL4:IMUX_ENABLE	18.1.19
BUFGCTRL4:INIT_OUT	21.0.28
BUFGCTRL4:PRESELECT_I0	21.1.28
BUFGCTRL4:PRESELECT_I1	21.1.26
BUFGCTRL5:IMUX_ENABLE	18.1.35
BUFGCTRL5:INIT_OUT	21.0.23
BUFGCTRL5:PRESELECT_I0	21.1.23
BUFGCTRL5:PRESELECT_I1	21.1.21
BUFGCTRL6:IMUX_ENABLE	18.1.51
BUFGCTRL6:INIT_OUT	21.0.38
BUFGCTRL6:PRESELECT_I0	21.1.38
BUFGCTRL6:PRESELECT_I1	21.1.36
BUFGCTRL7:IMUX_ENABLE	18.1.67
BUFGCTRL7:INIT_OUT	21.0.33
BUFGCTRL7:PRESELECT_I0	21.1.33
BUFGCTRL7:PRESELECT_I1	21.1.31
BUFGCTRL8:IMUX_ENABLE	19.1.19
BUFGCTRL8:INIT_OUT	21.0.48
BUFGCTRL8:PRESELECT_I0	21.1.48
BUFGCTRL8:PRESELECT_I1	21.1.46
BUFGCTRL9:IMUX_ENABLE	19.1.35
BUFGCTRL9:INIT_OUT	21.0.43
BUFGCTRL9:PRESELECT_I0	21.1.43
BUFGCTRL9:PRESELECT_I1	21.1.41
BUFG_MGTCLK_N:BUF.MGT_L0	30.0.64
BUFG_MGTCLK_N:BUF.MGT_L1	30.0.65
BUFG_MGTCLK_N:BUF.MGT_R0	30.0.62
BUFG_MGTCLK_N:BUF.MGT_R1	30.0.63
BUFG_MGTCLK_S:BUF.MGT_L0	17.0.15
BUFG_MGTCLK_S:BUF.MGT_L1	17.0.14
BUFG_MGTCLK_S:BUF.MGT_R0	17.0.17
BUFG_MGTCLK_S:BUF.MGT_R1	17.0.16
DCIRESET:ENABLE	10.18.8
ICAP0:ENABLE	7.18.68
ICAP1:ENABLE	8.18.68
JTAGPPC:ENABLE	7.18.72
STARTUP:GSR_SYNC	8.18.72
STARTUP:GTS_GSR_ENABLE	0.18.8
STARTUP:GTS_SYNC	7.18.79
STARTUP:GWE_SYNC	8.18.70
STARTUP:USRCCLK_ENABLE	6.18.5
non-inverted	[0]

BSCAN_COMMON:USERID	8.18.67	8.18.65	8.18.46	8.18.45	8.18.44	8.18.41	8.18.38	8.18.37	8.18.35	8.18.34	8.18.14	8.18.12	8.18.11	8.18.9	8.18.8	8.18.5	7.18.67	7.18.65	7.18.46	7.18.45	7.18.44	7.18.41	7.18.38	7.18.37	7.18.35	7.18.34	7.18.14	7.18.12	7.18.11	7.18.9	7.18.8	7.18.5
inverted	~[31]	~[30]	~[29]	~[28]	~[27]	~[26]	~[25]	~[24]	~[23]	~[22]	~[21]	~[20]	~[19]	~[18]	~[17]	~[16]	~[15]	~[14]	~[13]	~[12]	~[11]	~[10]	~[9]	~[8]	~[7]	~[6]	~[5]	~[4]	~[3]	~[2]	~[1]	~[0]

BUFGCTRL0:CREATE_EDGE	21.0.6
BUFGCTRL0:INV.CE0	21.1.9
BUFGCTRL0:INV.CE1	21.1.5
BUFGCTRL0:INV.IGNORE0	21.1.7
BUFGCTRL0:INV.IGNORE1	21.0.7
BUFGCTRL0:INV.S0	21.0.9
BUFGCTRL0:INV.S1	21.0.5
BUFGCTRL10:CREATE_EDGE	21.0.56
BUFGCTRL10:INV.CE0	21.1.59
BUFGCTRL10:INV.CE1	21.1.55
BUFGCTRL10:INV.IGNORE0	21.1.57
BUFGCTRL10:INV.IGNORE1	21.0.57
BUFGCTRL10:INV.S0	21.0.59
BUFGCTRL10:INV.S1	21.0.55
BUFGCTRL11:CREATE_EDGE	21.0.51
BUFGCTRL11:INV.CE0	21.1.54
BUFGCTRL11:INV.CE1	21.1.50
BUFGCTRL11:INV.IGNORE0	21.1.52
BUFGCTRL11:INV.IGNORE1	21.0.52
BUFGCTRL11:INV.S0	21.0.54
BUFGCTRL11:INV.S1	21.0.50
BUFGCTRL12:CREATE_EDGE	21.0.66
BUFGCTRL12:INV.CE0	21.1.69
BUFGCTRL12:INV.CE1	21.1.65
BUFGCTRL12:INV.IGNORE0	21.1.67
BUFGCTRL12:INV.IGNORE1	21.0.67
BUFGCTRL12:INV.S0	21.0.69
BUFGCTRL12:INV.S1	21.0.65
BUFGCTRL13:CREATE_EDGE	21.0.61
BUFGCTRL13:INV.CE0	21.1.64
BUFGCTRL13:INV.CE1	21.1.60
BUFGCTRL13:INV.IGNORE0	21.1.62
BUFGCTRL13:INV.IGNORE1	21.0.62
BUFGCTRL13:INV.S0	21.0.64
BUFGCTRL13:INV.S1	21.0.60
BUFGCTRL14:CREATE_EDGE	21.0.76
BUFGCTRL14:INV.CE0	21.1.79
BUFGCTRL14:INV.CE1	21.1.75
BUFGCTRL14:INV.IGNORE0	21.1.77
BUFGCTRL14:INV.IGNORE1	21.0.77
BUFGCTRL14:INV.S0	21.0.79
BUFGCTRL14:INV.S1	21.0.75
BUFGCTRL15:CREATE_EDGE	21.0.71
BUFGCTRL15:INV.CE0	21.1.74
BUFGCTRL15:INV.CE1	21.1.70
BUFGCTRL15:INV.IGNORE0	21.1.72
BUFGCTRL15:INV.IGNORE1	21.0.72
BUFGCTRL15:INV.S0	21.0.74
BUFGCTRL15:INV.S1	21.0.70
BUFGCTRL16:CREATE_EDGE	26.0.73
BUFGCTRL16:INV.CE0	26.1.70
BUFGCTRL16:INV.CE1	26.1.74
BUFGCTRL16:INV.IGNORE0	26.1.72
BUFGCTRL16:INV.IGNORE1	26.0.72
BUFGCTRL16:INV.S0	26.0.70
BUFGCTRL16:INV.S1	26.0.74
BUFGCTRL17:CREATE_EDGE	26.0.78
BUFGCTRL17:INV.CE0	26.1.75
BUFGCTRL17:INV.CE1	26.1.79
BUFGCTRL17:INV.IGNORE0	26.1.77
BUFGCTRL17:INV.IGNORE1	26.0.77
BUFGCTRL17:INV.S0	26.0.75
BUFGCTRL17:INV.S1	26.0.79
BUFGCTRL18:CREATE_EDGE	26.0.63
BUFGCTRL18:INV.CE0	26.1.60
BUFGCTRL18:INV.CE1	26.1.64
BUFGCTRL18:INV.IGNORE0	26.1.62
BUFGCTRL18:INV.IGNORE1	26.0.62
BUFGCTRL18:INV.S0	26.0.60
BUFGCTRL18:INV.S1	26.0.64
BUFGCTRL19:CREATE_EDGE	26.0.68
BUFGCTRL19:INV.CE0	26.1.65
BUFGCTRL19:INV.CE1	26.1.69
BUFGCTRL19:INV.IGNORE0	26.1.67
BUFGCTRL19:INV.IGNORE1	26.0.67
BUFGCTRL19:INV.S0	26.0.65
BUFGCTRL19:INV.S1	26.0.69
BUFGCTRL1:CREATE_EDGE	21.0.1
BUFGCTRL1:INV.CE0	21.1.4
BUFGCTRL1:INV.CE1	21.1.0
BUFGCTRL1:INV.IGNORE0	21.1.2
BUFGCTRL1:INV.IGNORE1	21.0.2
BUFGCTRL1:INV.S0	21.0.4
BUFGCTRL1:INV.S1	21.0.0
BUFGCTRL20:CREATE_EDGE	26.0.53
BUFGCTRL20:INV.CE0	26.1.50
BUFGCTRL20:INV.CE1	26.1.54
BUFGCTRL20:INV.IGNORE0	26.1.52
BUFGCTRL20:INV.IGNORE1	26.0.52
BUFGCTRL20:INV.S0	26.0.50
BUFGCTRL20:INV.S1	26.0.54
BUFGCTRL21:CREATE_EDGE	26.0.58
BUFGCTRL21:INV.CE0	26.1.55
BUFGCTRL21:INV.CE1	26.1.59
BUFGCTRL21:INV.IGNORE0	26.1.57
BUFGCTRL21:INV.IGNORE1	26.0.57
BUFGCTRL21:INV.S0	26.0.55
BUFGCTRL21:INV.S1	26.0.59
BUFGCTRL22:CREATE_EDGE	26.0.43
BUFGCTRL22:INV.CE0	26.1.40
BUFGCTRL22:INV.CE1	26.1.44
BUFGCTRL22:INV.IGNORE0	26.1.42
BUFGCTRL22:INV.IGNORE1	26.0.42
BUFGCTRL22:INV.S0	26.0.40
BUFGCTRL22:INV.S1	26.0.44
BUFGCTRL23:CREATE_EDGE	26.0.48
BUFGCTRL23:INV.CE0	26.1.45
BUFGCTRL23:INV.CE1	26.1.49
BUFGCTRL23:INV.IGNORE0	26.1.47
BUFGCTRL23:INV.IGNORE1	26.0.47
BUFGCTRL23:INV.S0	26.0.45
BUFGCTRL23:INV.S1	26.0.49
BUFGCTRL24:CREATE_EDGE	26.0.33
BUFGCTRL24:INV.CE0	26.1.30
BUFGCTRL24:INV.CE1	26.1.34
BUFGCTRL24:INV.IGNORE0	26.1.32
BUFGCTRL24:INV.IGNORE1	26.0.32
BUFGCTRL24:INV.S0	26.0.30
BUFGCTRL24:INV.S1	26.0.34
BUFGCTRL25:CREATE_EDGE	26.0.38
BUFGCTRL25:INV.CE0	26.1.35
BUFGCTRL25:INV.CE1	26.1.39
BUFGCTRL25:INV.IGNORE0	26.1.37
BUFGCTRL25:INV.IGNORE1	26.0.37
BUFGCTRL25:INV.S0	26.0.35
BUFGCTRL25:INV.S1	26.0.39
BUFGCTRL26:CREATE_EDGE	26.0.23
BUFGCTRL26:INV.CE0	26.1.20
BUFGCTRL26:INV.CE1	26.1.24
BUFGCTRL26:INV.IGNORE0	26.1.22
BUFGCTRL26:INV.IGNORE1	26.0.22
BUFGCTRL26:INV.S0	26.0.20
BUFGCTRL26:INV.S1	26.0.24
BUFGCTRL27:CREATE_EDGE	26.0.28
BUFGCTRL27:INV.CE0	26.1.25
BUFGCTRL27:INV.CE1	26.1.29
BUFGCTRL27:INV.IGNORE0	26.1.27
BUFGCTRL27:INV.IGNORE1	26.0.27
BUFGCTRL27:INV.S0	26.0.25
BUFGCTRL27:INV.S1	26.0.29
BUFGCTRL28:CREATE_EDGE	26.0.13
BUFGCTRL28:INV.CE0	26.1.10
BUFGCTRL28:INV.CE1	26.1.14
BUFGCTRL28:INV.IGNORE0	26.1.12
BUFGCTRL28:INV.IGNORE1	26.0.12
BUFGCTRL28:INV.S0	26.0.10
BUFGCTRL28:INV.S1	26.0.14
BUFGCTRL29:CREATE_EDGE	26.0.18
BUFGCTRL29:INV.CE0	26.1.15
BUFGCTRL29:INV.CE1	26.1.19
BUFGCTRL29:INV.IGNORE0	26.1.17
BUFGCTRL29:INV.IGNORE1	26.0.17
BUFGCTRL29:INV.S0	26.0.15
BUFGCTRL29:INV.S1	26.0.19
BUFGCTRL2:CREATE_EDGE	21.0.16
BUFGCTRL2:INV.CE0	21.1.19
BUFGCTRL2:INV.CE1	21.1.15
BUFGCTRL2:INV.IGNORE0	21.1.17
BUFGCTRL2:INV.IGNORE1	21.0.17
BUFGCTRL2:INV.S0	21.0.19
BUFGCTRL2:INV.S1	21.0.15
BUFGCTRL30:CREATE_EDGE	26.0.3
BUFGCTRL30:INV.CE0	26.1.0
BUFGCTRL30:INV.CE1	26.1.4
BUFGCTRL30:INV.IGNORE0	26.1.2
BUFGCTRL30:INV.IGNORE1	26.0.2
BUFGCTRL30:INV.S0	26.0.0
BUFGCTRL30:INV.S1	26.0.4
BUFGCTRL31:CREATE_EDGE	26.0.8
BUFGCTRL31:INV.CE0	26.1.5
BUFGCTRL31:INV.CE1	26.1.9
BUFGCTRL31:INV.IGNORE0	26.1.7
BUFGCTRL31:INV.IGNORE1	26.0.7
BUFGCTRL31:INV.S0	26.0.5
BUFGCTRL31:INV.S1	26.0.9
BUFGCTRL3:CREATE_EDGE	21.0.11
BUFGCTRL3:INV.CE0	21.1.14
BUFGCTRL3:INV.CE1	21.1.10
BUFGCTRL3:INV.IGNORE0	21.1.12
BUFGCTRL3:INV.IGNORE1	21.0.12
BUFGCTRL3:INV.S0	21.0.14
BUFGCTRL3:INV.S1	21.0.10
BUFGCTRL4:CREATE_EDGE	21.0.26
BUFGCTRL4:INV.CE0	21.1.29
BUFGCTRL4:INV.CE1	21.1.25
BUFGCTRL4:INV.IGNORE0	21.1.27
BUFGCTRL4:INV.IGNORE1	21.0.27
BUFGCTRL4:INV.S0	21.0.29
BUFGCTRL4:INV.S1	21.0.25
BUFGCTRL5:CREATE_EDGE	21.0.21
BUFGCTRL5:INV.CE0	21.1.24
BUFGCTRL5:INV.CE1	21.1.20
BUFGCTRL5:INV.IGNORE0	21.1.22
BUFGCTRL5:INV.IGNORE1	21.0.22
BUFGCTRL5:INV.S0	21.0.24
BUFGCTRL5:INV.S1	21.0.20
BUFGCTRL6:CREATE_EDGE	21.0.36
BUFGCTRL6:INV.CE0	21.1.39
BUFGCTRL6:INV.CE1	21.1.35
BUFGCTRL6:INV.IGNORE0	21.1.37
BUFGCTRL6:INV.IGNORE1	21.0.37
BUFGCTRL6:INV.S0	21.0.39
BUFGCTRL6:INV.S1	21.0.35
BUFGCTRL7:CREATE_EDGE	21.0.31
BUFGCTRL7:INV.CE0	21.1.34
BUFGCTRL7:INV.CE1	21.1.30
BUFGCTRL7:INV.IGNORE0	21.1.32
BUFGCTRL7:INV.IGNORE1	21.0.32
BUFGCTRL7:INV.S0	21.0.34
BUFGCTRL7:INV.S1	21.0.30
BUFGCTRL8:CREATE_EDGE	21.0.46
BUFGCTRL8:INV.CE0	21.1.49
BUFGCTRL8:INV.CE1	21.1.45
BUFGCTRL8:INV.IGNORE0	21.1.47
BUFGCTRL8:INV.IGNORE1	21.0.47
BUFGCTRL8:INV.S0	21.0.49
BUFGCTRL8:INV.S1	21.0.45
BUFGCTRL9:CREATE_EDGE	21.0.41
BUFGCTRL9:INV.CE0	21.1.44
BUFGCTRL9:INV.CE1	21.1.40
BUFGCTRL9:INV.IGNORE0	21.1.42
BUFGCTRL9:INV.IGNORE1	21.0.42
BUFGCTRL9:INV.S0	21.0.44
BUFGCTRL9:INV.S1	21.0.40
inverted	~[0]

BUFGCTRL0:ENABLE	22.1.9	22.1.8	22.1.7	22.1.6	22.0.7
BUFGCTRL10:ENABLE	23.1.29	23.1.28	23.1.27	23.1.26	23.0.27
BUFGCTRL11:ENABLE	23.1.39	23.1.38	23.1.37	23.1.36	23.0.37
BUFGCTRL12:ENABLE	23.1.49	23.1.48	23.1.47	23.1.46	23.0.47
BUFGCTRL13:ENABLE	23.1.59	23.1.58	23.1.57	23.1.56	23.0.57
BUFGCTRL14:ENABLE	23.1.69	23.1.68	23.1.67	23.1.66	23.0.67
BUFGCTRL15:ENABLE	23.1.79	23.1.78	23.1.77	23.1.76	23.0.77
BUFGCTRL16:ENABLE	25.1.73	25.1.72	25.1.71	25.1.70	25.0.72
BUFGCTRL17:ENABLE	25.1.63	25.1.62	25.1.61	25.1.60	25.0.62
BUFGCTRL18:ENABLE	25.1.53	25.1.52	25.1.51	25.1.50	25.0.52
BUFGCTRL19:ENABLE	25.1.43	25.1.42	25.1.41	25.1.40	25.0.42
BUFGCTRL1:ENABLE	22.1.19	22.1.18	22.1.17	22.1.16	22.0.17
BUFGCTRL20:ENABLE	25.1.33	25.1.32	25.1.31	25.1.30	25.0.32
BUFGCTRL21:ENABLE	25.1.23	25.1.22	25.1.21	25.1.20	25.0.22
BUFGCTRL22:ENABLE	25.1.13	25.1.12	25.1.11	25.1.10	25.0.12
BUFGCTRL23:ENABLE	25.1.3	25.1.2	25.1.1	25.1.0	25.0.2
BUFGCTRL24:ENABLE	24.1.73	24.1.72	24.1.71	24.1.70	24.0.72
BUFGCTRL25:ENABLE	24.1.63	24.1.62	24.1.61	24.1.60	24.0.62
BUFGCTRL26:ENABLE	24.1.53	24.1.52	24.1.51	24.1.50	24.0.52
BUFGCTRL27:ENABLE	24.1.43	24.1.42	24.1.41	24.1.40	24.0.42
BUFGCTRL28:ENABLE	24.1.33	24.1.32	24.1.31	24.1.30	24.0.32
BUFGCTRL29:ENABLE	24.1.23	24.1.22	24.1.21	24.1.20	24.0.22
BUFGCTRL2:ENABLE	22.1.29	22.1.28	22.1.27	22.1.26	22.0.27
BUFGCTRL30:ENABLE	24.1.13	24.1.12	24.1.11	24.1.10	24.0.12
BUFGCTRL31:ENABLE	24.1.3	24.1.2	24.1.1	24.1.0	24.0.2
BUFGCTRL3:ENABLE	22.1.39	22.1.38	22.1.37	22.1.36	22.0.37
BUFGCTRL4:ENABLE	22.1.49	22.1.48	22.1.47	22.1.46	22.0.47
BUFGCTRL5:ENABLE	22.1.59	22.1.58	22.1.57	22.1.56	22.0.57
BUFGCTRL6:ENABLE	22.1.69	22.1.68	22.1.67	22.1.66	22.0.67
BUFGCTRL7:ENABLE	22.1.79	22.1.78	22.1.77	22.1.76	22.0.77
BUFGCTRL8:ENABLE	23.1.9	23.1.8	23.1.7	23.1.6	23.0.7
BUFGCTRL9:ENABLE	23.1.19	23.1.18	23.1.17	23.1.16	23.0.17
non-inverted	[4]	[3]	[2]	[1]	[0]

BUFGCTRL0:MUX.I0	17.1.30	17.0.26	17.0.27	17.0.28	17.0.29	17.1.31	17.0.20	17.0.21	17.0.22	17.0.23	17.0.24	17.0.25
BUFGCTRL0:MUX.I1	17.0.30	17.1.26	17.1.27	17.1.28	17.1.29	17.0.31	17.1.20	17.1.21	17.1.22	17.1.23	17.1.24	17.1.25
BUFGCTRL10:MUX.I0	19.1.62	19.0.58	19.0.59	19.0.60	19.0.61	19.1.63	19.0.52	19.0.53	19.0.54	19.0.55	19.0.56	19.0.57
BUFGCTRL10:MUX.I1	19.0.62	19.1.58	19.1.59	19.1.60	19.1.61	19.0.63	19.1.52	19.1.53	19.1.54	19.1.55	19.1.56	19.1.57
BUFGCTRL11:MUX.I0	19.1.78	19.0.74	19.0.75	19.0.76	19.0.77	19.1.79	19.0.68	19.0.69	19.0.70	19.0.71	19.0.72	19.0.73
BUFGCTRL11:MUX.I1	19.0.78	19.1.74	19.1.75	19.1.76	19.1.77	19.0.79	19.1.68	19.1.69	19.1.70	19.1.71	19.1.72	19.1.73
BUFGCTRL12:MUX.I0	20.1.30	20.0.26	20.0.27	20.0.28	20.0.29	20.1.31	20.0.20	20.0.21	20.0.22	20.0.23	20.0.24	20.0.25
BUFGCTRL12:MUX.I1	20.0.30	20.1.26	20.1.27	20.1.28	20.1.29	20.0.31	20.1.20	20.1.21	20.1.22	20.1.23	20.1.24	20.1.25
BUFGCTRL13:MUX.I0	20.1.46	20.0.42	20.0.43	20.0.44	20.0.45	20.1.47	20.0.36	20.0.37	20.0.38	20.0.39	20.0.40	20.0.41
BUFGCTRL13:MUX.I1	20.0.46	20.1.42	20.1.43	20.1.44	20.1.45	20.0.47	20.1.36	20.1.37	20.1.38	20.1.39	20.1.40	20.1.41
BUFGCTRL14:MUX.I0	20.1.62	20.0.58	20.0.59	20.0.60	20.0.61	20.1.63	20.0.52	20.0.53	20.0.54	20.0.55	20.0.56	20.0.57
BUFGCTRL14:MUX.I1	20.0.62	20.1.58	20.1.59	20.1.60	20.1.61	20.0.63	20.1.52	20.1.53	20.1.54	20.1.55	20.1.56	20.1.57
BUFGCTRL15:MUX.I0	20.1.78	20.0.74	20.0.75	20.0.76	20.0.77	20.1.79	20.0.68	20.0.69	20.0.70	20.0.71	20.0.72	20.0.73
BUFGCTRL15:MUX.I1	20.0.78	20.1.74	20.1.75	20.1.76	20.1.77	20.0.79	20.1.68	20.1.69	20.1.70	20.1.71	20.1.72	20.1.73
BUFGCTRL16:MUX.I0	30.1.48	30.0.53	30.0.52	30.0.51	30.0.50	30.1.49	30.0.59	30.0.58	30.0.57	30.0.56	30.0.55	30.0.54
BUFGCTRL16:MUX.I1	30.0.48	30.1.53	30.1.52	30.1.51	30.1.50	30.0.49	30.1.59	30.1.58	30.1.57	30.1.56	30.1.55	30.1.54
BUFGCTRL17:MUX.I0	30.1.32	30.0.37	30.0.36	30.0.35	30.0.34	30.1.33	30.0.43	30.0.42	30.0.41	30.0.40	30.0.39	30.0.38
BUFGCTRL17:MUX.I1	30.0.32	30.1.37	30.1.36	30.1.35	30.1.34	30.0.33	30.1.43	30.1.42	30.1.41	30.1.40	30.1.39	30.1.38
BUFGCTRL18:MUX.I0	30.1.16	30.0.21	30.0.20	30.0.19	30.0.18	30.1.17	30.0.27	30.0.26	30.0.25	30.0.24	30.0.23	30.0.22
BUFGCTRL18:MUX.I1	30.0.16	30.1.21	30.1.20	30.1.19	30.1.18	30.0.17	30.1.27	30.1.26	30.1.25	30.1.24	30.1.23	30.1.22
BUFGCTRL19:MUX.I0	30.1.0	30.0.5	30.0.4	30.0.3	30.0.2	30.1.1	30.0.11	30.0.10	30.0.9	30.0.8	30.0.7	30.0.6
BUFGCTRL19:MUX.I1	30.0.0	30.1.5	30.1.4	30.1.3	30.1.2	30.0.1	30.1.11	30.1.10	30.1.9	30.1.8	30.1.7	30.1.6
BUFGCTRL1:MUX.I0	17.1.46	17.0.42	17.0.43	17.0.44	17.0.45	17.1.47	17.0.36	17.0.37	17.0.38	17.0.39	17.0.40	17.0.41
BUFGCTRL1:MUX.I1	17.0.46	17.1.42	17.1.43	17.1.44	17.1.45	17.0.47	17.1.36	17.1.37	17.1.38	17.1.39	17.1.40	17.1.41
BUFGCTRL20:MUX.I0	29.1.48	29.0.53	29.0.52	29.0.51	29.0.50	29.1.49	29.0.59	29.0.58	29.0.57	29.0.56	29.0.55	29.0.54
BUFGCTRL20:MUX.I1	29.0.48	29.1.53	29.1.52	29.1.51	29.1.50	29.0.49	29.1.59	29.1.58	29.1.57	29.1.56	29.1.55	29.1.54
BUFGCTRL21:MUX.I0	29.1.32	29.0.37	29.0.36	29.0.35	29.0.34	29.1.33	29.0.43	29.0.42	29.0.41	29.0.40	29.0.39	29.0.38
BUFGCTRL21:MUX.I1	29.0.32	29.1.37	29.1.36	29.1.35	29.1.34	29.0.33	29.1.43	29.1.42	29.1.41	29.1.40	29.1.39	29.1.38
BUFGCTRL22:MUX.I0	29.1.16	29.0.21	29.0.20	29.0.19	29.0.18	29.1.17	29.0.27	29.0.26	29.0.25	29.0.24	29.0.23	29.0.22
BUFGCTRL22:MUX.I1	29.0.16	29.1.21	29.1.20	29.1.19	29.1.18	29.0.17	29.1.27	29.1.26	29.1.25	29.1.24	29.1.23	29.1.22
BUFGCTRL23:MUX.I0	29.1.0	29.0.5	29.0.4	29.0.3	29.0.2	29.1.1	29.0.11	29.0.10	29.0.9	29.0.8	29.0.7	29.0.6
BUFGCTRL23:MUX.I1	29.0.0	29.1.5	29.1.4	29.1.3	29.1.2	29.0.1	29.1.11	29.1.10	29.1.9	29.1.8	29.1.7	29.1.6
BUFGCTRL24:MUX.I0	28.1.48	28.0.53	28.0.52	28.0.51	28.0.50	28.1.49	28.0.59	28.0.58	28.0.57	28.0.56	28.0.55	28.0.54
BUFGCTRL24:MUX.I1	28.0.48	28.1.53	28.1.52	28.1.51	28.1.50	28.0.49	28.1.59	28.1.58	28.1.57	28.1.56	28.1.55	28.1.54
BUFGCTRL25:MUX.I0	28.1.32	28.0.37	28.0.36	28.0.35	28.0.34	28.1.33	28.0.43	28.0.42	28.0.41	28.0.40	28.0.39	28.0.38
BUFGCTRL25:MUX.I1	28.0.32	28.1.37	28.1.36	28.1.35	28.1.34	28.0.33	28.1.43	28.1.42	28.1.41	28.1.40	28.1.39	28.1.38
BUFGCTRL26:MUX.I0	28.1.16	28.0.21	28.0.20	28.0.19	28.0.18	28.1.17	28.0.27	28.0.26	28.0.25	28.0.24	28.0.23	28.0.22
BUFGCTRL26:MUX.I1	28.0.16	28.1.21	28.1.20	28.1.19	28.1.18	28.0.17	28.1.27	28.1.26	28.1.25	28.1.24	28.1.23	28.1.22
BUFGCTRL27:MUX.I0	28.1.0	28.0.5	28.0.4	28.0.3	28.0.2	28.1.1	28.0.11	28.0.10	28.0.9	28.0.8	28.0.7	28.0.6
BUFGCTRL27:MUX.I1	28.0.0	28.1.5	28.1.4	28.1.3	28.1.2	28.0.1	28.1.11	28.1.10	28.1.9	28.1.8	28.1.7	28.1.6
BUFGCTRL28:MUX.I0	27.1.48	27.0.53	27.0.52	27.0.51	27.0.50	27.1.49	27.0.59	27.0.58	27.0.57	27.0.56	27.0.55	27.0.54
BUFGCTRL28:MUX.I1	27.0.48	27.1.53	27.1.52	27.1.51	27.1.50	27.0.49	27.1.59	27.1.58	27.1.57	27.1.56	27.1.55	27.1.54
BUFGCTRL29:MUX.I0	27.1.32	27.0.37	27.0.36	27.0.35	27.0.34	27.1.33	27.0.43	27.0.42	27.0.41	27.0.40	27.0.39	27.0.38
BUFGCTRL29:MUX.I1	27.0.32	27.1.37	27.1.36	27.1.35	27.1.34	27.0.33	27.1.43	27.1.42	27.1.41	27.1.40	27.1.39	27.1.38
BUFGCTRL2:MUX.I0	17.1.62	17.0.58	17.0.59	17.0.60	17.0.61	17.1.63	17.0.52	17.0.53	17.0.54	17.0.55	17.0.56	17.0.57
BUFGCTRL2:MUX.I1	17.0.62	17.1.58	17.1.59	17.1.60	17.1.61	17.0.63	17.1.52	17.1.53	17.1.54	17.1.55	17.1.56	17.1.57
BUFGCTRL30:MUX.I0	27.1.16	27.0.21	27.0.20	27.0.19	27.0.18	27.1.17	27.0.27	27.0.26	27.0.25	27.0.24	27.0.23	27.0.22
BUFGCTRL30:MUX.I1	27.0.16	27.1.21	27.1.20	27.1.19	27.1.18	27.0.17	27.1.27	27.1.26	27.1.25	27.1.24	27.1.23	27.1.22
BUFGCTRL31:MUX.I0	27.1.0	27.0.5	27.0.4	27.0.3	27.0.2	27.1.1	27.0.11	27.0.10	27.0.9	27.0.8	27.0.7	27.0.6
BUFGCTRL31:MUX.I1	27.0.0	27.1.5	27.1.4	27.1.3	27.1.2	27.0.1	27.1.11	27.1.10	27.1.9	27.1.8	27.1.7	27.1.6
BUFGCTRL3:MUX.I0	17.1.78	17.0.74	17.0.75	17.0.76	17.0.77	17.1.79	17.0.68	17.0.69	17.0.70	17.0.71	17.0.72	17.0.73
BUFGCTRL3:MUX.I1	17.0.78	17.1.74	17.1.75	17.1.76	17.1.77	17.0.79	17.1.68	17.1.69	17.1.70	17.1.71	17.1.72	17.1.73
BUFGCTRL4:MUX.I0	18.1.30	18.0.26	18.0.27	18.0.28	18.0.29	18.1.31	18.0.20	18.0.21	18.0.22	18.0.23	18.0.24	18.0.25
BUFGCTRL4:MUX.I1	18.0.30	18.1.26	18.1.27	18.1.28	18.1.29	18.0.31	18.1.20	18.1.21	18.1.22	18.1.23	18.1.24	18.1.25
BUFGCTRL5:MUX.I0	18.1.46	18.0.42	18.0.43	18.0.44	18.0.45	18.1.47	18.0.36	18.0.37	18.0.38	18.0.39	18.0.40	18.0.41
BUFGCTRL5:MUX.I1	18.0.46	18.1.42	18.1.43	18.1.44	18.1.45	18.0.47	18.1.36	18.1.37	18.1.38	18.1.39	18.1.40	18.1.41
BUFGCTRL6:MUX.I0	18.1.62	18.0.58	18.0.59	18.0.60	18.0.61	18.1.63	18.0.52	18.0.53	18.0.54	18.0.55	18.0.56	18.0.57
BUFGCTRL6:MUX.I1	18.0.62	18.1.58	18.1.59	18.1.60	18.1.61	18.0.63	18.1.52	18.1.53	18.1.54	18.1.55	18.1.56	18.1.57
BUFGCTRL7:MUX.I0	18.1.78	18.0.74	18.0.75	18.0.76	18.0.77	18.1.79	18.0.68	18.0.69	18.0.70	18.0.71	18.0.72	18.0.73
BUFGCTRL7:MUX.I1	18.0.78	18.1.74	18.1.75	18.1.76	18.1.77	18.0.79	18.1.68	18.1.69	18.1.70	18.1.71	18.1.72	18.1.73
BUFGCTRL8:MUX.I0	19.1.30	19.0.26	19.0.27	19.0.28	19.0.29	19.1.31	19.0.20	19.0.21	19.0.22	19.0.23	19.0.24	19.0.25
BUFGCTRL8:MUX.I1	19.0.30	19.1.26	19.1.27	19.1.28	19.1.29	19.0.31	19.1.20	19.1.21	19.1.22	19.1.23	19.1.24	19.1.25
BUFGCTRL9:MUX.I0	19.1.46	19.0.42	19.0.43	19.0.44	19.0.45	19.1.47	19.0.36	19.0.37	19.0.38	19.0.39	19.0.40	19.0.41
BUFGCTRL9:MUX.I1	19.0.46	19.1.42	19.1.43	19.1.44	19.1.45	19.0.47	19.1.36	19.1.37	19.1.38	19.1.39	19.1.40	19.1.41
NONE	0	0	0	0	0	0	0	0	0	0	0	0
GFB0	0	0	0	0	1	0	0	0	0	0	0	1
GFB1	0	0	0	0	1	0	0	0	0	0	1	0
GFB2	0	0	0	0	1	0	0	0	0	1	0	0
GFB3	0	0	0	0	1	0	0	0	1	0	0	0
GFB4	0	0	0	0	1	0	0	1	0	0	0	0
GFB5	0	0	0	0	1	0	1	0	0	0	0	0
GFB6	0	0	0	1	0	0	0	0	0	0	0	1
GFB7	0	0	0	1	0	0	0	0	0	0	1	0
GFB8	0	0	0	1	0	0	0	0	0	1	0	0
GFB9	0	0	0	1	0	0	0	0	1	0	0	0
GFB10	0	0	0	1	0	0	0	1	0	0	0	0
GFB11	0	0	0	1	0	0	1	0	0	0	0	0
GFB12	0	0	1	0	0	0	0	0	0	0	0	1
GFB13	0	0	1	0	0	0	0	0	0	0	1	0
GFB14	0	0	1	0	0	0	0	0	0	1	0	0
GFB15	0	0	1	0	0	0	0	0	1	0	0	0
MGT_L0	0	0	1	0	0	0	0	1	0	0	0	0
MGT_L1	0	0	1	0	0	0	1	0	0	0	0	0
CKINT0	0	1	0	0	0	0	0	0	0	0	0	1
CKINT1	0	1	0	0	0	0	0	0	0	0	1	0
MGT_R0	0	1	0	0	0	0	0	1	0	0	0	0
MGT_R1	0	1	0	0	0	0	1	0	0	0	0	0
MUXBUS	1	0	0	0	0	1	0	0	0	0	0	0

ICAP_COMMON:ICAP_WIDTH	7.18.70
X32	0
X8	1

MISC:BUSYPIN	0.18.41	0.18.38
MISC:CSPIN	15.18.11	15.18.12
MISC:DINPIN	15.18.14	15.18.34
MISC:HSWAPENPIN	15.18.44	15.18.45
MISC:M0PIN	0.18.9	0.18.11
MISC:M1PIN	0.18.12	0.18.14
MISC:M2PIN	0.18.34	0.18.35
MISC:RDWRPIN	15.18.8	15.18.9
MISC:TCKPIN	0.18.72	0.18.70
MISC:TDIPIN	0.18.65	0.18.46
MISC:TDOPIN	0.18.44	0.18.45
MISC:TMSPIN	0.18.68	0.18.67
PULLUP	0	0
PULLDOWN	0	1
PULLNONE	1	0

MISC:CCLKPIN	15.18.35
MISC:DONEPIN	15.18.37
MISC:INITPIN	15.18.38
MISC:POWERDOWNPIN	0.18.37
MISC:PROGPIN	15.18.41
PULLUP	0
PULLNONE	1

MISC:DCI_CLK_ENABLE	6.18.12	6.18.9
non-inverted	[1]	[0]

MISC:PROBESEL	14.18.67	14.18.65	14.18.46	14.18.45
NONE	0	0	0	0
0	0	0	0	1
1	0	0	1	0
2	0	1	0	0
3	1	0	0	0

Keyboard shortcuts

Project Combine