Clock management tile

TODO: describe this madness

Tile CMT

Cells: 10

Switchbox SPEC_INT

virtex5 CMT switchbox SPEC_INT permanent buffers
Destination	Source
CELL[5].OUT_BEL[20]	CELL[0].OUT_CMT[10]

virtex5 CMT switchbox SPEC_INT muxes OUT_CMT[10]
Bits			Destination
MAIN[6][28][45]	MAIN[6][29][45]	MAIN[6][28][44]	CELL[0].OUT_CMT[10]
			Source
0	0	0	CELL[0].IMUX_DCM_CLKIN[1]
0	0	1	CELL[0].IMUX_DCM_CLKIN[0]
0	1	0	CELL[0].TEST_PLL_CLKIN
0	1	1	CELL[0].IMUX_PLL_CLKFB
1	0	0	CELL[0].IMUX_DCM_CLKFB[1]
1	0	1	CELL[0].IMUX_DCM_CLKFB[0]
1	1	1	off

virtex5 CMT switchbox SPEC_INT muxes IMUX_DCM_CLKIN[0]
Bits					Destination
MAIN[1][29][2]	MAIN[1][28][1]	MAIN[1][29][1]	MAIN[1][29][0]	MAIN[1][28][0]	CELL[0].IMUX_DCM_CLKIN[0]
					Source
0	0	0	0	0	CELL[0].GIOB_CMT[0]
0	0	0	0	1	CELL[0].GIOB_CMT[2]
0	0	0	1	0	CELL[0].GIOB_CMT[1]
0	0	0	1	1	CELL[0].GIOB_CMT[3]
0	0	1	0	0	CELL[0].GIOB_CMT[6]
0	0	1	0	1	CELL[0].GIOB_CMT[8]
0	0	1	1	0	CELL[0].GIOB_CMT[7]
0	0	1	1	1	CELL[0].GIOB_CMT[9]
0	1	0	0	0	CELL[0].GIOB_CMT[4]
0	1	0	1	0	CELL[0].GIOB_CMT[5]
0	1	1	0	0	CELL[0].HCLK_CMT[0]
0	1	1	1	0	CELL[0].HCLK_CMT[1]
1	0	0	0	0	CELL[0].HCLK_CMT[2]
1	0	0	0	1	CELL[0].HCLK_CMT[4]
1	0	0	1	0	CELL[0].HCLK_CMT[3]
1	0	0	1	1	CELL[0].HCLK_CMT[5]
1	0	1	0	0	CELL[0].HCLK_CMT[8]
1	0	1	0	1	CELL[0].IMUX_CLK[0]
1	0	1	1	0	CELL[0].HCLK_CMT[9]
1	0	1	1	1	CELL[0].IMUX_CLK[1]
1	1	0	0	0	CELL[0].HCLK_CMT[6]
1	1	0	1	0	CELL[0].HCLK_CMT[7]
1	1	1	0	0	CELL[0].IMUX_IMUX[6]
1	1	1	1	0	CELL[0].OMUX_PLL_SKEWCLKIN1

virtex5 CMT switchbox SPEC_INT muxes IMUX_DCM_CLKIN[1]
Bits					Destination
MAIN[8][29][2]	MAIN[8][28][1]	MAIN[8][29][1]	MAIN[8][29][0]	MAIN[8][28][0]	CELL[0].IMUX_DCM_CLKIN[1]
					Source
0	0	0	0	0	CELL[0].GIOB_CMT[0]
0	0	0	0	1	CELL[0].GIOB_CMT[2]
0	0	0	1	0	CELL[0].GIOB_CMT[1]
0	0	0	1	1	CELL[0].GIOB_CMT[3]
0	0	1	0	0	CELL[0].GIOB_CMT[6]
0	0	1	0	1	CELL[0].GIOB_CMT[8]
0	0	1	1	0	CELL[0].GIOB_CMT[7]
0	0	1	1	1	CELL[0].GIOB_CMT[9]
0	1	0	0	0	CELL[0].GIOB_CMT[4]
0	1	0	1	0	CELL[0].GIOB_CMT[5]
0	1	1	0	0	CELL[0].HCLK_CMT[0]
0	1	1	1	0	CELL[0].HCLK_CMT[1]
1	0	0	0	0	CELL[0].HCLK_CMT[2]
1	0	0	0	1	CELL[0].HCLK_CMT[4]
1	0	0	1	0	CELL[0].HCLK_CMT[3]
1	0	0	1	1	CELL[0].HCLK_CMT[5]
1	0	1	0	0	CELL[0].HCLK_CMT[8]
1	0	1	0	1	CELL[7].IMUX_CLK[0]
1	0	1	1	0	CELL[0].HCLK_CMT[9]
1	0	1	1	1	CELL[7].IMUX_CLK[1]
1	1	0	0	0	CELL[0].HCLK_CMT[6]
1	1	0	1	0	CELL[0].HCLK_CMT[7]
1	1	1	0	0	CELL[7].IMUX_IMUX[12]
1	1	1	1	0	CELL[0].OMUX_PLL_SKEWCLKIN2

virtex5 CMT switchbox SPEC_INT muxes IMUX_DCM_CLKFB[0]
Bits					Destination
MAIN[1][29][4]	MAIN[1][28][4]	MAIN[1][28][3]	MAIN[1][29][3]	MAIN[1][28][2]	CELL[0].IMUX_DCM_CLKFB[0]
					Source
0	0	0	0	0	CELL[0].GIOB_CMT[0]
0	0	0	0	1	CELL[0].GIOB_CMT[1]
0	0	0	1	0	CELL[0].GIOB_CMT[4]
0	0	0	1	1	CELL[0].GIOB_CMT[5]
0	0	1	0	0	CELL[0].GIOB_CMT[2]
0	0	1	0	1	CELL[0].GIOB_CMT[3]
0	1	0	0	0	CELL[0].HCLK_CMT[2]
0	1	0	0	1	CELL[0].HCLK_CMT[3]
0	1	0	1	0	CELL[0].HCLK_CMT[6]
0	1	0	1	1	CELL[0].HCLK_CMT[7]
0	1	1	0	0	CELL[0].HCLK_CMT[4]
0	1	1	0	1	CELL[0].HCLK_CMT[5]
1	0	0	0	0	CELL[0].GIOB_CMT[6]
1	0	0	0	1	CELL[0].GIOB_CMT[7]
1	0	0	1	0	CELL[0].HCLK_CMT[0]
1	0	0	1	1	CELL[0].HCLK_CMT[1]
1	0	1	0	0	CELL[0].GIOB_CMT[8]
1	0	1	0	1	CELL[0].GIOB_CMT[9]
1	1	0	0	0	CELL[0].HCLK_CMT[8]
1	1	0	0	1	CELL[0].HCLK_CMT[9]
1	1	0	1	0	CELL[0].IMUX_IMUX[6]
1	1	0	1	1	CELL[0].OMUX_PLL_SKEWCLKIN1
1	1	1	0	0	CELL[0].IMUX_CLK[0]
1	1	1	0	1	CELL[0].IMUX_CLK[1]

virtex5 CMT switchbox SPEC_INT muxes IMUX_DCM_CLKFB[1]
Bits					Destination
MAIN[8][29][4]	MAIN[8][28][4]	MAIN[8][28][3]	MAIN[8][29][3]	MAIN[8][28][2]	CELL[0].IMUX_DCM_CLKFB[1]
					Source
0	0	0	0	0	CELL[0].GIOB_CMT[0]
0	0	0	0	1	CELL[0].GIOB_CMT[1]
0	0	0	1	0	CELL[0].GIOB_CMT[4]
0	0	0	1	1	CELL[0].GIOB_CMT[5]
0	0	1	0	0	CELL[0].GIOB_CMT[2]
0	0	1	0	1	CELL[0].GIOB_CMT[3]
0	1	0	0	0	CELL[0].HCLK_CMT[2]
0	1	0	0	1	CELL[0].HCLK_CMT[3]
0	1	0	1	0	CELL[0].HCLK_CMT[6]
0	1	0	1	1	CELL[0].HCLK_CMT[7]
0	1	1	0	0	CELL[0].HCLK_CMT[4]
0	1	1	0	1	CELL[0].HCLK_CMT[5]
1	0	0	0	0	CELL[0].GIOB_CMT[6]
1	0	0	0	1	CELL[0].GIOB_CMT[7]
1	0	0	1	0	CELL[0].HCLK_CMT[0]
1	0	0	1	1	CELL[0].HCLK_CMT[1]
1	0	1	0	0	CELL[0].GIOB_CMT[8]
1	0	1	0	1	CELL[0].GIOB_CMT[9]
1	1	0	0	0	CELL[0].HCLK_CMT[8]
1	1	0	0	1	CELL[0].HCLK_CMT[9]
1	1	0	1	0	CELL[7].IMUX_IMUX[12]
1	1	0	1	1	CELL[0].OMUX_PLL_SKEWCLKIN2
1	1	1	0	0	CELL[7].IMUX_CLK[0]
1	1	1	0	1	CELL[7].IMUX_CLK[1]

virtex5 CMT switchbox SPEC_INT muxes OMUX_DCM_SKEWCLKIN1[0]
Bits				Destination
MAIN[1][28][6]	MAIN[1][29][6]	MAIN[1][29][5]	MAIN[1][28][5]	CELL[0].OMUX_DCM_SKEWCLKIN1[0]
				Source
0	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	CELL[0].OUT_CMT[1]
0	0	1	0	CELL[0].OUT_CMT[2]
0	0	1	1	CELL[0].OUT_CMT[3]
0	1	0	0	CELL[0].OUT_CMT[4]
0	1	0	1	CELL[0].OUT_CMT[5]
0	1	1	0	CELL[0].OUT_CMT[6]
0	1	1	1	CELL[0].OUT_CMT[7]
1	0	0	0	CELL[0].OUT_CMT[8]
1	0	0	1	CELL[0].OUT_CMT[9]

virtex5 CMT switchbox SPEC_INT muxes OMUX_DCM_SKEWCLKIN1[1]
Bits				Destination
MAIN[8][28][6]	MAIN[8][29][6]	MAIN[8][29][5]	MAIN[8][28][5]	CELL[0].OMUX_DCM_SKEWCLKIN1[1]
				Source
0	0	0	0	CELL[0].OUT_CMT[18]
0	0	0	1	CELL[0].OUT_CMT[19]
0	0	1	0	CELL[0].OUT_CMT[20]
0	0	1	1	CELL[0].OUT_CMT[21]
0	1	0	0	CELL[0].OUT_CMT[22]
0	1	0	1	CELL[0].OUT_CMT[23]
0	1	1	0	CELL[0].OUT_CMT[24]
0	1	1	1	CELL[0].OUT_CMT[25]
1	0	0	0	CELL[0].OUT_CMT[26]
1	0	0	1	CELL[0].OUT_CMT[27]

virtex5 CMT switchbox SPEC_INT muxes OMUX_DCM_SKEWCLKIN2[0]
Bits				Destination
MAIN[1][29][9]	MAIN[1][28][9]	MAIN[1][28][8]	MAIN[1][29][8]	CELL[0].OMUX_DCM_SKEWCLKIN2[0]
				Source
0	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	CELL[0].OUT_CMT[1]
0	0	1	0	CELL[0].OUT_CMT[2]
0	0	1	1	CELL[0].OUT_CMT[3]
0	1	0	0	CELL[0].OUT_CMT[4]
0	1	0	1	CELL[0].OUT_CMT[5]
0	1	1	0	CELL[0].OUT_CMT[6]
0	1	1	1	CELL[0].OUT_CMT[7]
1	0	0	0	CELL[0].OUT_CMT[8]
1	0	0	1	CELL[0].OUT_CMT[9]

virtex5 CMT switchbox SPEC_INT muxes OMUX_DCM_SKEWCLKIN2[1]
Bits				Destination
MAIN[8][29][9]	MAIN[8][28][9]	MAIN[8][28][8]	MAIN[8][29][8]	CELL[0].OMUX_DCM_SKEWCLKIN2[1]
				Source
0	0	0	0	CELL[0].OUT_CMT[18]
0	0	0	1	CELL[0].OUT_CMT[19]
0	0	1	0	CELL[0].OUT_CMT[20]
0	0	1	1	CELL[0].OUT_CMT[21]
0	1	0	0	CELL[0].OUT_CMT[22]
0	1	0	1	CELL[0].OUT_CMT[23]
0	1	1	0	CELL[0].OUT_CMT[24]
0	1	1	1	CELL[0].OUT_CMT[25]
1	0	0	0	CELL[0].OUT_CMT[26]
1	0	0	1	CELL[0].OUT_CMT[27]

virtex5 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB
Bits					Destination
MAIN[6][29][52]	MAIN[6][28][52]	MAIN[6][28][51]	MAIN[6][29][51]	MAIN[6][28][50]	CELL[0].IMUX_PLL_CLKFB
					Source
0	0	0	0	0	CELL[0].GIOB_CMT[0]
0	0	0	0	1	CELL[0].GIOB_CMT[1]
0	0	0	1	0	CELL[0].HCLK_CMT[1]
0	0	0	1	1	CELL[0].HCLK_CMT[2]
0	0	1	0	0	CELL[0].GIOB_CMT[2]
0	0	1	0	1	CELL[0].HCLK_CMT[0]
0	1	0	0	0	CELL[0].GIOB_CMT[5]
0	1	0	0	1	CELL[0].GIOB_CMT[6]
0	1	0	1	0	CELL[0].HCLK_CMT[6]
0	1	0	1	1	CELL[0].HCLK_CMT[7]
0	1	1	0	0	CELL[0].GIOB_CMT[7]
0	1	1	0	1	CELL[0].HCLK_CMT[5]
1	0	0	0	0	CELL[0].GIOB_CMT[3]
1	0	0	0	1	CELL[0].GIOB_CMT[4]
1	0	1	0	0	CELL[0].HCLK_CMT[3]
1	0	1	0	1	CELL[0].HCLK_CMT[4]
1	1	0	0	0	CELL[0].GIOB_CMT[8]
1	1	0	0	1	CELL[0].GIOB_CMT[9]
1	1	0	1	0	CELL[0].OUT_PLL_CLKFBDCM
1	1	0	1	1	CELL[0].OUT_CMT[11]
1	1	1	0	0	CELL[0].HCLK_CMT[8]
1	1	1	0	1	CELL[0].HCLK_CMT[9]
1	1	1	1	0	CELL[4].IMUX_CLK[0]

virtex5 CMT switchbox SPEC_INT muxes OMUX_PLL_SKEWCLKIN1
Bits			Destination
MAIN[6][29][54]	MAIN[6][28][53]	MAIN[6][29][53]	CELL[0].OMUX_PLL_SKEWCLKIN1
			Source
0	0	0	CELL[0].OUT_PLL_CLKOUTDCM[0]
0	0	1	CELL[0].OUT_PLL_CLKOUTDCM[2]
0	1	0	CELL[0].OUT_PLL_CLKOUTDCM[1]
0	1	1	CELL[0].OUT_PLL_CLKOUTDCM[3]
1	0	0	CELL[0].OUT_PLL_CLKOUTDCM[4]
1	0	1	off
1	1	0	CELL[0].OUT_PLL_CLKOUTDCM[5]

virtex5 CMT switchbox SPEC_INT muxes OMUX_PLL_SKEWCLKIN2
Bits			Destination
MAIN[6][28][55]	MAIN[6][29][55]	MAIN[6][28][54]	CELL[0].OMUX_PLL_SKEWCLKIN2
			Source
0	0	0	CELL[0].OUT_PLL_CLKOUTDCM[0]
0	0	1	CELL[0].OUT_PLL_CLKOUTDCM[1]
0	1	0	CELL[0].OUT_PLL_CLKOUTDCM[4]
0	1	1	CELL[0].OUT_PLL_CLKOUTDCM[5]
1	0	0	CELL[0].OUT_PLL_CLKOUTDCM[2]
1	0	1	CELL[0].OUT_PLL_CLKOUTDCM[3]
1	1	0	off
1	1	1	CELL[0].OUT_PLL_CLKFBDCM

virtex5 CMT switchbox SPEC_INT pair mux CELL[0].IMUX_PLL_CLKIN1 CELL[0].IMUX_PLL_CLKIN2
Bits				Destination A	Destination B
MAIN[6][28][49]	MAIN[6][29][49]	MAIN[6][29][48]	MAIN[6][28][48]	CELL[0].IMUX_PLL_CLKIN1	CELL[0].IMUX_PLL_CLKIN2
0	0	1	1	-	CELL[0].OUT_PLL_CLKFBDCM
1	1	0	0	CELL[0].HCLK_CMT[0]	CELL[0].HCLK_CMT[5]
0	0	0	1	CELL[0].HCLK_CMT[1]	CELL[0].HCLK_CMT[6]
0	1	0	1	CELL[0].HCLK_CMT[2]	CELL[0].HCLK_CMT[7]
1	0	1	0	CELL[0].HCLK_CMT[3]	CELL[0].HCLK_CMT[8]
1	1	1	0	CELL[0].HCLK_CMT[4]	CELL[0].HCLK_CMT[9]
0	0	0	0	CELL[0].GIOB_CMT[0]	CELL[0].GIOB_CMT[5]
0	1	0	0	CELL[0].GIOB_CMT[1]	CELL[0].GIOB_CMT[6]
1	0	0	0	CELL[0].GIOB_CMT[2]	CELL[0].GIOB_CMT[7]
0	0	1	0	CELL[0].GIOB_CMT[3]	CELL[0].GIOB_CMT[8]
0	1	1	0	CELL[0].GIOB_CMT[4]	CELL[0].GIOB_CMT[9]
0	1	1	1	CELL[0].OMUX_DCM_SKEWCLKIN1[0]	-
1	0	1	1	CELL[0].OMUX_DCM_SKEWCLKIN1[1]	-
1	1	1	1	CELL[3].IMUX_CLK[0]	-

Bels DCM_V5

virtex5 CMT bel DCM_V5 pins
Pin	Direction	DCM[0]	DCM[1]
CLKIN	in	CELL[0].IMUX_DCM_CLKIN[0]	CELL[0].IMUX_DCM_CLKIN[1]
CLKFB	in	CELL[0].IMUX_DCM_CLKFB[0]	CELL[0].IMUX_DCM_CLKFB[1]
RST	in	CELL[1].IMUX_CTRL_SITE[0] invert by MAIN[1][28][26]	CELL[8].IMUX_CTRL_SITE[0] invert by MAIN[8][28][26]
PSCLK	in	CELL[2].IMUX_CLK[0]	CELL[9].IMUX_CLK[0]
PSEN	in	CELL[2].IMUX_IMUX[9] invert by MAIN[1][29][27]	CELL[9].IMUX_IMUX[9] invert by MAIN[8][29][27]
PSINCDEC	in	CELL[2].IMUX_IMUX[10] invert by MAIN[1][28][27]	CELL[9].IMUX_IMUX[10] invert by MAIN[8][28][27]
DCLK	in	CELL[1].IMUX_CLK[0]	CELL[8].IMUX_CLK[0]
DEN	in	CELL[1].IMUX_IMUX[23]	CELL[8].IMUX_IMUX[23]
DWE	in	CELL[1].IMUX_IMUX[24]	CELL[8].IMUX_IMUX[24]
DADDR[0]	in	CELL[1].IMUX_IMUX[16]	CELL[8].IMUX_IMUX[16]
DADDR[1]	in	CELL[1].IMUX_IMUX[17]	CELL[8].IMUX_IMUX[17]
DADDR[2]	in	CELL[1].IMUX_IMUX[18]	CELL[8].IMUX_IMUX[18]
DADDR[3]	in	CELL[1].IMUX_IMUX[19]	CELL[8].IMUX_IMUX[19]
DADDR[4]	in	CELL[1].IMUX_IMUX[20]	CELL[8].IMUX_IMUX[20]
DADDR[5]	in	CELL[1].IMUX_IMUX[21]	CELL[8].IMUX_IMUX[21]
DADDR[6]	in	CELL[1].IMUX_IMUX[22]	CELL[8].IMUX_IMUX[22]
DI[0]	in	CELL[1].IMUX_IMUX[0]	CELL[8].IMUX_IMUX[0]
DI[1]	in	CELL[1].IMUX_IMUX[1]	CELL[8].IMUX_IMUX[1]
DI[2]	in	CELL[1].IMUX_IMUX[2]	CELL[8].IMUX_IMUX[2]
DI[3]	in	CELL[1].IMUX_IMUX[3]	CELL[8].IMUX_IMUX[3]
DI[4]	in	CELL[1].IMUX_IMUX[4]	CELL[8].IMUX_IMUX[4]
DI[5]	in	CELL[1].IMUX_IMUX[5]	CELL[8].IMUX_IMUX[5]
DI[6]	in	CELL[1].IMUX_IMUX[6]	CELL[8].IMUX_IMUX[6]
DI[7]	in	CELL[1].IMUX_IMUX[7]	CELL[8].IMUX_IMUX[7]
DI[8]	in	CELL[1].IMUX_IMUX[8]	CELL[8].IMUX_IMUX[8]
DI[9]	in	CELL[1].IMUX_IMUX[9]	CELL[8].IMUX_IMUX[9]
DI[10]	in	CELL[1].IMUX_IMUX[10]	CELL[8].IMUX_IMUX[10]
DI[11]	in	CELL[1].IMUX_IMUX[11]	CELL[8].IMUX_IMUX[11]
DI[12]	in	CELL[1].IMUX_IMUX[12]	CELL[8].IMUX_IMUX[12]
DI[13]	in	CELL[1].IMUX_IMUX[13]	CELL[8].IMUX_IMUX[13]
DI[14]	in	CELL[1].IMUX_IMUX[14]	CELL[8].IMUX_IMUX[14]
DI[15]	in	CELL[1].IMUX_IMUX[15]	CELL[8].IMUX_IMUX[15]
FREEZEDLL	in	CELL[2].IMUX_IMUX[8]	CELL[9].IMUX_IMUX[8]
FREEZEDFS	in	CELL[2].IMUX_IMUX[7]	CELL[9].IMUX_IMUX[7]
CTLMODE	in	CELL[2].IMUX_IMUX[2]	CELL[9].IMUX_IMUX[2]
CTLGO	in	CELL[2].IMUX_IMUX[3]	CELL[9].IMUX_IMUX[3]
CTLOSC1	in	CELL[2].IMUX_IMUX[1]	CELL[9].IMUX_IMUX[1]
CTLOSC2	in	CELL[2].IMUX_IMUX[0]	CELL[9].IMUX_IMUX[0]
CTLSEL[0]	in	CELL[2].IMUX_IMUX[4]	CELL[9].IMUX_IMUX[4]
CTLSEL[1]	in	CELL[2].IMUX_IMUX[5]	CELL[9].IMUX_IMUX[5]
CTLSEL[2]	in	CELL[2].IMUX_IMUX[6]	CELL[9].IMUX_IMUX[6]
SKEWCLKIN1	in	CELL[0].OMUX_DCM_SKEWCLKIN1[0] invert by MAIN[1][28][7]	CELL[0].OMUX_DCM_SKEWCLKIN1[1] invert by MAIN[8][28][7]
SKEWCLKIN2	in	CELL[0].OMUX_DCM_SKEWCLKIN2[0] invert by MAIN[1][29][7]	CELL[0].OMUX_DCM_SKEWCLKIN2[1] invert by MAIN[8][29][7]
SKEWIN	in	CELL[8].IMUX_CLK[1] invert by MAIN[1][29][10]	CELL[1].IMUX_CLK[1] invert by MAIN[8][29][10]
SKEWRST	in	CELL[0].IMUX_CTRL_SITE[0] invert by MAIN[1][28][10]	CELL[7].IMUX_CTRL_SITE[0] invert by MAIN[8][28][10]
SCANIN[0]	in	CELL[0].IMUX_IMUX[0]	CELL[7].IMUX_IMUX[0]
SCANIN[1]	in	CELL[0].IMUX_IMUX[1]	CELL[7].IMUX_IMUX[1]
SCANIN[2]	in	CELL[0].IMUX_IMUX[2]	CELL[7].IMUX_IMUX[2]
SCANIN[3]	in	CELL[0].IMUX_IMUX[3]	CELL[7].IMUX_IMUX[3]
SCANIN[4]	in	CELL[0].IMUX_IMUX[4]	CELL[7].IMUX_IMUX[4]
CLK0	out	CELL[0].OUT_CMT[0]	CELL[0].OUT_CMT[18]
CLK90	out	CELL[0].OUT_CMT[1]	CELL[0].OUT_CMT[19]
CLK180	out	CELL[0].OUT_CMT[2]	CELL[0].OUT_CMT[20]
CLK270	out	CELL[0].OUT_CMT[3]	CELL[0].OUT_CMT[21]
CLK2X	out	CELL[0].OUT_CMT[4]	CELL[0].OUT_CMT[22]
CLK2X180	out	CELL[0].OUT_CMT[5]	CELL[0].OUT_CMT[23]
CLKDV	out	CELL[0].OUT_CMT[6]	CELL[0].OUT_CMT[24]
CLKFX	out	CELL[0].OUT_CMT[7]	CELL[0].OUT_CMT[25]
CLKFX180	out	CELL[0].OUT_CMT[8]	CELL[0].OUT_CMT[26]
CONCUR	out	CELL[0].OUT_CMT[9]	CELL[0].OUT_CMT[27]
LOCKED	out	CELL[2].OUT_BEL[0]	CELL[9].OUT_BEL[0]
PSDONE	out	CELL[2].OUT_BEL[11]	CELL[9].OUT_BEL[11]
DRDY	out	CELL[0].OUT_BEL[0]	CELL[7].OUT_BEL[0]
DO[0]	out	CELL[1].OUT_BEL[0]	CELL[8].OUT_BEL[0]
DO[1]	out	CELL[1].OUT_BEL[1]	CELL[8].OUT_BEL[1]
DO[2]	out	CELL[1].OUT_BEL[2]	CELL[8].OUT_BEL[2]
DO[3]	out	CELL[1].OUT_BEL[3]	CELL[8].OUT_BEL[3]
DO[4]	out	CELL[1].OUT_BEL[4]	CELL[8].OUT_BEL[4]
DO[5]	out	CELL[1].OUT_BEL[5]	CELL[8].OUT_BEL[5]
DO[6]	out	CELL[1].OUT_BEL[6]	CELL[8].OUT_BEL[6]
DO[7]	out	CELL[1].OUT_BEL[7]	CELL[8].OUT_BEL[7]
DO[8]	out	CELL[1].OUT_BEL[8]	CELL[8].OUT_BEL[8]
DO[9]	out	CELL[1].OUT_BEL[9]	CELL[8].OUT_BEL[9]
DO[10]	out	CELL[1].OUT_BEL[10]	CELL[8].OUT_BEL[10]
DO[11]	out	CELL[1].OUT_BEL[11]	CELL[8].OUT_BEL[11]
DO[12]	out	CELL[1].OUT_BEL[12]	CELL[8].OUT_BEL[12]
DO[13]	out	CELL[1].OUT_BEL[13]	CELL[8].OUT_BEL[13]
DO[14]	out	CELL[1].OUT_BEL[14]	CELL[8].OUT_BEL[14]
DO[15]	out	CELL[1].OUT_BEL[15]	CELL[8].OUT_BEL[15]
SKEWOUT	out	CELL[0].OUT_BEL[3]	CELL[7].OUT_BEL[3]
SCANOUT[0]	out	CELL[0].OUT_BEL[2]	CELL[7].OUT_BEL[2]
SCANOUT[1]	out	CELL[0].OUT_BEL[1]	CELL[7].OUT_BEL[1]

virtex5 CMT bel DCM_V5 attribute bits
Attribute	DCM[0]	DCM[1]
DRP[0] bit 0	MAIN[0][29][0]	MAIN[7][29][0]
DRP[0] bit 1	MAIN[0][28][0]	MAIN[7][28][0]
DRP[0] bit 2	MAIN[0][28][1]	MAIN[7][28][1]
DRP[0] bit 3	MAIN[0][29][1]	MAIN[7][29][1]
DRP[0] bit 4	MAIN[0][29][2]	MAIN[7][29][2]
DRP[0] bit 5	MAIN[0][28][2]	MAIN[7][28][2]
DRP[0] bit 6	MAIN[0][28][3]	MAIN[7][28][3]
DRP[0] bit 7	MAIN[0][29][3]	MAIN[7][29][3]
DRP[0] bit 8	MAIN[0][29][4]	MAIN[7][29][4]
DRP[0] bit 9	MAIN[0][28][4]	MAIN[7][28][4]
DRP[0] bit 10	MAIN[0][28][5]	MAIN[7][28][5]
DRP[0] bit 11	MAIN[0][29][5]	MAIN[7][29][5]
DRP[0] bit 12	MAIN[0][29][6]	MAIN[7][29][6]
DRP[0] bit 13	MAIN[0][28][6]	MAIN[7][28][6]
DRP[0] bit 14	MAIN[0][28][7]	MAIN[7][28][7]
DRP[0] bit 15	MAIN[0][29][7]	MAIN[7][29][7]
DRP[1] bit 0	MAIN[0][29][8]	MAIN[7][29][8]
DRP[1] bit 1	MAIN[0][28][8]	MAIN[7][28][8]
DRP[1] bit 2	MAIN[0][28][9]	MAIN[7][28][9]
DRP[1] bit 3	MAIN[0][29][9]	MAIN[7][29][9]
DRP[1] bit 4	MAIN[0][29][10]	MAIN[7][29][10]
DRP[1] bit 5	MAIN[0][28][10]	MAIN[7][28][10]
DRP[1] bit 6	MAIN[0][28][11]	MAIN[7][28][11]
DRP[1] bit 7	MAIN[0][29][11]	MAIN[7][29][11]
DRP[1] bit 8	MAIN[0][29][12]	MAIN[7][29][12]
DRP[1] bit 9	MAIN[0][28][12]	MAIN[7][28][12]
DRP[1] bit 10	MAIN[0][28][13]	MAIN[7][28][13]
DRP[1] bit 11	MAIN[0][29][13]	MAIN[7][29][13]
DRP[1] bit 12	MAIN[0][29][14]	MAIN[7][29][14]
DRP[1] bit 13	MAIN[0][28][14]	MAIN[7][28][14]
DRP[1] bit 14	MAIN[0][28][15]	MAIN[7][28][15]
DRP[1] bit 15	MAIN[0][29][15]	MAIN[7][29][15]
DRP[2] bit 0	MAIN[0][29][16]	MAIN[7][29][16]
DRP[2] bit 1	MAIN[0][28][16]	MAIN[7][28][16]
DRP[2] bit 2	MAIN[0][28][17]	MAIN[7][28][17]
DRP[2] bit 3	MAIN[0][29][17]	MAIN[7][29][17]
DRP[2] bit 4	MAIN[0][29][18]	MAIN[7][29][18]
DRP[2] bit 5	MAIN[0][28][18]	MAIN[7][28][18]
DRP[2] bit 6	MAIN[0][28][19]	MAIN[7][28][19]
DRP[2] bit 7	MAIN[0][29][19]	MAIN[7][29][19]
DRP[2] bit 8	MAIN[0][29][20]	MAIN[7][29][20]
DRP[2] bit 9	MAIN[0][28][20]	MAIN[7][28][20]
DRP[2] bit 10	MAIN[0][28][21]	MAIN[7][28][21]
DRP[2] bit 11	MAIN[0][29][21]	MAIN[7][29][21]
DRP[2] bit 12	MAIN[0][29][22]	MAIN[7][29][22]
DRP[2] bit 13	MAIN[0][28][22]	MAIN[7][28][22]
DRP[2] bit 14	MAIN[0][28][23]	MAIN[7][28][23]
DRP[2] bit 15	MAIN[0][29][23]	MAIN[7][29][23]
DRP[3] bit 0	MAIN[0][29][24]	MAIN[7][29][24]
DRP[3] bit 1	MAIN[0][28][24]	MAIN[7][28][24]
DRP[3] bit 2	MAIN[0][28][25]	MAIN[7][28][25]
DRP[3] bit 3	MAIN[0][29][25]	MAIN[7][29][25]
DRP[3] bit 4	MAIN[0][29][26]	MAIN[7][29][26]
DRP[3] bit 5	MAIN[0][28][26]	MAIN[7][28][26]
DRP[3] bit 6	MAIN[0][28][27]	MAIN[7][28][27]
DRP[3] bit 7	MAIN[0][29][27]	MAIN[7][29][27]
DRP[3] bit 8	MAIN[0][29][28]	MAIN[7][29][28]
DRP[3] bit 9	MAIN[0][28][28]	MAIN[7][28][28]
DRP[3] bit 10	MAIN[0][28][29]	MAIN[7][28][29]
DRP[3] bit 11	MAIN[0][29][29]	MAIN[7][29][29]
DRP[3] bit 12	MAIN[0][29][30]	MAIN[7][29][30]
DRP[3] bit 13	MAIN[0][28][30]	MAIN[7][28][30]
DRP[3] bit 14	MAIN[0][28][31]	MAIN[7][28][31]
DRP[3] bit 15	MAIN[0][29][31]	MAIN[7][29][31]
DRP[4] bit 0	MAIN[0][29][32]	MAIN[7][29][32]
DRP[4] bit 1	MAIN[0][28][32]	MAIN[7][28][32]
DRP[4] bit 2	MAIN[0][28][33]	MAIN[7][28][33]
DRP[4] bit 3	MAIN[0][29][33]	MAIN[7][29][33]
DRP[4] bit 4	MAIN[0][29][34]	MAIN[7][29][34]
DRP[4] bit 5	MAIN[0][28][34]	MAIN[7][28][34]
DRP[4] bit 6	MAIN[0][28][35]	MAIN[7][28][35]
DRP[4] bit 7	MAIN[0][29][35]	MAIN[7][29][35]
DRP[4] bit 8	MAIN[0][29][36]	MAIN[7][29][36]
DRP[4] bit 9	MAIN[0][28][36]	MAIN[7][28][36]
DRP[4] bit 10	MAIN[0][28][37]	MAIN[7][28][37]
DRP[4] bit 11	MAIN[0][29][37]	MAIN[7][29][37]
DRP[4] bit 12	MAIN[0][29][38]	MAIN[7][29][38]
DRP[4] bit 13	MAIN[0][28][38]	MAIN[7][28][38]
DRP[4] bit 14	MAIN[0][28][39]	MAIN[7][28][39]
DRP[4] bit 15	MAIN[0][29][39]	MAIN[7][29][39]
DRP[5] bit 0	MAIN[0][29][40]	MAIN[7][29][40]
DRP[5] bit 1	MAIN[0][28][40]	MAIN[7][28][40]
DRP[5] bit 2	MAIN[0][28][41]	MAIN[7][28][41]
DRP[5] bit 3	MAIN[0][29][41]	MAIN[7][29][41]
DRP[5] bit 4	MAIN[0][29][42]	MAIN[7][29][42]
DRP[5] bit 5	MAIN[0][28][42]	MAIN[7][28][42]
DRP[5] bit 6	MAIN[0][28][43]	MAIN[7][28][43]
DRP[5] bit 7	MAIN[0][29][43]	MAIN[7][29][43]
DRP[5] bit 8	MAIN[0][29][44]	MAIN[7][29][44]
DRP[5] bit 9	MAIN[0][28][44]	MAIN[7][28][44]
DRP[5] bit 10	MAIN[0][28][45]	MAIN[7][28][45]
DRP[5] bit 11	MAIN[0][29][45]	MAIN[7][29][45]
DRP[5] bit 12	MAIN[0][29][46]	MAIN[7][29][46]
DRP[5] bit 13	MAIN[0][28][46]	MAIN[7][28][46]
DRP[5] bit 14	MAIN[0][28][47]	MAIN[7][28][47]
DRP[5] bit 15	MAIN[0][29][47]	MAIN[7][29][47]
DRP[6] bit 0	MAIN[0][29][48]	MAIN[7][29][48]
DRP[6] bit 1	MAIN[0][28][48]	MAIN[7][28][48]
DRP[6] bit 2	MAIN[0][28][49]	MAIN[7][28][49]
DRP[6] bit 3	MAIN[0][29][49]	MAIN[7][29][49]
DRP[6] bit 4	MAIN[0][29][50]	MAIN[7][29][50]
DRP[6] bit 5	MAIN[0][28][50]	MAIN[7][28][50]
DRP[6] bit 6	MAIN[0][28][51]	MAIN[7][28][51]
DRP[6] bit 7	MAIN[0][29][51]	MAIN[7][29][51]
DRP[6] bit 8	MAIN[0][29][52]	MAIN[7][29][52]
DRP[6] bit 9	MAIN[0][28][52]	MAIN[7][28][52]
DRP[6] bit 10	MAIN[0][28][53]	MAIN[7][28][53]
DRP[6] bit 11	MAIN[0][29][53]	MAIN[7][29][53]
DRP[6] bit 12	MAIN[0][29][54]	MAIN[7][29][54]
DRP[6] bit 13	MAIN[0][28][54]	MAIN[7][28][54]
DRP[6] bit 14	MAIN[0][28][55]	MAIN[7][28][55]
DRP[6] bit 15	MAIN[0][29][55]	MAIN[7][29][55]
DRP[7] bit 0	MAIN[0][29][56]	MAIN[7][29][56]
DRP[7] bit 1	MAIN[0][28][56]	MAIN[7][28][56]
DRP[7] bit 2	MAIN[0][28][57]	MAIN[7][28][57]
DRP[7] bit 3	MAIN[0][29][57]	MAIN[7][29][57]
DRP[7] bit 4	MAIN[0][29][58]	MAIN[7][29][58]
DRP[7] bit 5	MAIN[0][28][58]	MAIN[7][28][58]
DRP[7] bit 6	MAIN[0][28][59]	MAIN[7][28][59]
DRP[7] bit 7	MAIN[0][29][59]	MAIN[7][29][59]
DRP[7] bit 8	MAIN[0][29][60]	MAIN[7][29][60]
DRP[7] bit 9	MAIN[0][28][60]	MAIN[7][28][60]
DRP[7] bit 10	MAIN[0][28][61]	MAIN[7][28][61]
DRP[7] bit 11	MAIN[0][29][61]	MAIN[7][29][61]
DRP[7] bit 12	MAIN[0][29][62]	MAIN[7][29][62]
DRP[7] bit 13	MAIN[0][28][62]	MAIN[7][28][62]
DRP[7] bit 14	MAIN[0][28][63]	MAIN[7][28][63]
DRP[7] bit 15	MAIN[0][29][63]	MAIN[7][29][63]
DRP[8] bit 0	MAIN[1][29][0]	MAIN[8][29][0]
DRP[8] bit 1	MAIN[1][28][0]	MAIN[8][28][0]
DRP[8] bit 2	MAIN[1][28][1]	MAIN[8][28][1]
DRP[8] bit 3	MAIN[1][29][1]	MAIN[8][29][1]
DRP[8] bit 4	MAIN[1][29][2]	MAIN[8][29][2]
DRP[8] bit 5	MAIN[1][28][2]	MAIN[8][28][2]
DRP[8] bit 6	MAIN[1][28][3]	MAIN[8][28][3]
DRP[8] bit 7	MAIN[1][29][3]	MAIN[8][29][3]
DRP[8] bit 8	MAIN[1][29][4]	MAIN[8][29][4]
DRP[8] bit 9	MAIN[1][28][4]	MAIN[8][28][4]
DRP[8] bit 10	MAIN[1][28][5]	MAIN[8][28][5]
DRP[8] bit 11	MAIN[1][29][5]	MAIN[8][29][5]
DRP[8] bit 12	MAIN[1][29][6]	MAIN[8][29][6]
DRP[8] bit 13	MAIN[1][28][6]	MAIN[8][28][6]
DRP[8] bit 14	MAIN[1][28][7]	MAIN[8][28][7]
DRP[8] bit 15	MAIN[1][29][7]	MAIN[8][29][7]
DRP[9] bit 0	MAIN[1][29][8]	MAIN[8][29][8]
DRP[9] bit 1	MAIN[1][28][8]	MAIN[8][28][8]
DRP[9] bit 2	MAIN[1][28][9]	MAIN[8][28][9]
DRP[9] bit 3	MAIN[1][29][9]	MAIN[8][29][9]
DRP[9] bit 4	MAIN[1][29][10]	MAIN[8][29][10]
DRP[9] bit 5	MAIN[1][28][10]	MAIN[8][28][10]
DRP[9] bit 6	MAIN[1][28][11]	MAIN[8][28][11]
DRP[9] bit 7	MAIN[1][29][11]	MAIN[8][29][11]
DRP[9] bit 8	MAIN[1][29][12]	MAIN[8][29][12]
DRP[9] bit 9	MAIN[1][28][12]	MAIN[8][28][12]
DRP[9] bit 10	MAIN[1][28][13]	MAIN[8][28][13]
DRP[9] bit 11	MAIN[1][29][13]	MAIN[8][29][13]
DRP[9] bit 12	MAIN[1][29][14]	MAIN[8][29][14]
DRP[9] bit 13	MAIN[1][28][14]	MAIN[8][28][14]
DRP[9] bit 14	MAIN[1][28][15]	MAIN[8][28][15]
DRP[9] bit 15	MAIN[1][29][15]	MAIN[8][29][15]
DRP[10] bit 0	MAIN[1][29][16]	MAIN[8][29][16]
DRP[10] bit 1	MAIN[1][28][16]	MAIN[8][28][16]
DRP[10] bit 2	MAIN[1][28][17]	MAIN[8][28][17]
DRP[10] bit 3	MAIN[1][29][17]	MAIN[8][29][17]
DRP[10] bit 4	MAIN[1][29][18]	MAIN[8][29][18]
DRP[10] bit 5	MAIN[1][28][18]	MAIN[8][28][18]
DRP[10] bit 6	MAIN[1][28][19]	MAIN[8][28][19]
DRP[10] bit 7	MAIN[1][29][19]	MAIN[8][29][19]
DRP[10] bit 8	MAIN[1][29][20]	MAIN[8][29][20]
DRP[10] bit 9	MAIN[1][28][20]	MAIN[8][28][20]
DRP[10] bit 10	MAIN[1][28][21]	MAIN[8][28][21]
DRP[10] bit 11	MAIN[1][29][21]	MAIN[8][29][21]
DRP[10] bit 12	MAIN[1][29][22]	MAIN[8][29][22]
DRP[10] bit 13	MAIN[1][28][22]	MAIN[8][28][22]
DRP[10] bit 14	MAIN[1][28][23]	MAIN[8][28][23]
DRP[10] bit 15	MAIN[1][29][23]	MAIN[8][29][23]
DRP[11] bit 0	MAIN[1][29][24]	MAIN[8][29][24]
DRP[11] bit 1	MAIN[1][28][24]	MAIN[8][28][24]
DRP[11] bit 2	MAIN[1][28][25]	MAIN[8][28][25]
DRP[11] bit 3	MAIN[1][29][25]	MAIN[8][29][25]
DRP[11] bit 4	MAIN[1][29][26]	MAIN[8][29][26]
DRP[11] bit 5	MAIN[1][28][26]	MAIN[8][28][26]
DRP[11] bit 6	MAIN[1][28][27]	MAIN[8][28][27]
DRP[11] bit 7	MAIN[1][29][27]	MAIN[8][29][27]
DRP[11] bit 8	MAIN[1][29][28]	MAIN[8][29][28]
DRP[11] bit 9	MAIN[1][28][28]	MAIN[8][28][28]
DRP[11] bit 10	MAIN[1][28][29]	MAIN[8][28][29]
DRP[11] bit 11	MAIN[1][29][29]	MAIN[8][29][29]
DRP[11] bit 12	MAIN[1][29][30]	MAIN[8][29][30]
DRP[11] bit 13	MAIN[1][28][30]	MAIN[8][28][30]
DRP[11] bit 14	MAIN[1][28][31]	MAIN[8][28][31]
DRP[11] bit 15	MAIN[1][29][31]	MAIN[8][29][31]
DRP[12] bit 0	MAIN[1][29][32]	MAIN[8][29][32]
DRP[12] bit 1	MAIN[1][28][32]	MAIN[8][28][32]
DRP[12] bit 2	MAIN[1][28][33]	MAIN[8][28][33]
DRP[12] bit 3	MAIN[1][29][33]	MAIN[8][29][33]
DRP[12] bit 4	MAIN[1][29][34]	MAIN[8][29][34]
DRP[12] bit 5	MAIN[1][28][34]	MAIN[8][28][34]
DRP[12] bit 6	MAIN[1][28][35]	MAIN[8][28][35]
DRP[12] bit 7	MAIN[1][29][35]	MAIN[8][29][35]
DRP[12] bit 8	MAIN[1][29][36]	MAIN[8][29][36]
DRP[12] bit 9	MAIN[1][28][36]	MAIN[8][28][36]
DRP[12] bit 10	MAIN[1][28][37]	MAIN[8][28][37]
DRP[12] bit 11	MAIN[1][29][37]	MAIN[8][29][37]
DRP[12] bit 12	MAIN[1][29][38]	MAIN[8][29][38]
DRP[12] bit 13	MAIN[1][28][38]	MAIN[8][28][38]
DRP[12] bit 14	MAIN[1][28][39]	MAIN[8][28][39]
DRP[12] bit 15	MAIN[1][29][39]	MAIN[8][29][39]
DRP[13] bit 0	MAIN[1][29][40]	MAIN[8][29][40]
DRP[13] bit 1	MAIN[1][28][40]	MAIN[8][28][40]
DRP[13] bit 2	MAIN[1][28][41]	MAIN[8][28][41]
DRP[13] bit 3	MAIN[1][29][41]	MAIN[8][29][41]
DRP[13] bit 4	MAIN[1][29][42]	MAIN[8][29][42]
DRP[13] bit 5	MAIN[1][28][42]	MAIN[8][28][42]
DRP[13] bit 6	MAIN[1][28][43]	MAIN[8][28][43]
DRP[13] bit 7	MAIN[1][29][43]	MAIN[8][29][43]
DRP[13] bit 8	MAIN[1][29][44]	MAIN[8][29][44]
DRP[13] bit 9	MAIN[1][28][44]	MAIN[8][28][44]
DRP[13] bit 10	MAIN[1][28][45]	MAIN[8][28][45]
DRP[13] bit 11	MAIN[1][29][45]	MAIN[8][29][45]
DRP[13] bit 12	MAIN[1][29][46]	MAIN[8][29][46]
DRP[13] bit 13	MAIN[1][28][46]	MAIN[8][28][46]
DRP[13] bit 14	MAIN[1][28][47]	MAIN[8][28][47]
DRP[13] bit 15	MAIN[1][29][47]	MAIN[8][29][47]
DRP[14] bit 0	MAIN[1][29][48]	MAIN[8][29][48]
DRP[14] bit 1	MAIN[1][28][48]	MAIN[8][28][48]
DRP[14] bit 2	MAIN[1][28][49]	MAIN[8][28][49]
DRP[14] bit 3	MAIN[1][29][49]	MAIN[8][29][49]
DRP[14] bit 4	MAIN[1][29][50]	MAIN[8][29][50]
DRP[14] bit 5	MAIN[1][28][50]	MAIN[8][28][50]
DRP[14] bit 6	MAIN[1][28][51]	MAIN[8][28][51]
DRP[14] bit 7	MAIN[1][29][51]	MAIN[8][29][51]
DRP[14] bit 8	MAIN[1][29][52]	MAIN[8][29][52]
DRP[14] bit 9	MAIN[1][28][52]	MAIN[8][28][52]
DRP[14] bit 10	MAIN[1][28][53]	MAIN[8][28][53]
DRP[14] bit 11	MAIN[1][29][53]	MAIN[8][29][53]
DRP[14] bit 12	MAIN[1][29][54]	MAIN[8][29][54]
DRP[14] bit 13	MAIN[1][28][54]	MAIN[8][28][54]
DRP[14] bit 14	MAIN[1][28][55]	MAIN[8][28][55]
DRP[14] bit 15	MAIN[1][29][55]	MAIN[8][29][55]
DRP[15] bit 0	MAIN[1][29][56]	MAIN[8][29][56]
DRP[15] bit 1	MAIN[1][28][56]	MAIN[8][28][56]
DRP[15] bit 2	MAIN[1][28][57]	MAIN[8][28][57]
DRP[15] bit 3	MAIN[1][29][57]	MAIN[8][29][57]
DRP[15] bit 4	MAIN[1][29][58]	MAIN[8][29][58]
DRP[15] bit 5	MAIN[1][28][58]	MAIN[8][28][58]
DRP[15] bit 6	MAIN[1][28][59]	MAIN[8][28][59]
DRP[15] bit 7	MAIN[1][29][59]	MAIN[8][29][59]
DRP[15] bit 8	MAIN[1][29][60]	MAIN[8][29][60]
DRP[15] bit 9	MAIN[1][28][60]	MAIN[8][28][60]
DRP[15] bit 10	MAIN[1][28][61]	MAIN[8][28][61]
DRP[15] bit 11	MAIN[1][29][61]	MAIN[8][29][61]
DRP[15] bit 12	MAIN[1][29][62]	MAIN[8][29][62]
DRP[15] bit 13	MAIN[1][28][62]	MAIN[8][28][62]
DRP[15] bit 14	MAIN[1][28][63]	MAIN[8][28][63]
DRP[15] bit 15	MAIN[1][29][63]	MAIN[8][29][63]
DRP[16] bit 0	MAIN[2][29][0]	MAIN[9][29][0]
DRP[16] bit 1	MAIN[2][28][0]	MAIN[9][28][0]
DRP[16] bit 2	MAIN[2][28][1]	MAIN[9][28][1]
DRP[16] bit 3	MAIN[2][29][1]	MAIN[9][29][1]
DRP[16] bit 4	MAIN[2][29][2]	MAIN[9][29][2]
DRP[16] bit 5	MAIN[2][28][2]	MAIN[9][28][2]
DRP[16] bit 6	MAIN[2][28][3]	MAIN[9][28][3]
DRP[16] bit 7	MAIN[2][29][3]	MAIN[9][29][3]
DRP[16] bit 8	MAIN[2][29][4]	MAIN[9][29][4]
DRP[16] bit 9	MAIN[2][28][4]	MAIN[9][28][4]
DRP[16] bit 10	MAIN[2][28][5]	MAIN[9][28][5]
DRP[16] bit 11	MAIN[2][29][5]	MAIN[9][29][5]
DRP[16] bit 12	MAIN[2][29][6]	MAIN[9][29][6]
DRP[16] bit 13	MAIN[2][28][6]	MAIN[9][28][6]
DRP[16] bit 14	MAIN[2][28][7]	MAIN[9][28][7]
DRP[16] bit 15	MAIN[2][29][7]	MAIN[9][29][7]
DRP[17] bit 0	MAIN[2][29][8]	MAIN[9][29][8]
DRP[17] bit 1	MAIN[2][28][8]	MAIN[9][28][8]
DRP[17] bit 2	MAIN[2][28][9]	MAIN[9][28][9]
DRP[17] bit 3	MAIN[2][29][9]	MAIN[9][29][9]
DRP[17] bit 4	MAIN[2][29][10]	MAIN[9][29][10]
DRP[17] bit 5	MAIN[2][28][10]	MAIN[9][28][10]
DRP[17] bit 6	MAIN[2][28][11]	MAIN[9][28][11]
DRP[17] bit 7	MAIN[2][29][11]	MAIN[9][29][11]
DRP[17] bit 8	MAIN[2][29][12]	MAIN[9][29][12]
DRP[17] bit 9	MAIN[2][28][12]	MAIN[9][28][12]
DRP[17] bit 10	MAIN[2][28][13]	MAIN[9][28][13]
DRP[17] bit 11	MAIN[2][29][13]	MAIN[9][29][13]
DRP[17] bit 12	MAIN[2][29][14]	MAIN[9][29][14]
DRP[17] bit 13	MAIN[2][28][14]	MAIN[9][28][14]
DRP[17] bit 14	MAIN[2][28][15]	MAIN[9][28][15]
DRP[17] bit 15	MAIN[2][29][15]	MAIN[9][29][15]
DRP[18] bit 0	MAIN[2][29][16]	MAIN[9][29][16]
DRP[18] bit 1	MAIN[2][28][16]	MAIN[9][28][16]
DRP[18] bit 2	MAIN[2][28][17]	MAIN[9][28][17]
DRP[18] bit 3	MAIN[2][29][17]	MAIN[9][29][17]
DRP[18] bit 4	MAIN[2][29][18]	MAIN[9][29][18]
DRP[18] bit 5	MAIN[2][28][18]	MAIN[9][28][18]
DRP[18] bit 6	MAIN[2][28][19]	MAIN[9][28][19]
DRP[18] bit 7	MAIN[2][29][19]	MAIN[9][29][19]
DRP[18] bit 8	MAIN[2][29][20]	MAIN[9][29][20]
DRP[18] bit 9	MAIN[2][28][20]	MAIN[9][28][20]
DRP[18] bit 10	MAIN[2][28][21]	MAIN[9][28][21]
DRP[18] bit 11	MAIN[2][29][21]	MAIN[9][29][21]
DRP[18] bit 12	MAIN[2][29][22]	MAIN[9][29][22]
DRP[18] bit 13	MAIN[2][28][22]	MAIN[9][28][22]
DRP[18] bit 14	MAIN[2][28][23]	MAIN[9][28][23]
DRP[18] bit 15	MAIN[2][29][23]	MAIN[9][29][23]
DRP[19] bit 0	MAIN[2][29][24]	MAIN[9][29][24]
DRP[19] bit 1	MAIN[2][28][24]	MAIN[9][28][24]
DRP[19] bit 2	MAIN[2][28][25]	MAIN[9][28][25]
DRP[19] bit 3	MAIN[2][29][25]	MAIN[9][29][25]
DRP[19] bit 4	MAIN[2][29][26]	MAIN[9][29][26]
DRP[19] bit 5	MAIN[2][28][26]	MAIN[9][28][26]
DRP[19] bit 6	MAIN[2][28][27]	MAIN[9][28][27]
DRP[19] bit 7	MAIN[2][29][27]	MAIN[9][29][27]
DRP[19] bit 8	MAIN[2][29][28]	MAIN[9][29][28]
DRP[19] bit 9	MAIN[2][28][28]	MAIN[9][28][28]
DRP[19] bit 10	MAIN[2][28][29]	MAIN[9][28][29]
DRP[19] bit 11	MAIN[2][29][29]	MAIN[9][29][29]
DRP[19] bit 12	MAIN[2][29][30]	MAIN[9][29][30]
DRP[19] bit 13	MAIN[2][28][30]	MAIN[9][28][30]
DRP[19] bit 14	MAIN[2][28][31]	MAIN[9][28][31]
DRP[19] bit 15	MAIN[2][29][31]	MAIN[9][29][31]
DRP[20] bit 0	MAIN[2][29][32]	MAIN[9][29][32]
DRP[20] bit 1	MAIN[2][28][32]	MAIN[9][28][32]
DRP[20] bit 2	MAIN[2][28][33]	MAIN[9][28][33]
DRP[20] bit 3	MAIN[2][29][33]	MAIN[9][29][33]
DRP[20] bit 4	MAIN[2][29][34]	MAIN[9][29][34]
DRP[20] bit 5	MAIN[2][28][34]	MAIN[9][28][34]
DRP[20] bit 6	MAIN[2][28][35]	MAIN[9][28][35]
DRP[20] bit 7	MAIN[2][29][35]	MAIN[9][29][35]
DRP[20] bit 8	MAIN[2][29][36]	MAIN[9][29][36]
DRP[20] bit 9	MAIN[2][28][36]	MAIN[9][28][36]
DRP[20] bit 10	MAIN[2][28][37]	MAIN[9][28][37]
DRP[20] bit 11	MAIN[2][29][37]	MAIN[9][29][37]
DRP[20] bit 12	MAIN[2][29][38]	MAIN[9][29][38]
DRP[20] bit 13	MAIN[2][28][38]	MAIN[9][28][38]
DRP[20] bit 14	MAIN[2][28][39]	MAIN[9][28][39]
DRP[20] bit 15	MAIN[2][29][39]	MAIN[9][29][39]
DRP[21] bit 0	MAIN[2][29][40]	MAIN[9][29][40]
DRP[21] bit 1	MAIN[2][28][40]	MAIN[9][28][40]
DRP[21] bit 2	MAIN[2][28][41]	MAIN[9][28][41]
DRP[21] bit 3	MAIN[2][29][41]	MAIN[9][29][41]
DRP[21] bit 4	MAIN[2][29][42]	MAIN[9][29][42]
DRP[21] bit 5	MAIN[2][28][42]	MAIN[9][28][42]
DRP[21] bit 6	MAIN[2][28][43]	MAIN[9][28][43]
DRP[21] bit 7	MAIN[2][29][43]	MAIN[9][29][43]
DRP[21] bit 8	MAIN[2][29][44]	MAIN[9][29][44]
DRP[21] bit 9	MAIN[2][28][44]	MAIN[9][28][44]
DRP[21] bit 10	MAIN[2][28][45]	MAIN[9][28][45]
DRP[21] bit 11	MAIN[2][29][45]	MAIN[9][29][45]
DRP[21] bit 12	MAIN[2][29][46]	MAIN[9][29][46]
DRP[21] bit 13	MAIN[2][28][46]	MAIN[9][28][46]
DRP[21] bit 14	MAIN[2][28][47]	MAIN[9][28][47]
DRP[21] bit 15	MAIN[2][29][47]	MAIN[9][29][47]
DRP[22] bit 0	MAIN[2][29][48]	MAIN[9][29][48]
DRP[22] bit 1	MAIN[2][28][48]	MAIN[9][28][48]
DRP[22] bit 2	MAIN[2][28][49]	MAIN[9][28][49]
DRP[22] bit 3	MAIN[2][29][49]	MAIN[9][29][49]
DRP[22] bit 4	MAIN[2][29][50]	MAIN[9][29][50]
DRP[22] bit 5	MAIN[2][28][50]	MAIN[9][28][50]
DRP[22] bit 6	MAIN[2][28][51]	MAIN[9][28][51]
DRP[22] bit 7	MAIN[2][29][51]	MAIN[9][29][51]
DRP[22] bit 8	MAIN[2][29][52]	MAIN[9][29][52]
DRP[22] bit 9	MAIN[2][28][52]	MAIN[9][28][52]
DRP[22] bit 10	MAIN[2][28][53]	MAIN[9][28][53]
DRP[22] bit 11	MAIN[2][29][53]	MAIN[9][29][53]
DRP[22] bit 12	MAIN[2][29][54]	MAIN[9][29][54]
DRP[22] bit 13	MAIN[2][28][54]	MAIN[9][28][54]
DRP[22] bit 14	MAIN[2][28][55]	MAIN[9][28][55]
DRP[22] bit 15	MAIN[2][29][55]	MAIN[9][29][55]
DRP[23] bit 0	MAIN[2][29][56]	MAIN[9][29][56]
DRP[23] bit 1	MAIN[2][28][56]	MAIN[9][28][56]
DRP[23] bit 2	MAIN[2][28][57]	MAIN[9][28][57]
DRP[23] bit 3	MAIN[2][29][57]	MAIN[9][29][57]
DRP[23] bit 4	MAIN[2][29][58]	MAIN[9][29][58]
DRP[23] bit 5	MAIN[2][28][58]	MAIN[9][28][58]
DRP[23] bit 6	MAIN[2][28][59]	MAIN[9][28][59]
DRP[23] bit 7	MAIN[2][29][59]	MAIN[9][29][59]
DRP[23] bit 8	MAIN[2][29][60]	MAIN[9][29][60]
DRP[23] bit 9	MAIN[2][28][60]	MAIN[9][28][60]
DRP[23] bit 10	MAIN[2][28][61]	MAIN[9][28][61]
DRP[23] bit 11	MAIN[2][29][61]	MAIN[9][29][61]
DRP[23] bit 12	MAIN[2][29][62]	MAIN[9][29][62]
DRP[23] bit 13	MAIN[2][28][62]	MAIN[9][28][62]
DRP[23] bit 14	MAIN[2][28][63]	MAIN[9][28][63]
DRP[23] bit 15	MAIN[2][29][63]	MAIN[9][29][63]
OUT_CLK0_ENABLE	MAIN[2][29][34]	MAIN[9][29][34]
OUT_CLK90_ENABLE	MAIN[2][28][34]	MAIN[9][28][34]
OUT_CLK180_ENABLE	MAIN[2][28][35]	MAIN[9][28][35]
OUT_CLK270_ENABLE	MAIN[2][29][35]	MAIN[9][29][35]
OUT_CLK2X_ENABLE	MAIN[2][29][36]	MAIN[9][29][36]
OUT_CLK2X180_ENABLE	MAIN[2][28][36]	MAIN[9][28][36]
OUT_CLKDV_ENABLE	MAIN[2][28][37]	MAIN[9][28][37]
OUT_CLKFX_ENABLE	MAIN[0][29][56]	MAIN[7][29][56]
OUT_CLKFX180_ENABLE	MAIN[0][28][56]	MAIN[7][28][56]
OUT_CONCUR_ENABLE	MAIN[0][28][57]	MAIN[7][28][57]
CLKDV_COUNT_MAX bit 0	MAIN[2][29][24]	MAIN[9][29][24]
CLKDV_COUNT_MAX bit 1	MAIN[2][28][24]	MAIN[9][28][24]
CLKDV_COUNT_MAX bit 2	MAIN[2][28][25]	MAIN[9][28][25]
CLKDV_COUNT_MAX bit 3	MAIN[2][29][25]	MAIN[9][29][25]
CLKDV_COUNT_FALL bit 0	MAIN[2][29][26]	MAIN[9][29][26]
CLKDV_COUNT_FALL bit 1	MAIN[2][28][26]	MAIN[9][28][26]
CLKDV_COUNT_FALL bit 2	MAIN[2][28][27]	MAIN[9][28][27]
CLKDV_COUNT_FALL bit 3	MAIN[2][29][27]	MAIN[9][29][27]
CLKDV_COUNT_FALL_2 bit 0	MAIN[2][29][28]	MAIN[9][29][28]
CLKDV_COUNT_FALL_2 bit 1	MAIN[2][28][28]	MAIN[9][28][28]
CLKDV_COUNT_FALL_2 bit 2	MAIN[2][28][29]	MAIN[9][28][29]
CLKDV_COUNT_FALL_2 bit 3	MAIN[2][29][29]	MAIN[9][29][29]
CLKDV_PHASE_RISE bit 0	MAIN[2][29][30]	MAIN[9][29][30]
CLKDV_PHASE_RISE bit 1	MAIN[2][28][30]	MAIN[9][28][30]
CLKDV_PHASE_FALL bit 0	MAIN[2][28][31]	MAIN[9][28][31]
CLKDV_PHASE_FALL bit 1	MAIN[2][29][31]	MAIN[9][29][31]
CLKDV_MODE	[enum: DCM_CLKDV_MODE]	[enum: DCM_CLKDV_MODE]
STARTUP_WAIT	MAIN[2][28][57]	MAIN[9][28][57]
DESKEW_ADJUST bit 0	MAIN[0][29][25]	MAIN[7][29][25]
DESKEW_ADJUST bit 1	MAIN[0][29][26]	MAIN[7][29][26]
DESKEW_ADJUST bit 2	MAIN[0][28][26]	MAIN[7][28][26]
DESKEW_ADJUST bit 3	MAIN[0][28][27]	MAIN[7][28][27]
DESKEW_ADJUST bit 4	MAIN[0][29][27]	MAIN[7][29][27]
CLKIN_DIVIDE_BY_2	MAIN[0][28][37]	MAIN[7][28][37]
CLKIN_CLKFB_ENABLE	MAIN[1][28][11]	MAIN[8][28][11]
CLKFX_MULTIPLY bit 0	MAIN[2][29][4]	MAIN[9][29][4]
CLKFX_MULTIPLY bit 1	MAIN[2][28][4]	MAIN[9][28][4]
CLKFX_MULTIPLY bit 2	MAIN[2][28][5]	MAIN[9][28][5]
CLKFX_MULTIPLY bit 3	MAIN[2][29][5]	MAIN[9][29][5]
CLKFX_MULTIPLY bit 4	MAIN[2][29][6]	MAIN[9][29][6]
CLKFX_MULTIPLY bit 5	MAIN[2][28][6]	MAIN[9][28][6]
CLKFX_MULTIPLY bit 6	MAIN[2][28][7]	MAIN[9][28][7]
CLKFX_MULTIPLY bit 7	MAIN[2][29][7]	MAIN[9][29][7]
CLKFX_DIVIDE bit 0	MAIN[2][29][0]	MAIN[9][29][0]
CLKFX_DIVIDE bit 1	MAIN[2][28][0]	MAIN[9][28][0]
CLKFX_DIVIDE bit 2	MAIN[2][28][1]	MAIN[9][28][1]
CLKFX_DIVIDE bit 3	MAIN[2][29][1]	MAIN[9][29][1]
CLKFX_DIVIDE bit 4	MAIN[2][29][2]	MAIN[9][29][2]
CLKFX_DIVIDE bit 5	MAIN[2][28][2]	MAIN[9][28][2]
CLKFX_DIVIDE bit 6	MAIN[2][28][3]	MAIN[9][28][3]
CLKFX_DIVIDE bit 7	MAIN[2][29][3]	MAIN[9][29][3]
FACTORY_JF bit 0	MAIN[1][29][56]	MAIN[8][29][56]
FACTORY_JF bit 1	MAIN[1][28][56]	MAIN[8][28][56]
FACTORY_JF bit 2	MAIN[1][28][57]	MAIN[8][28][57]
FACTORY_JF bit 3	MAIN[1][29][57]	MAIN[8][29][57]
FACTORY_JF bit 4	MAIN[1][29][58]	MAIN[8][29][58]
FACTORY_JF bit 5	MAIN[1][28][58]	MAIN[8][28][58]
FACTORY_JF bit 6	MAIN[1][28][59]	MAIN[8][28][59]
FACTORY_JF bit 7	MAIN[1][29][59]	MAIN[8][29][59]
FACTORY_JF bit 8	MAIN[1][29][60]	MAIN[8][29][60]
FACTORY_JF bit 9	MAIN[1][28][60]	MAIN[8][28][60]
FACTORY_JF bit 10	MAIN[1][28][61]	MAIN[8][28][61]
FACTORY_JF bit 11	MAIN[1][29][61]	MAIN[8][29][61]
FACTORY_JF bit 12	MAIN[1][29][62]	MAIN[8][29][62]
FACTORY_JF bit 13	MAIN[1][28][62]	MAIN[8][28][62]
FACTORY_JF bit 14	MAIN[1][28][63]	MAIN[8][28][63]
FACTORY_JF bit 15	MAIN[1][29][63]	MAIN[8][29][63]
PHASE_SHIFT bit 0	MAIN[2][29][40]	MAIN[9][29][40]
PHASE_SHIFT bit 1	MAIN[2][28][40]	MAIN[9][28][40]
PHASE_SHIFT bit 2	MAIN[2][28][41]	MAIN[9][28][41]
PHASE_SHIFT bit 3	MAIN[2][29][41]	MAIN[9][29][41]
PHASE_SHIFT bit 4	MAIN[2][29][42]	MAIN[9][29][42]
PHASE_SHIFT bit 5	MAIN[2][28][42]	MAIN[9][28][42]
PHASE_SHIFT bit 6	MAIN[2][28][43]	MAIN[9][28][43]
PHASE_SHIFT bit 7	MAIN[2][29][43]	MAIN[9][29][43]
PHASE_SHIFT bit 8	MAIN[2][29][44]	MAIN[9][29][44]
PHASE_SHIFT bit 9	MAIN[2][28][44]	MAIN[9][28][44]
PHASE_SHIFT_NEGATIVE	MAIN[2][28][45]	MAIN[9][28][45]
PS_CENTERED	MAIN[1][28][25]	MAIN[8][28][25]
PS_DIRECT	MAIN[1][29][25]	MAIN[8][29][25]
PS_ENABLE	MAIN[2][29][11]	MAIN[9][29][11]
PS_MODE	[enum: DCM_PS_MODE]	[enum: DCM_PS_MODE]
DCM_CLKDV_CLKFX_ALIGNMENT	MAIN[0][29][60]	MAIN[7][29][60]
DCM_CLKFB_IODLY_MUXINSEL	[enum: DCM_IODLY_MUX]	[enum: DCM_IODLY_MUX]
DCM_CLKFB_IODLY_MUXOUT_SEL	[enum: DCM_IODLY_MUX]	[enum: DCM_IODLY_MUX]
DCM_CLKIN_IODLY_MUXINSEL	[enum: DCM_IODLY_MUX]	[enum: DCM_IODLY_MUX]
DCM_CLKIN_IODLY_MUXOUT_SEL	[enum: DCM_IODLY_MUX]	[enum: DCM_IODLY_MUX]
DCM_CLKLOST_EN	MAIN[2][28][33]	MAIN[9][28][33]
DCM_COMMON_MSB_SEL bit 0	MAIN[2][28][62]	MAIN[9][28][62]
DCM_COMMON_MSB_SEL bit 1	MAIN[2][28][63]	MAIN[9][28][63]
DCM_COM_PWC_FB_EN	MAIN[0][28][32]	MAIN[7][28][32]
DCM_COM_PWC_FB_TAP bit 0	MAIN[0][28][30]	MAIN[7][28][30]
DCM_COM_PWC_FB_TAP bit 1	MAIN[0][28][31]	MAIN[7][28][31]
DCM_COM_PWC_FB_TAP bit 2	MAIN[0][29][31]	MAIN[7][29][31]
DCM_COM_PWC_REF_EN	MAIN[0][29][32]	MAIN[7][29][32]
DCM_COM_PWC_REF_TAP bit 0	MAIN[0][28][29]	MAIN[7][28][29]
DCM_COM_PWC_REF_TAP bit 1	MAIN[0][29][29]	MAIN[7][29][29]
DCM_COM_PWC_REF_TAP bit 2	MAIN[0][29][30]	MAIN[7][29][30]
DCM_EXT_FB_EN	MAIN[0][28][33]	MAIN[7][28][33]
DCM_LOCK_HIGH_B	!MAIN[2][29][33]	!MAIN[9][29][33]
DCM_PLL_RST_DCM	MAIN[0][28][28]	MAIN[7][28][28]
DCM_POWERDOWN_COMMON_EN_B	!MAIN[2][28][61]	!MAIN[9][28][61]
DCM_REG_PWRD_CFG	MAIN[1][29][15]	MAIN[8][29][15]
DCM_SCANMODE	MAIN[1][28][32]	MAIN[8][28][32]
DCM_TRIM_CAL bit 0	MAIN[2][29][37]	MAIN[9][29][37]
DCM_TRIM_CAL bit 1	MAIN[2][29][38]	MAIN[9][29][38]
DCM_TRIM_CAL bit 2	MAIN[2][28][38]	MAIN[9][28][38]
DCM_UNUSED_TAPS_POWERDOWN bit 0	MAIN[0][28][58]	MAIN[7][28][58]
DCM_UNUSED_TAPS_POWERDOWN bit 1	MAIN[1][28][39]	MAIN[8][28][39]
DCM_UNUSED_TAPS_POWERDOWN bit 2	MAIN[1][29][32]	MAIN[8][29][32]
DCM_UNUSED_TAPS_POWERDOWN bit 3	MAIN[1][29][38]	MAIN[8][29][38]
DCM_USE_REG_READY	MAIN[0][29][33]	MAIN[7][29][33]
DCM_VREG_ENABLE	MAIN[2][29][55]	MAIN[9][29][55]
DCM_VBG_PD bit 0	MAIN[2][29][61]	MAIN[9][29][61]
DCM_VBG_PD bit 1	MAIN[2][29][62]	MAIN[9][29][62]
DCM_VBG_SEL bit 0	MAIN[2][29][57]	MAIN[9][29][57]
DCM_VBG_SEL bit 1	MAIN[2][29][58]	MAIN[9][29][58]
DCM_VBG_SEL bit 2	MAIN[2][29][59]	MAIN[9][29][59]
DCM_VBG_SEL bit 3	MAIN[2][29][60]	MAIN[9][29][60]
DCM_VSPLY_VALID_ACC bit 0	MAIN[2][29][56]	MAIN[9][29][56]
DCM_VSPLY_VALID_ACC bit 1	MAIN[2][29][63]	MAIN[9][29][63]
DCM_WAIT_PLL	MAIN[0][28][36]	MAIN[7][28][36]
DLL_CLKFB_STOPPED_PWRD_EN_B	!MAIN[2][29][8]	!MAIN[9][29][8]
DLL_CLKIN_STOPPED_PWRD_EN_B	!MAIN[2][28][8]	!MAIN[9][28][8]
DLL_DEAD_TIME bit 0	MAIN[2][29][20]	MAIN[9][29][20]
DLL_DEAD_TIME bit 1	MAIN[2][28][20]	MAIN[9][28][20]
DLL_DEAD_TIME bit 2	MAIN[2][28][21]	MAIN[9][28][21]
DLL_DEAD_TIME bit 3	MAIN[2][29][21]	MAIN[9][29][21]
DLL_DEAD_TIME bit 4	MAIN[2][29][22]	MAIN[9][29][22]
DLL_DEAD_TIME bit 5	MAIN[2][28][22]	MAIN[9][28][22]
DLL_DEAD_TIME bit 6	MAIN[2][28][23]	MAIN[9][28][23]
DLL_DEAD_TIME bit 7	MAIN[2][29][23]	MAIN[9][29][23]
DLL_DESKEW_LOCK_BY1	MAIN[1][28][37]	MAIN[8][28][37]
DLL_DESKEW_MAXTAP bit 0	MAIN[1][29][52]	MAIN[8][29][52]
DLL_DESKEW_MAXTAP bit 1	MAIN[1][28][52]	MAIN[8][28][52]
DLL_DESKEW_MAXTAP bit 2	MAIN[1][28][53]	MAIN[8][28][53]
DLL_DESKEW_MAXTAP bit 3	MAIN[1][29][53]	MAIN[8][29][53]
DLL_DESKEW_MAXTAP bit 4	MAIN[1][29][54]	MAIN[8][29][54]
DLL_DESKEW_MAXTAP bit 5	MAIN[1][28][54]	MAIN[8][28][54]
DLL_DESKEW_MAXTAP bit 6	MAIN[1][28][55]	MAIN[8][28][55]
DLL_DESKEW_MAXTAP bit 7	MAIN[1][29][55]	MAIN[8][29][55]
DLL_DESKEW_MINTAP bit 0	MAIN[1][29][48]	MAIN[8][29][48]
DLL_DESKEW_MINTAP bit 1	MAIN[1][28][48]	MAIN[8][28][48]
DLL_DESKEW_MINTAP bit 2	MAIN[1][28][49]	MAIN[8][28][49]
DLL_DESKEW_MINTAP bit 3	MAIN[1][29][49]	MAIN[8][29][49]
DLL_DESKEW_MINTAP bit 4	MAIN[1][29][50]	MAIN[8][29][50]
DLL_DESKEW_MINTAP bit 5	MAIN[1][28][50]	MAIN[8][28][50]
DLL_DESKEW_MINTAP bit 6	MAIN[1][28][51]	MAIN[8][28][51]
DLL_DESKEW_MINTAP bit 7	MAIN[1][29][51]	MAIN[8][29][51]
DLL_ETPP_HOLD	MAIN[2][28][58]	MAIN[9][28][58]
DLL_FDBKLOST_EN	MAIN[2][28][32]	MAIN[9][28][32]
DLL_FREQUENCY_MODE	[enum: DCM_DLL_FREQUENCY_MODE]	[enum: DCM_DLL_FREQUENCY_MODE]
DLL_LIVE_TIME bit 0	MAIN[2][29][16]	MAIN[9][29][16]
DLL_LIVE_TIME bit 1	MAIN[2][28][16]	MAIN[9][28][16]
DLL_LIVE_TIME bit 2	MAIN[2][28][17]	MAIN[9][28][17]
DLL_LIVE_TIME bit 3	MAIN[2][29][17]	MAIN[9][29][17]
DLL_LIVE_TIME bit 4	MAIN[2][29][18]	MAIN[9][29][18]
DLL_LIVE_TIME bit 5	MAIN[2][28][18]	MAIN[9][28][18]
DLL_LIVE_TIME bit 6	MAIN[2][28][19]	MAIN[9][28][19]
DLL_LIVE_TIME bit 7	MAIN[2][29][19]	MAIN[9][29][19]
DLL_PERIOD_LOCK_BY1	MAIN[1][28][36]	MAIN[8][28][36]
DLL_PHASE_SHIFT_CALIBRATION	[enum: DCM_DLL_PHASE_SHIFT_CALIBRATION]	[enum: DCM_DLL_PHASE_SHIFT_CALIBRATION]
DLL_PHASE_SHIFT_LFC bit 0	MAIN[2][29][48]	MAIN[9][29][48]
DLL_PHASE_SHIFT_LFC bit 1	MAIN[2][28][48]	MAIN[9][28][48]
DLL_PHASE_SHIFT_LFC bit 2	MAIN[2][28][49]	MAIN[9][28][49]
DLL_PHASE_SHIFT_LFC bit 3	MAIN[2][29][49]	MAIN[9][29][49]
DLL_PHASE_SHIFT_LFC bit 4	MAIN[2][29][50]	MAIN[9][29][50]
DLL_PHASE_SHIFT_LFC bit 5	MAIN[2][28][50]	MAIN[9][28][50]
DLL_PHASE_SHIFT_LFC bit 6	MAIN[2][28][51]	MAIN[9][28][51]
DLL_PHASE_SHIFT_LFC bit 7	MAIN[2][29][51]	MAIN[9][29][51]
DLL_PHASE_SHIFT_LFC bit 8	MAIN[2][29][52]	MAIN[9][29][52]
DLL_PHASE_SHIFT_LOCK_BY1	MAIN[1][29][26]	MAIN[8][29][26]
DLL_PWRD_STICKY_B	!MAIN[2][28][59]	!MAIN[9][28][59]
DLL_PWRD_ON_SCANMODE_B	!MAIN[1][28][35]	!MAIN[8][28][35]
DLL_SETTLE_TIME bit 0	MAIN[2][29][12]	MAIN[9][29][12]
DLL_SETTLE_TIME bit 1	MAIN[2][28][12]	MAIN[9][28][12]
DLL_SETTLE_TIME bit 2	MAIN[2][28][13]	MAIN[9][28][13]
DLL_SETTLE_TIME bit 3	MAIN[2][29][13]	MAIN[9][29][13]
DLL_SETTLE_TIME bit 4	MAIN[2][29][14]	MAIN[9][29][14]
DLL_SETTLE_TIME bit 5	MAIN[2][28][14]	MAIN[9][28][14]
DLL_SETTLE_TIME bit 6	MAIN[2][28][15]	MAIN[9][28][15]
DLL_SETTLE_TIME bit 7	MAIN[2][29][15]	MAIN[9][29][15]
DLL_SYNTH_CLOCK_SPEED	[enum: DCM_DLL_SYNTH_CLOCK_SPEED]	[enum: DCM_DLL_SYNTH_CLOCK_SPEED]
DLL_TAPINIT_CTL bit 0	MAIN[1][28][33]	MAIN[8][28][33]
DLL_TAPINIT_CTL bit 1	MAIN[1][29][33]	MAIN[8][29][33]
DLL_TAPINIT_CTL bit 2	MAIN[1][29][34]	MAIN[8][29][34]
DLL_TEST_MUX_SEL bit 0	MAIN[2][28][39]	MAIN[9][28][39]
DLL_TEST_MUX_SEL bit 1	MAIN[2][29][39]	MAIN[9][29][39]
DLL_ZD1_EN	MAIN[2][28][11]	MAIN[9][28][11]
DLL_ZD1_JF_OVERFLOW_HOLD	MAIN[1][28][38]	MAIN[8][28][38]
DLL_ZD1_PHASE_SEL_INIT bit 0	MAIN[1][29][35]	MAIN[8][29][35]
DLL_ZD1_PHASE_SEL_INIT bit 1	MAIN[1][29][36]	MAIN[8][29][36]
DLL_ZD1_PWC_EN	MAIN[2][28][56]	MAIN[9][28][56]
DLL_ZD1_PWC_TAP bit 0	MAIN[2][29][54]	MAIN[9][29][54]
DLL_ZD1_PWC_TAP bit 1	MAIN[2][28][54]	MAIN[9][28][54]
DLL_ZD1_PWC_TAP bit 2	MAIN[2][28][55]	MAIN[9][28][55]
DLL_ZD1_TAP_INIT bit 0	MAIN[1][29][44]	MAIN[8][29][44]
DLL_ZD1_TAP_INIT bit 1	MAIN[1][28][44]	MAIN[8][28][44]
DLL_ZD1_TAP_INIT bit 2	MAIN[1][28][45]	MAIN[8][28][45]
DLL_ZD1_TAP_INIT bit 3	MAIN[1][29][45]	MAIN[8][29][45]
DLL_ZD1_TAP_INIT bit 4	MAIN[1][29][46]	MAIN[8][29][46]
DLL_ZD1_TAP_INIT bit 5	MAIN[1][28][46]	MAIN[8][28][46]
DLL_ZD1_TAP_INIT bit 6	MAIN[1][28][47]	MAIN[8][28][47]
DLL_ZD1_TAP_INIT bit 7	MAIN[1][29][47]	MAIN[8][29][47]
DLL_ZD2_EN	MAIN[2][28][10]	MAIN[9][28][10]
DLL_ZD2_JF_OVERFLOW_HOLD	MAIN[1][29][37]	MAIN[8][29][37]
DLL_ZD2_PWC_EN	MAIN[2][28][60]	MAIN[9][28][60]
DLL_ZD2_PWC_TAP bit 0	MAIN[2][28][52]	MAIN[9][28][52]
DLL_ZD2_PWC_TAP bit 1	MAIN[2][28][53]	MAIN[9][28][53]
DLL_ZD2_PWC_TAP bit 2	MAIN[2][29][53]	MAIN[9][29][53]
DLL_ZD2_TAP_INIT bit 0	MAIN[1][29][40]	MAIN[8][29][40]
DLL_ZD2_TAP_INIT bit 1	MAIN[1][28][40]	MAIN[8][28][40]
DLL_ZD2_TAP_INIT bit 2	MAIN[1][28][41]	MAIN[8][28][41]
DLL_ZD2_TAP_INIT bit 3	MAIN[1][29][41]	MAIN[8][29][41]
DLL_ZD2_TAP_INIT bit 4	MAIN[1][29][42]	MAIN[8][29][42]
DLL_ZD2_TAP_INIT bit 5	MAIN[1][28][42]	MAIN[8][28][42]
DLL_ZD2_TAP_INIT bit 6	MAIN[1][28][43]	MAIN[8][28][43]
DFS_AVE_FREQ_GAIN	[enum: DCM_DFS_AVE_FREQ_GAIN]	[enum: DCM_DFS_AVE_FREQ_GAIN]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 0	MAIN[0][28][62]	MAIN[7][28][62]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 1	MAIN[0][28][63]	MAIN[7][28][63]
DFS_AVE_FREQ_SAMPLE_INTERVAL bit 2	MAIN[0][29][63]	MAIN[7][29][63]
DFS_CFG_BYPASS	MAIN[0][29][9]	MAIN[7][29][9]
DFS_CUSTOM_FAST_SYNC bit 0	MAIN[0][28][60]	MAIN[7][28][60]
DFS_CUSTOM_FAST_SYNC bit 1	MAIN[0][28][61]	MAIN[7][28][61]
DFS_CUSTOM_FAST_SYNC bit 2	MAIN[0][29][61]	MAIN[7][29][61]
DFS_CUSTOM_FAST_SYNC bit 3	MAIN[0][29][62]	MAIN[7][29][62]
DFS_EARLY_LOCK	MAIN[0][28][12]	MAIN[7][28][12]
DFS_EN	MAIN[0][28][39]	MAIN[7][28][39]
DFS_EN_RELRST_B	!MAIN[0][29][58]	!MAIN[7][29][58]
DFS_FAST_UPDATE	MAIN[0][29][39]	MAIN[7][29][39]
DFS_FREQUENCY_MODE	[enum: DCM_DFS_FREQUENCY_MODE]	[enum: DCM_DFS_FREQUENCY_MODE]
DFS_HARDSYNC_B bit 0	MAIN[0][28][15]	MAIN[7][28][15]
DFS_HARDSYNC_B bit 1	MAIN[0][29][15]	MAIN[7][29][15]
DFS_HF_TRIM_CAL bit 0	MAIN[0][28][20]	MAIN[7][28][20]
DFS_HF_TRIM_CAL bit 1	MAIN[0][28][21]	MAIN[7][28][21]
DFS_HF_TRIM_CAL bit 2	MAIN[0][29][21]	MAIN[7][29][21]
DFS_JF_LOWER_LIMIT bit 0	MAIN[0][29][17]	MAIN[7][29][17]
DFS_JF_LOWER_LIMIT bit 1	MAIN[0][29][18]	MAIN[7][29][18]
DFS_JF_LOWER_LIMIT bit 2	MAIN[0][28][18]	MAIN[7][28][18]
DFS_JF_LOWER_LIMIT bit 3	MAIN[0][28][19]	MAIN[7][28][19]
DFS_MPW_LOW	MAIN[0][28][59]	MAIN[7][28][59]
DFS_MPW_HIGH	MAIN[0][29][59]	MAIN[7][29][59]
DFS_OSC_ON_FX	MAIN[0][29][19]	MAIN[7][29][19]
DFS_OSCILLATOR_MODE	[enum: DCM_DFS_OSCILLATOR_MODE]	[enum: DCM_DFS_OSCILLATOR_MODE]
DFS_OUTPUT_PSDLY_ON_CONCUR	MAIN[0][29][57]	MAIN[7][29][57]
DFS_PWRD_CLKIN_STOP_B	!MAIN[0][29][23]	!MAIN[7][29][23]
DFS_PWRD_CLKIN_STOP_STICKY_B	!MAIN[0][28][23]	!MAIN[7][28][23]
DFS_PWRD_REPLY_TIMES_OUT_B	!MAIN[0][28][22]	!MAIN[7][28][22]
DFS_REF_ON_FX	MAIN[0][29][20]	MAIN[7][29][20]
DFS_SYNC_TO_DLL	MAIN[0][28][38]	MAIN[7][28][38]
DFS_SYNTH_CLOCK_SPEED bit 0	MAIN[0][28][35]	MAIN[7][28][35]
DFS_SYNTH_CLOCK_SPEED bit 1	MAIN[0][29][35]	MAIN[7][29][35]
DFS_SYNTH_CLOCK_SPEED bit 2	MAIN[0][29][36]	MAIN[7][29][36]
DFS_SYNTH_FAST_SYNCH bit 0	MAIN[0][29][10]	MAIN[7][29][10]
DFS_SYNTH_FAST_SYNCH bit 1	MAIN[0][28][10]	MAIN[7][28][10]
DFS_TAPTRIM bit 0	MAIN[0][29][40]	MAIN[7][29][40]
DFS_TAPTRIM bit 1	MAIN[0][28][40]	MAIN[7][28][40]
DFS_TAPTRIM bit 2	MAIN[0][28][41]	MAIN[7][28][41]
DFS_TAPTRIM bit 3	MAIN[0][29][41]	MAIN[7][29][41]
DFS_TAPTRIM bit 4	MAIN[0][29][42]	MAIN[7][29][42]
DFS_TAPTRIM bit 5	MAIN[0][28][42]	MAIN[7][28][42]
DFS_TAPTRIM bit 6	MAIN[0][28][43]	MAIN[7][28][43]
DFS_TAPTRIM bit 7	MAIN[0][29][43]	MAIN[7][29][43]
DFS_TAPTRIM bit 8	MAIN[0][29][44]	MAIN[7][29][44]
DFS_TAPTRIM bit 9	MAIN[0][28][44]	MAIN[7][28][44]
DFS_TAPTRIM bit 10	MAIN[0][28][45]	MAIN[7][28][45]
DFS_TWEAK bit 0	MAIN[0][29][48]	MAIN[7][29][48]
DFS_TWEAK bit 1	MAIN[0][28][48]	MAIN[7][28][48]
DFS_TWEAK bit 2	MAIN[0][28][49]	MAIN[7][28][49]
DFS_TWEAK bit 3	MAIN[0][29][49]	MAIN[7][29][49]
DFS_TWEAK bit 4	MAIN[0][29][50]	MAIN[7][29][50]
DFS_TWEAK bit 5	MAIN[0][28][50]	MAIN[7][28][50]
DFS_TWEAK bit 6	MAIN[0][28][51]	MAIN[7][28][51]
DFS_TWEAK bit 7	MAIN[0][29][51]	MAIN[7][29][51]

virtex5 CMT enum DCM_CLKDV_MODE
DCM[0].CLKDV_MODE	MAIN[2][29][32]
DCM[1].CLKDV_MODE	MAIN[9][29][32]
HALF	0
INT	1

virtex5 CMT enum DCM_PS_MODE
DCM[0].PS_MODE	MAIN[2][29][10]
DCM[1].PS_MODE	MAIN[9][29][10]
CLKIN	1
CLKFB	0

virtex5 CMT enum DCM_IODLY_MUX
DCM[0].DCM_CLKFB_IODLY_MUXINSEL	MAIN[0][29][38]
DCM[1].DCM_CLKFB_IODLY_MUXINSEL	MAIN[7][29][38]
DCM[0].DCM_CLKFB_IODLY_MUXOUT_SEL	MAIN[0][29][24]
DCM[1].DCM_CLKFB_IODLY_MUXOUT_SEL	MAIN[7][29][24]
DCM[0].DCM_CLKIN_IODLY_MUXINSEL	MAIN[0][29][37]
DCM[1].DCM_CLKIN_IODLY_MUXINSEL	MAIN[7][29][37]
DCM[0].DCM_CLKIN_IODLY_MUXOUT_SEL	MAIN[0][28][24]
DCM[1].DCM_CLKIN_IODLY_MUXOUT_SEL	MAIN[7][28][24]
PASS	0
DELAY_LINE	1

virtex5 CMT enum DCM_DLL_FREQUENCY_MODE
DCM[0].DLL_FREQUENCY_MODE	MAIN[2][29][9]	MAIN[2][28][9]
DCM[1].DLL_FREQUENCY_MODE	MAIN[9][29][9]	MAIN[9][28][9]
LOW	0	0
HIGH	1	1

virtex5 CMT enum DCM_DLL_PHASE_SHIFT_CALIBRATION
DCM[0].DLL_PHASE_SHIFT_CALIBRATION	MAIN[1][28][24]	MAIN[1][29][24]
DCM[1].DLL_PHASE_SHIFT_CALIBRATION	MAIN[8][28][24]	MAIN[8][29][24]
AUTO_DPS	0	0
CONFIG	0	1
MASK	1	0
AUTO_ZD2	1	1

virtex5 CMT enum DCM_DLL_SYNTH_CLOCK_SPEED
DCM[0].DLL_SYNTH_CLOCK_SPEED	MAIN[0][28][34]	MAIN[0][29][34]
DCM[1].DLL_SYNTH_CLOCK_SPEED	MAIN[7][28][34]	MAIN[7][29][34]
NORMAL	0	0
HALF	0	1
QUARTER	1	0
VDD	1	1

virtex5 CMT enum DCM_DFS_AVE_FREQ_GAIN
DCM[0].DFS_AVE_FREQ_GAIN	MAIN[0][29][12]	MAIN[0][28][11]	MAIN[0][29][11]
DCM[1].DFS_AVE_FREQ_GAIN	MAIN[7][29][12]	MAIN[7][28][11]	MAIN[7][29][11]
NONE	0	0	0
_0P5	0	1	1
_0P25	0	0	1
_0P125	0	1	0
_1P0	1	0	0
_2P0	1	1	0
_4P0	1	0	1
_8P0	1	1	1

virtex5 CMT enum DCM_DFS_FREQUENCY_MODE
DCM[0].DFS_FREQUENCY_MODE	MAIN[0][28][9]
DCM[1].DFS_FREQUENCY_MODE	MAIN[7][28][9]
LOW	0
HIGH	1

virtex5 CMT enum DCM_DFS_OSCILLATOR_MODE
DCM[0].DFS_OSCILLATOR_MODE	MAIN[0][28][8]
DCM[1].DFS_OSCILLATOR_MODE	MAIN[7][28][8]
PHASE_FREQ_LOCK	0
AVE_FREQ_LOCK	1

Bels PLL_V5

virtex5 CMT bel PLL_V5 pins
Pin	Direction	PLL[0]
CLKIN1	in	CELL[0].IMUX_PLL_CLKIN1
CLKIN2	in	CELL[0].IMUX_PLL_CLKIN2
CLKINSEL	in	CELL[4].IMUX_IMUX[30] invert by !MAIN[6][29][44]
CLKFBIN	in	CELL[0].IMUX_PLL_CLKFB
RST	in	CELL[4].IMUX_CTRL_SITE[0] invert by MAIN[6][29][40]
REL	in	CELL[4].IMUX_IMUX[19] invert by MAIN[6][29][41]
DCLK	in	CELL[5].IMUX_CLK[0]
DEN	in	CELL[5].IMUX_IMUX[38]
DWE	in	CELL[5].IMUX_IMUX[9]
DADDR[0]	in	CELL[5].IMUX_IMUX[20]
DADDR[1]	in	CELL[5].IMUX_IMUX[37]
DADDR[2]	in	CELL[5].IMUX_IMUX[1]
DADDR[3]	in	CELL[5].IMUX_IMUX[12]
DADDR[4]	in	CELL[4].IMUX_IMUX[35]
DI[0]	in	CELL[6].IMUX_IMUX[15]
DI[1]	in	CELL[6].IMUX_IMUX[9]
DI[2]	in	CELL[6].IMUX_IMUX[3]
DI[3]	in	CELL[6].IMUX_IMUX[44]
DI[4]	in	CELL[6].IMUX_IMUX[20]
DI[5]	in	CELL[6].IMUX_IMUX[2]
DI[6]	in	CELL[6].IMUX_IMUX[13]
DI[7]	in	CELL[6].IMUX_IMUX[19]
DI[8]	in	CELL[6].IMUX_IMUX[30]
DI[9]	in	CELL[6].IMUX_IMUX[12]
DI[10]	in	CELL[5].IMUX_IMUX[35]
DI[11]	in	CELL[5].IMUX_IMUX[41]
DI[12]	in	CELL[5].IMUX_IMUX[46]
DI[13]	in	CELL[5].IMUX_IMUX[28]
DI[14]	in	CELL[5].IMUX_IMUX[45]
DI[15]	in	CELL[5].IMUX_IMUX[4]
CLKBRST	in	CELL[5].IMUX_IMUX[19] invert by MAIN[6][29][42]
ENOUTSYNC	in	CELL[4].IMUX_IMUX[0] invert by MAIN[6][28][42]
MANPDLF	in	CELL[3].IMUX_IMUX[37] invert by MAIN[6][28][40]
MANPULF	in	CELL[3].IMUX_IMUX[2] invert by MAIN[6][28][41]
SKEWRST	in	CELL[3].IMUX_IMUX[28] invert by MAIN[6][29][47]
SKEWSTB	in	CELL[3].IMUX_CLK[1] invert by MAIN[6][28][47]
SKEWCLKIN1	in	CELL[0].OMUX_PLL_SKEWCLKIN2 invert by MAIN[6][29][46]
SKEWCLKIN2	in	CELL[0].OMUX_PLL_SKEWCLKIN1 invert by MAIN[6][28][46]
TEST_CLKIN	out	CELL[0].TEST_PLL_CLKIN
CLKOUT0	out	CELL[0].OUT_CMT[12]
CLKOUT1	out	CELL[0].OUT_CMT[13]
CLKOUT2	out	CELL[0].OUT_CMT[14]
CLKOUT3	out	CELL[0].OUT_CMT[15]
CLKOUT4	out	CELL[0].OUT_CMT[16]
CLKOUT5	out	CELL[0].OUT_CMT[17]
CLKFBOUT	out	CELL[0].OUT_CMT[11]
CLKOUTDCM0	out	CELL[0].OUT_PLL_CLKOUTDCM[0]
CLKOUTDCM1	out	CELL[0].OUT_PLL_CLKOUTDCM[1]
CLKOUTDCM2	out	CELL[0].OUT_PLL_CLKOUTDCM[2]
CLKOUTDCM3	out	CELL[0].OUT_PLL_CLKOUTDCM[3]
CLKOUTDCM4	out	CELL[0].OUT_PLL_CLKOUTDCM[4]
CLKOUTDCM5	out	CELL[0].OUT_PLL_CLKOUTDCM[5]
CLKFBDCM	out	CELL[0].OUT_PLL_CLKFBDCM
LOCKED	out	CELL[3].OUT_BEL[21], CELL[4].OUT_BEL[22]
DRDY	out	CELL[5].OUT_BEL[9]
DO[0]	out	CELL[6].OUT_BEL[3]
DO[1]	out	CELL[6].OUT_BEL[6]
DO[2]	out	CELL[6].OUT_BEL[20]
DO[3]	out	CELL[6].OUT_BEL[23]
DO[4]	out	CELL[6].OUT_BEL[19]
DO[5]	out	CELL[6].OUT_BEL[13]
DO[6]	out	CELL[6].OUT_BEL[1]
DO[7]	out	CELL[6].OUT_BEL[4]
DO[8]	out	CELL[6].OUT_BEL[18]
DO[9]	out	CELL[6].OUT_BEL[8]
DO[10]	out	CELL[5].OUT_BEL[11]
DO[11]	out	CELL[5].OUT_BEL[17]
DO[12]	out	CELL[5].OUT_BEL[7]
DO[13]	out	CELL[5].OUT_BEL[2]
DO[14]	out	CELL[5].OUT_BEL[14]
DO[15]	out	CELL[5].OUT_BEL[16]
TEST[0]	out	CELL[3].OUT_BEL[19]
TEST[1]	out	CELL[3].OUT_BEL[9]
TEST[2]	out	CELL[3].OUT_BEL[23]
TEST[3]	out	CELL[3].OUT_BEL[20]
TEST[4]	out	CELL[3].OUT_BEL[16]
TEST[5]	out	CELL[3].OUT_BEL[3]
TEST[6]	out	CELL[3].OUT_BEL[2]
TEST[7]	out	CELL[3].OUT_BEL[7]
TEST[8]	out	CELL[3].OUT_BEL[15]
TEST[9]	out	CELL[3].OUT_BEL[17]
TEST[10]	out	CELL[3].OUT_BEL[11]
TEST[11]	out	CELL[4].OUT_BEL[8]
TEST[12]	out	CELL[4].OUT_BEL[18]
TEST[13]	out	CELL[4].OUT_BEL[4]
TEST[14]	out	CELL[4].OUT_BEL[1]
TEST[15]	out	CELL[4].OUT_BEL[5]
TEST[16]	out	CELL[4].OUT_BEL[13]
TEST[17]	out	CELL[3].OUT_BEL[10]
TEST[18]	out	CELL[4].OUT_BEL[9]
TEST[19]	out	CELL[4].OUT_BEL[23]
TEST[20]	out	CELL[4].OUT_BEL[20]
TEST[21]	out	CELL[4].OUT_BEL[10]
TEST[22]	out	CELL[4].OUT_BEL[14]
TEST[23]	out	CELL[4].OUT_BEL[6]
TEST[24]	out	CELL[4].OUT_BEL[7]
TEST[25]	out	CELL[4].OUT_BEL[15]
TEST[26]	out	CELL[4].OUT_BEL[11]
TEST[27]	out	CELL[4].OUT_BEL[21]
TEST[28]	out	CELL[5].OUT_BEL[8]
TEST[29]	out	CELL[5].OUT_BEL[18]
TEST[30]	out	CELL[5].OUT_BEL[4]
TEST[31]	out	CELL[5].OUT_BEL[1]
TEST[32]	out	CELL[5].OUT_BEL[5]
TEST[33]	out	CELL[5].OUT_BEL[13]
TEST[34]	out	CELL[5].OUT_BEL[19]

virtex5 CMT bel PLL_V5 attribute bits
Attribute	PLL[0]
DRP[0] bit 0	MAIN[3][29][0]
DRP[0] bit 1	MAIN[3][28][0]
DRP[0] bit 2	MAIN[3][28][1]
DRP[0] bit 3	MAIN[3][29][1]
DRP[0] bit 4	MAIN[3][29][2]
DRP[0] bit 5	MAIN[3][28][2]
DRP[0] bit 6	MAIN[3][28][3]
DRP[0] bit 7	MAIN[3][29][3]
DRP[0] bit 8	MAIN[3][29][4]
DRP[0] bit 9	MAIN[3][28][4]
DRP[0] bit 10	MAIN[3][28][5]
DRP[0] bit 11	MAIN[3][29][5]
DRP[0] bit 12	MAIN[3][29][6]
DRP[0] bit 13	MAIN[3][28][6]
DRP[0] bit 14	MAIN[3][28][7]
DRP[0] bit 15	MAIN[3][29][7]
DRP[1] bit 0	MAIN[3][29][8]
DRP[1] bit 1	MAIN[3][28][8]
DRP[1] bit 2	MAIN[3][28][9]
DRP[1] bit 3	MAIN[3][29][9]
DRP[1] bit 4	MAIN[3][29][10]
DRP[1] bit 5	MAIN[3][28][10]
DRP[1] bit 6	MAIN[3][28][11]
DRP[1] bit 7	MAIN[3][29][11]
DRP[1] bit 8	MAIN[3][29][12]
DRP[1] bit 9	MAIN[3][28][12]
DRP[1] bit 10	MAIN[3][28][13]
DRP[1] bit 11	MAIN[3][29][13]
DRP[1] bit 12	MAIN[3][29][14]
DRP[1] bit 13	MAIN[3][28][14]
DRP[1] bit 14	MAIN[3][28][15]
DRP[1] bit 15	MAIN[3][29][15]
DRP[2] bit 0	MAIN[3][29][16]
DRP[2] bit 1	MAIN[3][28][16]
DRP[2] bit 2	MAIN[3][28][17]
DRP[2] bit 3	MAIN[3][29][17]
DRP[2] bit 4	MAIN[3][29][18]
DRP[2] bit 5	MAIN[3][28][18]
DRP[2] bit 6	MAIN[3][28][19]
DRP[2] bit 7	MAIN[3][29][19]
DRP[2] bit 8	MAIN[3][29][20]
DRP[2] bit 9	MAIN[3][28][20]
DRP[2] bit 10	MAIN[3][28][21]
DRP[2] bit 11	MAIN[3][29][21]
DRP[2] bit 12	MAIN[3][29][22]
DRP[2] bit 13	MAIN[3][28][22]
DRP[2] bit 14	MAIN[3][28][23]
DRP[2] bit 15	MAIN[3][29][23]
DRP[3] bit 0	MAIN[3][29][24]
DRP[3] bit 1	MAIN[3][28][24]
DRP[3] bit 2	MAIN[3][28][25]
DRP[3] bit 3	MAIN[3][29][25]
DRP[3] bit 4	MAIN[3][29][26]
DRP[3] bit 5	MAIN[3][28][26]
DRP[3] bit 6	MAIN[3][28][27]
DRP[3] bit 7	MAIN[3][29][27]
DRP[3] bit 8	MAIN[3][29][28]
DRP[3] bit 9	MAIN[3][28][28]
DRP[3] bit 10	MAIN[3][28][29]
DRP[3] bit 11	MAIN[3][29][29]
DRP[3] bit 12	MAIN[3][29][30]
DRP[3] bit 13	MAIN[3][28][30]
DRP[3] bit 14	MAIN[3][28][31]
DRP[3] bit 15	MAIN[3][29][31]
DRP[4] bit 0	MAIN[3][29][32]
DRP[4] bit 1	MAIN[3][28][32]
DRP[4] bit 2	MAIN[3][28][33]
DRP[4] bit 3	MAIN[3][29][33]
DRP[4] bit 4	MAIN[3][29][34]
DRP[4] bit 5	MAIN[3][28][34]
DRP[4] bit 6	MAIN[3][28][35]
DRP[4] bit 7	MAIN[3][29][35]
DRP[4] bit 8	MAIN[3][29][36]
DRP[4] bit 9	MAIN[3][28][36]
DRP[4] bit 10	MAIN[3][28][37]
DRP[4] bit 11	MAIN[3][29][37]
DRP[4] bit 12	MAIN[3][29][38]
DRP[4] bit 13	MAIN[3][28][38]
DRP[4] bit 14	MAIN[3][28][39]
DRP[4] bit 15	MAIN[3][29][39]
DRP[5] bit 0	MAIN[3][29][40]
DRP[5] bit 1	MAIN[3][28][40]
DRP[5] bit 2	MAIN[3][28][41]
DRP[5] bit 3	MAIN[3][29][41]
DRP[5] bit 4	MAIN[3][29][42]
DRP[5] bit 5	MAIN[3][28][42]
DRP[5] bit 6	MAIN[3][28][43]
DRP[5] bit 7	MAIN[3][29][43]
DRP[5] bit 8	MAIN[3][29][44]
DRP[5] bit 9	MAIN[3][28][44]
DRP[5] bit 10	MAIN[3][28][45]
DRP[5] bit 11	MAIN[3][29][45]
DRP[5] bit 12	MAIN[3][29][46]
DRP[5] bit 13	MAIN[3][28][46]
DRP[5] bit 14	MAIN[3][28][47]
DRP[5] bit 15	MAIN[3][29][47]
DRP[6] bit 0	MAIN[3][29][48]
DRP[6] bit 1	MAIN[3][28][48]
DRP[6] bit 2	MAIN[3][28][49]
DRP[6] bit 3	MAIN[3][29][49]
DRP[6] bit 4	MAIN[3][29][50]
DRP[6] bit 5	MAIN[3][28][50]
DRP[6] bit 6	MAIN[3][28][51]
DRP[6] bit 7	MAIN[3][29][51]
DRP[6] bit 8	MAIN[3][29][52]
DRP[6] bit 9	MAIN[3][28][52]
DRP[6] bit 10	MAIN[3][28][53]
DRP[6] bit 11	MAIN[3][29][53]
DRP[6] bit 12	MAIN[3][29][54]
DRP[6] bit 13	MAIN[3][28][54]
DRP[6] bit 14	MAIN[3][28][55]
DRP[6] bit 15	MAIN[3][29][55]
DRP[7] bit 0	MAIN[3][29][56]
DRP[7] bit 1	MAIN[3][28][56]
DRP[7] bit 2	MAIN[3][28][57]
DRP[7] bit 3	MAIN[3][29][57]
DRP[7] bit 4	MAIN[3][29][58]
DRP[7] bit 5	MAIN[3][28][58]
DRP[7] bit 6	MAIN[3][28][59]
DRP[7] bit 7	MAIN[3][29][59]
DRP[7] bit 8	MAIN[3][29][60]
DRP[7] bit 9	MAIN[3][28][60]
DRP[7] bit 10	MAIN[3][28][61]
DRP[7] bit 11	MAIN[3][29][61]
DRP[7] bit 12	MAIN[3][29][62]
DRP[7] bit 13	MAIN[3][28][62]
DRP[7] bit 14	MAIN[3][28][63]
DRP[7] bit 15	MAIN[3][29][63]
DRP[8] bit 0	MAIN[4][29][0]
DRP[8] bit 1	MAIN[4][28][0]
DRP[8] bit 2	MAIN[4][28][1]
DRP[8] bit 3	MAIN[4][29][1]
DRP[8] bit 4	MAIN[4][29][2]
DRP[8] bit 5	MAIN[4][28][2]
DRP[8] bit 6	MAIN[4][28][3]
DRP[8] bit 7	MAIN[4][29][3]
DRP[8] bit 8	MAIN[4][29][4]
DRP[8] bit 9	MAIN[4][28][4]
DRP[8] bit 10	MAIN[4][28][5]
DRP[8] bit 11	MAIN[4][29][5]
DRP[8] bit 12	MAIN[4][29][6]
DRP[8] bit 13	MAIN[4][28][6]
DRP[8] bit 14	MAIN[4][28][7]
DRP[8] bit 15	MAIN[4][29][7]
DRP[9] bit 0	MAIN[4][29][8]
DRP[9] bit 1	MAIN[4][28][8]
DRP[9] bit 2	MAIN[4][28][9]
DRP[9] bit 3	MAIN[4][29][9]
DRP[9] bit 4	MAIN[4][29][10]
DRP[9] bit 5	MAIN[4][28][10]
DRP[9] bit 6	MAIN[4][28][11]
DRP[9] bit 7	MAIN[4][29][11]
DRP[9] bit 8	MAIN[4][29][12]
DRP[9] bit 9	MAIN[4][28][12]
DRP[9] bit 10	MAIN[4][28][13]
DRP[9] bit 11	MAIN[4][29][13]
DRP[9] bit 12	MAIN[4][29][14]
DRP[9] bit 13	MAIN[4][28][14]
DRP[9] bit 14	MAIN[4][28][15]
DRP[9] bit 15	MAIN[4][29][15]
DRP[10] bit 0	MAIN[4][29][16]
DRP[10] bit 1	MAIN[4][28][16]
DRP[10] bit 2	MAIN[4][28][17]
DRP[10] bit 3	MAIN[4][29][17]
DRP[10] bit 4	MAIN[4][29][18]
DRP[10] bit 5	MAIN[4][28][18]
DRP[10] bit 6	MAIN[4][28][19]
DRP[10] bit 7	MAIN[4][29][19]
DRP[10] bit 8	MAIN[4][29][20]
DRP[10] bit 9	MAIN[4][28][20]
DRP[10] bit 10	MAIN[4][28][21]
DRP[10] bit 11	MAIN[4][29][21]
DRP[10] bit 12	MAIN[4][29][22]
DRP[10] bit 13	MAIN[4][28][22]
DRP[10] bit 14	MAIN[4][28][23]
DRP[10] bit 15	MAIN[4][29][23]
DRP[11] bit 0	MAIN[4][29][24]
DRP[11] bit 1	MAIN[4][28][24]
DRP[11] bit 2	MAIN[4][28][25]
DRP[11] bit 3	MAIN[4][29][25]
DRP[11] bit 4	MAIN[4][29][26]
DRP[11] bit 5	MAIN[4][28][26]
DRP[11] bit 6	MAIN[4][28][27]
DRP[11] bit 7	MAIN[4][29][27]
DRP[11] bit 8	MAIN[4][29][28]
DRP[11] bit 9	MAIN[4][28][28]
DRP[11] bit 10	MAIN[4][28][29]
DRP[11] bit 11	MAIN[4][29][29]
DRP[11] bit 12	MAIN[4][29][30]
DRP[11] bit 13	MAIN[4][28][30]
DRP[11] bit 14	MAIN[4][28][31]
DRP[11] bit 15	MAIN[4][29][31]
DRP[12] bit 0	MAIN[4][29][32]
DRP[12] bit 1	MAIN[4][28][32]
DRP[12] bit 2	MAIN[4][28][33]
DRP[12] bit 3	MAIN[4][29][33]
DRP[12] bit 4	MAIN[4][29][34]
DRP[12] bit 5	MAIN[4][28][34]
DRP[12] bit 6	MAIN[4][28][35]
DRP[12] bit 7	MAIN[4][29][35]
DRP[12] bit 8	MAIN[4][29][36]
DRP[12] bit 9	MAIN[4][28][36]
DRP[12] bit 10	MAIN[4][28][37]
DRP[12] bit 11	MAIN[4][29][37]
DRP[12] bit 12	MAIN[4][29][38]
DRP[12] bit 13	MAIN[4][28][38]
DRP[12] bit 14	MAIN[4][28][39]
DRP[12] bit 15	MAIN[4][29][39]
DRP[13] bit 0	MAIN[4][29][40]
DRP[13] bit 1	MAIN[4][28][40]
DRP[13] bit 2	MAIN[4][28][41]
DRP[13] bit 3	MAIN[4][29][41]
DRP[13] bit 4	MAIN[4][29][42]
DRP[13] bit 5	MAIN[4][28][42]
DRP[13] bit 6	MAIN[4][28][43]
DRP[13] bit 7	MAIN[4][29][43]
DRP[13] bit 8	MAIN[4][29][44]
DRP[13] bit 9	MAIN[4][28][44]
DRP[13] bit 10	MAIN[4][28][45]
DRP[13] bit 11	MAIN[4][29][45]
DRP[13] bit 12	MAIN[4][29][46]
DRP[13] bit 13	MAIN[4][28][46]
DRP[13] bit 14	MAIN[4][28][47]
DRP[13] bit 15	MAIN[4][29][47]
DRP[14] bit 0	MAIN[4][29][48]
DRP[14] bit 1	MAIN[4][28][48]
DRP[14] bit 2	MAIN[4][28][49]
DRP[14] bit 3	MAIN[4][29][49]
DRP[14] bit 4	MAIN[4][29][50]
DRP[14] bit 5	MAIN[4][28][50]
DRP[14] bit 6	MAIN[4][28][51]
DRP[14] bit 7	MAIN[4][29][51]
DRP[14] bit 8	MAIN[4][29][52]
DRP[14] bit 9	MAIN[4][28][52]
DRP[14] bit 10	MAIN[4][28][53]
DRP[14] bit 11	MAIN[4][29][53]
DRP[14] bit 12	MAIN[4][29][54]
DRP[14] bit 13	MAIN[4][28][54]
DRP[14] bit 14	MAIN[4][28][55]
DRP[14] bit 15	MAIN[4][29][55]
DRP[15] bit 0	MAIN[4][29][56]
DRP[15] bit 1	MAIN[4][28][56]
DRP[15] bit 2	MAIN[4][28][57]
DRP[15] bit 3	MAIN[4][29][57]
DRP[15] bit 4	MAIN[4][29][58]
DRP[15] bit 5	MAIN[4][28][58]
DRP[15] bit 6	MAIN[4][28][59]
DRP[15] bit 7	MAIN[4][29][59]
DRP[15] bit 8	MAIN[4][29][60]
DRP[15] bit 9	MAIN[4][28][60]
DRP[15] bit 10	MAIN[4][28][61]
DRP[15] bit 11	MAIN[4][29][61]
DRP[15] bit 12	MAIN[4][29][62]
DRP[15] bit 13	MAIN[4][28][62]
DRP[15] bit 14	MAIN[4][28][63]
DRP[15] bit 15	MAIN[4][29][63]
DRP[16] bit 0	MAIN[5][29][0]
DRP[16] bit 1	MAIN[5][28][0]
DRP[16] bit 2	MAIN[5][28][1]
DRP[16] bit 3	MAIN[5][29][1]
DRP[16] bit 4	MAIN[5][29][2]
DRP[16] bit 5	MAIN[5][28][2]
DRP[16] bit 6	MAIN[5][28][3]
DRP[16] bit 7	MAIN[5][29][3]
DRP[16] bit 8	MAIN[5][29][4]
DRP[16] bit 9	MAIN[5][28][4]
DRP[16] bit 10	MAIN[5][28][5]
DRP[16] bit 11	MAIN[5][29][5]
DRP[16] bit 12	MAIN[5][29][6]
DRP[16] bit 13	MAIN[5][28][6]
DRP[16] bit 14	MAIN[5][28][7]
DRP[16] bit 15	MAIN[5][29][7]
DRP[17] bit 0	MAIN[5][29][8]
DRP[17] bit 1	MAIN[5][28][8]
DRP[17] bit 2	MAIN[5][28][9]
DRP[17] bit 3	MAIN[5][29][9]
DRP[17] bit 4	MAIN[5][29][10]
DRP[17] bit 5	MAIN[5][28][10]
DRP[17] bit 6	MAIN[5][28][11]
DRP[17] bit 7	MAIN[5][29][11]
DRP[17] bit 8	MAIN[5][29][12]
DRP[17] bit 9	MAIN[5][28][12]
DRP[17] bit 10	MAIN[5][28][13]
DRP[17] bit 11	MAIN[5][29][13]
DRP[17] bit 12	MAIN[5][29][14]
DRP[17] bit 13	MAIN[5][28][14]
DRP[17] bit 14	MAIN[5][28][15]
DRP[17] bit 15	MAIN[5][29][15]
DRP[18] bit 0	MAIN[5][29][16]
DRP[18] bit 1	MAIN[5][28][16]
DRP[18] bit 2	MAIN[5][28][17]
DRP[18] bit 3	MAIN[5][29][17]
DRP[18] bit 4	MAIN[5][29][18]
DRP[18] bit 5	MAIN[5][28][18]
DRP[18] bit 6	MAIN[5][28][19]
DRP[18] bit 7	MAIN[5][29][19]
DRP[18] bit 8	MAIN[5][29][20]
DRP[18] bit 9	MAIN[5][28][20]
DRP[18] bit 10	MAIN[5][28][21]
DRP[18] bit 11	MAIN[5][29][21]
DRP[18] bit 12	MAIN[5][29][22]
DRP[18] bit 13	MAIN[5][28][22]
DRP[18] bit 14	MAIN[5][28][23]
DRP[18] bit 15	MAIN[5][29][23]
DRP[19] bit 0	MAIN[5][29][24]
DRP[19] bit 1	MAIN[5][28][24]
DRP[19] bit 2	MAIN[5][28][25]
DRP[19] bit 3	MAIN[5][29][25]
DRP[19] bit 4	MAIN[5][29][26]
DRP[19] bit 5	MAIN[5][28][26]
DRP[19] bit 6	MAIN[5][28][27]
DRP[19] bit 7	MAIN[5][29][27]
DRP[19] bit 8	MAIN[5][29][28]
DRP[19] bit 9	MAIN[5][28][28]
DRP[19] bit 10	MAIN[5][28][29]
DRP[19] bit 11	MAIN[5][29][29]
DRP[19] bit 12	MAIN[5][29][30]
DRP[19] bit 13	MAIN[5][28][30]
DRP[19] bit 14	MAIN[5][28][31]
DRP[19] bit 15	MAIN[5][29][31]
DRP[20] bit 0	MAIN[5][29][32]
DRP[20] bit 1	MAIN[5][28][32]
DRP[20] bit 2	MAIN[5][28][33]
DRP[20] bit 3	MAIN[5][29][33]
DRP[20] bit 4	MAIN[5][29][34]
DRP[20] bit 5	MAIN[5][28][34]
DRP[20] bit 6	MAIN[5][28][35]
DRP[20] bit 7	MAIN[5][29][35]
DRP[20] bit 8	MAIN[5][29][36]
DRP[20] bit 9	MAIN[5][28][36]
DRP[20] bit 10	MAIN[5][28][37]
DRP[20] bit 11	MAIN[5][29][37]
DRP[20] bit 12	MAIN[5][29][38]
DRP[20] bit 13	MAIN[5][28][38]
DRP[20] bit 14	MAIN[5][28][39]
DRP[20] bit 15	MAIN[5][29][39]
DRP[21] bit 0	MAIN[5][29][40]
DRP[21] bit 1	MAIN[5][28][40]
DRP[21] bit 2	MAIN[5][28][41]
DRP[21] bit 3	MAIN[5][29][41]
DRP[21] bit 4	MAIN[5][29][42]
DRP[21] bit 5	MAIN[5][28][42]
DRP[21] bit 6	MAIN[5][28][43]
DRP[21] bit 7	MAIN[5][29][43]
DRP[21] bit 8	MAIN[5][29][44]
DRP[21] bit 9	MAIN[5][28][44]
DRP[21] bit 10	MAIN[5][28][45]
DRP[21] bit 11	MAIN[5][29][45]
DRP[21] bit 12	MAIN[5][29][46]
DRP[21] bit 13	MAIN[5][28][46]
DRP[21] bit 14	MAIN[5][28][47]
DRP[21] bit 15	MAIN[5][29][47]
DRP[22] bit 0	MAIN[5][29][48]
DRP[22] bit 1	MAIN[5][28][48]
DRP[22] bit 2	MAIN[5][28][49]
DRP[22] bit 3	MAIN[5][29][49]
DRP[22] bit 4	MAIN[5][29][50]
DRP[22] bit 5	MAIN[5][28][50]
DRP[22] bit 6	MAIN[5][28][51]
DRP[22] bit 7	MAIN[5][29][51]
DRP[22] bit 8	MAIN[5][29][52]
DRP[22] bit 9	MAIN[5][28][52]
DRP[22] bit 10	MAIN[5][28][53]
DRP[22] bit 11	MAIN[5][29][53]
DRP[22] bit 12	MAIN[5][29][54]
DRP[22] bit 13	MAIN[5][28][54]
DRP[22] bit 14	MAIN[5][28][55]
DRP[22] bit 15	MAIN[5][29][55]
DRP[23] bit 0	MAIN[5][29][56]
DRP[23] bit 1	MAIN[5][28][56]
DRP[23] bit 2	MAIN[5][28][57]
DRP[23] bit 3	MAIN[5][29][57]
DRP[23] bit 4	MAIN[5][29][58]
DRP[23] bit 5	MAIN[5][28][58]
DRP[23] bit 6	MAIN[5][28][59]
DRP[23] bit 7	MAIN[5][29][59]
DRP[23] bit 8	MAIN[5][29][60]
DRP[23] bit 9	MAIN[5][28][60]
DRP[23] bit 10	MAIN[5][28][61]
DRP[23] bit 11	MAIN[5][29][61]
DRP[23] bit 12	MAIN[5][29][62]
DRP[23] bit 13	MAIN[5][28][62]
DRP[23] bit 14	MAIN[5][28][63]
DRP[23] bit 15	MAIN[5][29][63]
DRP[24] bit 0	MAIN[6][29][0]
DRP[24] bit 1	MAIN[6][28][0]
DRP[24] bit 2	MAIN[6][28][1]
DRP[24] bit 3	MAIN[6][29][1]
DRP[24] bit 4	MAIN[6][29][2]
DRP[24] bit 5	MAIN[6][28][2]
DRP[24] bit 6	MAIN[6][28][3]
DRP[24] bit 7	MAIN[6][29][3]
DRP[24] bit 8	MAIN[6][29][4]
DRP[24] bit 9	MAIN[6][28][4]
DRP[24] bit 10	MAIN[6][28][5]
DRP[24] bit 11	MAIN[6][29][5]
DRP[24] bit 12	MAIN[6][29][6]
DRP[24] bit 13	MAIN[6][28][6]
DRP[24] bit 14	MAIN[6][28][7]
DRP[24] bit 15	MAIN[6][29][7]
DRP[25] bit 0	MAIN[6][29][8]
DRP[25] bit 1	MAIN[6][28][8]
DRP[25] bit 2	MAIN[6][28][9]
DRP[25] bit 3	MAIN[6][29][9]
DRP[25] bit 4	MAIN[6][29][10]
DRP[25] bit 5	MAIN[6][28][10]
DRP[25] bit 6	MAIN[6][28][11]
DRP[25] bit 7	MAIN[6][29][11]
DRP[25] bit 8	MAIN[6][29][12]
DRP[25] bit 9	MAIN[6][28][12]
DRP[25] bit 10	MAIN[6][28][13]
DRP[25] bit 11	MAIN[6][29][13]
DRP[25] bit 12	MAIN[6][29][14]
DRP[25] bit 13	MAIN[6][28][14]
DRP[25] bit 14	MAIN[6][28][15]
DRP[25] bit 15	MAIN[6][29][15]
DRP[26] bit 0	MAIN[6][29][16]
DRP[26] bit 1	MAIN[6][28][16]
DRP[26] bit 2	MAIN[6][28][17]
DRP[26] bit 3	MAIN[6][29][17]
DRP[26] bit 4	MAIN[6][29][18]
DRP[26] bit 5	MAIN[6][28][18]
DRP[26] bit 6	MAIN[6][28][19]
DRP[26] bit 7	MAIN[6][29][19]
DRP[26] bit 8	MAIN[6][29][20]
DRP[26] bit 9	MAIN[6][28][20]
DRP[26] bit 10	MAIN[6][28][21]
DRP[26] bit 11	MAIN[6][29][21]
DRP[26] bit 12	MAIN[6][29][22]
DRP[26] bit 13	MAIN[6][28][22]
DRP[26] bit 14	MAIN[6][28][23]
DRP[26] bit 15	MAIN[6][29][23]
DRP[27] bit 0	MAIN[6][29][24]
DRP[27] bit 1	MAIN[6][28][24]
DRP[27] bit 2	MAIN[6][28][25]
DRP[27] bit 3	MAIN[6][29][25]
DRP[27] bit 4	MAIN[6][29][26]
DRP[27] bit 5	MAIN[6][28][26]
DRP[27] bit 6	MAIN[6][28][27]
DRP[27] bit 7	MAIN[6][29][27]
DRP[27] bit 8	MAIN[6][29][28]
DRP[27] bit 9	MAIN[6][28][28]
DRP[27] bit 10	MAIN[6][28][29]
DRP[27] bit 11	MAIN[6][29][29]
DRP[27] bit 12	MAIN[6][29][30]
DRP[27] bit 13	MAIN[6][28][30]
DRP[27] bit 14	MAIN[6][28][31]
DRP[27] bit 15	MAIN[6][29][31]
DRP[28] bit 0	MAIN[6][29][32]
DRP[28] bit 1	MAIN[6][28][32]
DRP[28] bit 2	MAIN[6][28][33]
DRP[28] bit 3	MAIN[6][29][33]
DRP[28] bit 4	MAIN[6][29][34]
DRP[28] bit 5	MAIN[6][28][34]
DRP[28] bit 6	MAIN[6][28][35]
DRP[28] bit 7	MAIN[6][29][35]
DRP[28] bit 8	MAIN[6][29][36]
DRP[28] bit 9	MAIN[6][28][36]
DRP[28] bit 10	MAIN[6][28][37]
DRP[28] bit 11	MAIN[6][29][37]
DRP[28] bit 12	MAIN[6][29][38]
DRP[28] bit 13	MAIN[6][28][38]
DRP[28] bit 14	MAIN[6][28][39]
DRP[28] bit 15	MAIN[6][29][39]
DRP[29] bit 0	MAIN[6][29][40]
DRP[29] bit 1	MAIN[6][28][40]
DRP[29] bit 2	MAIN[6][28][41]
DRP[29] bit 3	MAIN[6][29][41]
DRP[29] bit 4	MAIN[6][29][42]
DRP[29] bit 5	MAIN[6][28][42]
DRP[29] bit 6	MAIN[6][28][43]
DRP[29] bit 7	MAIN[6][29][43]
DRP[29] bit 8	MAIN[6][29][44]
DRP[29] bit 9	MAIN[6][28][44]
DRP[29] bit 10	MAIN[6][28][45]
DRP[29] bit 11	MAIN[6][29][45]
DRP[29] bit 12	MAIN[6][29][46]
DRP[29] bit 13	MAIN[6][28][46]
DRP[29] bit 14	MAIN[6][28][47]
DRP[29] bit 15	MAIN[6][29][47]
DRP[30] bit 0	MAIN[6][29][48]
DRP[30] bit 1	MAIN[6][28][48]
DRP[30] bit 2	MAIN[6][28][49]
DRP[30] bit 3	MAIN[6][29][49]
DRP[30] bit 4	MAIN[6][29][50]
DRP[30] bit 5	MAIN[6][28][50]
DRP[30] bit 6	MAIN[6][28][51]
DRP[30] bit 7	MAIN[6][29][51]
DRP[30] bit 8	MAIN[6][29][52]
DRP[30] bit 9	MAIN[6][28][52]
DRP[30] bit 10	MAIN[6][28][53]
DRP[30] bit 11	MAIN[6][29][53]
DRP[30] bit 12	MAIN[6][29][54]
DRP[30] bit 13	MAIN[6][28][54]
DRP[30] bit 14	MAIN[6][28][55]
DRP[30] bit 15	MAIN[6][29][55]
DRP[31] bit 0	MAIN[6][29][56]
DRP[31] bit 1	MAIN[6][28][56]
DRP[31] bit 2	MAIN[6][28][57]
DRP[31] bit 3	MAIN[6][29][57]
DRP[31] bit 4	MAIN[6][29][58]
DRP[31] bit 5	MAIN[6][28][58]
DRP[31] bit 6	MAIN[6][28][59]
DRP[31] bit 7	MAIN[6][29][59]
DRP[31] bit 8	MAIN[6][29][60]
DRP[31] bit 9	MAIN[6][28][60]
DRP[31] bit 10	MAIN[6][28][61]
DRP[31] bit 11	MAIN[6][29][61]
DRP[31] bit 12	MAIN[6][29][62]
DRP[31] bit 13	MAIN[6][28][62]
DRP[31] bit 14	MAIN[6][28][63]
DRP[31] bit 15	MAIN[6][29][63]
CLKINSEL_STATIC_VAL bit 0	MAIN[6][29][50]
CLKINSEL_MODE_DYNAMIC	MAIN[6][29][43]
CLKOUT0_DESKEW_ADJUST bit 0	MAIN[6][29][37]
CLKOUT0_DESKEW_ADJUST bit 1	MAIN[6][29][38]
CLKOUT0_DESKEW_ADJUST bit 2	MAIN[6][28][38]
CLKOUT0_DESKEW_ADJUST bit 3	MAIN[6][28][39]
CLKOUT0_DESKEW_ADJUST bit 4	MAIN[6][29][39]
CLKOUT1_DESKEW_ADJUST bit 0	MAIN[6][29][21]
CLKOUT1_DESKEW_ADJUST bit 1	MAIN[6][29][22]
CLKOUT1_DESKEW_ADJUST bit 2	MAIN[6][28][22]
CLKOUT1_DESKEW_ADJUST bit 3	MAIN[6][28][23]
CLKOUT1_DESKEW_ADJUST bit 4	MAIN[6][29][23]
CLKOUT2_DESKEW_ADJUST bit 0	MAIN[5][29][61]
CLKOUT2_DESKEW_ADJUST bit 1	MAIN[5][29][62]
CLKOUT2_DESKEW_ADJUST bit 2	MAIN[5][28][62]
CLKOUT2_DESKEW_ADJUST bit 3	MAIN[5][28][63]
CLKOUT2_DESKEW_ADJUST bit 4	MAIN[5][29][63]
CLKOUT3_DESKEW_ADJUST bit 0	MAIN[5][29][45]
CLKOUT3_DESKEW_ADJUST bit 1	MAIN[5][29][46]
CLKOUT3_DESKEW_ADJUST bit 2	MAIN[5][28][46]
CLKOUT3_DESKEW_ADJUST bit 3	MAIN[5][28][47]
CLKOUT3_DESKEW_ADJUST bit 4	MAIN[5][29][47]
CLKOUT4_DESKEW_ADJUST bit 0	MAIN[5][29][29]
CLKOUT4_DESKEW_ADJUST bit 1	MAIN[5][29][30]
CLKOUT4_DESKEW_ADJUST bit 2	MAIN[5][28][30]
CLKOUT4_DESKEW_ADJUST bit 3	MAIN[5][28][31]
CLKOUT4_DESKEW_ADJUST bit 4	MAIN[5][29][31]
CLKOUT5_DESKEW_ADJUST bit 0	MAIN[4][29][61]
CLKOUT5_DESKEW_ADJUST bit 1	MAIN[4][29][62]
CLKOUT5_DESKEW_ADJUST bit 2	MAIN[4][28][62]
CLKOUT5_DESKEW_ADJUST bit 3	MAIN[4][28][63]
CLKOUT5_DESKEW_ADJUST bit 4	MAIN[4][29][63]
CLKFBOUT_DESKEW_ADJUST bit 0	MAIN[4][29][45]
CLKFBOUT_DESKEW_ADJUST bit 1	MAIN[4][29][46]
CLKFBOUT_DESKEW_ADJUST bit 2	MAIN[4][28][46]
CLKFBOUT_DESKEW_ADJUST bit 3	MAIN[4][28][47]
CLKFBOUT_DESKEW_ADJUST bit 4	MAIN[4][29][47]
PLL_AVDD_COMP_SET bit 0	MAIN[6][28][63]
PLL_AVDD_COMP_SET bit 1	MAIN[6][29][63]
PLL_AVDD_VBG_PD bit 0	MAIN[6][29][62]
PLL_AVDD_VBG_PD bit 1	MAIN[6][28][62]
PLL_AVDD_VBG_SEL bit 0	MAIN[6][29][60]
PLL_AVDD_VBG_SEL bit 1	MAIN[6][28][60]
PLL_AVDD_VBG_SEL bit 2	MAIN[6][28][61]
PLL_AVDD_VBG_SEL bit 3	MAIN[6][29][61]
PLL_CLKCNTRL bit 0	!MAIN[6][28][43]
PLL_CLK0MX bit 0	MAIN[6][29][36]
PLL_CLK0MX bit 1	MAIN[6][28][36]
PLL_CLK1MX bit 0	MAIN[6][29][20]
PLL_CLK1MX bit 1	MAIN[6][28][20]
PLL_CLK2MX bit 0	MAIN[5][29][60]
PLL_CLK2MX bit 1	MAIN[5][28][60]
PLL_CLK3MX bit 0	MAIN[5][29][44]
PLL_CLK3MX bit 1	MAIN[5][28][44]
PLL_CLK4MX bit 0	MAIN[5][29][28]
PLL_CLK4MX bit 1	MAIN[5][28][28]
PLL_CLK5MX bit 0	MAIN[4][29][60]
PLL_CLK5MX bit 1	MAIN[4][28][60]
PLL_CLKBURST_CNT bit 0	MAIN[6][28][6]
PLL_CLKBURST_CNT bit 1	MAIN[6][28][7]
PLL_CLKBURST_CNT bit 2	MAIN[6][29][7]
PLL_CLKBURST_ENABLE	MAIN[6][29][6]
PLL_CLKFBMX bit 0	MAIN[4][29][44]
PLL_CLKFBMX bit 1	MAIN[4][28][44]
PLL_CLKFBOUT2_DT bit 0	MAIN[4][29][16]
PLL_CLKFBOUT2_DT bit 1	MAIN[4][28][16]
PLL_CLKFBOUT2_DT bit 2	MAIN[4][28][17]
PLL_CLKFBOUT2_DT bit 3	MAIN[4][29][17]
PLL_CLKFBOUT2_DT bit 4	MAIN[4][29][18]
PLL_CLKFBOUT2_DT bit 5	MAIN[4][28][18]
PLL_CLKFBOUT2_EDGE	MAIN[4][29][19]
PLL_CLKFBOUT2_HT bit 0	MAIN[4][28][11]
PLL_CLKFBOUT2_HT bit 1	MAIN[4][29][11]
PLL_CLKFBOUT2_HT bit 2	MAIN[4][29][12]
PLL_CLKFBOUT2_HT bit 3	MAIN[4][28][12]
PLL_CLKFBOUT2_HT bit 4	MAIN[4][28][13]
PLL_CLKFBOUT2_HT bit 5	MAIN[4][29][13]
PLL_CLKFBOUT2_LT bit 0	MAIN[4][29][8]
PLL_CLKFBOUT2_LT bit 1	MAIN[4][28][8]
PLL_CLKFBOUT2_LT bit 2	MAIN[4][28][9]
PLL_CLKFBOUT2_LT bit 3	MAIN[4][29][9]
PLL_CLKFBOUT2_LT bit 4	MAIN[4][29][10]
PLL_CLKFBOUT2_LT bit 5	MAIN[4][28][10]
PLL_CLKFBOUT2_NOCOUNT	MAIN[4][28][19]
PLL_CLKFBOUT_DT bit 0	MAIN[4][29][40]
PLL_CLKFBOUT_DT bit 1	MAIN[4][28][40]
PLL_CLKFBOUT_DT bit 2	MAIN[4][28][41]
PLL_CLKFBOUT_DT bit 3	MAIN[4][29][41]
PLL_CLKFBOUT_DT bit 4	MAIN[4][29][42]
PLL_CLKFBOUT_DT bit 5	MAIN[4][28][42]
PLL_CLKFBOUT_EDGE	MAIN[4][29][43]
PLL_CLKFBOUT_EN	MAIN[4][29][38]
PLL_CLKFBOUT_HT bit 0	MAIN[4][28][35]
PLL_CLKFBOUT_HT bit 1	MAIN[4][29][35]
PLL_CLKFBOUT_HT bit 2	MAIN[4][29][36]
PLL_CLKFBOUT_HT bit 3	MAIN[4][28][36]
PLL_CLKFBOUT_HT bit 4	MAIN[4][28][37]
PLL_CLKFBOUT_HT bit 5	MAIN[4][29][37]
PLL_CLKFBOUT_LT bit 0	MAIN[4][29][32]
PLL_CLKFBOUT_LT bit 1	MAIN[4][28][32]
PLL_CLKFBOUT_LT bit 2	MAIN[4][28][33]
PLL_CLKFBOUT_LT bit 3	MAIN[4][29][33]
PLL_CLKFBOUT_LT bit 4	MAIN[4][29][34]
PLL_CLKFBOUT_LT bit 5	MAIN[4][28][34]
PLL_CLKFBOUT_NOCOUNT	MAIN[4][28][43]
PLL_CLKFBOUT_PM bit 0	MAIN[4][28][38]
PLL_CLKFBOUT_PM bit 1	MAIN[4][28][39]
PLL_CLKFBOUT_PM bit 2	MAIN[4][29][39]
PLL_CLKOUT0_DT bit 0	MAIN[6][29][32]
PLL_CLKOUT0_DT bit 1	MAIN[6][28][32]
PLL_CLKOUT0_DT bit 2	MAIN[6][28][33]
PLL_CLKOUT0_DT bit 3	MAIN[6][29][33]
PLL_CLKOUT0_DT bit 4	MAIN[6][29][34]
PLL_CLKOUT0_DT bit 5	MAIN[6][28][34]
PLL_CLKOUT0_EDGE	MAIN[6][29][35]
PLL_CLKOUT0_EN	MAIN[6][29][30]
PLL_CLKOUT0_HT bit 0	MAIN[6][28][27]
PLL_CLKOUT0_HT bit 1	MAIN[6][29][27]
PLL_CLKOUT0_HT bit 2	MAIN[6][29][28]
PLL_CLKOUT0_HT bit 3	MAIN[6][28][28]
PLL_CLKOUT0_HT bit 4	MAIN[6][28][29]
PLL_CLKOUT0_HT bit 5	MAIN[6][29][29]
PLL_CLKOUT0_LT bit 0	MAIN[6][29][24]
PLL_CLKOUT0_LT bit 1	MAIN[6][28][24]
PLL_CLKOUT0_LT bit 2	MAIN[6][28][25]
PLL_CLKOUT0_LT bit 3	MAIN[6][29][25]
PLL_CLKOUT0_LT bit 4	MAIN[6][29][26]
PLL_CLKOUT0_LT bit 5	MAIN[6][28][26]
PLL_CLKOUT0_NOCOUNT	MAIN[6][28][35]
PLL_CLKOUT0_PM bit 0	MAIN[6][28][30]
PLL_CLKOUT0_PM bit 1	MAIN[6][28][31]
PLL_CLKOUT0_PM bit 2	MAIN[6][29][31]
PLL_CLKOUT1_DT bit 0	MAIN[6][29][16]
PLL_CLKOUT1_DT bit 1	MAIN[6][28][16]
PLL_CLKOUT1_DT bit 2	MAIN[6][28][17]
PLL_CLKOUT1_DT bit 3	MAIN[6][29][17]
PLL_CLKOUT1_DT bit 4	MAIN[6][29][18]
PLL_CLKOUT1_DT bit 5	MAIN[6][28][18]
PLL_CLKOUT1_EDGE	MAIN[6][29][19]
PLL_CLKOUT1_EN	MAIN[6][29][14]
PLL_CLKOUT1_HT bit 0	MAIN[6][28][11]
PLL_CLKOUT1_HT bit 1	MAIN[6][29][11]
PLL_CLKOUT1_HT bit 2	MAIN[6][29][12]
PLL_CLKOUT1_HT bit 3	MAIN[6][28][12]
PLL_CLKOUT1_HT bit 4	MAIN[6][28][13]
PLL_CLKOUT1_HT bit 5	MAIN[6][29][13]
PLL_CLKOUT1_LT bit 0	MAIN[6][29][8]
PLL_CLKOUT1_LT bit 1	MAIN[6][28][8]
PLL_CLKOUT1_LT bit 2	MAIN[6][28][9]
PLL_CLKOUT1_LT bit 3	MAIN[6][29][9]
PLL_CLKOUT1_LT bit 4	MAIN[6][29][10]
PLL_CLKOUT1_LT bit 5	MAIN[6][28][10]
PLL_CLKOUT1_NOCOUNT	MAIN[6][28][19]
PLL_CLKOUT1_PM bit 0	MAIN[6][28][14]
PLL_CLKOUT1_PM bit 1	MAIN[6][28][15]
PLL_CLKOUT1_PM bit 2	MAIN[6][29][15]
PLL_CLKOUT2_DT bit 0	MAIN[5][29][56]
PLL_CLKOUT2_DT bit 1	MAIN[5][28][56]
PLL_CLKOUT2_DT bit 2	MAIN[5][28][57]
PLL_CLKOUT2_DT bit 3	MAIN[5][29][57]
PLL_CLKOUT2_DT bit 4	MAIN[5][29][58]
PLL_CLKOUT2_DT bit 5	MAIN[5][28][58]
PLL_CLKOUT2_EDGE	MAIN[5][29][59]
PLL_CLKOUT2_EN	MAIN[5][29][54]
PLL_CLKOUT2_HT bit 0	MAIN[5][28][51]
PLL_CLKOUT2_HT bit 1	MAIN[5][29][51]
PLL_CLKOUT2_HT bit 2	MAIN[5][29][52]
PLL_CLKOUT2_HT bit 3	MAIN[5][28][52]
PLL_CLKOUT2_HT bit 4	MAIN[5][28][53]
PLL_CLKOUT2_HT bit 5	MAIN[5][29][53]
PLL_CLKOUT2_LT bit 0	MAIN[5][29][48]
PLL_CLKOUT2_LT bit 1	MAIN[5][28][48]
PLL_CLKOUT2_LT bit 2	MAIN[5][28][49]
PLL_CLKOUT2_LT bit 3	MAIN[5][29][49]
PLL_CLKOUT2_LT bit 4	MAIN[5][29][50]
PLL_CLKOUT2_LT bit 5	MAIN[5][28][50]
PLL_CLKOUT2_NOCOUNT	MAIN[5][28][59]
PLL_CLKOUT2_PM bit 0	MAIN[5][28][54]
PLL_CLKOUT2_PM bit 1	MAIN[5][28][55]
PLL_CLKOUT2_PM bit 2	MAIN[5][29][55]
PLL_CLKOUT3_DT bit 0	MAIN[5][29][40]
PLL_CLKOUT3_DT bit 1	MAIN[5][28][40]
PLL_CLKOUT3_DT bit 2	MAIN[5][28][41]
PLL_CLKOUT3_DT bit 3	MAIN[5][29][41]
PLL_CLKOUT3_DT bit 4	MAIN[5][29][42]
PLL_CLKOUT3_DT bit 5	MAIN[5][28][42]
PLL_CLKOUT3_EDGE	MAIN[5][29][43]
PLL_CLKOUT3_EN	MAIN[5][29][38]
PLL_CLKOUT3_HT bit 0	MAIN[5][28][35]
PLL_CLKOUT3_HT bit 1	MAIN[5][29][35]
PLL_CLKOUT3_HT bit 2	MAIN[5][29][36]
PLL_CLKOUT3_HT bit 3	MAIN[5][28][36]
PLL_CLKOUT3_HT bit 4	MAIN[5][28][37]
PLL_CLKOUT3_HT bit 5	MAIN[5][29][37]
PLL_CLKOUT3_LT bit 0	MAIN[5][29][32]
PLL_CLKOUT3_LT bit 1	MAIN[5][28][32]
PLL_CLKOUT3_LT bit 2	MAIN[5][28][33]
PLL_CLKOUT3_LT bit 3	MAIN[5][29][33]
PLL_CLKOUT3_LT bit 4	MAIN[5][29][34]
PLL_CLKOUT3_LT bit 5	MAIN[5][28][34]
PLL_CLKOUT3_NOCOUNT	MAIN[5][28][43]
PLL_CLKOUT3_PM bit 0	MAIN[5][28][38]
PLL_CLKOUT3_PM bit 1	MAIN[5][28][39]
PLL_CLKOUT3_PM bit 2	MAIN[5][29][39]
PLL_CLKOUT4_DT bit 0	MAIN[5][29][24]
PLL_CLKOUT4_DT bit 1	MAIN[5][28][24]
PLL_CLKOUT4_DT bit 2	MAIN[5][28][25]
PLL_CLKOUT4_DT bit 3	MAIN[5][29][25]
PLL_CLKOUT4_DT bit 4	MAIN[5][29][26]
PLL_CLKOUT4_DT bit 5	MAIN[5][28][26]
PLL_CLKOUT4_EDGE	MAIN[5][29][27]
PLL_CLKOUT4_EN	MAIN[5][29][22]
PLL_CLKOUT4_HT bit 0	MAIN[5][28][19]
PLL_CLKOUT4_HT bit 1	MAIN[5][29][19]
PLL_CLKOUT4_HT bit 2	MAIN[5][29][20]
PLL_CLKOUT4_HT bit 3	MAIN[5][28][20]
PLL_CLKOUT4_HT bit 4	MAIN[5][28][21]
PLL_CLKOUT4_HT bit 5	MAIN[5][29][21]
PLL_CLKOUT4_LT bit 0	MAIN[5][29][16]
PLL_CLKOUT4_LT bit 1	MAIN[5][28][16]
PLL_CLKOUT4_LT bit 2	MAIN[5][28][17]
PLL_CLKOUT4_LT bit 3	MAIN[5][29][17]
PLL_CLKOUT4_LT bit 4	MAIN[5][29][18]
PLL_CLKOUT4_LT bit 5	MAIN[5][28][18]
PLL_CLKOUT4_NOCOUNT	MAIN[5][28][27]
PLL_CLKOUT4_PM bit 0	MAIN[5][28][22]
PLL_CLKOUT4_PM bit 1	MAIN[5][28][23]
PLL_CLKOUT4_PM bit 2	MAIN[5][29][23]
PLL_CLKOUT5_DT bit 0	MAIN[4][29][56]
PLL_CLKOUT5_DT bit 1	MAIN[4][28][56]
PLL_CLKOUT5_DT bit 2	MAIN[4][28][57]
PLL_CLKOUT5_DT bit 3	MAIN[4][29][57]
PLL_CLKOUT5_DT bit 4	MAIN[4][29][58]
PLL_CLKOUT5_DT bit 5	MAIN[4][28][58]
PLL_CLKOUT5_EDGE	MAIN[4][29][59]
PLL_CLKOUT5_EN	MAIN[4][29][54]
PLL_CLKOUT5_HT bit 0	MAIN[4][28][51]
PLL_CLKOUT5_HT bit 1	MAIN[4][29][51]
PLL_CLKOUT5_HT bit 2	MAIN[4][29][52]
PLL_CLKOUT5_HT bit 3	MAIN[4][28][52]
PLL_CLKOUT5_HT bit 4	MAIN[4][28][53]
PLL_CLKOUT5_HT bit 5	MAIN[4][29][53]
PLL_CLKOUT5_LT bit 0	MAIN[4][29][48]
PLL_CLKOUT5_LT bit 1	MAIN[4][28][48]
PLL_CLKOUT5_LT bit 2	MAIN[4][28][49]
PLL_CLKOUT5_LT bit 3	MAIN[4][29][49]
PLL_CLKOUT5_LT bit 4	MAIN[4][29][50]
PLL_CLKOUT5_LT bit 5	MAIN[4][28][50]
PLL_CLKOUT5_NOCOUNT	MAIN[4][28][59]
PLL_CLKOUT5_PM bit 0	MAIN[4][28][54]
PLL_CLKOUT5_PM bit 1	MAIN[4][28][55]
PLL_CLKOUT5_PM bit 2	MAIN[4][29][55]
PLL_CP bit 0	MAIN[3][29][8]
PLL_CP bit 1	MAIN[3][28][8]
PLL_CP bit 2	MAIN[3][28][9]
PLL_CP bit 3	MAIN[3][29][9]
PLL_CP_BIAS_TRIP_SHIFT	MAIN[3][28][7]
PLL_CP_RES bit 0	MAIN[3][29][10]
PLL_CP_RES bit 1	MAIN[3][28][10]
PLL_DIRECT_PATH_CNTRL	MAIN[6][29][0]
PLL_DIVCLK_DT bit 0	MAIN[4][28][21]
PLL_DIVCLK_DT bit 1	MAIN[4][29][21]
PLL_DIVCLK_DT bit 2	MAIN[4][29][22]
PLL_DIVCLK_DT bit 3	MAIN[4][28][22]
PLL_DIVCLK_DT bit 4	MAIN[4][28][23]
PLL_DIVCLK_DT bit 5	MAIN[4][29][23]
PLL_DIVCLK_EDGE	MAIN[3][28][54]
PLL_DIVCLK_HT bit 0	MAIN[3][28][51]
PLL_DIVCLK_HT bit 1	MAIN[3][29][51]
PLL_DIVCLK_HT bit 2	MAIN[3][29][52]
PLL_DIVCLK_HT bit 3	MAIN[3][28][52]
PLL_DIVCLK_HT bit 4	MAIN[3][28][53]
PLL_DIVCLK_HT bit 5	MAIN[3][29][53]
PLL_DIVCLK_LT bit 0	MAIN[3][29][48]
PLL_DIVCLK_LT bit 1	MAIN[3][28][48]
PLL_DIVCLK_LT bit 2	MAIN[3][28][49]
PLL_DIVCLK_LT bit 3	MAIN[3][29][49]
PLL_DIVCLK_LT bit 4	MAIN[3][29][50]
PLL_DIVCLK_LT bit 5	MAIN[3][28][50]
PLL_DIVCLK_NOCOUNT	MAIN[3][29][54]
PLL_DVDD_COMP_SET bit 0	MAIN[6][28][59]
PLL_DVDD_COMP_SET bit 1	MAIN[6][29][59]
PLL_DVDD_VBG_PD bit 0	MAIN[6][29][58]
PLL_DVDD_VBG_PD bit 1	MAIN[6][28][58]
PLL_DVDD_VBG_SEL bit 0	MAIN[6][29][56]
PLL_DVDD_VBG_SEL bit 1	MAIN[6][28][56]
PLL_DVDD_VBG_SEL bit 2	MAIN[6][28][57]
PLL_DVDD_VBG_SEL bit 3	MAIN[6][29][57]
PLL_EN	MAIN[5][29][15]
PLL_EN_CNTRL bit 0	MAIN[3][29][40]
PLL_EN_CNTRL bit 1	MAIN[3][28][40]
PLL_EN_CNTRL bit 2	MAIN[3][28][41]
PLL_EN_CNTRL bit 3	MAIN[3][29][41]
PLL_EN_CNTRL bit 4	MAIN[3][29][42]
PLL_EN_CNTRL bit 5	MAIN[3][28][42]
PLL_EN_CNTRL bit 6	MAIN[3][28][43]
PLL_EN_CNTRL bit 7	MAIN[3][29][43]
PLL_EN_CNTRL bit 8	MAIN[3][29][44]
PLL_EN_CNTRL bit 9	MAIN[3][28][44]
PLL_EN_CNTRL bit 10	MAIN[3][28][45]
PLL_EN_CNTRL bit 11	MAIN[3][29][45]
PLL_EN_CNTRL bit 12	MAIN[3][29][46]
PLL_EN_CNTRL bit 13	MAIN[3][28][46]
PLL_EN_CNTRL bit 14	MAIN[3][28][47]
PLL_EN_CNTRL bit 15	MAIN[3][29][47]
PLL_EN_CNTRL bit 16	MAIN[4][29][0]
PLL_EN_CNTRL bit 17	MAIN[4][28][0]
PLL_EN_CNTRL bit 18	MAIN[4][28][1]
PLL_EN_CNTRL bit 19	MAIN[4][29][1]
PLL_EN_CNTRL bit 20	MAIN[4][29][2]
PLL_EN_CNTRL bit 21	MAIN[4][28][2]
PLL_EN_CNTRL bit 22	MAIN[4][28][3]
PLL_EN_CNTRL bit 23	MAIN[4][29][3]
PLL_EN_CNTRL bit 24	MAIN[4][29][4]
PLL_EN_CNTRL bit 25	MAIN[4][28][4]
PLL_EN_CNTRL bit 26	MAIN[4][28][5]
PLL_EN_CNTRL bit 27	MAIN[4][29][5]
PLL_EN_CNTRL bit 28	MAIN[4][29][6]
PLL_EN_CNTRL bit 29	MAIN[4][28][6]
PLL_EN_CNTRL bit 30	MAIN[4][28][7]
PLL_EN_CNTRL bit 31	MAIN[4][29][7]
PLL_EN_CNTRL bit 32	MAIN[4][29][24]
PLL_EN_CNTRL bit 33	MAIN[4][28][24]
PLL_EN_CNTRL bit 34	MAIN[4][28][25]
PLL_EN_CNTRL bit 35	MAIN[4][29][25]
PLL_EN_CNTRL bit 36	MAIN[4][29][26]
PLL_EN_CNTRL bit 37	MAIN[4][28][26]
PLL_EN_CNTRL bit 38	MAIN[4][28][27]
PLL_EN_CNTRL bit 39	MAIN[4][29][27]
PLL_EN_CNTRL bit 40	MAIN[4][29][28]
PLL_EN_CNTRL bit 41	MAIN[4][28][28]
PLL_EN_CNTRL bit 42	MAIN[4][28][29]
PLL_EN_CNTRL bit 43	MAIN[4][29][29]
PLL_EN_CNTRL bit 44	MAIN[4][29][30]
PLL_EN_CNTRL bit 45	MAIN[4][28][30]
PLL_EN_CNTRL bit 46	MAIN[4][28][31]
PLL_EN_CNTRL bit 47	MAIN[4][29][31]
PLL_EN_CNTRL bit 48	MAIN[5][29][0]
PLL_EN_CNTRL bit 49	MAIN[5][28][0]
PLL_EN_CNTRL bit 50	MAIN[5][28][1]
PLL_EN_CNTRL bit 51	MAIN[5][29][1]
PLL_EN_CNTRL bit 52	MAIN[5][29][2]
PLL_EN_CNTRL bit 53	MAIN[5][28][2]
PLL_EN_CNTRL bit 54	MAIN[5][28][3]
PLL_EN_CNTRL bit 55	MAIN[5][29][3]
PLL_EN_CNTRL bit 56	MAIN[5][29][4]
PLL_EN_CNTRL bit 57	MAIN[5][28][4]
PLL_EN_CNTRL bit 58	MAIN[5][28][5]
PLL_EN_CNTRL bit 59	MAIN[5][29][5]
PLL_EN_CNTRL bit 60	MAIN[5][29][6]
PLL_EN_CNTRL bit 61	MAIN[5][28][6]
PLL_EN_CNTRL bit 62	MAIN[5][28][7]
PLL_EN_CNTRL bit 63	MAIN[5][29][7]
PLL_EN_CNTRL bit 64	MAIN[5][29][8]
PLL_EN_CNTRL bit 65	MAIN[5][28][8]
PLL_EN_CNTRL bit 66	MAIN[5][28][9]
PLL_EN_CNTRL bit 67	MAIN[5][29][9]
PLL_EN_CNTRL bit 68	MAIN[5][29][10]
PLL_EN_CNTRL bit 69	MAIN[5][28][10]
PLL_EN_CNTRL bit 70	MAIN[5][28][11]
PLL_EN_CNTRL bit 71	MAIN[5][29][11]
PLL_EN_CNTRL bit 72	MAIN[5][29][12]
PLL_EN_CNTRL bit 73	MAIN[5][28][12]
PLL_EN_CNTRL bit 74	MAIN[5][28][13]
PLL_EN_CNTRL bit 75	MAIN[5][29][13]
PLL_EN_CNTRL bit 76	MAIN[5][29][14]
PLL_EN_CNTRL bit 77	MAIN[5][28][14]
PLL_EN_DLY	MAIN[3][28][60]
PLL_EN_TCLK0	MAIN[3][28][37]
PLL_EN_TCLK1	MAIN[3][29][37]
PLL_EN_TCLK2	MAIN[3][29][38]
PLL_EN_TCLK3	MAIN[3][28][38]
PLL_EN_TCLK4	MAIN[3][28][39]
PLL_EN_VCO0	MAIN[6][29][1]
PLL_EN_VCO1	MAIN[6][29][2]
PLL_EN_VCO2	MAIN[6][28][2]
PLL_EN_VCO3	MAIN[6][28][3]
PLL_EN_VCO4	MAIN[6][29][3]
PLL_EN_VCO5	MAIN[6][29][4]
PLL_EN_VCO6	MAIN[6][28][4]
PLL_EN_VCO7	MAIN[6][28][5]
PLL_EN_VCO_DIV1	MAIN[6][28][0]
PLL_EN_VCO_DIV6	MAIN[6][28][1]
PLL_FLOCK bit 0	MAIN[3][28][33]
PLL_FLOCK bit 1	MAIN[3][29][33]
PLL_FLOCK bit 2	MAIN[3][29][34]
PLL_FLOCK bit 3	MAIN[3][28][34]
PLL_FLOCK bit 4	MAIN[3][28][35]
PLL_FLOCK bit 5	MAIN[3][29][35]
PLL_INC_FLOCK	MAIN[3][29][29]
PLL_INC_SLOCK	MAIN[3][28][29]
PLL_INTFB bit 0	MAIN[3][29][36]
PLL_INTFB bit 1	MAIN[3][28][36]
PLL_IN_DLY_MX_SEL bit 0	MAIN[3][28][61]
PLL_IN_DLY_MX_SEL bit 1	MAIN[3][29][61]
PLL_IN_DLY_MX_SEL bit 2	MAIN[3][29][62]
PLL_IN_DLY_MX_SEL bit 3	MAIN[3][28][62]
PLL_IN_DLY_MX_SEL bit 4	MAIN[3][28][63]
PLL_IN_DLY_SET bit 0	MAIN[3][29][56]
PLL_IN_DLY_SET bit 1	MAIN[3][28][56]
PLL_IN_DLY_SET bit 2	MAIN[3][28][57]
PLL_IN_DLY_SET bit 3	MAIN[3][29][57]
PLL_IN_DLY_SET bit 4	MAIN[3][29][58]
PLL_IN_DLY_SET bit 5	MAIN[3][28][58]
PLL_IN_DLY_SET bit 6	MAIN[3][28][59]
PLL_IN_DLY_SET bit 7	MAIN[3][29][59]
PLL_IN_DLY_SET bit 8	MAIN[3][29][60]
PLL_LFHF bit 0	MAIN[3][28][11]
PLL_LFHF bit 1	MAIN[3][29][11]
PLL_LF_NEN bit 0	MAIN[3][29][1]
PLL_LF_NEN bit 1	MAIN[3][29][2]
PLL_LF_PEN bit 0	MAIN[3][28][0]
PLL_LF_PEN bit 1	MAIN[3][28][1]
PLL_LOCK_CNT bit 0	MAIN[3][29][16]
PLL_LOCK_CNT bit 1	MAIN[3][28][16]
PLL_LOCK_CNT bit 2	MAIN[3][28][17]
PLL_LOCK_CNT bit 3	MAIN[3][29][17]
PLL_LOCK_CNT bit 4	MAIN[3][29][18]
PLL_LOCK_CNT bit 5	MAIN[3][28][18]
PLL_LOCK_CNT_RST_FAST	MAIN[3][29][32]
PLL_LOCK_FB_P1 bit 0	MAIN[3][29][24]
PLL_LOCK_FB_P1 bit 1	MAIN[3][28][24]
PLL_LOCK_FB_P1 bit 2	MAIN[3][28][25]
PLL_LOCK_FB_P1 bit 3	MAIN[3][29][25]
PLL_LOCK_FB_P1 bit 4	MAIN[3][29][26]
PLL_LOCK_FB_P2 bit 0	MAIN[3][28][26]
PLL_LOCK_FB_P2 bit 1	MAIN[3][28][27]
PLL_LOCK_FB_P2 bit 2	MAIN[3][29][27]
PLL_LOCK_FB_P2 bit 3	MAIN[3][29][28]
PLL_LOCK_FB_P2 bit 4	MAIN[3][28][28]
PLL_LOCK_REF_P1 bit 0	MAIN[3][28][19]
PLL_LOCK_REF_P1 bit 1	MAIN[3][29][19]
PLL_LOCK_REF_P1 bit 2	MAIN[3][29][20]
PLL_LOCK_REF_P1 bit 3	MAIN[3][28][20]
PLL_LOCK_REF_P1 bit 4	MAIN[3][28][21]
PLL_LOCK_REF_P2 bit 0	MAIN[3][29][21]
PLL_LOCK_REF_P2 bit 1	MAIN[3][29][22]
PLL_LOCK_REF_P2 bit 2	MAIN[3][28][22]
PLL_LOCK_REF_P2 bit 3	MAIN[3][28][23]
PLL_LOCK_REF_P2 bit 4	MAIN[3][29][23]
PLL_MAN_LF_EN	MAIN[3][29][0]
PLL_MISC bit 0	MAIN[3][28][5]
PLL_MISC bit 1	MAIN[3][29][5]
PLL_MISC bit 2	MAIN[3][29][6]
PLL_MISC bit 3	MAIN[3][28][6]
PLL_NBTI_EN	MAIN[4][28][45]
PLL_PFD_CNTRL bit 0	MAIN[3][28][13]
PLL_PFD_CNTRL bit 1	MAIN[3][29][13]
PLL_PFD_CNTRL bit 2	MAIN[3][29][14]
PLL_PFD_CNTRL bit 3	MAIN[3][28][14]
PLL_PFD_DLY bit 0	MAIN[3][29][12]
PLL_PFD_DLY bit 1	MAIN[3][28][12]
PLL_PMCD_MODE	MAIN[5][28][15]
PLL_PWRD_CFG	MAIN[3][29][15]
PLL_RES bit 0	MAIN[3][28][3]
PLL_RES bit 1	MAIN[3][29][3]
PLL_RES bit 2	MAIN[3][29][4]
PLL_RES bit 3	MAIN[3][28][4]
PLL_SEL_SLIPD	MAIN[3][29][7]
PLL_TCK4_SEL bit 0	!MAIN[3][29][39]
PLL_UNLOCK_CNT bit 0	MAIN[3][29][30]
PLL_UNLOCK_CNT bit 1	MAIN[3][28][30]
PLL_UNLOCK_CNT bit 2	MAIN[3][28][31]
PLL_UNLOCK_CNT bit 3	MAIN[3][29][31]
PLL_UNLOCK_CNT_RST_FAST	MAIN[3][28][32]
PLL_VLFHIGH_DIS	MAIN[3][28][2]

Bel wires

virtex5 CMT bel wires
Wire	Pins
CELL[0].IMUX_CTRL_SITE[0]	DCM[0].SKEWRST
CELL[0].IMUX_IMUX[0]	DCM[0].SCANIN[0]
CELL[0].IMUX_IMUX[1]	DCM[0].SCANIN[1]
CELL[0].IMUX_IMUX[2]	DCM[0].SCANIN[2]
CELL[0].IMUX_IMUX[3]	DCM[0].SCANIN[3]
CELL[0].IMUX_IMUX[4]	DCM[0].SCANIN[4]
CELL[0].OUT_BEL[0]	DCM[0].DRDY
CELL[0].OUT_BEL[1]	DCM[0].SCANOUT[1]
CELL[0].OUT_BEL[2]	DCM[0].SCANOUT[0]
CELL[0].OUT_BEL[3]	DCM[0].SKEWOUT
CELL[0].OUT_CMT[0]	DCM[0].CLK0
CELL[0].OUT_CMT[1]	DCM[0].CLK90
CELL[0].OUT_CMT[2]	DCM[0].CLK180
CELL[0].OUT_CMT[3]	DCM[0].CLK270
CELL[0].OUT_CMT[4]	DCM[0].CLK2X
CELL[0].OUT_CMT[5]	DCM[0].CLK2X180
CELL[0].OUT_CMT[6]	DCM[0].CLKDV
CELL[0].OUT_CMT[7]	DCM[0].CLKFX
CELL[0].OUT_CMT[8]	DCM[0].CLKFX180
CELL[0].OUT_CMT[9]	DCM[0].CONCUR
CELL[0].OUT_CMT[11]	PLL[0].CLKFBOUT
CELL[0].OUT_CMT[12]	PLL[0].CLKOUT0
CELL[0].OUT_CMT[13]	PLL[0].CLKOUT1
CELL[0].OUT_CMT[14]	PLL[0].CLKOUT2
CELL[0].OUT_CMT[15]	PLL[0].CLKOUT3
CELL[0].OUT_CMT[16]	PLL[0].CLKOUT4
CELL[0].OUT_CMT[17]	PLL[0].CLKOUT5
CELL[0].OUT_CMT[18]	DCM[1].CLK0
CELL[0].OUT_CMT[19]	DCM[1].CLK90
CELL[0].OUT_CMT[20]	DCM[1].CLK180
CELL[0].OUT_CMT[21]	DCM[1].CLK270
CELL[0].OUT_CMT[22]	DCM[1].CLK2X
CELL[0].OUT_CMT[23]	DCM[1].CLK2X180
CELL[0].OUT_CMT[24]	DCM[1].CLKDV
CELL[0].OUT_CMT[25]	DCM[1].CLKFX
CELL[0].OUT_CMT[26]	DCM[1].CLKFX180
CELL[0].OUT_CMT[27]	DCM[1].CONCUR
CELL[0].IMUX_DCM_CLKIN[0]	DCM[0].CLKIN
CELL[0].IMUX_DCM_CLKIN[1]	DCM[1].CLKIN
CELL[0].IMUX_DCM_CLKFB[0]	DCM[0].CLKFB
CELL[0].IMUX_DCM_CLKFB[1]	DCM[1].CLKFB
CELL[0].OMUX_DCM_SKEWCLKIN1[0]	DCM[0].SKEWCLKIN1
CELL[0].OMUX_DCM_SKEWCLKIN1[1]	DCM[1].SKEWCLKIN1
CELL[0].OMUX_DCM_SKEWCLKIN2[0]	DCM[0].SKEWCLKIN2
CELL[0].OMUX_DCM_SKEWCLKIN2[1]	DCM[1].SKEWCLKIN2
CELL[0].IMUX_PLL_CLKIN1	PLL[0].CLKIN1
CELL[0].IMUX_PLL_CLKIN2	PLL[0].CLKIN2
CELL[0].IMUX_PLL_CLKFB	PLL[0].CLKFBIN
CELL[0].TEST_PLL_CLKIN	PLL[0].TEST_CLKIN
CELL[0].OMUX_PLL_SKEWCLKIN1	PLL[0].SKEWCLKIN2
CELL[0].OMUX_PLL_SKEWCLKIN2	PLL[0].SKEWCLKIN1
CELL[0].OUT_PLL_CLKOUTDCM[0]	PLL[0].CLKOUTDCM0
CELL[0].OUT_PLL_CLKOUTDCM[1]	PLL[0].CLKOUTDCM1
CELL[0].OUT_PLL_CLKOUTDCM[2]	PLL[0].CLKOUTDCM2
CELL[0].OUT_PLL_CLKOUTDCM[3]	PLL[0].CLKOUTDCM3
CELL[0].OUT_PLL_CLKOUTDCM[4]	PLL[0].CLKOUTDCM4
CELL[0].OUT_PLL_CLKOUTDCM[5]	PLL[0].CLKOUTDCM5
CELL[0].OUT_PLL_CLKFBDCM	PLL[0].CLKFBDCM
CELL[1].IMUX_CLK[0]	DCM[0].DCLK
CELL[1].IMUX_CLK[1]	DCM[1].SKEWIN
CELL[1].IMUX_CTRL_SITE[0]	DCM[0].RST
CELL[1].IMUX_IMUX[0]	DCM[0].DI[0]
CELL[1].IMUX_IMUX[1]	DCM[0].DI[1]
CELL[1].IMUX_IMUX[2]	DCM[0].DI[2]
CELL[1].IMUX_IMUX[3]	DCM[0].DI[3]
CELL[1].IMUX_IMUX[4]	DCM[0].DI[4]
CELL[1].IMUX_IMUX[5]	DCM[0].DI[5]
CELL[1].IMUX_IMUX[6]	DCM[0].DI[6]
CELL[1].IMUX_IMUX[7]	DCM[0].DI[7]
CELL[1].IMUX_IMUX[8]	DCM[0].DI[8]
CELL[1].IMUX_IMUX[9]	DCM[0].DI[9]
CELL[1].IMUX_IMUX[10]	DCM[0].DI[10]
CELL[1].IMUX_IMUX[11]	DCM[0].DI[11]
CELL[1].IMUX_IMUX[12]	DCM[0].DI[12]
CELL[1].IMUX_IMUX[13]	DCM[0].DI[13]
CELL[1].IMUX_IMUX[14]	DCM[0].DI[14]
CELL[1].IMUX_IMUX[15]	DCM[0].DI[15]
CELL[1].IMUX_IMUX[16]	DCM[0].DADDR[0]
CELL[1].IMUX_IMUX[17]	DCM[0].DADDR[1]
CELL[1].IMUX_IMUX[18]	DCM[0].DADDR[2]
CELL[1].IMUX_IMUX[19]	DCM[0].DADDR[3]
CELL[1].IMUX_IMUX[20]	DCM[0].DADDR[4]
CELL[1].IMUX_IMUX[21]	DCM[0].DADDR[5]
CELL[1].IMUX_IMUX[22]	DCM[0].DADDR[6]
CELL[1].IMUX_IMUX[23]	DCM[0].DEN
CELL[1].IMUX_IMUX[24]	DCM[0].DWE
CELL[1].OUT_BEL[0]	DCM[0].DO[0]
CELL[1].OUT_BEL[1]	DCM[0].DO[1]
CELL[1].OUT_BEL[2]	DCM[0].DO[2]
CELL[1].OUT_BEL[3]	DCM[0].DO[3]
CELL[1].OUT_BEL[4]	DCM[0].DO[4]
CELL[1].OUT_BEL[5]	DCM[0].DO[5]
CELL[1].OUT_BEL[6]	DCM[0].DO[6]
CELL[1].OUT_BEL[7]	DCM[0].DO[7]
CELL[1].OUT_BEL[8]	DCM[0].DO[8]
CELL[1].OUT_BEL[9]	DCM[0].DO[9]
CELL[1].OUT_BEL[10]	DCM[0].DO[10]
CELL[1].OUT_BEL[11]	DCM[0].DO[11]
CELL[1].OUT_BEL[12]	DCM[0].DO[12]
CELL[1].OUT_BEL[13]	DCM[0].DO[13]
CELL[1].OUT_BEL[14]	DCM[0].DO[14]
CELL[1].OUT_BEL[15]	DCM[0].DO[15]
CELL[2].IMUX_CLK[0]	DCM[0].PSCLK
CELL[2].IMUX_IMUX[0]	DCM[0].CTLOSC2
CELL[2].IMUX_IMUX[1]	DCM[0].CTLOSC1
CELL[2].IMUX_IMUX[2]	DCM[0].CTLMODE
CELL[2].IMUX_IMUX[3]	DCM[0].CTLGO
CELL[2].IMUX_IMUX[4]	DCM[0].CTLSEL[0]
CELL[2].IMUX_IMUX[5]	DCM[0].CTLSEL[1]
CELL[2].IMUX_IMUX[6]	DCM[0].CTLSEL[2]
CELL[2].IMUX_IMUX[7]	DCM[0].FREEZEDFS
CELL[2].IMUX_IMUX[8]	DCM[0].FREEZEDLL
CELL[2].IMUX_IMUX[9]	DCM[0].PSEN
CELL[2].IMUX_IMUX[10]	DCM[0].PSINCDEC
CELL[2].OUT_BEL[0]	DCM[0].LOCKED
CELL[2].OUT_BEL[11]	DCM[0].PSDONE
CELL[3].IMUX_CLK[1]	PLL[0].SKEWSTB
CELL[3].IMUX_IMUX[2]	PLL[0].MANPULF
CELL[3].IMUX_IMUX[28]	PLL[0].SKEWRST
CELL[3].IMUX_IMUX[37]	PLL[0].MANPDLF
CELL[3].OUT_BEL[2]	PLL[0].TEST[6]
CELL[3].OUT_BEL[3]	PLL[0].TEST[5]
CELL[3].OUT_BEL[7]	PLL[0].TEST[7]
CELL[3].OUT_BEL[9]	PLL[0].TEST[1]
CELL[3].OUT_BEL[10]	PLL[0].TEST[17]
CELL[3].OUT_BEL[11]	PLL[0].TEST[10]
CELL[3].OUT_BEL[15]	PLL[0].TEST[8]
CELL[3].OUT_BEL[16]	PLL[0].TEST[4]
CELL[3].OUT_BEL[17]	PLL[0].TEST[9]
CELL[3].OUT_BEL[19]	PLL[0].TEST[0]
CELL[3].OUT_BEL[20]	PLL[0].TEST[3]
CELL[3].OUT_BEL[21]	PLL[0].LOCKED
CELL[3].OUT_BEL[23]	PLL[0].TEST[2]
CELL[4].IMUX_CTRL_SITE[0]	PLL[0].RST
CELL[4].IMUX_IMUX[0]	PLL[0].ENOUTSYNC
CELL[4].IMUX_IMUX[19]	PLL[0].REL
CELL[4].IMUX_IMUX[30]	PLL[0].CLKINSEL
CELL[4].IMUX_IMUX[35]	PLL[0].DADDR[4]
CELL[4].OUT_BEL[1]	PLL[0].TEST[14]
CELL[4].OUT_BEL[4]	PLL[0].TEST[13]
CELL[4].OUT_BEL[5]	PLL[0].TEST[15]
CELL[4].OUT_BEL[6]	PLL[0].TEST[23]
CELL[4].OUT_BEL[7]	PLL[0].TEST[24]
CELL[4].OUT_BEL[8]	PLL[0].TEST[11]
CELL[4].OUT_BEL[9]	PLL[0].TEST[18]
CELL[4].OUT_BEL[10]	PLL[0].TEST[21]
CELL[4].OUT_BEL[11]	PLL[0].TEST[26]
CELL[4].OUT_BEL[13]	PLL[0].TEST[16]
CELL[4].OUT_BEL[14]	PLL[0].TEST[22]
CELL[4].OUT_BEL[15]	PLL[0].TEST[25]
CELL[4].OUT_BEL[18]	PLL[0].TEST[12]
CELL[4].OUT_BEL[20]	PLL[0].TEST[20]
CELL[4].OUT_BEL[21]	PLL[0].TEST[27]
CELL[4].OUT_BEL[22]	PLL[0].LOCKED
CELL[4].OUT_BEL[23]	PLL[0].TEST[19]
CELL[5].IMUX_CLK[0]	PLL[0].DCLK
CELL[5].IMUX_IMUX[1]	PLL[0].DADDR[2]
CELL[5].IMUX_IMUX[4]	PLL[0].DI[15]
CELL[5].IMUX_IMUX[9]	PLL[0].DWE
CELL[5].IMUX_IMUX[12]	PLL[0].DADDR[3]
CELL[5].IMUX_IMUX[19]	PLL[0].CLKBRST
CELL[5].IMUX_IMUX[20]	PLL[0].DADDR[0]
CELL[5].IMUX_IMUX[28]	PLL[0].DI[13]
CELL[5].IMUX_IMUX[35]	PLL[0].DI[10]
CELL[5].IMUX_IMUX[37]	PLL[0].DADDR[1]
CELL[5].IMUX_IMUX[38]	PLL[0].DEN
CELL[5].IMUX_IMUX[41]	PLL[0].DI[11]
CELL[5].IMUX_IMUX[45]	PLL[0].DI[14]
CELL[5].IMUX_IMUX[46]	PLL[0].DI[12]
CELL[5].OUT_BEL[1]	PLL[0].TEST[31]
CELL[5].OUT_BEL[2]	PLL[0].DO[13]
CELL[5].OUT_BEL[4]	PLL[0].TEST[30]
CELL[5].OUT_BEL[5]	PLL[0].TEST[32]
CELL[5].OUT_BEL[7]	PLL[0].DO[12]
CELL[5].OUT_BEL[8]	PLL[0].TEST[28]
CELL[5].OUT_BEL[9]	PLL[0].DRDY
CELL[5].OUT_BEL[11]	PLL[0].DO[10]
CELL[5].OUT_BEL[13]	PLL[0].TEST[33]
CELL[5].OUT_BEL[14]	PLL[0].DO[14]
CELL[5].OUT_BEL[16]	PLL[0].DO[15]
CELL[5].OUT_BEL[17]	PLL[0].DO[11]
CELL[5].OUT_BEL[18]	PLL[0].TEST[29]
CELL[5].OUT_BEL[19]	PLL[0].TEST[34]
CELL[6].IMUX_IMUX[2]	PLL[0].DI[5]
CELL[6].IMUX_IMUX[3]	PLL[0].DI[2]
CELL[6].IMUX_IMUX[9]	PLL[0].DI[1]
CELL[6].IMUX_IMUX[12]	PLL[0].DI[9]
CELL[6].IMUX_IMUX[13]	PLL[0].DI[6]
CELL[6].IMUX_IMUX[15]	PLL[0].DI[0]
CELL[6].IMUX_IMUX[19]	PLL[0].DI[7]
CELL[6].IMUX_IMUX[20]	PLL[0].DI[4]
CELL[6].IMUX_IMUX[30]	PLL[0].DI[8]
CELL[6].IMUX_IMUX[44]	PLL[0].DI[3]
CELL[6].OUT_BEL[1]	PLL[0].DO[6]
CELL[6].OUT_BEL[3]	PLL[0].DO[0]
CELL[6].OUT_BEL[4]	PLL[0].DO[7]
CELL[6].OUT_BEL[6]	PLL[0].DO[1]
CELL[6].OUT_BEL[8]	PLL[0].DO[9]
CELL[6].OUT_BEL[13]	PLL[0].DO[5]
CELL[6].OUT_BEL[18]	PLL[0].DO[8]
CELL[6].OUT_BEL[19]	PLL[0].DO[4]
CELL[6].OUT_BEL[20]	PLL[0].DO[2]
CELL[6].OUT_BEL[23]	PLL[0].DO[3]
CELL[7].IMUX_CTRL_SITE[0]	DCM[1].SKEWRST
CELL[7].IMUX_IMUX[0]	DCM[1].SCANIN[0]
CELL[7].IMUX_IMUX[1]	DCM[1].SCANIN[1]
CELL[7].IMUX_IMUX[2]	DCM[1].SCANIN[2]
CELL[7].IMUX_IMUX[3]	DCM[1].SCANIN[3]
CELL[7].IMUX_IMUX[4]	DCM[1].SCANIN[4]
CELL[7].OUT_BEL[0]	DCM[1].DRDY
CELL[7].OUT_BEL[1]	DCM[1].SCANOUT[1]
CELL[7].OUT_BEL[2]	DCM[1].SCANOUT[0]
CELL[7].OUT_BEL[3]	DCM[1].SKEWOUT
CELL[8].IMUX_CLK[0]	DCM[1].DCLK
CELL[8].IMUX_CLK[1]	DCM[0].SKEWIN
CELL[8].IMUX_CTRL_SITE[0]	DCM[1].RST
CELL[8].IMUX_IMUX[0]	DCM[1].DI[0]
CELL[8].IMUX_IMUX[1]	DCM[1].DI[1]
CELL[8].IMUX_IMUX[2]	DCM[1].DI[2]
CELL[8].IMUX_IMUX[3]	DCM[1].DI[3]
CELL[8].IMUX_IMUX[4]	DCM[1].DI[4]
CELL[8].IMUX_IMUX[5]	DCM[1].DI[5]
CELL[8].IMUX_IMUX[6]	DCM[1].DI[6]
CELL[8].IMUX_IMUX[7]	DCM[1].DI[7]
CELL[8].IMUX_IMUX[8]	DCM[1].DI[8]
CELL[8].IMUX_IMUX[9]	DCM[1].DI[9]
CELL[8].IMUX_IMUX[10]	DCM[1].DI[10]
CELL[8].IMUX_IMUX[11]	DCM[1].DI[11]
CELL[8].IMUX_IMUX[12]	DCM[1].DI[12]
CELL[8].IMUX_IMUX[13]	DCM[1].DI[13]
CELL[8].IMUX_IMUX[14]	DCM[1].DI[14]
CELL[8].IMUX_IMUX[15]	DCM[1].DI[15]
CELL[8].IMUX_IMUX[16]	DCM[1].DADDR[0]
CELL[8].IMUX_IMUX[17]	DCM[1].DADDR[1]
CELL[8].IMUX_IMUX[18]	DCM[1].DADDR[2]
CELL[8].IMUX_IMUX[19]	DCM[1].DADDR[3]
CELL[8].IMUX_IMUX[20]	DCM[1].DADDR[4]
CELL[8].IMUX_IMUX[21]	DCM[1].DADDR[5]
CELL[8].IMUX_IMUX[22]	DCM[1].DADDR[6]
CELL[8].IMUX_IMUX[23]	DCM[1].DEN
CELL[8].IMUX_IMUX[24]	DCM[1].DWE
CELL[8].OUT_BEL[0]	DCM[1].DO[0]
CELL[8].OUT_BEL[1]	DCM[1].DO[1]
CELL[8].OUT_BEL[2]	DCM[1].DO[2]
CELL[8].OUT_BEL[3]	DCM[1].DO[3]
CELL[8].OUT_BEL[4]	DCM[1].DO[4]
CELL[8].OUT_BEL[5]	DCM[1].DO[5]
CELL[8].OUT_BEL[6]	DCM[1].DO[6]
CELL[8].OUT_BEL[7]	DCM[1].DO[7]
CELL[8].OUT_BEL[8]	DCM[1].DO[8]
CELL[8].OUT_BEL[9]	DCM[1].DO[9]
CELL[8].OUT_BEL[10]	DCM[1].DO[10]
CELL[8].OUT_BEL[11]	DCM[1].DO[11]
CELL[8].OUT_BEL[12]	DCM[1].DO[12]
CELL[8].OUT_BEL[13]	DCM[1].DO[13]
CELL[8].OUT_BEL[14]	DCM[1].DO[14]
CELL[8].OUT_BEL[15]	DCM[1].DO[15]
CELL[9].IMUX_CLK[0]	DCM[1].PSCLK
CELL[9].IMUX_IMUX[0]	DCM[1].CTLOSC2
CELL[9].IMUX_IMUX[1]	DCM[1].CTLOSC1
CELL[9].IMUX_IMUX[2]	DCM[1].CTLMODE
CELL[9].IMUX_IMUX[3]	DCM[1].CTLGO
CELL[9].IMUX_IMUX[4]	DCM[1].CTLSEL[0]
CELL[9].IMUX_IMUX[5]	DCM[1].CTLSEL[1]
CELL[9].IMUX_IMUX[6]	DCM[1].CTLSEL[2]
CELL[9].IMUX_IMUX[7]	DCM[1].FREEZEDFS
CELL[9].IMUX_IMUX[8]	DCM[1].FREEZEDLL
CELL[9].IMUX_IMUX[9]	DCM[1].PSEN
CELL[9].IMUX_IMUX[10]	DCM[1].PSINCDEC
CELL[9].OUT_BEL[0]	DCM[1].LOCKED
CELL[9].OUT_BEL[11]	DCM[1].PSDONE

Bitstream

virtex5 CMT rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 14 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 1	DCM[0]: DRP[7] bit 15 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 13 DCM[0]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 0	DCM[0]: DRP[7] bit 12 DCM[0]: DFS_CUSTOM_FAST_SYNC bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 10 DCM[0]: DFS_CUSTOM_FAST_SYNC bit 1	DCM[0]: DRP[7] bit 11 DCM[0]: DFS_CUSTOM_FAST_SYNC bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 9 DCM[0]: DFS_CUSTOM_FAST_SYNC bit 0	DCM[0]: DRP[7] bit 8 DCM[0]: DCM_CLKDV_CLKFX_ALIGNMENT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 6 DCM[0]: DFS_MPW_LOW	DCM[0]: DRP[7] bit 7 DCM[0]: DFS_MPW_HIGH	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 5 DCM[0]: DCM_UNUSED_TAPS_POWERDOWN bit 0	DCM[0]: DRP[7] bit 4 DCM[0]: ! DFS_EN_RELRST_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 2 DCM[0]: OUT_CONCUR_ENABLE	DCM[0]: DRP[7] bit 3 DCM[0]: DFS_OUTPUT_PSDLY_ON_CONCUR	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[7] bit 1 DCM[0]: OUT_CLKFX180_ENABLE	DCM[0]: DRP[7] bit 0 DCM[0]: OUT_CLKFX_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 14	DCM[0]: DRP[6] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 13	DCM[0]: DRP[6] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 10	DCM[0]: DRP[6] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 9	DCM[0]: DRP[6] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 6 DCM[0]: DFS_TWEAK bit 6	DCM[0]: DRP[6] bit 7 DCM[0]: DFS_TWEAK bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 5 DCM[0]: DFS_TWEAK bit 5	DCM[0]: DRP[6] bit 4 DCM[0]: DFS_TWEAK bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 2 DCM[0]: DFS_TWEAK bit 2	DCM[0]: DRP[6] bit 3 DCM[0]: DFS_TWEAK bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[6] bit 1 DCM[0]: DFS_TWEAK bit 1	DCM[0]: DRP[6] bit 0 DCM[0]: DFS_TWEAK bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 14	DCM[0]: DRP[5] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 13	DCM[0]: DRP[5] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 10 DCM[0]: DFS_TAPTRIM bit 10	DCM[0]: DRP[5] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 9 DCM[0]: DFS_TAPTRIM bit 9	DCM[0]: DRP[5] bit 8 DCM[0]: DFS_TAPTRIM bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 6 DCM[0]: DFS_TAPTRIM bit 6	DCM[0]: DRP[5] bit 7 DCM[0]: DFS_TAPTRIM bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 5 DCM[0]: DFS_TAPTRIM bit 5	DCM[0]: DRP[5] bit 4 DCM[0]: DFS_TAPTRIM bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 2 DCM[0]: DFS_TAPTRIM bit 2	DCM[0]: DRP[5] bit 3 DCM[0]: DFS_TAPTRIM bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[5] bit 1 DCM[0]: DFS_TAPTRIM bit 1	DCM[0]: DRP[5] bit 0 DCM[0]: DFS_TAPTRIM bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 14 DCM[0]: DFS_EN	DCM[0]: DRP[4] bit 15 DCM[0]: DFS_FAST_UPDATE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 13 DCM[0]: DFS_SYNC_TO_DLL	DCM[0]: DRP[4] bit 12 DCM[0]: DCM_CLKFB_IODLY_MUXINSEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 10 DCM[0]: CLKIN_DIVIDE_BY_2	DCM[0]: DRP[4] bit 11 DCM[0]: DCM_CLKIN_IODLY_MUXINSEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 9 DCM[0]: DCM_WAIT_PLL	DCM[0]: DRP[4] bit 8 DCM[0]: DFS_SYNTH_CLOCK_SPEED bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 6 DCM[0]: DFS_SYNTH_CLOCK_SPEED bit 0	DCM[0]: DRP[4] bit 7 DCM[0]: DFS_SYNTH_CLOCK_SPEED bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 5 DCM[0]: DLL_SYNTH_CLOCK_SPEED bit 1	DCM[0]: DRP[4] bit 4 DCM[0]: DLL_SYNTH_CLOCK_SPEED bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 2 DCM[0]: DCM_EXT_FB_EN	DCM[0]: DRP[4] bit 3 DCM[0]: DCM_USE_REG_READY	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[4] bit 1 DCM[0]: DCM_COM_PWC_FB_EN	DCM[0]: DRP[4] bit 0 DCM[0]: DCM_COM_PWC_REF_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 14 DCM[0]: DCM_COM_PWC_FB_TAP bit 1	DCM[0]: DRP[3] bit 15 DCM[0]: DCM_COM_PWC_FB_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 13 DCM[0]: DCM_COM_PWC_FB_TAP bit 0	DCM[0]: DRP[3] bit 12 DCM[0]: DCM_COM_PWC_REF_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 10 DCM[0]: DCM_COM_PWC_REF_TAP bit 0	DCM[0]: DRP[3] bit 11 DCM[0]: DCM_COM_PWC_REF_TAP bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 9 DCM[0]: DCM_PLL_RST_DCM	DCM[0]: DRP[3] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 6 DCM[0]: DESKEW_ADJUST bit 3	DCM[0]: DRP[3] bit 7 DCM[0]: DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 5 DCM[0]: DESKEW_ADJUST bit 2	DCM[0]: DRP[3] bit 4 DCM[0]: DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 2	DCM[0]: DRP[3] bit 3 DCM[0]: DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[3] bit 1 DCM[0]: DCM_CLKIN_IODLY_MUXOUT_SEL bit 0	DCM[0]: DRP[3] bit 0 DCM[0]: DCM_CLKFB_IODLY_MUXOUT_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 14 DCM[0]: ! DFS_PWRD_CLKIN_STOP_STICKY_B	DCM[0]: DRP[2] bit 15 DCM[0]: ! DFS_PWRD_CLKIN_STOP_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 13 DCM[0]: ! DFS_PWRD_REPLY_TIMES_OUT_B	DCM[0]: DRP[2] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 10 DCM[0]: DFS_HF_TRIM_CAL bit 1	DCM[0]: DRP[2] bit 11 DCM[0]: DFS_HF_TRIM_CAL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 9 DCM[0]: DFS_HF_TRIM_CAL bit 0	DCM[0]: DRP[2] bit 8 DCM[0]: DFS_REF_ON_FX	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 6 DCM[0]: DFS_JF_LOWER_LIMIT bit 3	DCM[0]: DRP[2] bit 7 DCM[0]: DFS_OSC_ON_FX	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 5 DCM[0]: DFS_JF_LOWER_LIMIT bit 2	DCM[0]: DRP[2] bit 4 DCM[0]: DFS_JF_LOWER_LIMIT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 2	DCM[0]: DRP[2] bit 3 DCM[0]: DFS_JF_LOWER_LIMIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[2] bit 1	DCM[0]: DRP[2] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 14 DCM[0]: DFS_HARDSYNC_B bit 0	DCM[0]: DRP[1] bit 15 DCM[0]: DFS_HARDSYNC_B bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 13	DCM[0]: DRP[1] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 10	DCM[0]: DRP[1] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 9 DCM[0]: DFS_EARLY_LOCK	DCM[0]: DRP[1] bit 8 DCM[0]: DFS_AVE_FREQ_GAIN bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 6 DCM[0]: DFS_AVE_FREQ_GAIN bit 1	DCM[0]: DRP[1] bit 7 DCM[0]: DFS_AVE_FREQ_GAIN bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 5 DCM[0]: DFS_SYNTH_FAST_SYNCH bit 1	DCM[0]: DRP[1] bit 4 DCM[0]: DFS_SYNTH_FAST_SYNCH bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 2 DCM[0]: DFS_FREQUENCY_MODE bit 0	DCM[0]: DRP[1] bit 3 DCM[0]: DFS_CFG_BYPASS	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[1] bit 1 DCM[0]: DFS_OSCILLATOR_MODE bit 0	DCM[0]: DRP[1] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 14	DCM[0]: DRP[0] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 13	DCM[0]: DRP[0] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 10	DCM[0]: DRP[0] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 9	DCM[0]: DRP[0] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 6	DCM[0]: DRP[0] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 5	DCM[0]: DRP[0] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 2	DCM[0]: DRP[0] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[0] bit 1	DCM[0]: DRP[0] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 14 DCM[0]: FACTORY_JF bit 14	DCM[0]: DRP[15] bit 15 DCM[0]: FACTORY_JF bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 13 DCM[0]: FACTORY_JF bit 13	DCM[0]: DRP[15] bit 12 DCM[0]: FACTORY_JF bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 10 DCM[0]: FACTORY_JF bit 10	DCM[0]: DRP[15] bit 11 DCM[0]: FACTORY_JF bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 9 DCM[0]: FACTORY_JF bit 9	DCM[0]: DRP[15] bit 8 DCM[0]: FACTORY_JF bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 6 DCM[0]: FACTORY_JF bit 6	DCM[0]: DRP[15] bit 7 DCM[0]: FACTORY_JF bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 5 DCM[0]: FACTORY_JF bit 5	DCM[0]: DRP[15] bit 4 DCM[0]: FACTORY_JF bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 2 DCM[0]: FACTORY_JF bit 2	DCM[0]: DRP[15] bit 3 DCM[0]: FACTORY_JF bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[15] bit 1 DCM[0]: FACTORY_JF bit 1	DCM[0]: DRP[15] bit 0 DCM[0]: FACTORY_JF bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 14 DCM[0]: DLL_DESKEW_MAXTAP bit 6	DCM[0]: DRP[14] bit 15 DCM[0]: DLL_DESKEW_MAXTAP bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 13 DCM[0]: DLL_DESKEW_MAXTAP bit 5	DCM[0]: DRP[14] bit 12 DCM[0]: DLL_DESKEW_MAXTAP bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 10 DCM[0]: DLL_DESKEW_MAXTAP bit 2	DCM[0]: DRP[14] bit 11 DCM[0]: DLL_DESKEW_MAXTAP bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 9 DCM[0]: DLL_DESKEW_MAXTAP bit 1	DCM[0]: DRP[14] bit 8 DCM[0]: DLL_DESKEW_MAXTAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 6 DCM[0]: DLL_DESKEW_MINTAP bit 6	DCM[0]: DRP[14] bit 7 DCM[0]: DLL_DESKEW_MINTAP bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 5 DCM[0]: DLL_DESKEW_MINTAP bit 5	DCM[0]: DRP[14] bit 4 DCM[0]: DLL_DESKEW_MINTAP bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 2 DCM[0]: DLL_DESKEW_MINTAP bit 2	DCM[0]: DRP[14] bit 3 DCM[0]: DLL_DESKEW_MINTAP bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[14] bit 1 DCM[0]: DLL_DESKEW_MINTAP bit 1	DCM[0]: DRP[14] bit 0 DCM[0]: DLL_DESKEW_MINTAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 14 DCM[0]: DLL_ZD1_TAP_INIT bit 6	DCM[0]: DRP[13] bit 15 DCM[0]: DLL_ZD1_TAP_INIT bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 13 DCM[0]: DLL_ZD1_TAP_INIT bit 5	DCM[0]: DRP[13] bit 12 DCM[0]: DLL_ZD1_TAP_INIT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 10 DCM[0]: DLL_ZD1_TAP_INIT bit 2	DCM[0]: DRP[13] bit 11 DCM[0]: DLL_ZD1_TAP_INIT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 9 DCM[0]: DLL_ZD1_TAP_INIT bit 1	DCM[0]: DRP[13] bit 8 DCM[0]: DLL_ZD1_TAP_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 6 DCM[0]: DLL_ZD2_TAP_INIT bit 6	DCM[0]: DRP[13] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 5 DCM[0]: DLL_ZD2_TAP_INIT bit 5	DCM[0]: DRP[13] bit 4 DCM[0]: DLL_ZD2_TAP_INIT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 2 DCM[0]: DLL_ZD2_TAP_INIT bit 2	DCM[0]: DRP[13] bit 3 DCM[0]: DLL_ZD2_TAP_INIT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[13] bit 1 DCM[0]: DLL_ZD2_TAP_INIT bit 1	DCM[0]: DRP[13] bit 0 DCM[0]: DLL_ZD2_TAP_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 14 DCM[0]: DCM_UNUSED_TAPS_POWERDOWN bit 1	DCM[0]: DRP[12] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 13 DCM[0]: DLL_ZD1_JF_OVERFLOW_HOLD	DCM[0]: DRP[12] bit 12 DCM[0]: DCM_UNUSED_TAPS_POWERDOWN bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 10 DCM[0]: DLL_DESKEW_LOCK_BY1	DCM[0]: DRP[12] bit 11 DCM[0]: DLL_ZD2_JF_OVERFLOW_HOLD	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 9 DCM[0]: DLL_PERIOD_LOCK_BY1	DCM[0]: DRP[12] bit 8 DCM[0]: DLL_ZD1_PHASE_SEL_INIT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 6 DCM[0]: ! DLL_PWRD_ON_SCANMODE_B	DCM[0]: DRP[12] bit 7 DCM[0]: DLL_ZD1_PHASE_SEL_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 5	DCM[0]: DRP[12] bit 4 DCM[0]: DLL_TAPINIT_CTL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 2 DCM[0]: DLL_TAPINIT_CTL bit 0	DCM[0]: DRP[12] bit 3 DCM[0]: DLL_TAPINIT_CTL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[12] bit 1 DCM[0]: DCM_SCANMODE	DCM[0]: DRP[12] bit 0 DCM[0]: DCM_UNUSED_TAPS_POWERDOWN bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 14	DCM[0]: DRP[11] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 13	DCM[0]: DRP[11] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 10	DCM[0]: DRP[11] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 9	DCM[0]: DRP[11] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: invert PSINCDEC DCM[0]: DRP[11] bit 6	DCM[0]: invert PSEN DCM[0]: DRP[11] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: invert RST DCM[0]: DRP[11] bit 5	DCM[0]: DRP[11] bit 4 DCM[0]: DLL_PHASE_SHIFT_LOCK_BY1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 2 DCM[0]: PS_CENTERED	DCM[0]: DRP[11] bit 3 DCM[0]: PS_DIRECT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[11] bit 1 DCM[0]: DLL_PHASE_SHIFT_CALIBRATION bit 1	DCM[0]: DRP[11] bit 0 DCM[0]: DLL_PHASE_SHIFT_CALIBRATION bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 14	DCM[0]: DRP[10] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 13	DCM[0]: DRP[10] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 10	DCM[0]: DRP[10] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 9	DCM[0]: DRP[10] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 6	DCM[0]: DRP[10] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 5	DCM[0]: DRP[10] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 2	DCM[0]: DRP[10] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[10] bit 1	DCM[0]: DRP[10] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[9] bit 14	DCM[0]: DRP[9] bit 15 DCM[0]: DCM_REG_PWRD_CFG	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[9] bit 13	DCM[0]: DRP[9] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[9] bit 10	DCM[0]: DRP[9] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[9] bit 9	DCM[0]: DRP[9] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[9] bit 6 DCM[0]: CLKIN_CLKFB_ENABLE	DCM[0]: DRP[9] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: invert SKEWRST DCM[0]: DRP[9] bit 5	DCM[0]: invert SKEWIN DCM[0]: DRP[9] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[0] bit 2 DCM[0]: DRP[9] bit 2	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[0] bit 3 DCM[0]: DRP[9] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[0] bit 1 DCM[0]: DRP[9] bit 1	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[0] bit 0 DCM[0]: DRP[9] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: invert SKEWCLKIN1 DCM[0]: DRP[8] bit 14	DCM[0]: invert SKEWCLKIN2 DCM[0]: DRP[8] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[0] bit 3 DCM[0]: DRP[8] bit 13	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[0] bit 2 DCM[0]: DRP[8] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[0] bit 0 DCM[0]: DRP[8] bit 10	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[0] bit 1 DCM[0]: DRP[8] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[0] bit 3 DCM[0]: DRP[8] bit 9	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[0] bit 4 DCM[0]: DRP[8] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[0] bit 2 DCM[0]: DRP[8] bit 6	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[0] bit 1 DCM[0]: DRP[8] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[0] bit 0 DCM[0]: DRP[8] bit 5	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[0] bit 4 DCM[0]: DRP[8] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[0] bit 3 DCM[0]: DRP[8] bit 2	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[0] bit 2 DCM[0]: DRP[8] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[0] bit 0 DCM[0]: DRP[8] bit 1	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[0] bit 1 DCM[0]: DRP[8] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 14 DCM[0]: DCM_COMMON_MSB_SEL bit 1	DCM[0]: DRP[23] bit 15 DCM[0]: DCM_VSPLY_VALID_ACC bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 13 DCM[0]: DCM_COMMON_MSB_SEL bit 0	DCM[0]: DRP[23] bit 12 DCM[0]: DCM_VBG_PD bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 10 DCM[0]: ! DCM_POWERDOWN_COMMON_EN_B	DCM[0]: DRP[23] bit 11 DCM[0]: DCM_VBG_PD bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 9 DCM[0]: DLL_ZD2_PWC_EN	DCM[0]: DRP[23] bit 8 DCM[0]: DCM_VBG_SEL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 6 DCM[0]: ! DLL_PWRD_STICKY_B	DCM[0]: DRP[23] bit 7 DCM[0]: DCM_VBG_SEL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 5 DCM[0]: DLL_ETPP_HOLD	DCM[0]: DRP[23] bit 4 DCM[0]: DCM_VBG_SEL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 2 DCM[0]: STARTUP_WAIT	DCM[0]: DRP[23] bit 3 DCM[0]: DCM_VBG_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[23] bit 1 DCM[0]: DLL_ZD1_PWC_EN	DCM[0]: DRP[23] bit 0 DCM[0]: DCM_VSPLY_VALID_ACC bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 14 DCM[0]: DLL_ZD1_PWC_TAP bit 2	DCM[0]: DRP[22] bit 15 DCM[0]: DCM_VREG_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 13 DCM[0]: DLL_ZD1_PWC_TAP bit 1	DCM[0]: DRP[22] bit 12 DCM[0]: DLL_ZD1_PWC_TAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 10 DCM[0]: DLL_ZD2_PWC_TAP bit 1	DCM[0]: DRP[22] bit 11 DCM[0]: DLL_ZD2_PWC_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 9 DCM[0]: DLL_ZD2_PWC_TAP bit 0	DCM[0]: DRP[22] bit 8 DCM[0]: DLL_PHASE_SHIFT_LFC bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 6 DCM[0]: DLL_PHASE_SHIFT_LFC bit 6	DCM[0]: DRP[22] bit 7 DCM[0]: DLL_PHASE_SHIFT_LFC bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 5 DCM[0]: DLL_PHASE_SHIFT_LFC bit 5	DCM[0]: DRP[22] bit 4 DCM[0]: DLL_PHASE_SHIFT_LFC bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 2 DCM[0]: DLL_PHASE_SHIFT_LFC bit 2	DCM[0]: DRP[22] bit 3 DCM[0]: DLL_PHASE_SHIFT_LFC bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[22] bit 1 DCM[0]: DLL_PHASE_SHIFT_LFC bit 1	DCM[0]: DRP[22] bit 0 DCM[0]: DLL_PHASE_SHIFT_LFC bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 14	DCM[0]: DRP[21] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 13	DCM[0]: DRP[21] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 10 DCM[0]: PHASE_SHIFT_NEGATIVE	DCM[0]: DRP[21] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 9 DCM[0]: PHASE_SHIFT bit 9	DCM[0]: DRP[21] bit 8 DCM[0]: PHASE_SHIFT bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 6 DCM[0]: PHASE_SHIFT bit 6	DCM[0]: DRP[21] bit 7 DCM[0]: PHASE_SHIFT bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 5 DCM[0]: PHASE_SHIFT bit 5	DCM[0]: DRP[21] bit 4 DCM[0]: PHASE_SHIFT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 2 DCM[0]: PHASE_SHIFT bit 2	DCM[0]: DRP[21] bit 3 DCM[0]: PHASE_SHIFT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[21] bit 1 DCM[0]: PHASE_SHIFT bit 1	DCM[0]: DRP[21] bit 0 DCM[0]: PHASE_SHIFT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 14 DCM[0]: DLL_TEST_MUX_SEL bit 0	DCM[0]: DRP[20] bit 15 DCM[0]: DLL_TEST_MUX_SEL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 13 DCM[0]: DCM_TRIM_CAL bit 2	DCM[0]: DRP[20] bit 12 DCM[0]: DCM_TRIM_CAL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 10 DCM[0]: OUT_CLKDV_ENABLE	DCM[0]: DRP[20] bit 11 DCM[0]: DCM_TRIM_CAL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 9 DCM[0]: OUT_CLK2X180_ENABLE	DCM[0]: DRP[20] bit 8 DCM[0]: OUT_CLK2X_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 6 DCM[0]: OUT_CLK180_ENABLE	DCM[0]: DRP[20] bit 7 DCM[0]: OUT_CLK270_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 5 DCM[0]: OUT_CLK90_ENABLE	DCM[0]: DRP[20] bit 4 DCM[0]: OUT_CLK0_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 2 DCM[0]: DCM_CLKLOST_EN	DCM[0]: DRP[20] bit 3 DCM[0]: ! DCM_LOCK_HIGH_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[20] bit 1 DCM[0]: DLL_FDBKLOST_EN	DCM[0]: DRP[20] bit 0 DCM[0]: CLKDV_MODE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 14 DCM[0]: CLKDV_PHASE_FALL bit 0	DCM[0]: DRP[19] bit 15 DCM[0]: CLKDV_PHASE_FALL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 13 DCM[0]: CLKDV_PHASE_RISE bit 1	DCM[0]: DRP[19] bit 12 DCM[0]: CLKDV_PHASE_RISE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 10 DCM[0]: CLKDV_COUNT_FALL_2 bit 2	DCM[0]: DRP[19] bit 11 DCM[0]: CLKDV_COUNT_FALL_2 bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 9 DCM[0]: CLKDV_COUNT_FALL_2 bit 1	DCM[0]: DRP[19] bit 8 DCM[0]: CLKDV_COUNT_FALL_2 bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 6 DCM[0]: CLKDV_COUNT_FALL bit 2	DCM[0]: DRP[19] bit 7 DCM[0]: CLKDV_COUNT_FALL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 5 DCM[0]: CLKDV_COUNT_FALL bit 1	DCM[0]: DRP[19] bit 4 DCM[0]: CLKDV_COUNT_FALL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 2 DCM[0]: CLKDV_COUNT_MAX bit 2	DCM[0]: DRP[19] bit 3 DCM[0]: CLKDV_COUNT_MAX bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[19] bit 1 DCM[0]: CLKDV_COUNT_MAX bit 1	DCM[0]: DRP[19] bit 0 DCM[0]: CLKDV_COUNT_MAX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 14 DCM[0]: DLL_DEAD_TIME bit 6	DCM[0]: DRP[18] bit 15 DCM[0]: DLL_DEAD_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 13 DCM[0]: DLL_DEAD_TIME bit 5	DCM[0]: DRP[18] bit 12 DCM[0]: DLL_DEAD_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 10 DCM[0]: DLL_DEAD_TIME bit 2	DCM[0]: DRP[18] bit 11 DCM[0]: DLL_DEAD_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 9 DCM[0]: DLL_DEAD_TIME bit 1	DCM[0]: DRP[18] bit 8 DCM[0]: DLL_DEAD_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 6 DCM[0]: DLL_LIVE_TIME bit 6	DCM[0]: DRP[18] bit 7 DCM[0]: DLL_LIVE_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 5 DCM[0]: DLL_LIVE_TIME bit 5	DCM[0]: DRP[18] bit 4 DCM[0]: DLL_LIVE_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 2 DCM[0]: DLL_LIVE_TIME bit 2	DCM[0]: DRP[18] bit 3 DCM[0]: DLL_LIVE_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[18] bit 1 DCM[0]: DLL_LIVE_TIME bit 1	DCM[0]: DRP[18] bit 0 DCM[0]: DLL_LIVE_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 14 DCM[0]: DLL_SETTLE_TIME bit 6	DCM[0]: DRP[17] bit 15 DCM[0]: DLL_SETTLE_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 13 DCM[0]: DLL_SETTLE_TIME bit 5	DCM[0]: DRP[17] bit 12 DCM[0]: DLL_SETTLE_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 10 DCM[0]: DLL_SETTLE_TIME bit 2	DCM[0]: DRP[17] bit 11 DCM[0]: DLL_SETTLE_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 9 DCM[0]: DLL_SETTLE_TIME bit 1	DCM[0]: DRP[17] bit 8 DCM[0]: DLL_SETTLE_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 6 DCM[0]: DLL_ZD1_EN	DCM[0]: DRP[17] bit 7 DCM[0]: PS_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 5 DCM[0]: DLL_ZD2_EN	DCM[0]: DRP[17] bit 4 DCM[0]: PS_MODE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 2 DCM[0]: DLL_FREQUENCY_MODE bit 0	DCM[0]: DRP[17] bit 3 DCM[0]: DLL_FREQUENCY_MODE bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[17] bit 1 DCM[0]: ! DLL_CLKIN_STOPPED_PWRD_EN_B	DCM[0]: DRP[17] bit 0 DCM[0]: ! DLL_CLKFB_STOPPED_PWRD_EN_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 14 DCM[0]: CLKFX_MULTIPLY bit 6	DCM[0]: DRP[16] bit 15 DCM[0]: CLKFX_MULTIPLY bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 13 DCM[0]: CLKFX_MULTIPLY bit 5	DCM[0]: DRP[16] bit 12 DCM[0]: CLKFX_MULTIPLY bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 10 DCM[0]: CLKFX_MULTIPLY bit 2	DCM[0]: DRP[16] bit 11 DCM[0]: CLKFX_MULTIPLY bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 9 DCM[0]: CLKFX_MULTIPLY bit 1	DCM[0]: DRP[16] bit 8 DCM[0]: CLKFX_MULTIPLY bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 6 DCM[0]: CLKFX_DIVIDE bit 6	DCM[0]: DRP[16] bit 7 DCM[0]: CLKFX_DIVIDE bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 5 DCM[0]: CLKFX_DIVIDE bit 5	DCM[0]: DRP[16] bit 4 DCM[0]: CLKFX_DIVIDE bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 2 DCM[0]: CLKFX_DIVIDE bit 2	DCM[0]: DRP[16] bit 3 DCM[0]: CLKFX_DIVIDE bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[0]: DRP[16] bit 1 DCM[0]: CLKFX_DIVIDE bit 1	DCM[0]: DRP[16] bit 0 DCM[0]: CLKFX_DIVIDE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 14 PLL[0]: PLL_IN_DLY_MX_SEL bit 4	PLL[0]: DRP[7] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 13 PLL[0]: PLL_IN_DLY_MX_SEL bit 3	PLL[0]: DRP[7] bit 12 PLL[0]: PLL_IN_DLY_MX_SEL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 10 PLL[0]: PLL_IN_DLY_MX_SEL bit 0	PLL[0]: DRP[7] bit 11 PLL[0]: PLL_IN_DLY_MX_SEL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 9 PLL[0]: PLL_EN_DLY	PLL[0]: DRP[7] bit 8 PLL[0]: PLL_IN_DLY_SET bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 6 PLL[0]: PLL_IN_DLY_SET bit 6	PLL[0]: DRP[7] bit 7 PLL[0]: PLL_IN_DLY_SET bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 5 PLL[0]: PLL_IN_DLY_SET bit 5	PLL[0]: DRP[7] bit 4 PLL[0]: PLL_IN_DLY_SET bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 2 PLL[0]: PLL_IN_DLY_SET bit 2	PLL[0]: DRP[7] bit 3 PLL[0]: PLL_IN_DLY_SET bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[7] bit 1 PLL[0]: PLL_IN_DLY_SET bit 1	PLL[0]: DRP[7] bit 0 PLL[0]: PLL_IN_DLY_SET bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 14	PLL[0]: DRP[6] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 13 PLL[0]: PLL_DIVCLK_EDGE	PLL[0]: DRP[6] bit 12 PLL[0]: PLL_DIVCLK_NOCOUNT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 10 PLL[0]: PLL_DIVCLK_HT bit 4	PLL[0]: DRP[6] bit 11 PLL[0]: PLL_DIVCLK_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 9 PLL[0]: PLL_DIVCLK_HT bit 3	PLL[0]: DRP[6] bit 8 PLL[0]: PLL_DIVCLK_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 6 PLL[0]: PLL_DIVCLK_HT bit 0	PLL[0]: DRP[6] bit 7 PLL[0]: PLL_DIVCLK_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 5 PLL[0]: PLL_DIVCLK_LT bit 5	PLL[0]: DRP[6] bit 4 PLL[0]: PLL_DIVCLK_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 2 PLL[0]: PLL_DIVCLK_LT bit 2	PLL[0]: DRP[6] bit 3 PLL[0]: PLL_DIVCLK_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[6] bit 1 PLL[0]: PLL_DIVCLK_LT bit 1	PLL[0]: DRP[6] bit 0 PLL[0]: PLL_DIVCLK_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 14 PLL[0]: PLL_EN_CNTRL bit 14	PLL[0]: DRP[5] bit 15 PLL[0]: PLL_EN_CNTRL bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 13 PLL[0]: PLL_EN_CNTRL bit 13	PLL[0]: DRP[5] bit 12 PLL[0]: PLL_EN_CNTRL bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 10 PLL[0]: PLL_EN_CNTRL bit 10	PLL[0]: DRP[5] bit 11 PLL[0]: PLL_EN_CNTRL bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 9 PLL[0]: PLL_EN_CNTRL bit 9	PLL[0]: DRP[5] bit 8 PLL[0]: PLL_EN_CNTRL bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 6 PLL[0]: PLL_EN_CNTRL bit 6	PLL[0]: DRP[5] bit 7 PLL[0]: PLL_EN_CNTRL bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 5 PLL[0]: PLL_EN_CNTRL bit 5	PLL[0]: DRP[5] bit 4 PLL[0]: PLL_EN_CNTRL bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 2 PLL[0]: PLL_EN_CNTRL bit 2	PLL[0]: DRP[5] bit 3 PLL[0]: PLL_EN_CNTRL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[5] bit 1 PLL[0]: PLL_EN_CNTRL bit 1	PLL[0]: DRP[5] bit 0 PLL[0]: PLL_EN_CNTRL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 14 PLL[0]: PLL_EN_TCLK4	PLL[0]: DRP[4] bit 15 PLL[0]: ! PLL_TCK4_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 13 PLL[0]: PLL_EN_TCLK3	PLL[0]: DRP[4] bit 12 PLL[0]: PLL_EN_TCLK2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 10 PLL[0]: PLL_EN_TCLK0	PLL[0]: DRP[4] bit 11 PLL[0]: PLL_EN_TCLK1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 9 PLL[0]: PLL_INTFB bit 1	PLL[0]: DRP[4] bit 8 PLL[0]: PLL_INTFB bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 6 PLL[0]: PLL_FLOCK bit 4	PLL[0]: DRP[4] bit 7 PLL[0]: PLL_FLOCK bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 5 PLL[0]: PLL_FLOCK bit 3	PLL[0]: DRP[4] bit 4 PLL[0]: PLL_FLOCK bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 2 PLL[0]: PLL_FLOCK bit 0	PLL[0]: DRP[4] bit 3 PLL[0]: PLL_FLOCK bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[4] bit 1 PLL[0]: PLL_UNLOCK_CNT_RST_FAST	PLL[0]: DRP[4] bit 0 PLL[0]: PLL_LOCK_CNT_RST_FAST	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 14 PLL[0]: PLL_UNLOCK_CNT bit 2	PLL[0]: DRP[3] bit 15 PLL[0]: PLL_UNLOCK_CNT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 13 PLL[0]: PLL_UNLOCK_CNT bit 1	PLL[0]: DRP[3] bit 12 PLL[0]: PLL_UNLOCK_CNT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 10 PLL[0]: PLL_INC_SLOCK	PLL[0]: DRP[3] bit 11 PLL[0]: PLL_INC_FLOCK	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 9 PLL[0]: PLL_LOCK_FB_P2 bit 4	PLL[0]: DRP[3] bit 8 PLL[0]: PLL_LOCK_FB_P2 bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 6 PLL[0]: PLL_LOCK_FB_P2 bit 1	PLL[0]: DRP[3] bit 7 PLL[0]: PLL_LOCK_FB_P2 bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 5 PLL[0]: PLL_LOCK_FB_P2 bit 0	PLL[0]: DRP[3] bit 4 PLL[0]: PLL_LOCK_FB_P1 bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 2 PLL[0]: PLL_LOCK_FB_P1 bit 2	PLL[0]: DRP[3] bit 3 PLL[0]: PLL_LOCK_FB_P1 bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[3] bit 1 PLL[0]: PLL_LOCK_FB_P1 bit 1	PLL[0]: DRP[3] bit 0 PLL[0]: PLL_LOCK_FB_P1 bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 14 PLL[0]: PLL_LOCK_REF_P2 bit 3	PLL[0]: DRP[2] bit 15 PLL[0]: PLL_LOCK_REF_P2 bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 13 PLL[0]: PLL_LOCK_REF_P2 bit 2	PLL[0]: DRP[2] bit 12 PLL[0]: PLL_LOCK_REF_P2 bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 10 PLL[0]: PLL_LOCK_REF_P1 bit 4	PLL[0]: DRP[2] bit 11 PLL[0]: PLL_LOCK_REF_P2 bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 9 PLL[0]: PLL_LOCK_REF_P1 bit 3	PLL[0]: DRP[2] bit 8 PLL[0]: PLL_LOCK_REF_P1 bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 6 PLL[0]: PLL_LOCK_REF_P1 bit 0	PLL[0]: DRP[2] bit 7 PLL[0]: PLL_LOCK_REF_P1 bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 5 PLL[0]: PLL_LOCK_CNT bit 5	PLL[0]: DRP[2] bit 4 PLL[0]: PLL_LOCK_CNT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 2 PLL[0]: PLL_LOCK_CNT bit 2	PLL[0]: DRP[2] bit 3 PLL[0]: PLL_LOCK_CNT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[2] bit 1 PLL[0]: PLL_LOCK_CNT bit 1	PLL[0]: DRP[2] bit 0 PLL[0]: PLL_LOCK_CNT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 14	PLL[0]: DRP[1] bit 15 PLL[0]: PLL_PWRD_CFG	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 13 PLL[0]: PLL_PFD_CNTRL bit 3	PLL[0]: DRP[1] bit 12 PLL[0]: PLL_PFD_CNTRL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 10 PLL[0]: PLL_PFD_CNTRL bit 0	PLL[0]: DRP[1] bit 11 PLL[0]: PLL_PFD_CNTRL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 9 PLL[0]: PLL_PFD_DLY bit 1	PLL[0]: DRP[1] bit 8 PLL[0]: PLL_PFD_DLY bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 6 PLL[0]: PLL_LFHF bit 0	PLL[0]: DRP[1] bit 7 PLL[0]: PLL_LFHF bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 5 PLL[0]: PLL_CP_RES bit 1	PLL[0]: DRP[1] bit 4 PLL[0]: PLL_CP_RES bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 2 PLL[0]: PLL_CP bit 2	PLL[0]: DRP[1] bit 3 PLL[0]: PLL_CP bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[1] bit 1 PLL[0]: PLL_CP bit 1	PLL[0]: DRP[1] bit 0 PLL[0]: PLL_CP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 14 PLL[0]: PLL_CP_BIAS_TRIP_SHIFT	PLL[0]: DRP[0] bit 15 PLL[0]: PLL_SEL_SLIPD	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 13 PLL[0]: PLL_MISC bit 3	PLL[0]: DRP[0] bit 12 PLL[0]: PLL_MISC bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 10 PLL[0]: PLL_MISC bit 0	PLL[0]: DRP[0] bit 11 PLL[0]: PLL_MISC bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 9 PLL[0]: PLL_RES bit 3	PLL[0]: DRP[0] bit 8 PLL[0]: PLL_RES bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 6 PLL[0]: PLL_RES bit 0	PLL[0]: DRP[0] bit 7 PLL[0]: PLL_RES bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 5 PLL[0]: PLL_VLFHIGH_DIS	PLL[0]: DRP[0] bit 4 PLL[0]: PLL_LF_NEN bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 2 PLL[0]: PLL_LF_PEN bit 1	PLL[0]: DRP[0] bit 3 PLL[0]: PLL_LF_NEN bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[0] bit 1 PLL[0]: PLL_LF_PEN bit 0	PLL[0]: DRP[0] bit 0 PLL[0]: PLL_MAN_LF_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 14 PLL[0]: CLKOUT5_DESKEW_ADJUST bit 3	PLL[0]: DRP[15] bit 15 PLL[0]: CLKOUT5_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 13 PLL[0]: CLKOUT5_DESKEW_ADJUST bit 2	PLL[0]: DRP[15] bit 12 PLL[0]: CLKOUT5_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 10	PLL[0]: DRP[15] bit 11 PLL[0]: CLKOUT5_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 9 PLL[0]: PLL_CLK5MX bit 1	PLL[0]: DRP[15] bit 8 PLL[0]: PLL_CLK5MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 6 PLL[0]: PLL_CLKOUT5_NOCOUNT	PLL[0]: DRP[15] bit 7 PLL[0]: PLL_CLKOUT5_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 5 PLL[0]: PLL_CLKOUT5_DT bit 5	PLL[0]: DRP[15] bit 4 PLL[0]: PLL_CLKOUT5_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 2 PLL[0]: PLL_CLKOUT5_DT bit 2	PLL[0]: DRP[15] bit 3 PLL[0]: PLL_CLKOUT5_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[15] bit 1 PLL[0]: PLL_CLKOUT5_DT bit 1	PLL[0]: DRP[15] bit 0 PLL[0]: PLL_CLKOUT5_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 14 PLL[0]: PLL_CLKOUT5_PM bit 1	PLL[0]: DRP[14] bit 15 PLL[0]: PLL_CLKOUT5_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 13 PLL[0]: PLL_CLKOUT5_PM bit 0	PLL[0]: DRP[14] bit 12 PLL[0]: PLL_CLKOUT5_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 10 PLL[0]: PLL_CLKOUT5_HT bit 4	PLL[0]: DRP[14] bit 11 PLL[0]: PLL_CLKOUT5_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 9 PLL[0]: PLL_CLKOUT5_HT bit 3	PLL[0]: DRP[14] bit 8 PLL[0]: PLL_CLKOUT5_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 6 PLL[0]: PLL_CLKOUT5_HT bit 0	PLL[0]: DRP[14] bit 7 PLL[0]: PLL_CLKOUT5_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 5 PLL[0]: PLL_CLKOUT5_LT bit 5	PLL[0]: DRP[14] bit 4 PLL[0]: PLL_CLKOUT5_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 2 PLL[0]: PLL_CLKOUT5_LT bit 2	PLL[0]: DRP[14] bit 3 PLL[0]: PLL_CLKOUT5_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[14] bit 1 PLL[0]: PLL_CLKOUT5_LT bit 1	PLL[0]: DRP[14] bit 0 PLL[0]: PLL_CLKOUT5_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 14 PLL[0]: CLKFBOUT_DESKEW_ADJUST bit 3	PLL[0]: DRP[13] bit 15 PLL[0]: CLKFBOUT_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 13 PLL[0]: CLKFBOUT_DESKEW_ADJUST bit 2	PLL[0]: DRP[13] bit 12 PLL[0]: CLKFBOUT_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 10 PLL[0]: PLL_NBTI_EN	PLL[0]: DRP[13] bit 11 PLL[0]: CLKFBOUT_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 9 PLL[0]: PLL_CLKFBMX bit 1	PLL[0]: DRP[13] bit 8 PLL[0]: PLL_CLKFBMX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 6 PLL[0]: PLL_CLKFBOUT_NOCOUNT	PLL[0]: DRP[13] bit 7 PLL[0]: PLL_CLKFBOUT_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 5 PLL[0]: PLL_CLKFBOUT_DT bit 5	PLL[0]: DRP[13] bit 4 PLL[0]: PLL_CLKFBOUT_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 2 PLL[0]: PLL_CLKFBOUT_DT bit 2	PLL[0]: DRP[13] bit 3 PLL[0]: PLL_CLKFBOUT_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[13] bit 1 PLL[0]: PLL_CLKFBOUT_DT bit 1	PLL[0]: DRP[13] bit 0 PLL[0]: PLL_CLKFBOUT_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 14 PLL[0]: PLL_CLKFBOUT_PM bit 1	PLL[0]: DRP[12] bit 15 PLL[0]: PLL_CLKFBOUT_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 13 PLL[0]: PLL_CLKFBOUT_PM bit 0	PLL[0]: DRP[12] bit 12 PLL[0]: PLL_CLKFBOUT_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 10 PLL[0]: PLL_CLKFBOUT_HT bit 4	PLL[0]: DRP[12] bit 11 PLL[0]: PLL_CLKFBOUT_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 9 PLL[0]: PLL_CLKFBOUT_HT bit 3	PLL[0]: DRP[12] bit 8 PLL[0]: PLL_CLKFBOUT_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 6 PLL[0]: PLL_CLKFBOUT_HT bit 0	PLL[0]: DRP[12] bit 7 PLL[0]: PLL_CLKFBOUT_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 5 PLL[0]: PLL_CLKFBOUT_LT bit 5	PLL[0]: DRP[12] bit 4 PLL[0]: PLL_CLKFBOUT_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 2 PLL[0]: PLL_CLKFBOUT_LT bit 2	PLL[0]: DRP[12] bit 3 PLL[0]: PLL_CLKFBOUT_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[12] bit 1 PLL[0]: PLL_CLKFBOUT_LT bit 1	PLL[0]: DRP[12] bit 0 PLL[0]: PLL_CLKFBOUT_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 14 PLL[0]: PLL_EN_CNTRL bit 46	PLL[0]: DRP[11] bit 15 PLL[0]: PLL_EN_CNTRL bit 47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 13 PLL[0]: PLL_EN_CNTRL bit 45	PLL[0]: DRP[11] bit 12 PLL[0]: PLL_EN_CNTRL bit 44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 10 PLL[0]: PLL_EN_CNTRL bit 42	PLL[0]: DRP[11] bit 11 PLL[0]: PLL_EN_CNTRL bit 43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 9 PLL[0]: PLL_EN_CNTRL bit 41	PLL[0]: DRP[11] bit 8 PLL[0]: PLL_EN_CNTRL bit 40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 6 PLL[0]: PLL_EN_CNTRL bit 38	PLL[0]: DRP[11] bit 7 PLL[0]: PLL_EN_CNTRL bit 39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 5 PLL[0]: PLL_EN_CNTRL bit 37	PLL[0]: DRP[11] bit 4 PLL[0]: PLL_EN_CNTRL bit 36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 2 PLL[0]: PLL_EN_CNTRL bit 34	PLL[0]: DRP[11] bit 3 PLL[0]: PLL_EN_CNTRL bit 35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[11] bit 1 PLL[0]: PLL_EN_CNTRL bit 33	PLL[0]: DRP[11] bit 0 PLL[0]: PLL_EN_CNTRL bit 32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 14 PLL[0]: PLL_DIVCLK_DT bit 4	PLL[0]: DRP[10] bit 15 PLL[0]: PLL_DIVCLK_DT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 13 PLL[0]: PLL_DIVCLK_DT bit 3	PLL[0]: DRP[10] bit 12 PLL[0]: PLL_DIVCLK_DT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 10 PLL[0]: PLL_DIVCLK_DT bit 0	PLL[0]: DRP[10] bit 11 PLL[0]: PLL_DIVCLK_DT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 9	PLL[0]: DRP[10] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 6 PLL[0]: PLL_CLKFBOUT2_NOCOUNT	PLL[0]: DRP[10] bit 7 PLL[0]: PLL_CLKFBOUT2_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 5 PLL[0]: PLL_CLKFBOUT2_DT bit 5	PLL[0]: DRP[10] bit 4 PLL[0]: PLL_CLKFBOUT2_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 2 PLL[0]: PLL_CLKFBOUT2_DT bit 2	PLL[0]: DRP[10] bit 3 PLL[0]: PLL_CLKFBOUT2_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[10] bit 1 PLL[0]: PLL_CLKFBOUT2_DT bit 1	PLL[0]: DRP[10] bit 0 PLL[0]: PLL_CLKFBOUT2_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 14	PLL[0]: DRP[9] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 13	PLL[0]: DRP[9] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 10 PLL[0]: PLL_CLKFBOUT2_HT bit 4	PLL[0]: DRP[9] bit 11 PLL[0]: PLL_CLKFBOUT2_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 9 PLL[0]: PLL_CLKFBOUT2_HT bit 3	PLL[0]: DRP[9] bit 8 PLL[0]: PLL_CLKFBOUT2_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 6 PLL[0]: PLL_CLKFBOUT2_HT bit 0	PLL[0]: DRP[9] bit 7 PLL[0]: PLL_CLKFBOUT2_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 5 PLL[0]: PLL_CLKFBOUT2_LT bit 5	PLL[0]: DRP[9] bit 4 PLL[0]: PLL_CLKFBOUT2_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 2 PLL[0]: PLL_CLKFBOUT2_LT bit 2	PLL[0]: DRP[9] bit 3 PLL[0]: PLL_CLKFBOUT2_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[9] bit 1 PLL[0]: PLL_CLKFBOUT2_LT bit 1	PLL[0]: DRP[9] bit 0 PLL[0]: PLL_CLKFBOUT2_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 14 PLL[0]: PLL_EN_CNTRL bit 30	PLL[0]: DRP[8] bit 15 PLL[0]: PLL_EN_CNTRL bit 31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 13 PLL[0]: PLL_EN_CNTRL bit 29	PLL[0]: DRP[8] bit 12 PLL[0]: PLL_EN_CNTRL bit 28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 10 PLL[0]: PLL_EN_CNTRL bit 26	PLL[0]: DRP[8] bit 11 PLL[0]: PLL_EN_CNTRL bit 27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 9 PLL[0]: PLL_EN_CNTRL bit 25	PLL[0]: DRP[8] bit 8 PLL[0]: PLL_EN_CNTRL bit 24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 6 PLL[0]: PLL_EN_CNTRL bit 22	PLL[0]: DRP[8] bit 7 PLL[0]: PLL_EN_CNTRL bit 23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 5 PLL[0]: PLL_EN_CNTRL bit 21	PLL[0]: DRP[8] bit 4 PLL[0]: PLL_EN_CNTRL bit 20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 2 PLL[0]: PLL_EN_CNTRL bit 18	PLL[0]: DRP[8] bit 3 PLL[0]: PLL_EN_CNTRL bit 19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[8] bit 1 PLL[0]: PLL_EN_CNTRL bit 17	PLL[0]: DRP[8] bit 0 PLL[0]: PLL_EN_CNTRL bit 16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 14 PLL[0]: CLKOUT2_DESKEW_ADJUST bit 3	PLL[0]: DRP[23] bit 15 PLL[0]: CLKOUT2_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 13 PLL[0]: CLKOUT2_DESKEW_ADJUST bit 2	PLL[0]: DRP[23] bit 12 PLL[0]: CLKOUT2_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 10	PLL[0]: DRP[23] bit 11 PLL[0]: CLKOUT2_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 9 PLL[0]: PLL_CLK2MX bit 1	PLL[0]: DRP[23] bit 8 PLL[0]: PLL_CLK2MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 6 PLL[0]: PLL_CLKOUT2_NOCOUNT	PLL[0]: DRP[23] bit 7 PLL[0]: PLL_CLKOUT2_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 5 PLL[0]: PLL_CLKOUT2_DT bit 5	PLL[0]: DRP[23] bit 4 PLL[0]: PLL_CLKOUT2_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 2 PLL[0]: PLL_CLKOUT2_DT bit 2	PLL[0]: DRP[23] bit 3 PLL[0]: PLL_CLKOUT2_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[23] bit 1 PLL[0]: PLL_CLKOUT2_DT bit 1	PLL[0]: DRP[23] bit 0 PLL[0]: PLL_CLKOUT2_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 14 PLL[0]: PLL_CLKOUT2_PM bit 1	PLL[0]: DRP[22] bit 15 PLL[0]: PLL_CLKOUT2_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 13 PLL[0]: PLL_CLKOUT2_PM bit 0	PLL[0]: DRP[22] bit 12 PLL[0]: PLL_CLKOUT2_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 10 PLL[0]: PLL_CLKOUT2_HT bit 4	PLL[0]: DRP[22] bit 11 PLL[0]: PLL_CLKOUT2_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 9 PLL[0]: PLL_CLKOUT2_HT bit 3	PLL[0]: DRP[22] bit 8 PLL[0]: PLL_CLKOUT2_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 6 PLL[0]: PLL_CLKOUT2_HT bit 0	PLL[0]: DRP[22] bit 7 PLL[0]: PLL_CLKOUT2_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 5 PLL[0]: PLL_CLKOUT2_LT bit 5	PLL[0]: DRP[22] bit 4 PLL[0]: PLL_CLKOUT2_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 2 PLL[0]: PLL_CLKOUT2_LT bit 2	PLL[0]: DRP[22] bit 3 PLL[0]: PLL_CLKOUT2_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[22] bit 1 PLL[0]: PLL_CLKOUT2_LT bit 1	PLL[0]: DRP[22] bit 0 PLL[0]: PLL_CLKOUT2_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 14 PLL[0]: CLKOUT3_DESKEW_ADJUST bit 3	PLL[0]: DRP[21] bit 15 PLL[0]: CLKOUT3_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 13 PLL[0]: CLKOUT3_DESKEW_ADJUST bit 2	PLL[0]: DRP[21] bit 12 PLL[0]: CLKOUT3_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 10	PLL[0]: DRP[21] bit 11 PLL[0]: CLKOUT3_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 9 PLL[0]: PLL_CLK3MX bit 1	PLL[0]: DRP[21] bit 8 PLL[0]: PLL_CLK3MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 6 PLL[0]: PLL_CLKOUT3_NOCOUNT	PLL[0]: DRP[21] bit 7 PLL[0]: PLL_CLKOUT3_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 5 PLL[0]: PLL_CLKOUT3_DT bit 5	PLL[0]: DRP[21] bit 4 PLL[0]: PLL_CLKOUT3_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 2 PLL[0]: PLL_CLKOUT3_DT bit 2	PLL[0]: DRP[21] bit 3 PLL[0]: PLL_CLKOUT3_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[21] bit 1 PLL[0]: PLL_CLKOUT3_DT bit 1	PLL[0]: DRP[21] bit 0 PLL[0]: PLL_CLKOUT3_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 14 PLL[0]: PLL_CLKOUT3_PM bit 1	PLL[0]: DRP[20] bit 15 PLL[0]: PLL_CLKOUT3_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 13 PLL[0]: PLL_CLKOUT3_PM bit 0	PLL[0]: DRP[20] bit 12 PLL[0]: PLL_CLKOUT3_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 10 PLL[0]: PLL_CLKOUT3_HT bit 4	PLL[0]: DRP[20] bit 11 PLL[0]: PLL_CLKOUT3_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 9 PLL[0]: PLL_CLKOUT3_HT bit 3	PLL[0]: DRP[20] bit 8 PLL[0]: PLL_CLKOUT3_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 6 PLL[0]: PLL_CLKOUT3_HT bit 0	PLL[0]: DRP[20] bit 7 PLL[0]: PLL_CLKOUT3_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 5 PLL[0]: PLL_CLKOUT3_LT bit 5	PLL[0]: DRP[20] bit 4 PLL[0]: PLL_CLKOUT3_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 2 PLL[0]: PLL_CLKOUT3_LT bit 2	PLL[0]: DRP[20] bit 3 PLL[0]: PLL_CLKOUT3_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[20] bit 1 PLL[0]: PLL_CLKOUT3_LT bit 1	PLL[0]: DRP[20] bit 0 PLL[0]: PLL_CLKOUT3_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 14 PLL[0]: CLKOUT4_DESKEW_ADJUST bit 3	PLL[0]: DRP[19] bit 15 PLL[0]: CLKOUT4_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 13 PLL[0]: CLKOUT4_DESKEW_ADJUST bit 2	PLL[0]: DRP[19] bit 12 PLL[0]: CLKOUT4_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 10	PLL[0]: DRP[19] bit 11 PLL[0]: CLKOUT4_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 9 PLL[0]: PLL_CLK4MX bit 1	PLL[0]: DRP[19] bit 8 PLL[0]: PLL_CLK4MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 6 PLL[0]: PLL_CLKOUT4_NOCOUNT	PLL[0]: DRP[19] bit 7 PLL[0]: PLL_CLKOUT4_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 5 PLL[0]: PLL_CLKOUT4_DT bit 5	PLL[0]: DRP[19] bit 4 PLL[0]: PLL_CLKOUT4_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 2 PLL[0]: PLL_CLKOUT4_DT bit 2	PLL[0]: DRP[19] bit 3 PLL[0]: PLL_CLKOUT4_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[19] bit 1 PLL[0]: PLL_CLKOUT4_DT bit 1	PLL[0]: DRP[19] bit 0 PLL[0]: PLL_CLKOUT4_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 14 PLL[0]: PLL_CLKOUT4_PM bit 1	PLL[0]: DRP[18] bit 15 PLL[0]: PLL_CLKOUT4_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 13 PLL[0]: PLL_CLKOUT4_PM bit 0	PLL[0]: DRP[18] bit 12 PLL[0]: PLL_CLKOUT4_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 10 PLL[0]: PLL_CLKOUT4_HT bit 4	PLL[0]: DRP[18] bit 11 PLL[0]: PLL_CLKOUT4_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 9 PLL[0]: PLL_CLKOUT4_HT bit 3	PLL[0]: DRP[18] bit 8 PLL[0]: PLL_CLKOUT4_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 6 PLL[0]: PLL_CLKOUT4_HT bit 0	PLL[0]: DRP[18] bit 7 PLL[0]: PLL_CLKOUT4_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 5 PLL[0]: PLL_CLKOUT4_LT bit 5	PLL[0]: DRP[18] bit 4 PLL[0]: PLL_CLKOUT4_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 2 PLL[0]: PLL_CLKOUT4_LT bit 2	PLL[0]: DRP[18] bit 3 PLL[0]: PLL_CLKOUT4_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[18] bit 1 PLL[0]: PLL_CLKOUT4_LT bit 1	PLL[0]: DRP[18] bit 0 PLL[0]: PLL_CLKOUT4_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 14 PLL[0]: PLL_PMCD_MODE	PLL[0]: DRP[17] bit 15 PLL[0]: PLL_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 13 PLL[0]: PLL_EN_CNTRL bit 77	PLL[0]: DRP[17] bit 12 PLL[0]: PLL_EN_CNTRL bit 76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 10 PLL[0]: PLL_EN_CNTRL bit 74	PLL[0]: DRP[17] bit 11 PLL[0]: PLL_EN_CNTRL bit 75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 9 PLL[0]: PLL_EN_CNTRL bit 73	PLL[0]: DRP[17] bit 8 PLL[0]: PLL_EN_CNTRL bit 72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 6 PLL[0]: PLL_EN_CNTRL bit 70	PLL[0]: DRP[17] bit 7 PLL[0]: PLL_EN_CNTRL bit 71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 5 PLL[0]: PLL_EN_CNTRL bit 69	PLL[0]: DRP[17] bit 4 PLL[0]: PLL_EN_CNTRL bit 68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 2 PLL[0]: PLL_EN_CNTRL bit 66	PLL[0]: DRP[17] bit 3 PLL[0]: PLL_EN_CNTRL bit 67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[17] bit 1 PLL[0]: PLL_EN_CNTRL bit 65	PLL[0]: DRP[17] bit 0 PLL[0]: PLL_EN_CNTRL bit 64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 14 PLL[0]: PLL_EN_CNTRL bit 62	PLL[0]: DRP[16] bit 15 PLL[0]: PLL_EN_CNTRL bit 63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 13 PLL[0]: PLL_EN_CNTRL bit 61	PLL[0]: DRP[16] bit 12 PLL[0]: PLL_EN_CNTRL bit 60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 10 PLL[0]: PLL_EN_CNTRL bit 58	PLL[0]: DRP[16] bit 11 PLL[0]: PLL_EN_CNTRL bit 59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 9 PLL[0]: PLL_EN_CNTRL bit 57	PLL[0]: DRP[16] bit 8 PLL[0]: PLL_EN_CNTRL bit 56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 6 PLL[0]: PLL_EN_CNTRL bit 54	PLL[0]: DRP[16] bit 7 PLL[0]: PLL_EN_CNTRL bit 55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 5 PLL[0]: PLL_EN_CNTRL bit 53	PLL[0]: DRP[16] bit 4 PLL[0]: PLL_EN_CNTRL bit 52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 2 PLL[0]: PLL_EN_CNTRL bit 50	PLL[0]: DRP[16] bit 3 PLL[0]: PLL_EN_CNTRL bit 51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[16] bit 1 PLL[0]: PLL_EN_CNTRL bit 49	PLL[0]: DRP[16] bit 0 PLL[0]: PLL_EN_CNTRL bit 48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 14 PLL[0]: PLL_AVDD_COMP_SET bit 0	PLL[0]: DRP[31] bit 15 PLL[0]: PLL_AVDD_COMP_SET bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 13 PLL[0]: PLL_AVDD_VBG_PD bit 1	PLL[0]: DRP[31] bit 12 PLL[0]: PLL_AVDD_VBG_PD bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 10 PLL[0]: PLL_AVDD_VBG_SEL bit 2	PLL[0]: DRP[31] bit 11 PLL[0]: PLL_AVDD_VBG_SEL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 9 PLL[0]: PLL_AVDD_VBG_SEL bit 1	PLL[0]: DRP[31] bit 8 PLL[0]: PLL_AVDD_VBG_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 6 PLL[0]: PLL_DVDD_COMP_SET bit 0	PLL[0]: DRP[31] bit 7 PLL[0]: PLL_DVDD_COMP_SET bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 5 PLL[0]: PLL_DVDD_VBG_PD bit 1	PLL[0]: DRP[31] bit 4 PLL[0]: PLL_DVDD_VBG_PD bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 2 PLL[0]: PLL_DVDD_VBG_SEL bit 2	PLL[0]: DRP[31] bit 3 PLL[0]: PLL_DVDD_VBG_SEL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[31] bit 1 PLL[0]: PLL_DVDD_VBG_SEL bit 1	PLL[0]: DRP[31] bit 0 PLL[0]: PLL_DVDD_VBG_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN2 bit 2 PLL[0]: DRP[30] bit 14	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN2 bit 1 PLL[0]: DRP[30] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN2 bit 0 PLL[0]: DRP[30] bit 13	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN1 bit 2 PLL[0]: DRP[30] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN1 bit 1 PLL[0]: DRP[30] bit 10	SPEC_INT: mux CELL[0].OMUX_PLL_SKEWCLKIN1 bit 0 PLL[0]: DRP[30] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_PLL_CLKFB bit 3 PLL[0]: DRP[30] bit 9	SPEC_INT: mux CELL[0].IMUX_PLL_CLKFB bit 4 PLL[0]: DRP[30] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_PLL_CLKFB bit 2 PLL[0]: DRP[30] bit 6	SPEC_INT: mux CELL[0].IMUX_PLL_CLKFB bit 1 PLL[0]: DRP[30] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_PLL_CLKFB bit 0 PLL[0]: DRP[30] bit 5	PLL[0]: DRP[30] bit 4 PLL[0]: CLKINSEL_STATIC_VAL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: pair mux (CELL[0].IMUX_PLL_CLKIN1, CELL[0].IMUX_PLL_CLKIN2) bit 3 PLL[0]: DRP[30] bit 2	SPEC_INT: pair mux (CELL[0].IMUX_PLL_CLKIN1, CELL[0].IMUX_PLL_CLKIN2) bit 2 PLL[0]: DRP[30] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: pair mux (CELL[0].IMUX_PLL_CLKIN1, CELL[0].IMUX_PLL_CLKIN2) bit 0 PLL[0]: DRP[30] bit 1	SPEC_INT: pair mux (CELL[0].IMUX_PLL_CLKIN1, CELL[0].IMUX_PLL_CLKIN2) bit 1 PLL[0]: DRP[30] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: invert SKEWSTB PLL[0]: DRP[29] bit 14	PLL[0]: invert SKEWRST PLL[0]: DRP[29] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: invert SKEWCLKIN2 PLL[0]: DRP[29] bit 13	PLL[0]: invert SKEWCLKIN1 PLL[0]: DRP[29] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OUT_CMT[10] bit 2 PLL[0]: DRP[29] bit 10	SPEC_INT: mux CELL[0].OUT_CMT[10] bit 1 PLL[0]: DRP[29] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OUT_CMT[10] bit 0 PLL[0]: DRP[29] bit 9	PLL[0]: !invert CLKINSEL PLL[0]: DRP[29] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[29] bit 6 PLL[0]: ! PLL_CLKCNTRL bit 0	PLL[0]: DRP[29] bit 7 PLL[0]: CLKINSEL_MODE_DYNAMIC	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: invert ENOUTSYNC PLL[0]: DRP[29] bit 5	PLL[0]: invert CLKBRST PLL[0]: DRP[29] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: invert MANPULF PLL[0]: DRP[29] bit 2	PLL[0]: invert REL PLL[0]: DRP[29] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: invert MANPDLF PLL[0]: DRP[29] bit 1	PLL[0]: invert RST PLL[0]: DRP[29] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 14 PLL[0]: CLKOUT0_DESKEW_ADJUST bit 3	PLL[0]: DRP[28] bit 15 PLL[0]: CLKOUT0_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 13 PLL[0]: CLKOUT0_DESKEW_ADJUST bit 2	PLL[0]: DRP[28] bit 12 PLL[0]: CLKOUT0_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 10	PLL[0]: DRP[28] bit 11 PLL[0]: CLKOUT0_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 9 PLL[0]: PLL_CLK0MX bit 1	PLL[0]: DRP[28] bit 8 PLL[0]: PLL_CLK0MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 6 PLL[0]: PLL_CLKOUT0_NOCOUNT	PLL[0]: DRP[28] bit 7 PLL[0]: PLL_CLKOUT0_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 5 PLL[0]: PLL_CLKOUT0_DT bit 5	PLL[0]: DRP[28] bit 4 PLL[0]: PLL_CLKOUT0_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 2 PLL[0]: PLL_CLKOUT0_DT bit 2	PLL[0]: DRP[28] bit 3 PLL[0]: PLL_CLKOUT0_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[28] bit 1 PLL[0]: PLL_CLKOUT0_DT bit 1	PLL[0]: DRP[28] bit 0 PLL[0]: PLL_CLKOUT0_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 14 PLL[0]: PLL_CLKOUT0_PM bit 1	PLL[0]: DRP[27] bit 15 PLL[0]: PLL_CLKOUT0_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 13 PLL[0]: PLL_CLKOUT0_PM bit 0	PLL[0]: DRP[27] bit 12 PLL[0]: PLL_CLKOUT0_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 10 PLL[0]: PLL_CLKOUT0_HT bit 4	PLL[0]: DRP[27] bit 11 PLL[0]: PLL_CLKOUT0_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 9 PLL[0]: PLL_CLKOUT0_HT bit 3	PLL[0]: DRP[27] bit 8 PLL[0]: PLL_CLKOUT0_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 6 PLL[0]: PLL_CLKOUT0_HT bit 0	PLL[0]: DRP[27] bit 7 PLL[0]: PLL_CLKOUT0_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 5 PLL[0]: PLL_CLKOUT0_LT bit 5	PLL[0]: DRP[27] bit 4 PLL[0]: PLL_CLKOUT0_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 2 PLL[0]: PLL_CLKOUT0_LT bit 2	PLL[0]: DRP[27] bit 3 PLL[0]: PLL_CLKOUT0_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[27] bit 1 PLL[0]: PLL_CLKOUT0_LT bit 1	PLL[0]: DRP[27] bit 0 PLL[0]: PLL_CLKOUT0_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 14 PLL[0]: CLKOUT1_DESKEW_ADJUST bit 3	PLL[0]: DRP[26] bit 15 PLL[0]: CLKOUT1_DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 13 PLL[0]: CLKOUT1_DESKEW_ADJUST bit 2	PLL[0]: DRP[26] bit 12 PLL[0]: CLKOUT1_DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 10	PLL[0]: DRP[26] bit 11 PLL[0]: CLKOUT1_DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 9 PLL[0]: PLL_CLK1MX bit 1	PLL[0]: DRP[26] bit 8 PLL[0]: PLL_CLK1MX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 6 PLL[0]: PLL_CLKOUT1_NOCOUNT	PLL[0]: DRP[26] bit 7 PLL[0]: PLL_CLKOUT1_EDGE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 5 PLL[0]: PLL_CLKOUT1_DT bit 5	PLL[0]: DRP[26] bit 4 PLL[0]: PLL_CLKOUT1_DT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 2 PLL[0]: PLL_CLKOUT1_DT bit 2	PLL[0]: DRP[26] bit 3 PLL[0]: PLL_CLKOUT1_DT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[26] bit 1 PLL[0]: PLL_CLKOUT1_DT bit 1	PLL[0]: DRP[26] bit 0 PLL[0]: PLL_CLKOUT1_DT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 14 PLL[0]: PLL_CLKOUT1_PM bit 1	PLL[0]: DRP[25] bit 15 PLL[0]: PLL_CLKOUT1_PM bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 13 PLL[0]: PLL_CLKOUT1_PM bit 0	PLL[0]: DRP[25] bit 12 PLL[0]: PLL_CLKOUT1_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 10 PLL[0]: PLL_CLKOUT1_HT bit 4	PLL[0]: DRP[25] bit 11 PLL[0]: PLL_CLKOUT1_HT bit 5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 9 PLL[0]: PLL_CLKOUT1_HT bit 3	PLL[0]: DRP[25] bit 8 PLL[0]: PLL_CLKOUT1_HT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 6 PLL[0]: PLL_CLKOUT1_HT bit 0	PLL[0]: DRP[25] bit 7 PLL[0]: PLL_CLKOUT1_HT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 5 PLL[0]: PLL_CLKOUT1_LT bit 5	PLL[0]: DRP[25] bit 4 PLL[0]: PLL_CLKOUT1_LT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 2 PLL[0]: PLL_CLKOUT1_LT bit 2	PLL[0]: DRP[25] bit 3 PLL[0]: PLL_CLKOUT1_LT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[25] bit 1 PLL[0]: PLL_CLKOUT1_LT bit 1	PLL[0]: DRP[25] bit 0 PLL[0]: PLL_CLKOUT1_LT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 14 PLL[0]: PLL_CLKBURST_CNT bit 1	PLL[0]: DRP[24] bit 15 PLL[0]: PLL_CLKBURST_CNT bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 13 PLL[0]: PLL_CLKBURST_CNT bit 0	PLL[0]: DRP[24] bit 12 PLL[0]: PLL_CLKBURST_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 10 PLL[0]: PLL_EN_VCO7	PLL[0]: DRP[24] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 9 PLL[0]: PLL_EN_VCO6	PLL[0]: DRP[24] bit 8 PLL[0]: PLL_EN_VCO5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 6 PLL[0]: PLL_EN_VCO3	PLL[0]: DRP[24] bit 7 PLL[0]: PLL_EN_VCO4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 5 PLL[0]: PLL_EN_VCO2	PLL[0]: DRP[24] bit 4 PLL[0]: PLL_EN_VCO1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 2 PLL[0]: PLL_EN_VCO_DIV6	PLL[0]: DRP[24] bit 3 PLL[0]: PLL_EN_VCO0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL[0]: DRP[24] bit 1 PLL[0]: PLL_EN_VCO_DIV1	PLL[0]: DRP[24] bit 0 PLL[0]: PLL_DIRECT_PATH_CNTRL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 14 DCM[1]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 1	DCM[1]: DRP[7] bit 15 DCM[1]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 13 DCM[1]: DFS_AVE_FREQ_SAMPLE_INTERVAL bit 0	DCM[1]: DRP[7] bit 12 DCM[1]: DFS_CUSTOM_FAST_SYNC bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 10 DCM[1]: DFS_CUSTOM_FAST_SYNC bit 1	DCM[1]: DRP[7] bit 11 DCM[1]: DFS_CUSTOM_FAST_SYNC bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 9 DCM[1]: DFS_CUSTOM_FAST_SYNC bit 0	DCM[1]: DRP[7] bit 8 DCM[1]: DCM_CLKDV_CLKFX_ALIGNMENT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 6 DCM[1]: DFS_MPW_LOW	DCM[1]: DRP[7] bit 7 DCM[1]: DFS_MPW_HIGH	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 5 DCM[1]: DCM_UNUSED_TAPS_POWERDOWN bit 0	DCM[1]: DRP[7] bit 4 DCM[1]: ! DFS_EN_RELRST_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 2 DCM[1]: OUT_CONCUR_ENABLE	DCM[1]: DRP[7] bit 3 DCM[1]: DFS_OUTPUT_PSDLY_ON_CONCUR	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[7] bit 1 DCM[1]: OUT_CLKFX180_ENABLE	DCM[1]: DRP[7] bit 0 DCM[1]: OUT_CLKFX_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 14	DCM[1]: DRP[6] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 13	DCM[1]: DRP[6] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 10	DCM[1]: DRP[6] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 9	DCM[1]: DRP[6] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 6 DCM[1]: DFS_TWEAK bit 6	DCM[1]: DRP[6] bit 7 DCM[1]: DFS_TWEAK bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 5 DCM[1]: DFS_TWEAK bit 5	DCM[1]: DRP[6] bit 4 DCM[1]: DFS_TWEAK bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 2 DCM[1]: DFS_TWEAK bit 2	DCM[1]: DRP[6] bit 3 DCM[1]: DFS_TWEAK bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[6] bit 1 DCM[1]: DFS_TWEAK bit 1	DCM[1]: DRP[6] bit 0 DCM[1]: DFS_TWEAK bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 14	DCM[1]: DRP[5] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 13	DCM[1]: DRP[5] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 10 DCM[1]: DFS_TAPTRIM bit 10	DCM[1]: DRP[5] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 9 DCM[1]: DFS_TAPTRIM bit 9	DCM[1]: DRP[5] bit 8 DCM[1]: DFS_TAPTRIM bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 6 DCM[1]: DFS_TAPTRIM bit 6	DCM[1]: DRP[5] bit 7 DCM[1]: DFS_TAPTRIM bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 5 DCM[1]: DFS_TAPTRIM bit 5	DCM[1]: DRP[5] bit 4 DCM[1]: DFS_TAPTRIM bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 2 DCM[1]: DFS_TAPTRIM bit 2	DCM[1]: DRP[5] bit 3 DCM[1]: DFS_TAPTRIM bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[5] bit 1 DCM[1]: DFS_TAPTRIM bit 1	DCM[1]: DRP[5] bit 0 DCM[1]: DFS_TAPTRIM bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 14 DCM[1]: DFS_EN	DCM[1]: DRP[4] bit 15 DCM[1]: DFS_FAST_UPDATE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 13 DCM[1]: DFS_SYNC_TO_DLL	DCM[1]: DRP[4] bit 12 DCM[1]: DCM_CLKFB_IODLY_MUXINSEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 10 DCM[1]: CLKIN_DIVIDE_BY_2	DCM[1]: DRP[4] bit 11 DCM[1]: DCM_CLKIN_IODLY_MUXINSEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 9 DCM[1]: DCM_WAIT_PLL	DCM[1]: DRP[4] bit 8 DCM[1]: DFS_SYNTH_CLOCK_SPEED bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 6 DCM[1]: DFS_SYNTH_CLOCK_SPEED bit 0	DCM[1]: DRP[4] bit 7 DCM[1]: DFS_SYNTH_CLOCK_SPEED bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 5 DCM[1]: DLL_SYNTH_CLOCK_SPEED bit 1	DCM[1]: DRP[4] bit 4 DCM[1]: DLL_SYNTH_CLOCK_SPEED bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 2 DCM[1]: DCM_EXT_FB_EN	DCM[1]: DRP[4] bit 3 DCM[1]: DCM_USE_REG_READY	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[4] bit 1 DCM[1]: DCM_COM_PWC_FB_EN	DCM[1]: DRP[4] bit 0 DCM[1]: DCM_COM_PWC_REF_EN	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 14 DCM[1]: DCM_COM_PWC_FB_TAP bit 1	DCM[1]: DRP[3] bit 15 DCM[1]: DCM_COM_PWC_FB_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 13 DCM[1]: DCM_COM_PWC_FB_TAP bit 0	DCM[1]: DRP[3] bit 12 DCM[1]: DCM_COM_PWC_REF_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 10 DCM[1]: DCM_COM_PWC_REF_TAP bit 0	DCM[1]: DRP[3] bit 11 DCM[1]: DCM_COM_PWC_REF_TAP bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 9 DCM[1]: DCM_PLL_RST_DCM	DCM[1]: DRP[3] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 6 DCM[1]: DESKEW_ADJUST bit 3	DCM[1]: DRP[3] bit 7 DCM[1]: DESKEW_ADJUST bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 5 DCM[1]: DESKEW_ADJUST bit 2	DCM[1]: DRP[3] bit 4 DCM[1]: DESKEW_ADJUST bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 2	DCM[1]: DRP[3] bit 3 DCM[1]: DESKEW_ADJUST bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[3] bit 1 DCM[1]: DCM_CLKIN_IODLY_MUXOUT_SEL bit 0	DCM[1]: DRP[3] bit 0 DCM[1]: DCM_CLKFB_IODLY_MUXOUT_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 14 DCM[1]: ! DFS_PWRD_CLKIN_STOP_STICKY_B	DCM[1]: DRP[2] bit 15 DCM[1]: ! DFS_PWRD_CLKIN_STOP_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 13 DCM[1]: ! DFS_PWRD_REPLY_TIMES_OUT_B	DCM[1]: DRP[2] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 10 DCM[1]: DFS_HF_TRIM_CAL bit 1	DCM[1]: DRP[2] bit 11 DCM[1]: DFS_HF_TRIM_CAL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 9 DCM[1]: DFS_HF_TRIM_CAL bit 0	DCM[1]: DRP[2] bit 8 DCM[1]: DFS_REF_ON_FX	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 6 DCM[1]: DFS_JF_LOWER_LIMIT bit 3	DCM[1]: DRP[2] bit 7 DCM[1]: DFS_OSC_ON_FX	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 5 DCM[1]: DFS_JF_LOWER_LIMIT bit 2	DCM[1]: DRP[2] bit 4 DCM[1]: DFS_JF_LOWER_LIMIT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 2	DCM[1]: DRP[2] bit 3 DCM[1]: DFS_JF_LOWER_LIMIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[2] bit 1	DCM[1]: DRP[2] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 14 DCM[1]: DFS_HARDSYNC_B bit 0	DCM[1]: DRP[1] bit 15 DCM[1]: DFS_HARDSYNC_B bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 13	DCM[1]: DRP[1] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 10	DCM[1]: DRP[1] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 9 DCM[1]: DFS_EARLY_LOCK	DCM[1]: DRP[1] bit 8 DCM[1]: DFS_AVE_FREQ_GAIN bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 6 DCM[1]: DFS_AVE_FREQ_GAIN bit 1	DCM[1]: DRP[1] bit 7 DCM[1]: DFS_AVE_FREQ_GAIN bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 5 DCM[1]: DFS_SYNTH_FAST_SYNCH bit 1	DCM[1]: DRP[1] bit 4 DCM[1]: DFS_SYNTH_FAST_SYNCH bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 2 DCM[1]: DFS_FREQUENCY_MODE bit 0	DCM[1]: DRP[1] bit 3 DCM[1]: DFS_CFG_BYPASS	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[1] bit 1 DCM[1]: DFS_OSCILLATOR_MODE bit 0	DCM[1]: DRP[1] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 14	DCM[1]: DRP[0] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 13	DCM[1]: DRP[0] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 10	DCM[1]: DRP[0] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 9	DCM[1]: DRP[0] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 6	DCM[1]: DRP[0] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 5	DCM[1]: DRP[0] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 2	DCM[1]: DRP[0] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[0] bit 1	DCM[1]: DRP[0] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 14 DCM[1]: FACTORY_JF bit 14	DCM[1]: DRP[15] bit 15 DCM[1]: FACTORY_JF bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 13 DCM[1]: FACTORY_JF bit 13	DCM[1]: DRP[15] bit 12 DCM[1]: FACTORY_JF bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 10 DCM[1]: FACTORY_JF bit 10	DCM[1]: DRP[15] bit 11 DCM[1]: FACTORY_JF bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 9 DCM[1]: FACTORY_JF bit 9	DCM[1]: DRP[15] bit 8 DCM[1]: FACTORY_JF bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 6 DCM[1]: FACTORY_JF bit 6	DCM[1]: DRP[15] bit 7 DCM[1]: FACTORY_JF bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 5 DCM[1]: FACTORY_JF bit 5	DCM[1]: DRP[15] bit 4 DCM[1]: FACTORY_JF bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 2 DCM[1]: FACTORY_JF bit 2	DCM[1]: DRP[15] bit 3 DCM[1]: FACTORY_JF bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[15] bit 1 DCM[1]: FACTORY_JF bit 1	DCM[1]: DRP[15] bit 0 DCM[1]: FACTORY_JF bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 14 DCM[1]: DLL_DESKEW_MAXTAP bit 6	DCM[1]: DRP[14] bit 15 DCM[1]: DLL_DESKEW_MAXTAP bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 13 DCM[1]: DLL_DESKEW_MAXTAP bit 5	DCM[1]: DRP[14] bit 12 DCM[1]: DLL_DESKEW_MAXTAP bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 10 DCM[1]: DLL_DESKEW_MAXTAP bit 2	DCM[1]: DRP[14] bit 11 DCM[1]: DLL_DESKEW_MAXTAP bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 9 DCM[1]: DLL_DESKEW_MAXTAP bit 1	DCM[1]: DRP[14] bit 8 DCM[1]: DLL_DESKEW_MAXTAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 6 DCM[1]: DLL_DESKEW_MINTAP bit 6	DCM[1]: DRP[14] bit 7 DCM[1]: DLL_DESKEW_MINTAP bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 5 DCM[1]: DLL_DESKEW_MINTAP bit 5	DCM[1]: DRP[14] bit 4 DCM[1]: DLL_DESKEW_MINTAP bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 2 DCM[1]: DLL_DESKEW_MINTAP bit 2	DCM[1]: DRP[14] bit 3 DCM[1]: DLL_DESKEW_MINTAP bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[14] bit 1 DCM[1]: DLL_DESKEW_MINTAP bit 1	DCM[1]: DRP[14] bit 0 DCM[1]: DLL_DESKEW_MINTAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 14 DCM[1]: DLL_ZD1_TAP_INIT bit 6	DCM[1]: DRP[13] bit 15 DCM[1]: DLL_ZD1_TAP_INIT bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 13 DCM[1]: DLL_ZD1_TAP_INIT bit 5	DCM[1]: DRP[13] bit 12 DCM[1]: DLL_ZD1_TAP_INIT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 10 DCM[1]: DLL_ZD1_TAP_INIT bit 2	DCM[1]: DRP[13] bit 11 DCM[1]: DLL_ZD1_TAP_INIT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 9 DCM[1]: DLL_ZD1_TAP_INIT bit 1	DCM[1]: DRP[13] bit 8 DCM[1]: DLL_ZD1_TAP_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 6 DCM[1]: DLL_ZD2_TAP_INIT bit 6	DCM[1]: DRP[13] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 5 DCM[1]: DLL_ZD2_TAP_INIT bit 5	DCM[1]: DRP[13] bit 4 DCM[1]: DLL_ZD2_TAP_INIT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 2 DCM[1]: DLL_ZD2_TAP_INIT bit 2	DCM[1]: DRP[13] bit 3 DCM[1]: DLL_ZD2_TAP_INIT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[13] bit 1 DCM[1]: DLL_ZD2_TAP_INIT bit 1	DCM[1]: DRP[13] bit 0 DCM[1]: DLL_ZD2_TAP_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 14 DCM[1]: DCM_UNUSED_TAPS_POWERDOWN bit 1	DCM[1]: DRP[12] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 13 DCM[1]: DLL_ZD1_JF_OVERFLOW_HOLD	DCM[1]: DRP[12] bit 12 DCM[1]: DCM_UNUSED_TAPS_POWERDOWN bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 10 DCM[1]: DLL_DESKEW_LOCK_BY1	DCM[1]: DRP[12] bit 11 DCM[1]: DLL_ZD2_JF_OVERFLOW_HOLD	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 9 DCM[1]: DLL_PERIOD_LOCK_BY1	DCM[1]: DRP[12] bit 8 DCM[1]: DLL_ZD1_PHASE_SEL_INIT bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 6 DCM[1]: ! DLL_PWRD_ON_SCANMODE_B	DCM[1]: DRP[12] bit 7 DCM[1]: DLL_ZD1_PHASE_SEL_INIT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 5	DCM[1]: DRP[12] bit 4 DCM[1]: DLL_TAPINIT_CTL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 2 DCM[1]: DLL_TAPINIT_CTL bit 0	DCM[1]: DRP[12] bit 3 DCM[1]: DLL_TAPINIT_CTL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[12] bit 1 DCM[1]: DCM_SCANMODE	DCM[1]: DRP[12] bit 0 DCM[1]: DCM_UNUSED_TAPS_POWERDOWN bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 14	DCM[1]: DRP[11] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 13	DCM[1]: DRP[11] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 10	DCM[1]: DRP[11] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 9	DCM[1]: DRP[11] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: invert PSINCDEC DCM[1]: DRP[11] bit 6	DCM[1]: invert PSEN DCM[1]: DRP[11] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: invert RST DCM[1]: DRP[11] bit 5	DCM[1]: DRP[11] bit 4 DCM[1]: DLL_PHASE_SHIFT_LOCK_BY1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 2 DCM[1]: PS_CENTERED	DCM[1]: DRP[11] bit 3 DCM[1]: PS_DIRECT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[11] bit 1 DCM[1]: DLL_PHASE_SHIFT_CALIBRATION bit 1	DCM[1]: DRP[11] bit 0 DCM[1]: DLL_PHASE_SHIFT_CALIBRATION bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 14	DCM[1]: DRP[10] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 13	DCM[1]: DRP[10] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 10	DCM[1]: DRP[10] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 9	DCM[1]: DRP[10] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 6	DCM[1]: DRP[10] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 5	DCM[1]: DRP[10] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 2	DCM[1]: DRP[10] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[10] bit 1	DCM[1]: DRP[10] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[9] bit 14	DCM[1]: DRP[9] bit 15 DCM[1]: DCM_REG_PWRD_CFG	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[9] bit 13	DCM[1]: DRP[9] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[9] bit 10	DCM[1]: DRP[9] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[9] bit 9	DCM[1]: DRP[9] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[9] bit 6 DCM[1]: CLKIN_CLKFB_ENABLE	DCM[1]: DRP[9] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: invert SKEWRST DCM[1]: DRP[9] bit 5	DCM[1]: invert SKEWIN DCM[1]: DRP[9] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[1] bit 2 DCM[1]: DRP[9] bit 2	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[1] bit 3 DCM[1]: DRP[9] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[1] bit 1 DCM[1]: DRP[9] bit 1	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN2[1] bit 0 DCM[1]: DRP[9] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: invert SKEWCLKIN1 DCM[1]: DRP[8] bit 14	DCM[1]: invert SKEWCLKIN2 DCM[1]: DRP[8] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[1] bit 3 DCM[1]: DRP[8] bit 13	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[1] bit 2 DCM[1]: DRP[8] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[1] bit 0 DCM[1]: DRP[8] bit 10	SPEC_INT: mux CELL[0].OMUX_DCM_SKEWCLKIN1[1] bit 1 DCM[1]: DRP[8] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[1] bit 3 DCM[1]: DRP[8] bit 9	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[1] bit 4 DCM[1]: DRP[8] bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[1] bit 2 DCM[1]: DRP[8] bit 6	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[1] bit 1 DCM[1]: DRP[8] bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKFB[1] bit 0 DCM[1]: DRP[8] bit 5	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[1] bit 4 DCM[1]: DRP[8] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[1] bit 3 DCM[1]: DRP[8] bit 2	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[1] bit 2 DCM[1]: DRP[8] bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[1] bit 0 DCM[1]: DRP[8] bit 1	SPEC_INT: mux CELL[0].IMUX_DCM_CLKIN[1] bit 1 DCM[1]: DRP[8] bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 CMT rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43	F44	F45	F46	F47	F48	F49	F50	F51	F52	F53
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 14 DCM[1]: DCM_COMMON_MSB_SEL bit 1	DCM[1]: DRP[23] bit 15 DCM[1]: DCM_VSPLY_VALID_ACC bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 13 DCM[1]: DCM_COMMON_MSB_SEL bit 0	DCM[1]: DRP[23] bit 12 DCM[1]: DCM_VBG_PD bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 10 DCM[1]: ! DCM_POWERDOWN_COMMON_EN_B	DCM[1]: DRP[23] bit 11 DCM[1]: DCM_VBG_PD bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 9 DCM[1]: DLL_ZD2_PWC_EN	DCM[1]: DRP[23] bit 8 DCM[1]: DCM_VBG_SEL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 6 DCM[1]: ! DLL_PWRD_STICKY_B	DCM[1]: DRP[23] bit 7 DCM[1]: DCM_VBG_SEL bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 5 DCM[1]: DLL_ETPP_HOLD	DCM[1]: DRP[23] bit 4 DCM[1]: DCM_VBG_SEL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 2 DCM[1]: STARTUP_WAIT	DCM[1]: DRP[23] bit 3 DCM[1]: DCM_VBG_SEL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[23] bit 1 DCM[1]: DLL_ZD1_PWC_EN	DCM[1]: DRP[23] bit 0 DCM[1]: DCM_VSPLY_VALID_ACC bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 14 DCM[1]: DLL_ZD1_PWC_TAP bit 2	DCM[1]: DRP[22] bit 15 DCM[1]: DCM_VREG_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 13 DCM[1]: DLL_ZD1_PWC_TAP bit 1	DCM[1]: DRP[22] bit 12 DCM[1]: DLL_ZD1_PWC_TAP bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 10 DCM[1]: DLL_ZD2_PWC_TAP bit 1	DCM[1]: DRP[22] bit 11 DCM[1]: DLL_ZD2_PWC_TAP bit 2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 9 DCM[1]: DLL_ZD2_PWC_TAP bit 0	DCM[1]: DRP[22] bit 8 DCM[1]: DLL_PHASE_SHIFT_LFC bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 6 DCM[1]: DLL_PHASE_SHIFT_LFC bit 6	DCM[1]: DRP[22] bit 7 DCM[1]: DLL_PHASE_SHIFT_LFC bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 5 DCM[1]: DLL_PHASE_SHIFT_LFC bit 5	DCM[1]: DRP[22] bit 4 DCM[1]: DLL_PHASE_SHIFT_LFC bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 2 DCM[1]: DLL_PHASE_SHIFT_LFC bit 2	DCM[1]: DRP[22] bit 3 DCM[1]: DLL_PHASE_SHIFT_LFC bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[22] bit 1 DCM[1]: DLL_PHASE_SHIFT_LFC bit 1	DCM[1]: DRP[22] bit 0 DCM[1]: DLL_PHASE_SHIFT_LFC bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 14	DCM[1]: DRP[21] bit 15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 13	DCM[1]: DRP[21] bit 12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 10 DCM[1]: PHASE_SHIFT_NEGATIVE	DCM[1]: DRP[21] bit 11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 9 DCM[1]: PHASE_SHIFT bit 9	DCM[1]: DRP[21] bit 8 DCM[1]: PHASE_SHIFT bit 8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 6 DCM[1]: PHASE_SHIFT bit 6	DCM[1]: DRP[21] bit 7 DCM[1]: PHASE_SHIFT bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 5 DCM[1]: PHASE_SHIFT bit 5	DCM[1]: DRP[21] bit 4 DCM[1]: PHASE_SHIFT bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 2 DCM[1]: PHASE_SHIFT bit 2	DCM[1]: DRP[21] bit 3 DCM[1]: PHASE_SHIFT bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[21] bit 1 DCM[1]: PHASE_SHIFT bit 1	DCM[1]: DRP[21] bit 0 DCM[1]: PHASE_SHIFT bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 14 DCM[1]: DLL_TEST_MUX_SEL bit 0	DCM[1]: DRP[20] bit 15 DCM[1]: DLL_TEST_MUX_SEL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 13 DCM[1]: DCM_TRIM_CAL bit 2	DCM[1]: DRP[20] bit 12 DCM[1]: DCM_TRIM_CAL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 10 DCM[1]: OUT_CLKDV_ENABLE	DCM[1]: DRP[20] bit 11 DCM[1]: DCM_TRIM_CAL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 9 DCM[1]: OUT_CLK2X180_ENABLE	DCM[1]: DRP[20] bit 8 DCM[1]: OUT_CLK2X_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 6 DCM[1]: OUT_CLK180_ENABLE	DCM[1]: DRP[20] bit 7 DCM[1]: OUT_CLK270_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 5 DCM[1]: OUT_CLK90_ENABLE	DCM[1]: DRP[20] bit 4 DCM[1]: OUT_CLK0_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 2 DCM[1]: DCM_CLKLOST_EN	DCM[1]: DRP[20] bit 3 DCM[1]: ! DCM_LOCK_HIGH_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[20] bit 1 DCM[1]: DLL_FDBKLOST_EN	DCM[1]: DRP[20] bit 0 DCM[1]: CLKDV_MODE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 14 DCM[1]: CLKDV_PHASE_FALL bit 0	DCM[1]: DRP[19] bit 15 DCM[1]: CLKDV_PHASE_FALL bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 13 DCM[1]: CLKDV_PHASE_RISE bit 1	DCM[1]: DRP[19] bit 12 DCM[1]: CLKDV_PHASE_RISE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 10 DCM[1]: CLKDV_COUNT_FALL_2 bit 2	DCM[1]: DRP[19] bit 11 DCM[1]: CLKDV_COUNT_FALL_2 bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 9 DCM[1]: CLKDV_COUNT_FALL_2 bit 1	DCM[1]: DRP[19] bit 8 DCM[1]: CLKDV_COUNT_FALL_2 bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 6 DCM[1]: CLKDV_COUNT_FALL bit 2	DCM[1]: DRP[19] bit 7 DCM[1]: CLKDV_COUNT_FALL bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 5 DCM[1]: CLKDV_COUNT_FALL bit 1	DCM[1]: DRP[19] bit 4 DCM[1]: CLKDV_COUNT_FALL bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 2 DCM[1]: CLKDV_COUNT_MAX bit 2	DCM[1]: DRP[19] bit 3 DCM[1]: CLKDV_COUNT_MAX bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[19] bit 1 DCM[1]: CLKDV_COUNT_MAX bit 1	DCM[1]: DRP[19] bit 0 DCM[1]: CLKDV_COUNT_MAX bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 14 DCM[1]: DLL_DEAD_TIME bit 6	DCM[1]: DRP[18] bit 15 DCM[1]: DLL_DEAD_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 13 DCM[1]: DLL_DEAD_TIME bit 5	DCM[1]: DRP[18] bit 12 DCM[1]: DLL_DEAD_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 10 DCM[1]: DLL_DEAD_TIME bit 2	DCM[1]: DRP[18] bit 11 DCM[1]: DLL_DEAD_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 9 DCM[1]: DLL_DEAD_TIME bit 1	DCM[1]: DRP[18] bit 8 DCM[1]: DLL_DEAD_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 6 DCM[1]: DLL_LIVE_TIME bit 6	DCM[1]: DRP[18] bit 7 DCM[1]: DLL_LIVE_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 5 DCM[1]: DLL_LIVE_TIME bit 5	DCM[1]: DRP[18] bit 4 DCM[1]: DLL_LIVE_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 2 DCM[1]: DLL_LIVE_TIME bit 2	DCM[1]: DRP[18] bit 3 DCM[1]: DLL_LIVE_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[18] bit 1 DCM[1]: DLL_LIVE_TIME bit 1	DCM[1]: DRP[18] bit 0 DCM[1]: DLL_LIVE_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 14 DCM[1]: DLL_SETTLE_TIME bit 6	DCM[1]: DRP[17] bit 15 DCM[1]: DLL_SETTLE_TIME bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 13 DCM[1]: DLL_SETTLE_TIME bit 5	DCM[1]: DRP[17] bit 12 DCM[1]: DLL_SETTLE_TIME bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 10 DCM[1]: DLL_SETTLE_TIME bit 2	DCM[1]: DRP[17] bit 11 DCM[1]: DLL_SETTLE_TIME bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 9 DCM[1]: DLL_SETTLE_TIME bit 1	DCM[1]: DRP[17] bit 8 DCM[1]: DLL_SETTLE_TIME bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 6 DCM[1]: DLL_ZD1_EN	DCM[1]: DRP[17] bit 7 DCM[1]: PS_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 5 DCM[1]: DLL_ZD2_EN	DCM[1]: DRP[17] bit 4 DCM[1]: PS_MODE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 2 DCM[1]: DLL_FREQUENCY_MODE bit 0	DCM[1]: DRP[17] bit 3 DCM[1]: DLL_FREQUENCY_MODE bit 1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[17] bit 1 DCM[1]: ! DLL_CLKIN_STOPPED_PWRD_EN_B	DCM[1]: DRP[17] bit 0 DCM[1]: ! DLL_CLKFB_STOPPED_PWRD_EN_B	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 14 DCM[1]: CLKFX_MULTIPLY bit 6	DCM[1]: DRP[16] bit 15 DCM[1]: CLKFX_MULTIPLY bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 13 DCM[1]: CLKFX_MULTIPLY bit 5	DCM[1]: DRP[16] bit 12 DCM[1]: CLKFX_MULTIPLY bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 10 DCM[1]: CLKFX_MULTIPLY bit 2	DCM[1]: DRP[16] bit 11 DCM[1]: CLKFX_MULTIPLY bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 9 DCM[1]: CLKFX_MULTIPLY bit 1	DCM[1]: DRP[16] bit 8 DCM[1]: CLKFX_MULTIPLY bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 6 DCM[1]: CLKFX_DIVIDE bit 6	DCM[1]: DRP[16] bit 7 DCM[1]: CLKFX_DIVIDE bit 7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 5 DCM[1]: CLKFX_DIVIDE bit 5	DCM[1]: DRP[16] bit 4 DCM[1]: CLKFX_DIVIDE bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 2 DCM[1]: CLKFX_DIVIDE bit 2	DCM[1]: DRP[16] bit 3 DCM[1]: CLKFX_DIVIDE bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM[1]: DRP[16] bit 1 DCM[1]: CLKFX_DIVIDE bit 1	DCM[1]: DRP[16] bit 0 DCM[1]: CLKFX_DIVIDE bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tables

Table PLL_MULT

virtex5 table PLL_MULT
Row	PLL_CP_LOW	PLL_CP_HIGH	PLL_RES_LOW	PLL_RES_HIGH	PLL_LFHF_LOW	PLL_LFHF_HIGH
_1	0b0001	0b0010	0b1101	0b1011	0b11	0b11
_2	0b0001	0b0101	0b1110	0b1111	0b11	0b11
_3	0b0001	0b1100	0b0110	0b1111	0b11	0b11
_4	0b0001	0b1111	0b1010	0b1111	0b11	0b11
_5	0b0001	0b1111	0b1100	0b0111	0b11	0b11
_6	0b0001	0b1111	0b1100	0b1101	0b11	0b11
_7	0b0001	0b1111	0b1100	0b0011	0b11	0b11
_8	0b0001	0b1111	0b0010	0b0101	0b11	0b11
_9	0b0001	0b1111	0b0010	0b1001	0b11	0b11
_10	0b0001	0b1110	0b0100	0b1110	0b11	0b11
_11	0b0001	0b1111	0b0100	0b1110	0b11	0b11
_12	0b0001	0b1111	0b0100	0b1110	0b11	0b11
_13	0b0001	0b1111	0b0100	0b0001	0b11	0b11
_14	0b0001	0b1111	0b0100	0b0001	0b11	0b11
_15	0b0001	0b1111	0b0100	0b0001	0b11	0b11
_16	0b0001	0b1110	0b0100	0b0110	0b11	0b11
_17	0b0001	0b1110	0b0100	0b0110	0b11	0b11
_18	0b0001	0b1111	0b0100	0b0110	0b11	0b11
_19	0b0001	0b1110	0b1000	0b1010	0b11	0b11
_20	0b0001	0b1110	0b1000	0b1010	0b11	0b11
_21	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_22	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_23	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_24	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_25	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_26	0b0001	0b1111	0b1000	0b1010	0b11	0b11
_27	0b0001	0b1101	0b1000	0b1100	0b11	0b11
_28	0b0001	0b1101	0b1000	0b1100	0b11	0b11
_29	0b0001	0b1101	0b1000	0b1100	0b11	0b11
_30	0b0001	0b1110	0b1000	0b1100	0b11	0b11
_31	0b0010	0b1101	0b0100	0b1100	0b11	0b11
_32	0b0010	0b1100	0b0100	0b0010	0b11	0b11
_33	0b0010	0b1111	0b0100	0b1010	0b11	0b11
_34	0b0010	0b0111	0b0100	0b0010	0b11	0b11
_35	0b0010	0b0111	0b0100	0b0010	0b11	0b11
_36	0b0010	0b0111	0b0100	0b0010	0b11	0b11
_37	0b0010	0b0110	0b0100	0b0010	0b11	0b11
_38	0b0010	0b0110	0b1000	0b0010	0b11	0b11
_39	0b0010	0b0110	0b1000	0b0010	0b11	0b11
_40	0b0010	0b0110	0b1000	0b0010	0b11	0b11
_41	0b0010	0b0110	0b1000	0b0010	0b11	0b11
_42	0b0010	0b0100	0b1000	0b0100	0b11	0b11
_43	0b0010	0b0100	0b1000	0b0100	0b11	0b11
_44	0b0010	0b0100	0b1000	0b0100	0b11	0b11
_45	0b0010	0b0011	0b1000	0b1000	0b11	0b11
_46	0b0010	0b0011	0b1000	0b1000	0b11	0b11
_47	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_48	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_49	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_50	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_51	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_52	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_53	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_54	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_55	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_56	0b0010	0b0011	0b1000	0b0100	0b11	0b11
_57	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_58	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_59	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_60	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_61	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_62	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_63	0b0010	0b0010	0b1000	0b1000	0b11	0b11
_64	0b0010	0b0010	0b1000	0b1000	0b11	0b11

Device data pll-in-dly-set

virtex5 device data pll-in-dly-set
Device	PLL_V5_IN_DLY_SET
xc5vlx30	0b000011100
xc5vlx50	0b000011100
xc5vlx85	0b000011101
xq5vlx85	0b000011101
xc5vlx110	0b000011101
xq5vlx110	0b000011101
xc5vlx155	0b000011101
xc5vlx220	0b000011111
xc5vlx330	0b000011111
xc5vlx20t	0b000011010
xc5vlx30t	0b000011100
xq5vlx30t	0b000011100
xc5vlx50t	0b000011100
xc5vlx85t	0b000011101
xc5vlx110t	0b000011101
xq5vlx110t	0b000011101
xc5vlx155t	0b000011101
xq5vlx155t	0b000011101
xc5vlx220t	0b000011111
xq5vlx220t	0b000011111
xc5vlx330t	0b000011111
xq5vlx330t	0b000011111
xc5vsx35t	0b000011101
xc5vsx50t	0b000011101
xq5vsx50t	0b000011101
xc5vsx95t	0b000011111
xq5vsx95t	0b000011111
xc5vsx240t	0b000011111
xq5vsx240t	0b000011111
xc5vfx30t	0b000011101
xc5vfx70t	0b000011101
xq5vfx70t	0b000011101
xc5vfx100t	0b000011101
xq5vfx100t	0b000011101
xc5vfx130t	0b000011110
xq5vfx130t	0b000011110
xc5vfx200t	0b000011111
xq5vfx200t	0b000011111
xc5vtx150t	0b000011101
xc5vtx240t	0b000011110

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