PCI Express cores
Tile PCIE
Cells: 40
Bel PCIE
| Pin | Direction | Wires |
|---|---|---|
| AUXPOWER | input | TCELL39:IMUX.IMUX5.DELAY |
| BUSMASTERENABLE | output | TCELL35:OUT19.TMIN |
| CFGNEGOTIATEDLINKWIDTH0 | input | TCELL39:IMUX.IMUX7.DELAY |
| CFGNEGOTIATEDLINKWIDTH1 | input | TCELL38:IMUX.IMUX8.DELAY |
| CFGNEGOTIATEDLINKWIDTH2 | input | TCELL38:IMUX.IMUX9.DELAY |
| CFGNEGOTIATEDLINKWIDTH3 | input | TCELL38:IMUX.IMUX10.DELAY |
| CFGNEGOTIATEDLINKWIDTH4 | input | TCELL38:IMUX.IMUX11.DELAY |
| CFGNEGOTIATEDLINKWIDTH5 | input | TCELL37:IMUX.IMUX4.DELAY |
| COMPLIANCEAVOID | input | TCELL37:IMUX.IMUX6.DELAY |
| CRMCFGBRIDGEHOTRESET | input | TCELL19:IMUX.IMUX9.DELAY |
| CRMCORECLK | input | TCELL19:IMUX.CLK0 |
| CRMCORECLKDLO | input | TCELL30:IMUX.CLK0 |
| CRMCORECLKRXO | input | TCELL10:IMUX.CLK0 |
| CRMCORECLKTXO | input | TCELL18:IMUX.CLK0 |
| CRMDOHOTRESETN | output | TCELL19:OUT13.TMIN |
| CRMLINKRSTN | input | TCELL20:IMUX.CTRL1.SITE |
| CRMMACRSTN | input | TCELL20:IMUX.CTRL0.SITE |
| CRMMGMTRSTN | input | TCELL19:IMUX.CTRL2.SITE |
| CRMNVRSTN | input | TCELL19:IMUX.CTRL1.SITE |
| CRMPWRSOFTRESETN | output | TCELL19:OUT14.TMIN |
| CRMRXHOTRESETN | output | TCELL19:OUT12.TMIN |
| CRMTXHOTRESETN | input | TCELL19:IMUX.IMUX8.DELAY |
| CRMURSTN | input | TCELL19:IMUX.CTRL0.SITE |
| CRMUSERCFGRSTN | input | TCELL19:IMUX.CTRL3.SITE |
| CRMUSERCLK | input | TCELL19:IMUX.CLK1 |
| CRMUSERCLKRXO | input | TCELL10:IMUX.CLK1 |
| CRMUSERCLKTXO | input | TCELL18:IMUX.CLK1 |
| CROSSLINKSEED | input | TCELL37:IMUX.IMUX5.DELAY |
| DLLTXPMDLLPOUTSTANDING | output | TCELL38:OUT9.TMIN |
| INTERRUPTDISABLE | output | TCELL35:OUT22.TMIN |
| IOSPACEENABLE | output | TCELL25:OUT17.TMIN |
| L0ACKNAKTIMERADJUSTMENT0 | input | TCELL25:IMUX.IMUX13.DELAY |
| L0ACKNAKTIMERADJUSTMENT1 | input | TCELL25:IMUX.IMUX14.DELAY |
| L0ACKNAKTIMERADJUSTMENT10 | input | TCELL23:IMUX.IMUX15.DELAY |
| L0ACKNAKTIMERADJUSTMENT11 | input | TCELL22:IMUX.IMUX8.DELAY |
| L0ACKNAKTIMERADJUSTMENT2 | input | TCELL25:IMUX.IMUX15.DELAY |
| L0ACKNAKTIMERADJUSTMENT3 | input | TCELL24:IMUX.IMUX8.DELAY |
| L0ACKNAKTIMERADJUSTMENT4 | input | TCELL24:IMUX.IMUX9.DELAY |
| L0ACKNAKTIMERADJUSTMENT5 | input | TCELL24:IMUX.IMUX10.DELAY |
| L0ACKNAKTIMERADJUSTMENT6 | input | TCELL24:IMUX.IMUX11.DELAY |
| L0ACKNAKTIMERADJUSTMENT7 | input | TCELL23:IMUX.IMUX12.DELAY |
| L0ACKNAKTIMERADJUSTMENT8 | input | TCELL23:IMUX.IMUX13.DELAY |
| L0ACKNAKTIMERADJUSTMENT9 | input | TCELL23:IMUX.IMUX14.DELAY |
| L0ALLDOWNPORTSINL1 | input | TCELL10:IMUX.IMUX14.DELAY |
| L0ALLDOWNRXPORTSINL0S | input | TCELL11:IMUX.IMUX14.DELAY |
| L0ASAUTONOMOUSINITCOMPLETED | output | TCELL27:OUT16.TMIN |
| L0ASE | input | TCELL21:IMUX.IMUX11.DELAY |
| L0ASPORTCOUNT0 | input | TCELL20:IMUX.IMUX11.DELAY |
| L0ASPORTCOUNT1 | input | TCELL19:IMUX.IMUX12.DELAY |
| L0ASPORTCOUNT2 | input | TCELL19:IMUX.IMUX13.DELAY |
| L0ASPORTCOUNT3 | input | TCELL19:IMUX.IMUX14.DELAY |
| L0ASPORTCOUNT4 | input | TCELL19:IMUX.IMUX15.DELAY |
| L0ASPORTCOUNT5 | input | TCELL18:IMUX.IMUX8.DELAY |
| L0ASPORTCOUNT6 | input | TCELL18:IMUX.IMUX9.DELAY |
| L0ASPORTCOUNT7 | input | TCELL18:IMUX.IMUX10.DELAY |
| L0ASTURNPOOLBITSCONSUMED0 | input | TCELL20:IMUX.IMUX8.DELAY |
| L0ASTURNPOOLBITSCONSUMED1 | input | TCELL20:IMUX.IMUX9.DELAY |
| L0ASTURNPOOLBITSCONSUMED2 | input | TCELL20:IMUX.IMUX10.DELAY |
| L0ATTENTIONBUTTONPRESSED | input | TCELL36:IMUX.IMUX17.DELAY |
| L0ATTENTIONINDICATORCONTROL0 | output | TCELL33:OUT16.TMIN |
| L0ATTENTIONINDICATORCONTROL1 | output | TCELL33:OUT17.TMIN |
| L0CFGASSPANTREEOWNEDSTATE | input | TCELL21:IMUX.IMUX10.DELAY |
| L0CFGASSTATECHANGECMD0 | input | TCELL22:IMUX.IMUX10.DELAY |
| L0CFGASSTATECHANGECMD1 | input | TCELL22:IMUX.IMUX11.DELAY |
| L0CFGASSTATECHANGECMD2 | input | TCELL21:IMUX.IMUX8.DELAY |
| L0CFGASSTATECHANGECMD3 | input | TCELL21:IMUX.IMUX9.DELAY |
| L0CFGDISABLESCRAMBLE | input | TCELL15:IMUX.IMUX10.DELAY |
| L0CFGEXTENDEDSYNC | input | TCELL15:IMUX.IMUX11.DELAY |
| L0CFGL0SENTRYENABLE | input | TCELL39:IMUX.IMUX15.DELAY |
| L0CFGL0SENTRYSUP | input | TCELL39:IMUX.IMUX14.DELAY |
| L0CFGL0SEXITLAT0 | input | TCELL38:IMUX.IMUX24.DELAY |
| L0CFGL0SEXITLAT1 | input | TCELL38:IMUX.IMUX25.DELAY |
| L0CFGL0SEXITLAT2 | input | TCELL38:IMUX.IMUX26.DELAY |
| L0CFGLINKDISABLE | input | TCELL14:IMUX.IMUX8.DELAY |
| L0CFGLOOPBACKACK | output | TCELL38:OUT11.TMIN |
| L0CFGLOOPBACKMASTER | input | TCELL28:IMUX.IMUX12.DELAY |
| L0CFGNEGOTIATEDMAXP0 | input | TCELL16:IMUX.IMUX11.DELAY |
| L0CFGNEGOTIATEDMAXP1 | input | TCELL15:IMUX.IMUX8.DELAY |
| L0CFGNEGOTIATEDMAXP2 | input | TCELL15:IMUX.IMUX9.DELAY |
| L0CFGVCENABLE0 | input | TCELL18:IMUX.IMUX11.DELAY |
| L0CFGVCENABLE1 | input | TCELL17:IMUX.IMUX8.DELAY |
| L0CFGVCENABLE2 | input | TCELL17:IMUX.IMUX9.DELAY |
| L0CFGVCENABLE3 | input | TCELL17:IMUX.IMUX10.DELAY |
| L0CFGVCENABLE4 | input | TCELL17:IMUX.IMUX11.DELAY |
| L0CFGVCENABLE5 | input | TCELL16:IMUX.IMUX8.DELAY |
| L0CFGVCENABLE6 | input | TCELL16:IMUX.IMUX9.DELAY |
| L0CFGVCENABLE7 | input | TCELL16:IMUX.IMUX10.DELAY |
| L0CFGVCID0 | input | TCELL36:IMUX.IMUX4.DELAY |
| L0CFGVCID1 | input | TCELL36:IMUX.IMUX5.DELAY |
| L0CFGVCID10 | input | TCELL34:IMUX.IMUX10.DELAY |
| L0CFGVCID11 | input | TCELL34:IMUX.IMUX11.DELAY |
| L0CFGVCID12 | input | TCELL33:IMUX.IMUX15.DELAY |
| L0CFGVCID13 | input | TCELL33:IMUX.IMUX16.DELAY |
| L0CFGVCID14 | input | TCELL33:IMUX.IMUX17.DELAY |
| L0CFGVCID15 | input | TCELL33:IMUX.IMUX18.DELAY |
| L0CFGVCID16 | input | TCELL32:IMUX.IMUX12.DELAY |
| L0CFGVCID17 | input | TCELL32:IMUX.IMUX13.DELAY |
| L0CFGVCID18 | input | TCELL32:IMUX.IMUX14.DELAY |
| L0CFGVCID19 | input | TCELL32:IMUX.IMUX15.DELAY |
| L0CFGVCID2 | input | TCELL36:IMUX.IMUX6.DELAY |
| L0CFGVCID20 | input | TCELL31:IMUX.IMUX15.DELAY |
| L0CFGVCID21 | input | TCELL31:IMUX.IMUX16.DELAY |
| L0CFGVCID22 | input | TCELL31:IMUX.IMUX17.DELAY |
| L0CFGVCID23 | input | TCELL31:IMUX.IMUX18.DELAY |
| L0CFGVCID3 | input | TCELL36:IMUX.IMUX7.DELAY |
| L0CFGVCID4 | input | TCELL35:IMUX.IMUX4.DELAY |
| L0CFGVCID5 | input | TCELL35:IMUX.IMUX5.DELAY |
| L0CFGVCID6 | input | TCELL35:IMUX.IMUX6.DELAY |
| L0CFGVCID7 | input | TCELL35:IMUX.IMUX7.DELAY |
| L0CFGVCID8 | input | TCELL34:IMUX.IMUX8.DELAY |
| L0CFGVCID9 | input | TCELL34:IMUX.IMUX9.DELAY |
| L0COMPLETERID0 | output | TCELL27:OUT17.TMIN |
| L0COMPLETERID1 | output | TCELL27:OUT18.TMIN |
| L0COMPLETERID10 | output | TCELL24:OUT4.TMIN |
| L0COMPLETERID11 | output | TCELL24:OUT5.TMIN |
| L0COMPLETERID12 | output | TCELL24:OUT6.TMIN |
| L0COMPLETERID2 | output | TCELL27:OUT19.TMIN |
| L0COMPLETERID3 | output | TCELL26:OUT16.TMIN |
| L0COMPLETERID4 | output | TCELL26:OUT17.TMIN |
| L0COMPLETERID5 | output | TCELL26:OUT18.TMIN |
| L0COMPLETERID6 | output | TCELL25:OUT12.TMIN |
| L0COMPLETERID7 | output | TCELL25:OUT13.TMIN |
| L0COMPLETERID8 | output | TCELL25:OUT14.TMIN |
| L0COMPLETERID9 | output | TCELL25:OUT15.TMIN |
| L0CORRERRMSGRCVD | output | TCELL23:OUT12.TMIN |
| L0DLLASRXSTATE0 | output | TCELL28:OUT17.TMIN |
| L0DLLASRXSTATE1 | output | TCELL28:OUT18.TMIN |
| L0DLLASTXSTATE | output | TCELL28:OUT19.TMIN |
| L0DLLERRORVECTOR0 | output | TCELL30:OUT15.TMIN |
| L0DLLERRORVECTOR1 | output | TCELL30:OUT16.TMIN |
| L0DLLERRORVECTOR2 | output | TCELL30:OUT17.TMIN |
| L0DLLERRORVECTOR3 | output | TCELL29:OUT16.TMIN |
| L0DLLERRORVECTOR4 | output | TCELL29:OUT17.TMIN |
| L0DLLERRORVECTOR5 | output | TCELL29:OUT18.TMIN |
| L0DLLERRORVECTOR6 | output | TCELL28:OUT16.TMIN |
| L0DLLHOLDLINKUP | input | TCELL22:IMUX.IMUX9.DELAY |
| L0DLLRXACKOUTSTANDING | output | TCELL37:OUT16.TMIN |
| L0DLLTXNONFCOUTSTANDING | output | TCELL37:OUT18.TMIN |
| L0DLLTXOUTSTANDING | output | TCELL37:OUT17.TMIN |
| L0DLLVCSTATUS0 | output | TCELL36:OUT5.TMIN |
| L0DLLVCSTATUS1 | output | TCELL36:OUT6.TMIN |
| L0DLLVCSTATUS2 | output | TCELL36:OUT7.TMIN |
| L0DLLVCSTATUS3 | output | TCELL35:OUT3.TMIN |
| L0DLLVCSTATUS4 | output | TCELL35:OUT4.TMIN |
| L0DLLVCSTATUS5 | output | TCELL35:OUT5.TMIN |
| L0DLLVCSTATUS6 | output | TCELL35:OUT6.TMIN |
| L0DLLVCSTATUS7 | output | TCELL34:OUT8.TMIN |
| L0DLUPDOWN0 | output | TCELL34:OUT9.TMIN |
| L0DLUPDOWN1 | output | TCELL34:OUT10.TMIN |
| L0DLUPDOWN2 | output | TCELL34:OUT11.TMIN |
| L0DLUPDOWN3 | output | TCELL33:OUT12.TMIN |
| L0DLUPDOWN4 | output | TCELL33:OUT13.TMIN |
| L0DLUPDOWN5 | output | TCELL33:OUT14.TMIN |
| L0DLUPDOWN6 | output | TCELL33:OUT15.TMIN |
| L0DLUPDOWN7 | output | TCELL32:OUT15.TMIN |
| L0ELECTROMECHANICALINTERLOCKENGAGED | input | TCELL35:IMUX.IMUX16.DELAY |
| L0ERRMSGREQID0 | output | TCELL23:OUT15.TMIN |
| L0ERRMSGREQID1 | output | TCELL22:OUT12.TMIN |
| L0ERRMSGREQID10 | output | TCELL20:OUT15.TMIN |
| L0ERRMSGREQID11 | output | TCELL3:OUT22.TMIN |
| L0ERRMSGREQID12 | output | TCELL3:OUT23.TMIN |
| L0ERRMSGREQID13 | output | TCELL2:OUT22.TMIN |
| L0ERRMSGREQID14 | output | TCELL2:OUT23.TMIN |
| L0ERRMSGREQID15 | output | TCELL1:OUT22.TMIN |
| L0ERRMSGREQID2 | output | TCELL22:OUT13.TMIN |
| L0ERRMSGREQID3 | output | TCELL22:OUT14.TMIN |
| L0ERRMSGREQID4 | output | TCELL22:OUT15.TMIN |
| L0ERRMSGREQID5 | output | TCELL21:OUT12.TMIN |
| L0ERRMSGREQID6 | output | TCELL21:OUT13.TMIN |
| L0ERRMSGREQID7 | output | TCELL21:OUT14.TMIN |
| L0ERRMSGREQID8 | output | TCELL21:OUT15.TMIN |
| L0ERRMSGREQID9 | output | TCELL20:OUT14.TMIN |
| L0FATALERRMSGRCVD | output | TCELL23:OUT13.TMIN |
| L0FIRSTCFGWRITEOCCURRED | output | TCELL38:OUT10.TMIN |
| L0FWDASSERTINTALEGACYINT | input | TCELL36:IMUX.IMUX14.DELAY |
| L0FWDASSERTINTBLEGACYINT | input | TCELL36:IMUX.IMUX15.DELAY |
| L0FWDASSERTINTCLEGACYINT | input | TCELL35:IMUX.IMUX12.DELAY |
| L0FWDASSERTINTDLEGACYINT | input | TCELL35:IMUX.IMUX13.DELAY |
| L0FWDCORRERRIN | input | TCELL8:IMUX.IMUX12.DELAY |
| L0FWDCORRERROUT | output | TCELL0:OUT16.TMIN |
| L0FWDDEASSERTINTALEGACYINT | input | TCELL35:IMUX.IMUX14.DELAY |
| L0FWDDEASSERTINTBLEGACYINT | input | TCELL35:IMUX.IMUX15.DELAY |
| L0FWDDEASSERTINTCLEGACYINT | input | TCELL34:IMUX.IMUX16.DELAY |
| L0FWDDEASSERTINTDLEGACYINT | input | TCELL34:IMUX.IMUX17.DELAY |
| L0FWDFATALERRIN | input | TCELL8:IMUX.IMUX13.DELAY |
| L0FWDFATALERROUT | output | TCELL0:OUT17.TMIN |
| L0FWDNONFATALERRIN | input | TCELL8:IMUX.IMUX14.DELAY |
| L0FWDNONFATALERROUT | output | TCELL31:OUT19.TMIN |
| L0LEGACYINTFUNCT0 | input | TCELL36:IMUX.IMUX13.DELAY |
| L0LTSSMSTATE0 | output | TCELL37:OUT9.TMIN |
| L0LTSSMSTATE1 | output | TCELL37:OUT10.TMIN |
| L0LTSSMSTATE2 | output | TCELL37:OUT11.TMIN |
| L0LTSSMSTATE3 | output | TCELL36:OUT4.TMIN |
| L0MACENTEREDL0 | output | TCELL39:OUT11.TMIN |
| L0MACLINKTRAINING | output | TCELL37:OUT8.TMIN |
| L0MACLINKUP | output | TCELL39:OUT7.TMIN |
| L0MACNEGOTIATEDLINKWIDTH0 | output | TCELL38:OUT12.TMIN |
| L0MACNEGOTIATEDLINKWIDTH1 | output | TCELL38:OUT13.TMIN |
| L0MACNEGOTIATEDLINKWIDTH2 | output | TCELL38:OUT14.TMIN |
| L0MACNEGOTIATEDLINKWIDTH3 | output | TCELL38:OUT15.TMIN |
| L0MACNEWSTATEACK | output | TCELL39:OUT9.TMIN |
| L0MACRXL0SSTATE | output | TCELL39:OUT10.TMIN |
| L0MACUPSTREAMDOWNSTREAM | output | TCELL39:OUT4.TMIN |
| L0MCFOUND0 | output | TCELL31:OUT15.TMIN |
| L0MCFOUND1 | output | TCELL31:OUT16.TMIN |
| L0MCFOUND2 | output | TCELL31:OUT17.TMIN |
| L0MRLSENSORCLOSEDN | input | TCELL35:IMUX.IMUX17.DELAY |
| L0MSIENABLE0 | output | TCELL20:OUT16.TMIN |
| L0MSIREQUEST00 | input | TCELL34:IMUX.IMUX18.DELAY |
| L0MSIREQUEST01 | input | TCELL32:IMUX.IMUX20.DELAY |
| L0MSIREQUEST02 | input | TCELL32:IMUX.IMUX21.DELAY |
| L0MSIREQUEST03 | input | TCELL32:IMUX.IMUX22.DELAY |
| L0MULTIMSGEN00 | output | TCELL20:OUT17.TMIN |
| L0MULTIMSGEN01 | output | TCELL20:OUT18.TMIN |
| L0MULTIMSGEN02 | output | TCELL21:OUT16.TMIN |
| L0NONFATALERRMSGRCVD | output | TCELL23:OUT14.TMIN |
| L0PACKETHEADERFROMUSER0 | input | TCELL1:IMUX.IMUX9.DELAY |
| L0PACKETHEADERFROMUSER1 | input | TCELL1:IMUX.IMUX10.DELAY |
| L0PACKETHEADERFROMUSER10 | input | TCELL1:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER100 | input | TCELL35:IMUX.IMUX9.DELAY |
| L0PACKETHEADERFROMUSER101 | input | TCELL35:IMUX.IMUX10.DELAY |
| L0PACKETHEADERFROMUSER102 | input | TCELL35:IMUX.IMUX11.DELAY |
| L0PACKETHEADERFROMUSER103 | input | TCELL36:IMUX.IMUX8.DELAY |
| L0PACKETHEADERFROMUSER104 | input | TCELL36:IMUX.IMUX9.DELAY |
| L0PACKETHEADERFROMUSER105 | input | TCELL36:IMUX.IMUX10.DELAY |
| L0PACKETHEADERFROMUSER106 | input | TCELL36:IMUX.IMUX11.DELAY |
| L0PACKETHEADERFROMUSER107 | input | TCELL37:IMUX.IMUX8.DELAY |
| L0PACKETHEADERFROMUSER108 | input | TCELL37:IMUX.IMUX9.DELAY |
| L0PACKETHEADERFROMUSER109 | input | TCELL37:IMUX.IMUX10.DELAY |
| L0PACKETHEADERFROMUSER11 | input | TCELL2:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER110 | input | TCELL37:IMUX.IMUX11.DELAY |
| L0PACKETHEADERFROMUSER111 | input | TCELL38:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER112 | input | TCELL38:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER113 | input | TCELL38:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER114 | input | TCELL38:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER115 | input | TCELL39:IMUX.IMUX8.DELAY |
| L0PACKETHEADERFROMUSER116 | input | TCELL39:IMUX.IMUX9.DELAY |
| L0PACKETHEADERFROMUSER117 | input | TCELL39:IMUX.IMUX10.DELAY |
| L0PACKETHEADERFROMUSER118 | input | TCELL39:IMUX.IMUX11.DELAY |
| L0PACKETHEADERFROMUSER119 | input | TCELL38:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER12 | input | TCELL2:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER120 | input | TCELL38:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER121 | input | TCELL38:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER122 | input | TCELL38:IMUX.IMUX19.DELAY |
| L0PACKETHEADERFROMUSER123 | input | TCELL37:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER124 | input | TCELL37:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER125 | input | TCELL37:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER126 | input | TCELL37:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER127 | input | TCELL36:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER13 | input | TCELL2:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER14 | input | TCELL2:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER15 | input | TCELL3:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER16 | input | TCELL3:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER17 | input | TCELL3:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER18 | input | TCELL4:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER19 | input | TCELL4:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER2 | input | TCELL1:IMUX.IMUX11.DELAY |
| L0PACKETHEADERFROMUSER20 | input | TCELL4:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER21 | input | TCELL5:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER22 | input | TCELL5:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER23 | input | TCELL5:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER24 | input | TCELL6:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER25 | input | TCELL6:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER26 | input | TCELL6:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER27 | input | TCELL7:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER28 | input | TCELL7:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER29 | input | TCELL7:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER3 | input | TCELL0:IMUX.IMUX4.DELAY |
| L0PACKETHEADERFROMUSER30 | input | TCELL12:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER31 | input | TCELL12:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER32 | input | TCELL12:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER33 | input | TCELL14:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER34 | input | TCELL14:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER35 | input | TCELL14:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER36 | input | TCELL14:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER37 | input | TCELL15:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER38 | input | TCELL15:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER39 | input | TCELL15:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER4 | input | TCELL0:IMUX.IMUX5.DELAY |
| L0PACKETHEADERFROMUSER40 | input | TCELL15:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER41 | input | TCELL16:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER42 | input | TCELL16:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER43 | input | TCELL16:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER44 | input | TCELL16:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER45 | input | TCELL17:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER46 | input | TCELL17:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER47 | input | TCELL17:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER48 | input | TCELL17:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER49 | input | TCELL18:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER5 | input | TCELL0:IMUX.IMUX6.DELAY |
| L0PACKETHEADERFROMUSER50 | input | TCELL18:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER51 | input | TCELL18:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER52 | input | TCELL18:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER53 | input | TCELL19:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER54 | input | TCELL19:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER55 | input | TCELL19:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER56 | input | TCELL19:IMUX.IMUX19.DELAY |
| L0PACKETHEADERFROMUSER57 | input | TCELL20:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER58 | input | TCELL20:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER59 | input | TCELL20:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER6 | input | TCELL0:IMUX.IMUX7.DELAY |
| L0PACKETHEADERFROMUSER60 | input | TCELL20:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER61 | input | TCELL21:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER62 | input | TCELL21:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER63 | input | TCELL21:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER64 | input | TCELL21:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER65 | input | TCELL22:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER66 | input | TCELL22:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER67 | input | TCELL22:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER68 | input | TCELL22:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER69 | input | TCELL23:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER7 | input | TCELL1:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER70 | input | TCELL23:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER71 | input | TCELL23:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER72 | input | TCELL23:IMUX.IMUX19.DELAY |
| L0PACKETHEADERFROMUSER73 | input | TCELL24:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER74 | input | TCELL24:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER75 | input | TCELL24:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER76 | input | TCELL24:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER77 | input | TCELL25:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER78 | input | TCELL25:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER79 | input | TCELL25:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER8 | input | TCELL1:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER80 | input | TCELL25:IMUX.IMUX19.DELAY |
| L0PACKETHEADERFROMUSER81 | input | TCELL26:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER82 | input | TCELL26:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER83 | input | TCELL26:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER84 | input | TCELL26:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER85 | input | TCELL27:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER86 | input | TCELL27:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER87 | input | TCELL27:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER88 | input | TCELL27:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER89 | input | TCELL28:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER9 | input | TCELL1:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER90 | input | TCELL28:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER91 | input | TCELL32:IMUX.IMUX16.DELAY |
| L0PACKETHEADERFROMUSER92 | input | TCELL32:IMUX.IMUX17.DELAY |
| L0PACKETHEADERFROMUSER93 | input | TCELL32:IMUX.IMUX18.DELAY |
| L0PACKETHEADERFROMUSER94 | input | TCELL32:IMUX.IMUX19.DELAY |
| L0PACKETHEADERFROMUSER95 | input | TCELL34:IMUX.IMUX12.DELAY |
| L0PACKETHEADERFROMUSER96 | input | TCELL34:IMUX.IMUX13.DELAY |
| L0PACKETHEADERFROMUSER97 | input | TCELL34:IMUX.IMUX14.DELAY |
| L0PACKETHEADERFROMUSER98 | input | TCELL34:IMUX.IMUX15.DELAY |
| L0PACKETHEADERFROMUSER99 | input | TCELL35:IMUX.IMUX8.DELAY |
| L0PMEACK | output | TCELL35:OUT10.TMIN |
| L0PMEEN | output | TCELL36:OUT9.TMIN |
| L0PMEREQIN | input | TCELL37:IMUX.IMUX17.DELAY |
| L0PMEREQOUT | output | TCELL36:OUT8.TMIN |
| L0PORTNUMBER0 | input | TCELL14:IMUX.IMUX9.DELAY |
| L0PORTNUMBER1 | input | TCELL14:IMUX.IMUX10.DELAY |
| L0PORTNUMBER2 | input | TCELL14:IMUX.IMUX11.DELAY |
| L0PORTNUMBER3 | input | TCELL12:IMUX.IMUX12.DELAY |
| L0PORTNUMBER4 | input | TCELL12:IMUX.IMUX13.DELAY |
| L0PORTNUMBER5 | input | TCELL12:IMUX.IMUX14.DELAY |
| L0PORTNUMBER6 | input | TCELL12:IMUX.IMUX15.DELAY |
| L0PORTNUMBER7 | input | TCELL11:IMUX.IMUX12.DELAY |
| L0POWERCONTROLLERCONTROL | output | TCELL34:OUT14.TMIN |
| L0POWERFAULTDETECTED | input | TCELL35:IMUX.IMUX18.DELAY |
| L0POWERINDICATORCONTROL0 | output | TCELL34:OUT12.TMIN |
| L0POWERINDICATORCONTROL1 | output | TCELL34:OUT13.TMIN |
| L0PRESENCEDETECTSLOTEMPTYN | input | TCELL36:IMUX.IMUX16.DELAY |
| L0PWRINHIBITTRANSFERS | output | TCELL36:OUT10.TMIN |
| L0PWRL1STATE | output | TCELL36:OUT11.TMIN |
| L0PWRL23READYDEVICE | output | TCELL37:OUT12.TMIN |
| L0PWRL23READYSTATE | output | TCELL37:OUT13.TMIN |
| L0PWRNEWSTATEREQ | input | TCELL38:IMUX.IMUX23.DELAY |
| L0PWRNEXTLINKSTATE0 | input | TCELL39:IMUX.IMUX12.DELAY |
| L0PWRNEXTLINKSTATE1 | input | TCELL39:IMUX.IMUX13.DELAY |
| L0PWRSTATE00 | output | TCELL35:OUT8.TMIN |
| L0PWRSTATE01 | output | TCELL35:OUT9.TMIN |
| L0PWRTURNOFFREQ | output | TCELL37:OUT15.TMIN |
| L0PWRTXL0SSTATE | output | TCELL37:OUT14.TMIN |
| L0RECEIVEDASSERTINTALEGACYINT | output | TCELL0:OUT19.TMIN |
| L0RECEIVEDASSERTINTBLEGACYINT | output | TCELL9:OUT19.TMIN |
| L0RECEIVEDASSERTINTCLEGACYINT | output | TCELL9:OUT20.TMIN |
| L0RECEIVEDASSERTINTDLEGACYINT | output | TCELL9:OUT21.TMIN |
| L0RECEIVEDDEASSERTINTALEGACYINT | output | TCELL10:OUT18.TMIN |
| L0RECEIVEDDEASSERTINTBLEGACYINT | output | TCELL10:OUT19.TMIN |
| L0RECEIVEDDEASSERTINTCLEGACYINT | output | TCELL10:OUT20.TMIN |
| L0RECEIVEDDEASSERTINTDLEGACYINT | output | TCELL11:OUT15.TMIN |
| L0REPLAYTIMERADJUSTMENT0 | input | TCELL28:IMUX.IMUX13.DELAY |
| L0REPLAYTIMERADJUSTMENT1 | input | TCELL28:IMUX.IMUX14.DELAY |
| L0REPLAYTIMERADJUSTMENT10 | input | TCELL26:IMUX.IMUX11.DELAY |
| L0REPLAYTIMERADJUSTMENT11 | input | TCELL25:IMUX.IMUX12.DELAY |
| L0REPLAYTIMERADJUSTMENT2 | input | TCELL28:IMUX.IMUX15.DELAY |
| L0REPLAYTIMERADJUSTMENT3 | input | TCELL27:IMUX.IMUX8.DELAY |
| L0REPLAYTIMERADJUSTMENT4 | input | TCELL27:IMUX.IMUX9.DELAY |
| L0REPLAYTIMERADJUSTMENT5 | input | TCELL27:IMUX.IMUX10.DELAY |
| L0REPLAYTIMERADJUSTMENT6 | input | TCELL27:IMUX.IMUX11.DELAY |
| L0REPLAYTIMERADJUSTMENT7 | input | TCELL26:IMUX.IMUX8.DELAY |
| L0REPLAYTIMERADJUSTMENT8 | input | TCELL26:IMUX.IMUX9.DELAY |
| L0REPLAYTIMERADJUSTMENT9 | input | TCELL26:IMUX.IMUX10.DELAY |
| L0ROOTTURNOFFREQ | input | TCELL37:IMUX.IMUX18.DELAY |
| L0RXBEACON | output | TCELL35:OUT7.TMIN |
| L0RXDLLFCCMPLMCCRED0 | output | TCELL13:OUT18.TMIN |
| L0RXDLLFCCMPLMCCRED1 | output | TCELL12:OUT15.TMIN |
| L0RXDLLFCCMPLMCCRED10 | output | TCELL9:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED11 | output | TCELL8:OUT22.TMIN |
| L0RXDLLFCCMPLMCCRED12 | output | TCELL8:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED13 | output | TCELL7:OUT22.TMIN |
| L0RXDLLFCCMPLMCCRED14 | output | TCELL7:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED15 | output | TCELL6:OUT22.TMIN |
| L0RXDLLFCCMPLMCCRED16 | output | TCELL6:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED17 | output | TCELL5:OUT22.TMIN |
| L0RXDLLFCCMPLMCCRED18 | output | TCELL5:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED19 | output | TCELL1:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED2 | output | TCELL12:OUT16.TMIN |
| L0RXDLLFCCMPLMCCRED20 | output | TCELL0:OUT20.TMIN |
| L0RXDLLFCCMPLMCCRED21 | output | TCELL0:OUT21.TMIN |
| L0RXDLLFCCMPLMCCRED22 | output | TCELL0:OUT22.TMIN |
| L0RXDLLFCCMPLMCCRED23 | output | TCELL0:OUT23.TMIN |
| L0RXDLLFCCMPLMCCRED3 | output | TCELL12:OUT17.TMIN |
| L0RXDLLFCCMPLMCCRED4 | output | TCELL12:OUT18.TMIN |
| L0RXDLLFCCMPLMCCRED5 | output | TCELL11:OUT16.TMIN |
| L0RXDLLFCCMPLMCCRED6 | output | TCELL11:OUT17.TMIN |
| L0RXDLLFCCMPLMCCRED7 | output | TCELL11:OUT18.TMIN |
| L0RXDLLFCCMPLMCCRED8 | output | TCELL11:OUT19.TMIN |
| L0RXDLLFCCMPLMCCRED9 | output | TCELL9:OUT22.TMIN |
| L0RXDLLFCCMPLMCUPDATE0 | output | TCELL12:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE1 | output | TCELL13:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE2 | output | TCELL14:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE3 | output | TCELL15:OUT22.TMIN |
| L0RXDLLFCCMPLMCUPDATE4 | output | TCELL16:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE5 | output | TCELL17:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE6 | output | TCELL18:OUT19.TMIN |
| L0RXDLLFCCMPLMCUPDATE7 | output | TCELL19:OUT19.TMIN |
| L0RXDLLFCNPOSTBYPCRED0 | output | TCELL34:OUT17.TMIN |
| L0RXDLLFCNPOSTBYPCRED1 | output | TCELL34:OUT18.TMIN |
| L0RXDLLFCNPOSTBYPCRED10 | output | TCELL36:OUT15.TMIN |
| L0RXDLLFCNPOSTBYPCRED11 | output | TCELL37:OUT19.TMIN |
| L0RXDLLFCNPOSTBYPCRED12 | output | TCELL39:OUT12.TMIN |
| L0RXDLLFCNPOSTBYPCRED13 | output | TCELL39:OUT13.TMIN |
| L0RXDLLFCNPOSTBYPCRED14 | output | TCELL39:OUT14.TMIN |
| L0RXDLLFCNPOSTBYPCRED15 | output | TCELL39:OUT18.TMIN |
| L0RXDLLFCNPOSTBYPCRED16 | output | TCELL36:OUT16.TMIN |
| L0RXDLLFCNPOSTBYPCRED17 | output | TCELL36:OUT17.TMIN |
| L0RXDLLFCNPOSTBYPCRED18 | output | TCELL36:OUT18.TMIN |
| L0RXDLLFCNPOSTBYPCRED19 | output | TCELL36:OUT19.TMIN |
| L0RXDLLFCNPOSTBYPCRED2 | output | TCELL34:OUT19.TMIN |
| L0RXDLLFCNPOSTBYPCRED3 | output | TCELL35:OUT11.TMIN |
| L0RXDLLFCNPOSTBYPCRED4 | output | TCELL35:OUT12.TMIN |
| L0RXDLLFCNPOSTBYPCRED5 | output | TCELL35:OUT13.TMIN |
| L0RXDLLFCNPOSTBYPCRED6 | output | TCELL35:OUT14.TMIN |
| L0RXDLLFCNPOSTBYPCRED7 | output | TCELL36:OUT12.TMIN |
| L0RXDLLFCNPOSTBYPCRED8 | output | TCELL36:OUT13.TMIN |
| L0RXDLLFCNPOSTBYPCRED9 | output | TCELL36:OUT14.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE0 | output | TCELL35:OUT15.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE1 | output | TCELL35:OUT16.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE2 | output | TCELL35:OUT17.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE3 | output | TCELL35:OUT18.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE4 | output | TCELL25:OUT20.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE5 | output | TCELL25:OUT21.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE6 | output | TCELL25:OUT22.TMIN |
| L0RXDLLFCNPOSTBYPUPDATE7 | output | TCELL25:OUT23.TMIN |
| L0RXDLLFCPOSTORDCRED0 | output | TCELL24:OUT16.TMIN |
| L0RXDLLFCPOSTORDCRED1 | output | TCELL24:OUT17.TMIN |
| L0RXDLLFCPOSTORDCRED10 | output | TCELL18:OUT16.TMIN |
| L0RXDLLFCPOSTORDCRED11 | output | TCELL18:OUT17.TMIN |
| L0RXDLLFCPOSTORDCRED12 | output | TCELL18:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED13 | output | TCELL17:OUT15.TMIN |
| L0RXDLLFCPOSTORDCRED14 | output | TCELL17:OUT16.TMIN |
| L0RXDLLFCPOSTORDCRED15 | output | TCELL17:OUT17.TMIN |
| L0RXDLLFCPOSTORDCRED16 | output | TCELL17:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED17 | output | TCELL16:OUT15.TMIN |
| L0RXDLLFCPOSTORDCRED18 | output | TCELL16:OUT16.TMIN |
| L0RXDLLFCPOSTORDCRED19 | output | TCELL16:OUT17.TMIN |
| L0RXDLLFCPOSTORDCRED2 | output | TCELL24:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED20 | output | TCELL16:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED21 | output | TCELL15:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED22 | output | TCELL15:OUT19.TMIN |
| L0RXDLLFCPOSTORDCRED23 | output | TCELL15:OUT20.TMIN |
| L0RXDLLFCPOSTORDCRED3 | output | TCELL24:OUT19.TMIN |
| L0RXDLLFCPOSTORDCRED4 | output | TCELL20:OUT23.TMIN |
| L0RXDLLFCPOSTORDCRED5 | output | TCELL19:OUT15.TMIN |
| L0RXDLLFCPOSTORDCRED6 | output | TCELL19:OUT16.TMIN |
| L0RXDLLFCPOSTORDCRED7 | output | TCELL19:OUT17.TMIN |
| L0RXDLLFCPOSTORDCRED8 | output | TCELL19:OUT18.TMIN |
| L0RXDLLFCPOSTORDCRED9 | output | TCELL18:OUT15.TMIN |
| L0RXDLLFCPOSTORDUPDATE0 | output | TCELL15:OUT21.TMIN |
| L0RXDLLFCPOSTORDUPDATE1 | output | TCELL14:OUT15.TMIN |
| L0RXDLLFCPOSTORDUPDATE2 | output | TCELL14:OUT16.TMIN |
| L0RXDLLFCPOSTORDUPDATE3 | output | TCELL14:OUT17.TMIN |
| L0RXDLLFCPOSTORDUPDATE4 | output | TCELL14:OUT18.TMIN |
| L0RXDLLFCPOSTORDUPDATE5 | output | TCELL13:OUT15.TMIN |
| L0RXDLLFCPOSTORDUPDATE6 | output | TCELL13:OUT16.TMIN |
| L0RXDLLFCPOSTORDUPDATE7 | output | TCELL13:OUT17.TMIN |
| L0RXDLLPM | output | TCELL38:OUT16.TMIN |
| L0RXDLLPMTYPE0 | output | TCELL38:OUT17.TMIN |
| L0RXDLLPMTYPE1 | output | TCELL38:OUT18.TMIN |
| L0RXDLLPMTYPE2 | output | TCELL38:OUT19.TMIN |
| L0RXDLLSBFCDATA0 | output | TCELL20:OUT20.TMIN |
| L0RXDLLSBFCDATA1 | output | TCELL20:OUT21.TMIN |
| L0RXDLLSBFCDATA10 | output | TCELL22:OUT23.TMIN |
| L0RXDLLSBFCDATA11 | output | TCELL23:OUT20.TMIN |
| L0RXDLLSBFCDATA12 | output | TCELL23:OUT21.TMIN |
| L0RXDLLSBFCDATA13 | output | TCELL23:OUT22.TMIN |
| L0RXDLLSBFCDATA14 | output | TCELL23:OUT23.TMIN |
| L0RXDLLSBFCDATA15 | output | TCELL24:OUT12.TMIN |
| L0RXDLLSBFCDATA16 | output | TCELL24:OUT13.TMIN |
| L0RXDLLSBFCDATA17 | output | TCELL24:OUT14.TMIN |
| L0RXDLLSBFCDATA18 | output | TCELL24:OUT15.TMIN |
| L0RXDLLSBFCDATA2 | output | TCELL20:OUT22.TMIN |
| L0RXDLLSBFCDATA3 | output | TCELL21:OUT20.TMIN |
| L0RXDLLSBFCDATA4 | output | TCELL21:OUT21.TMIN |
| L0RXDLLSBFCDATA5 | output | TCELL21:OUT22.TMIN |
| L0RXDLLSBFCDATA6 | output | TCELL21:OUT23.TMIN |
| L0RXDLLSBFCDATA7 | output | TCELL22:OUT20.TMIN |
| L0RXDLLSBFCDATA8 | output | TCELL22:OUT21.TMIN |
| L0RXDLLSBFCDATA9 | output | TCELL22:OUT22.TMIN |
| L0RXDLLSBFCUPDATE | output | TCELL25:OUT19.TMIN |
| L0RXDLLTLPECRCOK | output | TCELL38:OUT8.TMIN |
| L0RXDLLTLPEND0 | output | TCELL10:OUT21.TMIN |
| L0RXDLLTLPEND1 | output | TCELL10:OUT22.TMIN |
| L0RXMACLINKERROR0 | output | TCELL39:OUT5.TMIN |
| L0RXMACLINKERROR1 | output | TCELL39:OUT6.TMIN |
| L0RXTLTLPNONINITIALIZEDVC0 | input | TCELL7:IMUX.IMUX39.DELAY |
| L0RXTLTLPNONINITIALIZEDVC1 | input | TCELL7:IMUX.IMUX40.DELAY |
| L0RXTLTLPNONINITIALIZEDVC2 | input | TCELL7:IMUX.IMUX41.DELAY |
| L0RXTLTLPNONINITIALIZEDVC3 | input | TCELL7:IMUX.IMUX42.DELAY |
| L0RXTLTLPNONINITIALIZEDVC4 | input | TCELL18:IMUX.IMUX37.DELAY |
| L0RXTLTLPNONINITIALIZEDVC5 | input | TCELL18:IMUX.IMUX38.DELAY |
| L0RXTLTLPNONINITIALIZEDVC6 | input | TCELL19:IMUX.IMUX39.DELAY |
| L0RXTLTLPNONINITIALIZEDVC7 | input | TCELL19:IMUX.IMUX40.DELAY |
| L0SENDUNLOCKMESSAGE | input | TCELL11:IMUX.IMUX13.DELAY |
| L0SETCOMPLETERABORTERROR | input | TCELL7:IMUX.IMUX12.DELAY |
| L0SETCOMPLETIONTIMEOUTCORRERROR | input | TCELL2:IMUX.IMUX8.DELAY |
| L0SETCOMPLETIONTIMEOUTUNCORRERROR | input | TCELL3:IMUX.IMUX15.DELAY |
| L0SETDETECTEDCORRERROR | input | TCELL7:IMUX.IMUX13.DELAY |
| L0SETDETECTEDFATALERROR | input | TCELL7:IMUX.IMUX14.DELAY |
| L0SETDETECTEDNONFATALERROR | input | TCELL7:IMUX.IMUX15.DELAY |
| L0SETLINKDETECTEDPARITYERROR | input | TCELL6:IMUX.IMUX12.DELAY |
| L0SETLINKMASTERDATAPARITY | input | TCELL6:IMUX.IMUX13.DELAY |
| L0SETLINKRECEIVEDMASTERABORT | input | TCELL6:IMUX.IMUX14.DELAY |
| L0SETLINKRECEIVEDTARGETABORT | input | TCELL6:IMUX.IMUX15.DELAY |
| L0SETLINKSIGNALLEDTARGETABORT | input | TCELL4:IMUX.IMUX12.DELAY |
| L0SETLINKSYSTEMERROR | input | TCELL5:IMUX.IMUX15.DELAY |
| L0SETUNEXPECTEDCOMPLETIONCORRERROR | input | TCELL2:IMUX.IMUX10.DELAY |
| L0SETUNEXPECTEDCOMPLETIONUNCORRERROR | input | TCELL2:IMUX.IMUX9.DELAY |
| L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR | input | TCELL2:IMUX.IMUX11.DELAY |
| L0SETUNSUPPORTEDREQUESTOTHERERROR | input | TCELL1:IMUX.IMUX8.DELAY |
| L0SETUSERDETECTEDPARITYERROR | input | TCELL4:IMUX.IMUX13.DELAY |
| L0SETUSERMASTERDATAPARITY | input | TCELL4:IMUX.IMUX14.DELAY |
| L0SETUSERRECEIVEDMASTERABORT | input | TCELL4:IMUX.IMUX15.DELAY |
| L0SETUSERRECEIVEDTARGETABORT | input | TCELL3:IMUX.IMUX12.DELAY |
| L0SETUSERSIGNALLEDTARGETABORT | input | TCELL3:IMUX.IMUX14.DELAY |
| L0SETUSERSYSTEMERROR | input | TCELL3:IMUX.IMUX13.DELAY |
| L0STATSCFGOTHERRECEIVED | output | TCELL23:OUT17.TMIN |
| L0STATSCFGOTHERTRANSMITTED | output | TCELL23:OUT18.TMIN |
| L0STATSCFGRECEIVED | output | TCELL22:OUT19.TMIN |
| L0STATSCFGTRANSMITTED | output | TCELL23:OUT16.TMIN |
| L0STATSDLLPRECEIVED | output | TCELL21:OUT17.TMIN |
| L0STATSDLLPTRANSMITTED | output | TCELL21:OUT18.TMIN |
| L0STATSOSRECEIVED | output | TCELL21:OUT19.TMIN |
| L0STATSOSTRANSMITTED | output | TCELL22:OUT16.TMIN |
| L0STATSTLPRECEIVED | output | TCELL22:OUT17.TMIN |
| L0STATSTLPTRANSMITTED | output | TCELL22:OUT18.TMIN |
| L0TLASFCCREDSTARVATION | input | TCELL29:IMUX.IMUX17.DELAY |
| L0TLLINKRETRAIN | input | TCELL39:IMUX.IMUX6.DELAY |
| L0TOGGLEELECTROMECHANICALINTERLOCK | output | TCELL34:OUT15.TMIN |
| L0TRANSACTIONSPENDING | input | TCELL10:IMUX.IMUX13.DELAY |
| L0TRANSFORMEDVC0 | output | TCELL31:OUT18.TMIN |
| L0TRANSFORMEDVC1 | output | TCELL32:OUT18.TMIN |
| L0TRANSFORMEDVC2 | output | TCELL32:OUT19.TMIN |
| L0TXBEACON | input | TCELL36:IMUX.IMUX18.DELAY |
| L0TXCFGPM | input | TCELL37:IMUX.IMUX19.DELAY |
| L0TXCFGPMTYPE0 | input | TCELL38:IMUX.IMUX20.DELAY |
| L0TXCFGPMTYPE1 | input | TCELL38:IMUX.IMUX21.DELAY |
| L0TXCFGPMTYPE2 | input | TCELL38:IMUX.IMUX22.DELAY |
| L0TXDLLFCCMPLMCUPDATED0 | output | TCELL30:OUT18.TMIN |
| L0TXDLLFCCMPLMCUPDATED1 | output | TCELL30:OUT19.TMIN |
| L0TXDLLFCCMPLMCUPDATED2 | output | TCELL30:OUT20.TMIN |
| L0TXDLLFCCMPLMCUPDATED3 | output | TCELL32:OUT16.TMIN |
| L0TXDLLFCCMPLMCUPDATED4 | output | TCELL32:OUT17.TMIN |
| L0TXDLLFCCMPLMCUPDATED5 | output | TCELL33:OUT18.TMIN |
| L0TXDLLFCCMPLMCUPDATED6 | output | TCELL33:OUT19.TMIN |
| L0TXDLLFCCMPLMCUPDATED7 | output | TCELL34:OUT16.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED0 | output | TCELL26:OUT19.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED1 | output | TCELL26:OUT20.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED2 | output | TCELL26:OUT21.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED3 | output | TCELL26:OUT22.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED4 | output | TCELL27:OUT20.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED5 | output | TCELL27:OUT21.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED6 | output | TCELL27:OUT22.TMIN |
| L0TXDLLFCNPOSTBYPUPDATED7 | output | TCELL27:OUT23.TMIN |
| L0TXDLLFCPOSTORDUPDATED0 | output | TCELL28:OUT20.TMIN |
| L0TXDLLFCPOSTORDUPDATED1 | output | TCELL28:OUT21.TMIN |
| L0TXDLLFCPOSTORDUPDATED2 | output | TCELL28:OUT22.TMIN |
| L0TXDLLFCPOSTORDUPDATED3 | output | TCELL28:OUT23.TMIN |
| L0TXDLLFCPOSTORDUPDATED4 | output | TCELL29:OUT19.TMIN |
| L0TXDLLFCPOSTORDUPDATED5 | output | TCELL29:OUT20.TMIN |
| L0TXDLLFCPOSTORDUPDATED6 | output | TCELL29:OUT21.TMIN |
| L0TXDLLFCPOSTORDUPDATED7 | output | TCELL29:OUT22.TMIN |
| L0TXDLLPMUPDATED | output | TCELL39:OUT8.TMIN |
| L0TXDLLSBFCUPDATED | output | TCELL20:OUT19.TMIN |
| L0TXTLFCCMPLMCCRED0 | input | TCELL13:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED1 | input | TCELL13:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED10 | input | TCELL10:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED100 | input | TCELL14:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED101 | input | TCELL17:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED102 | input | TCELL17:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED103 | input | TCELL17:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED104 | input | TCELL17:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED105 | input | TCELL18:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED106 | input | TCELL18:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED107 | input | TCELL18:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED108 | input | TCELL18:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED109 | input | TCELL19:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED11 | input | TCELL10:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED110 | input | TCELL19:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED111 | input | TCELL19:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED112 | input | TCELL20:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED113 | input | TCELL20:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED114 | input | TCELL20:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED115 | input | TCELL20:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED116 | input | TCELL21:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED117 | input | TCELL21:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED118 | input | TCELL21:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED119 | input | TCELL21:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED12 | input | TCELL10:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED120 | input | TCELL22:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED121 | input | TCELL22:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED122 | input | TCELL22:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED123 | input | TCELL22:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED124 | input | TCELL37:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED125 | input | TCELL37:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED126 | input | TCELL37:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED127 | input | TCELL39:IMUX.IMUX24.DELAY |
| L0TXTLFCCMPLMCCRED128 | input | TCELL39:IMUX.IMUX25.DELAY |
| L0TXTLFCCMPLMCCRED129 | input | TCELL39:IMUX.IMUX26.DELAY |
| L0TXTLFCCMPLMCCRED13 | input | TCELL10:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED130 | input | TCELL39:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED131 | input | TCELL18:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED132 | input | TCELL8:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED133 | input | TCELL8:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED134 | input | TCELL8:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED135 | input | TCELL8:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED136 | input | TCELL7:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED137 | input | TCELL7:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED138 | input | TCELL7:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED139 | input | TCELL7:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED14 | input | TCELL9:IMUX.IMUX23.DELAY |
| L0TXTLFCCMPLMCCRED140 | input | TCELL6:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED141 | input | TCELL6:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED142 | input | TCELL6:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED143 | input | TCELL6:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED144 | input | TCELL5:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED145 | input | TCELL5:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED146 | input | TCELL5:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED147 | input | TCELL5:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED148 | input | TCELL4:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED149 | input | TCELL4:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED15 | input | TCELL9:IMUX.IMUX24.DELAY |
| L0TXTLFCCMPLMCCRED150 | input | TCELL4:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED151 | input | TCELL4:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED152 | input | TCELL3:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED153 | input | TCELL3:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED154 | input | TCELL3:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED155 | input | TCELL3:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED156 | input | TCELL2:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED157 | input | TCELL2:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED158 | input | TCELL2:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED159 | input | TCELL2:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED16 | input | TCELL9:IMUX.IMUX25.DELAY |
| L0TXTLFCCMPLMCCRED17 | input | TCELL9:IMUX.IMUX26.DELAY |
| L0TXTLFCCMPLMCCRED18 | input | TCELL8:IMUX.IMUX23.DELAY |
| L0TXTLFCCMPLMCCRED19 | input | TCELL8:IMUX.IMUX24.DELAY |
| L0TXTLFCCMPLMCCRED2 | input | TCELL12:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED20 | input | TCELL8:IMUX.IMUX25.DELAY |
| L0TXTLFCCMPLMCCRED21 | input | TCELL8:IMUX.IMUX26.DELAY |
| L0TXTLFCCMPLMCCRED22 | input | TCELL7:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED23 | input | TCELL7:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED24 | input | TCELL7:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED25 | input | TCELL7:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED26 | input | TCELL6:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED27 | input | TCELL6:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED28 | input | TCELL6:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED29 | input | TCELL6:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED3 | input | TCELL12:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED30 | input | TCELL5:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED31 | input | TCELL5:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED32 | input | TCELL5:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED33 | input | TCELL5:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED34 | input | TCELL4:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED35 | input | TCELL4:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED36 | input | TCELL4:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED37 | input | TCELL4:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED38 | input | TCELL3:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED39 | input | TCELL3:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED4 | input | TCELL12:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED40 | input | TCELL3:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED41 | input | TCELL3:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED42 | input | TCELL2:IMUX.IMUX24.DELAY |
| L0TXTLFCCMPLMCCRED43 | input | TCELL2:IMUX.IMUX25.DELAY |
| L0TXTLFCCMPLMCCRED44 | input | TCELL2:IMUX.IMUX26.DELAY |
| L0TXTLFCCMPLMCCRED45 | input | TCELL2:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED46 | input | TCELL1:IMUX.IMUX24.DELAY |
| L0TXTLFCCMPLMCCRED47 | input | TCELL1:IMUX.IMUX25.DELAY |
| L0TXTLFCCMPLMCCRED48 | input | TCELL1:IMUX.IMUX26.DELAY |
| L0TXTLFCCMPLMCCRED49 | input | TCELL1:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED5 | input | TCELL12:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED50 | input | TCELL0:IMUX.IMUX12.DELAY |
| L0TXTLFCCMPLMCCRED51 | input | TCELL0:IMUX.IMUX13.DELAY |
| L0TXTLFCCMPLMCCRED52 | input | TCELL0:IMUX.IMUX14.DELAY |
| L0TXTLFCCMPLMCCRED53 | input | TCELL0:IMUX.IMUX15.DELAY |
| L0TXTLFCCMPLMCCRED54 | input | TCELL1:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED55 | input | TCELL1:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED56 | input | TCELL1:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED57 | input | TCELL1:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED58 | input | TCELL2:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED59 | input | TCELL2:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED6 | input | TCELL11:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED60 | input | TCELL2:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED61 | input | TCELL2:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED62 | input | TCELL3:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED63 | input | TCELL3:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED64 | input | TCELL3:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED65 | input | TCELL3:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED66 | input | TCELL4:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED67 | input | TCELL4:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED68 | input | TCELL4:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED69 | input | TCELL4:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED7 | input | TCELL11:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED70 | input | TCELL5:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED71 | input | TCELL5:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED72 | input | TCELL5:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED73 | input | TCELL5:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED74 | input | TCELL6:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED75 | input | TCELL6:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED76 | input | TCELL6:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED77 | input | TCELL6:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED78 | input | TCELL7:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED79 | input | TCELL7:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED8 | input | TCELL11:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED80 | input | TCELL7:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED81 | input | TCELL7:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED82 | input | TCELL8:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED83 | input | TCELL8:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED84 | input | TCELL8:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED85 | input | TCELL8:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED86 | input | TCELL9:IMUX.IMUX27.DELAY |
| L0TXTLFCCMPLMCCRED87 | input | TCELL9:IMUX.IMUX28.DELAY |
| L0TXTLFCCMPLMCCRED88 | input | TCELL9:IMUX.IMUX29.DELAY |
| L0TXTLFCCMPLMCCRED89 | input | TCELL9:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED9 | input | TCELL11:IMUX.IMUX30.DELAY |
| L0TXTLFCCMPLMCCRED90 | input | TCELL12:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCCRED91 | input | TCELL12:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCCRED92 | input | TCELL12:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCCRED93 | input | TCELL12:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCCRED94 | input | TCELL13:IMUX.IMUX31.DELAY |
| L0TXTLFCCMPLMCCRED95 | input | TCELL13:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED96 | input | TCELL13:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCCRED97 | input | TCELL13:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCCRED98 | input | TCELL14:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCCRED99 | input | TCELL14:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCUPDATE0 | input | TCELL1:IMUX.IMUX32.DELAY |
| L0TXTLFCCMPLMCUPDATE1 | input | TCELL1:IMUX.IMUX33.DELAY |
| L0TXTLFCCMPLMCUPDATE10 | input | TCELL1:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCUPDATE11 | input | TCELL1:IMUX.IMUX39.DELAY |
| L0TXTLFCCMPLMCUPDATE12 | input | TCELL2:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCUPDATE13 | input | TCELL2:IMUX.IMUX37.DELAY |
| L0TXTLFCCMPLMCUPDATE14 | input | TCELL2:IMUX.IMUX38.DELAY |
| L0TXTLFCCMPLMCUPDATE15 | input | TCELL2:IMUX.IMUX39.DELAY |
| L0TXTLFCCMPLMCUPDATE2 | input | TCELL1:IMUX.IMUX34.DELAY |
| L0TXTLFCCMPLMCUPDATE3 | input | TCELL1:IMUX.IMUX35.DELAY |
| L0TXTLFCCMPLMCUPDATE4 | input | TCELL0:IMUX.IMUX16.DELAY |
| L0TXTLFCCMPLMCUPDATE5 | input | TCELL0:IMUX.IMUX17.DELAY |
| L0TXTLFCCMPLMCUPDATE6 | input | TCELL0:IMUX.IMUX18.DELAY |
| L0TXTLFCCMPLMCUPDATE7 | input | TCELL0:IMUX.IMUX19.DELAY |
| L0TXTLFCCMPLMCUPDATE8 | input | TCELL1:IMUX.IMUX36.DELAY |
| L0TXTLFCCMPLMCUPDATE9 | input | TCELL1:IMUX.IMUX37.DELAY |
| L0TXTLFCNPOSTBYPCRED0 | input | TCELL34:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED1 | input | TCELL35:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED10 | input | TCELL37:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED100 | input | TCELL17:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED101 | input | TCELL17:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED102 | input | TCELL17:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED103 | input | TCELL16:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED104 | input | TCELL16:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED105 | input | TCELL16:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED106 | input | TCELL16:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED107 | input | TCELL15:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED108 | input | TCELL15:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED109 | input | TCELL15:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED11 | input | TCELL37:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED110 | input | TCELL15:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED111 | input | TCELL14:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED112 | input | TCELL14:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED113 | input | TCELL14:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED114 | input | TCELL14:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED115 | input | TCELL13:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED116 | input | TCELL13:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED117 | input | TCELL13:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED118 | input | TCELL13:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED119 | input | TCELL12:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED12 | input | TCELL37:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED120 | input | TCELL12:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED121 | input | TCELL12:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED122 | input | TCELL12:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED123 | input | TCELL11:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED124 | input | TCELL11:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED125 | input | TCELL11:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED126 | input | TCELL11:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED127 | input | TCELL10:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED128 | input | TCELL10:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED129 | input | TCELL10:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED13 | input | TCELL38:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED130 | input | TCELL10:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED131 | input | TCELL9:IMUX.IMUX15.DELAY |
| L0TXTLFCNPOSTBYPCRED132 | input | TCELL9:IMUX.IMUX16.DELAY |
| L0TXTLFCNPOSTBYPCRED133 | input | TCELL9:IMUX.IMUX17.DELAY |
| L0TXTLFCNPOSTBYPCRED134 | input | TCELL9:IMUX.IMUX18.DELAY |
| L0TXTLFCNPOSTBYPCRED135 | input | TCELL8:IMUX.IMUX15.DELAY |
| L0TXTLFCNPOSTBYPCRED136 | input | TCELL8:IMUX.IMUX16.DELAY |
| L0TXTLFCNPOSTBYPCRED137 | input | TCELL8:IMUX.IMUX17.DELAY |
| L0TXTLFCNPOSTBYPCRED138 | input | TCELL8:IMUX.IMUX18.DELAY |
| L0TXTLFCNPOSTBYPCRED139 | input | TCELL7:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED14 | input | TCELL39:IMUX.IMUX16.DELAY |
| L0TXTLFCNPOSTBYPCRED140 | input | TCELL7:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED141 | input | TCELL7:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED142 | input | TCELL7:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED143 | input | TCELL6:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED144 | input | TCELL6:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED145 | input | TCELL6:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED146 | input | TCELL6:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED147 | input | TCELL5:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED148 | input | TCELL5:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED149 | input | TCELL5:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED15 | input | TCELL39:IMUX.IMUX17.DELAY |
| L0TXTLFCNPOSTBYPCRED150 | input | TCELL5:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED151 | input | TCELL4:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED152 | input | TCELL4:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED153 | input | TCELL4:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED154 | input | TCELL4:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED155 | input | TCELL3:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED156 | input | TCELL3:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED157 | input | TCELL3:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED158 | input | TCELL3:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED159 | input | TCELL2:IMUX.IMUX16.DELAY |
| L0TXTLFCNPOSTBYPCRED16 | input | TCELL39:IMUX.IMUX18.DELAY |
| L0TXTLFCNPOSTBYPCRED160 | input | TCELL2:IMUX.IMUX17.DELAY |
| L0TXTLFCNPOSTBYPCRED161 | input | TCELL2:IMUX.IMUX18.DELAY |
| L0TXTLFCNPOSTBYPCRED162 | input | TCELL2:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED163 | input | TCELL1:IMUX.IMUX16.DELAY |
| L0TXTLFCNPOSTBYPCRED164 | input | TCELL1:IMUX.IMUX17.DELAY |
| L0TXTLFCNPOSTBYPCRED165 | input | TCELL1:IMUX.IMUX18.DELAY |
| L0TXTLFCNPOSTBYPCRED166 | input | TCELL1:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED167 | input | TCELL0:IMUX.IMUX8.DELAY |
| L0TXTLFCNPOSTBYPCRED168 | input | TCELL0:IMUX.IMUX9.DELAY |
| L0TXTLFCNPOSTBYPCRED169 | input | TCELL0:IMUX.IMUX10.DELAY |
| L0TXTLFCNPOSTBYPCRED17 | input | TCELL39:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED170 | input | TCELL0:IMUX.IMUX11.DELAY |
| L0TXTLFCNPOSTBYPCRED171 | input | TCELL1:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED172 | input | TCELL1:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED173 | input | TCELL1:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED174 | input | TCELL1:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED175 | input | TCELL2:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED176 | input | TCELL2:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED177 | input | TCELL2:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED178 | input | TCELL2:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED179 | input | TCELL3:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED18 | input | TCELL38:IMUX.IMUX28.DELAY |
| L0TXTLFCNPOSTBYPCRED180 | input | TCELL3:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED181 | input | TCELL3:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED182 | input | TCELL3:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED183 | input | TCELL4:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED184 | input | TCELL4:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED185 | input | TCELL4:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED186 | input | TCELL4:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED187 | input | TCELL5:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED188 | input | TCELL5:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED189 | input | TCELL5:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED19 | input | TCELL38:IMUX.IMUX29.DELAY |
| L0TXTLFCNPOSTBYPCRED190 | input | TCELL5:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED191 | input | TCELL6:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED2 | input | TCELL35:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED20 | input | TCELL38:IMUX.IMUX30.DELAY |
| L0TXTLFCNPOSTBYPCRED21 | input | TCELL38:IMUX.IMUX31.DELAY |
| L0TXTLFCNPOSTBYPCRED22 | input | TCELL37:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED23 | input | TCELL37:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED24 | input | TCELL37:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED25 | input | TCELL37:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED26 | input | TCELL36:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED27 | input | TCELL36:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED28 | input | TCELL36:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED29 | input | TCELL36:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED3 | input | TCELL35:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED30 | input | TCELL35:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED31 | input | TCELL35:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED32 | input | TCELL35:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED33 | input | TCELL35:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED34 | input | TCELL34:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED35 | input | TCELL34:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED36 | input | TCELL34:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED37 | input | TCELL34:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED38 | input | TCELL33:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED39 | input | TCELL32:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED4 | input | TCELL35:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED40 | input | TCELL32:IMUX.IMUX28.DELAY |
| L0TXTLFCNPOSTBYPCRED41 | input | TCELL32:IMUX.IMUX29.DELAY |
| L0TXTLFCNPOSTBYPCRED42 | input | TCELL32:IMUX.IMUX30.DELAY |
| L0TXTLFCNPOSTBYPCRED43 | input | TCELL31:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED44 | input | TCELL31:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED45 | input | TCELL31:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED46 | input | TCELL31:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED47 | input | TCELL30:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED48 | input | TCELL30:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED49 | input | TCELL30:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED5 | input | TCELL36:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED50 | input | TCELL30:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED51 | input | TCELL29:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPCRED52 | input | TCELL29:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED53 | input | TCELL29:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED54 | input | TCELL29:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED55 | input | TCELL28:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED56 | input | TCELL28:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED57 | input | TCELL28:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED58 | input | TCELL28:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED59 | input | TCELL27:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED6 | input | TCELL36:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED60 | input | TCELL27:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED61 | input | TCELL27:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED62 | input | TCELL27:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED63 | input | TCELL26:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED64 | input | TCELL26:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED65 | input | TCELL26:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED66 | input | TCELL26:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED67 | input | TCELL25:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED68 | input | TCELL25:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED69 | input | TCELL25:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED7 | input | TCELL36:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED70 | input | TCELL25:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED71 | input | TCELL24:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED72 | input | TCELL24:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED73 | input | TCELL24:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED74 | input | TCELL24:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED75 | input | TCELL23:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED76 | input | TCELL23:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED77 | input | TCELL23:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED78 | input | TCELL23:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED79 | input | TCELL22:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED8 | input | TCELL36:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED80 | input | TCELL22:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED81 | input | TCELL22:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED82 | input | TCELL22:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED83 | input | TCELL21:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED84 | input | TCELL21:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED85 | input | TCELL21:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED86 | input | TCELL21:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED87 | input | TCELL20:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED88 | input | TCELL20:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED89 | input | TCELL20:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED9 | input | TCELL37:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED90 | input | TCELL20:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED91 | input | TCELL19:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPCRED92 | input | TCELL19:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPCRED93 | input | TCELL19:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPCRED94 | input | TCELL19:IMUX.IMUX27.DELAY |
| L0TXTLFCNPOSTBYPCRED95 | input | TCELL18:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPCRED96 | input | TCELL18:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPCRED97 | input | TCELL18:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPCRED98 | input | TCELL18:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPCRED99 | input | TCELL17:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPUPDATE0 | input | TCELL6:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPUPDATE1 | input | TCELL6:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPUPDATE10 | input | TCELL8:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPUPDATE11 | input | TCELL9:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPUPDATE12 | input | TCELL9:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPUPDATE13 | input | TCELL9:IMUX.IMUX21.DELAY |
| L0TXTLFCNPOSTBYPUPDATE14 | input | TCELL9:IMUX.IMUX22.DELAY |
| L0TXTLFCNPOSTBYPUPDATE15 | input | TCELL10:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPUPDATE2 | input | TCELL6:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPUPDATE3 | input | TCELL7:IMUX.IMUX23.DELAY |
| L0TXTLFCNPOSTBYPUPDATE4 | input | TCELL7:IMUX.IMUX24.DELAY |
| L0TXTLFCNPOSTBYPUPDATE5 | input | TCELL7:IMUX.IMUX25.DELAY |
| L0TXTLFCNPOSTBYPUPDATE6 | input | TCELL7:IMUX.IMUX26.DELAY |
| L0TXTLFCNPOSTBYPUPDATE7 | input | TCELL8:IMUX.IMUX19.DELAY |
| L0TXTLFCNPOSTBYPUPDATE8 | input | TCELL8:IMUX.IMUX20.DELAY |
| L0TXTLFCNPOSTBYPUPDATE9 | input | TCELL8:IMUX.IMUX21.DELAY |
| L0TXTLFCPOSTORDCRED0 | input | TCELL10:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED1 | input | TCELL10:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED10 | input | TCELL12:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED100 | input | TCELL38:IMUX.IMUX37.DELAY |
| L0TXTLFCPOSTORDCRED101 | input | TCELL38:IMUX.IMUX38.DELAY |
| L0TXTLFCPOSTORDCRED102 | input | TCELL38:IMUX.IMUX39.DELAY |
| L0TXTLFCPOSTORDCRED103 | input | TCELL37:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED104 | input | TCELL37:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED105 | input | TCELL37:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED106 | input | TCELL37:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED107 | input | TCELL36:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED108 | input | TCELL36:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED109 | input | TCELL36:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED11 | input | TCELL13:IMUX.IMUX23.DELAY |
| L0TXTLFCPOSTORDCRED110 | input | TCELL35:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED111 | input | TCELL35:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED112 | input | TCELL35:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED113 | input | TCELL35:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED114 | input | TCELL34:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED115 | input | TCELL34:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED116 | input | TCELL34:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED117 | input | TCELL32:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED118 | input | TCELL32:IMUX.IMUX36.DELAY |
| L0TXTLFCPOSTORDCRED119 | input | TCELL32:IMUX.IMUX37.DELAY |
| L0TXTLFCPOSTORDCRED12 | input | TCELL13:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED120 | input | TCELL32:IMUX.IMUX38.DELAY |
| L0TXTLFCPOSTORDCRED121 | input | TCELL27:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED122 | input | TCELL27:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED123 | input | TCELL27:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED124 | input | TCELL26:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED125 | input | TCELL26:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED126 | input | TCELL26:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED127 | input | TCELL26:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED128 | input | TCELL25:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED129 | input | TCELL25:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED13 | input | TCELL13:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED130 | input | TCELL24:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED131 | input | TCELL24:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED132 | input | TCELL24:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED133 | input | TCELL24:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED134 | input | TCELL23:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED135 | input | TCELL23:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED136 | input | TCELL23:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED137 | input | TCELL23:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED138 | input | TCELL22:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED139 | input | TCELL22:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED14 | input | TCELL13:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED140 | input | TCELL22:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED141 | input | TCELL22:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED142 | input | TCELL21:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED143 | input | TCELL21:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED144 | input | TCELL21:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED145 | input | TCELL21:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED146 | input | TCELL20:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED147 | input | TCELL20:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED148 | input | TCELL20:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED149 | input | TCELL20:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED15 | input | TCELL14:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED150 | input | TCELL19:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED151 | input | TCELL19:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED152 | input | TCELL19:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED153 | input | TCELL19:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED154 | input | TCELL18:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED155 | input | TCELL18:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED156 | input | TCELL18:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED157 | input | TCELL18:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED158 | input | TCELL17:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED159 | input | TCELL17:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED16 | input | TCELL14:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED17 | input | TCELL14:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED18 | input | TCELL14:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED19 | input | TCELL15:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED2 | input | TCELL10:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED20 | input | TCELL15:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED21 | input | TCELL15:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED22 | input | TCELL15:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED23 | input | TCELL16:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED24 | input | TCELL16:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED25 | input | TCELL16:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED26 | input | TCELL16:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED27 | input | TCELL17:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED28 | input | TCELL17:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED29 | input | TCELL17:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED3 | input | TCELL11:IMUX.IMUX23.DELAY |
| L0TXTLFCPOSTORDCRED30 | input | TCELL17:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED31 | input | TCELL18:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED32 | input | TCELL18:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED33 | input | TCELL18:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED34 | input | TCELL18:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED35 | input | TCELL19:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED36 | input | TCELL19:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED37 | input | TCELL19:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED38 | input | TCELL19:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED39 | input | TCELL20:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED4 | input | TCELL11:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED40 | input | TCELL20:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED41 | input | TCELL20:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED42 | input | TCELL20:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED43 | input | TCELL21:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED44 | input | TCELL21:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED45 | input | TCELL21:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED46 | input | TCELL21:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED47 | input | TCELL22:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED48 | input | TCELL22:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED49 | input | TCELL22:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED5 | input | TCELL11:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED50 | input | TCELL22:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED51 | input | TCELL23:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED52 | input | TCELL23:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED53 | input | TCELL23:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED54 | input | TCELL23:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED55 | input | TCELL24:IMUX.IMUX24.DELAY |
| L0TXTLFCPOSTORDCRED56 | input | TCELL24:IMUX.IMUX25.DELAY |
| L0TXTLFCPOSTORDCRED57 | input | TCELL24:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED58 | input | TCELL24:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED59 | input | TCELL25:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED6 | input | TCELL11:IMUX.IMUX26.DELAY |
| L0TXTLFCPOSTORDCRED60 | input | TCELL25:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED61 | input | TCELL25:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED62 | input | TCELL25:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED63 | input | TCELL26:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED64 | input | TCELL26:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED65 | input | TCELL26:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED66 | input | TCELL26:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED67 | input | TCELL27:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED68 | input | TCELL27:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED69 | input | TCELL27:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED7 | input | TCELL12:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED70 | input | TCELL27:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED71 | input | TCELL32:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED72 | input | TCELL32:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED73 | input | TCELL32:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED74 | input | TCELL32:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED75 | input | TCELL34:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED76 | input | TCELL34:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED77 | input | TCELL34:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED78 | input | TCELL34:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED79 | input | TCELL35:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED8 | input | TCELL12:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED80 | input | TCELL35:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED81 | input | TCELL35:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED82 | input | TCELL35:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED83 | input | TCELL36:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDCRED84 | input | TCELL36:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED85 | input | TCELL36:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED86 | input | TCELL36:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED87 | input | TCELL37:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDCRED88 | input | TCELL37:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED89 | input | TCELL37:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDCRED9 | input | TCELL12:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDCRED90 | input | TCELL37:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDCRED91 | input | TCELL38:IMUX.IMUX32.DELAY |
| L0TXTLFCPOSTORDCRED92 | input | TCELL38:IMUX.IMUX33.DELAY |
| L0TXTLFCPOSTORDCRED93 | input | TCELL38:IMUX.IMUX34.DELAY |
| L0TXTLFCPOSTORDCRED94 | input | TCELL38:IMUX.IMUX35.DELAY |
| L0TXTLFCPOSTORDCRED95 | input | TCELL39:IMUX.IMUX20.DELAY |
| L0TXTLFCPOSTORDCRED96 | input | TCELL39:IMUX.IMUX21.DELAY |
| L0TXTLFCPOSTORDCRED97 | input | TCELL39:IMUX.IMUX22.DELAY |
| L0TXTLFCPOSTORDCRED98 | input | TCELL39:IMUX.IMUX23.DELAY |
| L0TXTLFCPOSTORDCRED99 | input | TCELL38:IMUX.IMUX36.DELAY |
| L0TXTLFCPOSTORDUPDATE0 | input | TCELL17:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDUPDATE1 | input | TCELL17:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDUPDATE10 | input | TCELL14:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDUPDATE11 | input | TCELL14:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDUPDATE12 | input | TCELL14:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDUPDATE13 | input | TCELL14:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDUPDATE14 | input | TCELL13:IMUX.IMUX27.DELAY |
| L0TXTLFCPOSTORDUPDATE15 | input | TCELL13:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDUPDATE2 | input | TCELL16:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDUPDATE3 | input | TCELL16:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDUPDATE4 | input | TCELL16:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDUPDATE5 | input | TCELL16:IMUX.IMUX31.DELAY |
| L0TXTLFCPOSTORDUPDATE6 | input | TCELL15:IMUX.IMUX28.DELAY |
| L0TXTLFCPOSTORDUPDATE7 | input | TCELL15:IMUX.IMUX29.DELAY |
| L0TXTLFCPOSTORDUPDATE8 | input | TCELL15:IMUX.IMUX30.DELAY |
| L0TXTLFCPOSTORDUPDATE9 | input | TCELL15:IMUX.IMUX31.DELAY |
| L0TXTLSBFCDATA0 | input | TCELL29:IMUX.IMUX18.DELAY |
| L0TXTLSBFCDATA1 | input | TCELL30:IMUX.IMUX15.DELAY |
| L0TXTLSBFCDATA10 | input | TCELL32:IMUX.IMUX24.DELAY |
| L0TXTLSBFCDATA11 | input | TCELL32:IMUX.IMUX25.DELAY |
| L0TXTLSBFCDATA12 | input | TCELL32:IMUX.IMUX26.DELAY |
| L0TXTLSBFCDATA13 | input | TCELL33:IMUX.IMUX19.DELAY |
| L0TXTLSBFCDATA14 | input | TCELL33:IMUX.IMUX20.DELAY |
| L0TXTLSBFCDATA15 | input | TCELL33:IMUX.IMUX21.DELAY |
| L0TXTLSBFCDATA16 | input | TCELL33:IMUX.IMUX22.DELAY |
| L0TXTLSBFCDATA17 | input | TCELL34:IMUX.IMUX19.DELAY |
| L0TXTLSBFCDATA18 | input | TCELL34:IMUX.IMUX20.DELAY |
| L0TXTLSBFCDATA2 | input | TCELL30:IMUX.IMUX16.DELAY |
| L0TXTLSBFCDATA3 | input | TCELL30:IMUX.IMUX17.DELAY |
| L0TXTLSBFCDATA4 | input | TCELL30:IMUX.IMUX18.DELAY |
| L0TXTLSBFCDATA5 | input | TCELL31:IMUX.IMUX19.DELAY |
| L0TXTLSBFCDATA6 | input | TCELL31:IMUX.IMUX20.DELAY |
| L0TXTLSBFCDATA7 | input | TCELL31:IMUX.IMUX21.DELAY |
| L0TXTLSBFCDATA8 | input | TCELL31:IMUX.IMUX22.DELAY |
| L0TXTLSBFCDATA9 | input | TCELL32:IMUX.IMUX23.DELAY |
| L0TXTLSBFCUPDATE | input | TCELL34:IMUX.IMUX21.DELAY |
| L0TXTLTLPDATA0 | input | TCELL10:IMUX.IMUX15.DELAY |
| L0TXTLTLPDATA1 | input | TCELL10:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA10 | input | TCELL12:IMUX.IMUX21.DELAY |
| L0TXTLTLPDATA11 | input | TCELL12:IMUX.IMUX22.DELAY |
| L0TXTLTLPDATA12 | input | TCELL13:IMUX.IMUX15.DELAY |
| L0TXTLTLPDATA13 | input | TCELL13:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA14 | input | TCELL13:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA15 | input | TCELL13:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA16 | input | TCELL14:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA17 | input | TCELL14:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA18 | input | TCELL14:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA19 | input | TCELL14:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA2 | input | TCELL10:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA20 | input | TCELL15:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA21 | input | TCELL15:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA22 | input | TCELL15:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA23 | input | TCELL15:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA24 | input | TCELL16:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA25 | input | TCELL16:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA26 | input | TCELL16:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA27 | input | TCELL16:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA28 | input | TCELL17:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA29 | input | TCELL17:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA3 | input | TCELL10:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA30 | input | TCELL17:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA31 | input | TCELL17:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA32 | input | TCELL18:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA33 | input | TCELL18:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA34 | input | TCELL18:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA35 | input | TCELL18:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA36 | input | TCELL19:IMUX.IMUX20.DELAY |
| L0TXTLTLPDATA37 | input | TCELL19:IMUX.IMUX21.DELAY |
| L0TXTLTLPDATA38 | input | TCELL19:IMUX.IMUX22.DELAY |
| L0TXTLTLPDATA39 | input | TCELL19:IMUX.IMUX23.DELAY |
| L0TXTLTLPDATA4 | input | TCELL11:IMUX.IMUX15.DELAY |
| L0TXTLTLPDATA40 | input | TCELL20:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA41 | input | TCELL20:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA42 | input | TCELL20:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA43 | input | TCELL20:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA44 | input | TCELL21:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA45 | input | TCELL21:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA46 | input | TCELL21:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA47 | input | TCELL21:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA48 | input | TCELL22:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA49 | input | TCELL22:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA5 | input | TCELL11:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA50 | input | TCELL22:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA51 | input | TCELL22:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA52 | input | TCELL23:IMUX.IMUX20.DELAY |
| L0TXTLTLPDATA53 | input | TCELL23:IMUX.IMUX21.DELAY |
| L0TXTLTLPDATA54 | input | TCELL23:IMUX.IMUX22.DELAY |
| L0TXTLTLPDATA55 | input | TCELL23:IMUX.IMUX23.DELAY |
| L0TXTLTLPDATA56 | input | TCELL24:IMUX.IMUX16.DELAY |
| L0TXTLTLPDATA57 | input | TCELL24:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA58 | input | TCELL24:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA59 | input | TCELL24:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA6 | input | TCELL11:IMUX.IMUX17.DELAY |
| L0TXTLTLPDATA60 | input | TCELL25:IMUX.IMUX22.DELAY |
| L0TXTLTLPDATA61 | input | TCELL25:IMUX.IMUX23.DELAY |
| L0TXTLTLPDATA62 | input | TCELL26:IMUX.IMUX20.DELAY |
| L0TXTLTLPDATA63 | input | TCELL26:IMUX.IMUX21.DELAY |
| L0TXTLTLPDATA7 | input | TCELL11:IMUX.IMUX18.DELAY |
| L0TXTLTLPDATA8 | input | TCELL12:IMUX.IMUX19.DELAY |
| L0TXTLTLPDATA9 | input | TCELL12:IMUX.IMUX20.DELAY |
| L0TXTLTLPEDB | input | TCELL27:IMUX.IMUX22.DELAY |
| L0TXTLTLPENABLE0 | input | TCELL27:IMUX.IMUX20.DELAY |
| L0TXTLTLPENABLE1 | input | TCELL27:IMUX.IMUX21.DELAY |
| L0TXTLTLPEND0 | input | TCELL26:IMUX.IMUX22.DELAY |
| L0TXTLTLPEND1 | input | TCELL26:IMUX.IMUX23.DELAY |
| L0TXTLTLPLATENCY0 | input | TCELL28:IMUX.IMUX20.DELAY |
| L0TXTLTLPLATENCY1 | input | TCELL28:IMUX.IMUX21.DELAY |
| L0TXTLTLPLATENCY2 | input | TCELL29:IMUX.IMUX15.DELAY |
| L0TXTLTLPLATENCY3 | input | TCELL29:IMUX.IMUX16.DELAY |
| L0TXTLTLPREQ | input | TCELL27:IMUX.IMUX23.DELAY |
| L0TXTLTLPREQEND | input | TCELL28:IMUX.IMUX18.DELAY |
| L0TXTLTLPWIDTH | input | TCELL28:IMUX.IMUX19.DELAY |
| L0UCBYPFOUND0 | output | TCELL24:OUT20.TMIN |
| L0UCBYPFOUND1 | output | TCELL24:OUT21.TMIN |
| L0UCBYPFOUND2 | output | TCELL24:OUT22.TMIN |
| L0UCBYPFOUND3 | output | TCELL24:OUT23.TMIN |
| L0UCORDFOUND0 | output | TCELL26:OUT23.TMIN |
| L0UCORDFOUND1 | output | TCELL29:OUT23.TMIN |
| L0UCORDFOUND2 | output | TCELL30:OUT21.TMIN |
| L0UCORDFOUND3 | output | TCELL30:OUT22.TMIN |
| L0UNLOCKRECEIVED | output | TCELL24:OUT7.TMIN |
| L0UPSTREAMRXPORTINL0S | input | TCELL10:IMUX.IMUX12.DELAY |
| L0VC0PREVIEWEXPAND | input | TCELL37:IMUX.IMUX7.DELAY |
| L0WAKEN | input | TCELL37:IMUX.IMUX16.DELAY |
| LLKRX4DWHEADERN | output | TCELL4:OUT22.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN0 | output | TCELL4:OUT13.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN1 | output | TCELL4:OUT14.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN2 | output | TCELL4:OUT15.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN3 | output | TCELL5:OUT16.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN4 | output | TCELL5:OUT17.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN5 | output | TCELL5:OUT18.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN6 | output | TCELL4:OUT16.TMIN |
| LLKRXCHCOMPLETIONAVAILABLEN7 | output | TCELL4:OUT17.TMIN |
| LLKRXCHCOMPLETIONPARTIALN0 | output | TCELL6:OUT19.TMIN |
| LLKRXCHCOMPLETIONPARTIALN1 | output | TCELL6:OUT20.TMIN |
| LLKRXCHCOMPLETIONPARTIALN2 | output | TCELL6:OUT21.TMIN |
| LLKRXCHCOMPLETIONPARTIALN3 | output | TCELL7:OUT19.TMIN |
| LLKRXCHCOMPLETIONPARTIALN4 | output | TCELL7:OUT20.TMIN |
| LLKRXCHCOMPLETIONPARTIALN5 | output | TCELL7:OUT21.TMIN |
| LLKRXCHCOMPLETIONPARTIALN6 | output | TCELL8:OUT19.TMIN |
| LLKRXCHCOMPLETIONPARTIALN7 | output | TCELL8:OUT20.TMIN |
| LLKRXCHCONFIGAVAILABLEN | output | TCELL4:OUT18.TMIN |
| LLKRXCHCONFIGPARTIALN | output | TCELL8:OUT21.TMIN |
| LLKRXCHFIFO0 | input | TCELL5:IMUX.IMUX12.DELAY |
| LLKRXCHFIFO1 | input | TCELL5:IMUX.IMUX13.DELAY |
| LLKRXCHNONPOSTEDAVAILABLEN0 | output | TCELL2:OUT17.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN1 | output | TCELL2:OUT18.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN2 | output | TCELL2:OUT19.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN3 | output | TCELL3:OUT16.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN4 | output | TCELL3:OUT17.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN5 | output | TCELL3:OUT18.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN6 | output | TCELL3:OUT19.TMIN |
| LLKRXCHNONPOSTEDAVAILABLEN7 | output | TCELL4:OUT12.TMIN |
| LLKRXCHNONPOSTEDPARTIALN0 | output | TCELL0:OUT13.TMIN |
| LLKRXCHNONPOSTEDPARTIALN1 | output | TCELL0:OUT14.TMIN |
| LLKRXCHNONPOSTEDPARTIALN2 | output | TCELL0:OUT15.TMIN |
| LLKRXCHNONPOSTEDPARTIALN3 | output | TCELL4:OUT20.TMIN |
| LLKRXCHNONPOSTEDPARTIALN4 | output | TCELL4:OUT21.TMIN |
| LLKRXCHNONPOSTEDPARTIALN5 | output | TCELL5:OUT19.TMIN |
| LLKRXCHNONPOSTEDPARTIALN6 | output | TCELL5:OUT20.TMIN |
| LLKRXCHNONPOSTEDPARTIALN7 | output | TCELL5:OUT21.TMIN |
| LLKRXCHPOSTEDAVAILABLEN0 | output | TCELL0:OUT9.TMIN |
| LLKRXCHPOSTEDAVAILABLEN1 | output | TCELL0:OUT10.TMIN |
| LLKRXCHPOSTEDAVAILABLEN2 | output | TCELL0:OUT11.TMIN |
| LLKRXCHPOSTEDAVAILABLEN3 | output | TCELL1:OUT16.TMIN |
| LLKRXCHPOSTEDAVAILABLEN4 | output | TCELL1:OUT17.TMIN |
| LLKRXCHPOSTEDAVAILABLEN5 | output | TCELL1:OUT18.TMIN |
| LLKRXCHPOSTEDAVAILABLEN6 | output | TCELL1:OUT19.TMIN |
| LLKRXCHPOSTEDAVAILABLEN7 | output | TCELL2:OUT16.TMIN |
| LLKRXCHPOSTEDPARTIALN0 | output | TCELL4:OUT19.TMIN |
| LLKRXCHPOSTEDPARTIALN1 | output | TCELL3:OUT20.TMIN |
| LLKRXCHPOSTEDPARTIALN2 | output | TCELL3:OUT21.TMIN |
| LLKRXCHPOSTEDPARTIALN3 | output | TCELL2:OUT20.TMIN |
| LLKRXCHPOSTEDPARTIALN4 | output | TCELL2:OUT21.TMIN |
| LLKRXCHPOSTEDPARTIALN5 | output | TCELL1:OUT20.TMIN |
| LLKRXCHPOSTEDPARTIALN6 | output | TCELL1:OUT21.TMIN |
| LLKRXCHPOSTEDPARTIALN7 | output | TCELL39:OUT19.TMIN |
| LLKRXCHTC0 | input | TCELL4:IMUX.IMUX9.DELAY |
| LLKRXCHTC1 | input | TCELL4:IMUX.IMUX10.DELAY |
| LLKRXCHTC2 | input | TCELL4:IMUX.IMUX11.DELAY |
| LLKRXDATA0 | output | TCELL2:OUT6.TMIN |
| LLKRXDATA1 | output | TCELL2:OUT7.TMIN |
| LLKRXDATA10 | output | TCELL1:OUT8.TMIN |
| LLKRXDATA11 | output | TCELL1:OUT9.TMIN |
| LLKRXDATA12 | output | TCELL1:OUT10.TMIN |
| LLKRXDATA13 | output | TCELL1:OUT11.TMIN |
| LLKRXDATA14 | output | TCELL2:OUT8.TMIN |
| LLKRXDATA15 | output | TCELL2:OUT9.TMIN |
| LLKRXDATA16 | output | TCELL2:OUT10.TMIN |
| LLKRXDATA17 | output | TCELL2:OUT11.TMIN |
| LLKRXDATA18 | output | TCELL3:OUT8.TMIN |
| LLKRXDATA19 | output | TCELL3:OUT9.TMIN |
| LLKRXDATA2 | output | TCELL1:OUT4.TMIN |
| LLKRXDATA20 | output | TCELL3:OUT10.TMIN |
| LLKRXDATA21 | output | TCELL3:OUT11.TMIN |
| LLKRXDATA22 | output | TCELL4:OUT4.TMIN |
| LLKRXDATA23 | output | TCELL4:OUT5.TMIN |
| LLKRXDATA24 | output | TCELL4:OUT6.TMIN |
| LLKRXDATA25 | output | TCELL4:OUT7.TMIN |
| LLKRXDATA26 | output | TCELL5:OUT8.TMIN |
| LLKRXDATA27 | output | TCELL5:OUT9.TMIN |
| LLKRXDATA28 | output | TCELL5:OUT10.TMIN |
| LLKRXDATA29 | output | TCELL5:OUT11.TMIN |
| LLKRXDATA3 | output | TCELL1:OUT5.TMIN |
| LLKRXDATA30 | output | TCELL6:OUT12.TMIN |
| LLKRXDATA31 | output | TCELL6:OUT13.TMIN |
| LLKRXDATA32 | output | TCELL6:OUT14.TMIN |
| LLKRXDATA33 | output | TCELL6:OUT15.TMIN |
| LLKRXDATA34 | output | TCELL7:OUT12.TMIN |
| LLKRXDATA35 | output | TCELL7:OUT13.TMIN |
| LLKRXDATA36 | output | TCELL7:OUT14.TMIN |
| LLKRXDATA37 | output | TCELL7:OUT15.TMIN |
| LLKRXDATA38 | output | TCELL8:OUT12.TMIN |
| LLKRXDATA39 | output | TCELL8:OUT13.TMIN |
| LLKRXDATA4 | output | TCELL1:OUT6.TMIN |
| LLKRXDATA40 | output | TCELL8:OUT14.TMIN |
| LLKRXDATA41 | output | TCELL8:OUT15.TMIN |
| LLKRXDATA42 | output | TCELL9:OUT12.TMIN |
| LLKRXDATA43 | output | TCELL9:OUT13.TMIN |
| LLKRXDATA44 | output | TCELL9:OUT14.TMIN |
| LLKRXDATA45 | output | TCELL9:OUT15.TMIN |
| LLKRXDATA46 | output | TCELL14:OUT12.TMIN |
| LLKRXDATA47 | output | TCELL14:OUT13.TMIN |
| LLKRXDATA48 | output | TCELL14:OUT14.TMIN |
| LLKRXDATA49 | output | TCELL15:OUT11.TMIN |
| LLKRXDATA5 | output | TCELL1:OUT7.TMIN |
| LLKRXDATA50 | output | TCELL15:OUT12.TMIN |
| LLKRXDATA51 | output | TCELL15:OUT13.TMIN |
| LLKRXDATA52 | output | TCELL15:OUT14.TMIN |
| LLKRXDATA53 | output | TCELL15:OUT15.TMIN |
| LLKRXDATA54 | output | TCELL15:OUT16.TMIN |
| LLKRXDATA55 | output | TCELL15:OUT17.TMIN |
| LLKRXDATA56 | output | TCELL9:OUT16.TMIN |
| LLKRXDATA57 | output | TCELL9:OUT17.TMIN |
| LLKRXDATA58 | output | TCELL9:OUT18.TMIN |
| LLKRXDATA59 | output | TCELL8:OUT16.TMIN |
| LLKRXDATA6 | output | TCELL0:OUT4.TMIN |
| LLKRXDATA60 | output | TCELL8:OUT17.TMIN |
| LLKRXDATA61 | output | TCELL8:OUT18.TMIN |
| LLKRXDATA62 | output | TCELL7:OUT16.TMIN |
| LLKRXDATA63 | output | TCELL7:OUT17.TMIN |
| LLKRXDATA7 | output | TCELL0:OUT5.TMIN |
| LLKRXDATA8 | output | TCELL0:OUT6.TMIN |
| LLKRXDATA9 | output | TCELL0:OUT7.TMIN |
| LLKRXDSTCONTREQN | input | TCELL5:IMUX.IMUX14.DELAY |
| LLKRXDSTREQN | input | TCELL4:IMUX.IMUX8.DELAY |
| LLKRXECRCBADN | output | TCELL4:OUT23.TMIN |
| LLKRXEOFN | output | TCELL5:OUT12.TMIN |
| LLKRXEOPN | output | TCELL5:OUT14.TMIN |
| LLKRXPREFERREDTYPE0 | output | TCELL4:OUT9.TMIN |
| LLKRXPREFERREDTYPE1 | output | TCELL4:OUT10.TMIN |
| LLKRXPREFERREDTYPE10 | output | TCELL2:OUT15.TMIN |
| LLKRXPREFERREDTYPE11 | output | TCELL1:OUT12.TMIN |
| LLKRXPREFERREDTYPE12 | output | TCELL1:OUT13.TMIN |
| LLKRXPREFERREDTYPE13 | output | TCELL1:OUT14.TMIN |
| LLKRXPREFERREDTYPE14 | output | TCELL1:OUT15.TMIN |
| LLKRXPREFERREDTYPE15 | output | TCELL0:OUT8.TMIN |
| LLKRXPREFERREDTYPE2 | output | TCELL4:OUT11.TMIN |
| LLKRXPREFERREDTYPE3 | output | TCELL3:OUT12.TMIN |
| LLKRXPREFERREDTYPE4 | output | TCELL3:OUT13.TMIN |
| LLKRXPREFERREDTYPE5 | output | TCELL3:OUT14.TMIN |
| LLKRXPREFERREDTYPE6 | output | TCELL3:OUT15.TMIN |
| LLKRXPREFERREDTYPE7 | output | TCELL2:OUT12.TMIN |
| LLKRXPREFERREDTYPE8 | output | TCELL2:OUT13.TMIN |
| LLKRXPREFERREDTYPE9 | output | TCELL2:OUT14.TMIN |
| LLKRXSOFN | output | TCELL6:OUT18.TMIN |
| LLKRXSOPN | output | TCELL5:OUT13.TMIN |
| LLKRXSRCDSCN | output | TCELL6:OUT17.TMIN |
| LLKRXSRCLASTREQN | output | TCELL6:OUT16.TMIN |
| LLKRXSRCRDYN | output | TCELL7:OUT18.TMIN |
| LLKRXVALIDN0 | output | TCELL5:OUT15.TMIN |
| LLKRXVALIDN1 | output | TCELL4:OUT8.TMIN |
| LLKTCSTATUS0 | output | TCELL18:OUT12.TMIN |
| LLKTCSTATUS1 | output | TCELL18:OUT13.TMIN |
| LLKTCSTATUS2 | output | TCELL18:OUT14.TMIN |
| LLKTCSTATUS3 | output | TCELL17:OUT12.TMIN |
| LLKTCSTATUS4 | output | TCELL17:OUT13.TMIN |
| LLKTCSTATUS5 | output | TCELL17:OUT14.TMIN |
| LLKTCSTATUS6 | output | TCELL16:OUT12.TMIN |
| LLKTCSTATUS7 | output | TCELL16:OUT13.TMIN |
| LLKTX4DWHEADERN | input | TCELL3:IMUX.IMUX11.DELAY |
| LLKTXCHANSPACE0 | output | TCELL15:OUT7.TMIN |
| LLKTXCHANSPACE1 | output | TCELL15:OUT8.TMIN |
| LLKTXCHANSPACE2 | output | TCELL15:OUT9.TMIN |
| LLKTXCHANSPACE3 | output | TCELL15:OUT10.TMIN |
| LLKTXCHANSPACE4 | output | TCELL14:OUT8.TMIN |
| LLKTXCHANSPACE5 | output | TCELL14:OUT9.TMIN |
| LLKTXCHANSPACE6 | output | TCELL14:OUT10.TMIN |
| LLKTXCHANSPACE7 | output | TCELL14:OUT11.TMIN |
| LLKTXCHANSPACE8 | output | TCELL9:OUT10.TMIN |
| LLKTXCHANSPACE9 | output | TCELL9:OUT11.TMIN |
| LLKTXCHCOMPLETIONREADYN0 | output | TCELL4:OUT1.TMIN |
| LLKTXCHCOMPLETIONREADYN1 | output | TCELL4:OUT2.TMIN |
| LLKTXCHCOMPLETIONREADYN2 | output | TCELL4:OUT3.TMIN |
| LLKTXCHCOMPLETIONREADYN3 | output | TCELL3:OUT4.TMIN |
| LLKTXCHCOMPLETIONREADYN4 | output | TCELL3:OUT5.TMIN |
| LLKTXCHCOMPLETIONREADYN5 | output | TCELL3:OUT6.TMIN |
| LLKTXCHCOMPLETIONREADYN6 | output | TCELL3:OUT7.TMIN |
| LLKTXCHCOMPLETIONREADYN7 | output | TCELL2:OUT4.TMIN |
| LLKTXCHFIFO0 | input | TCELL3:IMUX.IMUX8.DELAY |
| LLKTXCHFIFO1 | input | TCELL3:IMUX.IMUX9.DELAY |
| LLKTXCHNONPOSTEDREADYN0 | output | TCELL6:OUT8.TMIN |
| LLKTXCHNONPOSTEDREADYN1 | output | TCELL6:OUT9.TMIN |
| LLKTXCHNONPOSTEDREADYN2 | output | TCELL6:OUT10.TMIN |
| LLKTXCHNONPOSTEDREADYN3 | output | TCELL6:OUT11.TMIN |
| LLKTXCHNONPOSTEDREADYN4 | output | TCELL5:OUT4.TMIN |
| LLKTXCHNONPOSTEDREADYN5 | output | TCELL5:OUT5.TMIN |
| LLKTXCHNONPOSTEDREADYN6 | output | TCELL5:OUT6.TMIN |
| LLKTXCHNONPOSTEDREADYN7 | output | TCELL5:OUT7.TMIN |
| LLKTXCHPOSTEDREADYN0 | output | TCELL8:OUT8.TMIN |
| LLKTXCHPOSTEDREADYN1 | output | TCELL8:OUT9.TMIN |
| LLKTXCHPOSTEDREADYN2 | output | TCELL8:OUT10.TMIN |
| LLKTXCHPOSTEDREADYN3 | output | TCELL8:OUT11.TMIN |
| LLKTXCHPOSTEDREADYN4 | output | TCELL7:OUT8.TMIN |
| LLKTXCHPOSTEDREADYN5 | output | TCELL7:OUT9.TMIN |
| LLKTXCHPOSTEDREADYN6 | output | TCELL7:OUT10.TMIN |
| LLKTXCHPOSTEDREADYN7 | output | TCELL7:OUT11.TMIN |
| LLKTXCHTC0 | input | TCELL2:IMUX.IMUX5.DELAY |
| LLKTXCHTC1 | input | TCELL2:IMUX.IMUX6.DELAY |
| LLKTXCHTC2 | input | TCELL2:IMUX.IMUX7.DELAY |
| LLKTXCOMPLETEN | input | TCELL0:IMUX.IMUX2.DELAY |
| LLKTXCONFIGREADYN | output | TCELL2:OUT5.TMIN |
| LLKTXCREATEECRCN | input | TCELL3:IMUX.IMUX10.DELAY |
| LLKTXDATA0 | input | TCELL19:IMUX.IMUX10.DELAY |
| LLKTXDATA1 | input | TCELL19:IMUX.IMUX11.DELAY |
| LLKTXDATA10 | input | TCELL15:IMUX.IMUX4.DELAY |
| LLKTXDATA11 | input | TCELL15:IMUX.IMUX5.DELAY |
| LLKTXDATA12 | input | TCELL15:IMUX.IMUX6.DELAY |
| LLKTXDATA13 | input | TCELL15:IMUX.IMUX7.DELAY |
| LLKTXDATA14 | input | TCELL14:IMUX.IMUX4.DELAY |
| LLKTXDATA15 | input | TCELL14:IMUX.IMUX5.DELAY |
| LLKTXDATA16 | input | TCELL14:IMUX.IMUX6.DELAY |
| LLKTXDATA17 | input | TCELL14:IMUX.IMUX7.DELAY |
| LLKTXDATA18 | input | TCELL12:IMUX.IMUX8.DELAY |
| LLKTXDATA19 | input | TCELL12:IMUX.IMUX9.DELAY |
| LLKTXDATA2 | input | TCELL17:IMUX.IMUX4.DELAY |
| LLKTXDATA20 | input | TCELL12:IMUX.IMUX10.DELAY |
| LLKTXDATA21 | input | TCELL12:IMUX.IMUX11.DELAY |
| LLKTXDATA22 | input | TCELL11:IMUX.IMUX8.DELAY |
| LLKTXDATA23 | input | TCELL11:IMUX.IMUX9.DELAY |
| LLKTXDATA24 | input | TCELL11:IMUX.IMUX10.DELAY |
| LLKTXDATA25 | input | TCELL11:IMUX.IMUX11.DELAY |
| LLKTXDATA26 | input | TCELL10:IMUX.IMUX9.DELAY |
| LLKTXDATA27 | input | TCELL10:IMUX.IMUX10.DELAY |
| LLKTXDATA28 | input | TCELL10:IMUX.IMUX11.DELAY |
| LLKTXDATA29 | input | TCELL9:IMUX.IMUX12.DELAY |
| LLKTXDATA3 | input | TCELL17:IMUX.IMUX5.DELAY |
| LLKTXDATA30 | input | TCELL9:IMUX.IMUX13.DELAY |
| LLKTXDATA31 | input | TCELL9:IMUX.IMUX14.DELAY |
| LLKTXDATA32 | input | TCELL8:IMUX.IMUX8.DELAY |
| LLKTXDATA33 | input | TCELL8:IMUX.IMUX9.DELAY |
| LLKTXDATA34 | input | TCELL8:IMUX.IMUX10.DELAY |
| LLKTXDATA35 | input | TCELL8:IMUX.IMUX11.DELAY |
| LLKTXDATA36 | input | TCELL7:IMUX.IMUX8.DELAY |
| LLKTXDATA37 | input | TCELL7:IMUX.IMUX9.DELAY |
| LLKTXDATA38 | input | TCELL7:IMUX.IMUX10.DELAY |
| LLKTXDATA39 | input | TCELL7:IMUX.IMUX11.DELAY |
| LLKTXDATA4 | input | TCELL17:IMUX.IMUX6.DELAY |
| LLKTXDATA40 | input | TCELL6:IMUX.IMUX8.DELAY |
| LLKTXDATA41 | input | TCELL6:IMUX.IMUX9.DELAY |
| LLKTXDATA42 | input | TCELL6:IMUX.IMUX10.DELAY |
| LLKTXDATA43 | input | TCELL6:IMUX.IMUX11.DELAY |
| LLKTXDATA44 | input | TCELL5:IMUX.IMUX8.DELAY |
| LLKTXDATA45 | input | TCELL5:IMUX.IMUX9.DELAY |
| LLKTXDATA46 | input | TCELL5:IMUX.IMUX10.DELAY |
| LLKTXDATA47 | input | TCELL5:IMUX.IMUX11.DELAY |
| LLKTXDATA48 | input | TCELL4:IMUX.IMUX4.DELAY |
| LLKTXDATA49 | input | TCELL4:IMUX.IMUX5.DELAY |
| LLKTXDATA5 | input | TCELL17:IMUX.IMUX7.DELAY |
| LLKTXDATA50 | input | TCELL4:IMUX.IMUX6.DELAY |
| LLKTXDATA51 | input | TCELL4:IMUX.IMUX7.DELAY |
| LLKTXDATA52 | input | TCELL3:IMUX.IMUX4.DELAY |
| LLKTXDATA53 | input | TCELL3:IMUX.IMUX5.DELAY |
| LLKTXDATA54 | input | TCELL3:IMUX.IMUX6.DELAY |
| LLKTXDATA55 | input | TCELL3:IMUX.IMUX7.DELAY |
| LLKTXDATA56 | input | TCELL2:IMUX.IMUX0.DELAY |
| LLKTXDATA57 | input | TCELL2:IMUX.IMUX1.DELAY |
| LLKTXDATA58 | input | TCELL2:IMUX.IMUX2.DELAY |
| LLKTXDATA59 | input | TCELL2:IMUX.IMUX3.DELAY |
| LLKTXDATA6 | input | TCELL16:IMUX.IMUX4.DELAY |
| LLKTXDATA60 | input | TCELL1:IMUX.IMUX0.DELAY |
| LLKTXDATA61 | input | TCELL1:IMUX.IMUX1.DELAY |
| LLKTXDATA62 | input | TCELL1:IMUX.IMUX2.DELAY |
| LLKTXDATA63 | input | TCELL1:IMUX.IMUX3.DELAY |
| LLKTXDATA7 | input | TCELL16:IMUX.IMUX5.DELAY |
| LLKTXDATA8 | input | TCELL16:IMUX.IMUX6.DELAY |
| LLKTXDATA9 | input | TCELL16:IMUX.IMUX7.DELAY |
| LLKTXDSTRDYN | output | TCELL16:OUT14.TMIN |
| LLKTXENABLEN0 | input | TCELL1:IMUX.IMUX7.DELAY |
| LLKTXENABLEN1 | input | TCELL2:IMUX.IMUX4.DELAY |
| LLKTXEOFN | input | TCELL1:IMUX.IMUX4.DELAY |
| LLKTXEOPN | input | TCELL1:IMUX.IMUX6.DELAY |
| LLKTXSOFN | input | TCELL0:IMUX.IMUX3.DELAY |
| LLKTXSOPN | input | TCELL1:IMUX.IMUX5.DELAY |
| LLKTXSRCDSCN | input | TCELL0:IMUX.IMUX1.DELAY |
| LLKTXSRCRDYN | input | TCELL0:IMUX.IMUX0.DELAY |
| MAINPOWER | input | TCELL39:IMUX.IMUX4.DELAY |
| MAXPAYLOADSIZE0 | output | TCELL23:OUT19.TMIN |
| MAXPAYLOADSIZE1 | output | TCELL24:OUT8.TMIN |
| MAXPAYLOADSIZE2 | output | TCELL24:OUT9.TMIN |
| MAXREADREQUESTSIZE0 | output | TCELL24:OUT10.TMIN |
| MAXREADREQUESTSIZE1 | output | TCELL24:OUT11.TMIN |
| MAXREADREQUESTSIZE2 | output | TCELL25:OUT16.TMIN |
| MEMSPACEENABLE | output | TCELL25:OUT18.TMIN |
| MGMTADDR0 | input | TCELL36:IMUX.IMUX1.DELAY |
| MGMTADDR1 | input | TCELL36:IMUX.IMUX2.DELAY |
| MGMTADDR10 | input | TCELL38:IMUX.IMUX3.DELAY |
| MGMTADDR2 | input | TCELL36:IMUX.IMUX3.DELAY |
| MGMTADDR3 | input | TCELL37:IMUX.IMUX0.DELAY |
| MGMTADDR4 | input | TCELL37:IMUX.IMUX1.DELAY |
| MGMTADDR5 | input | TCELL37:IMUX.IMUX2.DELAY |
| MGMTADDR6 | input | TCELL37:IMUX.IMUX3.DELAY |
| MGMTADDR7 | input | TCELL38:IMUX.IMUX0.DELAY |
| MGMTADDR8 | input | TCELL38:IMUX.IMUX1.DELAY |
| MGMTADDR9 | input | TCELL38:IMUX.IMUX2.DELAY |
| MGMTBWREN0 | input | TCELL35:IMUX.IMUX0.DELAY |
| MGMTBWREN1 | input | TCELL35:IMUX.IMUX1.DELAY |
| MGMTBWREN2 | input | TCELL35:IMUX.IMUX2.DELAY |
| MGMTBWREN3 | input | TCELL35:IMUX.IMUX3.DELAY |
| MGMTPSO0 | output | TCELL34:OUT6.TMIN |
| MGMTPSO1 | output | TCELL34:OUT7.TMIN |
| MGMTPSO10 | output | TCELL37:OUT1.TMIN |
| MGMTPSO11 | output | TCELL37:OUT2.TMIN |
| MGMTPSO12 | output | TCELL37:OUT3.TMIN |
| MGMTPSO13 | output | TCELL38:OUT0.TMIN |
| MGMTPSO14 | output | TCELL38:OUT1.TMIN |
| MGMTPSO15 | output | TCELL38:OUT2.TMIN |
| MGMTPSO16 | output | TCELL38:OUT3.TMIN |
| MGMTPSO2 | output | TCELL35:OUT0.TMIN |
| MGMTPSO3 | output | TCELL35:OUT1.TMIN |
| MGMTPSO4 | output | TCELL35:OUT2.TMIN |
| MGMTPSO5 | output | TCELL36:OUT0.TMIN |
| MGMTPSO6 | output | TCELL36:OUT1.TMIN |
| MGMTPSO7 | output | TCELL36:OUT2.TMIN |
| MGMTPSO8 | output | TCELL36:OUT3.TMIN |
| MGMTPSO9 | output | TCELL37:OUT0.TMIN |
| MGMTRDATA0 | output | TCELL25:OUT8.TMIN |
| MGMTRDATA1 | output | TCELL25:OUT9.TMIN |
| MGMTRDATA10 | output | TCELL27:OUT14.TMIN |
| MGMTRDATA11 | output | TCELL27:OUT15.TMIN |
| MGMTRDATA12 | output | TCELL28:OUT12.TMIN |
| MGMTRDATA13 | output | TCELL28:OUT13.TMIN |
| MGMTRDATA14 | output | TCELL28:OUT14.TMIN |
| MGMTRDATA15 | output | TCELL28:OUT15.TMIN |
| MGMTRDATA16 | output | TCELL29:OUT12.TMIN |
| MGMTRDATA17 | output | TCELL29:OUT13.TMIN |
| MGMTRDATA18 | output | TCELL29:OUT14.TMIN |
| MGMTRDATA19 | output | TCELL29:OUT15.TMIN |
| MGMTRDATA2 | output | TCELL25:OUT10.TMIN |
| MGMTRDATA20 | output | TCELL30:OUT12.TMIN |
| MGMTRDATA21 | output | TCELL30:OUT13.TMIN |
| MGMTRDATA22 | output | TCELL30:OUT14.TMIN |
| MGMTRDATA23 | output | TCELL32:OUT12.TMIN |
| MGMTRDATA24 | output | TCELL32:OUT13.TMIN |
| MGMTRDATA25 | output | TCELL32:OUT14.TMIN |
| MGMTRDATA26 | output | TCELL33:OUT8.TMIN |
| MGMTRDATA27 | output | TCELL33:OUT9.TMIN |
| MGMTRDATA28 | output | TCELL33:OUT10.TMIN |
| MGMTRDATA29 | output | TCELL33:OUT11.TMIN |
| MGMTRDATA3 | output | TCELL25:OUT11.TMIN |
| MGMTRDATA30 | output | TCELL34:OUT4.TMIN |
| MGMTRDATA31 | output | TCELL34:OUT5.TMIN |
| MGMTRDATA4 | output | TCELL26:OUT12.TMIN |
| MGMTRDATA5 | output | TCELL26:OUT13.TMIN |
| MGMTRDATA6 | output | TCELL26:OUT14.TMIN |
| MGMTRDATA7 | output | TCELL26:OUT15.TMIN |
| MGMTRDATA8 | output | TCELL27:OUT12.TMIN |
| MGMTRDATA9 | output | TCELL27:OUT13.TMIN |
| MGMTRDEN | input | TCELL39:IMUX.IMUX0.DELAY |
| MGMTSTATSCREDIT0 | output | TCELL39:OUT0.TMIN |
| MGMTSTATSCREDIT1 | output | TCELL39:OUT1.TMIN |
| MGMTSTATSCREDIT10 | output | TCELL37:OUT6.TMIN |
| MGMTSTATSCREDIT11 | output | TCELL37:OUT7.TMIN |
| MGMTSTATSCREDIT2 | output | TCELL39:OUT2.TMIN |
| MGMTSTATSCREDIT3 | output | TCELL39:OUT3.TMIN |
| MGMTSTATSCREDIT4 | output | TCELL38:OUT4.TMIN |
| MGMTSTATSCREDIT5 | output | TCELL38:OUT5.TMIN |
| MGMTSTATSCREDIT6 | output | TCELL38:OUT6.TMIN |
| MGMTSTATSCREDIT7 | output | TCELL38:OUT7.TMIN |
| MGMTSTATSCREDIT8 | output | TCELL37:OUT4.TMIN |
| MGMTSTATSCREDIT9 | output | TCELL37:OUT5.TMIN |
| MGMTSTATSCREDITSEL0 | input | TCELL39:IMUX.IMUX1.DELAY |
| MGMTSTATSCREDITSEL1 | input | TCELL39:IMUX.IMUX2.DELAY |
| MGMTSTATSCREDITSEL2 | input | TCELL39:IMUX.IMUX3.DELAY |
| MGMTSTATSCREDITSEL3 | input | TCELL38:IMUX.IMUX4.DELAY |
| MGMTSTATSCREDITSEL4 | input | TCELL38:IMUX.IMUX5.DELAY |
| MGMTSTATSCREDITSEL5 | input | TCELL38:IMUX.IMUX6.DELAY |
| MGMTSTATSCREDITSEL6 | input | TCELL38:IMUX.IMUX7.DELAY |
| MGMTWDATA0 | input | TCELL25:IMUX.IMUX8.DELAY |
| MGMTWDATA1 | input | TCELL25:IMUX.IMUX9.DELAY |
| MGMTWDATA10 | input | TCELL27:IMUX.IMUX7.DELAY |
| MGMTWDATA11 | input | TCELL28:IMUX.IMUX8.DELAY |
| MGMTWDATA12 | input | TCELL28:IMUX.IMUX9.DELAY |
| MGMTWDATA13 | input | TCELL28:IMUX.IMUX10.DELAY |
| MGMTWDATA14 | input | TCELL28:IMUX.IMUX11.DELAY |
| MGMTWDATA15 | input | TCELL29:IMUX.IMUX12.DELAY |
| MGMTWDATA16 | input | TCELL29:IMUX.IMUX13.DELAY |
| MGMTWDATA17 | input | TCELL29:IMUX.IMUX14.DELAY |
| MGMTWDATA18 | input | TCELL30:IMUX.IMUX12.DELAY |
| MGMTWDATA19 | input | TCELL30:IMUX.IMUX13.DELAY |
| MGMTWDATA2 | input | TCELL25:IMUX.IMUX10.DELAY |
| MGMTWDATA20 | input | TCELL30:IMUX.IMUX14.DELAY |
| MGMTWDATA21 | input | TCELL31:IMUX.IMUX12.DELAY |
| MGMTWDATA22 | input | TCELL31:IMUX.IMUX13.DELAY |
| MGMTWDATA23 | input | TCELL31:IMUX.IMUX14.DELAY |
| MGMTWDATA24 | input | TCELL32:IMUX.IMUX8.DELAY |
| MGMTWDATA25 | input | TCELL32:IMUX.IMUX9.DELAY |
| MGMTWDATA26 | input | TCELL32:IMUX.IMUX10.DELAY |
| MGMTWDATA27 | input | TCELL32:IMUX.IMUX11.DELAY |
| MGMTWDATA28 | input | TCELL34:IMUX.IMUX4.DELAY |
| MGMTWDATA29 | input | TCELL34:IMUX.IMUX5.DELAY |
| MGMTWDATA3 | input | TCELL25:IMUX.IMUX11.DELAY |
| MGMTWDATA30 | input | TCELL34:IMUX.IMUX6.DELAY |
| MGMTWDATA31 | input | TCELL34:IMUX.IMUX7.DELAY |
| MGMTWDATA4 | input | TCELL26:IMUX.IMUX4.DELAY |
| MGMTWDATA5 | input | TCELL26:IMUX.IMUX5.DELAY |
| MGMTWDATA6 | input | TCELL26:IMUX.IMUX6.DELAY |
| MGMTWDATA7 | input | TCELL26:IMUX.IMUX7.DELAY |
| MGMTWDATA8 | input | TCELL27:IMUX.IMUX5.DELAY |
| MGMTWDATA9 | input | TCELL27:IMUX.IMUX6.DELAY |
| MGMTWREN | input | TCELL36:IMUX.IMUX0.DELAY |
| MIMDLLBRADD0 | output | TCELL26:OUT11.TMIN |
| MIMDLLBRADD1 | output | TCELL27:OUT8.TMIN |
| MIMDLLBRADD10 | output | TCELL29:OUT9.TMIN |
| MIMDLLBRADD11 | output | TCELL29:OUT10.TMIN |
| MIMDLLBRADD2 | output | TCELL27:OUT9.TMIN |
| MIMDLLBRADD3 | output | TCELL27:OUT10.TMIN |
| MIMDLLBRADD4 | output | TCELL27:OUT11.TMIN |
| MIMDLLBRADD5 | output | TCELL28:OUT8.TMIN |
| MIMDLLBRADD6 | output | TCELL28:OUT9.TMIN |
| MIMDLLBRADD7 | output | TCELL28:OUT10.TMIN |
| MIMDLLBRADD8 | output | TCELL28:OUT11.TMIN |
| MIMDLLBRADD9 | output | TCELL29:OUT8.TMIN |
| MIMDLLBRDATA0 | input | TCELL25:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA1 | input | TCELL25:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA10 | input | TCELL28:IMUX.IMUX2.DELAY |
| MIMDLLBRDATA11 | input | TCELL28:IMUX.IMUX3.DELAY |
| MIMDLLBRDATA12 | input | TCELL29:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA13 | input | TCELL29:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA14 | input | TCELL29:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA15 | input | TCELL29:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA16 | input | TCELL30:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA17 | input | TCELL30:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA18 | input | TCELL30:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA19 | input | TCELL30:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA2 | input | TCELL25:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA20 | input | TCELL31:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA21 | input | TCELL31:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA22 | input | TCELL31:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA23 | input | TCELL31:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA24 | input | TCELL33:IMUX.IMUX0.DELAY |
| MIMDLLBRDATA25 | input | TCELL33:IMUX.IMUX1.DELAY |
| MIMDLLBRDATA26 | input | TCELL33:IMUX.IMUX2.DELAY |
| MIMDLLBRDATA27 | input | TCELL33:IMUX.IMUX3.DELAY |
| MIMDLLBRDATA28 | input | TCELL33:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA29 | input | TCELL33:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA3 | input | TCELL25:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA30 | input | TCELL33:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA31 | input | TCELL33:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA32 | input | TCELL33:IMUX.IMUX8.DELAY |
| MIMDLLBRDATA33 | input | TCELL33:IMUX.IMUX9.DELAY |
| MIMDLLBRDATA34 | input | TCELL33:IMUX.IMUX10.DELAY |
| MIMDLLBRDATA35 | input | TCELL33:IMUX.IMUX11.DELAY |
| MIMDLLBRDATA36 | input | TCELL33:IMUX.IMUX12.DELAY |
| MIMDLLBRDATA37 | input | TCELL33:IMUX.IMUX13.DELAY |
| MIMDLLBRDATA38 | input | TCELL33:IMUX.IMUX14.DELAY |
| MIMDLLBRDATA39 | input | TCELL34:IMUX.IMUX0.DELAY |
| MIMDLLBRDATA4 | input | TCELL27:IMUX.IMUX0.DELAY |
| MIMDLLBRDATA40 | input | TCELL34:IMUX.IMUX1.DELAY |
| MIMDLLBRDATA41 | input | TCELL34:IMUX.IMUX2.DELAY |
| MIMDLLBRDATA42 | input | TCELL34:IMUX.IMUX3.DELAY |
| MIMDLLBRDATA43 | input | TCELL32:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA44 | input | TCELL32:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA45 | input | TCELL32:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA46 | input | TCELL32:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA47 | input | TCELL31:IMUX.IMUX8.DELAY |
| MIMDLLBRDATA48 | input | TCELL31:IMUX.IMUX9.DELAY |
| MIMDLLBRDATA49 | input | TCELL31:IMUX.IMUX10.DELAY |
| MIMDLLBRDATA5 | input | TCELL27:IMUX.IMUX1.DELAY |
| MIMDLLBRDATA50 | input | TCELL31:IMUX.IMUX11.DELAY |
| MIMDLLBRDATA51 | input | TCELL30:IMUX.IMUX8.DELAY |
| MIMDLLBRDATA52 | input | TCELL30:IMUX.IMUX9.DELAY |
| MIMDLLBRDATA53 | input | TCELL30:IMUX.IMUX10.DELAY |
| MIMDLLBRDATA54 | input | TCELL30:IMUX.IMUX11.DELAY |
| MIMDLLBRDATA55 | input | TCELL29:IMUX.IMUX8.DELAY |
| MIMDLLBRDATA56 | input | TCELL29:IMUX.IMUX9.DELAY |
| MIMDLLBRDATA57 | input | TCELL29:IMUX.IMUX10.DELAY |
| MIMDLLBRDATA58 | input | TCELL29:IMUX.IMUX11.DELAY |
| MIMDLLBRDATA59 | input | TCELL28:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA6 | input | TCELL27:IMUX.IMUX2.DELAY |
| MIMDLLBRDATA60 | input | TCELL28:IMUX.IMUX5.DELAY |
| MIMDLLBRDATA61 | input | TCELL28:IMUX.IMUX6.DELAY |
| MIMDLLBRDATA62 | input | TCELL28:IMUX.IMUX7.DELAY |
| MIMDLLBRDATA63 | input | TCELL27:IMUX.IMUX4.DELAY |
| MIMDLLBRDATA7 | input | TCELL27:IMUX.IMUX3.DELAY |
| MIMDLLBRDATA8 | input | TCELL28:IMUX.IMUX0.DELAY |
| MIMDLLBRDATA9 | input | TCELL28:IMUX.IMUX1.DELAY |
| MIMDLLBREN | output | TCELL30:OUT11.TMIN |
| MIMDLLBWADD0 | output | TCELL27:OUT7.TMIN |
| MIMDLLBWADD1 | output | TCELL26:OUT4.TMIN |
| MIMDLLBWADD10 | output | TCELL26:OUT9.TMIN |
| MIMDLLBWADD11 | output | TCELL26:OUT10.TMIN |
| MIMDLLBWADD2 | output | TCELL26:OUT5.TMIN |
| MIMDLLBWADD3 | output | TCELL26:OUT6.TMIN |
| MIMDLLBWADD4 | output | TCELL26:OUT7.TMIN |
| MIMDLLBWADD5 | output | TCELL25:OUT4.TMIN |
| MIMDLLBWADD6 | output | TCELL25:OUT5.TMIN |
| MIMDLLBWADD7 | output | TCELL25:OUT6.TMIN |
| MIMDLLBWADD8 | output | TCELL25:OUT7.TMIN |
| MIMDLLBWADD9 | output | TCELL26:OUT8.TMIN |
| MIMDLLBWDATA0 | output | TCELL25:OUT0.TMIN |
| MIMDLLBWDATA1 | output | TCELL25:OUT1.TMIN |
| MIMDLLBWDATA10 | output | TCELL27:OUT2.TMIN |
| MIMDLLBWDATA11 | output | TCELL27:OUT3.TMIN |
| MIMDLLBWDATA12 | output | TCELL28:OUT0.TMIN |
| MIMDLLBWDATA13 | output | TCELL28:OUT1.TMIN |
| MIMDLLBWDATA14 | output | TCELL28:OUT2.TMIN |
| MIMDLLBWDATA15 | output | TCELL28:OUT3.TMIN |
| MIMDLLBWDATA16 | output | TCELL29:OUT0.TMIN |
| MIMDLLBWDATA17 | output | TCELL29:OUT1.TMIN |
| MIMDLLBWDATA18 | output | TCELL29:OUT2.TMIN |
| MIMDLLBWDATA19 | output | TCELL29:OUT3.TMIN |
| MIMDLLBWDATA2 | output | TCELL25:OUT2.TMIN |
| MIMDLLBWDATA20 | output | TCELL30:OUT5.TMIN |
| MIMDLLBWDATA21 | output | TCELL30:OUT6.TMIN |
| MIMDLLBWDATA22 | output | TCELL31:OUT8.TMIN |
| MIMDLLBWDATA23 | output | TCELL31:OUT9.TMIN |
| MIMDLLBWDATA24 | output | TCELL31:OUT10.TMIN |
| MIMDLLBWDATA25 | output | TCELL31:OUT11.TMIN |
| MIMDLLBWDATA26 | output | TCELL32:OUT4.TMIN |
| MIMDLLBWDATA27 | output | TCELL32:OUT5.TMIN |
| MIMDLLBWDATA28 | output | TCELL32:OUT6.TMIN |
| MIMDLLBWDATA29 | output | TCELL32:OUT7.TMIN |
| MIMDLLBWDATA3 | output | TCELL25:OUT3.TMIN |
| MIMDLLBWDATA30 | output | TCELL33:OUT0.TMIN |
| MIMDLLBWDATA31 | output | TCELL33:OUT1.TMIN |
| MIMDLLBWDATA32 | output | TCELL33:OUT2.TMIN |
| MIMDLLBWDATA33 | output | TCELL33:OUT3.TMIN |
| MIMDLLBWDATA34 | output | TCELL34:OUT0.TMIN |
| MIMDLLBWDATA35 | output | TCELL34:OUT1.TMIN |
| MIMDLLBWDATA36 | output | TCELL34:OUT2.TMIN |
| MIMDLLBWDATA37 | output | TCELL34:OUT3.TMIN |
| MIMDLLBWDATA38 | output | TCELL33:OUT4.TMIN |
| MIMDLLBWDATA39 | output | TCELL33:OUT5.TMIN |
| MIMDLLBWDATA4 | output | TCELL26:OUT0.TMIN |
| MIMDLLBWDATA40 | output | TCELL33:OUT6.TMIN |
| MIMDLLBWDATA41 | output | TCELL33:OUT7.TMIN |
| MIMDLLBWDATA42 | output | TCELL32:OUT8.TMIN |
| MIMDLLBWDATA43 | output | TCELL32:OUT9.TMIN |
| MIMDLLBWDATA44 | output | TCELL32:OUT10.TMIN |
| MIMDLLBWDATA45 | output | TCELL32:OUT11.TMIN |
| MIMDLLBWDATA46 | output | TCELL31:OUT12.TMIN |
| MIMDLLBWDATA47 | output | TCELL31:OUT13.TMIN |
| MIMDLLBWDATA48 | output | TCELL31:OUT14.TMIN |
| MIMDLLBWDATA49 | output | TCELL30:OUT7.TMIN |
| MIMDLLBWDATA5 | output | TCELL26:OUT1.TMIN |
| MIMDLLBWDATA50 | output | TCELL30:OUT8.TMIN |
| MIMDLLBWDATA51 | output | TCELL30:OUT9.TMIN |
| MIMDLLBWDATA52 | output | TCELL30:OUT10.TMIN |
| MIMDLLBWDATA53 | output | TCELL29:OUT4.TMIN |
| MIMDLLBWDATA54 | output | TCELL29:OUT5.TMIN |
| MIMDLLBWDATA55 | output | TCELL29:OUT6.TMIN |
| MIMDLLBWDATA56 | output | TCELL29:OUT7.TMIN |
| MIMDLLBWDATA57 | output | TCELL28:OUT4.TMIN |
| MIMDLLBWDATA58 | output | TCELL28:OUT5.TMIN |
| MIMDLLBWDATA59 | output | TCELL28:OUT6.TMIN |
| MIMDLLBWDATA6 | output | TCELL26:OUT2.TMIN |
| MIMDLLBWDATA60 | output | TCELL28:OUT7.TMIN |
| MIMDLLBWDATA61 | output | TCELL27:OUT4.TMIN |
| MIMDLLBWDATA62 | output | TCELL27:OUT5.TMIN |
| MIMDLLBWDATA63 | output | TCELL27:OUT6.TMIN |
| MIMDLLBWDATA7 | output | TCELL26:OUT3.TMIN |
| MIMDLLBWDATA8 | output | TCELL27:OUT0.TMIN |
| MIMDLLBWDATA9 | output | TCELL27:OUT1.TMIN |
| MIMDLLBWEN | output | TCELL29:OUT11.TMIN |
| MIMRXBRADD0 | output | TCELL13:OUT9.TMIN |
| MIMRXBRADD1 | output | TCELL13:OUT10.TMIN |
| MIMRXBRADD10 | output | TCELL10:OUT15.TMIN |
| MIMRXBRADD11 | output | TCELL10:OUT16.TMIN |
| MIMRXBRADD12 | output | TCELL10:OUT17.TMIN |
| MIMRXBRADD2 | output | TCELL13:OUT11.TMIN |
| MIMRXBRADD3 | output | TCELL14:OUT4.TMIN |
| MIMRXBRADD4 | output | TCELL14:OUT5.TMIN |
| MIMRXBRADD5 | output | TCELL14:OUT6.TMIN |
| MIMRXBRADD6 | output | TCELL14:OUT7.TMIN |
| MIMRXBRADD7 | output | TCELL13:OUT12.TMIN |
| MIMRXBRADD8 | output | TCELL13:OUT13.TMIN |
| MIMRXBRADD9 | output | TCELL13:OUT14.TMIN |
| MIMRXBRDATA0 | input | TCELL13:IMUX.IMUX0.DELAY |
| MIMRXBRDATA1 | input | TCELL13:IMUX.IMUX1.DELAY |
| MIMRXBRDATA10 | input | TCELL13:IMUX.IMUX10.DELAY |
| MIMRXBRDATA11 | input | TCELL13:IMUX.IMUX11.DELAY |
| MIMRXBRDATA12 | input | TCELL13:IMUX.IMUX12.DELAY |
| MIMRXBRDATA13 | input | TCELL13:IMUX.IMUX13.DELAY |
| MIMRXBRDATA14 | input | TCELL13:IMUX.IMUX14.DELAY |
| MIMRXBRDATA15 | input | TCELL14:IMUX.IMUX0.DELAY |
| MIMRXBRDATA16 | input | TCELL14:IMUX.IMUX1.DELAY |
| MIMRXBRDATA17 | input | TCELL14:IMUX.IMUX2.DELAY |
| MIMRXBRDATA18 | input | TCELL14:IMUX.IMUX3.DELAY |
| MIMRXBRDATA19 | input | TCELL12:IMUX.IMUX4.DELAY |
| MIMRXBRDATA2 | input | TCELL13:IMUX.IMUX2.DELAY |
| MIMRXBRDATA20 | input | TCELL12:IMUX.IMUX5.DELAY |
| MIMRXBRDATA21 | input | TCELL12:IMUX.IMUX6.DELAY |
| MIMRXBRDATA22 | input | TCELL12:IMUX.IMUX7.DELAY |
| MIMRXBRDATA23 | input | TCELL11:IMUX.IMUX4.DELAY |
| MIMRXBRDATA24 | input | TCELL11:IMUX.IMUX5.DELAY |
| MIMRXBRDATA25 | input | TCELL11:IMUX.IMUX6.DELAY |
| MIMRXBRDATA26 | input | TCELL11:IMUX.IMUX7.DELAY |
| MIMRXBRDATA27 | input | TCELL10:IMUX.IMUX4.DELAY |
| MIMRXBRDATA28 | input | TCELL10:IMUX.IMUX5.DELAY |
| MIMRXBRDATA29 | input | TCELL10:IMUX.IMUX6.DELAY |
| MIMRXBRDATA3 | input | TCELL13:IMUX.IMUX3.DELAY |
| MIMRXBRDATA30 | input | TCELL10:IMUX.IMUX7.DELAY |
| MIMRXBRDATA31 | input | TCELL9:IMUX.IMUX4.DELAY |
| MIMRXBRDATA32 | input | TCELL9:IMUX.IMUX5.DELAY |
| MIMRXBRDATA33 | input | TCELL9:IMUX.IMUX6.DELAY |
| MIMRXBRDATA34 | input | TCELL9:IMUX.IMUX7.DELAY |
| MIMRXBRDATA35 | input | TCELL8:IMUX.IMUX0.DELAY |
| MIMRXBRDATA36 | input | TCELL8:IMUX.IMUX1.DELAY |
| MIMRXBRDATA37 | input | TCELL8:IMUX.IMUX2.DELAY |
| MIMRXBRDATA38 | input | TCELL8:IMUX.IMUX3.DELAY |
| MIMRXBRDATA39 | input | TCELL7:IMUX.IMUX0.DELAY |
| MIMRXBRDATA4 | input | TCELL13:IMUX.IMUX4.DELAY |
| MIMRXBRDATA40 | input | TCELL7:IMUX.IMUX1.DELAY |
| MIMRXBRDATA41 | input | TCELL7:IMUX.IMUX2.DELAY |
| MIMRXBRDATA42 | input | TCELL7:IMUX.IMUX3.DELAY |
| MIMRXBRDATA43 | input | TCELL5:IMUX.IMUX4.DELAY |
| MIMRXBRDATA44 | input | TCELL5:IMUX.IMUX5.DELAY |
| MIMRXBRDATA45 | input | TCELL5:IMUX.IMUX6.DELAY |
| MIMRXBRDATA46 | input | TCELL5:IMUX.IMUX7.DELAY |
| MIMRXBRDATA47 | input | TCELL6:IMUX.IMUX4.DELAY |
| MIMRXBRDATA48 | input | TCELL6:IMUX.IMUX5.DELAY |
| MIMRXBRDATA49 | input | TCELL6:IMUX.IMUX6.DELAY |
| MIMRXBRDATA5 | input | TCELL13:IMUX.IMUX5.DELAY |
| MIMRXBRDATA50 | input | TCELL6:IMUX.IMUX7.DELAY |
| MIMRXBRDATA51 | input | TCELL7:IMUX.IMUX4.DELAY |
| MIMRXBRDATA52 | input | TCELL7:IMUX.IMUX5.DELAY |
| MIMRXBRDATA53 | input | TCELL7:IMUX.IMUX6.DELAY |
| MIMRXBRDATA54 | input | TCELL7:IMUX.IMUX7.DELAY |
| MIMRXBRDATA55 | input | TCELL8:IMUX.IMUX4.DELAY |
| MIMRXBRDATA56 | input | TCELL8:IMUX.IMUX5.DELAY |
| MIMRXBRDATA57 | input | TCELL8:IMUX.IMUX6.DELAY |
| MIMRXBRDATA58 | input | TCELL8:IMUX.IMUX7.DELAY |
| MIMRXBRDATA59 | input | TCELL9:IMUX.IMUX8.DELAY |
| MIMRXBRDATA6 | input | TCELL13:IMUX.IMUX6.DELAY |
| MIMRXBRDATA60 | input | TCELL9:IMUX.IMUX9.DELAY |
| MIMRXBRDATA61 | input | TCELL9:IMUX.IMUX10.DELAY |
| MIMRXBRDATA62 | input | TCELL9:IMUX.IMUX11.DELAY |
| MIMRXBRDATA63 | input | TCELL10:IMUX.IMUX8.DELAY |
| MIMRXBRDATA7 | input | TCELL13:IMUX.IMUX7.DELAY |
| MIMRXBRDATA8 | input | TCELL13:IMUX.IMUX8.DELAY |
| MIMRXBRDATA9 | input | TCELL13:IMUX.IMUX9.DELAY |
| MIMRXBREN | output | TCELL9:OUT9.TMIN |
| MIMRXBWADD0 | output | TCELL8:OUT7.TMIN |
| MIMRXBWADD1 | output | TCELL9:OUT4.TMIN |
| MIMRXBWADD10 | output | TCELL12:OUT13.TMIN |
| MIMRXBWADD11 | output | TCELL12:OUT14.TMIN |
| MIMRXBWADD12 | output | TCELL13:OUT8.TMIN |
| MIMRXBWADD2 | output | TCELL9:OUT5.TMIN |
| MIMRXBWADD3 | output | TCELL9:OUT6.TMIN |
| MIMRXBWADD4 | output | TCELL9:OUT7.TMIN |
| MIMRXBWADD5 | output | TCELL10:OUT11.TMIN |
| MIMRXBWADD6 | output | TCELL10:OUT12.TMIN |
| MIMRXBWADD7 | output | TCELL10:OUT13.TMIN |
| MIMRXBWADD8 | output | TCELL10:OUT14.TMIN |
| MIMRXBWADD9 | output | TCELL12:OUT12.TMIN |
| MIMRXBWDATA0 | output | TCELL10:OUT5.TMIN |
| MIMRXBWDATA1 | output | TCELL10:OUT6.TMIN |
| MIMRXBWDATA10 | output | TCELL13:OUT0.TMIN |
| MIMRXBWDATA11 | output | TCELL13:OUT1.TMIN |
| MIMRXBWDATA12 | output | TCELL13:OUT2.TMIN |
| MIMRXBWDATA13 | output | TCELL13:OUT3.TMIN |
| MIMRXBWDATA14 | output | TCELL14:OUT0.TMIN |
| MIMRXBWDATA15 | output | TCELL14:OUT1.TMIN |
| MIMRXBWDATA16 | output | TCELL14:OUT2.TMIN |
| MIMRXBWDATA17 | output | TCELL14:OUT3.TMIN |
| MIMRXBWDATA18 | output | TCELL13:OUT4.TMIN |
| MIMRXBWDATA19 | output | TCELL13:OUT5.TMIN |
| MIMRXBWDATA2 | output | TCELL11:OUT8.TMIN |
| MIMRXBWDATA20 | output | TCELL13:OUT6.TMIN |
| MIMRXBWDATA21 | output | TCELL13:OUT7.TMIN |
| MIMRXBWDATA22 | output | TCELL12:OUT8.TMIN |
| MIMRXBWDATA23 | output | TCELL12:OUT9.TMIN |
| MIMRXBWDATA24 | output | TCELL12:OUT10.TMIN |
| MIMRXBWDATA25 | output | TCELL12:OUT11.TMIN |
| MIMRXBWDATA26 | output | TCELL11:OUT12.TMIN |
| MIMRXBWDATA27 | output | TCELL11:OUT13.TMIN |
| MIMRXBWDATA28 | output | TCELL11:OUT14.TMIN |
| MIMRXBWDATA29 | output | TCELL10:OUT7.TMIN |
| MIMRXBWDATA3 | output | TCELL11:OUT9.TMIN |
| MIMRXBWDATA30 | output | TCELL10:OUT8.TMIN |
| MIMRXBWDATA31 | output | TCELL10:OUT9.TMIN |
| MIMRXBWDATA32 | output | TCELL10:OUT10.TMIN |
| MIMRXBWDATA33 | output | TCELL9:OUT0.TMIN |
| MIMRXBWDATA34 | output | TCELL9:OUT1.TMIN |
| MIMRXBWDATA35 | output | TCELL9:OUT2.TMIN |
| MIMRXBWDATA36 | output | TCELL9:OUT3.TMIN |
| MIMRXBWDATA37 | output | TCELL8:OUT0.TMIN |
| MIMRXBWDATA38 | output | TCELL8:OUT1.TMIN |
| MIMRXBWDATA39 | output | TCELL8:OUT2.TMIN |
| MIMRXBWDATA4 | output | TCELL11:OUT10.TMIN |
| MIMRXBWDATA40 | output | TCELL8:OUT3.TMIN |
| MIMRXBWDATA41 | output | TCELL7:OUT0.TMIN |
| MIMRXBWDATA42 | output | TCELL7:OUT1.TMIN |
| MIMRXBWDATA43 | output | TCELL7:OUT2.TMIN |
| MIMRXBWDATA44 | output | TCELL7:OUT3.TMIN |
| MIMRXBWDATA45 | output | TCELL6:OUT0.TMIN |
| MIMRXBWDATA46 | output | TCELL6:OUT1.TMIN |
| MIMRXBWDATA47 | output | TCELL6:OUT2.TMIN |
| MIMRXBWDATA48 | output | TCELL6:OUT3.TMIN |
| MIMRXBWDATA49 | output | TCELL5:OUT0.TMIN |
| MIMRXBWDATA5 | output | TCELL11:OUT11.TMIN |
| MIMRXBWDATA50 | output | TCELL5:OUT1.TMIN |
| MIMRXBWDATA51 | output | TCELL5:OUT2.TMIN |
| MIMRXBWDATA52 | output | TCELL5:OUT3.TMIN |
| MIMRXBWDATA53 | output | TCELL6:OUT4.TMIN |
| MIMRXBWDATA54 | output | TCELL6:OUT5.TMIN |
| MIMRXBWDATA55 | output | TCELL6:OUT6.TMIN |
| MIMRXBWDATA56 | output | TCELL6:OUT7.TMIN |
| MIMRXBWDATA57 | output | TCELL7:OUT4.TMIN |
| MIMRXBWDATA58 | output | TCELL7:OUT5.TMIN |
| MIMRXBWDATA59 | output | TCELL7:OUT6.TMIN |
| MIMRXBWDATA6 | output | TCELL12:OUT4.TMIN |
| MIMRXBWDATA60 | output | TCELL7:OUT7.TMIN |
| MIMRXBWDATA61 | output | TCELL8:OUT4.TMIN |
| MIMRXBWDATA62 | output | TCELL8:OUT5.TMIN |
| MIMRXBWDATA63 | output | TCELL8:OUT6.TMIN |
| MIMRXBWDATA7 | output | TCELL12:OUT5.TMIN |
| MIMRXBWDATA8 | output | TCELL12:OUT6.TMIN |
| MIMRXBWDATA9 | output | TCELL12:OUT7.TMIN |
| MIMRXBWEN | output | TCELL9:OUT8.TMIN |
| MIMTXBRADD0 | output | TCELL16:OUT11.TMIN |
| MIMTXBRADD1 | output | TCELL17:OUT8.TMIN |
| MIMTXBRADD10 | output | TCELL19:OUT9.TMIN |
| MIMTXBRADD11 | output | TCELL19:OUT10.TMIN |
| MIMTXBRADD12 | output | TCELL19:OUT11.TMIN |
| MIMTXBRADD2 | output | TCELL17:OUT9.TMIN |
| MIMTXBRADD3 | output | TCELL17:OUT10.TMIN |
| MIMTXBRADD4 | output | TCELL17:OUT11.TMIN |
| MIMTXBRADD5 | output | TCELL18:OUT8.TMIN |
| MIMTXBRADD6 | output | TCELL18:OUT9.TMIN |
| MIMTXBRADD7 | output | TCELL18:OUT10.TMIN |
| MIMTXBRADD8 | output | TCELL18:OUT11.TMIN |
| MIMTXBRADD9 | output | TCELL19:OUT8.TMIN |
| MIMTXBRDATA0 | input | TCELL15:IMUX.IMUX0.DELAY |
| MIMTXBRDATA1 | input | TCELL15:IMUX.IMUX1.DELAY |
| MIMTXBRDATA10 | input | TCELL17:IMUX.IMUX2.DELAY |
| MIMTXBRDATA11 | input | TCELL17:IMUX.IMUX3.DELAY |
| MIMTXBRDATA12 | input | TCELL18:IMUX.IMUX0.DELAY |
| MIMTXBRDATA13 | input | TCELL18:IMUX.IMUX1.DELAY |
| MIMTXBRDATA14 | input | TCELL18:IMUX.IMUX2.DELAY |
| MIMTXBRDATA15 | input | TCELL18:IMUX.IMUX3.DELAY |
| MIMTXBRDATA16 | input | TCELL19:IMUX.IMUX0.DELAY |
| MIMTXBRDATA17 | input | TCELL19:IMUX.IMUX1.DELAY |
| MIMTXBRDATA18 | input | TCELL19:IMUX.IMUX2.DELAY |
| MIMTXBRDATA19 | input | TCELL19:IMUX.IMUX3.DELAY |
| MIMTXBRDATA2 | input | TCELL15:IMUX.IMUX2.DELAY |
| MIMTXBRDATA20 | input | TCELL20:IMUX.IMUX0.DELAY |
| MIMTXBRDATA21 | input | TCELL20:IMUX.IMUX1.DELAY |
| MIMTXBRDATA22 | input | TCELL20:IMUX.IMUX2.DELAY |
| MIMTXBRDATA23 | input | TCELL20:IMUX.IMUX3.DELAY |
| MIMTXBRDATA24 | input | TCELL21:IMUX.IMUX0.DELAY |
| MIMTXBRDATA25 | input | TCELL21:IMUX.IMUX1.DELAY |
| MIMTXBRDATA26 | input | TCELL21:IMUX.IMUX2.DELAY |
| MIMTXBRDATA27 | input | TCELL21:IMUX.IMUX3.DELAY |
| MIMTXBRDATA28 | input | TCELL22:IMUX.IMUX0.DELAY |
| MIMTXBRDATA29 | input | TCELL22:IMUX.IMUX1.DELAY |
| MIMTXBRDATA3 | input | TCELL15:IMUX.IMUX3.DELAY |
| MIMTXBRDATA30 | input | TCELL22:IMUX.IMUX2.DELAY |
| MIMTXBRDATA31 | input | TCELL22:IMUX.IMUX3.DELAY |
| MIMTXBRDATA32 | input | TCELL23:IMUX.IMUX4.DELAY |
| MIMTXBRDATA33 | input | TCELL23:IMUX.IMUX5.DELAY |
| MIMTXBRDATA34 | input | TCELL23:IMUX.IMUX6.DELAY |
| MIMTXBRDATA35 | input | TCELL23:IMUX.IMUX7.DELAY |
| MIMTXBRDATA36 | input | TCELL24:IMUX.IMUX4.DELAY |
| MIMTXBRDATA37 | input | TCELL24:IMUX.IMUX5.DELAY |
| MIMTXBRDATA38 | input | TCELL24:IMUX.IMUX6.DELAY |
| MIMTXBRDATA39 | input | TCELL24:IMUX.IMUX7.DELAY |
| MIMTXBRDATA4 | input | TCELL16:IMUX.IMUX0.DELAY |
| MIMTXBRDATA40 | input | TCELL23:IMUX.IMUX8.DELAY |
| MIMTXBRDATA41 | input | TCELL23:IMUX.IMUX9.DELAY |
| MIMTXBRDATA42 | input | TCELL23:IMUX.IMUX10.DELAY |
| MIMTXBRDATA43 | input | TCELL23:IMUX.IMUX11.DELAY |
| MIMTXBRDATA44 | input | TCELL22:IMUX.IMUX4.DELAY |
| MIMTXBRDATA45 | input | TCELL22:IMUX.IMUX5.DELAY |
| MIMTXBRDATA46 | input | TCELL22:IMUX.IMUX6.DELAY |
| MIMTXBRDATA47 | input | TCELL22:IMUX.IMUX7.DELAY |
| MIMTXBRDATA48 | input | TCELL21:IMUX.IMUX4.DELAY |
| MIMTXBRDATA49 | input | TCELL21:IMUX.IMUX5.DELAY |
| MIMTXBRDATA5 | input | TCELL16:IMUX.IMUX1.DELAY |
| MIMTXBRDATA50 | input | TCELL21:IMUX.IMUX6.DELAY |
| MIMTXBRDATA51 | input | TCELL21:IMUX.IMUX7.DELAY |
| MIMTXBRDATA52 | input | TCELL20:IMUX.IMUX4.DELAY |
| MIMTXBRDATA53 | input | TCELL20:IMUX.IMUX5.DELAY |
| MIMTXBRDATA54 | input | TCELL20:IMUX.IMUX6.DELAY |
| MIMTXBRDATA55 | input | TCELL20:IMUX.IMUX7.DELAY |
| MIMTXBRDATA56 | input | TCELL19:IMUX.IMUX4.DELAY |
| MIMTXBRDATA57 | input | TCELL19:IMUX.IMUX5.DELAY |
| MIMTXBRDATA58 | input | TCELL19:IMUX.IMUX6.DELAY |
| MIMTXBRDATA59 | input | TCELL19:IMUX.IMUX7.DELAY |
| MIMTXBRDATA6 | input | TCELL16:IMUX.IMUX2.DELAY |
| MIMTXBRDATA60 | input | TCELL18:IMUX.IMUX4.DELAY |
| MIMTXBRDATA61 | input | TCELL18:IMUX.IMUX5.DELAY |
| MIMTXBRDATA62 | input | TCELL18:IMUX.IMUX6.DELAY |
| MIMTXBRDATA63 | input | TCELL18:IMUX.IMUX7.DELAY |
| MIMTXBRDATA7 | input | TCELL16:IMUX.IMUX3.DELAY |
| MIMTXBRDATA8 | input | TCELL17:IMUX.IMUX0.DELAY |
| MIMTXBRDATA9 | input | TCELL17:IMUX.IMUX1.DELAY |
| MIMTXBREN | output | TCELL20:OUT13.TMIN |
| MIMTXBWADD0 | output | TCELL17:OUT6.TMIN |
| MIMTXBWADD1 | output | TCELL17:OUT7.TMIN |
| MIMTXBWADD10 | output | TCELL16:OUT8.TMIN |
| MIMTXBWADD11 | output | TCELL16:OUT9.TMIN |
| MIMTXBWADD12 | output | TCELL16:OUT10.TMIN |
| MIMTXBWADD2 | output | TCELL16:OUT4.TMIN |
| MIMTXBWADD3 | output | TCELL16:OUT5.TMIN |
| MIMTXBWADD4 | output | TCELL16:OUT6.TMIN |
| MIMTXBWADD5 | output | TCELL16:OUT7.TMIN |
| MIMTXBWADD6 | output | TCELL15:OUT3.TMIN |
| MIMTXBWADD7 | output | TCELL15:OUT4.TMIN |
| MIMTXBWADD8 | output | TCELL15:OUT5.TMIN |
| MIMTXBWADD9 | output | TCELL15:OUT6.TMIN |
| MIMTXBWDATA0 | output | TCELL15:OUT0.TMIN |
| MIMTXBWDATA1 | output | TCELL15:OUT1.TMIN |
| MIMTXBWDATA10 | output | TCELL17:OUT3.TMIN |
| MIMTXBWDATA11 | output | TCELL18:OUT0.TMIN |
| MIMTXBWDATA12 | output | TCELL18:OUT1.TMIN |
| MIMTXBWDATA13 | output | TCELL18:OUT2.TMIN |
| MIMTXBWDATA14 | output | TCELL18:OUT3.TMIN |
| MIMTXBWDATA15 | output | TCELL19:OUT0.TMIN |
| MIMTXBWDATA16 | output | TCELL19:OUT1.TMIN |
| MIMTXBWDATA17 | output | TCELL19:OUT2.TMIN |
| MIMTXBWDATA18 | output | TCELL19:OUT3.TMIN |
| MIMTXBWDATA19 | output | TCELL20:OUT4.TMIN |
| MIMTXBWDATA2 | output | TCELL15:OUT2.TMIN |
| MIMTXBWDATA20 | output | TCELL20:OUT5.TMIN |
| MIMTXBWDATA21 | output | TCELL20:OUT6.TMIN |
| MIMTXBWDATA22 | output | TCELL20:OUT7.TMIN |
| MIMTXBWDATA23 | output | TCELL21:OUT4.TMIN |
| MIMTXBWDATA24 | output | TCELL21:OUT5.TMIN |
| MIMTXBWDATA25 | output | TCELL21:OUT6.TMIN |
| MIMTXBWDATA26 | output | TCELL21:OUT7.TMIN |
| MIMTXBWDATA27 | output | TCELL22:OUT4.TMIN |
| MIMTXBWDATA28 | output | TCELL22:OUT5.TMIN |
| MIMTXBWDATA29 | output | TCELL22:OUT6.TMIN |
| MIMTXBWDATA3 | output | TCELL16:OUT0.TMIN |
| MIMTXBWDATA30 | output | TCELL22:OUT7.TMIN |
| MIMTXBWDATA31 | output | TCELL23:OUT4.TMIN |
| MIMTXBWDATA32 | output | TCELL23:OUT5.TMIN |
| MIMTXBWDATA33 | output | TCELL23:OUT6.TMIN |
| MIMTXBWDATA34 | output | TCELL23:OUT7.TMIN |
| MIMTXBWDATA35 | output | TCELL24:OUT1.TMIN |
| MIMTXBWDATA36 | output | TCELL24:OUT2.TMIN |
| MIMTXBWDATA37 | output | TCELL24:OUT3.TMIN |
| MIMTXBWDATA38 | output | TCELL23:OUT8.TMIN |
| MIMTXBWDATA39 | output | TCELL23:OUT9.TMIN |
| MIMTXBWDATA4 | output | TCELL16:OUT1.TMIN |
| MIMTXBWDATA40 | output | TCELL23:OUT10.TMIN |
| MIMTXBWDATA41 | output | TCELL23:OUT11.TMIN |
| MIMTXBWDATA42 | output | TCELL22:OUT8.TMIN |
| MIMTXBWDATA43 | output | TCELL22:OUT9.TMIN |
| MIMTXBWDATA44 | output | TCELL22:OUT10.TMIN |
| MIMTXBWDATA45 | output | TCELL22:OUT11.TMIN |
| MIMTXBWDATA46 | output | TCELL21:OUT8.TMIN |
| MIMTXBWDATA47 | output | TCELL21:OUT9.TMIN |
| MIMTXBWDATA48 | output | TCELL21:OUT10.TMIN |
| MIMTXBWDATA49 | output | TCELL21:OUT11.TMIN |
| MIMTXBWDATA5 | output | TCELL16:OUT2.TMIN |
| MIMTXBWDATA50 | output | TCELL20:OUT8.TMIN |
| MIMTXBWDATA51 | output | TCELL20:OUT9.TMIN |
| MIMTXBWDATA52 | output | TCELL20:OUT10.TMIN |
| MIMTXBWDATA53 | output | TCELL20:OUT11.TMIN |
| MIMTXBWDATA54 | output | TCELL19:OUT4.TMIN |
| MIMTXBWDATA55 | output | TCELL19:OUT5.TMIN |
| MIMTXBWDATA56 | output | TCELL19:OUT6.TMIN |
| MIMTXBWDATA57 | output | TCELL19:OUT7.TMIN |
| MIMTXBWDATA58 | output | TCELL18:OUT4.TMIN |
| MIMTXBWDATA59 | output | TCELL18:OUT5.TMIN |
| MIMTXBWDATA6 | output | TCELL16:OUT3.TMIN |
| MIMTXBWDATA60 | output | TCELL18:OUT6.TMIN |
| MIMTXBWDATA61 | output | TCELL18:OUT7.TMIN |
| MIMTXBWDATA62 | output | TCELL17:OUT4.TMIN |
| MIMTXBWDATA63 | output | TCELL17:OUT5.TMIN |
| MIMTXBWDATA7 | output | TCELL17:OUT0.TMIN |
| MIMTXBWDATA8 | output | TCELL17:OUT1.TMIN |
| MIMTXBWDATA9 | output | TCELL17:OUT2.TMIN |
| MIMTXBWEN | output | TCELL20:OUT12.TMIN |
| PARITYERRORRESPONSE | output | TCELL35:OUT20.TMIN |
| PIPEDESKEWLANESL0 | output | TCELL36:OUT20.TMIN |
| PIPEDESKEWLANESL1 | output | TCELL23:OUT3.TMIN |
| PIPEDESKEWLANESL2 | output | TCELL16:OUT20.TMIN |
| PIPEDESKEWLANESL3 | output | TCELL3:OUT3.TMIN |
| PIPEDESKEWLANESL4 | output | TCELL31:OUT20.TMIN |
| PIPEDESKEWLANESL5 | output | TCELL30:OUT3.TMIN |
| PIPEDESKEWLANESL6 | output | TCELL11:OUT20.TMIN |
| PIPEDESKEWLANESL7 | output | TCELL10:OUT3.TMIN |
| PIPEPHYSTATUSL0 | input | TCELL33:IMUX.IMUX47.DELAY |
| PIPEPHYSTATUSL1 | input | TCELL26:IMUX.IMUX0.DELAY |
| PIPEPHYSTATUSL2 | input | TCELL13:IMUX.IMUX47.DELAY |
| PIPEPHYSTATUSL3 | input | TCELL6:IMUX.IMUX0.DELAY |
| PIPEPHYSTATUSL4 | input | TCELL28:IMUX.IMUX47.DELAY |
| PIPEPHYSTATUSL5 | input | TCELL32:IMUX.IMUX0.DELAY |
| PIPEPHYSTATUSL6 | input | TCELL8:IMUX.IMUX47.DELAY |
| PIPEPHYSTATUSL7 | input | TCELL12:IMUX.IMUX0.DELAY |
| PIPEPOWERDOWNL00 | output | TCELL36:OUT22.TMIN |
| PIPEPOWERDOWNL01 | output | TCELL36:OUT21.TMIN |
| PIPEPOWERDOWNL10 | output | TCELL23:OUT1.TMIN |
| PIPEPOWERDOWNL11 | output | TCELL23:OUT2.TMIN |
| PIPEPOWERDOWNL20 | output | TCELL16:OUT22.TMIN |
| PIPEPOWERDOWNL21 | output | TCELL16:OUT21.TMIN |
| PIPEPOWERDOWNL30 | output | TCELL3:OUT1.TMIN |
| PIPEPOWERDOWNL31 | output | TCELL3:OUT2.TMIN |
| PIPEPOWERDOWNL40 | output | TCELL31:OUT22.TMIN |
| PIPEPOWERDOWNL41 | output | TCELL31:OUT21.TMIN |
| PIPEPOWERDOWNL50 | output | TCELL31:OUT6.TMIN |
| PIPEPOWERDOWNL51 | output | TCELL31:OUT7.TMIN |
| PIPEPOWERDOWNL60 | output | TCELL11:OUT22.TMIN |
| PIPEPOWERDOWNL61 | output | TCELL11:OUT21.TMIN |
| PIPEPOWERDOWNL70 | output | TCELL11:OUT6.TMIN |
| PIPEPOWERDOWNL71 | output | TCELL11:OUT7.TMIN |
| PIPERESETL0 | output | TCELL35:OUT23.TMIN |
| PIPERESETL1 | output | TCELL24:OUT0.TMIN |
| PIPERESETL2 | output | TCELL15:OUT23.TMIN |
| PIPERESETL3 | output | TCELL4:OUT0.TMIN |
| PIPERESETL4 | output | TCELL30:OUT23.TMIN |
| PIPERESETL5 | output | TCELL30:OUT4.TMIN |
| PIPERESETL6 | output | TCELL10:OUT23.TMIN |
| PIPERESETL7 | output | TCELL10:OUT4.TMIN |
| PIPERXCHANISALIGNEDL0 | input | TCELL33:IMUX.IMUX44.DELAY |
| PIPERXCHANISALIGNEDL1 | input | TCELL26:IMUX.IMUX3.DELAY |
| PIPERXCHANISALIGNEDL2 | input | TCELL13:IMUX.IMUX44.DELAY |
| PIPERXCHANISALIGNEDL3 | input | TCELL6:IMUX.IMUX3.DELAY |
| PIPERXCHANISALIGNEDL4 | input | TCELL28:IMUX.IMUX44.DELAY |
| PIPERXCHANISALIGNEDL5 | input | TCELL32:IMUX.IMUX3.DELAY |
| PIPERXCHANISALIGNEDL6 | input | TCELL8:IMUX.IMUX44.DELAY |
| PIPERXCHANISALIGNEDL7 | input | TCELL12:IMUX.IMUX3.DELAY |
| PIPERXDATAKL0 | input | TCELL33:IMUX.IMUX46.DELAY |
| PIPERXDATAKL1 | input | TCELL26:IMUX.IMUX1.DELAY |
| PIPERXDATAKL2 | input | TCELL13:IMUX.IMUX46.DELAY |
| PIPERXDATAKL3 | input | TCELL6:IMUX.IMUX1.DELAY |
| PIPERXDATAKL4 | input | TCELL28:IMUX.IMUX46.DELAY |
| PIPERXDATAKL5 | input | TCELL32:IMUX.IMUX1.DELAY |
| PIPERXDATAKL6 | input | TCELL8:IMUX.IMUX46.DELAY |
| PIPERXDATAKL7 | input | TCELL12:IMUX.IMUX1.DELAY |
| PIPERXDATAL00 | input | TCELL35:IMUX.IMUX47.DELAY |
| PIPERXDATAL01 | input | TCELL35:IMUX.IMUX46.DELAY |
| PIPERXDATAL02 | input | TCELL35:IMUX.IMUX45.DELAY |
| PIPERXDATAL03 | input | TCELL35:IMUX.IMUX44.DELAY |
| PIPERXDATAL04 | input | TCELL34:IMUX.IMUX47.DELAY |
| PIPERXDATAL05 | input | TCELL34:IMUX.IMUX46.DELAY |
| PIPERXDATAL06 | input | TCELL34:IMUX.IMUX45.DELAY |
| PIPERXDATAL07 | input | TCELL34:IMUX.IMUX44.DELAY |
| PIPERXDATAL10 | input | TCELL24:IMUX.IMUX0.DELAY |
| PIPERXDATAL11 | input | TCELL24:IMUX.IMUX1.DELAY |
| PIPERXDATAL12 | input | TCELL24:IMUX.IMUX2.DELAY |
| PIPERXDATAL13 | input | TCELL24:IMUX.IMUX3.DELAY |
| PIPERXDATAL14 | input | TCELL25:IMUX.IMUX0.DELAY |
| PIPERXDATAL15 | input | TCELL25:IMUX.IMUX1.DELAY |
| PIPERXDATAL16 | input | TCELL25:IMUX.IMUX2.DELAY |
| PIPERXDATAL17 | input | TCELL25:IMUX.IMUX3.DELAY |
| PIPERXDATAL20 | input | TCELL15:IMUX.IMUX47.DELAY |
| PIPERXDATAL21 | input | TCELL15:IMUX.IMUX46.DELAY |
| PIPERXDATAL22 | input | TCELL15:IMUX.IMUX45.DELAY |
| PIPERXDATAL23 | input | TCELL15:IMUX.IMUX44.DELAY |
| PIPERXDATAL24 | input | TCELL14:IMUX.IMUX47.DELAY |
| PIPERXDATAL25 | input | TCELL14:IMUX.IMUX46.DELAY |
| PIPERXDATAL26 | input | TCELL14:IMUX.IMUX45.DELAY |
| PIPERXDATAL27 | input | TCELL14:IMUX.IMUX44.DELAY |
| PIPERXDATAL30 | input | TCELL4:IMUX.IMUX0.DELAY |
| PIPERXDATAL31 | input | TCELL4:IMUX.IMUX1.DELAY |
| PIPERXDATAL32 | input | TCELL4:IMUX.IMUX2.DELAY |
| PIPERXDATAL33 | input | TCELL4:IMUX.IMUX3.DELAY |
| PIPERXDATAL34 | input | TCELL5:IMUX.IMUX0.DELAY |
| PIPERXDATAL35 | input | TCELL5:IMUX.IMUX1.DELAY |
| PIPERXDATAL36 | input | TCELL5:IMUX.IMUX2.DELAY |
| PIPERXDATAL37 | input | TCELL5:IMUX.IMUX3.DELAY |
| PIPERXDATAL40 | input | TCELL30:IMUX.IMUX47.DELAY |
| PIPERXDATAL41 | input | TCELL30:IMUX.IMUX46.DELAY |
| PIPERXDATAL42 | input | TCELL30:IMUX.IMUX45.DELAY |
| PIPERXDATAL43 | input | TCELL30:IMUX.IMUX44.DELAY |
| PIPERXDATAL44 | input | TCELL29:IMUX.IMUX47.DELAY |
| PIPERXDATAL45 | input | TCELL29:IMUX.IMUX46.DELAY |
| PIPERXDATAL46 | input | TCELL29:IMUX.IMUX45.DELAY |
| PIPERXDATAL47 | input | TCELL29:IMUX.IMUX44.DELAY |
| PIPERXDATAL50 | input | TCELL30:IMUX.IMUX0.DELAY |
| PIPERXDATAL51 | input | TCELL30:IMUX.IMUX1.DELAY |
| PIPERXDATAL52 | input | TCELL30:IMUX.IMUX2.DELAY |
| PIPERXDATAL53 | input | TCELL30:IMUX.IMUX3.DELAY |
| PIPERXDATAL54 | input | TCELL31:IMUX.IMUX0.DELAY |
| PIPERXDATAL55 | input | TCELL31:IMUX.IMUX1.DELAY |
| PIPERXDATAL56 | input | TCELL31:IMUX.IMUX2.DELAY |
| PIPERXDATAL57 | input | TCELL31:IMUX.IMUX3.DELAY |
| PIPERXDATAL60 | input | TCELL10:IMUX.IMUX47.DELAY |
| PIPERXDATAL61 | input | TCELL10:IMUX.IMUX46.DELAY |
| PIPERXDATAL62 | input | TCELL10:IMUX.IMUX45.DELAY |
| PIPERXDATAL63 | input | TCELL10:IMUX.IMUX44.DELAY |
| PIPERXDATAL64 | input | TCELL9:IMUX.IMUX47.DELAY |
| PIPERXDATAL65 | input | TCELL9:IMUX.IMUX46.DELAY |
| PIPERXDATAL66 | input | TCELL9:IMUX.IMUX45.DELAY |
| PIPERXDATAL67 | input | TCELL9:IMUX.IMUX44.DELAY |
| PIPERXDATAL70 | input | TCELL10:IMUX.IMUX0.DELAY |
| PIPERXDATAL71 | input | TCELL10:IMUX.IMUX1.DELAY |
| PIPERXDATAL72 | input | TCELL10:IMUX.IMUX2.DELAY |
| PIPERXDATAL73 | input | TCELL10:IMUX.IMUX3.DELAY |
| PIPERXDATAL74 | input | TCELL11:IMUX.IMUX0.DELAY |
| PIPERXDATAL75 | input | TCELL11:IMUX.IMUX1.DELAY |
| PIPERXDATAL76 | input | TCELL11:IMUX.IMUX2.DELAY |
| PIPERXDATAL77 | input | TCELL11:IMUX.IMUX3.DELAY |
| PIPERXELECIDLEL0 | input | TCELL36:IMUX.IMUX47.DELAY |
| PIPERXELECIDLEL1 | input | TCELL23:IMUX.IMUX0.DELAY |
| PIPERXELECIDLEL2 | input | TCELL16:IMUX.IMUX47.DELAY |
| PIPERXELECIDLEL3 | input | TCELL3:IMUX.IMUX0.DELAY |
| PIPERXELECIDLEL4 | input | TCELL31:IMUX.IMUX47.DELAY |
| PIPERXELECIDLEL5 | input | TCELL29:IMUX.IMUX0.DELAY |
| PIPERXELECIDLEL6 | input | TCELL11:IMUX.IMUX47.DELAY |
| PIPERXELECIDLEL7 | input | TCELL9:IMUX.IMUX0.DELAY |
| PIPERXPOLARITYL0 | output | TCELL36:OUT23.TMIN |
| PIPERXPOLARITYL1 | output | TCELL23:OUT0.TMIN |
| PIPERXPOLARITYL2 | output | TCELL16:OUT23.TMIN |
| PIPERXPOLARITYL3 | output | TCELL3:OUT0.TMIN |
| PIPERXPOLARITYL4 | output | TCELL31:OUT23.TMIN |
| PIPERXPOLARITYL5 | output | TCELL31:OUT5.TMIN |
| PIPERXPOLARITYL6 | output | TCELL11:OUT23.TMIN |
| PIPERXPOLARITYL7 | output | TCELL11:OUT5.TMIN |
| PIPERXSTATUSL00 | input | TCELL36:IMUX.IMUX46.DELAY |
| PIPERXSTATUSL01 | input | TCELL36:IMUX.IMUX45.DELAY |
| PIPERXSTATUSL02 | input | TCELL36:IMUX.IMUX44.DELAY |
| PIPERXSTATUSL10 | input | TCELL23:IMUX.IMUX1.DELAY |
| PIPERXSTATUSL11 | input | TCELL23:IMUX.IMUX2.DELAY |
| PIPERXSTATUSL12 | input | TCELL23:IMUX.IMUX3.DELAY |
| PIPERXSTATUSL20 | input | TCELL16:IMUX.IMUX46.DELAY |
| PIPERXSTATUSL21 | input | TCELL16:IMUX.IMUX45.DELAY |
| PIPERXSTATUSL22 | input | TCELL16:IMUX.IMUX44.DELAY |
| PIPERXSTATUSL30 | input | TCELL3:IMUX.IMUX1.DELAY |
| PIPERXSTATUSL31 | input | TCELL3:IMUX.IMUX2.DELAY |
| PIPERXSTATUSL32 | input | TCELL3:IMUX.IMUX3.DELAY |
| PIPERXSTATUSL40 | input | TCELL31:IMUX.IMUX46.DELAY |
| PIPERXSTATUSL41 | input | TCELL31:IMUX.IMUX45.DELAY |
| PIPERXSTATUSL42 | input | TCELL31:IMUX.IMUX44.DELAY |
| PIPERXSTATUSL50 | input | TCELL29:IMUX.IMUX1.DELAY |
| PIPERXSTATUSL51 | input | TCELL29:IMUX.IMUX2.DELAY |
| PIPERXSTATUSL52 | input | TCELL29:IMUX.IMUX3.DELAY |
| PIPERXSTATUSL60 | input | TCELL11:IMUX.IMUX46.DELAY |
| PIPERXSTATUSL61 | input | TCELL11:IMUX.IMUX45.DELAY |
| PIPERXSTATUSL62 | input | TCELL11:IMUX.IMUX44.DELAY |
| PIPERXSTATUSL70 | input | TCELL9:IMUX.IMUX1.DELAY |
| PIPERXSTATUSL71 | input | TCELL9:IMUX.IMUX2.DELAY |
| PIPERXSTATUSL72 | input | TCELL9:IMUX.IMUX3.DELAY |
| PIPERXVALIDL0 | input | TCELL33:IMUX.IMUX45.DELAY |
| PIPERXVALIDL1 | input | TCELL26:IMUX.IMUX2.DELAY |
| PIPERXVALIDL2 | input | TCELL13:IMUX.IMUX45.DELAY |
| PIPERXVALIDL3 | input | TCELL6:IMUX.IMUX2.DELAY |
| PIPERXVALIDL4 | input | TCELL28:IMUX.IMUX45.DELAY |
| PIPERXVALIDL5 | input | TCELL32:IMUX.IMUX2.DELAY |
| PIPERXVALIDL6 | input | TCELL8:IMUX.IMUX45.DELAY |
| PIPERXVALIDL7 | input | TCELL12:IMUX.IMUX2.DELAY |
| PIPETXCOMPLIANCEL0 | output | TCELL37:OUT20.TMIN |
| PIPETXCOMPLIANCEL1 | output | TCELL22:OUT3.TMIN |
| PIPETXCOMPLIANCEL2 | output | TCELL17:OUT20.TMIN |
| PIPETXCOMPLIANCEL3 | output | TCELL2:OUT3.TMIN |
| PIPETXCOMPLIANCEL4 | output | TCELL32:OUT20.TMIN |
| PIPETXCOMPLIANCEL5 | output | TCELL31:OUT4.TMIN |
| PIPETXCOMPLIANCEL6 | output | TCELL12:OUT20.TMIN |
| PIPETXCOMPLIANCEL7 | output | TCELL11:OUT4.TMIN |
| PIPETXDATAKL0 | output | TCELL37:OUT23.TMIN |
| PIPETXDATAKL1 | output | TCELL22:OUT0.TMIN |
| PIPETXDATAKL2 | output | TCELL17:OUT23.TMIN |
| PIPETXDATAKL3 | output | TCELL2:OUT0.TMIN |
| PIPETXDATAKL4 | output | TCELL32:OUT23.TMIN |
| PIPETXDATAKL5 | output | TCELL32:OUT1.TMIN |
| PIPETXDATAKL6 | output | TCELL12:OUT23.TMIN |
| PIPETXDATAKL7 | output | TCELL12:OUT1.TMIN |
| PIPETXDATAL00 | output | TCELL39:OUT23.TMIN |
| PIPETXDATAL01 | output | TCELL39:OUT22.TMIN |
| PIPETXDATAL02 | output | TCELL39:OUT21.TMIN |
| PIPETXDATAL03 | output | TCELL39:OUT20.TMIN |
| PIPETXDATAL04 | output | TCELL38:OUT23.TMIN |
| PIPETXDATAL05 | output | TCELL38:OUT22.TMIN |
| PIPETXDATAL06 | output | TCELL38:OUT21.TMIN |
| PIPETXDATAL07 | output | TCELL38:OUT20.TMIN |
| PIPETXDATAL10 | output | TCELL20:OUT0.TMIN |
| PIPETXDATAL11 | output | TCELL20:OUT1.TMIN |
| PIPETXDATAL12 | output | TCELL20:OUT2.TMIN |
| PIPETXDATAL13 | output | TCELL20:OUT3.TMIN |
| PIPETXDATAL14 | output | TCELL21:OUT0.TMIN |
| PIPETXDATAL15 | output | TCELL21:OUT1.TMIN |
| PIPETXDATAL16 | output | TCELL21:OUT2.TMIN |
| PIPETXDATAL17 | output | TCELL21:OUT3.TMIN |
| PIPETXDATAL20 | output | TCELL19:OUT23.TMIN |
| PIPETXDATAL21 | output | TCELL19:OUT22.TMIN |
| PIPETXDATAL22 | output | TCELL19:OUT21.TMIN |
| PIPETXDATAL23 | output | TCELL19:OUT20.TMIN |
| PIPETXDATAL24 | output | TCELL18:OUT23.TMIN |
| PIPETXDATAL25 | output | TCELL18:OUT22.TMIN |
| PIPETXDATAL26 | output | TCELL18:OUT21.TMIN |
| PIPETXDATAL27 | output | TCELL18:OUT20.TMIN |
| PIPETXDATAL30 | output | TCELL0:OUT0.TMIN |
| PIPETXDATAL31 | output | TCELL0:OUT1.TMIN |
| PIPETXDATAL32 | output | TCELL0:OUT2.TMIN |
| PIPETXDATAL33 | output | TCELL0:OUT3.TMIN |
| PIPETXDATAL34 | output | TCELL1:OUT0.TMIN |
| PIPETXDATAL35 | output | TCELL1:OUT1.TMIN |
| PIPETXDATAL36 | output | TCELL1:OUT2.TMIN |
| PIPETXDATAL37 | output | TCELL1:OUT3.TMIN |
| PIPETXDATAL40 | output | TCELL34:OUT23.TMIN |
| PIPETXDATAL41 | output | TCELL34:OUT22.TMIN |
| PIPETXDATAL42 | output | TCELL34:OUT21.TMIN |
| PIPETXDATAL43 | output | TCELL34:OUT20.TMIN |
| PIPETXDATAL44 | output | TCELL33:OUT23.TMIN |
| PIPETXDATAL45 | output | TCELL33:OUT22.TMIN |
| PIPETXDATAL46 | output | TCELL33:OUT21.TMIN |
| PIPETXDATAL47 | output | TCELL33:OUT20.TMIN |
| PIPETXDATAL50 | output | TCELL30:OUT0.TMIN |
| PIPETXDATAL51 | output | TCELL30:OUT1.TMIN |
| PIPETXDATAL52 | output | TCELL30:OUT2.TMIN |
| PIPETXDATAL53 | output | TCELL31:OUT0.TMIN |
| PIPETXDATAL54 | output | TCELL31:OUT1.TMIN |
| PIPETXDATAL55 | output | TCELL31:OUT2.TMIN |
| PIPETXDATAL56 | output | TCELL31:OUT3.TMIN |
| PIPETXDATAL57 | output | TCELL32:OUT0.TMIN |
| PIPETXDATAL60 | output | TCELL14:OUT23.TMIN |
| PIPETXDATAL61 | output | TCELL14:OUT22.TMIN |
| PIPETXDATAL62 | output | TCELL14:OUT21.TMIN |
| PIPETXDATAL63 | output | TCELL14:OUT20.TMIN |
| PIPETXDATAL64 | output | TCELL13:OUT23.TMIN |
| PIPETXDATAL65 | output | TCELL13:OUT22.TMIN |
| PIPETXDATAL66 | output | TCELL13:OUT21.TMIN |
| PIPETXDATAL67 | output | TCELL13:OUT20.TMIN |
| PIPETXDATAL70 | output | TCELL10:OUT0.TMIN |
| PIPETXDATAL71 | output | TCELL10:OUT1.TMIN |
| PIPETXDATAL72 | output | TCELL10:OUT2.TMIN |
| PIPETXDATAL73 | output | TCELL11:OUT0.TMIN |
| PIPETXDATAL74 | output | TCELL11:OUT1.TMIN |
| PIPETXDATAL75 | output | TCELL11:OUT2.TMIN |
| PIPETXDATAL76 | output | TCELL11:OUT3.TMIN |
| PIPETXDATAL77 | output | TCELL12:OUT0.TMIN |
| PIPETXDETECTRXLOOPBACKL0 | output | TCELL37:OUT21.TMIN |
| PIPETXDETECTRXLOOPBACKL1 | output | TCELL22:OUT2.TMIN |
| PIPETXDETECTRXLOOPBACKL2 | output | TCELL17:OUT21.TMIN |
| PIPETXDETECTRXLOOPBACKL3 | output | TCELL2:OUT2.TMIN |
| PIPETXDETECTRXLOOPBACKL4 | output | TCELL32:OUT21.TMIN |
| PIPETXDETECTRXLOOPBACKL5 | output | TCELL32:OUT3.TMIN |
| PIPETXDETECTRXLOOPBACKL6 | output | TCELL12:OUT21.TMIN |
| PIPETXDETECTRXLOOPBACKL7 | output | TCELL12:OUT3.TMIN |
| PIPETXELECIDLEL0 | output | TCELL37:OUT22.TMIN |
| PIPETXELECIDLEL1 | output | TCELL22:OUT1.TMIN |
| PIPETXELECIDLEL2 | output | TCELL17:OUT22.TMIN |
| PIPETXELECIDLEL3 | output | TCELL2:OUT1.TMIN |
| PIPETXELECIDLEL4 | output | TCELL32:OUT22.TMIN |
| PIPETXELECIDLEL5 | output | TCELL32:OUT2.TMIN |
| PIPETXELECIDLEL6 | output | TCELL12:OUT22.TMIN |
| PIPETXELECIDLEL7 | output | TCELL12:OUT2.TMIN |
| SCANENABLEN | input | TCELL27:IMUX.IMUX16.DELAY |
| SCANIN0 | input | TCELL27:IMUX.IMUX18.DELAY |
| SCANIN1 | input | TCELL27:IMUX.IMUX19.DELAY |
| SCANIN2 | input | TCELL26:IMUX.IMUX16.DELAY |
| SCANIN3 | input | TCELL26:IMUX.IMUX17.DELAY |
| SCANIN4 | input | TCELL26:IMUX.IMUX18.DELAY |
| SCANIN5 | input | TCELL26:IMUX.IMUX19.DELAY |
| SCANIN6 | input | TCELL25:IMUX.IMUX20.DELAY |
| SCANIN7 | input | TCELL25:IMUX.IMUX21.DELAY |
| SCANMODEN | input | TCELL27:IMUX.IMUX17.DELAY |
| SERRENABLE | output | TCELL35:OUT21.TMIN |
| URREPORTINGENABLE | output | TCELL39:OUT16.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.IMUX0.DELAY | PCIE.LLKTXSRCRDYN |
| TCELL0:IMUX.IMUX1.DELAY | PCIE.LLKTXSRCDSCN |
| TCELL0:IMUX.IMUX2.DELAY | PCIE.LLKTXCOMPLETEN |
| TCELL0:IMUX.IMUX3.DELAY | PCIE.LLKTXSOFN |
| TCELL0:IMUX.IMUX4.DELAY | PCIE.L0PACKETHEADERFROMUSER3 |
| TCELL0:IMUX.IMUX5.DELAY | PCIE.L0PACKETHEADERFROMUSER4 |
| TCELL0:IMUX.IMUX6.DELAY | PCIE.L0PACKETHEADERFROMUSER5 |
| TCELL0:IMUX.IMUX7.DELAY | PCIE.L0PACKETHEADERFROMUSER6 |
| TCELL0:IMUX.IMUX8.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED167 |
| TCELL0:IMUX.IMUX9.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED168 |
| TCELL0:IMUX.IMUX10.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED169 |
| TCELL0:IMUX.IMUX11.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED170 |
| TCELL0:IMUX.IMUX12.DELAY | PCIE.L0TXTLFCCMPLMCCRED50 |
| TCELL0:IMUX.IMUX13.DELAY | PCIE.L0TXTLFCCMPLMCCRED51 |
| TCELL0:IMUX.IMUX14.DELAY | PCIE.L0TXTLFCCMPLMCCRED52 |
| TCELL0:IMUX.IMUX15.DELAY | PCIE.L0TXTLFCCMPLMCCRED53 |
| TCELL0:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE4 |
| TCELL0:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE5 |
| TCELL0:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE6 |
| TCELL0:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE7 |
| TCELL0:OUT0.TMIN | PCIE.PIPETXDATAL30 |
| TCELL0:OUT1.TMIN | PCIE.PIPETXDATAL31 |
| TCELL0:OUT2.TMIN | PCIE.PIPETXDATAL32 |
| TCELL0:OUT3.TMIN | PCIE.PIPETXDATAL33 |
| TCELL0:OUT4.TMIN | PCIE.LLKRXDATA6 |
| TCELL0:OUT5.TMIN | PCIE.LLKRXDATA7 |
| TCELL0:OUT6.TMIN | PCIE.LLKRXDATA8 |
| TCELL0:OUT7.TMIN | PCIE.LLKRXDATA9 |
| TCELL0:OUT8.TMIN | PCIE.LLKRXPREFERREDTYPE15 |
| TCELL0:OUT9.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN0 |
| TCELL0:OUT10.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN1 |
| TCELL0:OUT11.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN2 |
| TCELL0:OUT13.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN0 |
| TCELL0:OUT14.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN1 |
| TCELL0:OUT15.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN2 |
| TCELL0:OUT16.TMIN | PCIE.L0FWDCORRERROUT |
| TCELL0:OUT17.TMIN | PCIE.L0FWDFATALERROUT |
| TCELL0:OUT19.TMIN | PCIE.L0RECEIVEDASSERTINTALEGACYINT |
| TCELL0:OUT20.TMIN | PCIE.L0RXDLLFCCMPLMCCRED20 |
| TCELL0:OUT21.TMIN | PCIE.L0RXDLLFCCMPLMCCRED21 |
| TCELL0:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED22 |
| TCELL0:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED23 |
| TCELL1:IMUX.IMUX0.DELAY | PCIE.LLKTXDATA60 |
| TCELL1:IMUX.IMUX1.DELAY | PCIE.LLKTXDATA61 |
| TCELL1:IMUX.IMUX2.DELAY | PCIE.LLKTXDATA62 |
| TCELL1:IMUX.IMUX3.DELAY | PCIE.LLKTXDATA63 |
| TCELL1:IMUX.IMUX4.DELAY | PCIE.LLKTXEOFN |
| TCELL1:IMUX.IMUX5.DELAY | PCIE.LLKTXSOPN |
| TCELL1:IMUX.IMUX6.DELAY | PCIE.LLKTXEOPN |
| TCELL1:IMUX.IMUX7.DELAY | PCIE.LLKTXENABLEN0 |
| TCELL1:IMUX.IMUX8.DELAY | PCIE.L0SETUNSUPPORTEDREQUESTOTHERERROR |
| TCELL1:IMUX.IMUX9.DELAY | PCIE.L0PACKETHEADERFROMUSER0 |
| TCELL1:IMUX.IMUX10.DELAY | PCIE.L0PACKETHEADERFROMUSER1 |
| TCELL1:IMUX.IMUX11.DELAY | PCIE.L0PACKETHEADERFROMUSER2 |
| TCELL1:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER7 |
| TCELL1:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER8 |
| TCELL1:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER9 |
| TCELL1:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER10 |
| TCELL1:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED163 |
| TCELL1:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED164 |
| TCELL1:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED165 |
| TCELL1:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED166 |
| TCELL1:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED171 |
| TCELL1:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED172 |
| TCELL1:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED173 |
| TCELL1:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED174 |
| TCELL1:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCCMPLMCCRED46 |
| TCELL1:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCCMPLMCCRED47 |
| TCELL1:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCCMPLMCCRED48 |
| TCELL1:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED49 |
| TCELL1:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED54 |
| TCELL1:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED55 |
| TCELL1:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED56 |
| TCELL1:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED57 |
| TCELL1:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE0 |
| TCELL1:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE1 |
| TCELL1:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE2 |
| TCELL1:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE3 |
| TCELL1:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE8 |
| TCELL1:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE9 |
| TCELL1:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE10 |
| TCELL1:IMUX.IMUX39.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE11 |
| TCELL1:OUT0.TMIN | PCIE.PIPETXDATAL34 |
| TCELL1:OUT1.TMIN | PCIE.PIPETXDATAL35 |
| TCELL1:OUT2.TMIN | PCIE.PIPETXDATAL36 |
| TCELL1:OUT3.TMIN | PCIE.PIPETXDATAL37 |
| TCELL1:OUT4.TMIN | PCIE.LLKRXDATA2 |
| TCELL1:OUT5.TMIN | PCIE.LLKRXDATA3 |
| TCELL1:OUT6.TMIN | PCIE.LLKRXDATA4 |
| TCELL1:OUT7.TMIN | PCIE.LLKRXDATA5 |
| TCELL1:OUT8.TMIN | PCIE.LLKRXDATA10 |
| TCELL1:OUT9.TMIN | PCIE.LLKRXDATA11 |
| TCELL1:OUT10.TMIN | PCIE.LLKRXDATA12 |
| TCELL1:OUT11.TMIN | PCIE.LLKRXDATA13 |
| TCELL1:OUT12.TMIN | PCIE.LLKRXPREFERREDTYPE11 |
| TCELL1:OUT13.TMIN | PCIE.LLKRXPREFERREDTYPE12 |
| TCELL1:OUT14.TMIN | PCIE.LLKRXPREFERREDTYPE13 |
| TCELL1:OUT15.TMIN | PCIE.LLKRXPREFERREDTYPE14 |
| TCELL1:OUT16.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN3 |
| TCELL1:OUT17.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN4 |
| TCELL1:OUT18.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN5 |
| TCELL1:OUT19.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN6 |
| TCELL1:OUT20.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN5 |
| TCELL1:OUT21.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN6 |
| TCELL1:OUT22.TMIN | PCIE.L0ERRMSGREQID15 |
| TCELL1:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED19 |
| TCELL2:IMUX.IMUX0.DELAY | PCIE.LLKTXDATA56 |
| TCELL2:IMUX.IMUX1.DELAY | PCIE.LLKTXDATA57 |
| TCELL2:IMUX.IMUX2.DELAY | PCIE.LLKTXDATA58 |
| TCELL2:IMUX.IMUX3.DELAY | PCIE.LLKTXDATA59 |
| TCELL2:IMUX.IMUX4.DELAY | PCIE.LLKTXENABLEN1 |
| TCELL2:IMUX.IMUX5.DELAY | PCIE.LLKTXCHTC0 |
| TCELL2:IMUX.IMUX6.DELAY | PCIE.LLKTXCHTC1 |
| TCELL2:IMUX.IMUX7.DELAY | PCIE.LLKTXCHTC2 |
| TCELL2:IMUX.IMUX8.DELAY | PCIE.L0SETCOMPLETIONTIMEOUTCORRERROR |
| TCELL2:IMUX.IMUX9.DELAY | PCIE.L0SETUNEXPECTEDCOMPLETIONUNCORRERROR |
| TCELL2:IMUX.IMUX10.DELAY | PCIE.L0SETUNEXPECTEDCOMPLETIONCORRERROR |
| TCELL2:IMUX.IMUX11.DELAY | PCIE.L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR |
| TCELL2:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER11 |
| TCELL2:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER12 |
| TCELL2:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER13 |
| TCELL2:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER14 |
| TCELL2:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED159 |
| TCELL2:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED160 |
| TCELL2:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED161 |
| TCELL2:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED162 |
| TCELL2:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED175 |
| TCELL2:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED176 |
| TCELL2:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED177 |
| TCELL2:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED178 |
| TCELL2:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCCMPLMCCRED42 |
| TCELL2:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCCMPLMCCRED43 |
| TCELL2:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCCMPLMCCRED44 |
| TCELL2:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED45 |
| TCELL2:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED58 |
| TCELL2:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED59 |
| TCELL2:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED60 |
| TCELL2:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED61 |
| TCELL2:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED156 |
| TCELL2:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED157 |
| TCELL2:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED158 |
| TCELL2:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED159 |
| TCELL2:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE12 |
| TCELL2:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE13 |
| TCELL2:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE14 |
| TCELL2:IMUX.IMUX39.DELAY | PCIE.L0TXTLFCCMPLMCUPDATE15 |
| TCELL2:OUT0.TMIN | PCIE.PIPETXDATAKL3 |
| TCELL2:OUT1.TMIN | PCIE.PIPETXELECIDLEL3 |
| TCELL2:OUT2.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL3 |
| TCELL2:OUT3.TMIN | PCIE.PIPETXCOMPLIANCEL3 |
| TCELL2:OUT4.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN7 |
| TCELL2:OUT5.TMIN | PCIE.LLKTXCONFIGREADYN |
| TCELL2:OUT6.TMIN | PCIE.LLKRXDATA0 |
| TCELL2:OUT7.TMIN | PCIE.LLKRXDATA1 |
| TCELL2:OUT8.TMIN | PCIE.LLKRXDATA14 |
| TCELL2:OUT9.TMIN | PCIE.LLKRXDATA15 |
| TCELL2:OUT10.TMIN | PCIE.LLKRXDATA16 |
| TCELL2:OUT11.TMIN | PCIE.LLKRXDATA17 |
| TCELL2:OUT12.TMIN | PCIE.LLKRXPREFERREDTYPE7 |
| TCELL2:OUT13.TMIN | PCIE.LLKRXPREFERREDTYPE8 |
| TCELL2:OUT14.TMIN | PCIE.LLKRXPREFERREDTYPE9 |
| TCELL2:OUT15.TMIN | PCIE.LLKRXPREFERREDTYPE10 |
| TCELL2:OUT16.TMIN | PCIE.LLKRXCHPOSTEDAVAILABLEN7 |
| TCELL2:OUT17.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN0 |
| TCELL2:OUT18.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN1 |
| TCELL2:OUT19.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN2 |
| TCELL2:OUT20.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN3 |
| TCELL2:OUT21.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN4 |
| TCELL2:OUT22.TMIN | PCIE.L0ERRMSGREQID13 |
| TCELL2:OUT23.TMIN | PCIE.L0ERRMSGREQID14 |
| TCELL3:IMUX.IMUX0.DELAY | PCIE.PIPERXELECIDLEL3 |
| TCELL3:IMUX.IMUX1.DELAY | PCIE.PIPERXSTATUSL30 |
| TCELL3:IMUX.IMUX2.DELAY | PCIE.PIPERXSTATUSL31 |
| TCELL3:IMUX.IMUX3.DELAY | PCIE.PIPERXSTATUSL32 |
| TCELL3:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA52 |
| TCELL3:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA53 |
| TCELL3:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA54 |
| TCELL3:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA55 |
| TCELL3:IMUX.IMUX8.DELAY | PCIE.LLKTXCHFIFO0 |
| TCELL3:IMUX.IMUX9.DELAY | PCIE.LLKTXCHFIFO1 |
| TCELL3:IMUX.IMUX10.DELAY | PCIE.LLKTXCREATEECRCN |
| TCELL3:IMUX.IMUX11.DELAY | PCIE.LLKTX4DWHEADERN |
| TCELL3:IMUX.IMUX12.DELAY | PCIE.L0SETUSERRECEIVEDTARGETABORT |
| TCELL3:IMUX.IMUX13.DELAY | PCIE.L0SETUSERSYSTEMERROR |
| TCELL3:IMUX.IMUX14.DELAY | PCIE.L0SETUSERSIGNALLEDTARGETABORT |
| TCELL3:IMUX.IMUX15.DELAY | PCIE.L0SETCOMPLETIONTIMEOUTUNCORRERROR |
| TCELL3:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER15 |
| TCELL3:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER16 |
| TCELL3:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER17 |
| TCELL3:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED155 |
| TCELL3:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED156 |
| TCELL3:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED157 |
| TCELL3:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED158 |
| TCELL3:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED179 |
| TCELL3:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED180 |
| TCELL3:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED181 |
| TCELL3:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED182 |
| TCELL3:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED38 |
| TCELL3:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED39 |
| TCELL3:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED40 |
| TCELL3:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED41 |
| TCELL3:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED62 |
| TCELL3:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED63 |
| TCELL3:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED64 |
| TCELL3:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED65 |
| TCELL3:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED152 |
| TCELL3:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED153 |
| TCELL3:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED154 |
| TCELL3:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED155 |
| TCELL3:OUT0.TMIN | PCIE.PIPERXPOLARITYL3 |
| TCELL3:OUT1.TMIN | PCIE.PIPEPOWERDOWNL30 |
| TCELL3:OUT2.TMIN | PCIE.PIPEPOWERDOWNL31 |
| TCELL3:OUT3.TMIN | PCIE.PIPEDESKEWLANESL3 |
| TCELL3:OUT4.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN3 |
| TCELL3:OUT5.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN4 |
| TCELL3:OUT6.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN5 |
| TCELL3:OUT7.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN6 |
| TCELL3:OUT8.TMIN | PCIE.LLKRXDATA18 |
| TCELL3:OUT9.TMIN | PCIE.LLKRXDATA19 |
| TCELL3:OUT10.TMIN | PCIE.LLKRXDATA20 |
| TCELL3:OUT11.TMIN | PCIE.LLKRXDATA21 |
| TCELL3:OUT12.TMIN | PCIE.LLKRXPREFERREDTYPE3 |
| TCELL3:OUT13.TMIN | PCIE.LLKRXPREFERREDTYPE4 |
| TCELL3:OUT14.TMIN | PCIE.LLKRXPREFERREDTYPE5 |
| TCELL3:OUT15.TMIN | PCIE.LLKRXPREFERREDTYPE6 |
| TCELL3:OUT16.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN3 |
| TCELL3:OUT17.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN4 |
| TCELL3:OUT18.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN5 |
| TCELL3:OUT19.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN6 |
| TCELL3:OUT20.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN1 |
| TCELL3:OUT21.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN2 |
| TCELL3:OUT22.TMIN | PCIE.L0ERRMSGREQID11 |
| TCELL3:OUT23.TMIN | PCIE.L0ERRMSGREQID12 |
| TCELL4:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL30 |
| TCELL4:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL31 |
| TCELL4:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL32 |
| TCELL4:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL33 |
| TCELL4:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA48 |
| TCELL4:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA49 |
| TCELL4:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA50 |
| TCELL4:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA51 |
| TCELL4:IMUX.IMUX8.DELAY | PCIE.LLKRXDSTREQN |
| TCELL4:IMUX.IMUX9.DELAY | PCIE.LLKRXCHTC0 |
| TCELL4:IMUX.IMUX10.DELAY | PCIE.LLKRXCHTC1 |
| TCELL4:IMUX.IMUX11.DELAY | PCIE.LLKRXCHTC2 |
| TCELL4:IMUX.IMUX12.DELAY | PCIE.L0SETLINKSIGNALLEDTARGETABORT |
| TCELL4:IMUX.IMUX13.DELAY | PCIE.L0SETUSERDETECTEDPARITYERROR |
| TCELL4:IMUX.IMUX14.DELAY | PCIE.L0SETUSERMASTERDATAPARITY |
| TCELL4:IMUX.IMUX15.DELAY | PCIE.L0SETUSERRECEIVEDMASTERABORT |
| TCELL4:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER18 |
| TCELL4:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER19 |
| TCELL4:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER20 |
| TCELL4:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED151 |
| TCELL4:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED152 |
| TCELL4:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED153 |
| TCELL4:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED154 |
| TCELL4:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED183 |
| TCELL4:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED184 |
| TCELL4:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED185 |
| TCELL4:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED186 |
| TCELL4:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED34 |
| TCELL4:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED35 |
| TCELL4:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED36 |
| TCELL4:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED37 |
| TCELL4:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED66 |
| TCELL4:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED67 |
| TCELL4:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED68 |
| TCELL4:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED69 |
| TCELL4:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED148 |
| TCELL4:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED149 |
| TCELL4:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED150 |
| TCELL4:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED151 |
| TCELL4:OUT0.TMIN | PCIE.PIPERESETL3 |
| TCELL4:OUT1.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN0 |
| TCELL4:OUT2.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN1 |
| TCELL4:OUT3.TMIN | PCIE.LLKTXCHCOMPLETIONREADYN2 |
| TCELL4:OUT4.TMIN | PCIE.LLKRXDATA22 |
| TCELL4:OUT5.TMIN | PCIE.LLKRXDATA23 |
| TCELL4:OUT6.TMIN | PCIE.LLKRXDATA24 |
| TCELL4:OUT7.TMIN | PCIE.LLKRXDATA25 |
| TCELL4:OUT8.TMIN | PCIE.LLKRXVALIDN1 |
| TCELL4:OUT9.TMIN | PCIE.LLKRXPREFERREDTYPE0 |
| TCELL4:OUT10.TMIN | PCIE.LLKRXPREFERREDTYPE1 |
| TCELL4:OUT11.TMIN | PCIE.LLKRXPREFERREDTYPE2 |
| TCELL4:OUT12.TMIN | PCIE.LLKRXCHNONPOSTEDAVAILABLEN7 |
| TCELL4:OUT13.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN0 |
| TCELL4:OUT14.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN1 |
| TCELL4:OUT15.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN2 |
| TCELL4:OUT16.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN6 |
| TCELL4:OUT17.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN7 |
| TCELL4:OUT18.TMIN | PCIE.LLKRXCHCONFIGAVAILABLEN |
| TCELL4:OUT19.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN0 |
| TCELL4:OUT20.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN3 |
| TCELL4:OUT21.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN4 |
| TCELL4:OUT22.TMIN | PCIE.LLKRX4DWHEADERN |
| TCELL4:OUT23.TMIN | PCIE.LLKRXECRCBADN |
| TCELL5:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL34 |
| TCELL5:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL35 |
| TCELL5:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL36 |
| TCELL5:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL37 |
| TCELL5:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA43 |
| TCELL5:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA44 |
| TCELL5:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA45 |
| TCELL5:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA46 |
| TCELL5:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA44 |
| TCELL5:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA45 |
| TCELL5:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA46 |
| TCELL5:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA47 |
| TCELL5:IMUX.IMUX12.DELAY | PCIE.LLKRXCHFIFO0 |
| TCELL5:IMUX.IMUX13.DELAY | PCIE.LLKRXCHFIFO1 |
| TCELL5:IMUX.IMUX14.DELAY | PCIE.LLKRXDSTCONTREQN |
| TCELL5:IMUX.IMUX15.DELAY | PCIE.L0SETLINKSYSTEMERROR |
| TCELL5:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER21 |
| TCELL5:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER22 |
| TCELL5:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER23 |
| TCELL5:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED147 |
| TCELL5:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED148 |
| TCELL5:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED149 |
| TCELL5:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED150 |
| TCELL5:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED187 |
| TCELL5:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED188 |
| TCELL5:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED189 |
| TCELL5:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED190 |
| TCELL5:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED30 |
| TCELL5:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED31 |
| TCELL5:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED32 |
| TCELL5:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED33 |
| TCELL5:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED70 |
| TCELL5:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED71 |
| TCELL5:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED72 |
| TCELL5:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED73 |
| TCELL5:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED144 |
| TCELL5:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED145 |
| TCELL5:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED146 |
| TCELL5:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED147 |
| TCELL5:OUT0.TMIN | PCIE.MIMRXBWDATA49 |
| TCELL5:OUT1.TMIN | PCIE.MIMRXBWDATA50 |
| TCELL5:OUT2.TMIN | PCIE.MIMRXBWDATA51 |
| TCELL5:OUT3.TMIN | PCIE.MIMRXBWDATA52 |
| TCELL5:OUT4.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN4 |
| TCELL5:OUT5.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN5 |
| TCELL5:OUT6.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN6 |
| TCELL5:OUT7.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN7 |
| TCELL5:OUT8.TMIN | PCIE.LLKRXDATA26 |
| TCELL5:OUT9.TMIN | PCIE.LLKRXDATA27 |
| TCELL5:OUT10.TMIN | PCIE.LLKRXDATA28 |
| TCELL5:OUT11.TMIN | PCIE.LLKRXDATA29 |
| TCELL5:OUT12.TMIN | PCIE.LLKRXEOFN |
| TCELL5:OUT13.TMIN | PCIE.LLKRXSOPN |
| TCELL5:OUT14.TMIN | PCIE.LLKRXEOPN |
| TCELL5:OUT15.TMIN | PCIE.LLKRXVALIDN0 |
| TCELL5:OUT16.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN3 |
| TCELL5:OUT17.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN4 |
| TCELL5:OUT18.TMIN | PCIE.LLKRXCHCOMPLETIONAVAILABLEN5 |
| TCELL5:OUT19.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN5 |
| TCELL5:OUT20.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN6 |
| TCELL5:OUT21.TMIN | PCIE.LLKRXCHNONPOSTEDPARTIALN7 |
| TCELL5:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED17 |
| TCELL5:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED18 |
| TCELL6:IMUX.IMUX0.DELAY | PCIE.PIPEPHYSTATUSL3 |
| TCELL6:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAKL3 |
| TCELL6:IMUX.IMUX2.DELAY | PCIE.PIPERXVALIDL3 |
| TCELL6:IMUX.IMUX3.DELAY | PCIE.PIPERXCHANISALIGNEDL3 |
| TCELL6:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA47 |
| TCELL6:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA48 |
| TCELL6:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA49 |
| TCELL6:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA50 |
| TCELL6:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA40 |
| TCELL6:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA41 |
| TCELL6:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA42 |
| TCELL6:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA43 |
| TCELL6:IMUX.IMUX12.DELAY | PCIE.L0SETLINKDETECTEDPARITYERROR |
| TCELL6:IMUX.IMUX13.DELAY | PCIE.L0SETLINKMASTERDATAPARITY |
| TCELL6:IMUX.IMUX14.DELAY | PCIE.L0SETLINKRECEIVEDMASTERABORT |
| TCELL6:IMUX.IMUX15.DELAY | PCIE.L0SETLINKRECEIVEDTARGETABORT |
| TCELL6:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER24 |
| TCELL6:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER25 |
| TCELL6:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER26 |
| TCELL6:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED143 |
| TCELL6:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED144 |
| TCELL6:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED145 |
| TCELL6:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED146 |
| TCELL6:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED191 |
| TCELL6:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE0 |
| TCELL6:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE1 |
| TCELL6:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE2 |
| TCELL6:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED26 |
| TCELL6:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED27 |
| TCELL6:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED28 |
| TCELL6:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED29 |
| TCELL6:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED74 |
| TCELL6:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED75 |
| TCELL6:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED76 |
| TCELL6:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED77 |
| TCELL6:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED140 |
| TCELL6:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED141 |
| TCELL6:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED142 |
| TCELL6:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED143 |
| TCELL6:OUT0.TMIN | PCIE.MIMRXBWDATA45 |
| TCELL6:OUT1.TMIN | PCIE.MIMRXBWDATA46 |
| TCELL6:OUT2.TMIN | PCIE.MIMRXBWDATA47 |
| TCELL6:OUT3.TMIN | PCIE.MIMRXBWDATA48 |
| TCELL6:OUT4.TMIN | PCIE.MIMRXBWDATA53 |
| TCELL6:OUT5.TMIN | PCIE.MIMRXBWDATA54 |
| TCELL6:OUT6.TMIN | PCIE.MIMRXBWDATA55 |
| TCELL6:OUT7.TMIN | PCIE.MIMRXBWDATA56 |
| TCELL6:OUT8.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN0 |
| TCELL6:OUT9.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN1 |
| TCELL6:OUT10.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN2 |
| TCELL6:OUT11.TMIN | PCIE.LLKTXCHNONPOSTEDREADYN3 |
| TCELL6:OUT12.TMIN | PCIE.LLKRXDATA30 |
| TCELL6:OUT13.TMIN | PCIE.LLKRXDATA31 |
| TCELL6:OUT14.TMIN | PCIE.LLKRXDATA32 |
| TCELL6:OUT15.TMIN | PCIE.LLKRXDATA33 |
| TCELL6:OUT16.TMIN | PCIE.LLKRXSRCLASTREQN |
| TCELL6:OUT17.TMIN | PCIE.LLKRXSRCDSCN |
| TCELL6:OUT18.TMIN | PCIE.LLKRXSOFN |
| TCELL6:OUT19.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN0 |
| TCELL6:OUT20.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN1 |
| TCELL6:OUT21.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN2 |
| TCELL6:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED15 |
| TCELL6:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED16 |
| TCELL7:IMUX.IMUX0.DELAY | PCIE.MIMRXBRDATA39 |
| TCELL7:IMUX.IMUX1.DELAY | PCIE.MIMRXBRDATA40 |
| TCELL7:IMUX.IMUX2.DELAY | PCIE.MIMRXBRDATA41 |
| TCELL7:IMUX.IMUX3.DELAY | PCIE.MIMRXBRDATA42 |
| TCELL7:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA51 |
| TCELL7:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA52 |
| TCELL7:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA53 |
| TCELL7:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA54 |
| TCELL7:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA36 |
| TCELL7:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA37 |
| TCELL7:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA38 |
| TCELL7:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA39 |
| TCELL7:IMUX.IMUX12.DELAY | PCIE.L0SETCOMPLETERABORTERROR |
| TCELL7:IMUX.IMUX13.DELAY | PCIE.L0SETDETECTEDCORRERROR |
| TCELL7:IMUX.IMUX14.DELAY | PCIE.L0SETDETECTEDFATALERROR |
| TCELL7:IMUX.IMUX15.DELAY | PCIE.L0SETDETECTEDNONFATALERROR |
| TCELL7:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER27 |
| TCELL7:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER28 |
| TCELL7:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER29 |
| TCELL7:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED139 |
| TCELL7:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED140 |
| TCELL7:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED141 |
| TCELL7:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED142 |
| TCELL7:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE3 |
| TCELL7:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE4 |
| TCELL7:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE5 |
| TCELL7:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE6 |
| TCELL7:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED22 |
| TCELL7:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED23 |
| TCELL7:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED24 |
| TCELL7:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED25 |
| TCELL7:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED78 |
| TCELL7:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED79 |
| TCELL7:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED80 |
| TCELL7:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED81 |
| TCELL7:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED136 |
| TCELL7:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED137 |
| TCELL7:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED138 |
| TCELL7:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED139 |
| TCELL7:IMUX.IMUX39.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC0 |
| TCELL7:IMUX.IMUX40.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC1 |
| TCELL7:IMUX.IMUX41.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC2 |
| TCELL7:IMUX.IMUX42.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC3 |
| TCELL7:OUT0.TMIN | PCIE.MIMRXBWDATA41 |
| TCELL7:OUT1.TMIN | PCIE.MIMRXBWDATA42 |
| TCELL7:OUT2.TMIN | PCIE.MIMRXBWDATA43 |
| TCELL7:OUT3.TMIN | PCIE.MIMRXBWDATA44 |
| TCELL7:OUT4.TMIN | PCIE.MIMRXBWDATA57 |
| TCELL7:OUT5.TMIN | PCIE.MIMRXBWDATA58 |
| TCELL7:OUT6.TMIN | PCIE.MIMRXBWDATA59 |
| TCELL7:OUT7.TMIN | PCIE.MIMRXBWDATA60 |
| TCELL7:OUT8.TMIN | PCIE.LLKTXCHPOSTEDREADYN4 |
| TCELL7:OUT9.TMIN | PCIE.LLKTXCHPOSTEDREADYN5 |
| TCELL7:OUT10.TMIN | PCIE.LLKTXCHPOSTEDREADYN6 |
| TCELL7:OUT11.TMIN | PCIE.LLKTXCHPOSTEDREADYN7 |
| TCELL7:OUT12.TMIN | PCIE.LLKRXDATA34 |
| TCELL7:OUT13.TMIN | PCIE.LLKRXDATA35 |
| TCELL7:OUT14.TMIN | PCIE.LLKRXDATA36 |
| TCELL7:OUT15.TMIN | PCIE.LLKRXDATA37 |
| TCELL7:OUT16.TMIN | PCIE.LLKRXDATA62 |
| TCELL7:OUT17.TMIN | PCIE.LLKRXDATA63 |
| TCELL7:OUT18.TMIN | PCIE.LLKRXSRCRDYN |
| TCELL7:OUT19.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN3 |
| TCELL7:OUT20.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN4 |
| TCELL7:OUT21.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN5 |
| TCELL7:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED13 |
| TCELL7:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED14 |
| TCELL8:IMUX.IMUX0.DELAY | PCIE.MIMRXBRDATA35 |
| TCELL8:IMUX.IMUX1.DELAY | PCIE.MIMRXBRDATA36 |
| TCELL8:IMUX.IMUX2.DELAY | PCIE.MIMRXBRDATA37 |
| TCELL8:IMUX.IMUX3.DELAY | PCIE.MIMRXBRDATA38 |
| TCELL8:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA55 |
| TCELL8:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA56 |
| TCELL8:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA57 |
| TCELL8:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA58 |
| TCELL8:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA32 |
| TCELL8:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA33 |
| TCELL8:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA34 |
| TCELL8:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA35 |
| TCELL8:IMUX.IMUX12.DELAY | PCIE.L0FWDCORRERRIN |
| TCELL8:IMUX.IMUX13.DELAY | PCIE.L0FWDFATALERRIN |
| TCELL8:IMUX.IMUX14.DELAY | PCIE.L0FWDNONFATALERRIN |
| TCELL8:IMUX.IMUX15.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED135 |
| TCELL8:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED136 |
| TCELL8:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED137 |
| TCELL8:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED138 |
| TCELL8:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE7 |
| TCELL8:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE8 |
| TCELL8:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE9 |
| TCELL8:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE10 |
| TCELL8:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCCMPLMCCRED18 |
| TCELL8:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCCMPLMCCRED19 |
| TCELL8:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCCMPLMCCRED20 |
| TCELL8:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCCMPLMCCRED21 |
| TCELL8:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED82 |
| TCELL8:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED83 |
| TCELL8:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED84 |
| TCELL8:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED85 |
| TCELL8:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED132 |
| TCELL8:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED133 |
| TCELL8:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED134 |
| TCELL8:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED135 |
| TCELL8:IMUX.IMUX44.DELAY | PCIE.PIPERXCHANISALIGNEDL6 |
| TCELL8:IMUX.IMUX45.DELAY | PCIE.PIPERXVALIDL6 |
| TCELL8:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAKL6 |
| TCELL8:IMUX.IMUX47.DELAY | PCIE.PIPEPHYSTATUSL6 |
| TCELL8:OUT0.TMIN | PCIE.MIMRXBWDATA37 |
| TCELL8:OUT1.TMIN | PCIE.MIMRXBWDATA38 |
| TCELL8:OUT2.TMIN | PCIE.MIMRXBWDATA39 |
| TCELL8:OUT3.TMIN | PCIE.MIMRXBWDATA40 |
| TCELL8:OUT4.TMIN | PCIE.MIMRXBWDATA61 |
| TCELL8:OUT5.TMIN | PCIE.MIMRXBWDATA62 |
| TCELL8:OUT6.TMIN | PCIE.MIMRXBWDATA63 |
| TCELL8:OUT7.TMIN | PCIE.MIMRXBWADD0 |
| TCELL8:OUT8.TMIN | PCIE.LLKTXCHPOSTEDREADYN0 |
| TCELL8:OUT9.TMIN | PCIE.LLKTXCHPOSTEDREADYN1 |
| TCELL8:OUT10.TMIN | PCIE.LLKTXCHPOSTEDREADYN2 |
| TCELL8:OUT11.TMIN | PCIE.LLKTXCHPOSTEDREADYN3 |
| TCELL8:OUT12.TMIN | PCIE.LLKRXDATA38 |
| TCELL8:OUT13.TMIN | PCIE.LLKRXDATA39 |
| TCELL8:OUT14.TMIN | PCIE.LLKRXDATA40 |
| TCELL8:OUT15.TMIN | PCIE.LLKRXDATA41 |
| TCELL8:OUT16.TMIN | PCIE.LLKRXDATA59 |
| TCELL8:OUT17.TMIN | PCIE.LLKRXDATA60 |
| TCELL8:OUT18.TMIN | PCIE.LLKRXDATA61 |
| TCELL8:OUT19.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN6 |
| TCELL8:OUT20.TMIN | PCIE.LLKRXCHCOMPLETIONPARTIALN7 |
| TCELL8:OUT21.TMIN | PCIE.LLKRXCHCONFIGPARTIALN |
| TCELL8:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED11 |
| TCELL8:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED12 |
| TCELL9:IMUX.IMUX0.DELAY | PCIE.PIPERXELECIDLEL7 |
| TCELL9:IMUX.IMUX1.DELAY | PCIE.PIPERXSTATUSL70 |
| TCELL9:IMUX.IMUX2.DELAY | PCIE.PIPERXSTATUSL71 |
| TCELL9:IMUX.IMUX3.DELAY | PCIE.PIPERXSTATUSL72 |
| TCELL9:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA31 |
| TCELL9:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA32 |
| TCELL9:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA33 |
| TCELL9:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA34 |
| TCELL9:IMUX.IMUX8.DELAY | PCIE.MIMRXBRDATA59 |
| TCELL9:IMUX.IMUX9.DELAY | PCIE.MIMRXBRDATA60 |
| TCELL9:IMUX.IMUX10.DELAY | PCIE.MIMRXBRDATA61 |
| TCELL9:IMUX.IMUX11.DELAY | PCIE.MIMRXBRDATA62 |
| TCELL9:IMUX.IMUX12.DELAY | PCIE.LLKTXDATA29 |
| TCELL9:IMUX.IMUX13.DELAY | PCIE.LLKTXDATA30 |
| TCELL9:IMUX.IMUX14.DELAY | PCIE.LLKTXDATA31 |
| TCELL9:IMUX.IMUX15.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED131 |
| TCELL9:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED132 |
| TCELL9:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED133 |
| TCELL9:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED134 |
| TCELL9:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE11 |
| TCELL9:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE12 |
| TCELL9:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE13 |
| TCELL9:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE14 |
| TCELL9:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCCMPLMCCRED14 |
| TCELL9:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCCMPLMCCRED15 |
| TCELL9:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCCMPLMCCRED16 |
| TCELL9:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCCMPLMCCRED17 |
| TCELL9:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED86 |
| TCELL9:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED87 |
| TCELL9:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED88 |
| TCELL9:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED89 |
| TCELL9:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL67 |
| TCELL9:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL66 |
| TCELL9:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL65 |
| TCELL9:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL64 |
| TCELL9:OUT0.TMIN | PCIE.MIMRXBWDATA33 |
| TCELL9:OUT1.TMIN | PCIE.MIMRXBWDATA34 |
| TCELL9:OUT2.TMIN | PCIE.MIMRXBWDATA35 |
| TCELL9:OUT3.TMIN | PCIE.MIMRXBWDATA36 |
| TCELL9:OUT4.TMIN | PCIE.MIMRXBWADD1 |
| TCELL9:OUT5.TMIN | PCIE.MIMRXBWADD2 |
| TCELL9:OUT6.TMIN | PCIE.MIMRXBWADD3 |
| TCELL9:OUT7.TMIN | PCIE.MIMRXBWADD4 |
| TCELL9:OUT8.TMIN | PCIE.MIMRXBWEN |
| TCELL9:OUT9.TMIN | PCIE.MIMRXBREN |
| TCELL9:OUT10.TMIN | PCIE.LLKTXCHANSPACE8 |
| TCELL9:OUT11.TMIN | PCIE.LLKTXCHANSPACE9 |
| TCELL9:OUT12.TMIN | PCIE.LLKRXDATA42 |
| TCELL9:OUT13.TMIN | PCIE.LLKRXDATA43 |
| TCELL9:OUT14.TMIN | PCIE.LLKRXDATA44 |
| TCELL9:OUT15.TMIN | PCIE.LLKRXDATA45 |
| TCELL9:OUT16.TMIN | PCIE.LLKRXDATA56 |
| TCELL9:OUT17.TMIN | PCIE.LLKRXDATA57 |
| TCELL9:OUT18.TMIN | PCIE.LLKRXDATA58 |
| TCELL9:OUT19.TMIN | PCIE.L0RECEIVEDASSERTINTBLEGACYINT |
| TCELL9:OUT20.TMIN | PCIE.L0RECEIVEDASSERTINTCLEGACYINT |
| TCELL9:OUT21.TMIN | PCIE.L0RECEIVEDASSERTINTDLEGACYINT |
| TCELL9:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCCRED9 |
| TCELL9:OUT23.TMIN | PCIE.L0RXDLLFCCMPLMCCRED10 |
| TCELL10:IMUX.CLK0 | PCIE.CRMCORECLKRXO |
| TCELL10:IMUX.CLK1 | PCIE.CRMUSERCLKRXO |
| TCELL10:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL70 |
| TCELL10:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL71 |
| TCELL10:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL72 |
| TCELL10:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL73 |
| TCELL10:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA27 |
| TCELL10:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA28 |
| TCELL10:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA29 |
| TCELL10:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA30 |
| TCELL10:IMUX.IMUX8.DELAY | PCIE.MIMRXBRDATA63 |
| TCELL10:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA26 |
| TCELL10:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA27 |
| TCELL10:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA28 |
| TCELL10:IMUX.IMUX12.DELAY | PCIE.L0UPSTREAMRXPORTINL0S |
| TCELL10:IMUX.IMUX13.DELAY | PCIE.L0TRANSACTIONSPENDING |
| TCELL10:IMUX.IMUX14.DELAY | PCIE.L0ALLDOWNPORTSINL1 |
| TCELL10:IMUX.IMUX15.DELAY | PCIE.L0TXTLTLPDATA0 |
| TCELL10:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA1 |
| TCELL10:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA2 |
| TCELL10:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA3 |
| TCELL10:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED127 |
| TCELL10:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED128 |
| TCELL10:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED129 |
| TCELL10:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED130 |
| TCELL10:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPUPDATE15 |
| TCELL10:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED0 |
| TCELL10:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED1 |
| TCELL10:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED2 |
| TCELL10:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED10 |
| TCELL10:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED11 |
| TCELL10:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED12 |
| TCELL10:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED13 |
| TCELL10:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL63 |
| TCELL10:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL62 |
| TCELL10:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL61 |
| TCELL10:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL60 |
| TCELL10:OUT0.TMIN | PCIE.PIPETXDATAL70 |
| TCELL10:OUT1.TMIN | PCIE.PIPETXDATAL71 |
| TCELL10:OUT2.TMIN | PCIE.PIPETXDATAL72 |
| TCELL10:OUT3.TMIN | PCIE.PIPEDESKEWLANESL7 |
| TCELL10:OUT4.TMIN | PCIE.PIPERESETL7 |
| TCELL10:OUT5.TMIN | PCIE.MIMRXBWDATA0 |
| TCELL10:OUT6.TMIN | PCIE.MIMRXBWDATA1 |
| TCELL10:OUT7.TMIN | PCIE.MIMRXBWDATA29 |
| TCELL10:OUT8.TMIN | PCIE.MIMRXBWDATA30 |
| TCELL10:OUT9.TMIN | PCIE.MIMRXBWDATA31 |
| TCELL10:OUT10.TMIN | PCIE.MIMRXBWDATA32 |
| TCELL10:OUT11.TMIN | PCIE.MIMRXBWADD5 |
| TCELL10:OUT12.TMIN | PCIE.MIMRXBWADD6 |
| TCELL10:OUT13.TMIN | PCIE.MIMRXBWADD7 |
| TCELL10:OUT14.TMIN | PCIE.MIMRXBWADD8 |
| TCELL10:OUT15.TMIN | PCIE.MIMRXBRADD10 |
| TCELL10:OUT16.TMIN | PCIE.MIMRXBRADD11 |
| TCELL10:OUT17.TMIN | PCIE.MIMRXBRADD12 |
| TCELL10:OUT18.TMIN | PCIE.L0RECEIVEDDEASSERTINTALEGACYINT |
| TCELL10:OUT19.TMIN | PCIE.L0RECEIVEDDEASSERTINTBLEGACYINT |
| TCELL10:OUT20.TMIN | PCIE.L0RECEIVEDDEASSERTINTCLEGACYINT |
| TCELL10:OUT21.TMIN | PCIE.L0RXDLLTLPEND0 |
| TCELL10:OUT22.TMIN | PCIE.L0RXDLLTLPEND1 |
| TCELL10:OUT23.TMIN | PCIE.PIPERESETL6 |
| TCELL11:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL74 |
| TCELL11:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL75 |
| TCELL11:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL76 |
| TCELL11:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL77 |
| TCELL11:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA23 |
| TCELL11:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA24 |
| TCELL11:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA25 |
| TCELL11:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA26 |
| TCELL11:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA22 |
| TCELL11:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA23 |
| TCELL11:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA24 |
| TCELL11:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA25 |
| TCELL11:IMUX.IMUX12.DELAY | PCIE.L0PORTNUMBER7 |
| TCELL11:IMUX.IMUX13.DELAY | PCIE.L0SENDUNLOCKMESSAGE |
| TCELL11:IMUX.IMUX14.DELAY | PCIE.L0ALLDOWNRXPORTSINL0S |
| TCELL11:IMUX.IMUX15.DELAY | PCIE.L0TXTLTLPDATA4 |
| TCELL11:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA5 |
| TCELL11:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA6 |
| TCELL11:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA7 |
| TCELL11:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED123 |
| TCELL11:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED124 |
| TCELL11:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED125 |
| TCELL11:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED126 |
| TCELL11:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCPOSTORDCRED3 |
| TCELL11:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED4 |
| TCELL11:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED5 |
| TCELL11:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED6 |
| TCELL11:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED6 |
| TCELL11:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCCMPLMCCRED7 |
| TCELL11:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED8 |
| TCELL11:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED9 |
| TCELL11:IMUX.IMUX44.DELAY | PCIE.PIPERXSTATUSL62 |
| TCELL11:IMUX.IMUX45.DELAY | PCIE.PIPERXSTATUSL61 |
| TCELL11:IMUX.IMUX46.DELAY | PCIE.PIPERXSTATUSL60 |
| TCELL11:IMUX.IMUX47.DELAY | PCIE.PIPERXELECIDLEL6 |
| TCELL11:OUT0.TMIN | PCIE.PIPETXDATAL73 |
| TCELL11:OUT1.TMIN | PCIE.PIPETXDATAL74 |
| TCELL11:OUT2.TMIN | PCIE.PIPETXDATAL75 |
| TCELL11:OUT3.TMIN | PCIE.PIPETXDATAL76 |
| TCELL11:OUT4.TMIN | PCIE.PIPETXCOMPLIANCEL7 |
| TCELL11:OUT5.TMIN | PCIE.PIPERXPOLARITYL7 |
| TCELL11:OUT6.TMIN | PCIE.PIPEPOWERDOWNL70 |
| TCELL11:OUT7.TMIN | PCIE.PIPEPOWERDOWNL71 |
| TCELL11:OUT8.TMIN | PCIE.MIMRXBWDATA2 |
| TCELL11:OUT9.TMIN | PCIE.MIMRXBWDATA3 |
| TCELL11:OUT10.TMIN | PCIE.MIMRXBWDATA4 |
| TCELL11:OUT11.TMIN | PCIE.MIMRXBWDATA5 |
| TCELL11:OUT12.TMIN | PCIE.MIMRXBWDATA26 |
| TCELL11:OUT13.TMIN | PCIE.MIMRXBWDATA27 |
| TCELL11:OUT14.TMIN | PCIE.MIMRXBWDATA28 |
| TCELL11:OUT15.TMIN | PCIE.L0RECEIVEDDEASSERTINTDLEGACYINT |
| TCELL11:OUT16.TMIN | PCIE.L0RXDLLFCCMPLMCCRED5 |
| TCELL11:OUT17.TMIN | PCIE.L0RXDLLFCCMPLMCCRED6 |
| TCELL11:OUT18.TMIN | PCIE.L0RXDLLFCCMPLMCCRED7 |
| TCELL11:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCCRED8 |
| TCELL11:OUT20.TMIN | PCIE.PIPEDESKEWLANESL6 |
| TCELL11:OUT21.TMIN | PCIE.PIPEPOWERDOWNL61 |
| TCELL11:OUT22.TMIN | PCIE.PIPEPOWERDOWNL60 |
| TCELL11:OUT23.TMIN | PCIE.PIPERXPOLARITYL6 |
| TCELL12:IMUX.IMUX0.DELAY | PCIE.PIPEPHYSTATUSL7 |
| TCELL12:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAKL7 |
| TCELL12:IMUX.IMUX2.DELAY | PCIE.PIPERXVALIDL7 |
| TCELL12:IMUX.IMUX3.DELAY | PCIE.PIPERXCHANISALIGNEDL7 |
| TCELL12:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA19 |
| TCELL12:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA20 |
| TCELL12:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA21 |
| TCELL12:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA22 |
| TCELL12:IMUX.IMUX8.DELAY | PCIE.LLKTXDATA18 |
| TCELL12:IMUX.IMUX9.DELAY | PCIE.LLKTXDATA19 |
| TCELL12:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA20 |
| TCELL12:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA21 |
| TCELL12:IMUX.IMUX12.DELAY | PCIE.L0PORTNUMBER3 |
| TCELL12:IMUX.IMUX13.DELAY | PCIE.L0PORTNUMBER4 |
| TCELL12:IMUX.IMUX14.DELAY | PCIE.L0PORTNUMBER5 |
| TCELL12:IMUX.IMUX15.DELAY | PCIE.L0PORTNUMBER6 |
| TCELL12:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER30 |
| TCELL12:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER31 |
| TCELL12:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER32 |
| TCELL12:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA8 |
| TCELL12:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPDATA9 |
| TCELL12:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPDATA10 |
| TCELL12:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPDATA11 |
| TCELL12:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED119 |
| TCELL12:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED120 |
| TCELL12:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED121 |
| TCELL12:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED122 |
| TCELL12:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED7 |
| TCELL12:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED8 |
| TCELL12:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED9 |
| TCELL12:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED10 |
| TCELL12:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED2 |
| TCELL12:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED3 |
| TCELL12:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED4 |
| TCELL12:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED5 |
| TCELL12:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED90 |
| TCELL12:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED91 |
| TCELL12:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED92 |
| TCELL12:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED93 |
| TCELL12:OUT0.TMIN | PCIE.PIPETXDATAL77 |
| TCELL12:OUT1.TMIN | PCIE.PIPETXDATAKL7 |
| TCELL12:OUT2.TMIN | PCIE.PIPETXELECIDLEL7 |
| TCELL12:OUT3.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL7 |
| TCELL12:OUT4.TMIN | PCIE.MIMRXBWDATA6 |
| TCELL12:OUT5.TMIN | PCIE.MIMRXBWDATA7 |
| TCELL12:OUT6.TMIN | PCIE.MIMRXBWDATA8 |
| TCELL12:OUT7.TMIN | PCIE.MIMRXBWDATA9 |
| TCELL12:OUT8.TMIN | PCIE.MIMRXBWDATA22 |
| TCELL12:OUT9.TMIN | PCIE.MIMRXBWDATA23 |
| TCELL12:OUT10.TMIN | PCIE.MIMRXBWDATA24 |
| TCELL12:OUT11.TMIN | PCIE.MIMRXBWDATA25 |
| TCELL12:OUT12.TMIN | PCIE.MIMRXBWADD9 |
| TCELL12:OUT13.TMIN | PCIE.MIMRXBWADD10 |
| TCELL12:OUT14.TMIN | PCIE.MIMRXBWADD11 |
| TCELL12:OUT15.TMIN | PCIE.L0RXDLLFCCMPLMCCRED1 |
| TCELL12:OUT16.TMIN | PCIE.L0RXDLLFCCMPLMCCRED2 |
| TCELL12:OUT17.TMIN | PCIE.L0RXDLLFCCMPLMCCRED3 |
| TCELL12:OUT18.TMIN | PCIE.L0RXDLLFCCMPLMCCRED4 |
| TCELL12:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE0 |
| TCELL12:OUT20.TMIN | PCIE.PIPETXCOMPLIANCEL6 |
| TCELL12:OUT21.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL6 |
| TCELL12:OUT22.TMIN | PCIE.PIPETXELECIDLEL6 |
| TCELL12:OUT23.TMIN | PCIE.PIPETXDATAKL6 |
| TCELL13:IMUX.IMUX0.DELAY | PCIE.MIMRXBRDATA0 |
| TCELL13:IMUX.IMUX1.DELAY | PCIE.MIMRXBRDATA1 |
| TCELL13:IMUX.IMUX2.DELAY | PCIE.MIMRXBRDATA2 |
| TCELL13:IMUX.IMUX3.DELAY | PCIE.MIMRXBRDATA3 |
| TCELL13:IMUX.IMUX4.DELAY | PCIE.MIMRXBRDATA4 |
| TCELL13:IMUX.IMUX5.DELAY | PCIE.MIMRXBRDATA5 |
| TCELL13:IMUX.IMUX6.DELAY | PCIE.MIMRXBRDATA6 |
| TCELL13:IMUX.IMUX7.DELAY | PCIE.MIMRXBRDATA7 |
| TCELL13:IMUX.IMUX8.DELAY | PCIE.MIMRXBRDATA8 |
| TCELL13:IMUX.IMUX9.DELAY | PCIE.MIMRXBRDATA9 |
| TCELL13:IMUX.IMUX10.DELAY | PCIE.MIMRXBRDATA10 |
| TCELL13:IMUX.IMUX11.DELAY | PCIE.MIMRXBRDATA11 |
| TCELL13:IMUX.IMUX12.DELAY | PCIE.MIMRXBRDATA12 |
| TCELL13:IMUX.IMUX13.DELAY | PCIE.MIMRXBRDATA13 |
| TCELL13:IMUX.IMUX14.DELAY | PCIE.MIMRXBRDATA14 |
| TCELL13:IMUX.IMUX15.DELAY | PCIE.L0TXTLTLPDATA12 |
| TCELL13:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA13 |
| TCELL13:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA14 |
| TCELL13:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA15 |
| TCELL13:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED115 |
| TCELL13:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED116 |
| TCELL13:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED117 |
| TCELL13:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED118 |
| TCELL13:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCPOSTORDCRED11 |
| TCELL13:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED12 |
| TCELL13:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED13 |
| TCELL13:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED14 |
| TCELL13:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE14 |
| TCELL13:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE15 |
| TCELL13:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCCMPLMCCRED0 |
| TCELL13:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCCMPLMCCRED1 |
| TCELL13:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCCMPLMCCRED94 |
| TCELL13:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED95 |
| TCELL13:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED96 |
| TCELL13:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED97 |
| TCELL13:IMUX.IMUX44.DELAY | PCIE.PIPERXCHANISALIGNEDL2 |
| TCELL13:IMUX.IMUX45.DELAY | PCIE.PIPERXVALIDL2 |
| TCELL13:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAKL2 |
| TCELL13:IMUX.IMUX47.DELAY | PCIE.PIPEPHYSTATUSL2 |
| TCELL13:OUT0.TMIN | PCIE.MIMRXBWDATA10 |
| TCELL13:OUT1.TMIN | PCIE.MIMRXBWDATA11 |
| TCELL13:OUT2.TMIN | PCIE.MIMRXBWDATA12 |
| TCELL13:OUT3.TMIN | PCIE.MIMRXBWDATA13 |
| TCELL13:OUT4.TMIN | PCIE.MIMRXBWDATA18 |
| TCELL13:OUT5.TMIN | PCIE.MIMRXBWDATA19 |
| TCELL13:OUT6.TMIN | PCIE.MIMRXBWDATA20 |
| TCELL13:OUT7.TMIN | PCIE.MIMRXBWDATA21 |
| TCELL13:OUT8.TMIN | PCIE.MIMRXBWADD12 |
| TCELL13:OUT9.TMIN | PCIE.MIMRXBRADD0 |
| TCELL13:OUT10.TMIN | PCIE.MIMRXBRADD1 |
| TCELL13:OUT11.TMIN | PCIE.MIMRXBRADD2 |
| TCELL13:OUT12.TMIN | PCIE.MIMRXBRADD7 |
| TCELL13:OUT13.TMIN | PCIE.MIMRXBRADD8 |
| TCELL13:OUT14.TMIN | PCIE.MIMRXBRADD9 |
| TCELL13:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE5 |
| TCELL13:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE6 |
| TCELL13:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE7 |
| TCELL13:OUT18.TMIN | PCIE.L0RXDLLFCCMPLMCCRED0 |
| TCELL13:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE1 |
| TCELL13:OUT20.TMIN | PCIE.PIPETXDATAL67 |
| TCELL13:OUT21.TMIN | PCIE.PIPETXDATAL66 |
| TCELL13:OUT22.TMIN | PCIE.PIPETXDATAL65 |
| TCELL13:OUT23.TMIN | PCIE.PIPETXDATAL64 |
| TCELL14:IMUX.IMUX0.DELAY | PCIE.MIMRXBRDATA15 |
| TCELL14:IMUX.IMUX1.DELAY | PCIE.MIMRXBRDATA16 |
| TCELL14:IMUX.IMUX2.DELAY | PCIE.MIMRXBRDATA17 |
| TCELL14:IMUX.IMUX3.DELAY | PCIE.MIMRXBRDATA18 |
| TCELL14:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA14 |
| TCELL14:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA15 |
| TCELL14:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA16 |
| TCELL14:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA17 |
| TCELL14:IMUX.IMUX8.DELAY | PCIE.L0CFGLINKDISABLE |
| TCELL14:IMUX.IMUX9.DELAY | PCIE.L0PORTNUMBER0 |
| TCELL14:IMUX.IMUX10.DELAY | PCIE.L0PORTNUMBER1 |
| TCELL14:IMUX.IMUX11.DELAY | PCIE.L0PORTNUMBER2 |
| TCELL14:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER33 |
| TCELL14:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER34 |
| TCELL14:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER35 |
| TCELL14:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER36 |
| TCELL14:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA16 |
| TCELL14:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA17 |
| TCELL14:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA18 |
| TCELL14:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA19 |
| TCELL14:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED111 |
| TCELL14:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED112 |
| TCELL14:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED113 |
| TCELL14:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED114 |
| TCELL14:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED15 |
| TCELL14:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED16 |
| TCELL14:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED17 |
| TCELL14:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED18 |
| TCELL14:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE10 |
| TCELL14:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE11 |
| TCELL14:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE12 |
| TCELL14:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE13 |
| TCELL14:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED98 |
| TCELL14:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED99 |
| TCELL14:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED100 |
| TCELL14:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL27 |
| TCELL14:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL26 |
| TCELL14:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL25 |
| TCELL14:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL24 |
| TCELL14:OUT0.TMIN | PCIE.MIMRXBWDATA14 |
| TCELL14:OUT1.TMIN | PCIE.MIMRXBWDATA15 |
| TCELL14:OUT2.TMIN | PCIE.MIMRXBWDATA16 |
| TCELL14:OUT3.TMIN | PCIE.MIMRXBWDATA17 |
| TCELL14:OUT4.TMIN | PCIE.MIMRXBRADD3 |
| TCELL14:OUT5.TMIN | PCIE.MIMRXBRADD4 |
| TCELL14:OUT6.TMIN | PCIE.MIMRXBRADD5 |
| TCELL14:OUT7.TMIN | PCIE.MIMRXBRADD6 |
| TCELL14:OUT8.TMIN | PCIE.LLKTXCHANSPACE4 |
| TCELL14:OUT9.TMIN | PCIE.LLKTXCHANSPACE5 |
| TCELL14:OUT10.TMIN | PCIE.LLKTXCHANSPACE6 |
| TCELL14:OUT11.TMIN | PCIE.LLKTXCHANSPACE7 |
| TCELL14:OUT12.TMIN | PCIE.LLKRXDATA46 |
| TCELL14:OUT13.TMIN | PCIE.LLKRXDATA47 |
| TCELL14:OUT14.TMIN | PCIE.LLKRXDATA48 |
| TCELL14:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE1 |
| TCELL14:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE2 |
| TCELL14:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE3 |
| TCELL14:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE4 |
| TCELL14:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE2 |
| TCELL14:OUT20.TMIN | PCIE.PIPETXDATAL63 |
| TCELL14:OUT21.TMIN | PCIE.PIPETXDATAL62 |
| TCELL14:OUT22.TMIN | PCIE.PIPETXDATAL61 |
| TCELL14:OUT23.TMIN | PCIE.PIPETXDATAL60 |
| TCELL15:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA0 |
| TCELL15:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA1 |
| TCELL15:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA2 |
| TCELL15:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA3 |
| TCELL15:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA10 |
| TCELL15:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA11 |
| TCELL15:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA12 |
| TCELL15:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA13 |
| TCELL15:IMUX.IMUX8.DELAY | PCIE.L0CFGNEGOTIATEDMAXP1 |
| TCELL15:IMUX.IMUX9.DELAY | PCIE.L0CFGNEGOTIATEDMAXP2 |
| TCELL15:IMUX.IMUX10.DELAY | PCIE.L0CFGDISABLESCRAMBLE |
| TCELL15:IMUX.IMUX11.DELAY | PCIE.L0CFGEXTENDEDSYNC |
| TCELL15:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER37 |
| TCELL15:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER38 |
| TCELL15:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER39 |
| TCELL15:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER40 |
| TCELL15:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA20 |
| TCELL15:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA21 |
| TCELL15:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA22 |
| TCELL15:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA23 |
| TCELL15:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED107 |
| TCELL15:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED108 |
| TCELL15:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED109 |
| TCELL15:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED110 |
| TCELL15:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED19 |
| TCELL15:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED20 |
| TCELL15:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED21 |
| TCELL15:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED22 |
| TCELL15:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE6 |
| TCELL15:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE7 |
| TCELL15:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE8 |
| TCELL15:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE9 |
| TCELL15:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL23 |
| TCELL15:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL22 |
| TCELL15:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL21 |
| TCELL15:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL20 |
| TCELL15:OUT0.TMIN | PCIE.MIMTXBWDATA0 |
| TCELL15:OUT1.TMIN | PCIE.MIMTXBWDATA1 |
| TCELL15:OUT2.TMIN | PCIE.MIMTXBWDATA2 |
| TCELL15:OUT3.TMIN | PCIE.MIMTXBWADD6 |
| TCELL15:OUT4.TMIN | PCIE.MIMTXBWADD7 |
| TCELL15:OUT5.TMIN | PCIE.MIMTXBWADD8 |
| TCELL15:OUT6.TMIN | PCIE.MIMTXBWADD9 |
| TCELL15:OUT7.TMIN | PCIE.LLKTXCHANSPACE0 |
| TCELL15:OUT8.TMIN | PCIE.LLKTXCHANSPACE1 |
| TCELL15:OUT9.TMIN | PCIE.LLKTXCHANSPACE2 |
| TCELL15:OUT10.TMIN | PCIE.LLKTXCHANSPACE3 |
| TCELL15:OUT11.TMIN | PCIE.LLKRXDATA49 |
| TCELL15:OUT12.TMIN | PCIE.LLKRXDATA50 |
| TCELL15:OUT13.TMIN | PCIE.LLKRXDATA51 |
| TCELL15:OUT14.TMIN | PCIE.LLKRXDATA52 |
| TCELL15:OUT15.TMIN | PCIE.LLKRXDATA53 |
| TCELL15:OUT16.TMIN | PCIE.LLKRXDATA54 |
| TCELL15:OUT17.TMIN | PCIE.LLKRXDATA55 |
| TCELL15:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED21 |
| TCELL15:OUT19.TMIN | PCIE.L0RXDLLFCPOSTORDCRED22 |
| TCELL15:OUT20.TMIN | PCIE.L0RXDLLFCPOSTORDCRED23 |
| TCELL15:OUT21.TMIN | PCIE.L0RXDLLFCPOSTORDUPDATE0 |
| TCELL15:OUT22.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE3 |
| TCELL15:OUT23.TMIN | PCIE.PIPERESETL2 |
| TCELL16:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA4 |
| TCELL16:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA5 |
| TCELL16:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA6 |
| TCELL16:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA7 |
| TCELL16:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA6 |
| TCELL16:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA7 |
| TCELL16:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA8 |
| TCELL16:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA9 |
| TCELL16:IMUX.IMUX8.DELAY | PCIE.L0CFGVCENABLE5 |
| TCELL16:IMUX.IMUX9.DELAY | PCIE.L0CFGVCENABLE6 |
| TCELL16:IMUX.IMUX10.DELAY | PCIE.L0CFGVCENABLE7 |
| TCELL16:IMUX.IMUX11.DELAY | PCIE.L0CFGNEGOTIATEDMAXP0 |
| TCELL16:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER41 |
| TCELL16:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER42 |
| TCELL16:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER43 |
| TCELL16:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER44 |
| TCELL16:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA24 |
| TCELL16:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA25 |
| TCELL16:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA26 |
| TCELL16:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA27 |
| TCELL16:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED103 |
| TCELL16:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED104 |
| TCELL16:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED105 |
| TCELL16:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED106 |
| TCELL16:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED23 |
| TCELL16:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED24 |
| TCELL16:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED25 |
| TCELL16:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED26 |
| TCELL16:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE2 |
| TCELL16:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE3 |
| TCELL16:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE4 |
| TCELL16:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE5 |
| TCELL16:IMUX.IMUX44.DELAY | PCIE.PIPERXSTATUSL22 |
| TCELL16:IMUX.IMUX45.DELAY | PCIE.PIPERXSTATUSL21 |
| TCELL16:IMUX.IMUX46.DELAY | PCIE.PIPERXSTATUSL20 |
| TCELL16:IMUX.IMUX47.DELAY | PCIE.PIPERXELECIDLEL2 |
| TCELL16:OUT0.TMIN | PCIE.MIMTXBWDATA3 |
| TCELL16:OUT1.TMIN | PCIE.MIMTXBWDATA4 |
| TCELL16:OUT2.TMIN | PCIE.MIMTXBWDATA5 |
| TCELL16:OUT3.TMIN | PCIE.MIMTXBWDATA6 |
| TCELL16:OUT4.TMIN | PCIE.MIMTXBWADD2 |
| TCELL16:OUT5.TMIN | PCIE.MIMTXBWADD3 |
| TCELL16:OUT6.TMIN | PCIE.MIMTXBWADD4 |
| TCELL16:OUT7.TMIN | PCIE.MIMTXBWADD5 |
| TCELL16:OUT8.TMIN | PCIE.MIMTXBWADD10 |
| TCELL16:OUT9.TMIN | PCIE.MIMTXBWADD11 |
| TCELL16:OUT10.TMIN | PCIE.MIMTXBWADD12 |
| TCELL16:OUT11.TMIN | PCIE.MIMTXBRADD0 |
| TCELL16:OUT12.TMIN | PCIE.LLKTCSTATUS6 |
| TCELL16:OUT13.TMIN | PCIE.LLKTCSTATUS7 |
| TCELL16:OUT14.TMIN | PCIE.LLKTXDSTRDYN |
| TCELL16:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDCRED17 |
| TCELL16:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDCRED18 |
| TCELL16:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDCRED19 |
| TCELL16:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED20 |
| TCELL16:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE4 |
| TCELL16:OUT20.TMIN | PCIE.PIPEDESKEWLANESL2 |
| TCELL16:OUT21.TMIN | PCIE.PIPEPOWERDOWNL21 |
| TCELL16:OUT22.TMIN | PCIE.PIPEPOWERDOWNL20 |
| TCELL16:OUT23.TMIN | PCIE.PIPERXPOLARITYL2 |
| TCELL17:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA8 |
| TCELL17:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA9 |
| TCELL17:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA10 |
| TCELL17:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA11 |
| TCELL17:IMUX.IMUX4.DELAY | PCIE.LLKTXDATA2 |
| TCELL17:IMUX.IMUX5.DELAY | PCIE.LLKTXDATA3 |
| TCELL17:IMUX.IMUX6.DELAY | PCIE.LLKTXDATA4 |
| TCELL17:IMUX.IMUX7.DELAY | PCIE.LLKTXDATA5 |
| TCELL17:IMUX.IMUX8.DELAY | PCIE.L0CFGVCENABLE1 |
| TCELL17:IMUX.IMUX9.DELAY | PCIE.L0CFGVCENABLE2 |
| TCELL17:IMUX.IMUX10.DELAY | PCIE.L0CFGVCENABLE3 |
| TCELL17:IMUX.IMUX11.DELAY | PCIE.L0CFGVCENABLE4 |
| TCELL17:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER45 |
| TCELL17:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER46 |
| TCELL17:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER47 |
| TCELL17:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER48 |
| TCELL17:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA28 |
| TCELL17:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA29 |
| TCELL17:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA30 |
| TCELL17:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA31 |
| TCELL17:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED99 |
| TCELL17:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED100 |
| TCELL17:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED101 |
| TCELL17:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED102 |
| TCELL17:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED27 |
| TCELL17:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED28 |
| TCELL17:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED29 |
| TCELL17:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED30 |
| TCELL17:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED158 |
| TCELL17:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED159 |
| TCELL17:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE0 |
| TCELL17:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDUPDATE1 |
| TCELL17:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED101 |
| TCELL17:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED102 |
| TCELL17:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED103 |
| TCELL17:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED104 |
| TCELL17:OUT0.TMIN | PCIE.MIMTXBWDATA7 |
| TCELL17:OUT1.TMIN | PCIE.MIMTXBWDATA8 |
| TCELL17:OUT2.TMIN | PCIE.MIMTXBWDATA9 |
| TCELL17:OUT3.TMIN | PCIE.MIMTXBWDATA10 |
| TCELL17:OUT4.TMIN | PCIE.MIMTXBWDATA62 |
| TCELL17:OUT5.TMIN | PCIE.MIMTXBWDATA63 |
| TCELL17:OUT6.TMIN | PCIE.MIMTXBWADD0 |
| TCELL17:OUT7.TMIN | PCIE.MIMTXBWADD1 |
| TCELL17:OUT8.TMIN | PCIE.MIMTXBRADD1 |
| TCELL17:OUT9.TMIN | PCIE.MIMTXBRADD2 |
| TCELL17:OUT10.TMIN | PCIE.MIMTXBRADD3 |
| TCELL17:OUT11.TMIN | PCIE.MIMTXBRADD4 |
| TCELL17:OUT12.TMIN | PCIE.LLKTCSTATUS3 |
| TCELL17:OUT13.TMIN | PCIE.LLKTCSTATUS4 |
| TCELL17:OUT14.TMIN | PCIE.LLKTCSTATUS5 |
| TCELL17:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDCRED13 |
| TCELL17:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDCRED14 |
| TCELL17:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDCRED15 |
| TCELL17:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED16 |
| TCELL17:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE5 |
| TCELL17:OUT20.TMIN | PCIE.PIPETXCOMPLIANCEL2 |
| TCELL17:OUT21.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL2 |
| TCELL17:OUT22.TMIN | PCIE.PIPETXELECIDLEL2 |
| TCELL17:OUT23.TMIN | PCIE.PIPETXDATAKL2 |
| TCELL18:IMUX.CLK0 | PCIE.CRMCORECLKTXO |
| TCELL18:IMUX.CLK1 | PCIE.CRMUSERCLKTXO |
| TCELL18:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA12 |
| TCELL18:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA13 |
| TCELL18:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA14 |
| TCELL18:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA15 |
| TCELL18:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA60 |
| TCELL18:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA61 |
| TCELL18:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA62 |
| TCELL18:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA63 |
| TCELL18:IMUX.IMUX8.DELAY | PCIE.L0ASPORTCOUNT5 |
| TCELL18:IMUX.IMUX9.DELAY | PCIE.L0ASPORTCOUNT6 |
| TCELL18:IMUX.IMUX10.DELAY | PCIE.L0ASPORTCOUNT7 |
| TCELL18:IMUX.IMUX11.DELAY | PCIE.L0CFGVCENABLE0 |
| TCELL18:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER49 |
| TCELL18:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER50 |
| TCELL18:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER51 |
| TCELL18:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER52 |
| TCELL18:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA32 |
| TCELL18:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA33 |
| TCELL18:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA34 |
| TCELL18:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA35 |
| TCELL18:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED95 |
| TCELL18:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED96 |
| TCELL18:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED97 |
| TCELL18:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED98 |
| TCELL18:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED31 |
| TCELL18:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED32 |
| TCELL18:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED33 |
| TCELL18:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED34 |
| TCELL18:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED154 |
| TCELL18:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED155 |
| TCELL18:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED156 |
| TCELL18:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED157 |
| TCELL18:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED105 |
| TCELL18:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED106 |
| TCELL18:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED107 |
| TCELL18:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED108 |
| TCELL18:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED131 |
| TCELL18:IMUX.IMUX37.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC4 |
| TCELL18:IMUX.IMUX38.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC5 |
| TCELL18:OUT0.TMIN | PCIE.MIMTXBWDATA11 |
| TCELL18:OUT1.TMIN | PCIE.MIMTXBWDATA12 |
| TCELL18:OUT2.TMIN | PCIE.MIMTXBWDATA13 |
| TCELL18:OUT3.TMIN | PCIE.MIMTXBWDATA14 |
| TCELL18:OUT4.TMIN | PCIE.MIMTXBWDATA58 |
| TCELL18:OUT5.TMIN | PCIE.MIMTXBWDATA59 |
| TCELL18:OUT6.TMIN | PCIE.MIMTXBWDATA60 |
| TCELL18:OUT7.TMIN | PCIE.MIMTXBWDATA61 |
| TCELL18:OUT8.TMIN | PCIE.MIMTXBRADD5 |
| TCELL18:OUT9.TMIN | PCIE.MIMTXBRADD6 |
| TCELL18:OUT10.TMIN | PCIE.MIMTXBRADD7 |
| TCELL18:OUT11.TMIN | PCIE.MIMTXBRADD8 |
| TCELL18:OUT12.TMIN | PCIE.LLKTCSTATUS0 |
| TCELL18:OUT13.TMIN | PCIE.LLKTCSTATUS1 |
| TCELL18:OUT14.TMIN | PCIE.LLKTCSTATUS2 |
| TCELL18:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDCRED9 |
| TCELL18:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDCRED10 |
| TCELL18:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDCRED11 |
| TCELL18:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED12 |
| TCELL18:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE6 |
| TCELL18:OUT20.TMIN | PCIE.PIPETXDATAL27 |
| TCELL18:OUT21.TMIN | PCIE.PIPETXDATAL26 |
| TCELL18:OUT22.TMIN | PCIE.PIPETXDATAL25 |
| TCELL18:OUT23.TMIN | PCIE.PIPETXDATAL24 |
| TCELL19:IMUX.CLK0 | PCIE.CRMCORECLK |
| TCELL19:IMUX.CLK1 | PCIE.CRMUSERCLK |
| TCELL19:IMUX.CTRL0.SITE | PCIE.CRMURSTN |
| TCELL19:IMUX.CTRL1.SITE | PCIE.CRMNVRSTN |
| TCELL19:IMUX.CTRL2.SITE | PCIE.CRMMGMTRSTN |
| TCELL19:IMUX.CTRL3.SITE | PCIE.CRMUSERCFGRSTN |
| TCELL19:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA16 |
| TCELL19:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA17 |
| TCELL19:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA18 |
| TCELL19:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA19 |
| TCELL19:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA56 |
| TCELL19:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA57 |
| TCELL19:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA58 |
| TCELL19:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA59 |
| TCELL19:IMUX.IMUX8.DELAY | PCIE.CRMTXHOTRESETN |
| TCELL19:IMUX.IMUX9.DELAY | PCIE.CRMCFGBRIDGEHOTRESET |
| TCELL19:IMUX.IMUX10.DELAY | PCIE.LLKTXDATA0 |
| TCELL19:IMUX.IMUX11.DELAY | PCIE.LLKTXDATA1 |
| TCELL19:IMUX.IMUX12.DELAY | PCIE.L0ASPORTCOUNT1 |
| TCELL19:IMUX.IMUX13.DELAY | PCIE.L0ASPORTCOUNT2 |
| TCELL19:IMUX.IMUX14.DELAY | PCIE.L0ASPORTCOUNT3 |
| TCELL19:IMUX.IMUX15.DELAY | PCIE.L0ASPORTCOUNT4 |
| TCELL19:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER53 |
| TCELL19:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER54 |
| TCELL19:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER55 |
| TCELL19:IMUX.IMUX19.DELAY | PCIE.L0PACKETHEADERFROMUSER56 |
| TCELL19:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPDATA36 |
| TCELL19:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPDATA37 |
| TCELL19:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPDATA38 |
| TCELL19:IMUX.IMUX23.DELAY | PCIE.L0TXTLTLPDATA39 |
| TCELL19:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED91 |
| TCELL19:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED92 |
| TCELL19:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED93 |
| TCELL19:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED94 |
| TCELL19:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED35 |
| TCELL19:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED36 |
| TCELL19:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED37 |
| TCELL19:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED38 |
| TCELL19:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED150 |
| TCELL19:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED151 |
| TCELL19:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED152 |
| TCELL19:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED153 |
| TCELL19:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED109 |
| TCELL19:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED110 |
| TCELL19:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED111 |
| TCELL19:IMUX.IMUX39.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC6 |
| TCELL19:IMUX.IMUX40.DELAY | PCIE.L0RXTLTLPNONINITIALIZEDVC7 |
| TCELL19:OUT0.TMIN | PCIE.MIMTXBWDATA15 |
| TCELL19:OUT1.TMIN | PCIE.MIMTXBWDATA16 |
| TCELL19:OUT2.TMIN | PCIE.MIMTXBWDATA17 |
| TCELL19:OUT3.TMIN | PCIE.MIMTXBWDATA18 |
| TCELL19:OUT4.TMIN | PCIE.MIMTXBWDATA54 |
| TCELL19:OUT5.TMIN | PCIE.MIMTXBWDATA55 |
| TCELL19:OUT6.TMIN | PCIE.MIMTXBWDATA56 |
| TCELL19:OUT7.TMIN | PCIE.MIMTXBWDATA57 |
| TCELL19:OUT8.TMIN | PCIE.MIMTXBRADD9 |
| TCELL19:OUT9.TMIN | PCIE.MIMTXBRADD10 |
| TCELL19:OUT10.TMIN | PCIE.MIMTXBRADD11 |
| TCELL19:OUT11.TMIN | PCIE.MIMTXBRADD12 |
| TCELL19:OUT12.TMIN | PCIE.CRMRXHOTRESETN |
| TCELL19:OUT13.TMIN | PCIE.CRMDOHOTRESETN |
| TCELL19:OUT14.TMIN | PCIE.CRMPWRSOFTRESETN |
| TCELL19:OUT15.TMIN | PCIE.L0RXDLLFCPOSTORDCRED5 |
| TCELL19:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDCRED6 |
| TCELL19:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDCRED7 |
| TCELL19:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED8 |
| TCELL19:OUT19.TMIN | PCIE.L0RXDLLFCCMPLMCUPDATE7 |
| TCELL19:OUT20.TMIN | PCIE.PIPETXDATAL23 |
| TCELL19:OUT21.TMIN | PCIE.PIPETXDATAL22 |
| TCELL19:OUT22.TMIN | PCIE.PIPETXDATAL21 |
| TCELL19:OUT23.TMIN | PCIE.PIPETXDATAL20 |
| TCELL20:IMUX.CTRL0.SITE | PCIE.CRMMACRSTN |
| TCELL20:IMUX.CTRL1.SITE | PCIE.CRMLINKRSTN |
| TCELL20:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA20 |
| TCELL20:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA21 |
| TCELL20:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA22 |
| TCELL20:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA23 |
| TCELL20:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA52 |
| TCELL20:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA53 |
| TCELL20:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA54 |
| TCELL20:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA55 |
| TCELL20:IMUX.IMUX8.DELAY | PCIE.L0ASTURNPOOLBITSCONSUMED0 |
| TCELL20:IMUX.IMUX9.DELAY | PCIE.L0ASTURNPOOLBITSCONSUMED1 |
| TCELL20:IMUX.IMUX10.DELAY | PCIE.L0ASTURNPOOLBITSCONSUMED2 |
| TCELL20:IMUX.IMUX11.DELAY | PCIE.L0ASPORTCOUNT0 |
| TCELL20:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER57 |
| TCELL20:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER58 |
| TCELL20:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER59 |
| TCELL20:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER60 |
| TCELL20:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA40 |
| TCELL20:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA41 |
| TCELL20:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA42 |
| TCELL20:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA43 |
| TCELL20:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED87 |
| TCELL20:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED88 |
| TCELL20:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED89 |
| TCELL20:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED90 |
| TCELL20:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED39 |
| TCELL20:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED40 |
| TCELL20:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED41 |
| TCELL20:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED42 |
| TCELL20:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED146 |
| TCELL20:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED147 |
| TCELL20:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED148 |
| TCELL20:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED149 |
| TCELL20:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED112 |
| TCELL20:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED113 |
| TCELL20:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED114 |
| TCELL20:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED115 |
| TCELL20:OUT0.TMIN | PCIE.PIPETXDATAL10 |
| TCELL20:OUT1.TMIN | PCIE.PIPETXDATAL11 |
| TCELL20:OUT2.TMIN | PCIE.PIPETXDATAL12 |
| TCELL20:OUT3.TMIN | PCIE.PIPETXDATAL13 |
| TCELL20:OUT4.TMIN | PCIE.MIMTXBWDATA19 |
| TCELL20:OUT5.TMIN | PCIE.MIMTXBWDATA20 |
| TCELL20:OUT6.TMIN | PCIE.MIMTXBWDATA21 |
| TCELL20:OUT7.TMIN | PCIE.MIMTXBWDATA22 |
| TCELL20:OUT8.TMIN | PCIE.MIMTXBWDATA50 |
| TCELL20:OUT9.TMIN | PCIE.MIMTXBWDATA51 |
| TCELL20:OUT10.TMIN | PCIE.MIMTXBWDATA52 |
| TCELL20:OUT11.TMIN | PCIE.MIMTXBWDATA53 |
| TCELL20:OUT12.TMIN | PCIE.MIMTXBWEN |
| TCELL20:OUT13.TMIN | PCIE.MIMTXBREN |
| TCELL20:OUT14.TMIN | PCIE.L0ERRMSGREQID9 |
| TCELL20:OUT15.TMIN | PCIE.L0ERRMSGREQID10 |
| TCELL20:OUT16.TMIN | PCIE.L0MSIENABLE0 |
| TCELL20:OUT17.TMIN | PCIE.L0MULTIMSGEN00 |
| TCELL20:OUT18.TMIN | PCIE.L0MULTIMSGEN01 |
| TCELL20:OUT19.TMIN | PCIE.L0TXDLLSBFCUPDATED |
| TCELL20:OUT20.TMIN | PCIE.L0RXDLLSBFCDATA0 |
| TCELL20:OUT21.TMIN | PCIE.L0RXDLLSBFCDATA1 |
| TCELL20:OUT22.TMIN | PCIE.L0RXDLLSBFCDATA2 |
| TCELL20:OUT23.TMIN | PCIE.L0RXDLLFCPOSTORDCRED4 |
| TCELL21:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA24 |
| TCELL21:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA25 |
| TCELL21:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA26 |
| TCELL21:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA27 |
| TCELL21:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA48 |
| TCELL21:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA49 |
| TCELL21:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA50 |
| TCELL21:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA51 |
| TCELL21:IMUX.IMUX8.DELAY | PCIE.L0CFGASSTATECHANGECMD2 |
| TCELL21:IMUX.IMUX9.DELAY | PCIE.L0CFGASSTATECHANGECMD3 |
| TCELL21:IMUX.IMUX10.DELAY | PCIE.L0CFGASSPANTREEOWNEDSTATE |
| TCELL21:IMUX.IMUX11.DELAY | PCIE.L0ASE |
| TCELL21:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER61 |
| TCELL21:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER62 |
| TCELL21:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER63 |
| TCELL21:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER64 |
| TCELL21:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA44 |
| TCELL21:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA45 |
| TCELL21:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA46 |
| TCELL21:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA47 |
| TCELL21:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED83 |
| TCELL21:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED84 |
| TCELL21:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED85 |
| TCELL21:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED86 |
| TCELL21:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED43 |
| TCELL21:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED44 |
| TCELL21:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED45 |
| TCELL21:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED46 |
| TCELL21:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED142 |
| TCELL21:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED143 |
| TCELL21:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED144 |
| TCELL21:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED145 |
| TCELL21:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED116 |
| TCELL21:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED117 |
| TCELL21:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED118 |
| TCELL21:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED119 |
| TCELL21:OUT0.TMIN | PCIE.PIPETXDATAL14 |
| TCELL21:OUT1.TMIN | PCIE.PIPETXDATAL15 |
| TCELL21:OUT2.TMIN | PCIE.PIPETXDATAL16 |
| TCELL21:OUT3.TMIN | PCIE.PIPETXDATAL17 |
| TCELL21:OUT4.TMIN | PCIE.MIMTXBWDATA23 |
| TCELL21:OUT5.TMIN | PCIE.MIMTXBWDATA24 |
| TCELL21:OUT6.TMIN | PCIE.MIMTXBWDATA25 |
| TCELL21:OUT7.TMIN | PCIE.MIMTXBWDATA26 |
| TCELL21:OUT8.TMIN | PCIE.MIMTXBWDATA46 |
| TCELL21:OUT9.TMIN | PCIE.MIMTXBWDATA47 |
| TCELL21:OUT10.TMIN | PCIE.MIMTXBWDATA48 |
| TCELL21:OUT11.TMIN | PCIE.MIMTXBWDATA49 |
| TCELL21:OUT12.TMIN | PCIE.L0ERRMSGREQID5 |
| TCELL21:OUT13.TMIN | PCIE.L0ERRMSGREQID6 |
| TCELL21:OUT14.TMIN | PCIE.L0ERRMSGREQID7 |
| TCELL21:OUT15.TMIN | PCIE.L0ERRMSGREQID8 |
| TCELL21:OUT16.TMIN | PCIE.L0MULTIMSGEN02 |
| TCELL21:OUT17.TMIN | PCIE.L0STATSDLLPRECEIVED |
| TCELL21:OUT18.TMIN | PCIE.L0STATSDLLPTRANSMITTED |
| TCELL21:OUT19.TMIN | PCIE.L0STATSOSRECEIVED |
| TCELL21:OUT20.TMIN | PCIE.L0RXDLLSBFCDATA3 |
| TCELL21:OUT21.TMIN | PCIE.L0RXDLLSBFCDATA4 |
| TCELL21:OUT22.TMIN | PCIE.L0RXDLLSBFCDATA5 |
| TCELL21:OUT23.TMIN | PCIE.L0RXDLLSBFCDATA6 |
| TCELL22:IMUX.IMUX0.DELAY | PCIE.MIMTXBRDATA28 |
| TCELL22:IMUX.IMUX1.DELAY | PCIE.MIMTXBRDATA29 |
| TCELL22:IMUX.IMUX2.DELAY | PCIE.MIMTXBRDATA30 |
| TCELL22:IMUX.IMUX3.DELAY | PCIE.MIMTXBRDATA31 |
| TCELL22:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA44 |
| TCELL22:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA45 |
| TCELL22:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA46 |
| TCELL22:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA47 |
| TCELL22:IMUX.IMUX8.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT11 |
| TCELL22:IMUX.IMUX9.DELAY | PCIE.L0DLLHOLDLINKUP |
| TCELL22:IMUX.IMUX10.DELAY | PCIE.L0CFGASSTATECHANGECMD0 |
| TCELL22:IMUX.IMUX11.DELAY | PCIE.L0CFGASSTATECHANGECMD1 |
| TCELL22:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER65 |
| TCELL22:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER66 |
| TCELL22:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER67 |
| TCELL22:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER68 |
| TCELL22:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA48 |
| TCELL22:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA49 |
| TCELL22:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA50 |
| TCELL22:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA51 |
| TCELL22:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED79 |
| TCELL22:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED80 |
| TCELL22:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED81 |
| TCELL22:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED82 |
| TCELL22:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED47 |
| TCELL22:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED48 |
| TCELL22:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED49 |
| TCELL22:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED50 |
| TCELL22:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED138 |
| TCELL22:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED139 |
| TCELL22:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED140 |
| TCELL22:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED141 |
| TCELL22:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCCMPLMCCRED120 |
| TCELL22:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCCMPLMCCRED121 |
| TCELL22:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCCMPLMCCRED122 |
| TCELL22:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCCMPLMCCRED123 |
| TCELL22:OUT0.TMIN | PCIE.PIPETXDATAKL1 |
| TCELL22:OUT1.TMIN | PCIE.PIPETXELECIDLEL1 |
| TCELL22:OUT2.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL1 |
| TCELL22:OUT3.TMIN | PCIE.PIPETXCOMPLIANCEL1 |
| TCELL22:OUT4.TMIN | PCIE.MIMTXBWDATA27 |
| TCELL22:OUT5.TMIN | PCIE.MIMTXBWDATA28 |
| TCELL22:OUT6.TMIN | PCIE.MIMTXBWDATA29 |
| TCELL22:OUT7.TMIN | PCIE.MIMTXBWDATA30 |
| TCELL22:OUT8.TMIN | PCIE.MIMTXBWDATA42 |
| TCELL22:OUT9.TMIN | PCIE.MIMTXBWDATA43 |
| TCELL22:OUT10.TMIN | PCIE.MIMTXBWDATA44 |
| TCELL22:OUT11.TMIN | PCIE.MIMTXBWDATA45 |
| TCELL22:OUT12.TMIN | PCIE.L0ERRMSGREQID1 |
| TCELL22:OUT13.TMIN | PCIE.L0ERRMSGREQID2 |
| TCELL22:OUT14.TMIN | PCIE.L0ERRMSGREQID3 |
| TCELL22:OUT15.TMIN | PCIE.L0ERRMSGREQID4 |
| TCELL22:OUT16.TMIN | PCIE.L0STATSOSTRANSMITTED |
| TCELL22:OUT17.TMIN | PCIE.L0STATSTLPRECEIVED |
| TCELL22:OUT18.TMIN | PCIE.L0STATSTLPTRANSMITTED |
| TCELL22:OUT19.TMIN | PCIE.L0STATSCFGRECEIVED |
| TCELL22:OUT20.TMIN | PCIE.L0RXDLLSBFCDATA7 |
| TCELL22:OUT21.TMIN | PCIE.L0RXDLLSBFCDATA8 |
| TCELL22:OUT22.TMIN | PCIE.L0RXDLLSBFCDATA9 |
| TCELL22:OUT23.TMIN | PCIE.L0RXDLLSBFCDATA10 |
| TCELL23:IMUX.IMUX0.DELAY | PCIE.PIPERXELECIDLEL1 |
| TCELL23:IMUX.IMUX1.DELAY | PCIE.PIPERXSTATUSL10 |
| TCELL23:IMUX.IMUX2.DELAY | PCIE.PIPERXSTATUSL11 |
| TCELL23:IMUX.IMUX3.DELAY | PCIE.PIPERXSTATUSL12 |
| TCELL23:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA32 |
| TCELL23:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA33 |
| TCELL23:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA34 |
| TCELL23:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA35 |
| TCELL23:IMUX.IMUX8.DELAY | PCIE.MIMTXBRDATA40 |
| TCELL23:IMUX.IMUX9.DELAY | PCIE.MIMTXBRDATA41 |
| TCELL23:IMUX.IMUX10.DELAY | PCIE.MIMTXBRDATA42 |
| TCELL23:IMUX.IMUX11.DELAY | PCIE.MIMTXBRDATA43 |
| TCELL23:IMUX.IMUX12.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT7 |
| TCELL23:IMUX.IMUX13.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT8 |
| TCELL23:IMUX.IMUX14.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT9 |
| TCELL23:IMUX.IMUX15.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT10 |
| TCELL23:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER69 |
| TCELL23:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER70 |
| TCELL23:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER71 |
| TCELL23:IMUX.IMUX19.DELAY | PCIE.L0PACKETHEADERFROMUSER72 |
| TCELL23:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPDATA52 |
| TCELL23:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPDATA53 |
| TCELL23:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPDATA54 |
| TCELL23:IMUX.IMUX23.DELAY | PCIE.L0TXTLTLPDATA55 |
| TCELL23:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED75 |
| TCELL23:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED76 |
| TCELL23:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED77 |
| TCELL23:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED78 |
| TCELL23:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED51 |
| TCELL23:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED52 |
| TCELL23:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED53 |
| TCELL23:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED54 |
| TCELL23:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED134 |
| TCELL23:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED135 |
| TCELL23:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED136 |
| TCELL23:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED137 |
| TCELL23:OUT0.TMIN | PCIE.PIPERXPOLARITYL1 |
| TCELL23:OUT1.TMIN | PCIE.PIPEPOWERDOWNL10 |
| TCELL23:OUT2.TMIN | PCIE.PIPEPOWERDOWNL11 |
| TCELL23:OUT3.TMIN | PCIE.PIPEDESKEWLANESL1 |
| TCELL23:OUT4.TMIN | PCIE.MIMTXBWDATA31 |
| TCELL23:OUT5.TMIN | PCIE.MIMTXBWDATA32 |
| TCELL23:OUT6.TMIN | PCIE.MIMTXBWDATA33 |
| TCELL23:OUT7.TMIN | PCIE.MIMTXBWDATA34 |
| TCELL23:OUT8.TMIN | PCIE.MIMTXBWDATA38 |
| TCELL23:OUT9.TMIN | PCIE.MIMTXBWDATA39 |
| TCELL23:OUT10.TMIN | PCIE.MIMTXBWDATA40 |
| TCELL23:OUT11.TMIN | PCIE.MIMTXBWDATA41 |
| TCELL23:OUT12.TMIN | PCIE.L0CORRERRMSGRCVD |
| TCELL23:OUT13.TMIN | PCIE.L0FATALERRMSGRCVD |
| TCELL23:OUT14.TMIN | PCIE.L0NONFATALERRMSGRCVD |
| TCELL23:OUT15.TMIN | PCIE.L0ERRMSGREQID0 |
| TCELL23:OUT16.TMIN | PCIE.L0STATSCFGTRANSMITTED |
| TCELL23:OUT17.TMIN | PCIE.L0STATSCFGOTHERRECEIVED |
| TCELL23:OUT18.TMIN | PCIE.L0STATSCFGOTHERTRANSMITTED |
| TCELL23:OUT19.TMIN | PCIE.MAXPAYLOADSIZE0 |
| TCELL23:OUT20.TMIN | PCIE.L0RXDLLSBFCDATA11 |
| TCELL23:OUT21.TMIN | PCIE.L0RXDLLSBFCDATA12 |
| TCELL23:OUT22.TMIN | PCIE.L0RXDLLSBFCDATA13 |
| TCELL23:OUT23.TMIN | PCIE.L0RXDLLSBFCDATA14 |
| TCELL24:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL10 |
| TCELL24:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL11 |
| TCELL24:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL12 |
| TCELL24:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL13 |
| TCELL24:IMUX.IMUX4.DELAY | PCIE.MIMTXBRDATA36 |
| TCELL24:IMUX.IMUX5.DELAY | PCIE.MIMTXBRDATA37 |
| TCELL24:IMUX.IMUX6.DELAY | PCIE.MIMTXBRDATA38 |
| TCELL24:IMUX.IMUX7.DELAY | PCIE.MIMTXBRDATA39 |
| TCELL24:IMUX.IMUX8.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT3 |
| TCELL24:IMUX.IMUX9.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT4 |
| TCELL24:IMUX.IMUX10.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT5 |
| TCELL24:IMUX.IMUX11.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT6 |
| TCELL24:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER73 |
| TCELL24:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER74 |
| TCELL24:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER75 |
| TCELL24:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER76 |
| TCELL24:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPDATA56 |
| TCELL24:IMUX.IMUX17.DELAY | PCIE.L0TXTLTLPDATA57 |
| TCELL24:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPDATA58 |
| TCELL24:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPDATA59 |
| TCELL24:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED71 |
| TCELL24:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED72 |
| TCELL24:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED73 |
| TCELL24:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED74 |
| TCELL24:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCPOSTORDCRED55 |
| TCELL24:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCPOSTORDCRED56 |
| TCELL24:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCPOSTORDCRED57 |
| TCELL24:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED58 |
| TCELL24:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED130 |
| TCELL24:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED131 |
| TCELL24:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED132 |
| TCELL24:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED133 |
| TCELL24:OUT0.TMIN | PCIE.PIPERESETL1 |
| TCELL24:OUT1.TMIN | PCIE.MIMTXBWDATA35 |
| TCELL24:OUT2.TMIN | PCIE.MIMTXBWDATA36 |
| TCELL24:OUT3.TMIN | PCIE.MIMTXBWDATA37 |
| TCELL24:OUT4.TMIN | PCIE.L0COMPLETERID10 |
| TCELL24:OUT5.TMIN | PCIE.L0COMPLETERID11 |
| TCELL24:OUT6.TMIN | PCIE.L0COMPLETERID12 |
| TCELL24:OUT7.TMIN | PCIE.L0UNLOCKRECEIVED |
| TCELL24:OUT8.TMIN | PCIE.MAXPAYLOADSIZE1 |
| TCELL24:OUT9.TMIN | PCIE.MAXPAYLOADSIZE2 |
| TCELL24:OUT10.TMIN | PCIE.MAXREADREQUESTSIZE0 |
| TCELL24:OUT11.TMIN | PCIE.MAXREADREQUESTSIZE1 |
| TCELL24:OUT12.TMIN | PCIE.L0RXDLLSBFCDATA15 |
| TCELL24:OUT13.TMIN | PCIE.L0RXDLLSBFCDATA16 |
| TCELL24:OUT14.TMIN | PCIE.L0RXDLLSBFCDATA17 |
| TCELL24:OUT15.TMIN | PCIE.L0RXDLLSBFCDATA18 |
| TCELL24:OUT16.TMIN | PCIE.L0RXDLLFCPOSTORDCRED0 |
| TCELL24:OUT17.TMIN | PCIE.L0RXDLLFCPOSTORDCRED1 |
| TCELL24:OUT18.TMIN | PCIE.L0RXDLLFCPOSTORDCRED2 |
| TCELL24:OUT19.TMIN | PCIE.L0RXDLLFCPOSTORDCRED3 |
| TCELL24:OUT20.TMIN | PCIE.L0UCBYPFOUND0 |
| TCELL24:OUT21.TMIN | PCIE.L0UCBYPFOUND1 |
| TCELL24:OUT22.TMIN | PCIE.L0UCBYPFOUND2 |
| TCELL24:OUT23.TMIN | PCIE.L0UCBYPFOUND3 |
| TCELL25:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL14 |
| TCELL25:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL15 |
| TCELL25:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL16 |
| TCELL25:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL17 |
| TCELL25:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA0 |
| TCELL25:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA1 |
| TCELL25:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA2 |
| TCELL25:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA3 |
| TCELL25:IMUX.IMUX8.DELAY | PCIE.MGMTWDATA0 |
| TCELL25:IMUX.IMUX9.DELAY | PCIE.MGMTWDATA1 |
| TCELL25:IMUX.IMUX10.DELAY | PCIE.MGMTWDATA2 |
| TCELL25:IMUX.IMUX11.DELAY | PCIE.MGMTWDATA3 |
| TCELL25:IMUX.IMUX12.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT11 |
| TCELL25:IMUX.IMUX13.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT0 |
| TCELL25:IMUX.IMUX14.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT1 |
| TCELL25:IMUX.IMUX15.DELAY | PCIE.L0ACKNAKTIMERADJUSTMENT2 |
| TCELL25:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER77 |
| TCELL25:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER78 |
| TCELL25:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER79 |
| TCELL25:IMUX.IMUX19.DELAY | PCIE.L0PACKETHEADERFROMUSER80 |
| TCELL25:IMUX.IMUX20.DELAY | PCIE.SCANIN6 |
| TCELL25:IMUX.IMUX21.DELAY | PCIE.SCANIN7 |
| TCELL25:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPDATA60 |
| TCELL25:IMUX.IMUX23.DELAY | PCIE.L0TXTLTLPDATA61 |
| TCELL25:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED67 |
| TCELL25:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED68 |
| TCELL25:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED69 |
| TCELL25:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED70 |
| TCELL25:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED59 |
| TCELL25:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED60 |
| TCELL25:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED61 |
| TCELL25:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED62 |
| TCELL25:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED128 |
| TCELL25:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED129 |
| TCELL25:OUT0.TMIN | PCIE.MIMDLLBWDATA0 |
| TCELL25:OUT1.TMIN | PCIE.MIMDLLBWDATA1 |
| TCELL25:OUT2.TMIN | PCIE.MIMDLLBWDATA2 |
| TCELL25:OUT3.TMIN | PCIE.MIMDLLBWDATA3 |
| TCELL25:OUT4.TMIN | PCIE.MIMDLLBWADD5 |
| TCELL25:OUT5.TMIN | PCIE.MIMDLLBWADD6 |
| TCELL25:OUT6.TMIN | PCIE.MIMDLLBWADD7 |
| TCELL25:OUT7.TMIN | PCIE.MIMDLLBWADD8 |
| TCELL25:OUT8.TMIN | PCIE.MGMTRDATA0 |
| TCELL25:OUT9.TMIN | PCIE.MGMTRDATA1 |
| TCELL25:OUT10.TMIN | PCIE.MGMTRDATA2 |
| TCELL25:OUT11.TMIN | PCIE.MGMTRDATA3 |
| TCELL25:OUT12.TMIN | PCIE.L0COMPLETERID6 |
| TCELL25:OUT13.TMIN | PCIE.L0COMPLETERID7 |
| TCELL25:OUT14.TMIN | PCIE.L0COMPLETERID8 |
| TCELL25:OUT15.TMIN | PCIE.L0COMPLETERID9 |
| TCELL25:OUT16.TMIN | PCIE.MAXREADREQUESTSIZE2 |
| TCELL25:OUT17.TMIN | PCIE.IOSPACEENABLE |
| TCELL25:OUT18.TMIN | PCIE.MEMSPACEENABLE |
| TCELL25:OUT19.TMIN | PCIE.L0RXDLLSBFCUPDATE |
| TCELL25:OUT20.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE4 |
| TCELL25:OUT21.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE5 |
| TCELL25:OUT22.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE6 |
| TCELL25:OUT23.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE7 |
| TCELL26:IMUX.IMUX0.DELAY | PCIE.PIPEPHYSTATUSL1 |
| TCELL26:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAKL1 |
| TCELL26:IMUX.IMUX2.DELAY | PCIE.PIPERXVALIDL1 |
| TCELL26:IMUX.IMUX3.DELAY | PCIE.PIPERXCHANISALIGNEDL1 |
| TCELL26:IMUX.IMUX4.DELAY | PCIE.MGMTWDATA4 |
| TCELL26:IMUX.IMUX5.DELAY | PCIE.MGMTWDATA5 |
| TCELL26:IMUX.IMUX6.DELAY | PCIE.MGMTWDATA6 |
| TCELL26:IMUX.IMUX7.DELAY | PCIE.MGMTWDATA7 |
| TCELL26:IMUX.IMUX8.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT7 |
| TCELL26:IMUX.IMUX9.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT8 |
| TCELL26:IMUX.IMUX10.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT9 |
| TCELL26:IMUX.IMUX11.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT10 |
| TCELL26:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER81 |
| TCELL26:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER82 |
| TCELL26:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER83 |
| TCELL26:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER84 |
| TCELL26:IMUX.IMUX16.DELAY | PCIE.SCANIN2 |
| TCELL26:IMUX.IMUX17.DELAY | PCIE.SCANIN3 |
| TCELL26:IMUX.IMUX18.DELAY | PCIE.SCANIN4 |
| TCELL26:IMUX.IMUX19.DELAY | PCIE.SCANIN5 |
| TCELL26:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPDATA62 |
| TCELL26:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPDATA63 |
| TCELL26:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPEND0 |
| TCELL26:IMUX.IMUX23.DELAY | PCIE.L0TXTLTLPEND1 |
| TCELL26:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED63 |
| TCELL26:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED64 |
| TCELL26:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED65 |
| TCELL26:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED66 |
| TCELL26:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED63 |
| TCELL26:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED64 |
| TCELL26:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED65 |
| TCELL26:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED66 |
| TCELL26:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED124 |
| TCELL26:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED125 |
| TCELL26:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED126 |
| TCELL26:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED127 |
| TCELL26:OUT0.TMIN | PCIE.MIMDLLBWDATA4 |
| TCELL26:OUT1.TMIN | PCIE.MIMDLLBWDATA5 |
| TCELL26:OUT2.TMIN | PCIE.MIMDLLBWDATA6 |
| TCELL26:OUT3.TMIN | PCIE.MIMDLLBWDATA7 |
| TCELL26:OUT4.TMIN | PCIE.MIMDLLBWADD1 |
| TCELL26:OUT5.TMIN | PCIE.MIMDLLBWADD2 |
| TCELL26:OUT6.TMIN | PCIE.MIMDLLBWADD3 |
| TCELL26:OUT7.TMIN | PCIE.MIMDLLBWADD4 |
| TCELL26:OUT8.TMIN | PCIE.MIMDLLBWADD9 |
| TCELL26:OUT9.TMIN | PCIE.MIMDLLBWADD10 |
| TCELL26:OUT10.TMIN | PCIE.MIMDLLBWADD11 |
| TCELL26:OUT11.TMIN | PCIE.MIMDLLBRADD0 |
| TCELL26:OUT12.TMIN | PCIE.MGMTRDATA4 |
| TCELL26:OUT13.TMIN | PCIE.MGMTRDATA5 |
| TCELL26:OUT14.TMIN | PCIE.MGMTRDATA6 |
| TCELL26:OUT15.TMIN | PCIE.MGMTRDATA7 |
| TCELL26:OUT16.TMIN | PCIE.L0COMPLETERID3 |
| TCELL26:OUT17.TMIN | PCIE.L0COMPLETERID4 |
| TCELL26:OUT18.TMIN | PCIE.L0COMPLETERID5 |
| TCELL26:OUT19.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED0 |
| TCELL26:OUT20.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED1 |
| TCELL26:OUT21.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED2 |
| TCELL26:OUT22.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED3 |
| TCELL26:OUT23.TMIN | PCIE.L0UCORDFOUND0 |
| TCELL27:IMUX.IMUX0.DELAY | PCIE.MIMDLLBRDATA4 |
| TCELL27:IMUX.IMUX1.DELAY | PCIE.MIMDLLBRDATA5 |
| TCELL27:IMUX.IMUX2.DELAY | PCIE.MIMDLLBRDATA6 |
| TCELL27:IMUX.IMUX3.DELAY | PCIE.MIMDLLBRDATA7 |
| TCELL27:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA63 |
| TCELL27:IMUX.IMUX5.DELAY | PCIE.MGMTWDATA8 |
| TCELL27:IMUX.IMUX6.DELAY | PCIE.MGMTWDATA9 |
| TCELL27:IMUX.IMUX7.DELAY | PCIE.MGMTWDATA10 |
| TCELL27:IMUX.IMUX8.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT3 |
| TCELL27:IMUX.IMUX9.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT4 |
| TCELL27:IMUX.IMUX10.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT5 |
| TCELL27:IMUX.IMUX11.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT6 |
| TCELL27:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER85 |
| TCELL27:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER86 |
| TCELL27:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER87 |
| TCELL27:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER88 |
| TCELL27:IMUX.IMUX16.DELAY | PCIE.SCANENABLEN |
| TCELL27:IMUX.IMUX17.DELAY | PCIE.SCANMODEN |
| TCELL27:IMUX.IMUX18.DELAY | PCIE.SCANIN0 |
| TCELL27:IMUX.IMUX19.DELAY | PCIE.SCANIN1 |
| TCELL27:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPENABLE0 |
| TCELL27:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPENABLE1 |
| TCELL27:IMUX.IMUX22.DELAY | PCIE.L0TXTLTLPEDB |
| TCELL27:IMUX.IMUX23.DELAY | PCIE.L0TXTLTLPREQ |
| TCELL27:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED59 |
| TCELL27:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED60 |
| TCELL27:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED61 |
| TCELL27:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED62 |
| TCELL27:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED67 |
| TCELL27:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED68 |
| TCELL27:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED69 |
| TCELL27:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED70 |
| TCELL27:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED121 |
| TCELL27:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED122 |
| TCELL27:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED123 |
| TCELL27:OUT0.TMIN | PCIE.MIMDLLBWDATA8 |
| TCELL27:OUT1.TMIN | PCIE.MIMDLLBWDATA9 |
| TCELL27:OUT2.TMIN | PCIE.MIMDLLBWDATA10 |
| TCELL27:OUT3.TMIN | PCIE.MIMDLLBWDATA11 |
| TCELL27:OUT4.TMIN | PCIE.MIMDLLBWDATA61 |
| TCELL27:OUT5.TMIN | PCIE.MIMDLLBWDATA62 |
| TCELL27:OUT6.TMIN | PCIE.MIMDLLBWDATA63 |
| TCELL27:OUT7.TMIN | PCIE.MIMDLLBWADD0 |
| TCELL27:OUT8.TMIN | PCIE.MIMDLLBRADD1 |
| TCELL27:OUT9.TMIN | PCIE.MIMDLLBRADD2 |
| TCELL27:OUT10.TMIN | PCIE.MIMDLLBRADD3 |
| TCELL27:OUT11.TMIN | PCIE.MIMDLLBRADD4 |
| TCELL27:OUT12.TMIN | PCIE.MGMTRDATA8 |
| TCELL27:OUT13.TMIN | PCIE.MGMTRDATA9 |
| TCELL27:OUT14.TMIN | PCIE.MGMTRDATA10 |
| TCELL27:OUT15.TMIN | PCIE.MGMTRDATA11 |
| TCELL27:OUT16.TMIN | PCIE.L0ASAUTONOMOUSINITCOMPLETED |
| TCELL27:OUT17.TMIN | PCIE.L0COMPLETERID0 |
| TCELL27:OUT18.TMIN | PCIE.L0COMPLETERID1 |
| TCELL27:OUT19.TMIN | PCIE.L0COMPLETERID2 |
| TCELL27:OUT20.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED4 |
| TCELL27:OUT21.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED5 |
| TCELL27:OUT22.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED6 |
| TCELL27:OUT23.TMIN | PCIE.L0TXDLLFCNPOSTBYPUPDATED7 |
| TCELL28:IMUX.IMUX0.DELAY | PCIE.MIMDLLBRDATA8 |
| TCELL28:IMUX.IMUX1.DELAY | PCIE.MIMDLLBRDATA9 |
| TCELL28:IMUX.IMUX2.DELAY | PCIE.MIMDLLBRDATA10 |
| TCELL28:IMUX.IMUX3.DELAY | PCIE.MIMDLLBRDATA11 |
| TCELL28:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA59 |
| TCELL28:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA60 |
| TCELL28:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA61 |
| TCELL28:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA62 |
| TCELL28:IMUX.IMUX8.DELAY | PCIE.MGMTWDATA11 |
| TCELL28:IMUX.IMUX9.DELAY | PCIE.MGMTWDATA12 |
| TCELL28:IMUX.IMUX10.DELAY | PCIE.MGMTWDATA13 |
| TCELL28:IMUX.IMUX11.DELAY | PCIE.MGMTWDATA14 |
| TCELL28:IMUX.IMUX12.DELAY | PCIE.L0CFGLOOPBACKMASTER |
| TCELL28:IMUX.IMUX13.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT0 |
| TCELL28:IMUX.IMUX14.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT1 |
| TCELL28:IMUX.IMUX15.DELAY | PCIE.L0REPLAYTIMERADJUSTMENT2 |
| TCELL28:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER89 |
| TCELL28:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER90 |
| TCELL28:IMUX.IMUX18.DELAY | PCIE.L0TXTLTLPREQEND |
| TCELL28:IMUX.IMUX19.DELAY | PCIE.L0TXTLTLPWIDTH |
| TCELL28:IMUX.IMUX20.DELAY | PCIE.L0TXTLTLPLATENCY0 |
| TCELL28:IMUX.IMUX21.DELAY | PCIE.L0TXTLTLPLATENCY1 |
| TCELL28:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED55 |
| TCELL28:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED56 |
| TCELL28:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED57 |
| TCELL28:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED58 |
| TCELL28:IMUX.IMUX44.DELAY | PCIE.PIPERXCHANISALIGNEDL4 |
| TCELL28:IMUX.IMUX45.DELAY | PCIE.PIPERXVALIDL4 |
| TCELL28:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAKL4 |
| TCELL28:IMUX.IMUX47.DELAY | PCIE.PIPEPHYSTATUSL4 |
| TCELL28:OUT0.TMIN | PCIE.MIMDLLBWDATA12 |
| TCELL28:OUT1.TMIN | PCIE.MIMDLLBWDATA13 |
| TCELL28:OUT2.TMIN | PCIE.MIMDLLBWDATA14 |
| TCELL28:OUT3.TMIN | PCIE.MIMDLLBWDATA15 |
| TCELL28:OUT4.TMIN | PCIE.MIMDLLBWDATA57 |
| TCELL28:OUT5.TMIN | PCIE.MIMDLLBWDATA58 |
| TCELL28:OUT6.TMIN | PCIE.MIMDLLBWDATA59 |
| TCELL28:OUT7.TMIN | PCIE.MIMDLLBWDATA60 |
| TCELL28:OUT8.TMIN | PCIE.MIMDLLBRADD5 |
| TCELL28:OUT9.TMIN | PCIE.MIMDLLBRADD6 |
| TCELL28:OUT10.TMIN | PCIE.MIMDLLBRADD7 |
| TCELL28:OUT11.TMIN | PCIE.MIMDLLBRADD8 |
| TCELL28:OUT12.TMIN | PCIE.MGMTRDATA12 |
| TCELL28:OUT13.TMIN | PCIE.MGMTRDATA13 |
| TCELL28:OUT14.TMIN | PCIE.MGMTRDATA14 |
| TCELL28:OUT15.TMIN | PCIE.MGMTRDATA15 |
| TCELL28:OUT16.TMIN | PCIE.L0DLLERRORVECTOR6 |
| TCELL28:OUT17.TMIN | PCIE.L0DLLASRXSTATE0 |
| TCELL28:OUT18.TMIN | PCIE.L0DLLASRXSTATE1 |
| TCELL28:OUT19.TMIN | PCIE.L0DLLASTXSTATE |
| TCELL28:OUT20.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED0 |
| TCELL28:OUT21.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED1 |
| TCELL28:OUT22.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED2 |
| TCELL28:OUT23.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED3 |
| TCELL29:IMUX.IMUX0.DELAY | PCIE.PIPERXELECIDLEL5 |
| TCELL29:IMUX.IMUX1.DELAY | PCIE.PIPERXSTATUSL50 |
| TCELL29:IMUX.IMUX2.DELAY | PCIE.PIPERXSTATUSL51 |
| TCELL29:IMUX.IMUX3.DELAY | PCIE.PIPERXSTATUSL52 |
| TCELL29:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA12 |
| TCELL29:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA13 |
| TCELL29:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA14 |
| TCELL29:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA15 |
| TCELL29:IMUX.IMUX8.DELAY | PCIE.MIMDLLBRDATA55 |
| TCELL29:IMUX.IMUX9.DELAY | PCIE.MIMDLLBRDATA56 |
| TCELL29:IMUX.IMUX10.DELAY | PCIE.MIMDLLBRDATA57 |
| TCELL29:IMUX.IMUX11.DELAY | PCIE.MIMDLLBRDATA58 |
| TCELL29:IMUX.IMUX12.DELAY | PCIE.MGMTWDATA15 |
| TCELL29:IMUX.IMUX13.DELAY | PCIE.MGMTWDATA16 |
| TCELL29:IMUX.IMUX14.DELAY | PCIE.MGMTWDATA17 |
| TCELL29:IMUX.IMUX15.DELAY | PCIE.L0TXTLTLPLATENCY2 |
| TCELL29:IMUX.IMUX16.DELAY | PCIE.L0TXTLTLPLATENCY3 |
| TCELL29:IMUX.IMUX17.DELAY | PCIE.L0TLASFCCREDSTARVATION |
| TCELL29:IMUX.IMUX18.DELAY | PCIE.L0TXTLSBFCDATA0 |
| TCELL29:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED51 |
| TCELL29:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED52 |
| TCELL29:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED53 |
| TCELL29:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED54 |
| TCELL29:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL47 |
| TCELL29:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL46 |
| TCELL29:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL45 |
| TCELL29:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL44 |
| TCELL29:OUT0.TMIN | PCIE.MIMDLLBWDATA16 |
| TCELL29:OUT1.TMIN | PCIE.MIMDLLBWDATA17 |
| TCELL29:OUT2.TMIN | PCIE.MIMDLLBWDATA18 |
| TCELL29:OUT3.TMIN | PCIE.MIMDLLBWDATA19 |
| TCELL29:OUT4.TMIN | PCIE.MIMDLLBWDATA53 |
| TCELL29:OUT5.TMIN | PCIE.MIMDLLBWDATA54 |
| TCELL29:OUT6.TMIN | PCIE.MIMDLLBWDATA55 |
| TCELL29:OUT7.TMIN | PCIE.MIMDLLBWDATA56 |
| TCELL29:OUT8.TMIN | PCIE.MIMDLLBRADD9 |
| TCELL29:OUT9.TMIN | PCIE.MIMDLLBRADD10 |
| TCELL29:OUT10.TMIN | PCIE.MIMDLLBRADD11 |
| TCELL29:OUT11.TMIN | PCIE.MIMDLLBWEN |
| TCELL29:OUT12.TMIN | PCIE.MGMTRDATA16 |
| TCELL29:OUT13.TMIN | PCIE.MGMTRDATA17 |
| TCELL29:OUT14.TMIN | PCIE.MGMTRDATA18 |
| TCELL29:OUT15.TMIN | PCIE.MGMTRDATA19 |
| TCELL29:OUT16.TMIN | PCIE.L0DLLERRORVECTOR3 |
| TCELL29:OUT17.TMIN | PCIE.L0DLLERRORVECTOR4 |
| TCELL29:OUT18.TMIN | PCIE.L0DLLERRORVECTOR5 |
| TCELL29:OUT19.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED4 |
| TCELL29:OUT20.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED5 |
| TCELL29:OUT21.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED6 |
| TCELL29:OUT22.TMIN | PCIE.L0TXDLLFCPOSTORDUPDATED7 |
| TCELL29:OUT23.TMIN | PCIE.L0UCORDFOUND1 |
| TCELL30:IMUX.CLK0 | PCIE.CRMCORECLKDLO |
| TCELL30:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL50 |
| TCELL30:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL51 |
| TCELL30:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL52 |
| TCELL30:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL53 |
| TCELL30:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA16 |
| TCELL30:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA17 |
| TCELL30:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA18 |
| TCELL30:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA19 |
| TCELL30:IMUX.IMUX8.DELAY | PCIE.MIMDLLBRDATA51 |
| TCELL30:IMUX.IMUX9.DELAY | PCIE.MIMDLLBRDATA52 |
| TCELL30:IMUX.IMUX10.DELAY | PCIE.MIMDLLBRDATA53 |
| TCELL30:IMUX.IMUX11.DELAY | PCIE.MIMDLLBRDATA54 |
| TCELL30:IMUX.IMUX12.DELAY | PCIE.MGMTWDATA18 |
| TCELL30:IMUX.IMUX13.DELAY | PCIE.MGMTWDATA19 |
| TCELL30:IMUX.IMUX14.DELAY | PCIE.MGMTWDATA20 |
| TCELL30:IMUX.IMUX15.DELAY | PCIE.L0TXTLSBFCDATA1 |
| TCELL30:IMUX.IMUX16.DELAY | PCIE.L0TXTLSBFCDATA2 |
| TCELL30:IMUX.IMUX17.DELAY | PCIE.L0TXTLSBFCDATA3 |
| TCELL30:IMUX.IMUX18.DELAY | PCIE.L0TXTLSBFCDATA4 |
| TCELL30:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED47 |
| TCELL30:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED48 |
| TCELL30:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED49 |
| TCELL30:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED50 |
| TCELL30:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL43 |
| TCELL30:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL42 |
| TCELL30:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL41 |
| TCELL30:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL40 |
| TCELL30:OUT0.TMIN | PCIE.PIPETXDATAL50 |
| TCELL30:OUT1.TMIN | PCIE.PIPETXDATAL51 |
| TCELL30:OUT2.TMIN | PCIE.PIPETXDATAL52 |
| TCELL30:OUT3.TMIN | PCIE.PIPEDESKEWLANESL5 |
| TCELL30:OUT4.TMIN | PCIE.PIPERESETL5 |
| TCELL30:OUT5.TMIN | PCIE.MIMDLLBWDATA20 |
| TCELL30:OUT6.TMIN | PCIE.MIMDLLBWDATA21 |
| TCELL30:OUT7.TMIN | PCIE.MIMDLLBWDATA49 |
| TCELL30:OUT8.TMIN | PCIE.MIMDLLBWDATA50 |
| TCELL30:OUT9.TMIN | PCIE.MIMDLLBWDATA51 |
| TCELL30:OUT10.TMIN | PCIE.MIMDLLBWDATA52 |
| TCELL30:OUT11.TMIN | PCIE.MIMDLLBREN |
| TCELL30:OUT12.TMIN | PCIE.MGMTRDATA20 |
| TCELL30:OUT13.TMIN | PCIE.MGMTRDATA21 |
| TCELL30:OUT14.TMIN | PCIE.MGMTRDATA22 |
| TCELL30:OUT15.TMIN | PCIE.L0DLLERRORVECTOR0 |
| TCELL30:OUT16.TMIN | PCIE.L0DLLERRORVECTOR1 |
| TCELL30:OUT17.TMIN | PCIE.L0DLLERRORVECTOR2 |
| TCELL30:OUT18.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED0 |
| TCELL30:OUT19.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED1 |
| TCELL30:OUT20.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED2 |
| TCELL30:OUT21.TMIN | PCIE.L0UCORDFOUND2 |
| TCELL30:OUT22.TMIN | PCIE.L0UCORDFOUND3 |
| TCELL30:OUT23.TMIN | PCIE.PIPERESETL4 |
| TCELL31:IMUX.IMUX0.DELAY | PCIE.PIPERXDATAL54 |
| TCELL31:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAL55 |
| TCELL31:IMUX.IMUX2.DELAY | PCIE.PIPERXDATAL56 |
| TCELL31:IMUX.IMUX3.DELAY | PCIE.PIPERXDATAL57 |
| TCELL31:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA20 |
| TCELL31:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA21 |
| TCELL31:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA22 |
| TCELL31:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA23 |
| TCELL31:IMUX.IMUX8.DELAY | PCIE.MIMDLLBRDATA47 |
| TCELL31:IMUX.IMUX9.DELAY | PCIE.MIMDLLBRDATA48 |
| TCELL31:IMUX.IMUX10.DELAY | PCIE.MIMDLLBRDATA49 |
| TCELL31:IMUX.IMUX11.DELAY | PCIE.MIMDLLBRDATA50 |
| TCELL31:IMUX.IMUX12.DELAY | PCIE.MGMTWDATA21 |
| TCELL31:IMUX.IMUX13.DELAY | PCIE.MGMTWDATA22 |
| TCELL31:IMUX.IMUX14.DELAY | PCIE.MGMTWDATA23 |
| TCELL31:IMUX.IMUX15.DELAY | PCIE.L0CFGVCID20 |
| TCELL31:IMUX.IMUX16.DELAY | PCIE.L0CFGVCID21 |
| TCELL31:IMUX.IMUX17.DELAY | PCIE.L0CFGVCID22 |
| TCELL31:IMUX.IMUX18.DELAY | PCIE.L0CFGVCID23 |
| TCELL31:IMUX.IMUX19.DELAY | PCIE.L0TXTLSBFCDATA5 |
| TCELL31:IMUX.IMUX20.DELAY | PCIE.L0TXTLSBFCDATA6 |
| TCELL31:IMUX.IMUX21.DELAY | PCIE.L0TXTLSBFCDATA7 |
| TCELL31:IMUX.IMUX22.DELAY | PCIE.L0TXTLSBFCDATA8 |
| TCELL31:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED43 |
| TCELL31:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED44 |
| TCELL31:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED45 |
| TCELL31:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED46 |
| TCELL31:IMUX.IMUX44.DELAY | PCIE.PIPERXSTATUSL42 |
| TCELL31:IMUX.IMUX45.DELAY | PCIE.PIPERXSTATUSL41 |
| TCELL31:IMUX.IMUX46.DELAY | PCIE.PIPERXSTATUSL40 |
| TCELL31:IMUX.IMUX47.DELAY | PCIE.PIPERXELECIDLEL4 |
| TCELL31:OUT0.TMIN | PCIE.PIPETXDATAL53 |
| TCELL31:OUT1.TMIN | PCIE.PIPETXDATAL54 |
| TCELL31:OUT2.TMIN | PCIE.PIPETXDATAL55 |
| TCELL31:OUT3.TMIN | PCIE.PIPETXDATAL56 |
| TCELL31:OUT4.TMIN | PCIE.PIPETXCOMPLIANCEL5 |
| TCELL31:OUT5.TMIN | PCIE.PIPERXPOLARITYL5 |
| TCELL31:OUT6.TMIN | PCIE.PIPEPOWERDOWNL50 |
| TCELL31:OUT7.TMIN | PCIE.PIPEPOWERDOWNL51 |
| TCELL31:OUT8.TMIN | PCIE.MIMDLLBWDATA22 |
| TCELL31:OUT9.TMIN | PCIE.MIMDLLBWDATA23 |
| TCELL31:OUT10.TMIN | PCIE.MIMDLLBWDATA24 |
| TCELL31:OUT11.TMIN | PCIE.MIMDLLBWDATA25 |
| TCELL31:OUT12.TMIN | PCIE.MIMDLLBWDATA46 |
| TCELL31:OUT13.TMIN | PCIE.MIMDLLBWDATA47 |
| TCELL31:OUT14.TMIN | PCIE.MIMDLLBWDATA48 |
| TCELL31:OUT15.TMIN | PCIE.L0MCFOUND0 |
| TCELL31:OUT16.TMIN | PCIE.L0MCFOUND1 |
| TCELL31:OUT17.TMIN | PCIE.L0MCFOUND2 |
| TCELL31:OUT18.TMIN | PCIE.L0TRANSFORMEDVC0 |
| TCELL31:OUT19.TMIN | PCIE.L0FWDNONFATALERROUT |
| TCELL31:OUT20.TMIN | PCIE.PIPEDESKEWLANESL4 |
| TCELL31:OUT21.TMIN | PCIE.PIPEPOWERDOWNL41 |
| TCELL31:OUT22.TMIN | PCIE.PIPEPOWERDOWNL40 |
| TCELL31:OUT23.TMIN | PCIE.PIPERXPOLARITYL4 |
| TCELL32:IMUX.IMUX0.DELAY | PCIE.PIPEPHYSTATUSL5 |
| TCELL32:IMUX.IMUX1.DELAY | PCIE.PIPERXDATAKL5 |
| TCELL32:IMUX.IMUX2.DELAY | PCIE.PIPERXVALIDL5 |
| TCELL32:IMUX.IMUX3.DELAY | PCIE.PIPERXCHANISALIGNEDL5 |
| TCELL32:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA43 |
| TCELL32:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA44 |
| TCELL32:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA45 |
| TCELL32:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA46 |
| TCELL32:IMUX.IMUX8.DELAY | PCIE.MGMTWDATA24 |
| TCELL32:IMUX.IMUX9.DELAY | PCIE.MGMTWDATA25 |
| TCELL32:IMUX.IMUX10.DELAY | PCIE.MGMTWDATA26 |
| TCELL32:IMUX.IMUX11.DELAY | PCIE.MGMTWDATA27 |
| TCELL32:IMUX.IMUX12.DELAY | PCIE.L0CFGVCID16 |
| TCELL32:IMUX.IMUX13.DELAY | PCIE.L0CFGVCID17 |
| TCELL32:IMUX.IMUX14.DELAY | PCIE.L0CFGVCID18 |
| TCELL32:IMUX.IMUX15.DELAY | PCIE.L0CFGVCID19 |
| TCELL32:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER91 |
| TCELL32:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER92 |
| TCELL32:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER93 |
| TCELL32:IMUX.IMUX19.DELAY | PCIE.L0PACKETHEADERFROMUSER94 |
| TCELL32:IMUX.IMUX20.DELAY | PCIE.L0MSIREQUEST01 |
| TCELL32:IMUX.IMUX21.DELAY | PCIE.L0MSIREQUEST02 |
| TCELL32:IMUX.IMUX22.DELAY | PCIE.L0MSIREQUEST03 |
| TCELL32:IMUX.IMUX23.DELAY | PCIE.L0TXTLSBFCDATA9 |
| TCELL32:IMUX.IMUX24.DELAY | PCIE.L0TXTLSBFCDATA10 |
| TCELL32:IMUX.IMUX25.DELAY | PCIE.L0TXTLSBFCDATA11 |
| TCELL32:IMUX.IMUX26.DELAY | PCIE.L0TXTLSBFCDATA12 |
| TCELL32:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED39 |
| TCELL32:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED40 |
| TCELL32:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED41 |
| TCELL32:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED42 |
| TCELL32:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED71 |
| TCELL32:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED72 |
| TCELL32:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED73 |
| TCELL32:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED74 |
| TCELL32:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED117 |
| TCELL32:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCPOSTORDCRED118 |
| TCELL32:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCPOSTORDCRED119 |
| TCELL32:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCPOSTORDCRED120 |
| TCELL32:OUT0.TMIN | PCIE.PIPETXDATAL57 |
| TCELL32:OUT1.TMIN | PCIE.PIPETXDATAKL5 |
| TCELL32:OUT2.TMIN | PCIE.PIPETXELECIDLEL5 |
| TCELL32:OUT3.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL5 |
| TCELL32:OUT4.TMIN | PCIE.MIMDLLBWDATA26 |
| TCELL32:OUT5.TMIN | PCIE.MIMDLLBWDATA27 |
| TCELL32:OUT6.TMIN | PCIE.MIMDLLBWDATA28 |
| TCELL32:OUT7.TMIN | PCIE.MIMDLLBWDATA29 |
| TCELL32:OUT8.TMIN | PCIE.MIMDLLBWDATA42 |
| TCELL32:OUT9.TMIN | PCIE.MIMDLLBWDATA43 |
| TCELL32:OUT10.TMIN | PCIE.MIMDLLBWDATA44 |
| TCELL32:OUT11.TMIN | PCIE.MIMDLLBWDATA45 |
| TCELL32:OUT12.TMIN | PCIE.MGMTRDATA23 |
| TCELL32:OUT13.TMIN | PCIE.MGMTRDATA24 |
| TCELL32:OUT14.TMIN | PCIE.MGMTRDATA25 |
| TCELL32:OUT15.TMIN | PCIE.L0DLUPDOWN7 |
| TCELL32:OUT16.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED3 |
| TCELL32:OUT17.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED4 |
| TCELL32:OUT18.TMIN | PCIE.L0TRANSFORMEDVC1 |
| TCELL32:OUT19.TMIN | PCIE.L0TRANSFORMEDVC2 |
| TCELL32:OUT20.TMIN | PCIE.PIPETXCOMPLIANCEL4 |
| TCELL32:OUT21.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL4 |
| TCELL32:OUT22.TMIN | PCIE.PIPETXELECIDLEL4 |
| TCELL32:OUT23.TMIN | PCIE.PIPETXDATAKL4 |
| TCELL33:IMUX.IMUX0.DELAY | PCIE.MIMDLLBRDATA24 |
| TCELL33:IMUX.IMUX1.DELAY | PCIE.MIMDLLBRDATA25 |
| TCELL33:IMUX.IMUX2.DELAY | PCIE.MIMDLLBRDATA26 |
| TCELL33:IMUX.IMUX3.DELAY | PCIE.MIMDLLBRDATA27 |
| TCELL33:IMUX.IMUX4.DELAY | PCIE.MIMDLLBRDATA28 |
| TCELL33:IMUX.IMUX5.DELAY | PCIE.MIMDLLBRDATA29 |
| TCELL33:IMUX.IMUX6.DELAY | PCIE.MIMDLLBRDATA30 |
| TCELL33:IMUX.IMUX7.DELAY | PCIE.MIMDLLBRDATA31 |
| TCELL33:IMUX.IMUX8.DELAY | PCIE.MIMDLLBRDATA32 |
| TCELL33:IMUX.IMUX9.DELAY | PCIE.MIMDLLBRDATA33 |
| TCELL33:IMUX.IMUX10.DELAY | PCIE.MIMDLLBRDATA34 |
| TCELL33:IMUX.IMUX11.DELAY | PCIE.MIMDLLBRDATA35 |
| TCELL33:IMUX.IMUX12.DELAY | PCIE.MIMDLLBRDATA36 |
| TCELL33:IMUX.IMUX13.DELAY | PCIE.MIMDLLBRDATA37 |
| TCELL33:IMUX.IMUX14.DELAY | PCIE.MIMDLLBRDATA38 |
| TCELL33:IMUX.IMUX15.DELAY | PCIE.L0CFGVCID12 |
| TCELL33:IMUX.IMUX16.DELAY | PCIE.L0CFGVCID13 |
| TCELL33:IMUX.IMUX17.DELAY | PCIE.L0CFGVCID14 |
| TCELL33:IMUX.IMUX18.DELAY | PCIE.L0CFGVCID15 |
| TCELL33:IMUX.IMUX19.DELAY | PCIE.L0TXTLSBFCDATA13 |
| TCELL33:IMUX.IMUX20.DELAY | PCIE.L0TXTLSBFCDATA14 |
| TCELL33:IMUX.IMUX21.DELAY | PCIE.L0TXTLSBFCDATA15 |
| TCELL33:IMUX.IMUX22.DELAY | PCIE.L0TXTLSBFCDATA16 |
| TCELL33:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED38 |
| TCELL33:IMUX.IMUX44.DELAY | PCIE.PIPERXCHANISALIGNEDL0 |
| TCELL33:IMUX.IMUX45.DELAY | PCIE.PIPERXVALIDL0 |
| TCELL33:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAKL0 |
| TCELL33:IMUX.IMUX47.DELAY | PCIE.PIPEPHYSTATUSL0 |
| TCELL33:OUT0.TMIN | PCIE.MIMDLLBWDATA30 |
| TCELL33:OUT1.TMIN | PCIE.MIMDLLBWDATA31 |
| TCELL33:OUT2.TMIN | PCIE.MIMDLLBWDATA32 |
| TCELL33:OUT3.TMIN | PCIE.MIMDLLBWDATA33 |
| TCELL33:OUT4.TMIN | PCIE.MIMDLLBWDATA38 |
| TCELL33:OUT5.TMIN | PCIE.MIMDLLBWDATA39 |
| TCELL33:OUT6.TMIN | PCIE.MIMDLLBWDATA40 |
| TCELL33:OUT7.TMIN | PCIE.MIMDLLBWDATA41 |
| TCELL33:OUT8.TMIN | PCIE.MGMTRDATA26 |
| TCELL33:OUT9.TMIN | PCIE.MGMTRDATA27 |
| TCELL33:OUT10.TMIN | PCIE.MGMTRDATA28 |
| TCELL33:OUT11.TMIN | PCIE.MGMTRDATA29 |
| TCELL33:OUT12.TMIN | PCIE.L0DLUPDOWN3 |
| TCELL33:OUT13.TMIN | PCIE.L0DLUPDOWN4 |
| TCELL33:OUT14.TMIN | PCIE.L0DLUPDOWN5 |
| TCELL33:OUT15.TMIN | PCIE.L0DLUPDOWN6 |
| TCELL33:OUT16.TMIN | PCIE.L0ATTENTIONINDICATORCONTROL0 |
| TCELL33:OUT17.TMIN | PCIE.L0ATTENTIONINDICATORCONTROL1 |
| TCELL33:OUT18.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED5 |
| TCELL33:OUT19.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED6 |
| TCELL33:OUT20.TMIN | PCIE.PIPETXDATAL47 |
| TCELL33:OUT21.TMIN | PCIE.PIPETXDATAL46 |
| TCELL33:OUT22.TMIN | PCIE.PIPETXDATAL45 |
| TCELL33:OUT23.TMIN | PCIE.PIPETXDATAL44 |
| TCELL34:IMUX.IMUX0.DELAY | PCIE.MIMDLLBRDATA39 |
| TCELL34:IMUX.IMUX1.DELAY | PCIE.MIMDLLBRDATA40 |
| TCELL34:IMUX.IMUX2.DELAY | PCIE.MIMDLLBRDATA41 |
| TCELL34:IMUX.IMUX3.DELAY | PCIE.MIMDLLBRDATA42 |
| TCELL34:IMUX.IMUX4.DELAY | PCIE.MGMTWDATA28 |
| TCELL34:IMUX.IMUX5.DELAY | PCIE.MGMTWDATA29 |
| TCELL34:IMUX.IMUX6.DELAY | PCIE.MGMTWDATA30 |
| TCELL34:IMUX.IMUX7.DELAY | PCIE.MGMTWDATA31 |
| TCELL34:IMUX.IMUX8.DELAY | PCIE.L0CFGVCID8 |
| TCELL34:IMUX.IMUX9.DELAY | PCIE.L0CFGVCID9 |
| TCELL34:IMUX.IMUX10.DELAY | PCIE.L0CFGVCID10 |
| TCELL34:IMUX.IMUX11.DELAY | PCIE.L0CFGVCID11 |
| TCELL34:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER95 |
| TCELL34:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER96 |
| TCELL34:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER97 |
| TCELL34:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER98 |
| TCELL34:IMUX.IMUX16.DELAY | PCIE.L0FWDDEASSERTINTCLEGACYINT |
| TCELL34:IMUX.IMUX17.DELAY | PCIE.L0FWDDEASSERTINTDLEGACYINT |
| TCELL34:IMUX.IMUX18.DELAY | PCIE.L0MSIREQUEST00 |
| TCELL34:IMUX.IMUX19.DELAY | PCIE.L0TXTLSBFCDATA17 |
| TCELL34:IMUX.IMUX20.DELAY | PCIE.L0TXTLSBFCDATA18 |
| TCELL34:IMUX.IMUX21.DELAY | PCIE.L0TXTLSBFCUPDATE |
| TCELL34:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED0 |
| TCELL34:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED34 |
| TCELL34:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED35 |
| TCELL34:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED36 |
| TCELL34:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED37 |
| TCELL34:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED75 |
| TCELL34:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED76 |
| TCELL34:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED77 |
| TCELL34:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED78 |
| TCELL34:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED114 |
| TCELL34:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED115 |
| TCELL34:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED116 |
| TCELL34:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL07 |
| TCELL34:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL06 |
| TCELL34:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL05 |
| TCELL34:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL04 |
| TCELL34:OUT0.TMIN | PCIE.MIMDLLBWDATA34 |
| TCELL34:OUT1.TMIN | PCIE.MIMDLLBWDATA35 |
| TCELL34:OUT2.TMIN | PCIE.MIMDLLBWDATA36 |
| TCELL34:OUT3.TMIN | PCIE.MIMDLLBWDATA37 |
| TCELL34:OUT4.TMIN | PCIE.MGMTRDATA30 |
| TCELL34:OUT5.TMIN | PCIE.MGMTRDATA31 |
| TCELL34:OUT6.TMIN | PCIE.MGMTPSO0 |
| TCELL34:OUT7.TMIN | PCIE.MGMTPSO1 |
| TCELL34:OUT8.TMIN | PCIE.L0DLLVCSTATUS7 |
| TCELL34:OUT9.TMIN | PCIE.L0DLUPDOWN0 |
| TCELL34:OUT10.TMIN | PCIE.L0DLUPDOWN1 |
| TCELL34:OUT11.TMIN | PCIE.L0DLUPDOWN2 |
| TCELL34:OUT12.TMIN | PCIE.L0POWERINDICATORCONTROL0 |
| TCELL34:OUT13.TMIN | PCIE.L0POWERINDICATORCONTROL1 |
| TCELL34:OUT14.TMIN | PCIE.L0POWERCONTROLLERCONTROL |
| TCELL34:OUT15.TMIN | PCIE.L0TOGGLEELECTROMECHANICALINTERLOCK |
| TCELL34:OUT16.TMIN | PCIE.L0TXDLLFCCMPLMCUPDATED7 |
| TCELL34:OUT17.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED0 |
| TCELL34:OUT18.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED1 |
| TCELL34:OUT19.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED2 |
| TCELL34:OUT20.TMIN | PCIE.PIPETXDATAL43 |
| TCELL34:OUT21.TMIN | PCIE.PIPETXDATAL42 |
| TCELL34:OUT22.TMIN | PCIE.PIPETXDATAL41 |
| TCELL34:OUT23.TMIN | PCIE.PIPETXDATAL40 |
| TCELL35:IMUX.IMUX0.DELAY | PCIE.MGMTBWREN0 |
| TCELL35:IMUX.IMUX1.DELAY | PCIE.MGMTBWREN1 |
| TCELL35:IMUX.IMUX2.DELAY | PCIE.MGMTBWREN2 |
| TCELL35:IMUX.IMUX3.DELAY | PCIE.MGMTBWREN3 |
| TCELL35:IMUX.IMUX4.DELAY | PCIE.L0CFGVCID4 |
| TCELL35:IMUX.IMUX5.DELAY | PCIE.L0CFGVCID5 |
| TCELL35:IMUX.IMUX6.DELAY | PCIE.L0CFGVCID6 |
| TCELL35:IMUX.IMUX7.DELAY | PCIE.L0CFGVCID7 |
| TCELL35:IMUX.IMUX8.DELAY | PCIE.L0PACKETHEADERFROMUSER99 |
| TCELL35:IMUX.IMUX9.DELAY | PCIE.L0PACKETHEADERFROMUSER100 |
| TCELL35:IMUX.IMUX10.DELAY | PCIE.L0PACKETHEADERFROMUSER101 |
| TCELL35:IMUX.IMUX11.DELAY | PCIE.L0PACKETHEADERFROMUSER102 |
| TCELL35:IMUX.IMUX12.DELAY | PCIE.L0FWDASSERTINTCLEGACYINT |
| TCELL35:IMUX.IMUX13.DELAY | PCIE.L0FWDASSERTINTDLEGACYINT |
| TCELL35:IMUX.IMUX14.DELAY | PCIE.L0FWDDEASSERTINTALEGACYINT |
| TCELL35:IMUX.IMUX15.DELAY | PCIE.L0FWDDEASSERTINTBLEGACYINT |
| TCELL35:IMUX.IMUX16.DELAY | PCIE.L0ELECTROMECHANICALINTERLOCKENGAGED |
| TCELL35:IMUX.IMUX17.DELAY | PCIE.L0MRLSENSORCLOSEDN |
| TCELL35:IMUX.IMUX18.DELAY | PCIE.L0POWERFAULTDETECTED |
| TCELL35:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED1 |
| TCELL35:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED2 |
| TCELL35:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED3 |
| TCELL35:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED4 |
| TCELL35:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED30 |
| TCELL35:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED31 |
| TCELL35:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED32 |
| TCELL35:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED33 |
| TCELL35:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED79 |
| TCELL35:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED80 |
| TCELL35:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED81 |
| TCELL35:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED82 |
| TCELL35:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED110 |
| TCELL35:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED111 |
| TCELL35:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED112 |
| TCELL35:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED113 |
| TCELL35:IMUX.IMUX44.DELAY | PCIE.PIPERXDATAL03 |
| TCELL35:IMUX.IMUX45.DELAY | PCIE.PIPERXDATAL02 |
| TCELL35:IMUX.IMUX46.DELAY | PCIE.PIPERXDATAL01 |
| TCELL35:IMUX.IMUX47.DELAY | PCIE.PIPERXDATAL00 |
| TCELL35:OUT0.TMIN | PCIE.MGMTPSO2 |
| TCELL35:OUT1.TMIN | PCIE.MGMTPSO3 |
| TCELL35:OUT2.TMIN | PCIE.MGMTPSO4 |
| TCELL35:OUT3.TMIN | PCIE.L0DLLVCSTATUS3 |
| TCELL35:OUT4.TMIN | PCIE.L0DLLVCSTATUS4 |
| TCELL35:OUT5.TMIN | PCIE.L0DLLVCSTATUS5 |
| TCELL35:OUT6.TMIN | PCIE.L0DLLVCSTATUS6 |
| TCELL35:OUT7.TMIN | PCIE.L0RXBEACON |
| TCELL35:OUT8.TMIN | PCIE.L0PWRSTATE00 |
| TCELL35:OUT9.TMIN | PCIE.L0PWRSTATE01 |
| TCELL35:OUT10.TMIN | PCIE.L0PMEACK |
| TCELL35:OUT11.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED3 |
| TCELL35:OUT12.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED4 |
| TCELL35:OUT13.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED5 |
| TCELL35:OUT14.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED6 |
| TCELL35:OUT15.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE0 |
| TCELL35:OUT16.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE1 |
| TCELL35:OUT17.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE2 |
| TCELL35:OUT18.TMIN | PCIE.L0RXDLLFCNPOSTBYPUPDATE3 |
| TCELL35:OUT19.TMIN | PCIE.BUSMASTERENABLE |
| TCELL35:OUT20.TMIN | PCIE.PARITYERRORRESPONSE |
| TCELL35:OUT21.TMIN | PCIE.SERRENABLE |
| TCELL35:OUT22.TMIN | PCIE.INTERRUPTDISABLE |
| TCELL35:OUT23.TMIN | PCIE.PIPERESETL0 |
| TCELL36:IMUX.IMUX0.DELAY | PCIE.MGMTWREN |
| TCELL36:IMUX.IMUX1.DELAY | PCIE.MGMTADDR0 |
| TCELL36:IMUX.IMUX2.DELAY | PCIE.MGMTADDR1 |
| TCELL36:IMUX.IMUX3.DELAY | PCIE.MGMTADDR2 |
| TCELL36:IMUX.IMUX4.DELAY | PCIE.L0CFGVCID0 |
| TCELL36:IMUX.IMUX5.DELAY | PCIE.L0CFGVCID1 |
| TCELL36:IMUX.IMUX6.DELAY | PCIE.L0CFGVCID2 |
| TCELL36:IMUX.IMUX7.DELAY | PCIE.L0CFGVCID3 |
| TCELL36:IMUX.IMUX8.DELAY | PCIE.L0PACKETHEADERFROMUSER103 |
| TCELL36:IMUX.IMUX9.DELAY | PCIE.L0PACKETHEADERFROMUSER104 |
| TCELL36:IMUX.IMUX10.DELAY | PCIE.L0PACKETHEADERFROMUSER105 |
| TCELL36:IMUX.IMUX11.DELAY | PCIE.L0PACKETHEADERFROMUSER106 |
| TCELL36:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER127 |
| TCELL36:IMUX.IMUX13.DELAY | PCIE.L0LEGACYINTFUNCT0 |
| TCELL36:IMUX.IMUX14.DELAY | PCIE.L0FWDASSERTINTALEGACYINT |
| TCELL36:IMUX.IMUX15.DELAY | PCIE.L0FWDASSERTINTBLEGACYINT |
| TCELL36:IMUX.IMUX16.DELAY | PCIE.L0PRESENCEDETECTSLOTEMPTYN |
| TCELL36:IMUX.IMUX17.DELAY | PCIE.L0ATTENTIONBUTTONPRESSED |
| TCELL36:IMUX.IMUX18.DELAY | PCIE.L0TXBEACON |
| TCELL36:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED5 |
| TCELL36:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED6 |
| TCELL36:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED7 |
| TCELL36:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED8 |
| TCELL36:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED26 |
| TCELL36:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED27 |
| TCELL36:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED28 |
| TCELL36:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED29 |
| TCELL36:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCPOSTORDCRED83 |
| TCELL36:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED84 |
| TCELL36:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED85 |
| TCELL36:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED86 |
| TCELL36:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED107 |
| TCELL36:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED108 |
| TCELL36:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED109 |
| TCELL36:IMUX.IMUX44.DELAY | PCIE.PIPERXSTATUSL02 |
| TCELL36:IMUX.IMUX45.DELAY | PCIE.PIPERXSTATUSL01 |
| TCELL36:IMUX.IMUX46.DELAY | PCIE.PIPERXSTATUSL00 |
| TCELL36:IMUX.IMUX47.DELAY | PCIE.PIPERXELECIDLEL0 |
| TCELL36:OUT0.TMIN | PCIE.MGMTPSO5 |
| TCELL36:OUT1.TMIN | PCIE.MGMTPSO6 |
| TCELL36:OUT2.TMIN | PCIE.MGMTPSO7 |
| TCELL36:OUT3.TMIN | PCIE.MGMTPSO8 |
| TCELL36:OUT4.TMIN | PCIE.L0LTSSMSTATE3 |
| TCELL36:OUT5.TMIN | PCIE.L0DLLVCSTATUS0 |
| TCELL36:OUT6.TMIN | PCIE.L0DLLVCSTATUS1 |
| TCELL36:OUT7.TMIN | PCIE.L0DLLVCSTATUS2 |
| TCELL36:OUT8.TMIN | PCIE.L0PMEREQOUT |
| TCELL36:OUT9.TMIN | PCIE.L0PMEEN |
| TCELL36:OUT10.TMIN | PCIE.L0PWRINHIBITTRANSFERS |
| TCELL36:OUT11.TMIN | PCIE.L0PWRL1STATE |
| TCELL36:OUT12.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED7 |
| TCELL36:OUT13.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED8 |
| TCELL36:OUT14.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED9 |
| TCELL36:OUT15.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED10 |
| TCELL36:OUT16.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED16 |
| TCELL36:OUT17.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED17 |
| TCELL36:OUT18.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED18 |
| TCELL36:OUT19.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED19 |
| TCELL36:OUT20.TMIN | PCIE.PIPEDESKEWLANESL0 |
| TCELL36:OUT21.TMIN | PCIE.PIPEPOWERDOWNL01 |
| TCELL36:OUT22.TMIN | PCIE.PIPEPOWERDOWNL00 |
| TCELL36:OUT23.TMIN | PCIE.PIPERXPOLARITYL0 |
| TCELL37:IMUX.IMUX0.DELAY | PCIE.MGMTADDR3 |
| TCELL37:IMUX.IMUX1.DELAY | PCIE.MGMTADDR4 |
| TCELL37:IMUX.IMUX2.DELAY | PCIE.MGMTADDR5 |
| TCELL37:IMUX.IMUX3.DELAY | PCIE.MGMTADDR6 |
| TCELL37:IMUX.IMUX4.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH5 |
| TCELL37:IMUX.IMUX5.DELAY | PCIE.CROSSLINKSEED |
| TCELL37:IMUX.IMUX6.DELAY | PCIE.COMPLIANCEAVOID |
| TCELL37:IMUX.IMUX7.DELAY | PCIE.L0VC0PREVIEWEXPAND |
| TCELL37:IMUX.IMUX8.DELAY | PCIE.L0PACKETHEADERFROMUSER107 |
| TCELL37:IMUX.IMUX9.DELAY | PCIE.L0PACKETHEADERFROMUSER108 |
| TCELL37:IMUX.IMUX10.DELAY | PCIE.L0PACKETHEADERFROMUSER109 |
| TCELL37:IMUX.IMUX11.DELAY | PCIE.L0PACKETHEADERFROMUSER110 |
| TCELL37:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER123 |
| TCELL37:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER124 |
| TCELL37:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER125 |
| TCELL37:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER126 |
| TCELL37:IMUX.IMUX16.DELAY | PCIE.L0WAKEN |
| TCELL37:IMUX.IMUX17.DELAY | PCIE.L0PMEREQIN |
| TCELL37:IMUX.IMUX18.DELAY | PCIE.L0ROOTTURNOFFREQ |
| TCELL37:IMUX.IMUX19.DELAY | PCIE.L0TXCFGPM |
| TCELL37:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED9 |
| TCELL37:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED10 |
| TCELL37:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED11 |
| TCELL37:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED12 |
| TCELL37:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED22 |
| TCELL37:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED23 |
| TCELL37:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED24 |
| TCELL37:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED25 |
| TCELL37:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCPOSTORDCRED87 |
| TCELL37:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCPOSTORDCRED88 |
| TCELL37:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCPOSTORDCRED89 |
| TCELL37:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCPOSTORDCRED90 |
| TCELL37:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED103 |
| TCELL37:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED104 |
| TCELL37:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED105 |
| TCELL37:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED106 |
| TCELL37:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCCMPLMCCRED124 |
| TCELL37:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCCMPLMCCRED125 |
| TCELL37:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCCMPLMCCRED126 |
| TCELL37:OUT0.TMIN | PCIE.MGMTPSO9 |
| TCELL37:OUT1.TMIN | PCIE.MGMTPSO10 |
| TCELL37:OUT2.TMIN | PCIE.MGMTPSO11 |
| TCELL37:OUT3.TMIN | PCIE.MGMTPSO12 |
| TCELL37:OUT4.TMIN | PCIE.MGMTSTATSCREDIT8 |
| TCELL37:OUT5.TMIN | PCIE.MGMTSTATSCREDIT9 |
| TCELL37:OUT6.TMIN | PCIE.MGMTSTATSCREDIT10 |
| TCELL37:OUT7.TMIN | PCIE.MGMTSTATSCREDIT11 |
| TCELL37:OUT8.TMIN | PCIE.L0MACLINKTRAINING |
| TCELL37:OUT9.TMIN | PCIE.L0LTSSMSTATE0 |
| TCELL37:OUT10.TMIN | PCIE.L0LTSSMSTATE1 |
| TCELL37:OUT11.TMIN | PCIE.L0LTSSMSTATE2 |
| TCELL37:OUT12.TMIN | PCIE.L0PWRL23READYDEVICE |
| TCELL37:OUT13.TMIN | PCIE.L0PWRL23READYSTATE |
| TCELL37:OUT14.TMIN | PCIE.L0PWRTXL0SSTATE |
| TCELL37:OUT15.TMIN | PCIE.L0PWRTURNOFFREQ |
| TCELL37:OUT16.TMIN | PCIE.L0DLLRXACKOUTSTANDING |
| TCELL37:OUT17.TMIN | PCIE.L0DLLTXOUTSTANDING |
| TCELL37:OUT18.TMIN | PCIE.L0DLLTXNONFCOUTSTANDING |
| TCELL37:OUT19.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED11 |
| TCELL37:OUT20.TMIN | PCIE.PIPETXCOMPLIANCEL0 |
| TCELL37:OUT21.TMIN | PCIE.PIPETXDETECTRXLOOPBACKL0 |
| TCELL37:OUT22.TMIN | PCIE.PIPETXELECIDLEL0 |
| TCELL37:OUT23.TMIN | PCIE.PIPETXDATAKL0 |
| TCELL38:IMUX.IMUX0.DELAY | PCIE.MGMTADDR7 |
| TCELL38:IMUX.IMUX1.DELAY | PCIE.MGMTADDR8 |
| TCELL38:IMUX.IMUX2.DELAY | PCIE.MGMTADDR9 |
| TCELL38:IMUX.IMUX3.DELAY | PCIE.MGMTADDR10 |
| TCELL38:IMUX.IMUX4.DELAY | PCIE.MGMTSTATSCREDITSEL3 |
| TCELL38:IMUX.IMUX5.DELAY | PCIE.MGMTSTATSCREDITSEL4 |
| TCELL38:IMUX.IMUX6.DELAY | PCIE.MGMTSTATSCREDITSEL5 |
| TCELL38:IMUX.IMUX7.DELAY | PCIE.MGMTSTATSCREDITSEL6 |
| TCELL38:IMUX.IMUX8.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH1 |
| TCELL38:IMUX.IMUX9.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH2 |
| TCELL38:IMUX.IMUX10.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH3 |
| TCELL38:IMUX.IMUX11.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH4 |
| TCELL38:IMUX.IMUX12.DELAY | PCIE.L0PACKETHEADERFROMUSER111 |
| TCELL38:IMUX.IMUX13.DELAY | PCIE.L0PACKETHEADERFROMUSER112 |
| TCELL38:IMUX.IMUX14.DELAY | PCIE.L0PACKETHEADERFROMUSER113 |
| TCELL38:IMUX.IMUX15.DELAY | PCIE.L0PACKETHEADERFROMUSER114 |
| TCELL38:IMUX.IMUX16.DELAY | PCIE.L0PACKETHEADERFROMUSER119 |
| TCELL38:IMUX.IMUX17.DELAY | PCIE.L0PACKETHEADERFROMUSER120 |
| TCELL38:IMUX.IMUX18.DELAY | PCIE.L0PACKETHEADERFROMUSER121 |
| TCELL38:IMUX.IMUX19.DELAY | PCIE.L0PACKETHEADERFROMUSER122 |
| TCELL38:IMUX.IMUX20.DELAY | PCIE.L0TXCFGPMTYPE0 |
| TCELL38:IMUX.IMUX21.DELAY | PCIE.L0TXCFGPMTYPE1 |
| TCELL38:IMUX.IMUX22.DELAY | PCIE.L0TXCFGPMTYPE2 |
| TCELL38:IMUX.IMUX23.DELAY | PCIE.L0PWRNEWSTATEREQ |
| TCELL38:IMUX.IMUX24.DELAY | PCIE.L0CFGL0SEXITLAT0 |
| TCELL38:IMUX.IMUX25.DELAY | PCIE.L0CFGL0SEXITLAT1 |
| TCELL38:IMUX.IMUX26.DELAY | PCIE.L0CFGL0SEXITLAT2 |
| TCELL38:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED13 |
| TCELL38:IMUX.IMUX28.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED18 |
| TCELL38:IMUX.IMUX29.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED19 |
| TCELL38:IMUX.IMUX30.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED20 |
| TCELL38:IMUX.IMUX31.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED21 |
| TCELL38:IMUX.IMUX32.DELAY | PCIE.L0TXTLFCPOSTORDCRED91 |
| TCELL38:IMUX.IMUX33.DELAY | PCIE.L0TXTLFCPOSTORDCRED92 |
| TCELL38:IMUX.IMUX34.DELAY | PCIE.L0TXTLFCPOSTORDCRED93 |
| TCELL38:IMUX.IMUX35.DELAY | PCIE.L0TXTLFCPOSTORDCRED94 |
| TCELL38:IMUX.IMUX36.DELAY | PCIE.L0TXTLFCPOSTORDCRED99 |
| TCELL38:IMUX.IMUX37.DELAY | PCIE.L0TXTLFCPOSTORDCRED100 |
| TCELL38:IMUX.IMUX38.DELAY | PCIE.L0TXTLFCPOSTORDCRED101 |
| TCELL38:IMUX.IMUX39.DELAY | PCIE.L0TXTLFCPOSTORDCRED102 |
| TCELL38:OUT0.TMIN | PCIE.MGMTPSO13 |
| TCELL38:OUT1.TMIN | PCIE.MGMTPSO14 |
| TCELL38:OUT2.TMIN | PCIE.MGMTPSO15 |
| TCELL38:OUT3.TMIN | PCIE.MGMTPSO16 |
| TCELL38:OUT4.TMIN | PCIE.MGMTSTATSCREDIT4 |
| TCELL38:OUT5.TMIN | PCIE.MGMTSTATSCREDIT5 |
| TCELL38:OUT6.TMIN | PCIE.MGMTSTATSCREDIT6 |
| TCELL38:OUT7.TMIN | PCIE.MGMTSTATSCREDIT7 |
| TCELL38:OUT8.TMIN | PCIE.L0RXDLLTLPECRCOK |
| TCELL38:OUT9.TMIN | PCIE.DLLTXPMDLLPOUTSTANDING |
| TCELL38:OUT10.TMIN | PCIE.L0FIRSTCFGWRITEOCCURRED |
| TCELL38:OUT11.TMIN | PCIE.L0CFGLOOPBACKACK |
| TCELL38:OUT12.TMIN | PCIE.L0MACNEGOTIATEDLINKWIDTH0 |
| TCELL38:OUT13.TMIN | PCIE.L0MACNEGOTIATEDLINKWIDTH1 |
| TCELL38:OUT14.TMIN | PCIE.L0MACNEGOTIATEDLINKWIDTH2 |
| TCELL38:OUT15.TMIN | PCIE.L0MACNEGOTIATEDLINKWIDTH3 |
| TCELL38:OUT16.TMIN | PCIE.L0RXDLLPM |
| TCELL38:OUT17.TMIN | PCIE.L0RXDLLPMTYPE0 |
| TCELL38:OUT18.TMIN | PCIE.L0RXDLLPMTYPE1 |
| TCELL38:OUT19.TMIN | PCIE.L0RXDLLPMTYPE2 |
| TCELL38:OUT20.TMIN | PCIE.PIPETXDATAL07 |
| TCELL38:OUT21.TMIN | PCIE.PIPETXDATAL06 |
| TCELL38:OUT22.TMIN | PCIE.PIPETXDATAL05 |
| TCELL38:OUT23.TMIN | PCIE.PIPETXDATAL04 |
| TCELL39:IMUX.IMUX0.DELAY | PCIE.MGMTRDEN |
| TCELL39:IMUX.IMUX1.DELAY | PCIE.MGMTSTATSCREDITSEL0 |
| TCELL39:IMUX.IMUX2.DELAY | PCIE.MGMTSTATSCREDITSEL1 |
| TCELL39:IMUX.IMUX3.DELAY | PCIE.MGMTSTATSCREDITSEL2 |
| TCELL39:IMUX.IMUX4.DELAY | PCIE.MAINPOWER |
| TCELL39:IMUX.IMUX5.DELAY | PCIE.AUXPOWER |
| TCELL39:IMUX.IMUX6.DELAY | PCIE.L0TLLINKRETRAIN |
| TCELL39:IMUX.IMUX7.DELAY | PCIE.CFGNEGOTIATEDLINKWIDTH0 |
| TCELL39:IMUX.IMUX8.DELAY | PCIE.L0PACKETHEADERFROMUSER115 |
| TCELL39:IMUX.IMUX9.DELAY | PCIE.L0PACKETHEADERFROMUSER116 |
| TCELL39:IMUX.IMUX10.DELAY | PCIE.L0PACKETHEADERFROMUSER117 |
| TCELL39:IMUX.IMUX11.DELAY | PCIE.L0PACKETHEADERFROMUSER118 |
| TCELL39:IMUX.IMUX12.DELAY | PCIE.L0PWRNEXTLINKSTATE0 |
| TCELL39:IMUX.IMUX13.DELAY | PCIE.L0PWRNEXTLINKSTATE1 |
| TCELL39:IMUX.IMUX14.DELAY | PCIE.L0CFGL0SENTRYSUP |
| TCELL39:IMUX.IMUX15.DELAY | PCIE.L0CFGL0SENTRYENABLE |
| TCELL39:IMUX.IMUX16.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED14 |
| TCELL39:IMUX.IMUX17.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED15 |
| TCELL39:IMUX.IMUX18.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED16 |
| TCELL39:IMUX.IMUX19.DELAY | PCIE.L0TXTLFCNPOSTBYPCRED17 |
| TCELL39:IMUX.IMUX20.DELAY | PCIE.L0TXTLFCPOSTORDCRED95 |
| TCELL39:IMUX.IMUX21.DELAY | PCIE.L0TXTLFCPOSTORDCRED96 |
| TCELL39:IMUX.IMUX22.DELAY | PCIE.L0TXTLFCPOSTORDCRED97 |
| TCELL39:IMUX.IMUX23.DELAY | PCIE.L0TXTLFCPOSTORDCRED98 |
| TCELL39:IMUX.IMUX24.DELAY | PCIE.L0TXTLFCCMPLMCCRED127 |
| TCELL39:IMUX.IMUX25.DELAY | PCIE.L0TXTLFCCMPLMCCRED128 |
| TCELL39:IMUX.IMUX26.DELAY | PCIE.L0TXTLFCCMPLMCCRED129 |
| TCELL39:IMUX.IMUX27.DELAY | PCIE.L0TXTLFCCMPLMCCRED130 |
| TCELL39:OUT0.TMIN | PCIE.MGMTSTATSCREDIT0 |
| TCELL39:OUT1.TMIN | PCIE.MGMTSTATSCREDIT1 |
| TCELL39:OUT2.TMIN | PCIE.MGMTSTATSCREDIT2 |
| TCELL39:OUT3.TMIN | PCIE.MGMTSTATSCREDIT3 |
| TCELL39:OUT4.TMIN | PCIE.L0MACUPSTREAMDOWNSTREAM |
| TCELL39:OUT5.TMIN | PCIE.L0RXMACLINKERROR0 |
| TCELL39:OUT6.TMIN | PCIE.L0RXMACLINKERROR1 |
| TCELL39:OUT7.TMIN | PCIE.L0MACLINKUP |
| TCELL39:OUT8.TMIN | PCIE.L0TXDLLPMUPDATED |
| TCELL39:OUT9.TMIN | PCIE.L0MACNEWSTATEACK |
| TCELL39:OUT10.TMIN | PCIE.L0MACRXL0SSTATE |
| TCELL39:OUT11.TMIN | PCIE.L0MACENTEREDL0 |
| TCELL39:OUT12.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED12 |
| TCELL39:OUT13.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED13 |
| TCELL39:OUT14.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED14 |
| TCELL39:OUT16.TMIN | PCIE.URREPORTINGENABLE |
| TCELL39:OUT18.TMIN | PCIE.L0RXDLLFCNPOSTBYPCRED15 |
| TCELL39:OUT19.TMIN | PCIE.LLKRXCHPOSTEDPARTIALN7 |
| TCELL39:OUT20.TMIN | PCIE.PIPETXDATAL03 |
| TCELL39:OUT21.TMIN | PCIE.PIPETXDATAL02 |
| TCELL39:OUT22.TMIN | PCIE.PIPETXDATAL01 |
| TCELL39:OUT23.TMIN | PCIE.PIPETXDATAL00 |
Bitstream
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSNPH[3] | PCIE:VC0TOTALCREDITSNPH[2] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSNPH[0] | PCIE:VC0TOTALCREDITSNPH[1] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPH[6] | PCIE:VC0TOTALCREDITSPH[5] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPH[3] | PCIE:VC0TOTALCREDITSPH[4] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPH[2] | PCIE:VC0TOTALCREDITSPH[1] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[12] | PCIE:VC0TOTALCREDITSPH[0] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[11] | PCIE:VC0TXFIFOLIMITC[10] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[8] | PCIE:VC0TXFIFOLIMITC[9] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[7] | PCIE:VC0TXFIFOLIMITC[6] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[4] | PCIE:VC0TXFIFOLIMITC[5] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[3] | PCIE:VC0TXFIFOLIMITC[2] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITC[0] | PCIE:VC0TXFIFOLIMITC[1] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[12] | PCIE:VC0TXFIFOLIMITNP[11] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[9] | PCIE:VC0TXFIFOLIMITNP[10] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[8] | PCIE:VC0TXFIFOLIMITNP[7] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[5] | PCIE:VC0TXFIFOLIMITNP[6] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[4] | PCIE:VC0TXFIFOLIMITNP[3] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[1] | PCIE:VC0TXFIFOLIMITNP[2] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITNP[0] | PCIE:VC0TXFIFOLIMITP[12] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[10] | PCIE:VC0TXFIFOLIMITP[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[9] | PCIE:VC0TXFIFOLIMITP[8] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[6] | PCIE:VC0TXFIFOLIMITP[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[5] | PCIE:VC0TXFIFOLIMITP[4] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[2] | PCIE:VC0TXFIFOLIMITP[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOLIMITP[1] | PCIE:VC0TXFIFOLIMITP[0] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[11] | PCIE:VC0TXFIFOBASEC[12] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[10] | PCIE:VC0TXFIFOBASEC[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[7] | PCIE:VC0TXFIFOBASEC[8] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[6] | PCIE:VC0TXFIFOBASEC[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[3] | PCIE:VC0TXFIFOBASEC[4] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEC[2] | PCIE:VC0TXFIFOBASEC[1] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[12] | PCIE:VC0TXFIFOBASEC[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[11] | PCIE:VC0TXFIFOBASENP[10] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[8] | PCIE:VC0TXFIFOBASENP[9] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[7] | PCIE:VC0TXFIFOBASENP[6] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[4] | PCIE:VC0TXFIFOBASENP[5] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[3] | PCIE:VC0TXFIFOBASENP[2] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASENP[0] | PCIE:VC0TXFIFOBASENP[1] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[12] | PCIE:VC0TXFIFOBASEP[11] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[9] | PCIE:VC0TXFIFOBASEP[10] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[8] | PCIE:VC0TXFIFOBASEP[7] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[5] | PCIE:VC0TXFIFOBASEP[6] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[4] | PCIE:VC0TXFIFOBASEP[3] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[1] | PCIE:VC0TXFIFOBASEP[2] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TXFIFOBASEP[0] | PCIE:INV.CRMUSERCLKRXO |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INV.CRMCORECLKRXO | PCIE:INV.CRMUSERCLKTXO |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INV.CRMCORECLKTXO | PCIE:INV.CRMCORECLKDLO |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INV.CRMCORECLK | PCIE:INV.CRMUSERCLK |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[11] | PCIE:VC0RXFIFOLIMITNP[10] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[8] | PCIE:VC0RXFIFOLIMITNP[9] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[7] | PCIE:VC0RXFIFOLIMITNP[6] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[4] | PCIE:VC0RXFIFOLIMITNP[5] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[3] | PCIE:VC0RXFIFOLIMITNP[2] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[0] | PCIE:VC0RXFIFOLIMITNP[1] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[12] | PCIE:VC0RXFIFOLIMITP[11] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[9] | PCIE:VC0RXFIFOLIMITP[10] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[8] | PCIE:VC0RXFIFOLIMITP[7] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[5] | PCIE:VC0RXFIFOLIMITP[6] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[4] | PCIE:VC0RXFIFOLIMITP[3] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[1] | PCIE:VC0RXFIFOLIMITP[2] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITP[0] | PCIE:VC0RXFIFOBASEC[12] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[10] | PCIE:VC0RXFIFOBASEC[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[9] | PCIE:VC0RXFIFOBASEC[8] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[6] | PCIE:VC0RXFIFOBASEC[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[5] | PCIE:VC0RXFIFOBASEC[4] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[2] | PCIE:VC0RXFIFOBASEC[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEC[1] | PCIE:VC0RXFIFOBASEC[0] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[11] | PCIE:VC0RXFIFOBASENP[12] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[10] | PCIE:VC0RXFIFOBASENP[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[7] | PCIE:VC0RXFIFOBASENP[8] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[6] | PCIE:VC0RXFIFOBASENP[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[3] | PCIE:VC0RXFIFOBASENP[4] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASENP[2] | PCIE:VC0RXFIFOBASENP[1] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[12] | PCIE:VC0RXFIFOBASENP[0] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[11] | PCIE:VC0RXFIFOBASEP[10] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[8] | PCIE:VC0RXFIFOBASEP[9] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[7] | PCIE:VC0RXFIFOBASEP[6] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[4] | PCIE:VC0RXFIFOBASEP[5] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[3] | PCIE:VC0RXFIFOBASEP[2] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOBASEP[0] | PCIE:VC0RXFIFOBASEP[1] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCD[10] | PCIE:VC0TOTALCREDITSCD[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCD[7] | PCIE:VC0TOTALCREDITSCD[8] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCD[6] | PCIE:VC0TOTALCREDITSCD[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCD[3] | PCIE:VC0TOTALCREDITSCD[4] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCD[2] | PCIE:VC0TOTALCREDITSCD[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[10] | PCIE:VC0TOTALCREDITSCD[0] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[9] | PCIE:VC0TOTALCREDITSPD[8] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[6] | PCIE:VC0TOTALCREDITSPD[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[5] | PCIE:VC0TOTALCREDITSPD[4] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[2] | PCIE:VC0TOTALCREDITSPD[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSPD[1] | PCIE:VC0TOTALCREDITSPD[0] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCH[5] | PCIE:VC0TOTALCREDITSCH[6] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCH[4] | PCIE:VC0TOTALCREDITSCH[3] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCH[1] | PCIE:VC0TOTALCREDITSCH[2] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSCH[0] | PCIE:VC0TOTALCREDITSNPH[6] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0TOTALCREDITSNPH[4] | PCIE:VC0TOTALCREDITSNPH[5] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPH[3] | PCIE:VC1TOTALCREDITSPH[2] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPH[0] | PCIE:VC1TOTALCREDITSPH[1] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[12] | PCIE:VC1TXFIFOLIMITC[11] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[9] | PCIE:VC1TXFIFOLIMITC[10] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[8] | PCIE:VC1TXFIFOLIMITC[7] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[5] | PCIE:VC1TXFIFOLIMITC[6] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[4] | PCIE:VC1TXFIFOLIMITC[3] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[1] | PCIE:VC1TXFIFOLIMITC[2] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITC[0] | PCIE:VC1TXFIFOLIMITNP[12] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[10] | PCIE:VC1TXFIFOLIMITNP[11] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[9] | PCIE:VC1TXFIFOLIMITNP[8] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[6] | PCIE:VC1TXFIFOLIMITNP[7] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[5] | PCIE:VC1TXFIFOLIMITNP[4] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[2] | PCIE:VC1TXFIFOLIMITNP[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITNP[1] | PCIE:VC1TXFIFOLIMITNP[0] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[11] | PCIE:VC1TXFIFOLIMITP[12] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[10] | PCIE:VC1TXFIFOLIMITP[9] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[7] | PCIE:VC1TXFIFOLIMITP[8] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[6] | PCIE:VC1TXFIFOLIMITP[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[3] | PCIE:VC1TXFIFOLIMITP[4] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOLIMITP[2] | PCIE:VC1TXFIFOLIMITP[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[12] | PCIE:VC1TXFIFOLIMITP[0] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[11] | PCIE:VC1TXFIFOBASEC[10] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[8] | PCIE:VC1TXFIFOBASEC[9] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[7] | PCIE:VC1TXFIFOBASEC[6] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[4] | PCIE:VC1TXFIFOBASEC[5] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[3] | PCIE:VC1TXFIFOBASEC[2] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEC[0] | PCIE:VC1TXFIFOBASEC[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[12] | PCIE:VC1TXFIFOBASENP[11] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[9] | PCIE:VC1TXFIFOBASENP[10] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[8] | PCIE:VC1TXFIFOBASENP[7] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[5] | PCIE:VC1TXFIFOBASENP[6] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[4] | PCIE:VC1TXFIFOBASENP[3] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[1] | PCIE:VC1TXFIFOBASENP[2] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASENP[0] | PCIE:VC1TXFIFOBASEP[12] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[10] | PCIE:VC1TXFIFOBASEP[11] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[9] | PCIE:VC1TXFIFOBASEP[8] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[6] | PCIE:VC1TXFIFOBASEP[7] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[5] | PCIE:VC1TXFIFOBASEP[4] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[2] | PCIE:VC1TXFIFOBASEP[3] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TXFIFOBASEP[1] | PCIE:VC1TXFIFOBASEP[0] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[11] | PCIE:VC0RXFIFOLIMITC[12] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[10] | PCIE:VC0RXFIFOLIMITC[9] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[7] | PCIE:VC0RXFIFOLIMITC[8] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[6] | PCIE:VC0RXFIFOLIMITC[5] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[3] | PCIE:VC0RXFIFOLIMITC[4] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITC[2] | PCIE:VC0RXFIFOLIMITC[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC0RXFIFOLIMITNP[12] | PCIE:VC0RXFIFOLIMITC[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[4] | PCIE:VC1RXFIFOLIMITNP[3] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[1] | PCIE:VC1RXFIFOLIMITNP[2] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[0] | PCIE:VC1RXFIFOLIMITP[12] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[10] | PCIE:VC1RXFIFOLIMITP[11] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[9] | PCIE:VC1RXFIFOLIMITP[8] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[6] | PCIE:VC1RXFIFOLIMITP[7] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[5] | PCIE:VC1RXFIFOLIMITP[4] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[2] | PCIE:VC1RXFIFOLIMITP[3] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITP[1] | PCIE:VC1RXFIFOLIMITP[0] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[11] | PCIE:VC1RXFIFOBASEC[12] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[10] | PCIE:VC1RXFIFOBASEC[9] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[7] | PCIE:VC1RXFIFOBASEC[8] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[6] | PCIE:VC1RXFIFOBASEC[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[3] | PCIE:VC1RXFIFOBASEC[4] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEC[2] | PCIE:VC1RXFIFOBASEC[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[12] | PCIE:VC1RXFIFOBASEC[0] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[11] | PCIE:VC1RXFIFOBASENP[10] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[8] | PCIE:VC1RXFIFOBASENP[9] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[7] | PCIE:VC1RXFIFOBASENP[6] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[4] | PCIE:VC1RXFIFOBASENP[5] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[3] | PCIE:VC1RXFIFOBASENP[2] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASENP[0] | PCIE:VC1RXFIFOBASENP[1] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[12] | PCIE:VC1RXFIFOBASEP[11] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[9] | PCIE:VC1RXFIFOBASEP[10] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[8] | PCIE:VC1RXFIFOBASEP[7] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[5] | PCIE:VC1RXFIFOBASEP[6] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[4] | PCIE:VC1RXFIFOBASEP[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[1] | PCIE:VC1RXFIFOBASEP[2] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOBASEP[0] | PCIE:VC1TOTALCREDITSCD[10] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCD[8] | PCIE:VC1TOTALCREDITSCD[9] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCD[7] | PCIE:VC1TOTALCREDITSCD[6] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCD[4] | PCIE:VC1TOTALCREDITSCD[5] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCD[3] | PCIE:VC1TOTALCREDITSCD[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCD[0] | PCIE:VC1TOTALCREDITSCD[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPD[10] | PCIE:VC1TOTALCREDITSPD[9] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPD[7] | PCIE:VC1TOTALCREDITSPD[8] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPD[6] | PCIE:VC1TOTALCREDITSPD[5] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPD[3] | PCIE:VC1TOTALCREDITSPD[4] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPD[2] | PCIE:VC1TOTALCREDITSPD[1] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCH[6] | PCIE:VC1TOTALCREDITSPD[0] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCH[5] | PCIE:VC1TOTALCREDITSCH[4] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCH[2] | PCIE:VC1TOTALCREDITSCH[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSCH[1] | PCIE:VC1TOTALCREDITSCH[0] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSNPH[5] | PCIE:VC1TOTALCREDITSNPH[6] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSNPH[4] | PCIE:VC1TOTALCREDITSNPH[3] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSNPH[1] | PCIE:VC1TOTALCREDITSNPH[2] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSNPH[0] | PCIE:VC1TOTALCREDITSPH[6] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1TOTALCREDITSPH[4] | PCIE:VC1TOTALCREDITSPH[5] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXREADADDRPIPE | PCIE:TXWRITEPIPE |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RXREADADDRPIPE | PCIE:RXREADDATAPIPE |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DUALROLECFGCNTRLROOTEPN | PCIE:DUALCOREENABLE |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L1EXITLATENCYCOMCLK[2] | PCIE:DUALCORESLAVE |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L1EXITLATENCYCOMCLK[1] | PCIE:L1EXITLATENCYCOMCLK[0] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L1EXITLATENCY[1] | PCIE:L1EXITLATENCY[2] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L1EXITLATENCY[0] | PCIE:L0SEXITLATENCYCOMCLK[2] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L0SEXITLATENCYCOMCLK[0] | PCIE:L0SEXITLATENCYCOMCLK[1] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:L0SEXITLATENCY[2] | PCIE:L0SEXITLATENCY[1] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RAMSHARETXRX | PCIE:L0SEXITLATENCY[0] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TLRAMWIDTH | PCIE:TLRAMWRITELATENCY[2] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TLRAMWRITELATENCY[0] | PCIE:TLRAMWRITELATENCY[1] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TLRAMREADLATENCY[2] | PCIE:TLRAMREADLATENCY[1] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INFINITECOMPLETIONS | PCIE:TLRAMREADLATENCY[0] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XLINKSUPPORTED | PCIE:RETRYREADDATAPIPE |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYWRITEPIPE | PCIE:RETRYREADADDRPIPE |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[11] | PCIE:RETRYRAMSIZE[10] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[8] | PCIE:RETRYRAMSIZE[9] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[7] | PCIE:RETRYRAMSIZE[6] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[4] | PCIE:RETRYRAMSIZE[5] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[3] | PCIE:RETRYRAMSIZE[2] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMSIZE[0] | PCIE:RETRYRAMSIZE[1] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMWIDTH | PCIE:RETRYRAMWRITELATENCY[2] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMWRITELATENCY[0] | PCIE:RETRYRAMWRITELATENCY[1] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:RETRYRAMREADLATENCY[2] | PCIE:RETRYRAMREADLATENCY[1] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTSCOMCLK[7] | PCIE:RETRYRAMREADLATENCY[0] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTSCOMCLK[6] | PCIE:TXTSNFTSCOMCLK[5] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTSCOMCLK[3] | PCIE:TXTSNFTSCOMCLK[4] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTSCOMCLK[2] | PCIE:TXTSNFTSCOMCLK[1] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTS[7] | PCIE:TXTSNFTSCOMCLK[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTS[6] | PCIE:TXTSNFTS[5] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTS[3] | PCIE:TXTSNFTS[4] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXTSNFTS[2] | PCIE:TXTSNFTS[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:ACTIVELANESIN[7] | PCIE:TXTSNFTS[0] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:ACTIVELANESIN[6] | PCIE:ACTIVELANESIN[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:ACTIVELANESIN[3] | PCIE:ACTIVELANESIN[4] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:ACTIVELANESIN[2] | PCIE:ACTIVELANESIN[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[12] | PCIE:ACTIVELANESIN[0] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[11] | PCIE:VC1RXFIFOLIMITC[10] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[8] | PCIE:VC1RXFIFOLIMITC[9] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[7] | PCIE:VC1RXFIFOLIMITC[6] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[4] | PCIE:VC1RXFIFOLIMITC[5] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[3] | PCIE:VC1RXFIFOLIMITC[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITC[0] | PCIE:VC1RXFIFOLIMITC[1] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[12] | PCIE:VC1RXFIFOLIMITNP[11] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[9] | PCIE:VC1RXFIFOLIMITNP[10] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[8] | PCIE:VC1RXFIFOLIMITNP[7] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VC1RXFIFOLIMITNP[5] | PCIE:VC1RXFIFOLIMITNP[6] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPDEVICEPORTTYPE[3] | PCIE:XPDEVICEPORTTYPE[2] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPDEVICEPORTTYPE[0] | PCIE:XPDEVICEPORTTYPE[1] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CONFIGROUTING[2] | PCIE:CONFIGROUTING[1] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5MASKWIDTH[5] | PCIE:CONFIGROUTING[0] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5MASKWIDTH[4] | PCIE:BAR5MASKWIDTH[3] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5MASKWIDTH[1] | PCIE:BAR5MASKWIDTH[2] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5MASKWIDTH[0] | PCIE:BAR4MASKWIDTH[5] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4MASKWIDTH[3] | PCIE:BAR4MASKWIDTH[4] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4MASKWIDTH[2] | PCIE:BAR4MASKWIDTH[1] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3MASKWIDTH[5] | PCIE:BAR4MASKWIDTH[0] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3MASKWIDTH[4] | PCIE:BAR3MASKWIDTH[3] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3MASKWIDTH[1] | PCIE:BAR3MASKWIDTH[2] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3MASKWIDTH[0] | PCIE:BAR2MASKWIDTH[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2MASKWIDTH[3] | PCIE:BAR2MASKWIDTH[4] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2MASKWIDTH[2] | PCIE:BAR2MASKWIDTH[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1MASKWIDTH[5] | PCIE:BAR2MASKWIDTH[0] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1MASKWIDTH[4] | PCIE:BAR1MASKWIDTH[3] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1MASKWIDTH[1] | PCIE:BAR1MASKWIDTH[2] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1MASKWIDTH[0] | PCIE:BAR0MASKWIDTH[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0MASKWIDTH[3] | PCIE:BAR0MASKWIDTH[4] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0MASKWIDTH[2] | PCIE:BAR0MASKWIDTH[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5IOMEMN | PCIE:BAR0MASKWIDTH[0] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4IOMEMN | PCIE:BAR3IOMEMN |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1IOMEMN | PCIE:BAR2IOMEMN |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0IOMEMN | PCIE:BAR5PREFETCHABLE |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3PREFETCHABLE | PCIE:BAR4PREFETCHABLE |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2PREFETCHABLE | PCIE:BAR1PREFETCHABLE |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5ADDRWIDTH | PCIE:BAR0PREFETCHABLE |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4ADDRWIDTH | PCIE:BAR3ADDRWIDTH |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1ADDRWIDTH | PCIE:BAR2ADDRWIDTH |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0ADDRWIDTH | PCIE:BAR5EXIST |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3EXIST | PCIE:BAR4EXIST |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2EXIST | PCIE:BAR1EXIST |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[11] | PCIE:BAR0EXIST |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[10] | PCIE:EXTCFGXPCAPPTR[9] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[7] | PCIE:EXTCFGXPCAPPTR[8] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[6] | PCIE:EXTCFGXPCAPPTR[5] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[3] | PCIE:EXTCFGXPCAPPTR[4] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGXPCAPPTR[2] | PCIE:EXTCFGXPCAPPTR[1] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGCAPPTR[7] | PCIE:EXTCFGXPCAPPTR[0] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGCAPPTR[6] | PCIE:EXTCFGCAPPTR[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGCAPPTR[3] | PCIE:EXTCFGCAPPTR[4] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:EXTCFGCAPPTR[2] | PCIE:EXTCFGCAPPTR[1] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTIMPLEMENTED | PCIE:EXTCFGCAPPTR[0] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:UPSTREAMFACING | PCIE:ISSWITCH |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SELECTDLLIF | PCIE:SELECTASMODE |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIEREVISION | PCIE:LLKBYPASS |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:TXREADDATAPIPE | PCIE:RXWRITEPIPE |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[16] | PCIE:CARDBUSCISPOINTER[15] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[13] | PCIE:CARDBUSCISPOINTER[14] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[12] | PCIE:CARDBUSCISPOINTER[11] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[9] | PCIE:CARDBUSCISPOINTER[10] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[8] | PCIE:CARDBUSCISPOINTER[7] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[5] | PCIE:CARDBUSCISPOINTER[6] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[4] | PCIE:CARDBUSCISPOINTER[3] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[1] | PCIE:CARDBUSCISPOINTER[2] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[0] | PCIE:CLASSCODE[23] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[21] | PCIE:CLASSCODE[22] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[20] | PCIE:CLASSCODE[19] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[17] | PCIE:CLASSCODE[18] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[16] | PCIE:CLASSCODE[15] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[13] | PCIE:CLASSCODE[14] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[12] | PCIE:CLASSCODE[11] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[9] | PCIE:CLASSCODE[10] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[8] | PCIE:CLASSCODE[7] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[5] | PCIE:CLASSCODE[6] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[4] | PCIE:CLASSCODE[3] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[1] | PCIE:CLASSCODE[2] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CLASSCODE[0] | PCIE:REVISIONID[7] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:REVISIONID[5] | PCIE:REVISIONID[6] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:REVISIONID[4] | PCIE:REVISIONID[3] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:REVISIONID[1] | PCIE:REVISIONID[2] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:REVISIONID[0] | PCIE:DEVICEID[15] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[13] | PCIE:DEVICEID[14] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[12] | PCIE:DEVICEID[11] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[9] | PCIE:DEVICEID[10] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[8] | PCIE:DEVICEID[7] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[5] | PCIE:DEVICEID[6] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[4] | PCIE:DEVICEID[3] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[1] | PCIE:DEVICEID[2] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICEID[0] | PCIE:VENDORID[15] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[13] | PCIE:VENDORID[14] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[12] | PCIE:VENDORID[11] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[9] | PCIE:VENDORID[10] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[8] | PCIE:VENDORID[7] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[5] | PCIE:VENDORID[6] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[4] | PCIE:VENDORID[3] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[1] | PCIE:VENDORID[2] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VENDORID[0] | PCIE:LOWPRIORITYVCCOUNT[2] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:LOWPRIORITYVCCOUNT[0] | PCIE:LOWPRIORITYVCCOUNT[1] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPRCBCONTROL | PCIE:XPMAXPAYLOAD[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPMAXPAYLOAD[0] | PCIE:XPMAXPAYLOAD[1] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:HEADERTYPE[7] | PCIE:HEADERTYPE[6] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:HEADERTYPE[4] | PCIE:HEADERTYPE[5] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:HEADERTYPE[3] | PCIE:HEADERTYPE[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:HEADERTYPE[0] | PCIE:HEADERTYPE[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA1[3] | PCIE:PMDATA1[2] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA1[0] | PCIE:PMDATA1[1] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA0[7] | PCIE:PMDATA0[6] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA0[4] | PCIE:PMDATA0[5] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA0[3] | PCIE:PMDATA0[2] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA0[0] | PCIE:PMDATA0[1] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMSTATUSCONTROLDATASCALE[1] | PCIE:PMSTATUSCONTROLDATASCALE[0] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYPMESUPPORT[3] | PCIE:PMCAPABILITYPMESUPPORT[4] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYPMESUPPORT[2] | PCIE:PMCAPABILITYPMESUPPORT[1] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYD2SUPPORT | PCIE:PMCAPABILITYPMESUPPORT[0] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYD1SUPPORT | PCIE:PMCAPABILITYAUXCURRENT[2] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYAUXCURRENT[0] | PCIE:PMCAPABILITYAUXCURRENT[1] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYDSI | PCIE:PMCAPABILITYNEXTPTR[7] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYNEXTPTR[5] | PCIE:PMCAPABILITYNEXTPTR[6] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYNEXTPTR[4] | PCIE:PMCAPABILITYNEXTPTR[3] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYNEXTPTR[1] | PCIE:PMCAPABILITYNEXTPTR[2] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMCAPABILITYNEXTPTR[0] | PCIE:INTERRUPTPIN[7] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INTERRUPTPIN[5] | PCIE:INTERRUPTPIN[6] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INTERRUPTPIN[4] | PCIE:INTERRUPTPIN[3] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INTERRUPTPIN[1] | PCIE:INTERRUPTPIN[2] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:INTERRUPTPIN[0] | PCIE:CAPABILITIESPOINTER[7] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CAPABILITIESPOINTER[5] | PCIE:CAPABILITIESPOINTER[6] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CAPABILITIESPOINTER[4] | PCIE:CAPABILITIESPOINTER[3] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CAPABILITIESPOINTER[1] | PCIE:CAPABILITIESPOINTER[2] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CAPABILITIESPOINTER[0] | PCIE:SUBSYSTEMID[15] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[13] | PCIE:SUBSYSTEMID[14] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[12] | PCIE:SUBSYSTEMID[11] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[9] | PCIE:SUBSYSTEMID[10] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[8] | PCIE:SUBSYSTEMID[7] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[5] | PCIE:SUBSYSTEMID[6] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[4] | PCIE:SUBSYSTEMID[3] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[1] | PCIE:SUBSYSTEMID[2] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMID[0] | PCIE:SUBSYSTEMVENDORID[15] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[13] | PCIE:SUBSYSTEMVENDORID[14] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[12] | PCIE:SUBSYSTEMVENDORID[11] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[9] | PCIE:SUBSYSTEMVENDORID[10] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[8] | PCIE:SUBSYSTEMVENDORID[7] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[5] | PCIE:SUBSYSTEMVENDORID[6] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[4] | PCIE:SUBSYSTEMVENDORID[3] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[1] | PCIE:SUBSYSTEMVENDORID[2] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SUBSYSTEMVENDORID[0] | PCIE:CARDBUSCISPOINTER[31] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[29] | PCIE:CARDBUSCISPOINTER[30] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[28] | PCIE:CARDBUSCISPOINTER[27] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[25] | PCIE:CARDBUSCISPOINTER[26] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[24] | PCIE:CARDBUSCISPOINTER[23] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[21] | PCIE:CARDBUSCISPOINTER[22] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[20] | PCIE:CARDBUSCISPOINTER[19] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CARDBUSCISPOINTER[17] | PCIE:CARDBUSCISPOINTER[18] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYNEXTPTR[6] | PCIE:PCIECAPABILITYNEXTPTR[5] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYNEXTPTR[3] | PCIE:PCIECAPABILITYNEXTPTR[4] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYNEXTPTR[2] | PCIE:PCIECAPABILITYNEXTPTR[1] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYMULTIMSGCAP[2] | PCIE:PCIECAPABILITYNEXTPTR[0] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYMULTIMSGCAP[1] | PCIE:MSICAPABILITYMULTIMSGCAP[0] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYNEXTPTR[6] | PCIE:MSICAPABILITYNEXTPTR[7] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYNEXTPTR[5] | PCIE:MSICAPABILITYNEXTPTR[4] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYNEXTPTR[2] | PCIE:MSICAPABILITYNEXTPTR[3] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSICAPABILITYNEXTPTR[1] | PCIE:MSICAPABILITYNEXTPTR[0] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE8[0] | PCIE:PMDATASCALE8[1] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE7[1] | PCIE:PMDATASCALE7[0] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE6[0] | PCIE:PMDATASCALE6[1] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE5[1] | PCIE:PMDATASCALE5[0] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE4[0] | PCIE:PMDATASCALE4[1] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE3[1] | PCIE:PMDATASCALE3[0] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE2[0] | PCIE:PMDATASCALE2[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE1[1] | PCIE:PMDATASCALE1[0] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATASCALE0[0] | PCIE:PMDATASCALE0[1] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA8[7] | PCIE:PMDATA8[6] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA8[4] | PCIE:PMDATA8[5] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA8[3] | PCIE:PMDATA8[2] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA8[0] | PCIE:PMDATA8[1] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA7[7] | PCIE:PMDATA7[6] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA7[4] | PCIE:PMDATA7[5] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA7[3] | PCIE:PMDATA7[2] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA7[0] | PCIE:PMDATA7[1] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA6[7] | PCIE:PMDATA6[6] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA6[4] | PCIE:PMDATA6[5] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA6[3] | PCIE:PMDATA6[2] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA6[0] | PCIE:PMDATA6[1] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA5[7] | PCIE:PMDATA5[6] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA5[4] | PCIE:PMDATA5[5] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA5[3] | PCIE:PMDATA5[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA5[0] | PCIE:PMDATA5[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA4[7] | PCIE:PMDATA4[6] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA4[4] | PCIE:PMDATA4[5] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA4[3] | PCIE:PMDATA4[2] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA4[0] | PCIE:PMDATA4[1] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA3[7] | PCIE:PMDATA3[6] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA3[4] | PCIE:PMDATA3[5] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA3[3] | PCIE:PMDATA3[2] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA3[0] | PCIE:PMDATA3[1] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA2[7] | PCIE:PMDATA2[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA2[4] | PCIE:PMDATA2[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA2[3] | PCIE:PMDATA2[2] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA2[0] | PCIE:PMDATA2[1] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA1[7] | PCIE:PMDATA1[6] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMDATA1[4] | PCIE:PMDATA1[5] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[6] | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[5] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[3] | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[4] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[2] | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[1] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBCAP[7] | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[0] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBCAP[6] | PCIE:PORTVCCAPABILITYVCARBCAP[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBCAP[3] | PCIE:PORTVCCAPABILITYVCARBCAP[4] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBCAP[2] | PCIE:PORTVCCAPABILITYVCARBCAP[1] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYEXTENDEDVCCOUNT[2] | PCIE:PORTVCCAPABILITYVCARBCAP[0] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYEXTENDEDVCCOUNT[1] | PCIE:PORTVCCAPABILITYEXTENDEDVCCOUNT[0] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[10] | PCIE:VCCAPABILITYNEXTPTR[11] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[9] | PCIE:VCCAPABILITYNEXTPTR[8] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[6] | PCIE:VCCAPABILITYNEXTPTR[7] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[5] | PCIE:VCCAPABILITYNEXTPTR[4] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[2] | PCIE:VCCAPABILITYNEXTPTR[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCCAPABILITYNEXTPTR[1] | PCIE:VCCAPABILITYNEXTPTR[0] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYECRCGENCAPABLE | PCIE:AERCAPABILITYECRCCHECKCAPABLE |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[11] | PCIE:AERCAPABILITYNEXTPTR[10] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[8] | PCIE:AERCAPABILITYNEXTPTR[9] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[7] | PCIE:AERCAPABILITYNEXTPTR[6] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[4] | PCIE:AERCAPABILITYNEXTPTR[5] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[3] | PCIE:AERCAPABILITYNEXTPTR[2] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERCAPABILITYNEXTPTR[0] | PCIE:AERCAPABILITYNEXTPTR[1] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[12] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[11] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[9] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[10] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[8] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[7] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[5] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[6] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[4] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[1] | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[2] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPHYSICALSLOTNUM[0] | PCIE:SLOTCAPABILITYSLOTPOWERLIMITSCALE[1] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[7] | PCIE:SLOTCAPABILITYSLOTPOWERLIMITSCALE[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[6] | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[5] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[3] | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[4] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[2] | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYHOTPLUGCAPABLE | PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE[0] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYHOTPLUGSURPRISE | PCIE:SLOTCAPABILITYPOWERINDICATORPRESENT |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYMSLSENSORPRESENT | PCIE:SLOTCAPABILITYATTINDICATORPRESENT |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:SLOTCAPABILITYPOWERCONTROLLERPRESENT | PCIE:SLOTCAPABILITYATTBUTTONPRESENT |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:LINKCAPABILITYASPMSUPPORT[1] | PCIE:LINKSTATUSSLOTCLOCKCONFIG |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:LINKCAPABILITYASPMSUPPORT[0] | PCIE:LINKCAPABILITYMAXLINKWIDTH[5] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:LINKCAPABILITYMAXLINKWIDTH[3] | PCIE:LINKCAPABILITYMAXLINKWIDTH[4] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:LINKCAPABILITYMAXLINKWIDTH[2] | PCIE:LINKCAPABILITYMAXLINKWIDTH[1] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICECAPABILITYENDPOINTL1LATENCY[2] | PCIE:LINKCAPABILITYMAXLINKWIDTH[0] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICECAPABILITYENDPOINTL1LATENCY[1] | PCIE:DEVICECAPABILITYENDPOINTL1LATENCY[0] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICECAPABILITYENDPOINTL0SLATENCY[1] | PCIE:DEVICECAPABILITYENDPOINTL0SLATENCY[2] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICECAPABILITYENDPOINTL0SLATENCY[0] | PCIE:PCIECAPABILITYINTMSGNUM[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYINTMSGNUM[2] | PCIE:PCIECAPABILITYINTMSGNUM[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYINTMSGNUM[1] | PCIE:PCIECAPABILITYINTMSGNUM[0] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PCIECAPABILITYNEXTPTR[7] | PCIE:PCIECAPABILITYSLOTIMPL |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0BASEPOWER[6] | PCIE:PBCAPABILITYDW0BASEPOWER[5] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0BASEPOWER[3] | PCIE:PBCAPABILITYDW0BASEPOWER[4] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0BASEPOWER[2] | PCIE:PBCAPABILITYDW0BASEPOWER[1] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[11] | PCIE:PBCAPABILITYDW0BASEPOWER[0] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[10] | PCIE:PBCAPABILITYNEXTPTR[9] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[7] | PCIE:PBCAPABILITYNEXTPTR[8] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[6] | PCIE:PBCAPABILITYNEXTPTR[5] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[3] | PCIE:PBCAPABILITYNEXTPTR[4] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYNEXTPTR[2] | PCIE:PBCAPABILITYNEXTPTR[1] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[63] | PCIE:PBCAPABILITYNEXTPTR[0] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[62] | PCIE:DEVICESERIALNUMBER[61] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[59] | PCIE:DEVICESERIALNUMBER[60] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[58] | PCIE:DEVICESERIALNUMBER[57] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[55] | PCIE:DEVICESERIALNUMBER[56] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[54] | PCIE:DEVICESERIALNUMBER[53] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[51] | PCIE:DEVICESERIALNUMBER[52] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[50] | PCIE:DEVICESERIALNUMBER[49] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[47] | PCIE:DEVICESERIALNUMBER[48] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[46] | PCIE:DEVICESERIALNUMBER[45] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[43] | PCIE:DEVICESERIALNUMBER[44] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[42] | PCIE:DEVICESERIALNUMBER[41] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[39] | PCIE:DEVICESERIALNUMBER[40] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[38] | PCIE:DEVICESERIALNUMBER[37] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[35] | PCIE:DEVICESERIALNUMBER[36] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[34] | PCIE:DEVICESERIALNUMBER[33] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[31] | PCIE:DEVICESERIALNUMBER[32] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[30] | PCIE:DEVICESERIALNUMBER[29] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[27] | PCIE:DEVICESERIALNUMBER[28] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[26] | PCIE:DEVICESERIALNUMBER[25] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[23] | PCIE:DEVICESERIALNUMBER[24] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[22] | PCIE:DEVICESERIALNUMBER[21] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[19] | PCIE:DEVICESERIALNUMBER[20] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[18] | PCIE:DEVICESERIALNUMBER[17] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[15] | PCIE:DEVICESERIALNUMBER[16] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[14] | PCIE:DEVICESERIALNUMBER[13] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[11] | PCIE:DEVICESERIALNUMBER[12] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[10] | PCIE:DEVICESERIALNUMBER[9] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[7] | PCIE:DEVICESERIALNUMBER[8] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[6] | PCIE:DEVICESERIALNUMBER[5] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[3] | PCIE:DEVICESERIALNUMBER[4] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DEVICESERIALNUMBER[2] | PCIE:DEVICESERIALNUMBER[1] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[11] | PCIE:DEVICESERIALNUMBER[0] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[10] | PCIE:DSNCAPABILITYNEXTPTR[9] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[7] | PCIE:DSNCAPABILITYNEXTPTR[8] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[6] | PCIE:DSNCAPABILITYNEXTPTR[5] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[3] | PCIE:DSNCAPABILITYNEXTPTR[4] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNCAPABILITYNEXTPTR[2] | PCIE:DSNCAPABILITYNEXTPTR[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET[7] | PCIE:DSNCAPABILITYNEXTPTR[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[4] | PCIE:DSNBASEPTR[3] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[1] | PCIE:DSNBASEPTR[2] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[0] | PCIE:AERBASEPTR[11] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[9] | PCIE:AERBASEPTR[10] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[8] | PCIE:AERBASEPTR[7] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[5] | PCIE:AERBASEPTR[6] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[4] | PCIE:AERBASEPTR[3] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[1] | PCIE:AERBASEPTR[2] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AERBASEPTR[0] | PCIE:RESETMODE |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3POWERRAIL[2] | PCIE:PBCAPABILITYSYSTEMALLOCATED |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3POWERRAIL[1] | PCIE:PBCAPABILITYDW3POWERRAIL[0] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3TYPE[1] | PCIE:PBCAPABILITYDW3TYPE[2] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3TYPE[0] | PCIE:PBCAPABILITYDW3PMSTATE[1] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3PMSUBSTATE[2] | PCIE:PBCAPABILITYDW3PMSTATE[0] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3PMSUBSTATE[1] | PCIE:PBCAPABILITYDW3PMSUBSTATE[0] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3DATASCALE[0] | PCIE:PBCAPABILITYDW3DATASCALE[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3BASEPOWER[7] | PCIE:PBCAPABILITYDW3BASEPOWER[6] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3BASEPOWER[4] | PCIE:PBCAPABILITYDW3BASEPOWER[5] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3BASEPOWER[3] | PCIE:PBCAPABILITYDW3BASEPOWER[2] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW3BASEPOWER[0] | PCIE:PBCAPABILITYDW3BASEPOWER[1] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2POWERRAIL[2] | PCIE:PBCAPABILITYDW2POWERRAIL[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2TYPE[2] | PCIE:PBCAPABILITYDW2POWERRAIL[0] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2TYPE[1] | PCIE:PBCAPABILITYDW2TYPE[0] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2PMSTATE[0] | PCIE:PBCAPABILITYDW2PMSTATE[1] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2PMSUBSTATE[2] | PCIE:PBCAPABILITYDW2PMSUBSTATE[1] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2DATASCALE[1] | PCIE:PBCAPABILITYDW2PMSUBSTATE[0] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2DATASCALE[0] | PCIE:PBCAPABILITYDW2BASEPOWER[7] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2BASEPOWER[5] | PCIE:PBCAPABILITYDW2BASEPOWER[6] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2BASEPOWER[4] | PCIE:PBCAPABILITYDW2BASEPOWER[3] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2BASEPOWER[1] | PCIE:PBCAPABILITYDW2BASEPOWER[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW2BASEPOWER[0] | PCIE:PBCAPABILITYDW1POWERRAIL[2] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1POWERRAIL[0] | PCIE:PBCAPABILITYDW1POWERRAIL[1] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1TYPE[2] | PCIE:PBCAPABILITYDW1TYPE[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1PMSTATE[1] | PCIE:PBCAPABILITYDW1TYPE[0] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1PMSTATE[0] | PCIE:PBCAPABILITYDW1PMSUBSTATE[2] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1PMSUBSTATE[0] | PCIE:PBCAPABILITYDW1PMSUBSTATE[1] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1DATASCALE[1] | PCIE:PBCAPABILITYDW1DATASCALE[0] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1BASEPOWER[6] | PCIE:PBCAPABILITYDW1BASEPOWER[7] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1BASEPOWER[5] | PCIE:PBCAPABILITYDW1BASEPOWER[4] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1BASEPOWER[2] | PCIE:PBCAPABILITYDW1BASEPOWER[3] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW1BASEPOWER[1] | PCIE:PBCAPABILITYDW1BASEPOWER[0] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0POWERRAIL[1] | PCIE:PBCAPABILITYDW0POWERRAIL[2] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0POWERRAIL[0] | PCIE:PBCAPABILITYDW0TYPE[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0TYPE[0] | PCIE:PBCAPABILITYDW0TYPE[1] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0PMSTATE[1] | PCIE:PBCAPABILITYDW0PMSTATE[0] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0PMSUBSTATE[1] | PCIE:PBCAPABILITYDW0PMSUBSTATE[2] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0PMSUBSTATE[0] | PCIE:PBCAPABILITYDW0DATASCALE[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBCAPABILITYDW0BASEPOWER[7] | PCIE:PBCAPABILITYDW0DATASCALE[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPBASEPTR[7] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPBASEPTR[5] | PCIE:XPBASEPTR[6] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPBASEPTR[4] | PCIE:XPBASEPTR[3] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPBASEPTR[1] | PCIE:XPBASEPTR[2] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:XPBASEPTR[0] | PCIE:VCBASEPTR[11] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[9] | PCIE:VCBASEPTR[10] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[8] | PCIE:VCBASEPTR[7] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[5] | PCIE:VCBASEPTR[6] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[4] | PCIE:VCBASEPTR[3] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[1] | PCIE:VCBASEPTR[2] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:VCBASEPTR[0] | PCIE:PMBASEPTR[11] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[9] | PCIE:PMBASEPTR[10] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[8] | PCIE:PMBASEPTR[7] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[5] | PCIE:PMBASEPTR[6] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[4] | PCIE:PMBASEPTR[3] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[1] | PCIE:PMBASEPTR[2] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PMBASEPTR[0] | PCIE:PBBASEPTR[11] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[9] | PCIE:PBBASEPTR[10] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[8] | PCIE:PBBASEPTR[7] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[5] | PCIE:PBBASEPTR[6] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[4] | PCIE:PBBASEPTR[3] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[1] | PCIE:PBBASEPTR[2] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:PBBASEPTR[0] | PCIE:MSIBASEPTR[11] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[9] | PCIE:MSIBASEPTR[10] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[8] | PCIE:MSIBASEPTR[7] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[5] | PCIE:MSIBASEPTR[6] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[4] | PCIE:MSIBASEPTR[3] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[1] | PCIE:MSIBASEPTR[2] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:MSIBASEPTR[0] | PCIE:DSNBASEPTR[11] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[9] | PCIE:DSNBASEPTR[10] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[8] | PCIE:DSNBASEPTR[7] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DSNBASEPTR[5] | PCIE:DSNBASEPTR[6] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| PCIE:ACTIVELANESIN | 29.28.19 | 29.28.18 | 29.29.18 | 29.29.17 | 29.28.17 | 29.28.14 | 29.29.14 | 29.29.13 |
|---|---|---|---|---|---|---|---|---|
| PCIE:CAPABILITIESPOINTER | 32.29.36 | 32.29.35 | 32.28.35 | 32.28.34 | 32.29.34 | 32.29.33 | 32.28.33 | 32.28.30 |
| PCIE:EXTCFGCAPPTR | 30.28.11 | 30.28.10 | 30.29.10 | 30.29.9 | 30.28.9 | 30.28.6 | 30.29.6 | 30.29.5 |
| PCIE:HEADERTYPE | 31.28.4 | 31.29.4 | 31.29.3 | 31.28.3 | 31.28.2 | 31.29.2 | 31.29.1 | 31.28.1 |
| PCIE:INTERRUPTPIN | 32.29.42 | 32.29.41 | 32.28.41 | 32.28.38 | 32.29.38 | 32.29.37 | 32.28.37 | 32.28.36 |
| PCIE:MSICAPABILITYNEXTPTR | 33.29.57 | 33.28.57 | 33.28.54 | 33.29.54 | 33.29.53 | 33.28.53 | 33.28.52 | 33.29.52 |
| PCIE:PBCAPABILITYDW0BASEPOWER | 36.28.1 | 35.28.62 | 35.29.62 | 35.29.61 | 35.28.61 | 35.28.60 | 35.29.60 | 35.29.59 |
| PCIE:PBCAPABILITYDW1BASEPOWER | 36.29.13 | 36.28.13 | 36.28.12 | 36.29.12 | 36.29.11 | 36.28.11 | 36.28.10 | 36.29.10 |
| PCIE:PBCAPABILITYDW2BASEPOWER | 36.29.28 | 36.29.27 | 36.28.27 | 36.28.26 | 36.29.26 | 36.29.25 | 36.28.25 | 36.28.22 |
| PCIE:PBCAPABILITYDW3BASEPOWER | 36.28.42 | 36.29.42 | 36.29.41 | 36.28.41 | 36.28.38 | 36.29.38 | 36.29.37 | 36.28.37 |
| PCIE:PCIECAPABILITYNEXTPTR | 34.28.1 | 33.28.62 | 33.29.62 | 33.29.61 | 33.28.61 | 33.28.60 | 33.29.60 | 33.29.59 |
| PCIE:PMCAPABILITYNEXTPTR | 32.29.46 | 32.29.45 | 32.28.45 | 32.28.44 | 32.29.44 | 32.29.43 | 32.28.43 | 32.28.42 |
| PCIE:PMDATA0 | 32.28.60 | 32.29.60 | 32.29.59 | 32.28.59 | 32.28.58 | 32.29.58 | 32.29.57 | 32.28.57 |
| PCIE:PMDATA1 | 33.28.2 | 33.29.2 | 33.29.1 | 33.28.1 | 32.28.62 | 32.29.62 | 32.29.61 | 32.28.61 |
| PCIE:PMDATA2 | 33.28.6 | 33.29.6 | 33.29.5 | 33.28.5 | 33.28.4 | 33.29.4 | 33.29.3 | 33.28.3 |
| PCIE:PMDATA3 | 33.28.12 | 33.29.12 | 33.29.11 | 33.28.11 | 33.28.10 | 33.29.10 | 33.29.9 | 33.28.9 |
| PCIE:PMDATA4 | 33.28.18 | 33.29.18 | 33.29.17 | 33.28.17 | 33.28.14 | 33.29.14 | 33.29.13 | 33.28.13 |
| PCIE:PMDATA5 | 33.28.22 | 33.29.22 | 33.29.21 | 33.28.21 | 33.28.20 | 33.29.20 | 33.29.19 | 33.28.19 |
| PCIE:PMDATA6 | 33.28.28 | 33.29.28 | 33.29.27 | 33.28.27 | 33.28.26 | 33.29.26 | 33.29.25 | 33.28.25 |
| PCIE:PMDATA7 | 33.28.34 | 33.29.34 | 33.29.33 | 33.28.33 | 33.28.30 | 33.29.30 | 33.29.29 | 33.28.29 |
| PCIE:PMDATA8 | 33.28.38 | 33.29.38 | 33.29.37 | 33.28.37 | 33.28.36 | 33.29.36 | 33.29.35 | 33.28.35 |
| PCIE:PORTVCCAPABILITYVCARBCAP | 34.28.59 | 34.28.58 | 34.29.58 | 34.29.57 | 34.28.57 | 34.28.54 | 34.29.54 | 34.29.53 |
| PCIE:PORTVCCAPABILITYVCARBTABLEOFFSET | 35.28.1 | 34.28.62 | 34.29.62 | 34.29.61 | 34.28.61 | 34.28.60 | 34.29.60 | 34.29.59 |
| PCIE:REVISIONID | 31.29.36 | 31.29.35 | 31.28.35 | 31.28.34 | 31.29.34 | 31.29.33 | 31.28.33 | 31.28.30 |
| PCIE:SLOTCAPABILITYSLOTPOWERLIMITVALUE | 34.28.25 | 34.28.22 | 34.29.22 | 34.29.21 | 34.28.21 | 34.28.20 | 34.29.20 | 34.29.19 |
| PCIE:TXTSNFTS | 29.28.25 | 29.28.22 | 29.29.22 | 29.29.21 | 29.28.21 | 29.28.20 | 29.29.20 | 29.29.19 |
| PCIE:TXTSNFTSCOMCLK | 29.28.29 | 29.28.28 | 29.29.28 | 29.29.27 | 29.28.27 | 29.28.26 | 29.29.26 | 29.29.25 |
| PCIE:XPBASEPTR | 37.29.42 | 37.29.41 | 37.28.41 | 37.28.38 | 37.29.38 | 37.29.37 | 37.28.37 | 37.28.36 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AERBASEPTR | 36.29.60 | 36.29.59 | 36.28.59 | 36.28.58 | 36.29.58 | 36.29.57 | 36.28.57 | 36.28.54 | 36.29.54 | 36.29.53 | 36.28.53 | 36.28.52 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:AERCAPABILITYNEXTPTR | 34.28.42 | 34.29.42 | 34.29.41 | 34.28.41 | 34.28.38 | 34.29.38 | 34.29.37 | 34.28.37 | 34.28.36 | 34.29.36 | 34.29.35 | 34.28.35 |
| PCIE:DSNBASEPTR | 37.29.4 | 37.29.3 | 37.28.3 | 37.28.2 | 37.29.2 | 37.29.1 | 37.28.1 | 36.28.62 | 36.29.62 | 36.29.61 | 36.28.61 | 36.28.60 |
| PCIE:DSNCAPABILITYNEXTPTR | 35.28.9 | 35.28.6 | 35.29.6 | 35.29.5 | 35.28.5 | 35.28.4 | 35.29.4 | 35.29.3 | 35.28.3 | 35.28.2 | 35.29.2 | 35.29.1 |
| PCIE:EXTCFGXPCAPPTR | 30.28.19 | 30.28.18 | 30.29.18 | 30.29.17 | 30.28.17 | 30.28.14 | 30.29.14 | 30.29.13 | 30.28.13 | 30.28.12 | 30.29.12 | 30.29.11 |
| PCIE:MSIBASEPTR | 37.29.12 | 37.29.11 | 37.28.11 | 37.28.10 | 37.29.10 | 37.29.9 | 37.28.9 | 37.28.6 | 37.29.6 | 37.29.5 | 37.28.5 | 37.28.4 |
| PCIE:PBBASEPTR | 37.29.20 | 37.29.19 | 37.28.19 | 37.28.18 | 37.29.18 | 37.29.17 | 37.28.17 | 37.28.14 | 37.29.14 | 37.29.13 | 37.28.13 | 37.28.12 |
| PCIE:PBCAPABILITYNEXTPTR | 35.28.59 | 35.28.58 | 35.29.58 | 35.29.57 | 35.28.57 | 35.28.54 | 35.29.54 | 35.29.53 | 35.28.53 | 35.28.52 | 35.29.52 | 35.29.51 |
| PCIE:PMBASEPTR | 37.29.28 | 37.29.27 | 37.28.27 | 37.28.26 | 37.29.26 | 37.29.25 | 37.28.25 | 37.28.22 | 37.29.22 | 37.29.21 | 37.28.21 | 37.28.20 |
| PCIE:RETRYRAMSIZE | 29.28.42 | 29.29.42 | 29.29.41 | 29.28.41 | 29.28.38 | 29.29.38 | 29.29.37 | 29.28.37 | 29.28.36 | 29.29.36 | 29.29.35 | 29.28.35 |
| PCIE:VCBASEPTR | 37.29.36 | 37.29.35 | 37.28.35 | 37.28.34 | 37.29.34 | 37.29.33 | 37.28.33 | 37.28.30 | 37.29.30 | 37.29.29 | 37.28.29 | 37.28.28 |
| PCIE:VCCAPABILITYNEXTPTR | 34.29.51 | 34.28.51 | 34.28.50 | 34.29.50 | 34.29.49 | 34.28.49 | 34.28.46 | 34.29.46 | 34.29.45 | 34.28.45 | 34.28.44 | 34.29.44 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AERCAPABILITYECRCCHECKCAPABLE | 34.29.43 |
|---|---|
| PCIE:AERCAPABILITYECRCGENCAPABLE | 34.28.43 |
| PCIE:BAR0ADDRWIDTH | 30.28.22 |
| PCIE:BAR0EXIST | 30.29.19 |
| PCIE:BAR0IOMEMN | 30.28.30 |
| PCIE:BAR0PREFETCHABLE | 30.29.27 |
| PCIE:BAR1ADDRWIDTH | 30.28.25 |
| PCIE:BAR1EXIST | 30.29.20 |
| PCIE:BAR1IOMEMN | 30.28.33 |
| PCIE:BAR1PREFETCHABLE | 30.29.28 |
| PCIE:BAR2ADDRWIDTH | 30.29.25 |
| PCIE:BAR2EXIST | 30.28.20 |
| PCIE:BAR2IOMEMN | 30.29.33 |
| PCIE:BAR2PREFETCHABLE | 30.28.28 |
| PCIE:BAR3ADDRWIDTH | 30.29.26 |
| PCIE:BAR3EXIST | 30.28.21 |
| PCIE:BAR3IOMEMN | 30.29.34 |
| PCIE:BAR3PREFETCHABLE | 30.28.29 |
| PCIE:BAR4ADDRWIDTH | 30.28.26 |
| PCIE:BAR4EXIST | 30.29.21 |
| PCIE:BAR4IOMEMN | 30.28.34 |
| PCIE:BAR4PREFETCHABLE | 30.29.29 |
| PCIE:BAR5ADDRWIDTH | 30.28.27 |
| PCIE:BAR5EXIST | 30.29.22 |
| PCIE:BAR5IOMEMN | 30.28.35 |
| PCIE:BAR5PREFETCHABLE | 30.29.30 |
| PCIE:DUALCOREENABLE | 29.29.60 |
| PCIE:DUALCORESLAVE | 29.29.59 |
| PCIE:DUALROLECFGCNTRLROOTEPN | 29.28.60 |
| PCIE:INFINITECOMPLETIONS | 29.28.45 |
| PCIE:INV.CRMCORECLK | 25.28.1 |
| PCIE:INV.CRMCORECLKDLO | 25.29.2 |
| PCIE:INV.CRMCORECLKRXO | 25.28.3 |
| PCIE:INV.CRMCORECLKTXO | 25.28.2 |
| PCIE:INV.CRMUSERCLK | 25.29.1 |
| PCIE:INV.CRMUSERCLKRXO | 25.29.4 |
| PCIE:INV.CRMUSERCLKTXO | 25.29.3 |
| PCIE:ISSWITCH | 30.29.4 |
| PCIE:LINKSTATUSSLOTCLOCKCONFIG | 34.29.13 |
| PCIE:LLKBYPASS | 30.29.2 |
| PCIE:PBCAPABILITYSYSTEMALLOCATED | 36.29.51 |
| PCIE:PCIECAPABILITYSLOTIMPL | 34.29.1 |
| PCIE:PCIEREVISION | 30.28.2 |
| PCIE:PMCAPABILITYD1SUPPORT | 32.28.50 |
| PCIE:PMCAPABILITYD2SUPPORT | 32.28.51 |
| PCIE:PMCAPABILITYDSI | 32.28.46 |
| PCIE:RAMSHARETXRX | 29.28.51 |
| PCIE:RESETMODE | 36.29.52 |
| PCIE:RETRYRAMWIDTH | 29.28.34 |
| PCIE:RETRYREADADDRPIPE | 29.29.43 |
| PCIE:RETRYREADDATAPIPE | 29.29.44 |
| PCIE:RETRYWRITEPIPE | 29.28.43 |
| PCIE:RXREADADDRPIPE | 29.28.61 |
| PCIE:RXREADDATAPIPE | 29.29.61 |
| PCIE:RXWRITEPIPE | 30.29.1 |
| PCIE:SELECTASMODE | 30.29.3 |
| PCIE:SELECTDLLIF | 30.28.3 |
| PCIE:SLOTCAPABILITYATTBUTTONPRESENT | 34.29.14 |
| PCIE:SLOTCAPABILITYATTINDICATORPRESENT | 34.29.17 |
| PCIE:SLOTCAPABILITYHOTPLUGCAPABLE | 34.28.19 |
| PCIE:SLOTCAPABILITYHOTPLUGSURPRISE | 34.28.18 |
| PCIE:SLOTCAPABILITYMSLSENSORPRESENT | 34.28.17 |
| PCIE:SLOTCAPABILITYPOWERCONTROLLERPRESENT | 34.28.14 |
| PCIE:SLOTCAPABILITYPOWERINDICATORPRESENT | 34.29.18 |
| PCIE:SLOTIMPLEMENTED | 30.28.5 |
| PCIE:TLRAMWIDTH | 29.28.50 |
| PCIE:TXREADADDRPIPE | 29.28.62 |
| PCIE:TXREADDATAPIPE | 30.28.1 |
| PCIE:TXWRITEPIPE | 29.29.62 |
| PCIE:UPSTREAMFACING | 30.28.4 |
| PCIE:XLINKSUPPORTED | 29.28.44 |
| PCIE:XPRCBCONTROL | 31.28.6 |
| non-inverted | [0] |
| PCIE:BAR0MASKWIDTH | 30.29.38 | 30.29.37 | 30.28.37 | 30.28.36 | 30.29.36 | 30.29.35 |
|---|---|---|---|---|---|---|
| PCIE:BAR1MASKWIDTH | 30.28.43 | 30.28.42 | 30.29.42 | 30.29.41 | 30.28.41 | 30.28.38 |
| PCIE:BAR2MASKWIDTH | 30.29.46 | 30.29.45 | 30.28.45 | 30.28.44 | 30.29.44 | 30.29.43 |
| PCIE:BAR3MASKWIDTH | 30.28.51 | 30.28.50 | 30.29.50 | 30.29.49 | 30.28.49 | 30.28.46 |
| PCIE:BAR4MASKWIDTH | 30.29.54 | 30.29.53 | 30.28.53 | 30.28.52 | 30.29.52 | 30.29.51 |
| PCIE:BAR5MASKWIDTH | 30.28.59 | 30.28.58 | 30.29.58 | 30.29.57 | 30.28.57 | 30.28.54 |
| PCIE:LINKCAPABILITYMAXLINKWIDTH | 34.29.12 | 34.29.11 | 34.28.11 | 34.28.10 | 34.29.10 | 34.29.9 |
| non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CARDBUSCISPOINTER | 32.29.10 | 32.29.9 | 32.28.9 | 32.28.6 | 32.29.6 | 32.29.5 | 32.28.5 | 32.28.4 | 32.29.4 | 32.29.3 | 32.28.3 | 32.28.2 | 32.29.2 | 32.29.1 | 32.28.1 | 31.28.62 | 31.29.62 | 31.29.61 | 31.28.61 | 31.28.60 | 31.29.60 | 31.29.59 | 31.28.59 | 31.28.58 | 31.29.58 | 31.29.57 | 31.28.57 | 31.28.54 | 31.29.54 | 31.29.53 | 31.28.53 | 31.28.52 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CLASSCODE | 31.29.52 | 31.29.51 | 31.28.51 | 31.28.50 | 31.29.50 | 31.29.49 | 31.28.49 | 31.28.46 | 31.29.46 | 31.29.45 | 31.28.45 | 31.28.44 | 31.29.44 | 31.29.43 | 31.28.43 | 31.28.42 | 31.29.42 | 31.29.41 | 31.28.41 | 31.28.38 | 31.29.38 | 31.29.37 | 31.28.37 | 31.28.36 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CONFIGROUTING | 30.28.60 | 30.29.60 | 30.29.59 |
|---|---|---|---|
| PCIE:DEVICECAPABILITYENDPOINTL0SLATENCY | 34.29.5 | 34.28.5 | 34.28.4 |
| PCIE:DEVICECAPABILITYENDPOINTL1LATENCY | 34.28.9 | 34.28.6 | 34.29.6 |
| PCIE:L0SEXITLATENCY | 29.28.52 | 29.29.52 | 29.29.51 |
| PCIE:L0SEXITLATENCYCOMCLK | 29.29.54 | 29.29.53 | 29.28.53 |
| PCIE:L1EXITLATENCY | 29.29.57 | 29.28.57 | 29.28.54 |
| PCIE:L1EXITLATENCYCOMCLK | 29.28.59 | 29.28.58 | 29.29.58 |
| PCIE:LOWPRIORITYVCCOUNT | 31.29.10 | 31.29.9 | 31.28.9 |
| PCIE:MSICAPABILITYMULTIMSGCAP | 33.28.59 | 33.28.58 | 33.29.58 |
| PCIE:PBCAPABILITYDW0PMSUBSTATE | 36.29.3 | 36.28.3 | 36.28.2 |
| PCIE:PBCAPABILITYDW0POWERRAIL | 36.29.9 | 36.28.9 | 36.28.6 |
| PCIE:PBCAPABILITYDW0TYPE | 36.29.6 | 36.29.5 | 36.28.5 |
| PCIE:PBCAPABILITYDW1PMSUBSTATE | 36.29.18 | 36.29.17 | 36.28.17 |
| PCIE:PBCAPABILITYDW1POWERRAIL | 36.29.22 | 36.29.21 | 36.28.21 |
| PCIE:PBCAPABILITYDW1TYPE | 36.28.20 | 36.29.20 | 36.29.19 |
| PCIE:PBCAPABILITYDW2PMSUBSTATE | 36.28.30 | 36.29.30 | 36.29.29 |
| PCIE:PBCAPABILITYDW2POWERRAIL | 36.28.36 | 36.29.36 | 36.29.35 |
| PCIE:PBCAPABILITYDW2TYPE | 36.28.35 | 36.28.34 | 36.29.34 |
| PCIE:PBCAPABILITYDW3PMSUBSTATE | 36.28.45 | 36.28.44 | 36.29.44 |
| PCIE:PBCAPABILITYDW3POWERRAIL | 36.28.51 | 36.28.50 | 36.29.50 |
| PCIE:PBCAPABILITYDW3TYPE | 36.29.49 | 36.28.49 | 36.28.46 |
| PCIE:PMCAPABILITYAUXCURRENT | 32.29.50 | 32.29.49 | 32.28.49 |
| PCIE:PORTVCCAPABILITYEXTENDEDVCCOUNT | 34.28.53 | 34.28.52 | 34.29.52 |
| PCIE:RETRYRAMREADLATENCY | 29.28.30 | 29.29.30 | 29.29.29 |
| PCIE:RETRYRAMWRITELATENCY | 29.29.34 | 29.29.33 | 29.28.33 |
| PCIE:TLRAMREADLATENCY | 29.28.46 | 29.29.46 | 29.29.45 |
| PCIE:TLRAMWRITELATENCY | 29.29.50 | 29.29.49 | 29.28.49 |
| PCIE:XPMAXPAYLOAD | 31.29.6 | 31.29.5 | 31.28.5 |
| non-inverted | [2] | [1] | [0] |
| PCIE:DEVICEID | 31.29.30 | 31.29.29 | 31.28.29 | 31.28.28 | 31.29.28 | 31.29.27 | 31.28.27 | 31.28.26 | 31.29.26 | 31.29.25 | 31.28.25 | 31.28.22 | 31.29.22 | 31.29.21 | 31.28.21 | 31.28.20 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:SUBSYSTEMID | 32.29.30 | 32.29.29 | 32.28.29 | 32.28.28 | 32.29.28 | 32.29.27 | 32.28.27 | 32.28.26 | 32.29.26 | 32.29.25 | 32.28.25 | 32.28.22 | 32.29.22 | 32.29.21 | 32.28.21 | 32.28.20 |
| PCIE:SUBSYSTEMVENDORID | 32.29.20 | 32.29.19 | 32.28.19 | 32.28.18 | 32.29.18 | 32.29.17 | 32.28.17 | 32.28.14 | 32.29.14 | 32.29.13 | 32.28.13 | 32.28.12 | 32.29.12 | 32.29.11 | 32.28.11 | 32.28.10 |
| PCIE:VENDORID | 31.29.20 | 31.29.19 | 31.28.19 | 31.28.18 | 31.29.18 | 31.29.17 | 31.28.17 | 31.28.14 | 31.29.14 | 31.29.13 | 31.28.13 | 31.28.12 | 31.29.12 | 31.29.11 | 31.28.11 | 31.28.10 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:DEVICESERIALNUMBER | 35.28.51 | 35.28.50 | 35.29.50 | 35.29.49 | 35.28.49 | 35.28.46 | 35.29.46 | 35.29.45 | 35.28.45 | 35.28.44 | 35.29.44 | 35.29.43 | 35.28.43 | 35.28.42 | 35.29.42 | 35.29.41 | 35.28.41 | 35.28.38 | 35.29.38 | 35.29.37 | 35.28.37 | 35.28.36 | 35.29.36 | 35.29.35 | 35.28.35 | 35.28.34 | 35.29.34 | 35.29.33 | 35.28.33 | 35.28.30 | 35.29.30 | 35.29.29 | 35.28.29 | 35.28.28 | 35.29.28 | 35.29.27 | 35.28.27 | 35.28.26 | 35.29.26 | 35.29.25 | 35.28.25 | 35.28.22 | 35.29.22 | 35.29.21 | 35.28.21 | 35.28.20 | 35.29.20 | 35.29.19 | 35.28.19 | 35.28.18 | 35.29.18 | 35.29.17 | 35.28.17 | 35.28.14 | 35.29.14 | 35.29.13 | 35.28.13 | 35.28.12 | 35.29.12 | 35.29.11 | 35.28.11 | 35.28.10 | 35.29.10 | 35.29.9 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [63] | [62] | [61] | [60] | [59] | [58] | [57] | [56] | [55] | [54] | [53] | [52] | [51] | [50] | [49] | [48] | [47] | [46] | [45] | [44] | [43] | [42] | [41] | [40] | [39] | [38] | [37] | [36] | [35] | [34] | [33] | [32] | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:LINKCAPABILITYASPMSUPPORT | 34.28.13 | 34.28.12 |
|---|---|---|
| PCIE:PBCAPABILITYDW0DATASCALE | 36.29.2 | 36.29.1 |
| PCIE:PBCAPABILITYDW0PMSTATE | 36.28.4 | 36.29.4 |
| PCIE:PBCAPABILITYDW1DATASCALE | 36.28.14 | 36.29.14 |
| PCIE:PBCAPABILITYDW1PMSTATE | 36.28.19 | 36.28.18 |
| PCIE:PBCAPABILITYDW2DATASCALE | 36.28.29 | 36.28.28 |
| PCIE:PBCAPABILITYDW2PMSTATE | 36.29.33 | 36.28.33 |
| PCIE:PBCAPABILITYDW3DATASCALE | 36.29.43 | 36.28.43 |
| PCIE:PBCAPABILITYDW3PMSTATE | 36.29.46 | 36.29.45 |
| PCIE:PMDATASCALE0 | 33.29.41 | 33.28.41 |
| PCIE:PMDATASCALE1 | 33.28.42 | 33.29.42 |
| PCIE:PMDATASCALE2 | 33.29.43 | 33.28.43 |
| PCIE:PMDATASCALE3 | 33.28.44 | 33.29.44 |
| PCIE:PMDATASCALE4 | 33.29.45 | 33.28.45 |
| PCIE:PMDATASCALE5 | 33.28.46 | 33.29.46 |
| PCIE:PMDATASCALE6 | 33.29.49 | 33.28.49 |
| PCIE:PMDATASCALE7 | 33.28.50 | 33.29.50 |
| PCIE:PMDATASCALE8 | 33.29.51 | 33.28.51 |
| PCIE:PMSTATUSCONTROLDATASCALE | 32.28.54 | 32.29.54 |
| PCIE:SLOTCAPABILITYSLOTPOWERLIMITSCALE | 34.29.26 | 34.29.25 |
| non-inverted | [1] | [0] |
| PCIE:PCIECAPABILITYINTMSGNUM | 34.29.4 | 34.29.3 | 34.28.3 | 34.28.2 | 34.29.2 |
|---|---|---|---|---|---|
| PCIE:PMCAPABILITYPMESUPPORT | 32.29.53 | 32.28.53 | 32.28.52 | 32.29.52 | 32.29.51 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| PCIE:SLOTCAPABILITYPHYSICALSLOTNUM | 34.28.34 | 34.29.34 | 34.29.33 | 34.28.33 | 34.28.30 | 34.29.30 | 34.29.29 | 34.28.29 | 34.28.28 | 34.29.28 | 34.29.27 | 34.28.27 | 34.28.26 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:VC0RXFIFOBASEC | 26.29.46 | 26.29.45 | 26.28.45 | 26.28.44 | 26.29.44 | 26.29.43 | 26.28.43 | 26.28.42 | 26.29.42 | 26.29.41 | 26.28.41 | 26.28.38 | 26.29.38 |
| PCIE:VC0RXFIFOBASENP | 26.29.37 | 26.28.37 | 26.28.36 | 26.29.36 | 26.29.35 | 26.28.35 | 26.28.34 | 26.29.34 | 26.29.33 | 26.28.33 | 26.28.30 | 26.29.30 | 26.29.29 |
| PCIE:VC0RXFIFOBASEP | 26.28.29 | 26.28.28 | 26.29.28 | 26.29.27 | 26.28.27 | 26.28.26 | 26.29.26 | 26.29.25 | 26.28.25 | 26.28.22 | 26.29.22 | 26.29.21 | 26.28.21 |
| PCIE:VC0RXFIFOLIMITC | 27.29.9 | 27.28.9 | 27.28.6 | 27.29.6 | 27.29.5 | 27.28.5 | 27.28.4 | 27.29.4 | 27.29.3 | 27.28.3 | 27.28.2 | 27.29.2 | 27.29.1 |
| PCIE:VC0RXFIFOLIMITNP | 27.28.1 | 26.28.62 | 26.29.62 | 26.29.61 | 26.28.61 | 26.28.60 | 26.29.60 | 26.29.59 | 26.28.59 | 26.28.58 | 26.29.58 | 26.29.57 | 26.28.57 |
| PCIE:VC0RXFIFOLIMITP | 26.28.54 | 26.29.54 | 26.29.53 | 26.28.53 | 26.28.52 | 26.29.52 | 26.29.51 | 26.28.51 | 26.28.50 | 26.29.50 | 26.29.49 | 26.28.49 | 26.28.46 |
| PCIE:VC0TXFIFOBASEC | 25.29.29 | 25.28.29 | 25.28.28 | 25.29.28 | 25.29.27 | 25.28.27 | 25.28.26 | 25.29.26 | 25.29.25 | 25.28.25 | 25.28.22 | 25.29.22 | 25.29.21 |
| PCIE:VC0TXFIFOBASENP | 25.28.21 | 25.28.20 | 25.29.20 | 25.29.19 | 25.28.19 | 25.28.18 | 25.29.18 | 25.29.17 | 25.28.17 | 25.28.14 | 25.29.14 | 25.29.13 | 25.28.13 |
| PCIE:VC0TXFIFOBASEP | 25.28.12 | 25.29.12 | 25.29.11 | 25.28.11 | 25.28.10 | 25.29.10 | 25.29.9 | 25.28.9 | 25.28.6 | 25.29.6 | 25.29.5 | 25.28.5 | 25.28.4 |
| PCIE:VC0TXFIFOLIMITC | 25.28.57 | 25.28.54 | 25.29.54 | 25.29.53 | 25.28.53 | 25.28.52 | 25.29.52 | 25.29.51 | 25.28.51 | 25.28.50 | 25.29.50 | 25.29.49 | 25.28.49 |
| PCIE:VC0TXFIFOLIMITNP | 25.28.46 | 25.29.46 | 25.29.45 | 25.28.45 | 25.28.44 | 25.29.44 | 25.29.43 | 25.28.43 | 25.28.42 | 25.29.42 | 25.29.41 | 25.28.41 | 25.28.38 |
| PCIE:VC0TXFIFOLIMITP | 25.29.38 | 25.29.37 | 25.28.37 | 25.28.36 | 25.29.36 | 25.29.35 | 25.28.35 | 25.28.34 | 25.29.34 | 25.29.33 | 25.28.33 | 25.28.30 | 25.29.30 |
| PCIE:VC1RXFIFOBASEC | 28.29.51 | 28.28.51 | 28.28.50 | 28.29.50 | 28.29.49 | 28.28.49 | 28.28.46 | 28.29.46 | 28.29.45 | 28.28.45 | 28.28.44 | 28.29.44 | 28.29.43 |
| PCIE:VC1RXFIFOBASENP | 28.28.43 | 28.28.42 | 28.29.42 | 28.29.41 | 28.28.41 | 28.28.38 | 28.29.38 | 28.29.37 | 28.28.37 | 28.28.36 | 28.29.36 | 28.29.35 | 28.28.35 |
| PCIE:VC1RXFIFOBASEP | 28.28.34 | 28.29.34 | 28.29.33 | 28.28.33 | 28.28.30 | 28.29.30 | 28.29.29 | 28.28.29 | 28.28.28 | 28.29.28 | 28.29.27 | 28.28.27 | 28.28.26 |
| PCIE:VC1RXFIFOLIMITC | 29.28.13 | 29.28.12 | 29.29.12 | 29.29.11 | 29.28.11 | 29.28.10 | 29.29.10 | 29.29.9 | 29.28.9 | 29.28.6 | 29.29.6 | 29.29.5 | 29.28.5 |
| PCIE:VC1RXFIFOLIMITNP | 29.28.4 | 29.29.4 | 29.29.3 | 29.28.3 | 29.28.2 | 29.29.2 | 29.29.1 | 29.28.1 | 28.28.62 | 28.29.62 | 28.29.61 | 28.28.61 | 28.28.60 |
| PCIE:VC1RXFIFOLIMITP | 28.29.60 | 28.29.59 | 28.28.59 | 28.28.58 | 28.29.58 | 28.29.57 | 28.28.57 | 28.28.54 | 28.29.54 | 28.29.53 | 28.28.53 | 28.28.52 | 28.29.52 |
| PCIE:VC1TXFIFOBASEC | 27.28.35 | 27.28.34 | 27.29.34 | 27.29.33 | 27.28.33 | 27.28.30 | 27.29.30 | 27.29.29 | 27.28.29 | 27.28.28 | 27.29.28 | 27.29.27 | 27.28.27 |
| PCIE:VC1TXFIFOBASENP | 27.28.26 | 27.29.26 | 27.29.25 | 27.28.25 | 27.28.22 | 27.29.22 | 27.29.21 | 27.28.21 | 27.28.20 | 27.29.20 | 27.29.19 | 27.28.19 | 27.28.18 |
| PCIE:VC1TXFIFOBASEP | 27.29.18 | 27.29.17 | 27.28.17 | 27.28.14 | 27.29.14 | 27.29.13 | 27.28.13 | 27.28.12 | 27.29.12 | 27.29.11 | 27.28.11 | 27.28.10 | 27.29.10 |
| PCIE:VC1TXFIFOLIMITC | 27.28.60 | 27.29.60 | 27.29.59 | 27.28.59 | 27.28.58 | 27.29.58 | 27.29.57 | 27.28.57 | 27.28.54 | 27.29.54 | 27.29.53 | 27.28.53 | 27.28.52 |
| PCIE:VC1TXFIFOLIMITNP | 27.29.52 | 27.29.51 | 27.28.51 | 27.28.50 | 27.29.50 | 27.29.49 | 27.28.49 | 27.28.46 | 27.29.46 | 27.29.45 | 27.28.45 | 27.28.44 | 27.29.44 |
| PCIE:VC1TXFIFOLIMITP | 27.29.43 | 27.28.43 | 27.28.42 | 27.29.42 | 27.29.41 | 27.28.41 | 27.28.38 | 27.29.38 | 27.29.37 | 27.28.37 | 27.28.36 | 27.29.36 | 27.29.35 |
| non-inverted | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:VC0TOTALCREDITSCD | 26.28.20 | 26.29.20 | 26.29.19 | 26.28.19 | 26.28.18 | 26.29.18 | 26.29.17 | 26.28.17 | 26.28.14 | 26.29.14 | 26.29.13 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:VC0TOTALCREDITSPD | 26.28.13 | 26.28.12 | 26.29.12 | 26.29.11 | 26.28.11 | 26.28.10 | 26.29.10 | 26.29.9 | 26.28.9 | 26.28.6 | 26.29.6 |
| PCIE:VC1TOTALCREDITSCD | 28.29.26 | 28.29.25 | 28.28.25 | 28.28.22 | 28.29.22 | 28.29.21 | 28.28.21 | 28.28.20 | 28.29.20 | 28.29.19 | 28.28.19 |
| PCIE:VC1TOTALCREDITSPD | 28.28.18 | 28.29.18 | 28.29.17 | 28.28.17 | 28.28.14 | 28.29.14 | 28.29.13 | 28.28.13 | 28.28.12 | 28.29.12 | 28.29.11 |
| non-inverted | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:VC0TOTALCREDITSCH | 26.29.5 | 26.28.5 | 26.28.4 | 26.29.4 | 26.29.3 | 26.28.3 | 26.28.2 |
|---|---|---|---|---|---|---|---|
| PCIE:VC0TOTALCREDITSNPH | 26.29.2 | 26.29.1 | 26.28.1 | 25.28.62 | 25.29.62 | 25.29.61 | 25.28.61 |
| PCIE:VC0TOTALCREDITSPH | 25.28.60 | 25.29.60 | 25.29.59 | 25.28.59 | 25.28.58 | 25.29.58 | 25.29.57 |
| PCIE:VC1TOTALCREDITSCH | 28.28.11 | 28.28.10 | 28.29.10 | 28.29.9 | 28.28.9 | 28.28.6 | 28.29.6 |
| PCIE:VC1TOTALCREDITSNPH | 28.29.5 | 28.28.5 | 28.28.4 | 28.29.4 | 28.29.3 | 28.28.3 | 28.28.2 |
| PCIE:VC1TOTALCREDITSPH | 28.29.2 | 28.29.1 | 28.28.1 | 27.28.62 | 27.29.62 | 27.29.61 | 27.28.61 |
| non-inverted | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:XPDEVICEPORTTYPE | 30.28.62 | 30.29.62 | 30.29.61 | 30.28.61 |
|---|---|---|---|---|
| non-inverted | [3] | [2] | [1] | [0] |