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Clock management tile

TODO: describe this madness

Tile CMT

Cells: 100

Switchbox SPEC_INT

virtex7 CMT switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[25].HCLK_CMT[0]CELL[25].HCLK_ROW[0]HCLK[27][25]
CELL[25].HCLK_CMT[1]CELL[25].HCLK_ROW[1]HCLK[26][25]
CELL[25].HCLK_CMT[2]CELL[25].HCLK_ROW[2]HCLK[27][24]
CELL[25].HCLK_CMT[3]CELL[25].HCLK_ROW[3]HCLK[26][24]
CELL[25].HCLK_CMT[4]CELL[25].HCLK_ROW[4]HCLK[27][23]
CELL[25].HCLK_CMT[5]CELL[25].HCLK_ROW[5]HCLK[26][23]
CELL[25].HCLK_CMT[6]CELL[25].HCLK_ROW[6]HCLK[27][22]
CELL[25].HCLK_CMT[7]CELL[25].HCLK_ROW[7]HCLK[26][22]
CELL[25].HCLK_CMT[8]CELL[25].HCLK_ROW[8]HCLK[27][21]
CELL[25].HCLK_CMT[9]CELL[25].HCLK_ROW[9]HCLK[26][21]
CELL[25].HCLK_CMT[10]CELL[25].HCLK_ROW[10]HCLK[28][26]
CELL[25].HCLK_CMT[11]CELL[25].HCLK_ROW[11]HCLK[29][26]
CELL[25].RCLK_CMT[0]CELL[25].RCLK_ROW[0]HCLK[28][14]
CELL[25].RCLK_CMT[1]CELL[25].RCLK_ROW[1]HCLK[29][14]
CELL[25].RCLK_CMT[2]CELL[25].RCLK_ROW[2]HCLK[28][15]
CELL[25].RCLK_CMT[3]CELL[25].RCLK_ROW[3]HCLK[29][15]
CELL[25].CCIO_CMT[0]IO[26].OUT_CLKPADMAIN[24][27][63]
CELL[25].CCIO_CMT[1]IO[28].OUT_CLKPADMAIN[24][26][63]
CELL[25].CCIO_CMT[2]IO[22].OUT_CLKPADMAIN[24][27][62]
CELL[25].CCIO_CMT[3]IO[24].OUT_CLKPADMAIN[24][26][62]
CELL[25].CKINT_CMT[0]CELL[24].IMUX_CLK[0]HCLK[26][14]
CELL[25].CKINT_CMT[1]CELL[24].IMUX_CLK[1]HCLK[27][14]
CELL[25].CKINT_CMT[2]CELL[25].IMUX_CLK[0]HCLK[26][15]
CELL[25].CKINT_CMT[3]CELL[25].IMUX_CLK[1]HCLK[27][15]
CELL[25].HROW_I_CMT[4]CELL[25].HROW_I[4]HCLK[28][21]
CELL[25].HROW_I_CMT[5]CELL[25].HROW_I[5]HCLK[29][21]
CELL[25].HROW_I_CMT[6]CELL[25].HROW_I[6]HCLK[28][22]
CELL[25].HROW_I_CMT[7]CELL[25].HROW_I[7]HCLK[29][22]
CELL[25].HROW_I_CMT[8]CELL[25].HROW_I[8]HCLK[28][23]
CELL[25].HROW_I_CMT[9]CELL[25].HROW_I[9]HCLK[29][23]
CELL[25].HROW_I_CMT[10]CELL[25].HROW_I[10]HCLK[28][24]
CELL[25].HROW_I_CMT[11]CELL[25].HROW_I[11]HCLK[29][24]
CELL[25].HROW_I_CMT[12]CELL[25].HROW_I[12]HCLK[28][25]
CELL[25].HROW_I_CMT[13]CELL[25].HROW_I[13]HCLK[29][25]
CELL[25].PERF_IN_PLL[0]CELL[25].OMUX_PLL_PERF[0]MAIN[24][29][38]
CELL[25].PERF_IN_PLL[1]CELL[25].OMUX_PLL_PERF[1]MAIN[24][28][38]
CELL[25].PERF_IN_PLL[2]CELL[25].OMUX_PLL_PERF[2]MAIN[24][29][37]
CELL[25].PERF_IN_PLL[3]CELL[25].OMUX_PLL_PERF[3]MAIN[24][28][37]
CELL[25].PERF_IN_PHASER[0]CELL[25].OUT_PHASER_IN_RCLK[0]MAIN[24][29][36]
CELL[25].PERF_IN_PHASER[1]CELL[25].OUT_PHASER_IN_RCLK[1]MAIN[24][28][36]
CELL[25].PERF_IN_PHASER[2]CELL[25].OUT_PHASER_IN_RCLK[2]MAIN[24][29][35]
CELL[25].PERF_IN_PHASER[3]CELL[25].OUT_PHASER_IN_RCLK[3]MAIN[24][28][35]
CELL[25].CMT_SYNC_BBCELL[25].CMT_SYNC_BB_SMAIN[16][28][39]
CELL[25].CMT_SYNC_BBCELL[25].CMT_SYNC_BB_NMAIN[36][28][38]
CELL[25].CMT_SYNC_BBCELL[25].OUT_PHY_PHYCTLEMPTYMAIN[36][28][40]
CELL[25].CMT_SYNC_BB_SCELL[25].CMT_SYNC_BBMAIN[16][28][38]
CELL[25].CMT_SYNC_BB_NCELL[25].CMT_SYNC_BBMAIN[36][28][39]
CELL[25].OUT_PLL_FREQ_BB_S[0]CELL[25].OUT_PLL_S[0]MAIN[15][29][51]
CELL[25].OUT_PLL_FREQ_BB_S[1]CELL[25].OUT_PLL_S[2]MAIN[15][28][51]
CELL[25].OUT_PLL_FREQ_BB_S[2]CELL[25].OUT_PLL_S[4]MAIN[15][29][50]
CELL[25].OUT_PLL_FREQ_BB_S[3]CELL[25].OUT_PLL_S[6]MAIN[15][28][50]
CELL[25].OUT_PLL_FREQ_BB_N[0]CELL[25].OUT_PLL_N[0]MAIN[37][28][12]
CELL[25].OUT_PLL_FREQ_BB_N[1]CELL[25].OUT_PLL_N[1]MAIN[37][29][12]
CELL[25].OUT_PLL_FREQ_BB_N[2]CELL[25].OUT_PLL_N[2]MAIN[37][28][13]
CELL[25].OUT_PLL_FREQ_BB_N[3]CELL[25].OUT_PLL_N[3]MAIN[37][29][13]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[0]
BitsDestination
MAIN[24][26][57]MAIN[24][27][57]MAIN[24][26][58]MAIN[24][27][58]MAIN[24][26][59]MAIN[24][27][59]MAIN[24][26][53]MAIN[24][27][55]MAIN[24][26][54]MAIN[24][27][53]MAIN[24][27][56]MAIN[24][26][56]MAIN[24][26][55]MAIN[24][27][54]CELL[25].HROW_O[0]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[1]
BitsDestination
MAIN[24][28][57]MAIN[24][29][57]MAIN[24][28][58]MAIN[24][29][58]MAIN[24][28][59]MAIN[24][29][59]MAIN[24][28][53]MAIN[24][29][55]MAIN[24][28][54]MAIN[24][29][53]MAIN[24][29][56]MAIN[24][28][56]MAIN[24][28][55]MAIN[24][29][54]CELL[25].HROW_O[1]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[2]
BitsDestination
MAIN[24][26][50]MAIN[24][27][50]MAIN[24][26][51]MAIN[24][27][51]MAIN[24][26][52]MAIN[24][27][52]MAIN[24][26][46]MAIN[24][27][48]MAIN[24][26][47]MAIN[24][27][46]MAIN[24][27][49]MAIN[24][26][49]MAIN[24][26][48]MAIN[24][27][47]CELL[25].HROW_O[2]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[3]
BitsDestination
MAIN[24][28][50]MAIN[24][29][50]MAIN[24][28][51]MAIN[24][29][51]MAIN[24][28][52]MAIN[24][29][52]MAIN[24][28][46]MAIN[24][29][48]MAIN[24][28][47]MAIN[24][29][46]MAIN[24][29][49]MAIN[24][28][49]MAIN[24][28][48]MAIN[24][29][47]CELL[25].HROW_O[3]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[4]
BitsDestination
MAIN[24][26][43]MAIN[24][27][43]MAIN[24][26][44]MAIN[24][27][44]MAIN[24][26][45]MAIN[24][27][45]MAIN[24][26][39]MAIN[24][27][41]MAIN[24][26][40]MAIN[24][27][39]MAIN[24][27][42]MAIN[24][26][42]MAIN[24][26][41]MAIN[24][27][40]CELL[25].HROW_O[4]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[5]
BitsDestination
MAIN[24][28][43]MAIN[24][29][43]MAIN[24][28][44]MAIN[24][29][44]MAIN[24][28][45]MAIN[24][29][45]MAIN[24][28][39]MAIN[24][29][41]MAIN[24][28][40]MAIN[24][29][39]MAIN[24][29][42]MAIN[24][28][42]MAIN[24][28][41]MAIN[24][29][40]CELL[25].HROW_O[5]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[6]
BitsDestination
MAIN[24][26][36]MAIN[24][27][36]MAIN[24][26][37]MAIN[24][27][37]MAIN[24][26][38]MAIN[24][27][38]MAIN[24][26][32]MAIN[24][27][34]MAIN[24][26][33]MAIN[24][27][32]MAIN[24][27][35]MAIN[24][26][35]MAIN[24][26][34]MAIN[24][27][33]CELL[25].HROW_O[6]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[7]
BitsDestination
MAIN[25][27][6]MAIN[25][26][6]MAIN[25][27][5]MAIN[25][26][5]MAIN[25][27][4]MAIN[25][26][4]MAIN[25][27][10]MAIN[25][26][8]MAIN[25][27][9]MAIN[25][26][10]MAIN[25][26][7]MAIN[25][27][7]MAIN[25][27][8]MAIN[25][26][9]CELL[25].HROW_O[7]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[8]
BitsDestination
MAIN[25][29][6]MAIN[25][28][6]MAIN[25][29][5]MAIN[25][28][5]MAIN[25][29][4]MAIN[25][28][4]MAIN[25][29][10]MAIN[25][28][8]MAIN[25][29][9]MAIN[25][28][10]MAIN[25][28][7]MAIN[25][29][7]MAIN[25][29][8]MAIN[25][28][9]CELL[25].HROW_O[8]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[9]
BitsDestination
MAIN[25][27][13]MAIN[25][26][13]MAIN[25][27][12]MAIN[25][26][12]MAIN[25][27][11]MAIN[25][26][11]MAIN[25][27][17]MAIN[25][26][15]MAIN[25][27][16]MAIN[25][26][17]MAIN[25][26][14]MAIN[25][27][14]MAIN[25][27][15]MAIN[25][26][16]CELL[25].HROW_O[9]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[10]
BitsDestination
MAIN[25][29][13]MAIN[25][28][13]MAIN[25][29][12]MAIN[25][28][12]MAIN[25][29][11]MAIN[25][28][11]MAIN[25][29][17]MAIN[25][28][15]MAIN[25][29][16]MAIN[25][28][17]MAIN[25][28][14]MAIN[25][29][14]MAIN[25][29][15]MAIN[25][28][16]CELL[25].HROW_O[10]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[11]
BitsDestination
MAIN[25][27][20]MAIN[25][26][20]MAIN[25][27][19]MAIN[25][26][19]MAIN[25][27][18]MAIN[25][26][18]MAIN[25][27][24]MAIN[25][26][22]MAIN[25][27][23]MAIN[25][26][24]MAIN[25][26][21]MAIN[25][27][21]MAIN[25][27][22]MAIN[25][26][23]CELL[25].HROW_O[11]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[12]
BitsDestination
MAIN[25][29][20]MAIN[25][28][20]MAIN[25][29][19]MAIN[25][28][19]MAIN[25][29][18]MAIN[25][28][18]MAIN[25][29][24]MAIN[25][28][22]MAIN[25][29][23]MAIN[25][28][24]MAIN[25][28][21]MAIN[25][29][21]MAIN[25][29][22]MAIN[25][28][23]CELL[25].HROW_O[12]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes HROW_O[13]
BitsDestination
MAIN[25][27][27]MAIN[25][26][27]MAIN[25][27][26]MAIN[25][26][26]MAIN[25][27][25]MAIN[25][26][25]MAIN[25][27][31]MAIN[25][26][29]MAIN[25][27][30]MAIN[25][26][31]MAIN[25][26][28]MAIN[25][27][28]MAIN[25][27][29]MAIN[25][26][30]CELL[25].HROW_O[13]
Source
00000000000000off
00000100000001CELL[25].HCLK_CMT[0]
00000100000010CELL[25].HCLK_CMT[6]
00000100000100CELL[25].HROW_I_CMT[4]
00000100001000CELL[25].HROW_I_CMT[8]
00000100010000CELL[25].OUT_PLL_N[6]
00000100100000CELL[25].OUT_PLL_S[4]
00000101000000CELL[25].OUT_PLL_S[10]
00000110000000CELL[25].OUT_PLL_N[0]
00001000000001CELL[25].HCLK_CMT[1]
00001000000010CELL[25].HCLK_CMT[7]
00001000000100CELL[25].HROW_I_CMT[5]
00001000001000CELL[25].HROW_I_CMT[9]
00001000010000CELL[25].OUT_PLL_N[7]
00001000100000CELL[25].OUT_PLL_S[5]
00001001000000CELL[25].OUT_PLL_S[11]
00001010000000CELL[25].OUT_PLL_N[1]
00010000000001CELL[25].HCLK_CMT[2]
00010000000010CELL[25].HCLK_CMT[8]
00010000000100CELL[25].HROW_I_CMT[6]
00010000001000CELL[25].HROW_I_CMT[10]
00010000010000CELL[25].OUT_PLL_S[0]
00010000100000CELL[25].OUT_PLL_S[6]
00010001000000CELL[25].OUT_PLL_S[12]
00010010000000CELL[25].OUT_PLL_N[2]
00100000000001CELL[25].HCLK_CMT[3]
00100000000010CELL[25].HCLK_CMT[9]
00100000000100CELL[25].HROW_I_CMT[7]
00100000001000CELL[25].HROW_I_CMT[11]
00100000010000CELL[25].OUT_PLL_S[1]
00100000100000CELL[25].OUT_PLL_S[7]
00100001000000CELL[25].OUT_PLL_S[13]
00100010000000CELL[25].OUT_PLL_N[3]
01000000000001CELL[25].HCLK_CMT[4]
01000000000010CELL[25].HCLK_CMT[10]
01000000000100CELL[25].OMUX_CCIO[2]
01000000001000CELL[25].HROW_I_CMT[12]
01000000010000CELL[25].OUT_PLL_S[2]
01000000100000CELL[25].OUT_PLL_S[8]
01000001000000CELL[25].OMUX_CCIO[0]
01000010000000CELL[25].OUT_PLL_N[4]
10000000000001CELL[25].HCLK_CMT[5]
10000000000010CELL[25].HCLK_CMT[11]
10000000000100CELL[25].OMUX_CCIO[3]
10000000001000CELL[25].HROW_I_CMT[13]
10000000010000CELL[25].OUT_PLL_S[3]
10000000100000CELL[25].OUT_PLL_S[9]
10000001000000CELL[25].OMUX_CCIO[1]
10000010000000CELL[25].OUT_PLL_N[5]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB[0]
BitsDestination
MAIN[36][29][45]MAIN[16][29][53]MAIN[36][28][54]MAIN[16][28][46]MAIN[36][29][34]MAIN[16][29][34]MAIN[24][29][63]CELL[25].CMT_FREQ_BB[0]
Source
0000000off
0000001CELL[25].OMUX_HCLK_FREQ_BB[0]
0000010CELL[25].OMUX_PLL_FREQ_BB_S[0]
0000100CELL[25].OMUX_PLL_FREQ_BB_N[0]
0101000CELL[25].CMT_FREQ_BB_S[0]
1010000CELL[25].CMT_FREQ_BB_N[0]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB[1]
BitsDestination
MAIN[36][29][46]MAIN[16][29][54]MAIN[36][28][55]MAIN[16][28][47]MAIN[36][28][35]MAIN[16][28][35]MAIN[24][28][63]CELL[25].CMT_FREQ_BB[1]
Source
0000000off
0000001CELL[25].OMUX_HCLK_FREQ_BB[1]
0000010CELL[25].OMUX_PLL_FREQ_BB_S[1]
0000100CELL[25].OMUX_PLL_FREQ_BB_N[1]
0101000CELL[25].CMT_FREQ_BB_S[1]
1010000CELL[25].CMT_FREQ_BB_N[1]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB[2]
BitsDestination
MAIN[36][29][47]MAIN[16][29][55]MAIN[36][28][56]MAIN[16][28][48]MAIN[36][29][35]MAIN[16][29][35]MAIN[24][29][62]CELL[25].CMT_FREQ_BB[2]
Source
0000000off
0000001CELL[25].OMUX_HCLK_FREQ_BB[2]
0000010CELL[25].OMUX_PLL_FREQ_BB_S[2]
0000100CELL[25].OMUX_PLL_FREQ_BB_N[2]
0101000CELL[25].CMT_FREQ_BB_S[2]
1010000CELL[25].CMT_FREQ_BB_N[2]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB[3]
BitsDestination
MAIN[36][29][48]MAIN[16][29][56]MAIN[36][28][57]MAIN[16][28][49]MAIN[36][28][36]MAIN[16][28][36]MAIN[24][28][62]CELL[25].CMT_FREQ_BB[3]
Source
0000000off
0000001CELL[25].OMUX_HCLK_FREQ_BB[3]
0000010CELL[25].OMUX_PLL_FREQ_BB_S[3]
0000100CELL[25].OMUX_PLL_FREQ_BB_N[3]
0101000CELL[25].CMT_FREQ_BB_S[3]
1010000CELL[25].CMT_FREQ_BB_N[3]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_S[0]
BitsDestination
MAIN[16][29][45]MAIN[16][28][54]CELL[25].CMT_FREQ_BB_S[0]
Source
00off
11CELL[25].CMT_FREQ_BB[0]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_S[1]
BitsDestination
MAIN[16][29][46]MAIN[16][28][55]CELL[25].CMT_FREQ_BB_S[1]
Source
00off
11CELL[25].CMT_FREQ_BB[1]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_S[2]
BitsDestination
MAIN[16][29][47]MAIN[16][28][56]CELL[25].CMT_FREQ_BB_S[2]
Source
00off
11CELL[25].CMT_FREQ_BB[2]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_S[3]
BitsDestination
MAIN[16][29][48]MAIN[16][28][57]CELL[25].CMT_FREQ_BB_S[3]
Source
00off
11CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_N[0]
BitsDestination
MAIN[36][29][53]MAIN[36][28][46]CELL[25].CMT_FREQ_BB_N[0]
Source
00off
11CELL[25].CMT_FREQ_BB[0]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_N[1]
BitsDestination
MAIN[36][29][54]MAIN[36][28][47]CELL[25].CMT_FREQ_BB_N[1]
Source
00off
11CELL[25].CMT_FREQ_BB[1]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_N[2]
BitsDestination
MAIN[36][29][55]MAIN[36][28][48]CELL[25].CMT_FREQ_BB_N[2]
Source
00off
11CELL[25].CMT_FREQ_BB[2]
virtex7 CMT switchbox SPEC_INT muxes CMT_FREQ_BB_N[3]
BitsDestination
MAIN[36][29][56]MAIN[36][28][49]CELL[25].CMT_FREQ_BB_N[3]
Source
00off
11CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_BUFMRCE[0]
BitsDestination
HCLK[27][28]HCLK[27][30]MAIN[25][26][1]MAIN[25][27][0]MAIN[25][26][0]HCLK[27][31]HCLK[26][31]HCLK[26][28]MAIN[25][29][2]MAIN[25][28][2]CELL[25].IMUX_BUFMRCE[0]
Source
0000000000off
0000000001CELL[25].CCIO_CMT[0]
0000001110CELL[25].CKINT_CMT[0]
0000010110CELL[25].CKINT_CMT[1]
0000100110CELL[25].HROW_I_CMT[4]
0001000110CELL[25].HROW_I_CMT[5]
0010000110CELL[25].HROW_I_CMT[6]
0100000110CELL[25].HROW_I_CMT[7]
1000001010CELL[25].HROW_I_CMT[12]
1000010010CELL[25].HROW_I_CMT[13]
1000100010CELL[25].HROW_I_CMT[8]
1001000010CELL[25].HROW_I_CMT[9]
1010000010CELL[25].HROW_I_CMT[10]
1100000010CELL[25].HROW_I_CMT[11]
virtex7 CMT switchbox SPEC_INT muxes IMUX_BUFMRCE[1]
BitsDestination
HCLK[27][27]HCLK[26][29]MAIN[25][27][2]MAIN[25][26][2]MAIN[25][27][1]HCLK[26][30]HCLK[27][29]HCLK[26][27]HCLK[27][26]HCLK[26][26]CELL[25].IMUX_BUFMRCE[1]
Source
0000000000off
0000000001CELL[25].CCIO_CMT[3]
0000001110CELL[25].CKINT_CMT[0]
0000010110CELL[25].CKINT_CMT[1]
0000100110CELL[25].HROW_I_CMT[4]
0001000110CELL[25].HROW_I_CMT[5]
0010000110CELL[25].HROW_I_CMT[6]
0100000110CELL[25].HROW_I_CMT[7]
1000001010CELL[25].HROW_I_CMT[12]
1000010010CELL[25].HROW_I_CMT[13]
1000100010CELL[25].HROW_I_CMT[8]
1001000010CELL[25].HROW_I_CMT[9]
1010000010CELL[25].HROW_I_CMT[10]
1100000010CELL[25].HROW_I_CMT[11]
virtex7 CMT switchbox SPEC_INT muxes LCLK_CMT_S[0]
BitsDestination
MAIN[24][27][17]MAIN[24][26][17]MAIN[24][27][16]MAIN[24][26][18]MAIN[24][27][18]MAIN[24][26][19]MAIN[24][27][19]MAIN[24][26][20]MAIN[24][27][20]CELL[25].LCLK_CMT_S[0]
Source
000000000off
001000001CELL[25].HCLK_CMT[0]
001000010CELL[25].HCLK_CMT[1]
001000100CELL[25].HCLK_CMT[2]
001001000CELL[25].HCLK_CMT[3]
001010000CELL[25].HCLK_CMT[4]
001100000CELL[25].HCLK_CMT[5]
010000001CELL[25].HCLK_CMT[6]
010000010CELL[25].HCLK_CMT[7]
010000100CELL[25].HCLK_CMT[8]
010001000CELL[25].HCLK_CMT[9]
010010000CELL[25].HCLK_CMT[10]
010100000CELL[25].HCLK_CMT[11]
100000001CELL[25].RCLK_CMT[0]
100000010CELL[25].RCLK_CMT[1]
100000100CELL[25].RCLK_CMT[2]
100001000CELL[25].RCLK_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes LCLK_CMT_S[1]
BitsDestination
MAIN[24][29][17]MAIN[24][28][17]MAIN[24][29][16]MAIN[24][28][18]MAIN[24][29][18]MAIN[24][28][19]MAIN[24][29][19]MAIN[24][28][20]MAIN[24][29][20]CELL[25].LCLK_CMT_S[1]
Source
000000000off
001000001CELL[25].HCLK_CMT[0]
001000010CELL[25].HCLK_CMT[1]
001000100CELL[25].HCLK_CMT[2]
001001000CELL[25].HCLK_CMT[3]
001010000CELL[25].HCLK_CMT[4]
001100000CELL[25].HCLK_CMT[5]
010000001CELL[25].HCLK_CMT[6]
010000010CELL[25].HCLK_CMT[7]
010000100CELL[25].HCLK_CMT[8]
010001000CELL[25].HCLK_CMT[9]
010010000CELL[25].HCLK_CMT[10]
010100000CELL[25].HCLK_CMT[11]
100000001CELL[25].RCLK_CMT[0]
100000010CELL[25].RCLK_CMT[1]
100000100CELL[25].RCLK_CMT[2]
100001000CELL[25].RCLK_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes LCLK_CMT_N[0]
BitsDestination
MAIN[25][26][46]MAIN[25][27][46]MAIN[25][26][47]MAIN[25][27][45]MAIN[25][26][45]MAIN[25][27][44]MAIN[25][26][44]MAIN[25][27][43]MAIN[25][26][43]CELL[25].LCLK_CMT_N[0]
Source
000000000off
001000001CELL[25].HCLK_CMT[0]
001000010CELL[25].HCLK_CMT[1]
001000100CELL[25].HCLK_CMT[2]
001001000CELL[25].HCLK_CMT[3]
001010000CELL[25].HCLK_CMT[4]
001100000CELL[25].HCLK_CMT[5]
010000001CELL[25].HCLK_CMT[6]
010000010CELL[25].HCLK_CMT[7]
010000100CELL[25].HCLK_CMT[8]
010001000CELL[25].HCLK_CMT[9]
010010000CELL[25].HCLK_CMT[10]
010100000CELL[25].HCLK_CMT[11]
100000001CELL[25].RCLK_CMT[0]
100000010CELL[25].RCLK_CMT[1]
100000100CELL[25].RCLK_CMT[2]
100001000CELL[25].RCLK_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes LCLK_CMT_N[1]
BitsDestination
MAIN[25][28][46]MAIN[25][29][46]MAIN[25][28][47]MAIN[25][29][45]MAIN[25][28][45]MAIN[25][29][44]MAIN[25][28][44]MAIN[25][29][43]MAIN[25][28][43]CELL[25].LCLK_CMT_N[1]
Source
000000000off
001000001CELL[25].HCLK_CMT[0]
001000010CELL[25].HCLK_CMT[1]
001000100CELL[25].HCLK_CMT[2]
001001000CELL[25].HCLK_CMT[3]
001010000CELL[25].HCLK_CMT[4]
001100000CELL[25].HCLK_CMT[5]
010000001CELL[25].HCLK_CMT[6]
010000010CELL[25].HCLK_CMT[7]
010000100CELL[25].HCLK_CMT[8]
010001000CELL[25].HCLK_CMT[9]
010010000CELL[25].HCLK_CMT[10]
010100000CELL[25].HCLK_CMT[11]
100000001CELL[25].RCLK_CMT[0]
100000010CELL[25].RCLK_CMT[1]
100000100CELL[25].RCLK_CMT[2]
100001000CELL[25].RCLK_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK[0]
BitsDestination
MAIN[24][28][23]MAIN[24][29][22]MAIN[24][28][22]MAIN[24][29][21]MAIN[24][28][21]MAIN[24][29][23]MAIN[24][28][24]MAIN[24][29][24]MAIN[24][28][25]MAIN[24][29][25]MAIN[24][28][26]CELL[25].IMUX_PLL_CLKIN1_HCLK[0]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK[1]
BitsDestination
MAIN[25][29][40]MAIN[25][28][41]MAIN[25][29][41]MAIN[25][28][42]MAIN[25][29][42]MAIN[25][28][40]MAIN[25][29][39]MAIN[25][28][39]MAIN[25][29][38]MAIN[25][28][38]MAIN[25][29][37]CELL[25].IMUX_PLL_CLKIN1_HCLK[1]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK[0]
BitsDestination
MAIN[24][26][23]MAIN[24][27][22]MAIN[24][26][22]MAIN[24][27][21]MAIN[24][26][21]MAIN[24][27][23]MAIN[24][26][24]MAIN[24][27][24]MAIN[24][26][25]MAIN[24][27][25]MAIN[24][26][26]CELL[25].IMUX_PLL_CLKIN2_HCLK[0]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK[1]
BitsDestination
MAIN[25][27][40]MAIN[25][26][41]MAIN[25][27][41]MAIN[25][26][42]MAIN[25][27][42]MAIN[25][26][40]MAIN[25][27][39]MAIN[25][26][39]MAIN[25][27][38]MAIN[25][26][38]MAIN[25][27][37]CELL[25].IMUX_PLL_CLKIN2_HCLK[1]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK[0]
BitsDestination
MAIN[24][27][28]MAIN[24][26][28]MAIN[24][27][27]MAIN[24][26][27]MAIN[24][27][26]MAIN[24][26][29]MAIN[24][27][29]MAIN[24][26][30]MAIN[24][27][30]MAIN[24][26][31]MAIN[24][27][31]CELL[25].IMUX_PLL_CLKFB_HCLK[0]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK[1]
BitsDestination
MAIN[25][26][35]MAIN[25][27][35]MAIN[25][26][36]MAIN[25][27][36]MAIN[25][26][37]MAIN[25][27][34]MAIN[25][26][34]MAIN[25][27][33]MAIN[25][26][33]MAIN[25][27][32]MAIN[25][26][32]CELL[25].IMUX_PLL_CLKFB_HCLK[1]
Source
00000000000off
00001000001CELL[25].HCLK_CMT[0]
00001000010CELL[25].HCLK_CMT[1]
00001000100CELL[25].HCLK_CMT[2]
00001001000CELL[25].HCLK_CMT[3]
00001010000CELL[25].HCLK_CMT[4]
00001100000CELL[25].HCLK_CMT[5]
00010000001CELL[25].HCLK_CMT[6]
00010000010CELL[25].HCLK_CMT[7]
00010000100CELL[25].HCLK_CMT[8]
00010001000CELL[25].HCLK_CMT[9]
00010010000CELL[25].HCLK_CMT[10]
00010100000CELL[25].HCLK_CMT[11]
00100000001CELL[25].RCLK_CMT[0]
00100000010CELL[25].RCLK_CMT[1]
00100000100CELL[25].RCLK_CMT[2]
00100001000CELL[25].RCLK_CMT[3]
00100010000CELL[25].OMUX_CCIO[0]
00100100000CELL[25].OMUX_CCIO[1]
01000000001CELL[25].HROW_I_CMT[4]
01000000010CELL[25].HROW_I_CMT[5]
01000000100CELL[25].HROW_I_CMT[6]
01000001000CELL[25].HROW_I_CMT[7]
01000010000CELL[25].OMUX_CCIO[2]
01000100000CELL[25].OMUX_CCIO[3]
10000000001CELL[25].HROW_I_CMT[8]
10000000010CELL[25].HROW_I_CMT[9]
10000000100CELL[25].HROW_I_CMT[10]
10000001000CELL[25].HROW_I_CMT[11]
10000010000CELL[25].HROW_I_CMT[12]
10000100000CELL[25].HROW_I_CMT[13]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1[0]
BitsDestination
MAIN[15][28][54]MAIN[15][29][53]MAIN[15][29][54]CELL[25].IMUX_PLL_CLKIN1[0]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].IMUX_PLL_CLKIN1_HCLK[0]
011CELL[15].IMUX_CLK[0]
100CELL[25].CMT_FREQ_BB[2]
101CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1[1]
BitsDestination
MAIN[37][28][10]MAIN[37][29][9]MAIN[37][28][9]CELL[25].IMUX_PLL_CLKIN1[1]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].CMT_FREQ_BB[2]
011CELL[25].CMT_FREQ_BB[3]
100CELL[25].IMUX_PLL_CLKIN1_HCLK[1]
101CELL[37].IMUX_CLK[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2[0]
BitsDestination
MAIN[15][29][55]MAIN[15][28][55]MAIN[15][28][56]CELL[25].IMUX_PLL_CLKIN2[0]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].IMUX_PLL_CLKIN2_HCLK[0]
011CELL[15].IMUX_CLK[1]
100CELL[25].CMT_FREQ_BB[2]
101CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2[1]
BitsDestination
MAIN[37][29][8]MAIN[37][28][8]MAIN[37][29][7]CELL[25].IMUX_PLL_CLKIN2[1]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].CMT_FREQ_BB[2]
011CELL[25].CMT_FREQ_BB[3]
100CELL[25].IMUX_PLL_CLKIN2_HCLK[1]
101CELL[37].IMUX_CLK[0]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB[0]
BitsDestination
MAIN[15][29][52]MAIN[15][28][52]MAIN[15][28][53]CELL[25].IMUX_PLL_CLKFB[0]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].IMUX_PLL_CLKFB_HCLK[0]
011CELL[14].IMUX_CLK[0]
100CELL[25].CMT_FREQ_BB[2]
101CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB[1]
BitsDestination
MAIN[37][29][11]MAIN[37][28][11]MAIN[37][29][10]CELL[25].IMUX_PLL_CLKFB[1]
Source
000CELL[25].CMT_FREQ_BB[0]
001CELL[25].CMT_FREQ_BB[1]
010CELL[25].CMT_FREQ_BB[2]
011CELL[25].CMT_FREQ_BB[3]
100CELL[25].IMUX_PLL_CLKFB_HCLK[1]
101CELL[38].IMUX_CLK[0]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF[0]
BitsDestination
MAIN[15][29][63]MAIN[15][29][37]MAIN[15][28][37]MAIN[15][29][36]CELL[25].OMUX_PLL_PERF[0]
Source
0000off
1000CELL[25].OUT_PLL_S[0]
1001CELL[25].OUT_PLL_S[11]
1010CELL[25].OUT_PLL_S[4]
1100CELL[25].OUT_PLL_S[2]
1110CELL[25].OUT_PLL_S[6]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF[1]
BitsDestination
MAIN[15][28][63]MAIN[15][28][36]MAIN[15][29][35]MAIN[15][28][35]CELL[25].OMUX_PLL_PERF[1]
Source
0000off
1000CELL[25].OUT_PLL_S[0]
1001CELL[25].OUT_PLL_S[11]
1010CELL[25].OUT_PLL_S[4]
1100CELL[25].OUT_PLL_S[2]
1110CELL[25].OUT_PLL_S[6]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF[2]
BitsDestination
MAIN[15][29][62]MAIN[15][29][34]MAIN[15][28][34]MAIN[15][29][33]CELL[25].OMUX_PLL_PERF[2]
Source
0000off
1000CELL[25].OUT_PLL_S[0]
1001CELL[25].OUT_PLL_S[11]
1010CELL[25].OUT_PLL_S[4]
1100CELL[25].OUT_PLL_S[2]
1110CELL[25].OUT_PLL_S[6]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF[3]
BitsDestination
MAIN[15][28][62]MAIN[15][28][33]MAIN[15][29][32]MAIN[15][28][32]CELL[25].OMUX_PLL_PERF[3]
Source
0000off
1000CELL[25].OUT_PLL_S[0]
1001CELL[25].OUT_PLL_S[11]
1010CELL[25].OUT_PLL_S[4]
1100CELL[25].OUT_PLL_S[2]
1110CELL[25].OUT_PLL_S[6]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_S[0]
BitsDestination
MAIN[16][28][60]MAIN[16][29][59]CELL[25].OMUX_PLL_FREQ_BB_S[0]
Source
00CELL[25].OUT_PLL_FREQ_BB_S[0]
01CELL[25].OUT_PLL_FREQ_BB_S[1]
10CELL[25].OUT_PLL_FREQ_BB_S[2]
11CELL[25].OUT_PLL_FREQ_BB_S[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_S[1]
BitsDestination
MAIN[16][28][61]MAIN[16][29][60]CELL[25].OMUX_PLL_FREQ_BB_S[1]
Source
00CELL[25].OUT_PLL_FREQ_BB_S[0]
01CELL[25].OUT_PLL_FREQ_BB_S[1]
10CELL[25].OUT_PLL_FREQ_BB_S[2]
11CELL[25].OUT_PLL_FREQ_BB_S[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_S[2]
BitsDestination
MAIN[16][28][62]MAIN[16][29][61]CELL[25].OMUX_PLL_FREQ_BB_S[2]
Source
00CELL[25].OUT_PLL_FREQ_BB_S[0]
01CELL[25].OUT_PLL_FREQ_BB_S[1]
10CELL[25].OUT_PLL_FREQ_BB_S[2]
11CELL[25].OUT_PLL_FREQ_BB_S[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_S[3]
BitsDestination
MAIN[16][28][63]MAIN[16][29][62]CELL[25].OMUX_PLL_FREQ_BB_S[3]
Source
00CELL[25].OUT_PLL_FREQ_BB_S[0]
01CELL[25].OUT_PLL_FREQ_BB_S[1]
10CELL[25].OUT_PLL_FREQ_BB_S[2]
11CELL[25].OUT_PLL_FREQ_BB_S[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_N[0]
BitsDestination
MAIN[36][28][60]MAIN[36][29][59]CELL[25].OMUX_PLL_FREQ_BB_N[0]
Source
00CELL[25].OUT_PLL_FREQ_BB_N[0]
01CELL[25].OUT_PLL_FREQ_BB_N[1]
10CELL[25].OUT_PLL_FREQ_BB_N[2]
11CELL[25].OUT_PLL_FREQ_BB_N[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_N[1]
BitsDestination
MAIN[36][28][61]MAIN[36][29][60]CELL[25].OMUX_PLL_FREQ_BB_N[1]
Source
00CELL[25].OUT_PLL_FREQ_BB_N[0]
01CELL[25].OUT_PLL_FREQ_BB_N[1]
10CELL[25].OUT_PLL_FREQ_BB_N[2]
11CELL[25].OUT_PLL_FREQ_BB_N[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_N[2]
BitsDestination
MAIN[36][28][62]MAIN[36][29][61]CELL[25].OMUX_PLL_FREQ_BB_N[2]
Source
00CELL[25].OUT_PLL_FREQ_BB_N[0]
01CELL[25].OUT_PLL_FREQ_BB_N[1]
10CELL[25].OUT_PLL_FREQ_BB_N[2]
11CELL[25].OUT_PLL_FREQ_BB_N[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_PLL_FREQ_BB_N[3]
BitsDestination
MAIN[36][28][63]MAIN[36][29][62]CELL[25].OMUX_PLL_FREQ_BB_N[3]
Source
00CELL[25].OUT_PLL_FREQ_BB_N[0]
01CELL[25].OUT_PLL_FREQ_BB_N[1]
10CELL[25].OUT_PLL_FREQ_BB_N[2]
11CELL[25].OUT_PLL_FREQ_BB_N[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_HCLK_FREQ_BB[0]
BitsDestination
MAIN[25][28][3]MAIN[25][29][3]CELL[25].OMUX_HCLK_FREQ_BB[0]
Source
00off
01CELL[25].CKINT_CMT[0]
10CELL[25].CCIO_CMT[0]
virtex7 CMT switchbox SPEC_INT muxes OMUX_HCLK_FREQ_BB[1]
BitsDestination
MAIN[25][28][1]MAIN[25][29][1]CELL[25].OMUX_HCLK_FREQ_BB[1]
Source
00off
01CELL[25].CKINT_CMT[1]
10CELL[25].CCIO_CMT[1]
virtex7 CMT switchbox SPEC_INT muxes OMUX_HCLK_FREQ_BB[2]
BitsDestination
MAIN[25][28][0]MAIN[25][29][0]CELL[25].OMUX_HCLK_FREQ_BB[2]
Source
00off
01CELL[25].CKINT_CMT[2]
10CELL[25].CCIO_CMT[2]
virtex7 CMT switchbox SPEC_INT muxes OMUX_HCLK_FREQ_BB[3]
BitsDestination
MAIN[25][26][3]MAIN[25][27][3]CELL[25].OMUX_HCLK_FREQ_BB[3]
Source
00off
01CELL[25].CKINT_CMT[3]
10CELL[25].CCIO_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes OMUX_CCIO[0]
BitsDestination
MAIN[24][27][61]MAIN[24][27][60]MAIN[24][26][61]CELL[25].OMUX_CCIO[0]
Source
000off
001CELL[25].OUT_PHASER_REF_CLKOUT
010CELL[25].OUT_PHASER_REF_TMUXOUT
100CELL[25].CCIO_CMT[0]
virtex7 CMT switchbox SPEC_INT muxes OMUX_CCIO[1]
BitsDestination
MAIN[24][26][60]MAIN[25][27][47]MAIN[24][26][16]CELL[25].OMUX_CCIO[1]
Source
000off
001CELL[25].OUT_PHASER_REF_CLKOUT
010CELL[25].OUT_PHASER_REF_TMUXOUT
100CELL[25].CCIO_CMT[1]
virtex7 CMT switchbox SPEC_INT muxes OMUX_CCIO[2]
BitsDestination
MAIN[25][28][25]MAIN[25][28][26]MAIN[25][29][25]CELL[25].OMUX_CCIO[2]
Source
000off
001CELL[25].OUT_PHASER_REF_CLKOUT
010CELL[25].OUT_PHASER_REF_TMUXOUT
100CELL[25].CCIO_CMT[2]
virtex7 CMT switchbox SPEC_INT muxes OMUX_CCIO[3]
BitsDestination
MAIN[25][29][26]MAIN[25][29][27]MAIN[25][28][27]CELL[25].OMUX_CCIO[3]
Source
000off
001CELL[25].OUT_PHASER_REF_CLKOUT
010CELL[25].OUT_PHASER_REF_TMUXOUT
100CELL[25].CCIO_CMT[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_REFMUX[0]
BitsDestination
MAIN[36][29][37]MAIN[36][28][37]MAIN[36][29][36]CELL[25].IMUX_PHASER_REFMUX[0]
Source
000CELL[25].OUT_PLL_FREQ_BB_N[0]
001CELL[25].CMT_FREQ_BB[0]
011CELL[25].CMT_FREQ_BB[1]
101CELL[25].CMT_FREQ_BB[2]
111CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_REFMUX[1]
BitsDestination
MAIN[36][29][57]MAIN[36][28][41]MAIN[36][29][40]CELL[25].IMUX_PHASER_REFMUX[1]
Source
000CELL[25].OUT_PLL_FREQ_BB_N[1]
001CELL[25].CMT_FREQ_BB[0]
011CELL[25].CMT_FREQ_BB[1]
101CELL[25].CMT_FREQ_BB[2]
111CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_REFMUX[2]
BitsDestination
MAIN[36][28][59]MAIN[36][29][58]MAIN[36][28][58]CELL[25].IMUX_PHASER_REFMUX[2]
Source
000CELL[25].OUT_PLL_FREQ_BB_N[2]
001CELL[25].CMT_FREQ_BB[0]
011CELL[25].CMT_FREQ_BB[1]
101CELL[25].CMT_FREQ_BB[2]
111CELL[25].CMT_FREQ_BB[3]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_IN_PHASEREFCLK[0]
BitsDestination
MAIN[19][28][28]MAIN[19][28][27]MAIN[19][29][27]MAIN[18][29][59]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0]
Source
0000IO[8].OUT_CLKPAD
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_IN_PHASEREFCLK[1]
BitsDestination
MAIN[22][28][60]MAIN[22][28][59]MAIN[22][29][59]MAIN[22][29][27]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1]
Source
0000IO[20].OUT_CLKPAD
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_IN_PHASEREFCLK[2]
BitsDestination
MAIN[29][28][28]MAIN[29][28][27]MAIN[29][29][27]MAIN[28][29][59]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2]
Source
0000IO[32].OUT_CLKPAD
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_IN_PHASEREFCLK[3]
BitsDestination
MAIN[32][28][60]MAIN[32][28][59]MAIN[32][29][59]MAIN[32][29][27]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3]
Source
0000IO[44].OUT_CLKPAD
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_OUT_PHASEREFCLK[0]
BitsDestination
MAIN[18][28][2]MAIN[18][28][1]MAIN[18][29][1]MAIN[18][29][0]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0]
Source
0000off
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_OUT_PHASEREFCLK[1]
BitsDestination
MAIN[21][28][34]MAIN[21][28][33]MAIN[21][29][33]MAIN[21][29][32]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1]
Source
0000off
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_OUT_PHASEREFCLK[2]
BitsDestination
MAIN[28][28][2]MAIN[28][28][1]MAIN[28][29][1]MAIN[28][29][0]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2]
Source
0000off
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes IMUX_PHASER_OUT_PHASEREFCLK[3]
BitsDestination
MAIN[31][28][34]MAIN[31][28][33]MAIN[31][29][33]MAIN[31][29][32]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3]
Source
0000off
0001CELL[25].VMRCLK_N[0]
0011CELL[25].VMRCLK[0]
0101CELL[25].VMRCLK_N[1]
0111CELL[25].VMRCLK[1]
1001CELL[25].VMRCLK_S[0]
1101CELL[25].VMRCLK_S[1]
virtex7 CMT switchbox SPEC_INT muxes PERF[0]
BitsDestination
HCLK[27][19]HCLK[26][20]HCLK[26][18]HCLK[26][17]HCLK[26][16]IO[25].PERF[0]
Source
00000off
01001CELL[25].PERF_IN_PLL[0]
01010CELL[25].PERF_IN_PLL[1]
01100CELL[25].PERF_IN_PHASER[3]
10001CELL[25].PERF_IN_PHASER[0]
10010CELL[25].PERF_IN_PHASER[1]
10100CELL[25].PERF_IN_PHASER[2]
virtex7 CMT switchbox SPEC_INT muxes PERF[1]
BitsDestination
HCLK[26][19]HCLK[27][20]HCLK[27][18]HCLK[27][17]HCLK[27][16]IO[25].PERF[1]
Source
00000off
01001CELL[25].PERF_IN_PLL[0]
01010CELL[25].PERF_IN_PLL[1]
01100CELL[25].PERF_IN_PHASER[3]
10001CELL[25].PERF_IN_PHASER[0]
10010CELL[25].PERF_IN_PHASER[1]
10100CELL[25].PERF_IN_PHASER[2]
virtex7 CMT switchbox SPEC_INT muxes PERF[2]
BitsDestination
HCLK[29][19]HCLK[28][20]HCLK[28][18]HCLK[28][17]HCLK[28][16]IO[25].PERF[2]
Source
00000off
01001CELL[25].PERF_IN_PLL[2]
01010CELL[25].PERF_IN_PLL[3]
01100CELL[25].PERF_IN_PHASER[3]
10001CELL[25].PERF_IN_PHASER[0]
10010CELL[25].PERF_IN_PHASER[1]
10100CELL[25].PERF_IN_PHASER[2]
virtex7 CMT switchbox SPEC_INT muxes PERF[3]
BitsDestination
HCLK[28][19]HCLK[29][20]HCLK[29][18]HCLK[29][17]HCLK[29][16]IO[25].PERF[3]
Source
00000off
01001CELL[25].PERF_IN_PLL[2]
01010CELL[25].PERF_IN_PLL[3]
01100CELL[25].PERF_IN_PHASER[3]
10001CELL[25].PERF_IN_PHASER[0]
10010CELL[25].PERF_IN_PHASER[1]
10100CELL[25].PERF_IN_PHASER[2]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB[0]
Bit
MAIN[16][28][42]
MAIN[16][28][50]
MAIN[16][29][32]
MAIN[24][29][61]
MAIN[36][29][32]
MAIN[36][29][41]
MAIN[36][29][49]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB[1]
Bit
MAIN[16][28][33]
MAIN[16][28][43]
MAIN[16][28][51]
MAIN[24][28][61]
MAIN[36][28][33]
MAIN[36][29][42]
MAIN[36][29][50]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB[2]
Bit
MAIN[16][28][44]
MAIN[16][28][52]
MAIN[16][29][33]
MAIN[24][29][60]
MAIN[36][29][33]
MAIN[36][29][43]
MAIN[36][29][51]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB[3]
Bit
MAIN[16][28][34]
MAIN[16][28][45]
MAIN[16][28][53]
MAIN[24][28][60]
MAIN[36][28][34]
MAIN[36][29][44]
MAIN[36][29][52]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_S[0]
Bit
MAIN[16][29][41]
MAIN[16][29][49]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_S[1]
Bit
MAIN[16][29][42]
MAIN[16][29][50]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_S[2]
Bit
MAIN[16][29][43]
MAIN[16][29][51]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_S[3]
Bit
MAIN[16][29][44]
MAIN[16][29][52]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_N[0]
Bit
MAIN[36][28][42]
MAIN[36][28][50]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_N[1]
Bit
MAIN[36][28][43]
MAIN[36][28][51]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_N[2]
Bit
MAIN[36][28][44]
MAIN[36][28][52]
virtex7 CMT wire support CELL[25].CMT_FREQ_BB_N[3]
Bit
MAIN[36][28][45]
MAIN[36][28][53]
virtex7 CMT wire support CELL[25].CMT_SYNC_BB
Bit
MAIN[36][28][32]
MAIN[36][29][39]
MAIN[16][29][38]
virtex7 CMT wire support CELL[25].CMT_SYNC_BB_S
Bit
MAIN[16][28][32]
virtex7 CMT wire support CELL[25].CMT_SYNC_BB_N
Bit
MAIN[36][29][38]

Bels PLL_V6

virtex7 CMT bel PLL_V6 pins
PinDirectionPLL[0]PLL[1]
CLKIN1inCELL[25].IMUX_PLL_CLKIN1[0]CELL[25].IMUX_PLL_CLKIN1[1]
CLKIN2inCELL[25].IMUX_PLL_CLKIN2[0]CELL[25].IMUX_PLL_CLKIN2[1]
CLKINSELinCELL[2].IMUX_IMUX[0] invert by MAIN[1][29][45]CELL[47].IMUX_IMUX[47] invert by MAIN[48][28][18]
CLKFBINinCELL[25].IMUX_PLL_CLKFB[0]CELL[25].IMUX_PLL_CLKFB[1]
RSTinCELL[2].IMUX_IMUX[34] invert by MAIN[1][29][47]CELL[47].IMUX_IMUX[13] invert by MAIN[48][28][16]
PWRDWNinCELL[1].IMUX_IMUX[47] invert by MAIN[1][28][47]CELL[48].IMUX_IMUX[0] invert by MAIN[48][29][16]
DCLKinCELL[0].IMUX_CLK[0]CELL[49].IMUX_CLK[0]
DENinCELL[1].IMUX_IMUX[15]CELL[48].IMUX_IMUX[1]
DWEinCELL[1].IMUX_IMUX[22]CELL[48].IMUX_IMUX[2]
DADDR[0]inCELL[1].IMUX_IMUX[0]CELL[48].IMUX_IMUX[47]
DADDR[1]inCELL[1].IMUX_IMUX[1]CELL[48].IMUX_IMUX[15]
DADDR[2]inCELL[1].IMUX_IMUX[2]CELL[48].IMUX_IMUX[22]
DADDR[3]inCELL[1].IMUX_IMUX[34]CELL[48].IMUX_IMUX[13]
DADDR[4]inCELL[1].IMUX_IMUX[3]CELL[48].IMUX_IMUX[44]
DADDR[5]inCELL[1].IMUX_IMUX[35]CELL[48].IMUX_IMUX[35]
DADDR[6]inCELL[1].IMUX_IMUX[44]CELL[48].IMUX_IMUX[3]
DI[0]inCELL[0].IMUX_IMUX[0]CELL[49].IMUX_IMUX[39]
DI[1]inCELL[0].IMUX_IMUX[32]CELL[49].IMUX_IMUX[7]
DI[2]inCELL[0].IMUX_IMUX[1]CELL[49].IMUX_IMUX[38]
DI[3]inCELL[0].IMUX_IMUX[33]CELL[49].IMUX_IMUX[6]
DI[4]inCELL[0].IMUX_IMUX[2]CELL[49].IMUX_IMUX[37]
DI[5]inCELL[0].IMUX_IMUX[34]CELL[49].IMUX_IMUX[5]
DI[6]inCELL[0].IMUX_IMUX[3]CELL[49].IMUX_IMUX[36]
DI[7]inCELL[0].IMUX_IMUX[35]CELL[49].IMUX_IMUX[4]
DI[8]inCELL[0].IMUX_IMUX[4]CELL[49].IMUX_IMUX[35]
DI[9]inCELL[0].IMUX_IMUX[36]CELL[49].IMUX_IMUX[3]
DI[10]inCELL[0].IMUX_IMUX[5]CELL[49].IMUX_IMUX[34]
DI[11]inCELL[0].IMUX_IMUX[37]CELL[49].IMUX_IMUX[2]
DI[12]inCELL[0].IMUX_IMUX[6]CELL[49].IMUX_IMUX[33]
DI[13]inCELL[0].IMUX_IMUX[38]CELL[49].IMUX_IMUX[1]
DI[14]inCELL[0].IMUX_IMUX[7]CELL[49].IMUX_IMUX[32]
DI[15]inCELL[0].IMUX_IMUX[39]CELL[49].IMUX_IMUX[0]
PSCLKinCELL[1].IMUX_CLK[0]-
PSENinCELL[2].IMUX_IMUX[1] invert by MAIN[1][28][46]-
PSINCDECinCELL[2].IMUX_IMUX[2] invert by MAIN[1][29][46]-
TESTIN[0]inCELL[3].IMUX_IMUX[16]CELL[46].IMUX_IMUX[15]
TESTIN[1]inCELL[3].IMUX_IMUX[41]CELL[46].IMUX_IMUX[30]
TESTIN[2]inCELL[3].IMUX_IMUX[3]CELL[46].IMUX_IMUX[45]
TESTIN[3]inCELL[3].IMUX_IMUX[43]CELL[46].IMUX_IMUX[44]
TESTIN[4]inCELL[3].IMUX_IMUX[44]CELL[46].IMUX_IMUX[43]
TESTIN[5]inCELL[3].IMUX_IMUX[45]CELL[46].IMUX_IMUX[3]
TESTIN[6]inCELL[3].IMUX_IMUX[30]CELL[46].IMUX_IMUX[41]
TESTIN[7]inCELL[3].IMUX_IMUX[15]CELL[46].IMUX_IMUX[16]
TESTIN[8]inCELL[4].IMUX_IMUX[16]CELL[45].IMUX_IMUX[15]
TESTIN[9]inCELL[4].IMUX_IMUX[41]CELL[45].IMUX_IMUX[30]
TESTIN[10]inCELL[4].IMUX_IMUX[3]CELL[45].IMUX_IMUX[45]
TESTIN[11]inCELL[4].IMUX_IMUX[43]CELL[45].IMUX_IMUX[44]
TESTIN[12]inCELL[4].IMUX_IMUX[44]CELL[45].IMUX_IMUX[43]
TESTIN[13]inCELL[4].IMUX_IMUX[45]CELL[45].IMUX_IMUX[3]
TESTIN[14]inCELL[4].IMUX_IMUX[30]CELL[45].IMUX_IMUX[41]
TESTIN[15]inCELL[4].IMUX_IMUX[15]CELL[45].IMUX_IMUX[16]
TESTIN[16]inCELL[5].IMUX_IMUX[16]CELL[44].IMUX_IMUX[15]
TESTIN[17]inCELL[5].IMUX_IMUX[41]CELL[44].IMUX_IMUX[30]
TESTIN[18]inCELL[5].IMUX_IMUX[3]CELL[44].IMUX_IMUX[45]
TESTIN[19]inCELL[5].IMUX_IMUX[43]CELL[44].IMUX_IMUX[44]
TESTIN[20]inCELL[5].IMUX_IMUX[44]CELL[44].IMUX_IMUX[43]
TESTIN[21]inCELL[5].IMUX_IMUX[45]CELL[44].IMUX_IMUX[11]
TESTIN[22]inCELL[5].IMUX_IMUX[30]CELL[44].IMUX_IMUX[41]
TESTIN[23]inCELL[5].IMUX_IMUX[15]CELL[44].IMUX_IMUX[16]
TESTIN[24]inCELL[6].IMUX_IMUX[16]CELL[43].IMUX_IMUX[15]
TESTIN[25]inCELL[6].IMUX_IMUX[41]CELL[43].IMUX_IMUX[30]
TESTIN[26]inCELL[6].IMUX_IMUX[3]CELL[43].IMUX_IMUX[45]
TESTIN[27]inCELL[6].IMUX_IMUX[43]CELL[43].IMUX_IMUX[44]
TESTIN[28]inCELL[6].IMUX_IMUX[44]CELL[43].IMUX_IMUX[43]
TESTIN[29]inCELL[6].IMUX_IMUX[45]CELL[43].IMUX_IMUX[11]
TESTIN[30]inCELL[6].IMUX_IMUX[30]CELL[43].IMUX_IMUX[41]
TESTIN[31]inCELL[6].IMUX_IMUX[15]CELL[43].IMUX_IMUX[16]
CLKOUT0outCELL[25].OUT_PLL_S[0]CELL[25].OUT_PLL_N[0]
CLKOUT0BoutCELL[25].OUT_PLL_S[1]-
CLKOUT1outCELL[25].OUT_PLL_S[2]CELL[25].OUT_PLL_N[1]
CLKOUT1BoutCELL[25].OUT_PLL_S[3]-
CLKOUT2outCELL[25].OUT_PLL_S[4]CELL[25].OUT_PLL_N[2]
CLKOUT2BoutCELL[25].OUT_PLL_S[5]-
CLKOUT3outCELL[25].OUT_PLL_S[6]CELL[25].OUT_PLL_N[3]
CLKOUT3BoutCELL[25].OUT_PLL_S[7]-
CLKOUT4outCELL[25].OUT_PLL_S[8]CELL[25].OUT_PLL_N[4]
CLKOUT5outCELL[25].OUT_PLL_S[9]CELL[25].OUT_PLL_N[5]
CLKOUT6outCELL[25].OUT_PLL_S[10]-
CLKFBOUToutCELL[25].OUT_PLL_S[11]CELL[25].OUT_PLL_N[6]
CLKFBOUTBoutCELL[25].OUT_PLL_S[12]-
TMUXOUToutCELL[25].OUT_PLL_S[13]CELL[25].OUT_PLL_N[7]
LOCKEDoutCELL[1].OUT_BEL[18]CELL[48].OUT_BEL[21]
DRDYoutCELL[1].OUT_BEL[16]CELL[48].OUT_BEL[16]
DO[0]outCELL[0].OUT_BEL[8]CELL[49].OUT_BEL[17]
DO[1]outCELL[0].OUT_BEL[18]CELL[49].OUT_BEL[7]
DO[2]outCELL[0].OUT_BEL[0]CELL[49].OUT_BEL[21]
DO[3]outCELL[0].OUT_BEL[22]CELL[49].OUT_BEL[15]
DO[4]outCELL[0].OUT_BEL[13]CELL[49].OUT_BEL[20]
DO[5]outCELL[0].OUT_BEL[23]CELL[49].OUT_BEL[2]
DO[6]outCELL[0].OUT_BEL[5]CELL[49].OUT_BEL[16]
DO[7]outCELL[0].OUT_BEL[19]CELL[49].OUT_BEL[10]
DO[8]outCELL[0].OUT_BEL[10]CELL[49].OUT_BEL[19]
DO[9]outCELL[0].OUT_BEL[16]CELL[49].OUT_BEL[5]
DO[10]outCELL[0].OUT_BEL[2]CELL[49].OUT_BEL[23]
DO[11]outCELL[0].OUT_BEL[20]CELL[49].OUT_BEL[13]
DO[12]outCELL[0].OUT_BEL[15]CELL[49].OUT_BEL[22]
DO[13]outCELL[0].OUT_BEL[21]CELL[49].OUT_BEL[0]
DO[14]outCELL[0].OUT_BEL[7]CELL[49].OUT_BEL[18]
DO[15]outCELL[0].OUT_BEL[17]CELL[49].OUT_BEL[8]
PSDONEoutCELL[1].OUT_BEL[21]-
CLKINSTOPPEDoutCELL[2].OUT_BEL[18]-
CLKFBSTOPPEDoutCELL[2].OUT_BEL[16]-
TESTOUT[0]outCELL[3].OUT_BEL[18]CELL[46].OUT_BEL[17]
TESTOUT[1]outCELL[3].OUT_BEL[23]CELL[46].OUT_BEL[7]
TESTOUT[2]outCELL[3].OUT_BEL[10]CELL[46].OUT_BEL[21]
TESTOUT[3]outCELL[3].OUT_BEL[2]CELL[46].OUT_BEL[15]
TESTOUT[4]outCELL[3].OUT_BEL[15]CELL[46].OUT_BEL[2]
TESTOUT[5]outCELL[3].OUT_BEL[21]CELL[46].OUT_BEL[10]
TESTOUT[6]outCELL[3].OUT_BEL[7]CELL[46].OUT_BEL[23]
TESTOUT[7]outCELL[3].OUT_BEL[17]CELL[46].OUT_BEL[18]
TESTOUT[8]outCELL[4].OUT_BEL[18]CELL[45].OUT_BEL[17]
TESTOUT[9]outCELL[4].OUT_BEL[23]CELL[45].OUT_BEL[7]
TESTOUT[10]outCELL[4].OUT_BEL[10]CELL[45].OUT_BEL[15]
TESTOUT[11]outCELL[4].OUT_BEL[2]CELL[45].OUT_BEL[2]
TESTOUT[12]outCELL[4].OUT_BEL[15]CELL[45].OUT_BEL[16]
TESTOUT[13]outCELL[4].OUT_BEL[21]CELL[45].OUT_BEL[10]
TESTOUT[14]outCELL[4].OUT_BEL[7]CELL[45].OUT_BEL[23]
TESTOUT[15]outCELL[4].OUT_BEL[17]CELL[45].OUT_BEL[18]
TESTOUT[16]outCELL[5].OUT_BEL[18]CELL[44].OUT_BEL[17]
TESTOUT[17]outCELL[5].OUT_BEL[23]CELL[44].OUT_BEL[15]
TESTOUT[18]outCELL[5].OUT_BEL[10]CELL[44].OUT_BEL[16]
TESTOUT[19]outCELL[5].OUT_BEL[2]CELL[44].OUT_BEL[6]
TESTOUT[20]outCELL[5].OUT_BEL[15]CELL[44].OUT_BEL[9]
TESTOUT[21]outCELL[5].OUT_BEL[21]CELL[44].OUT_BEL[1]
TESTOUT[22]outCELL[5].OUT_BEL[7]CELL[44].OUT_BEL[18]
TESTOUT[23]outCELL[5].OUT_BEL[17]CELL[44].OUT_BEL[4]
TESTOUT[24]outCELL[6].OUT_BEL[18]CELL[43].OUT_BEL[17]
TESTOUT[25]outCELL[6].OUT_BEL[23]CELL[43].OUT_BEL[21]
TESTOUT[26]outCELL[6].OUT_BEL[10]CELL[43].OUT_BEL[15]
TESTOUT[27]outCELL[6].OUT_BEL[2]CELL[43].OUT_BEL[16]
TESTOUT[28]outCELL[6].OUT_BEL[15]CELL[43].OUT_BEL[6]
TESTOUT[29]outCELL[6].OUT_BEL[21]CELL[43].OUT_BEL[9]
TESTOUT[30]outCELL[6].OUT_BEL[7]CELL[43].OUT_BEL[1]
TESTOUT[31]outCELL[6].OUT_BEL[17]CELL[43].OUT_BEL[18]
TESTOUT[32]outCELL[7].OUT_BEL[18]CELL[42].OUT_BEL[17]
TESTOUT[33]outCELL[7].OUT_BEL[1]CELL[42].OUT_BEL[7]
TESTOUT[34]outCELL[7].OUT_BEL[9]CELL[42].OUT_BEL[21]
TESTOUT[35]outCELL[7].OUT_BEL[6]CELL[42].OUT_BEL[15]
TESTOUT[36]outCELL[7].OUT_BEL[16]CELL[42].OUT_BEL[2]
TESTOUT[37]outCELL[7].OUT_BEL[15]CELL[42].OUT_BEL[10]
TESTOUT[38]outCELL[7].OUT_BEL[21]CELL[42].OUT_BEL[23]
TESTOUT[39]outCELL[7].OUT_BEL[17]CELL[42].OUT_BEL[18]
TESTOUT[40]outCELL[8].OUT_BEL[4]CELL[41].OUT_BEL[17]
TESTOUT[41]outCELL[8].OUT_BEL[18]CELL[41].OUT_BEL[7]
TESTOUT[42]outCELL[8].OUT_BEL[1]CELL[41].OUT_BEL[21]
TESTOUT[43]outCELL[8].OUT_BEL[9]CELL[41].OUT_BEL[15]
TESTOUT[44]outCELL[8].OUT_BEL[6]CELL[41].OUT_BEL[2]
TESTOUT[45]outCELL[8].OUT_BEL[16]CELL[41].OUT_BEL[10]
TESTOUT[46]outCELL[8].OUT_BEL[15]CELL[41].OUT_BEL[23]
TESTOUT[47]outCELL[8].OUT_BEL[17]CELL[41].OUT_BEL[18]
TESTOUT[48]outCELL[9].OUT_BEL[18]CELL[40].OUT_BEL[17]
TESTOUT[49]outCELL[9].OUT_BEL[23]CELL[40].OUT_BEL[7]
TESTOUT[50]outCELL[9].OUT_BEL[10]CELL[40].OUT_BEL[21]
TESTOUT[51]outCELL[9].OUT_BEL[2]CELL[40].OUT_BEL[15]
TESTOUT[52]outCELL[9].OUT_BEL[15]CELL[40].OUT_BEL[2]
TESTOUT[53]outCELL[9].OUT_BEL[21]CELL[40].OUT_BEL[10]
TESTOUT[54]outCELL[9].OUT_BEL[7]CELL[40].OUT_BEL[23]
TESTOUT[55]outCELL[9].OUT_BEL[17]CELL[40].OUT_BEL[18]
TESTOUT[56]outCELL[10].OUT_BEL[18]CELL[39].OUT_BEL[17]
TESTOUT[57]outCELL[10].OUT_BEL[23]CELL[39].OUT_BEL[7]
TESTOUT[58]outCELL[10].OUT_BEL[10]CELL[39].OUT_BEL[21]
TESTOUT[59]outCELL[10].OUT_BEL[2]CELL[39].OUT_BEL[15]
TESTOUT[60]outCELL[10].OUT_BEL[15]CELL[39].OUT_BEL[2]
TESTOUT[61]outCELL[10].OUT_BEL[21]CELL[39].OUT_BEL[10]
TESTOUT[62]outCELL[10].OUT_BEL[7]CELL[39].OUT_BEL[23]
TESTOUT[63]outCELL[10].OUT_BEL[17]CELL[39].OUT_BEL[18]
virtex7 CMT bel PLL_V6 attribute bits
AttributePLL[0]PLL[1]
MMCM_DRP[0] bit 0MAIN[15][29][63]-
MMCM_DRP[0] bit 1MAIN[15][28][63]-
MMCM_DRP[0] bit 2MAIN[15][29][62]-
MMCM_DRP[0] bit 3MAIN[15][28][62]-
MMCM_DRP[0] bit 4MAIN[15][29][61]-
MMCM_DRP[0] bit 5MAIN[15][28][61]-
MMCM_DRP[0] bit 6MAIN[15][29][60]-
MMCM_DRP[0] bit 7MAIN[15][28][60]-
MMCM_DRP[0] bit 8MAIN[15][29][59]-
MMCM_DRP[0] bit 9MAIN[15][28][59]-
MMCM_DRP[0] bit 10MAIN[15][29][58]-
MMCM_DRP[0] bit 11MAIN[15][28][58]-
MMCM_DRP[0] bit 12MAIN[15][29][57]-
MMCM_DRP[0] bit 13MAIN[15][28][57]-
MMCM_DRP[0] bit 14MAIN[15][29][56]-
MMCM_DRP[0] bit 15MAIN[15][28][56]-
MMCM_DRP[1] bit 0MAIN[15][29][55]-
MMCM_DRP[1] bit 1MAIN[15][28][55]-
MMCM_DRP[1] bit 2MAIN[15][29][54]-
MMCM_DRP[1] bit 3MAIN[15][28][54]-
MMCM_DRP[1] bit 4MAIN[15][29][53]-
MMCM_DRP[1] bit 5MAIN[15][28][53]-
MMCM_DRP[1] bit 6MAIN[15][29][52]-
MMCM_DRP[1] bit 7MAIN[15][28][52]-
MMCM_DRP[1] bit 8MAIN[15][29][51]-
MMCM_DRP[1] bit 9MAIN[15][28][51]-
MMCM_DRP[1] bit 10MAIN[15][29][50]-
MMCM_DRP[1] bit 11MAIN[15][28][50]-
MMCM_DRP[1] bit 12MAIN[15][29][49]-
MMCM_DRP[1] bit 13MAIN[15][28][49]-
MMCM_DRP[1] bit 14MAIN[15][29][48]-
MMCM_DRP[1] bit 15MAIN[15][28][48]-
MMCM_DRP[2] bit 0MAIN[15][29][47]-
MMCM_DRP[2] bit 1MAIN[15][28][47]-
MMCM_DRP[2] bit 2MAIN[15][29][46]-
MMCM_DRP[2] bit 3MAIN[15][28][46]-
MMCM_DRP[2] bit 4MAIN[15][29][45]-
MMCM_DRP[2] bit 5MAIN[15][28][45]-
MMCM_DRP[2] bit 6MAIN[15][29][44]-
MMCM_DRP[2] bit 7MAIN[15][28][44]-
MMCM_DRP[2] bit 8MAIN[15][29][43]-
MMCM_DRP[2] bit 9MAIN[15][28][43]-
MMCM_DRP[2] bit 10MAIN[15][29][42]-
MMCM_DRP[2] bit 11MAIN[15][28][42]-
MMCM_DRP[2] bit 12MAIN[15][29][41]-
MMCM_DRP[2] bit 13MAIN[15][28][41]-
MMCM_DRP[2] bit 14MAIN[15][29][40]-
MMCM_DRP[2] bit 15MAIN[15][28][40]-
MMCM_DRP[3] bit 0MAIN[15][29][39]-
MMCM_DRP[3] bit 1MAIN[15][28][39]-
MMCM_DRP[3] bit 2MAIN[15][29][38]-
MMCM_DRP[3] bit 3MAIN[15][28][38]-
MMCM_DRP[3] bit 4MAIN[15][29][37]-
MMCM_DRP[3] bit 5MAIN[15][28][37]-
MMCM_DRP[3] bit 6MAIN[15][29][36]-
MMCM_DRP[3] bit 7MAIN[15][28][36]-
MMCM_DRP[3] bit 8MAIN[15][29][35]-
MMCM_DRP[3] bit 9MAIN[15][28][35]-
MMCM_DRP[3] bit 10MAIN[15][29][34]-
MMCM_DRP[3] bit 11MAIN[15][28][34]-
MMCM_DRP[3] bit 12MAIN[15][29][33]-
MMCM_DRP[3] bit 13MAIN[15][28][33]-
MMCM_DRP[3] bit 14MAIN[15][29][32]-
MMCM_DRP[3] bit 15MAIN[15][28][32]-
MMCM_DRP[4] bit 0MAIN[15][29][31]-
MMCM_DRP[4] bit 1MAIN[15][28][31]-
MMCM_DRP[4] bit 2MAIN[15][29][30]-
MMCM_DRP[4] bit 3MAIN[15][28][30]-
MMCM_DRP[4] bit 4MAIN[15][29][29]-
MMCM_DRP[4] bit 5MAIN[15][28][29]-
MMCM_DRP[4] bit 6MAIN[15][29][28]-
MMCM_DRP[4] bit 7MAIN[15][28][28]-
MMCM_DRP[4] bit 8MAIN[15][29][27]-
MMCM_DRP[4] bit 9MAIN[15][28][27]-
MMCM_DRP[4] bit 10MAIN[15][29][26]-
MMCM_DRP[4] bit 11MAIN[15][28][26]-
MMCM_DRP[4] bit 12MAIN[15][29][25]-
MMCM_DRP[4] bit 13MAIN[15][28][25]-
MMCM_DRP[4] bit 14MAIN[15][29][24]-
MMCM_DRP[4] bit 15MAIN[15][28][24]-
MMCM_DRP[5] bit 0MAIN[15][29][23]-
MMCM_DRP[5] bit 1MAIN[15][28][23]-
MMCM_DRP[5] bit 2MAIN[15][29][22]-
MMCM_DRP[5] bit 3MAIN[15][28][22]-
MMCM_DRP[5] bit 4MAIN[15][29][21]-
MMCM_DRP[5] bit 5MAIN[15][28][21]-
MMCM_DRP[5] bit 6MAIN[15][29][20]-
MMCM_DRP[5] bit 7MAIN[15][28][20]-
MMCM_DRP[5] bit 8MAIN[15][29][19]-
MMCM_DRP[5] bit 9MAIN[15][28][19]-
MMCM_DRP[5] bit 10MAIN[15][29][18]-
MMCM_DRP[5] bit 11MAIN[15][28][18]-
MMCM_DRP[5] bit 12MAIN[15][29][17]-
MMCM_DRP[5] bit 13MAIN[15][28][17]-
MMCM_DRP[5] bit 14MAIN[15][29][16]-
MMCM_DRP[5] bit 15MAIN[15][28][16]-
MMCM_DRP[6] bit 0MAIN[15][29][15]-
MMCM_DRP[6] bit 1MAIN[15][28][15]-
MMCM_DRP[6] bit 2MAIN[15][29][14]-
MMCM_DRP[6] bit 3MAIN[15][28][14]-
MMCM_DRP[6] bit 4MAIN[15][29][13]-
MMCM_DRP[6] bit 5MAIN[15][28][13]-
MMCM_DRP[6] bit 6MAIN[15][29][12]-
MMCM_DRP[6] bit 7MAIN[15][28][12]-
MMCM_DRP[6] bit 8MAIN[15][29][11]-
MMCM_DRP[6] bit 9MAIN[15][28][11]-
MMCM_DRP[6] bit 10MAIN[15][29][10]-
MMCM_DRP[6] bit 11MAIN[15][28][10]-
MMCM_DRP[6] bit 12MAIN[15][29][9]-
MMCM_DRP[6] bit 13MAIN[15][28][9]-
MMCM_DRP[6] bit 14MAIN[15][29][8]-
MMCM_DRP[6] bit 15MAIN[15][28][8]-
MMCM_DRP[7] bit 0MAIN[15][29][7]-
MMCM_DRP[7] bit 1MAIN[15][28][7]-
MMCM_DRP[7] bit 2MAIN[15][29][6]-
MMCM_DRP[7] bit 3MAIN[15][28][6]-
MMCM_DRP[7] bit 4MAIN[15][29][5]-
MMCM_DRP[7] bit 5MAIN[15][28][5]-
MMCM_DRP[7] bit 6MAIN[15][29][4]-
MMCM_DRP[7] bit 7MAIN[15][28][4]-
MMCM_DRP[7] bit 8MAIN[15][29][3]-
MMCM_DRP[7] bit 9MAIN[15][28][3]-
MMCM_DRP[7] bit 10MAIN[15][29][2]-
MMCM_DRP[7] bit 11MAIN[15][28][2]-
MMCM_DRP[7] bit 12MAIN[15][29][1]-
MMCM_DRP[7] bit 13MAIN[15][28][1]-
MMCM_DRP[7] bit 14MAIN[15][29][0]-
MMCM_DRP[7] bit 15MAIN[15][28][0]-
MMCM_DRP[8] bit 0MAIN[14][29][63]-
MMCM_DRP[8] bit 1MAIN[14][28][63]-
MMCM_DRP[8] bit 2MAIN[14][29][62]-
MMCM_DRP[8] bit 3MAIN[14][28][62]-
MMCM_DRP[8] bit 4MAIN[14][29][61]-
MMCM_DRP[8] bit 5MAIN[14][28][61]-
MMCM_DRP[8] bit 6MAIN[14][29][60]-
MMCM_DRP[8] bit 7MAIN[14][28][60]-
MMCM_DRP[8] bit 8MAIN[14][29][59]-
MMCM_DRP[8] bit 9MAIN[14][28][59]-
MMCM_DRP[8] bit 10MAIN[14][29][58]-
MMCM_DRP[8] bit 11MAIN[14][28][58]-
MMCM_DRP[8] bit 12MAIN[14][29][57]-
MMCM_DRP[8] bit 13MAIN[14][28][57]-
MMCM_DRP[8] bit 14MAIN[14][29][56]-
MMCM_DRP[8] bit 15MAIN[14][28][56]-
MMCM_DRP[9] bit 0MAIN[14][29][55]-
MMCM_DRP[9] bit 1MAIN[14][28][55]-
MMCM_DRP[9] bit 2MAIN[14][29][54]-
MMCM_DRP[9] bit 3MAIN[14][28][54]-
MMCM_DRP[9] bit 4MAIN[14][29][53]-
MMCM_DRP[9] bit 5MAIN[14][28][53]-
MMCM_DRP[9] bit 6MAIN[14][29][52]-
MMCM_DRP[9] bit 7MAIN[14][28][52]-
MMCM_DRP[9] bit 8MAIN[14][29][51]-
MMCM_DRP[9] bit 9MAIN[14][28][51]-
MMCM_DRP[9] bit 10MAIN[14][29][50]-
MMCM_DRP[9] bit 11MAIN[14][28][50]-
MMCM_DRP[9] bit 12MAIN[14][29][49]-
MMCM_DRP[9] bit 13MAIN[14][28][49]-
MMCM_DRP[9] bit 14MAIN[14][29][48]-
MMCM_DRP[9] bit 15MAIN[14][28][48]-
MMCM_DRP[10] bit 0MAIN[14][29][47]-
MMCM_DRP[10] bit 1MAIN[14][28][47]-
MMCM_DRP[10] bit 2MAIN[14][29][46]-
MMCM_DRP[10] bit 3MAIN[14][28][46]-
MMCM_DRP[10] bit 4MAIN[14][29][45]-
MMCM_DRP[10] bit 5MAIN[14][28][45]-
MMCM_DRP[10] bit 6MAIN[14][29][44]-
MMCM_DRP[10] bit 7MAIN[14][28][44]-
MMCM_DRP[10] bit 8MAIN[14][29][43]-
MMCM_DRP[10] bit 9MAIN[14][28][43]-
MMCM_DRP[10] bit 10MAIN[14][29][42]-
MMCM_DRP[10] bit 11MAIN[14][28][42]-
MMCM_DRP[10] bit 12MAIN[14][29][41]-
MMCM_DRP[10] bit 13MAIN[14][28][41]-
MMCM_DRP[10] bit 14MAIN[14][29][40]-
MMCM_DRP[10] bit 15MAIN[14][28][40]-
MMCM_DRP[11] bit 0MAIN[14][29][39]-
MMCM_DRP[11] bit 1MAIN[14][28][39]-
MMCM_DRP[11] bit 2MAIN[14][29][38]-
MMCM_DRP[11] bit 3MAIN[14][28][38]-
MMCM_DRP[11] bit 4MAIN[14][29][37]-
MMCM_DRP[11] bit 5MAIN[14][28][37]-
MMCM_DRP[11] bit 6MAIN[14][29][36]-
MMCM_DRP[11] bit 7MAIN[14][28][36]-
MMCM_DRP[11] bit 8MAIN[14][29][35]-
MMCM_DRP[11] bit 9MAIN[14][28][35]-
MMCM_DRP[11] bit 10MAIN[14][29][34]-
MMCM_DRP[11] bit 11MAIN[14][28][34]-
MMCM_DRP[11] bit 12MAIN[14][29][33]-
MMCM_DRP[11] bit 13MAIN[14][28][33]-
MMCM_DRP[11] bit 14MAIN[14][29][32]-
MMCM_DRP[11] bit 15MAIN[14][28][32]-
MMCM_DRP[12] bit 0MAIN[14][29][31]-
MMCM_DRP[12] bit 1MAIN[14][28][31]-
MMCM_DRP[12] bit 2MAIN[14][29][30]-
MMCM_DRP[12] bit 3MAIN[14][28][30]-
MMCM_DRP[12] bit 4MAIN[14][29][29]-
MMCM_DRP[12] bit 5MAIN[14][28][29]-
MMCM_DRP[12] bit 6MAIN[14][29][28]-
MMCM_DRP[12] bit 7MAIN[14][28][28]-
MMCM_DRP[12] bit 8MAIN[14][29][27]-
MMCM_DRP[12] bit 9MAIN[14][28][27]-
MMCM_DRP[12] bit 10MAIN[14][29][26]-
MMCM_DRP[12] bit 11MAIN[14][28][26]-
MMCM_DRP[12] bit 12MAIN[14][29][25]-
MMCM_DRP[12] bit 13MAIN[14][28][25]-
MMCM_DRP[12] bit 14MAIN[14][29][24]-
MMCM_DRP[12] bit 15MAIN[14][28][24]-
MMCM_DRP[13] bit 0MAIN[14][29][23]-
MMCM_DRP[13] bit 1MAIN[14][28][23]-
MMCM_DRP[13] bit 2MAIN[14][29][22]-
MMCM_DRP[13] bit 3MAIN[14][28][22]-
MMCM_DRP[13] bit 4MAIN[14][29][21]-
MMCM_DRP[13] bit 5MAIN[14][28][21]-
MMCM_DRP[13] bit 6MAIN[14][29][20]-
MMCM_DRP[13] bit 7MAIN[14][28][20]-
MMCM_DRP[13] bit 8MAIN[14][29][19]-
MMCM_DRP[13] bit 9MAIN[14][28][19]-
MMCM_DRP[13] bit 10MAIN[14][29][18]-
MMCM_DRP[13] bit 11MAIN[14][28][18]-
MMCM_DRP[13] bit 12MAIN[14][29][17]-
MMCM_DRP[13] bit 13MAIN[14][28][17]-
MMCM_DRP[13] bit 14MAIN[14][29][16]-
MMCM_DRP[13] bit 15MAIN[14][28][16]-
MMCM_DRP[14] bit 0MAIN[14][29][15]-
MMCM_DRP[14] bit 1MAIN[14][28][15]-
MMCM_DRP[14] bit 2MAIN[14][29][14]-
MMCM_DRP[14] bit 3MAIN[14][28][14]-
MMCM_DRP[14] bit 4MAIN[14][29][13]-
MMCM_DRP[14] bit 5MAIN[14][28][13]-
MMCM_DRP[14] bit 6MAIN[14][29][12]-
MMCM_DRP[14] bit 7MAIN[14][28][12]-
MMCM_DRP[14] bit 8MAIN[14][29][11]-
MMCM_DRP[14] bit 9MAIN[14][28][11]-
MMCM_DRP[14] bit 10MAIN[14][29][10]-
MMCM_DRP[14] bit 11MAIN[14][28][10]-
MMCM_DRP[14] bit 12MAIN[14][29][9]-
MMCM_DRP[14] bit 13MAIN[14][28][9]-
MMCM_DRP[14] bit 14MAIN[14][29][8]-
MMCM_DRP[14] bit 15MAIN[14][28][8]-
MMCM_DRP[15] bit 0MAIN[14][29][7]-
MMCM_DRP[15] bit 1MAIN[14][28][7]-
MMCM_DRP[15] bit 2MAIN[14][29][6]-
MMCM_DRP[15] bit 3MAIN[14][28][6]-
MMCM_DRP[15] bit 4MAIN[14][29][5]-
MMCM_DRP[15] bit 5MAIN[14][28][5]-
MMCM_DRP[15] bit 6MAIN[14][29][4]-
MMCM_DRP[15] bit 7MAIN[14][28][4]-
MMCM_DRP[15] bit 8MAIN[14][29][3]-
MMCM_DRP[15] bit 9MAIN[14][28][3]-
MMCM_DRP[15] bit 10MAIN[14][29][2]-
MMCM_DRP[15] bit 11MAIN[14][28][2]-
MMCM_DRP[15] bit 12MAIN[14][29][1]-
MMCM_DRP[15] bit 13MAIN[14][28][1]-
MMCM_DRP[15] bit 14MAIN[14][29][0]-
MMCM_DRP[15] bit 15MAIN[14][28][0]-
MMCM_DRP[16] bit 0MAIN[13][29][63]-
MMCM_DRP[16] bit 1MAIN[13][28][63]-
MMCM_DRP[16] bit 2MAIN[13][29][62]-
MMCM_DRP[16] bit 3MAIN[13][28][62]-
MMCM_DRP[16] bit 4MAIN[13][29][61]-
MMCM_DRP[16] bit 5MAIN[13][28][61]-
MMCM_DRP[16] bit 6MAIN[13][29][60]-
MMCM_DRP[16] bit 7MAIN[13][28][60]-
MMCM_DRP[16] bit 8MAIN[13][29][59]-
MMCM_DRP[16] bit 9MAIN[13][28][59]-
MMCM_DRP[16] bit 10MAIN[13][29][58]-
MMCM_DRP[16] bit 11MAIN[13][28][58]-
MMCM_DRP[16] bit 12MAIN[13][29][57]-
MMCM_DRP[16] bit 13MAIN[13][28][57]-
MMCM_DRP[16] bit 14MAIN[13][29][56]-
MMCM_DRP[16] bit 15MAIN[13][28][56]-
MMCM_DRP[17] bit 0MAIN[13][29][55]-
MMCM_DRP[17] bit 1MAIN[13][28][55]-
MMCM_DRP[17] bit 2MAIN[13][29][54]-
MMCM_DRP[17] bit 3MAIN[13][28][54]-
MMCM_DRP[17] bit 4MAIN[13][29][53]-
MMCM_DRP[17] bit 5MAIN[13][28][53]-
MMCM_DRP[17] bit 6MAIN[13][29][52]-
MMCM_DRP[17] bit 7MAIN[13][28][52]-
MMCM_DRP[17] bit 8MAIN[13][29][51]-
MMCM_DRP[17] bit 9MAIN[13][28][51]-
MMCM_DRP[17] bit 10MAIN[13][29][50]-
MMCM_DRP[17] bit 11MAIN[13][28][50]-
MMCM_DRP[17] bit 12MAIN[13][29][49]-
MMCM_DRP[17] bit 13MAIN[13][28][49]-
MMCM_DRP[17] bit 14MAIN[13][29][48]-
MMCM_DRP[17] bit 15MAIN[13][28][48]-
MMCM_DRP[18] bit 0MAIN[13][29][47]-
MMCM_DRP[18] bit 1MAIN[13][28][47]-
MMCM_DRP[18] bit 2MAIN[13][29][46]-
MMCM_DRP[18] bit 3MAIN[13][28][46]-
MMCM_DRP[18] bit 4MAIN[13][29][45]-
MMCM_DRP[18] bit 5MAIN[13][28][45]-
MMCM_DRP[18] bit 6MAIN[13][29][44]-
MMCM_DRP[18] bit 7MAIN[13][28][44]-
MMCM_DRP[18] bit 8MAIN[13][29][43]-
MMCM_DRP[18] bit 9MAIN[13][28][43]-
MMCM_DRP[18] bit 10MAIN[13][29][42]-
MMCM_DRP[18] bit 11MAIN[13][28][42]-
MMCM_DRP[18] bit 12MAIN[13][29][41]-
MMCM_DRP[18] bit 13MAIN[13][28][41]-
MMCM_DRP[18] bit 14MAIN[13][29][40]-
MMCM_DRP[18] bit 15MAIN[13][28][40]-
MMCM_DRP[19] bit 0MAIN[13][29][39]-
MMCM_DRP[19] bit 1MAIN[13][28][39]-
MMCM_DRP[19] bit 2MAIN[13][29][38]-
MMCM_DRP[19] bit 3MAIN[13][28][38]-
MMCM_DRP[19] bit 4MAIN[13][29][37]-
MMCM_DRP[19] bit 5MAIN[13][28][37]-
MMCM_DRP[19] bit 6MAIN[13][29][36]-
MMCM_DRP[19] bit 7MAIN[13][28][36]-
MMCM_DRP[19] bit 8MAIN[13][29][35]-
MMCM_DRP[19] bit 9MAIN[13][28][35]-
MMCM_DRP[19] bit 10MAIN[13][29][34]-
MMCM_DRP[19] bit 11MAIN[13][28][34]-
MMCM_DRP[19] bit 12MAIN[13][29][33]-
MMCM_DRP[19] bit 13MAIN[13][28][33]-
MMCM_DRP[19] bit 14MAIN[13][29][32]-
MMCM_DRP[19] bit 15MAIN[13][28][32]-
MMCM_DRP[20] bit 0MAIN[13][29][31]-
MMCM_DRP[20] bit 1MAIN[13][28][31]-
MMCM_DRP[20] bit 2MAIN[13][29][30]-
MMCM_DRP[20] bit 3MAIN[13][28][30]-
MMCM_DRP[20] bit 4MAIN[13][29][29]-
MMCM_DRP[20] bit 5MAIN[13][28][29]-
MMCM_DRP[20] bit 6MAIN[13][29][28]-
MMCM_DRP[20] bit 7MAIN[13][28][28]-
MMCM_DRP[20] bit 8MAIN[13][29][27]-
MMCM_DRP[20] bit 9MAIN[13][28][27]-
MMCM_DRP[20] bit 10MAIN[13][29][26]-
MMCM_DRP[20] bit 11MAIN[13][28][26]-
MMCM_DRP[20] bit 12MAIN[13][29][25]-
MMCM_DRP[20] bit 13MAIN[13][28][25]-
MMCM_DRP[20] bit 14MAIN[13][29][24]-
MMCM_DRP[20] bit 15MAIN[13][28][24]-
MMCM_DRP[21] bit 0MAIN[13][29][23]-
MMCM_DRP[21] bit 1MAIN[13][28][23]-
MMCM_DRP[21] bit 2MAIN[13][29][22]-
MMCM_DRP[21] bit 3MAIN[13][28][22]-
MMCM_DRP[21] bit 4MAIN[13][29][21]-
MMCM_DRP[21] bit 5MAIN[13][28][21]-
MMCM_DRP[21] bit 6MAIN[13][29][20]-
MMCM_DRP[21] bit 7MAIN[13][28][20]-
MMCM_DRP[21] bit 8MAIN[13][29][19]-
MMCM_DRP[21] bit 9MAIN[13][28][19]-
MMCM_DRP[21] bit 10MAIN[13][29][18]-
MMCM_DRP[21] bit 11MAIN[13][28][18]-
MMCM_DRP[21] bit 12MAIN[13][29][17]-
MMCM_DRP[21] bit 13MAIN[13][28][17]-
MMCM_DRP[21] bit 14MAIN[13][29][16]-
MMCM_DRP[21] bit 15MAIN[13][28][16]-
MMCM_DRP[22] bit 0MAIN[13][29][15]-
MMCM_DRP[22] bit 1MAIN[13][28][15]-
MMCM_DRP[22] bit 2MAIN[13][29][14]-
MMCM_DRP[22] bit 3MAIN[13][28][14]-
MMCM_DRP[22] bit 4MAIN[13][29][13]-
MMCM_DRP[22] bit 5MAIN[13][28][13]-
MMCM_DRP[22] bit 6MAIN[13][29][12]-
MMCM_DRP[22] bit 7MAIN[13][28][12]-
MMCM_DRP[22] bit 8MAIN[13][29][11]-
MMCM_DRP[22] bit 9MAIN[13][28][11]-
MMCM_DRP[22] bit 10MAIN[13][29][10]-
MMCM_DRP[22] bit 11MAIN[13][28][10]-
MMCM_DRP[22] bit 12MAIN[13][29][9]-
MMCM_DRP[22] bit 13MAIN[13][28][9]-
MMCM_DRP[22] bit 14MAIN[13][29][8]-
MMCM_DRP[22] bit 15MAIN[13][28][8]-
MMCM_DRP[23] bit 0MAIN[13][29][7]-
MMCM_DRP[23] bit 1MAIN[13][28][7]-
MMCM_DRP[23] bit 2MAIN[13][29][6]-
MMCM_DRP[23] bit 3MAIN[13][28][6]-
MMCM_DRP[23] bit 4MAIN[13][29][5]-
MMCM_DRP[23] bit 5MAIN[13][28][5]-
MMCM_DRP[23] bit 6MAIN[13][29][4]-
MMCM_DRP[23] bit 7MAIN[13][28][4]-
MMCM_DRP[23] bit 8MAIN[13][29][3]-
MMCM_DRP[23] bit 9MAIN[13][28][3]-
MMCM_DRP[23] bit 10MAIN[13][29][2]-
MMCM_DRP[23] bit 11MAIN[13][28][2]-
MMCM_DRP[23] bit 12MAIN[13][29][1]-
MMCM_DRP[23] bit 13MAIN[13][28][1]-
MMCM_DRP[23] bit 14MAIN[13][29][0]-
MMCM_DRP[23] bit 15MAIN[13][28][0]-
MMCM_DRP[24] bit 0MAIN[12][29][63]-
MMCM_DRP[24] bit 1MAIN[12][28][63]-
MMCM_DRP[24] bit 2MAIN[12][29][62]-
MMCM_DRP[24] bit 3MAIN[12][28][62]-
MMCM_DRP[24] bit 4MAIN[12][29][61]-
MMCM_DRP[24] bit 5MAIN[12][28][61]-
MMCM_DRP[24] bit 6MAIN[12][29][60]-
MMCM_DRP[24] bit 7MAIN[12][28][60]-
MMCM_DRP[24] bit 8MAIN[12][29][59]-
MMCM_DRP[24] bit 9MAIN[12][28][59]-
MMCM_DRP[24] bit 10MAIN[12][29][58]-
MMCM_DRP[24] bit 11MAIN[12][28][58]-
MMCM_DRP[24] bit 12MAIN[12][29][57]-
MMCM_DRP[24] bit 13MAIN[12][28][57]-
MMCM_DRP[24] bit 14MAIN[12][29][56]-
MMCM_DRP[24] bit 15MAIN[12][28][56]-
MMCM_DRP[25] bit 0MAIN[12][29][55]-
MMCM_DRP[25] bit 1MAIN[12][28][55]-
MMCM_DRP[25] bit 2MAIN[12][29][54]-
MMCM_DRP[25] bit 3MAIN[12][28][54]-
MMCM_DRP[25] bit 4MAIN[12][29][53]-
MMCM_DRP[25] bit 5MAIN[12][28][53]-
MMCM_DRP[25] bit 6MAIN[12][29][52]-
MMCM_DRP[25] bit 7MAIN[12][28][52]-
MMCM_DRP[25] bit 8MAIN[12][29][51]-
MMCM_DRP[25] bit 9MAIN[12][28][51]-
MMCM_DRP[25] bit 10MAIN[12][29][50]-
MMCM_DRP[25] bit 11MAIN[12][28][50]-
MMCM_DRP[25] bit 12MAIN[12][29][49]-
MMCM_DRP[25] bit 13MAIN[12][28][49]-
MMCM_DRP[25] bit 14MAIN[12][29][48]-
MMCM_DRP[25] bit 15MAIN[12][28][48]-
MMCM_DRP[26] bit 0MAIN[12][29][47]-
MMCM_DRP[26] bit 1MAIN[12][28][47]-
MMCM_DRP[26] bit 2MAIN[12][29][46]-
MMCM_DRP[26] bit 3MAIN[12][28][46]-
MMCM_DRP[26] bit 4MAIN[12][29][45]-
MMCM_DRP[26] bit 5MAIN[12][28][45]-
MMCM_DRP[26] bit 6MAIN[12][29][44]-
MMCM_DRP[26] bit 7MAIN[12][28][44]-
MMCM_DRP[26] bit 8MAIN[12][29][43]-
MMCM_DRP[26] bit 9MAIN[12][28][43]-
MMCM_DRP[26] bit 10MAIN[12][29][42]-
MMCM_DRP[26] bit 11MAIN[12][28][42]-
MMCM_DRP[26] bit 12MAIN[12][29][41]-
MMCM_DRP[26] bit 13MAIN[12][28][41]-
MMCM_DRP[26] bit 14MAIN[12][29][40]-
MMCM_DRP[26] bit 15MAIN[12][28][40]-
MMCM_DRP[27] bit 0MAIN[12][29][39]-
MMCM_DRP[27] bit 1MAIN[12][28][39]-
MMCM_DRP[27] bit 2MAIN[12][29][38]-
MMCM_DRP[27] bit 3MAIN[12][28][38]-
MMCM_DRP[27] bit 4MAIN[12][29][37]-
MMCM_DRP[27] bit 5MAIN[12][28][37]-
MMCM_DRP[27] bit 6MAIN[12][29][36]-
MMCM_DRP[27] bit 7MAIN[12][28][36]-
MMCM_DRP[27] bit 8MAIN[12][29][35]-
MMCM_DRP[27] bit 9MAIN[12][28][35]-
MMCM_DRP[27] bit 10MAIN[12][29][34]-
MMCM_DRP[27] bit 11MAIN[12][28][34]-
MMCM_DRP[27] bit 12MAIN[12][29][33]-
MMCM_DRP[27] bit 13MAIN[12][28][33]-
MMCM_DRP[27] bit 14MAIN[12][29][32]-
MMCM_DRP[27] bit 15MAIN[12][28][32]-
MMCM_DRP[28] bit 0MAIN[12][29][31]-
MMCM_DRP[28] bit 1MAIN[12][28][31]-
MMCM_DRP[28] bit 2MAIN[12][29][30]-
MMCM_DRP[28] bit 3MAIN[12][28][30]-
MMCM_DRP[28] bit 4MAIN[12][29][29]-
MMCM_DRP[28] bit 5MAIN[12][28][29]-
MMCM_DRP[28] bit 6MAIN[12][29][28]-
MMCM_DRP[28] bit 7MAIN[12][28][28]-
MMCM_DRP[28] bit 8MAIN[12][29][27]-
MMCM_DRP[28] bit 9MAIN[12][28][27]-
MMCM_DRP[28] bit 10MAIN[12][29][26]-
MMCM_DRP[28] bit 11MAIN[12][28][26]-
MMCM_DRP[28] bit 12MAIN[12][29][25]-
MMCM_DRP[28] bit 13MAIN[12][28][25]-
MMCM_DRP[28] bit 14MAIN[12][29][24]-
MMCM_DRP[28] bit 15MAIN[12][28][24]-
MMCM_DRP[29] bit 0MAIN[12][29][23]-
MMCM_DRP[29] bit 1MAIN[12][28][23]-
MMCM_DRP[29] bit 2MAIN[12][29][22]-
MMCM_DRP[29] bit 3MAIN[12][28][22]-
MMCM_DRP[29] bit 4MAIN[12][29][21]-
MMCM_DRP[29] bit 5MAIN[12][28][21]-
MMCM_DRP[29] bit 6MAIN[12][29][20]-
MMCM_DRP[29] bit 7MAIN[12][28][20]-
MMCM_DRP[29] bit 8MAIN[12][29][19]-
MMCM_DRP[29] bit 9MAIN[12][28][19]-
MMCM_DRP[29] bit 10MAIN[12][29][18]-
MMCM_DRP[29] bit 11MAIN[12][28][18]-
MMCM_DRP[29] bit 12MAIN[12][29][17]-
MMCM_DRP[29] bit 13MAIN[12][28][17]-
MMCM_DRP[29] bit 14MAIN[12][29][16]-
MMCM_DRP[29] bit 15MAIN[12][28][16]-
MMCM_DRP[30] bit 0MAIN[12][29][15]-
MMCM_DRP[30] bit 1MAIN[12][28][15]-
MMCM_DRP[30] bit 2MAIN[12][29][14]-
MMCM_DRP[30] bit 3MAIN[12][28][14]-
MMCM_DRP[30] bit 4MAIN[12][29][13]-
MMCM_DRP[30] bit 5MAIN[12][28][13]-
MMCM_DRP[30] bit 6MAIN[12][29][12]-
MMCM_DRP[30] bit 7MAIN[12][28][12]-
MMCM_DRP[30] bit 8MAIN[12][29][11]-
MMCM_DRP[30] bit 9MAIN[12][28][11]-
MMCM_DRP[30] bit 10MAIN[12][29][10]-
MMCM_DRP[30] bit 11MAIN[12][28][10]-
MMCM_DRP[30] bit 12MAIN[12][29][9]-
MMCM_DRP[30] bit 13MAIN[12][28][9]-
MMCM_DRP[30] bit 14MAIN[12][29][8]-
MMCM_DRP[30] bit 15MAIN[12][28][8]-
MMCM_DRP[31] bit 0MAIN[12][29][7]-
MMCM_DRP[31] bit 1MAIN[12][28][7]-
MMCM_DRP[31] bit 2MAIN[12][29][6]-
MMCM_DRP[31] bit 3MAIN[12][28][6]-
MMCM_DRP[31] bit 4MAIN[12][29][5]-
MMCM_DRP[31] bit 5MAIN[12][28][5]-
MMCM_DRP[31] bit 6MAIN[12][29][4]-
MMCM_DRP[31] bit 7MAIN[12][28][4]-
MMCM_DRP[31] bit 8MAIN[12][29][3]-
MMCM_DRP[31] bit 9MAIN[12][28][3]-
MMCM_DRP[31] bit 10MAIN[12][29][2]-
MMCM_DRP[31] bit 11MAIN[12][28][2]-
MMCM_DRP[31] bit 12MAIN[12][29][1]-
MMCM_DRP[31] bit 13MAIN[12][28][1]-
MMCM_DRP[31] bit 14MAIN[12][29][0]-
MMCM_DRP[31] bit 15MAIN[12][28][0]-
MMCM_DRP[32] bit 0MAIN[11][29][63]-
MMCM_DRP[32] bit 1MAIN[11][28][63]-
MMCM_DRP[32] bit 2MAIN[11][29][62]-
MMCM_DRP[32] bit 3MAIN[11][28][62]-
MMCM_DRP[32] bit 4MAIN[11][29][61]-
MMCM_DRP[32] bit 5MAIN[11][28][61]-
MMCM_DRP[32] bit 6MAIN[11][29][60]-
MMCM_DRP[32] bit 7MAIN[11][28][60]-
MMCM_DRP[32] bit 8MAIN[11][29][59]-
MMCM_DRP[32] bit 9MAIN[11][28][59]-
MMCM_DRP[32] bit 10MAIN[11][29][58]-
MMCM_DRP[32] bit 11MAIN[11][28][58]-
MMCM_DRP[32] bit 12MAIN[11][29][57]-
MMCM_DRP[32] bit 13MAIN[11][28][57]-
MMCM_DRP[32] bit 14MAIN[11][29][56]-
MMCM_DRP[32] bit 15MAIN[11][28][56]-
MMCM_DRP[33] bit 0MAIN[11][29][55]-
MMCM_DRP[33] bit 1MAIN[11][28][55]-
MMCM_DRP[33] bit 2MAIN[11][29][54]-
MMCM_DRP[33] bit 3MAIN[11][28][54]-
MMCM_DRP[33] bit 4MAIN[11][29][53]-
MMCM_DRP[33] bit 5MAIN[11][28][53]-
MMCM_DRP[33] bit 6MAIN[11][29][52]-
MMCM_DRP[33] bit 7MAIN[11][28][52]-
MMCM_DRP[33] bit 8MAIN[11][29][51]-
MMCM_DRP[33] bit 9MAIN[11][28][51]-
MMCM_DRP[33] bit 10MAIN[11][29][50]-
MMCM_DRP[33] bit 11MAIN[11][28][50]-
MMCM_DRP[33] bit 12MAIN[11][29][49]-
MMCM_DRP[33] bit 13MAIN[11][28][49]-
MMCM_DRP[33] bit 14MAIN[11][29][48]-
MMCM_DRP[33] bit 15MAIN[11][28][48]-
MMCM_DRP[34] bit 0MAIN[11][29][47]-
MMCM_DRP[34] bit 1MAIN[11][28][47]-
MMCM_DRP[34] bit 2MAIN[11][29][46]-
MMCM_DRP[34] bit 3MAIN[11][28][46]-
MMCM_DRP[34] bit 4MAIN[11][29][45]-
MMCM_DRP[34] bit 5MAIN[11][28][45]-
MMCM_DRP[34] bit 6MAIN[11][29][44]-
MMCM_DRP[34] bit 7MAIN[11][28][44]-
MMCM_DRP[34] bit 8MAIN[11][29][43]-
MMCM_DRP[34] bit 9MAIN[11][28][43]-
MMCM_DRP[34] bit 10MAIN[11][29][42]-
MMCM_DRP[34] bit 11MAIN[11][28][42]-
MMCM_DRP[34] bit 12MAIN[11][29][41]-
MMCM_DRP[34] bit 13MAIN[11][28][41]-
MMCM_DRP[34] bit 14MAIN[11][29][40]-
MMCM_DRP[34] bit 15MAIN[11][28][40]-
MMCM_DRP[35] bit 0MAIN[11][29][39]-
MMCM_DRP[35] bit 1MAIN[11][28][39]-
MMCM_DRP[35] bit 2MAIN[11][29][38]-
MMCM_DRP[35] bit 3MAIN[11][28][38]-
MMCM_DRP[35] bit 4MAIN[11][29][37]-
MMCM_DRP[35] bit 5MAIN[11][28][37]-
MMCM_DRP[35] bit 6MAIN[11][29][36]-
MMCM_DRP[35] bit 7MAIN[11][28][36]-
MMCM_DRP[35] bit 8MAIN[11][29][35]-
MMCM_DRP[35] bit 9MAIN[11][28][35]-
MMCM_DRP[35] bit 10MAIN[11][29][34]-
MMCM_DRP[35] bit 11MAIN[11][28][34]-
MMCM_DRP[35] bit 12MAIN[11][29][33]-
MMCM_DRP[35] bit 13MAIN[11][28][33]-
MMCM_DRP[35] bit 14MAIN[11][29][32]-
MMCM_DRP[35] bit 15MAIN[11][28][32]-
MMCM_DRP[36] bit 0MAIN[11][29][31]-
MMCM_DRP[36] bit 1MAIN[11][28][31]-
MMCM_DRP[36] bit 2MAIN[11][29][30]-
MMCM_DRP[36] bit 3MAIN[11][28][30]-
MMCM_DRP[36] bit 4MAIN[11][29][29]-
MMCM_DRP[36] bit 5MAIN[11][28][29]-
MMCM_DRP[36] bit 6MAIN[11][29][28]-
MMCM_DRP[36] bit 7MAIN[11][28][28]-
MMCM_DRP[36] bit 8MAIN[11][29][27]-
MMCM_DRP[36] bit 9MAIN[11][28][27]-
MMCM_DRP[36] bit 10MAIN[11][29][26]-
MMCM_DRP[36] bit 11MAIN[11][28][26]-
MMCM_DRP[36] bit 12MAIN[11][29][25]-
MMCM_DRP[36] bit 13MAIN[11][28][25]-
MMCM_DRP[36] bit 14MAIN[11][29][24]-
MMCM_DRP[36] bit 15MAIN[11][28][24]-
MMCM_DRP[37] bit 0MAIN[11][29][23]-
MMCM_DRP[37] bit 1MAIN[11][28][23]-
MMCM_DRP[37] bit 2MAIN[11][29][22]-
MMCM_DRP[37] bit 3MAIN[11][28][22]-
MMCM_DRP[37] bit 4MAIN[11][29][21]-
MMCM_DRP[37] bit 5MAIN[11][28][21]-
MMCM_DRP[37] bit 6MAIN[11][29][20]-
MMCM_DRP[37] bit 7MAIN[11][28][20]-
MMCM_DRP[37] bit 8MAIN[11][29][19]-
MMCM_DRP[37] bit 9MAIN[11][28][19]-
MMCM_DRP[37] bit 10MAIN[11][29][18]-
MMCM_DRP[37] bit 11MAIN[11][28][18]-
MMCM_DRP[37] bit 12MAIN[11][29][17]-
MMCM_DRP[37] bit 13MAIN[11][28][17]-
MMCM_DRP[37] bit 14MAIN[11][29][16]-
MMCM_DRP[37] bit 15MAIN[11][28][16]-
MMCM_DRP[38] bit 0MAIN[11][29][15]-
MMCM_DRP[38] bit 1MAIN[11][28][15]-
MMCM_DRP[38] bit 2MAIN[11][29][14]-
MMCM_DRP[38] bit 3MAIN[11][28][14]-
MMCM_DRP[38] bit 4MAIN[11][29][13]-
MMCM_DRP[38] bit 5MAIN[11][28][13]-
MMCM_DRP[38] bit 6MAIN[11][29][12]-
MMCM_DRP[38] bit 7MAIN[11][28][12]-
MMCM_DRP[38] bit 8MAIN[11][29][11]-
MMCM_DRP[38] bit 9MAIN[11][28][11]-
MMCM_DRP[38] bit 10MAIN[11][29][10]-
MMCM_DRP[38] bit 11MAIN[11][28][10]-
MMCM_DRP[38] bit 12MAIN[11][29][9]-
MMCM_DRP[38] bit 13MAIN[11][28][9]-
MMCM_DRP[38] bit 14MAIN[11][29][8]-
MMCM_DRP[38] bit 15MAIN[11][28][8]-
MMCM_DRP[39] bit 0MAIN[11][29][7]-
MMCM_DRP[39] bit 1MAIN[11][28][7]-
MMCM_DRP[39] bit 2MAIN[11][29][6]-
MMCM_DRP[39] bit 3MAIN[11][28][6]-
MMCM_DRP[39] bit 4MAIN[11][29][5]-
MMCM_DRP[39] bit 5MAIN[11][28][5]-
MMCM_DRP[39] bit 6MAIN[11][29][4]-
MMCM_DRP[39] bit 7MAIN[11][28][4]-
MMCM_DRP[39] bit 8MAIN[11][29][3]-
MMCM_DRP[39] bit 9MAIN[11][28][3]-
MMCM_DRP[39] bit 10MAIN[11][29][2]-
MMCM_DRP[39] bit 11MAIN[11][28][2]-
MMCM_DRP[39] bit 12MAIN[11][29][1]-
MMCM_DRP[39] bit 13MAIN[11][28][1]-
MMCM_DRP[39] bit 14MAIN[11][29][0]-
MMCM_DRP[39] bit 15MAIN[11][28][0]-
MMCM_DRP[40] bit 0MAIN[10][29][63]-
MMCM_DRP[40] bit 1MAIN[10][28][63]-
MMCM_DRP[40] bit 2MAIN[10][29][62]-
MMCM_DRP[40] bit 3MAIN[10][28][62]-
MMCM_DRP[40] bit 4MAIN[10][29][61]-
MMCM_DRP[40] bit 5MAIN[10][28][61]-
MMCM_DRP[40] bit 6MAIN[10][29][60]-
MMCM_DRP[40] bit 7MAIN[10][28][60]-
MMCM_DRP[40] bit 8MAIN[10][29][59]-
MMCM_DRP[40] bit 9MAIN[10][28][59]-
MMCM_DRP[40] bit 10MAIN[10][29][58]-
MMCM_DRP[40] bit 11MAIN[10][28][58]-
MMCM_DRP[40] bit 12MAIN[10][29][57]-
MMCM_DRP[40] bit 13MAIN[10][28][57]-
MMCM_DRP[40] bit 14MAIN[10][29][56]-
MMCM_DRP[40] bit 15MAIN[10][28][56]-
MMCM_DRP[41] bit 0MAIN[10][29][55]-
MMCM_DRP[41] bit 1MAIN[10][28][55]-
MMCM_DRP[41] bit 2MAIN[10][29][54]-
MMCM_DRP[41] bit 3MAIN[10][28][54]-
MMCM_DRP[41] bit 4MAIN[10][29][53]-
MMCM_DRP[41] bit 5MAIN[10][28][53]-
MMCM_DRP[41] bit 6MAIN[10][29][52]-
MMCM_DRP[41] bit 7MAIN[10][28][52]-
MMCM_DRP[41] bit 8MAIN[10][29][51]-
MMCM_DRP[41] bit 9MAIN[10][28][51]-
MMCM_DRP[41] bit 10MAIN[10][29][50]-
MMCM_DRP[41] bit 11MAIN[10][28][50]-
MMCM_DRP[41] bit 12MAIN[10][29][49]-
MMCM_DRP[41] bit 13MAIN[10][28][49]-
MMCM_DRP[41] bit 14MAIN[10][29][48]-
MMCM_DRP[41] bit 15MAIN[10][28][48]-
MMCM_DRP[42] bit 0MAIN[10][29][47]-
MMCM_DRP[42] bit 1MAIN[10][28][47]-
MMCM_DRP[42] bit 2MAIN[10][29][46]-
MMCM_DRP[42] bit 3MAIN[10][28][46]-
MMCM_DRP[42] bit 4MAIN[10][29][45]-
MMCM_DRP[42] bit 5MAIN[10][28][45]-
MMCM_DRP[42] bit 6MAIN[10][29][44]-
MMCM_DRP[42] bit 7MAIN[10][28][44]-
MMCM_DRP[42] bit 8MAIN[10][29][43]-
MMCM_DRP[42] bit 9MAIN[10][28][43]-
MMCM_DRP[42] bit 10MAIN[10][29][42]-
MMCM_DRP[42] bit 11MAIN[10][28][42]-
MMCM_DRP[42] bit 12MAIN[10][29][41]-
MMCM_DRP[42] bit 13MAIN[10][28][41]-
MMCM_DRP[42] bit 14MAIN[10][29][40]-
MMCM_DRP[42] bit 15MAIN[10][28][40]-
MMCM_DRP[43] bit 0MAIN[10][29][39]-
MMCM_DRP[43] bit 1MAIN[10][28][39]-
MMCM_DRP[43] bit 2MAIN[10][29][38]-
MMCM_DRP[43] bit 3MAIN[10][28][38]-
MMCM_DRP[43] bit 4MAIN[10][29][37]-
MMCM_DRP[43] bit 5MAIN[10][28][37]-
MMCM_DRP[43] bit 6MAIN[10][29][36]-
MMCM_DRP[43] bit 7MAIN[10][28][36]-
MMCM_DRP[43] bit 8MAIN[10][29][35]-
MMCM_DRP[43] bit 9MAIN[10][28][35]-
MMCM_DRP[43] bit 10MAIN[10][29][34]-
MMCM_DRP[43] bit 11MAIN[10][28][34]-
MMCM_DRP[43] bit 12MAIN[10][29][33]-
MMCM_DRP[43] bit 13MAIN[10][28][33]-
MMCM_DRP[43] bit 14MAIN[10][29][32]-
MMCM_DRP[43] bit 15MAIN[10][28][32]-
MMCM_DRP[44] bit 0MAIN[10][29][31]-
MMCM_DRP[44] bit 1MAIN[10][28][31]-
MMCM_DRP[44] bit 2MAIN[10][29][30]-
MMCM_DRP[44] bit 3MAIN[10][28][30]-
MMCM_DRP[44] bit 4MAIN[10][29][29]-
MMCM_DRP[44] bit 5MAIN[10][28][29]-
MMCM_DRP[44] bit 6MAIN[10][29][28]-
MMCM_DRP[44] bit 7MAIN[10][28][28]-
MMCM_DRP[44] bit 8MAIN[10][29][27]-
MMCM_DRP[44] bit 9MAIN[10][28][27]-
MMCM_DRP[44] bit 10MAIN[10][29][26]-
MMCM_DRP[44] bit 11MAIN[10][28][26]-
MMCM_DRP[44] bit 12MAIN[10][29][25]-
MMCM_DRP[44] bit 13MAIN[10][28][25]-
MMCM_DRP[44] bit 14MAIN[10][29][24]-
MMCM_DRP[44] bit 15MAIN[10][28][24]-
MMCM_DRP[45] bit 0MAIN[10][29][23]-
MMCM_DRP[45] bit 1MAIN[10][28][23]-
MMCM_DRP[45] bit 2MAIN[10][29][22]-
MMCM_DRP[45] bit 3MAIN[10][28][22]-
MMCM_DRP[45] bit 4MAIN[10][29][21]-
MMCM_DRP[45] bit 5MAIN[10][28][21]-
MMCM_DRP[45] bit 6MAIN[10][29][20]-
MMCM_DRP[45] bit 7MAIN[10][28][20]-
MMCM_DRP[45] bit 8MAIN[10][29][19]-
MMCM_DRP[45] bit 9MAIN[10][28][19]-
MMCM_DRP[45] bit 10MAIN[10][29][18]-
MMCM_DRP[45] bit 11MAIN[10][28][18]-
MMCM_DRP[45] bit 12MAIN[10][29][17]-
MMCM_DRP[45] bit 13MAIN[10][28][17]-
MMCM_DRP[45] bit 14MAIN[10][29][16]-
MMCM_DRP[45] bit 15MAIN[10][28][16]-
MMCM_DRP[46] bit 0MAIN[10][29][15]-
MMCM_DRP[46] bit 1MAIN[10][28][15]-
MMCM_DRP[46] bit 2MAIN[10][29][14]-
MMCM_DRP[46] bit 3MAIN[10][28][14]-
MMCM_DRP[46] bit 4MAIN[10][29][13]-
MMCM_DRP[46] bit 5MAIN[10][28][13]-
MMCM_DRP[46] bit 6MAIN[10][29][12]-
MMCM_DRP[46] bit 7MAIN[10][28][12]-
MMCM_DRP[46] bit 8MAIN[10][29][11]-
MMCM_DRP[46] bit 9MAIN[10][28][11]-
MMCM_DRP[46] bit 10MAIN[10][29][10]-
MMCM_DRP[46] bit 11MAIN[10][28][10]-
MMCM_DRP[46] bit 12MAIN[10][29][9]-
MMCM_DRP[46] bit 13MAIN[10][28][9]-
MMCM_DRP[46] bit 14MAIN[10][29][8]-
MMCM_DRP[46] bit 15MAIN[10][28][8]-
MMCM_DRP[47] bit 0MAIN[10][29][7]-
MMCM_DRP[47] bit 1MAIN[10][28][7]-
MMCM_DRP[47] bit 2MAIN[10][29][6]-
MMCM_DRP[47] bit 3MAIN[10][28][6]-
MMCM_DRP[47] bit 4MAIN[10][29][5]-
MMCM_DRP[47] bit 5MAIN[10][28][5]-
MMCM_DRP[47] bit 6MAIN[10][29][4]-
MMCM_DRP[47] bit 7MAIN[10][28][4]-
MMCM_DRP[47] bit 8MAIN[10][29][3]-
MMCM_DRP[47] bit 9MAIN[10][28][3]-
MMCM_DRP[47] bit 10MAIN[10][29][2]-
MMCM_DRP[47] bit 11MAIN[10][28][2]-
MMCM_DRP[47] bit 12MAIN[10][29][1]-
MMCM_DRP[47] bit 13MAIN[10][28][1]-
MMCM_DRP[47] bit 14MAIN[10][29][0]-
MMCM_DRP[47] bit 15MAIN[10][28][0]-
MMCM_DRP[48] bit 0MAIN[9][29][63]-
MMCM_DRP[48] bit 1MAIN[9][28][63]-
MMCM_DRP[48] bit 2MAIN[9][29][62]-
MMCM_DRP[48] bit 3MAIN[9][28][62]-
MMCM_DRP[48] bit 4MAIN[9][29][61]-
MMCM_DRP[48] bit 5MAIN[9][28][61]-
MMCM_DRP[48] bit 6MAIN[9][29][60]-
MMCM_DRP[48] bit 7MAIN[9][28][60]-
MMCM_DRP[48] bit 8MAIN[9][29][59]-
MMCM_DRP[48] bit 9MAIN[9][28][59]-
MMCM_DRP[48] bit 10MAIN[9][29][58]-
MMCM_DRP[48] bit 11MAIN[9][28][58]-
MMCM_DRP[48] bit 12MAIN[9][29][57]-
MMCM_DRP[48] bit 13MAIN[9][28][57]-
MMCM_DRP[48] bit 14MAIN[9][29][56]-
MMCM_DRP[48] bit 15MAIN[9][28][56]-
MMCM_DRP[49] bit 0MAIN[9][29][55]-
MMCM_DRP[49] bit 1MAIN[9][28][55]-
MMCM_DRP[49] bit 2MAIN[9][29][54]-
MMCM_DRP[49] bit 3MAIN[9][28][54]-
MMCM_DRP[49] bit 4MAIN[9][29][53]-
MMCM_DRP[49] bit 5MAIN[9][28][53]-
MMCM_DRP[49] bit 6MAIN[9][29][52]-
MMCM_DRP[49] bit 7MAIN[9][28][52]-
MMCM_DRP[49] bit 8MAIN[9][29][51]-
MMCM_DRP[49] bit 9MAIN[9][28][51]-
MMCM_DRP[49] bit 10MAIN[9][29][50]-
MMCM_DRP[49] bit 11MAIN[9][28][50]-
MMCM_DRP[49] bit 12MAIN[9][29][49]-
MMCM_DRP[49] bit 13MAIN[9][28][49]-
MMCM_DRP[49] bit 14MAIN[9][29][48]-
MMCM_DRP[49] bit 15MAIN[9][28][48]-
MMCM_DRP[50] bit 0MAIN[9][29][47]-
MMCM_DRP[50] bit 1MAIN[9][28][47]-
MMCM_DRP[50] bit 2MAIN[9][29][46]-
MMCM_DRP[50] bit 3MAIN[9][28][46]-
MMCM_DRP[50] bit 4MAIN[9][29][45]-
MMCM_DRP[50] bit 5MAIN[9][28][45]-
MMCM_DRP[50] bit 6MAIN[9][29][44]-
MMCM_DRP[50] bit 7MAIN[9][28][44]-
MMCM_DRP[50] bit 8MAIN[9][29][43]-
MMCM_DRP[50] bit 9MAIN[9][28][43]-
MMCM_DRP[50] bit 10MAIN[9][29][42]-
MMCM_DRP[50] bit 11MAIN[9][28][42]-
MMCM_DRP[50] bit 12MAIN[9][29][41]-
MMCM_DRP[50] bit 13MAIN[9][28][41]-
MMCM_DRP[50] bit 14MAIN[9][29][40]-
MMCM_DRP[50] bit 15MAIN[9][28][40]-
MMCM_DRP[51] bit 0MAIN[9][29][39]-
MMCM_DRP[51] bit 1MAIN[9][28][39]-
MMCM_DRP[51] bit 2MAIN[9][29][38]-
MMCM_DRP[51] bit 3MAIN[9][28][38]-
MMCM_DRP[51] bit 4MAIN[9][29][37]-
MMCM_DRP[51] bit 5MAIN[9][28][37]-
MMCM_DRP[51] bit 6MAIN[9][29][36]-
MMCM_DRP[51] bit 7MAIN[9][28][36]-
MMCM_DRP[51] bit 8MAIN[9][29][35]-
MMCM_DRP[51] bit 9MAIN[9][28][35]-
MMCM_DRP[51] bit 10MAIN[9][29][34]-
MMCM_DRP[51] bit 11MAIN[9][28][34]-
MMCM_DRP[51] bit 12MAIN[9][29][33]-
MMCM_DRP[51] bit 13MAIN[9][28][33]-
MMCM_DRP[51] bit 14MAIN[9][29][32]-
MMCM_DRP[51] bit 15MAIN[9][28][32]-
MMCM_DRP[52] bit 0MAIN[9][29][31]-
MMCM_DRP[52] bit 1MAIN[9][28][31]-
MMCM_DRP[52] bit 2MAIN[9][29][30]-
MMCM_DRP[52] bit 3MAIN[9][28][30]-
MMCM_DRP[52] bit 4MAIN[9][29][29]-
MMCM_DRP[52] bit 5MAIN[9][28][29]-
MMCM_DRP[52] bit 6MAIN[9][29][28]-
MMCM_DRP[52] bit 7MAIN[9][28][28]-
MMCM_DRP[52] bit 8MAIN[9][29][27]-
MMCM_DRP[52] bit 9MAIN[9][28][27]-
MMCM_DRP[52] bit 10MAIN[9][29][26]-
MMCM_DRP[52] bit 11MAIN[9][28][26]-
MMCM_DRP[52] bit 12MAIN[9][29][25]-
MMCM_DRP[52] bit 13MAIN[9][28][25]-
MMCM_DRP[52] bit 14MAIN[9][29][24]-
MMCM_DRP[52] bit 15MAIN[9][28][24]-
MMCM_DRP[53] bit 0MAIN[9][29][23]-
MMCM_DRP[53] bit 1MAIN[9][28][23]-
MMCM_DRP[53] bit 2MAIN[9][29][22]-
MMCM_DRP[53] bit 3MAIN[9][28][22]-
MMCM_DRP[53] bit 4MAIN[9][29][21]-
MMCM_DRP[53] bit 5MAIN[9][28][21]-
MMCM_DRP[53] bit 6MAIN[9][29][20]-
MMCM_DRP[53] bit 7MAIN[9][28][20]-
MMCM_DRP[53] bit 8MAIN[9][29][19]-
MMCM_DRP[53] bit 9MAIN[9][28][19]-
MMCM_DRP[53] bit 10MAIN[9][29][18]-
MMCM_DRP[53] bit 11MAIN[9][28][18]-
MMCM_DRP[53] bit 12MAIN[9][29][17]-
MMCM_DRP[53] bit 13MAIN[9][28][17]-
MMCM_DRP[53] bit 14MAIN[9][29][16]-
MMCM_DRP[53] bit 15MAIN[9][28][16]-
MMCM_DRP[54] bit 0MAIN[9][29][15]-
MMCM_DRP[54] bit 1MAIN[9][28][15]-
MMCM_DRP[54] bit 2MAIN[9][29][14]-
MMCM_DRP[54] bit 3MAIN[9][28][14]-
MMCM_DRP[54] bit 4MAIN[9][29][13]-
MMCM_DRP[54] bit 5MAIN[9][28][13]-
MMCM_DRP[54] bit 6MAIN[9][29][12]-
MMCM_DRP[54] bit 7MAIN[9][28][12]-
MMCM_DRP[54] bit 8MAIN[9][29][11]-
MMCM_DRP[54] bit 9MAIN[9][28][11]-
MMCM_DRP[54] bit 10MAIN[9][29][10]-
MMCM_DRP[54] bit 11MAIN[9][28][10]-
MMCM_DRP[54] bit 12MAIN[9][29][9]-
MMCM_DRP[54] bit 13MAIN[9][28][9]-
MMCM_DRP[54] bit 14MAIN[9][29][8]-
MMCM_DRP[54] bit 15MAIN[9][28][8]-
MMCM_DRP[55] bit 0MAIN[9][29][7]-
MMCM_DRP[55] bit 1MAIN[9][28][7]-
MMCM_DRP[55] bit 2MAIN[9][29][6]-
MMCM_DRP[55] bit 3MAIN[9][28][6]-
MMCM_DRP[55] bit 4MAIN[9][29][5]-
MMCM_DRP[55] bit 5MAIN[9][28][5]-
MMCM_DRP[55] bit 6MAIN[9][29][4]-
MMCM_DRP[55] bit 7MAIN[9][28][4]-
MMCM_DRP[55] bit 8MAIN[9][29][3]-
MMCM_DRP[55] bit 9MAIN[9][28][3]-
MMCM_DRP[55] bit 10MAIN[9][29][2]-
MMCM_DRP[55] bit 11MAIN[9][28][2]-
MMCM_DRP[55] bit 12MAIN[9][29][1]-
MMCM_DRP[55] bit 13MAIN[9][28][1]-
MMCM_DRP[55] bit 14MAIN[9][29][0]-
MMCM_DRP[55] bit 15MAIN[9][28][0]-
MMCM_DRP[56] bit 0MAIN[8][29][63]-
MMCM_DRP[56] bit 1MAIN[8][28][63]-
MMCM_DRP[56] bit 2MAIN[8][29][62]-
MMCM_DRP[56] bit 3MAIN[8][28][62]-
MMCM_DRP[56] bit 4MAIN[8][29][61]-
MMCM_DRP[56] bit 5MAIN[8][28][61]-
MMCM_DRP[56] bit 6MAIN[8][29][60]-
MMCM_DRP[56] bit 7MAIN[8][28][60]-
MMCM_DRP[56] bit 8MAIN[8][29][59]-
MMCM_DRP[56] bit 9MAIN[8][28][59]-
MMCM_DRP[56] bit 10MAIN[8][29][58]-
MMCM_DRP[56] bit 11MAIN[8][28][58]-
MMCM_DRP[56] bit 12MAIN[8][29][57]-
MMCM_DRP[56] bit 13MAIN[8][28][57]-
MMCM_DRP[56] bit 14MAIN[8][29][56]-
MMCM_DRP[56] bit 15MAIN[8][28][56]-
MMCM_DRP[57] bit 0MAIN[8][29][55]-
MMCM_DRP[57] bit 1MAIN[8][28][55]-
MMCM_DRP[57] bit 2MAIN[8][29][54]-
MMCM_DRP[57] bit 3MAIN[8][28][54]-
MMCM_DRP[57] bit 4MAIN[8][29][53]-
MMCM_DRP[57] bit 5MAIN[8][28][53]-
MMCM_DRP[57] bit 6MAIN[8][29][52]-
MMCM_DRP[57] bit 7MAIN[8][28][52]-
MMCM_DRP[57] bit 8MAIN[8][29][51]-
MMCM_DRP[57] bit 9MAIN[8][28][51]-
MMCM_DRP[57] bit 10MAIN[8][29][50]-
MMCM_DRP[57] bit 11MAIN[8][28][50]-
MMCM_DRP[57] bit 12MAIN[8][29][49]-
MMCM_DRP[57] bit 13MAIN[8][28][49]-
MMCM_DRP[57] bit 14MAIN[8][29][48]-
MMCM_DRP[57] bit 15MAIN[8][28][48]-
MMCM_DRP[58] bit 0MAIN[8][29][47]-
MMCM_DRP[58] bit 1MAIN[8][28][47]-
MMCM_DRP[58] bit 2MAIN[8][29][46]-
MMCM_DRP[58] bit 3MAIN[8][28][46]-
MMCM_DRP[58] bit 4MAIN[8][29][45]-
MMCM_DRP[58] bit 5MAIN[8][28][45]-
MMCM_DRP[58] bit 6MAIN[8][29][44]-
MMCM_DRP[58] bit 7MAIN[8][28][44]-
MMCM_DRP[58] bit 8MAIN[8][29][43]-
MMCM_DRP[58] bit 9MAIN[8][28][43]-
MMCM_DRP[58] bit 10MAIN[8][29][42]-
MMCM_DRP[58] bit 11MAIN[8][28][42]-
MMCM_DRP[58] bit 12MAIN[8][29][41]-
MMCM_DRP[58] bit 13MAIN[8][28][41]-
MMCM_DRP[58] bit 14MAIN[8][29][40]-
MMCM_DRP[58] bit 15MAIN[8][28][40]-
MMCM_DRP[59] bit 0MAIN[8][29][39]-
MMCM_DRP[59] bit 1MAIN[8][28][39]-
MMCM_DRP[59] bit 2MAIN[8][29][38]-
MMCM_DRP[59] bit 3MAIN[8][28][38]-
MMCM_DRP[59] bit 4MAIN[8][29][37]-
MMCM_DRP[59] bit 5MAIN[8][28][37]-
MMCM_DRP[59] bit 6MAIN[8][29][36]-
MMCM_DRP[59] bit 7MAIN[8][28][36]-
MMCM_DRP[59] bit 8MAIN[8][29][35]-
MMCM_DRP[59] bit 9MAIN[8][28][35]-
MMCM_DRP[59] bit 10MAIN[8][29][34]-
MMCM_DRP[59] bit 11MAIN[8][28][34]-
MMCM_DRP[59] bit 12MAIN[8][29][33]-
MMCM_DRP[59] bit 13MAIN[8][28][33]-
MMCM_DRP[59] bit 14MAIN[8][29][32]-
MMCM_DRP[59] bit 15MAIN[8][28][32]-
MMCM_DRP[60] bit 0MAIN[8][29][31]-
MMCM_DRP[60] bit 1MAIN[8][28][31]-
MMCM_DRP[60] bit 2MAIN[8][29][30]-
MMCM_DRP[60] bit 3MAIN[8][28][30]-
MMCM_DRP[60] bit 4MAIN[8][29][29]-
MMCM_DRP[60] bit 5MAIN[8][28][29]-
MMCM_DRP[60] bit 6MAIN[8][29][28]-
MMCM_DRP[60] bit 7MAIN[8][28][28]-
MMCM_DRP[60] bit 8MAIN[8][29][27]-
MMCM_DRP[60] bit 9MAIN[8][28][27]-
MMCM_DRP[60] bit 10MAIN[8][29][26]-
MMCM_DRP[60] bit 11MAIN[8][28][26]-
MMCM_DRP[60] bit 12MAIN[8][29][25]-
MMCM_DRP[60] bit 13MAIN[8][28][25]-
MMCM_DRP[60] bit 14MAIN[8][29][24]-
MMCM_DRP[60] bit 15MAIN[8][28][24]-
MMCM_DRP[61] bit 0MAIN[8][29][23]-
MMCM_DRP[61] bit 1MAIN[8][28][23]-
MMCM_DRP[61] bit 2MAIN[8][29][22]-
MMCM_DRP[61] bit 3MAIN[8][28][22]-
MMCM_DRP[61] bit 4MAIN[8][29][21]-
MMCM_DRP[61] bit 5MAIN[8][28][21]-
MMCM_DRP[61] bit 6MAIN[8][29][20]-
MMCM_DRP[61] bit 7MAIN[8][28][20]-
MMCM_DRP[61] bit 8MAIN[8][29][19]-
MMCM_DRP[61] bit 9MAIN[8][28][19]-
MMCM_DRP[61] bit 10MAIN[8][29][18]-
MMCM_DRP[61] bit 11MAIN[8][28][18]-
MMCM_DRP[61] bit 12MAIN[8][29][17]-
MMCM_DRP[61] bit 13MAIN[8][28][17]-
MMCM_DRP[61] bit 14MAIN[8][29][16]-
MMCM_DRP[61] bit 15MAIN[8][28][16]-
MMCM_DRP[62] bit 0MAIN[8][29][15]-
MMCM_DRP[62] bit 1MAIN[8][28][15]-
MMCM_DRP[62] bit 2MAIN[8][29][14]-
MMCM_DRP[62] bit 3MAIN[8][28][14]-
MMCM_DRP[62] bit 4MAIN[8][29][13]-
MMCM_DRP[62] bit 5MAIN[8][28][13]-
MMCM_DRP[62] bit 6MAIN[8][29][12]-
MMCM_DRP[62] bit 7MAIN[8][28][12]-
MMCM_DRP[62] bit 8MAIN[8][29][11]-
MMCM_DRP[62] bit 9MAIN[8][28][11]-
MMCM_DRP[62] bit 10MAIN[8][29][10]-
MMCM_DRP[62] bit 11MAIN[8][28][10]-
MMCM_DRP[62] bit 12MAIN[8][29][9]-
MMCM_DRP[62] bit 13MAIN[8][28][9]-
MMCM_DRP[62] bit 14MAIN[8][29][8]-
MMCM_DRP[62] bit 15MAIN[8][28][8]-
MMCM_DRP[63] bit 0MAIN[8][29][7]-
MMCM_DRP[63] bit 1MAIN[8][28][7]-
MMCM_DRP[63] bit 2MAIN[8][29][6]-
MMCM_DRP[63] bit 3MAIN[8][28][6]-
MMCM_DRP[63] bit 4MAIN[8][29][5]-
MMCM_DRP[63] bit 5MAIN[8][28][5]-
MMCM_DRP[63] bit 6MAIN[8][29][4]-
MMCM_DRP[63] bit 7MAIN[8][28][4]-
MMCM_DRP[63] bit 8MAIN[8][29][3]-
MMCM_DRP[63] bit 9MAIN[8][28][3]-
MMCM_DRP[63] bit 10MAIN[8][29][2]-
MMCM_DRP[63] bit 11MAIN[8][28][2]-
MMCM_DRP[63] bit 12MAIN[8][29][1]-
MMCM_DRP[63] bit 13MAIN[8][28][1]-
MMCM_DRP[63] bit 14MAIN[8][29][0]-
MMCM_DRP[63] bit 15MAIN[8][28][0]-
MMCM_DRP[64] bit 0MAIN[7][29][63]-
MMCM_DRP[64] bit 1MAIN[7][28][63]-
MMCM_DRP[64] bit 2MAIN[7][29][62]-
MMCM_DRP[64] bit 3MAIN[7][28][62]-
MMCM_DRP[64] bit 4MAIN[7][29][61]-
MMCM_DRP[64] bit 5MAIN[7][28][61]-
MMCM_DRP[64] bit 6MAIN[7][29][60]-
MMCM_DRP[64] bit 7MAIN[7][28][60]-
MMCM_DRP[64] bit 8MAIN[7][29][59]-
MMCM_DRP[64] bit 9MAIN[7][28][59]-
MMCM_DRP[64] bit 10MAIN[7][29][58]-
MMCM_DRP[64] bit 11MAIN[7][28][58]-
MMCM_DRP[64] bit 12MAIN[7][29][57]-
MMCM_DRP[64] bit 13MAIN[7][28][57]-
MMCM_DRP[64] bit 14MAIN[7][29][56]-
MMCM_DRP[64] bit 15MAIN[7][28][56]-
MMCM_DRP[65] bit 0MAIN[7][29][55]-
MMCM_DRP[65] bit 1MAIN[7][28][55]-
MMCM_DRP[65] bit 2MAIN[7][29][54]-
MMCM_DRP[65] bit 3MAIN[7][28][54]-
MMCM_DRP[65] bit 4MAIN[7][29][53]-
MMCM_DRP[65] bit 5MAIN[7][28][53]-
MMCM_DRP[65] bit 6MAIN[7][29][52]-
MMCM_DRP[65] bit 7MAIN[7][28][52]-
MMCM_DRP[65] bit 8MAIN[7][29][51]-
MMCM_DRP[65] bit 9MAIN[7][28][51]-
MMCM_DRP[65] bit 10MAIN[7][29][50]-
MMCM_DRP[65] bit 11MAIN[7][28][50]-
MMCM_DRP[65] bit 12MAIN[7][29][49]-
MMCM_DRP[65] bit 13MAIN[7][28][49]-
MMCM_DRP[65] bit 14MAIN[7][29][48]-
MMCM_DRP[65] bit 15MAIN[7][28][48]-
MMCM_DRP[66] bit 0MAIN[7][29][47]-
MMCM_DRP[66] bit 1MAIN[7][28][47]-
MMCM_DRP[66] bit 2MAIN[7][29][46]-
MMCM_DRP[66] bit 3MAIN[7][28][46]-
MMCM_DRP[66] bit 4MAIN[7][29][45]-
MMCM_DRP[66] bit 5MAIN[7][28][45]-
MMCM_DRP[66] bit 6MAIN[7][29][44]-
MMCM_DRP[66] bit 7MAIN[7][28][44]-
MMCM_DRP[66] bit 8MAIN[7][29][43]-
MMCM_DRP[66] bit 9MAIN[7][28][43]-
MMCM_DRP[66] bit 10MAIN[7][29][42]-
MMCM_DRP[66] bit 11MAIN[7][28][42]-
MMCM_DRP[66] bit 12MAIN[7][29][41]-
MMCM_DRP[66] bit 13MAIN[7][28][41]-
MMCM_DRP[66] bit 14MAIN[7][29][40]-
MMCM_DRP[66] bit 15MAIN[7][28][40]-
MMCM_DRP[67] bit 0MAIN[7][29][39]-
MMCM_DRP[67] bit 1MAIN[7][28][39]-
MMCM_DRP[67] bit 2MAIN[7][29][38]-
MMCM_DRP[67] bit 3MAIN[7][28][38]-
MMCM_DRP[67] bit 4MAIN[7][29][37]-
MMCM_DRP[67] bit 5MAIN[7][28][37]-
MMCM_DRP[67] bit 6MAIN[7][29][36]-
MMCM_DRP[67] bit 7MAIN[7][28][36]-
MMCM_DRP[67] bit 8MAIN[7][29][35]-
MMCM_DRP[67] bit 9MAIN[7][28][35]-
MMCM_DRP[67] bit 10MAIN[7][29][34]-
MMCM_DRP[67] bit 11MAIN[7][28][34]-
MMCM_DRP[67] bit 12MAIN[7][29][33]-
MMCM_DRP[67] bit 13MAIN[7][28][33]-
MMCM_DRP[67] bit 14MAIN[7][29][32]-
MMCM_DRP[67] bit 15MAIN[7][28][32]-
MMCM_DRP[68] bit 0MAIN[7][29][31]-
MMCM_DRP[68] bit 1MAIN[7][28][31]-
MMCM_DRP[68] bit 2MAIN[7][29][30]-
MMCM_DRP[68] bit 3MAIN[7][28][30]-
MMCM_DRP[68] bit 4MAIN[7][29][29]-
MMCM_DRP[68] bit 5MAIN[7][28][29]-
MMCM_DRP[68] bit 6MAIN[7][29][28]-
MMCM_DRP[68] bit 7MAIN[7][28][28]-
MMCM_DRP[68] bit 8MAIN[7][29][27]-
MMCM_DRP[68] bit 9MAIN[7][28][27]-
MMCM_DRP[68] bit 10MAIN[7][29][26]-
MMCM_DRP[68] bit 11MAIN[7][28][26]-
MMCM_DRP[68] bit 12MAIN[7][29][25]-
MMCM_DRP[68] bit 13MAIN[7][28][25]-
MMCM_DRP[68] bit 14MAIN[7][29][24]-
MMCM_DRP[68] bit 15MAIN[7][28][24]-
MMCM_DRP[69] bit 0MAIN[7][29][23]-
MMCM_DRP[69] bit 1MAIN[7][28][23]-
MMCM_DRP[69] bit 2MAIN[7][29][22]-
MMCM_DRP[69] bit 3MAIN[7][28][22]-
MMCM_DRP[69] bit 4MAIN[7][29][21]-
MMCM_DRP[69] bit 5MAIN[7][28][21]-
MMCM_DRP[69] bit 6MAIN[7][29][20]-
MMCM_DRP[69] bit 7MAIN[7][28][20]-
MMCM_DRP[69] bit 8MAIN[7][29][19]-
MMCM_DRP[69] bit 9MAIN[7][28][19]-
MMCM_DRP[69] bit 10MAIN[7][29][18]-
MMCM_DRP[69] bit 11MAIN[7][28][18]-
MMCM_DRP[69] bit 12MAIN[7][29][17]-
MMCM_DRP[69] bit 13MAIN[7][28][17]-
MMCM_DRP[69] bit 14MAIN[7][29][16]-
MMCM_DRP[69] bit 15MAIN[7][28][16]-
MMCM_DRP[70] bit 0MAIN[7][29][15]-
MMCM_DRP[70] bit 1MAIN[7][28][15]-
MMCM_DRP[70] bit 2MAIN[7][29][14]-
MMCM_DRP[70] bit 3MAIN[7][28][14]-
MMCM_DRP[70] bit 4MAIN[7][29][13]-
MMCM_DRP[70] bit 5MAIN[7][28][13]-
MMCM_DRP[70] bit 6MAIN[7][29][12]-
MMCM_DRP[70] bit 7MAIN[7][28][12]-
MMCM_DRP[70] bit 8MAIN[7][29][11]-
MMCM_DRP[70] bit 9MAIN[7][28][11]-
MMCM_DRP[70] bit 10MAIN[7][29][10]-
MMCM_DRP[70] bit 11MAIN[7][28][10]-
MMCM_DRP[70] bit 12MAIN[7][29][9]-
MMCM_DRP[70] bit 13MAIN[7][28][9]-
MMCM_DRP[70] bit 14MAIN[7][29][8]-
MMCM_DRP[70] bit 15MAIN[7][28][8]-
MMCM_DRP[71] bit 0MAIN[7][29][7]-
MMCM_DRP[71] bit 1MAIN[7][28][7]-
MMCM_DRP[71] bit 2MAIN[7][29][6]-
MMCM_DRP[71] bit 3MAIN[7][28][6]-
MMCM_DRP[71] bit 4MAIN[7][29][5]-
MMCM_DRP[71] bit 5MAIN[7][28][5]-
MMCM_DRP[71] bit 6MAIN[7][29][4]-
MMCM_DRP[71] bit 7MAIN[7][28][4]-
MMCM_DRP[71] bit 8MAIN[7][29][3]-
MMCM_DRP[71] bit 9MAIN[7][28][3]-
MMCM_DRP[71] bit 10MAIN[7][29][2]-
MMCM_DRP[71] bit 11MAIN[7][28][2]-
MMCM_DRP[71] bit 12MAIN[7][29][1]-
MMCM_DRP[71] bit 13MAIN[7][28][1]-
MMCM_DRP[71] bit 14MAIN[7][29][0]-
MMCM_DRP[71] bit 15MAIN[7][28][0]-
MMCM_DRP[72] bit 0MAIN[6][29][63]-
MMCM_DRP[72] bit 1MAIN[6][28][63]-
MMCM_DRP[72] bit 2MAIN[6][29][62]-
MMCM_DRP[72] bit 3MAIN[6][28][62]-
MMCM_DRP[72] bit 4MAIN[6][29][61]-
MMCM_DRP[72] bit 5MAIN[6][28][61]-
MMCM_DRP[72] bit 6MAIN[6][29][60]-
MMCM_DRP[72] bit 7MAIN[6][28][60]-
MMCM_DRP[72] bit 8MAIN[6][29][59]-
MMCM_DRP[72] bit 9MAIN[6][28][59]-
MMCM_DRP[72] bit 10MAIN[6][29][58]-
MMCM_DRP[72] bit 11MAIN[6][28][58]-
MMCM_DRP[72] bit 12MAIN[6][29][57]-
MMCM_DRP[72] bit 13MAIN[6][28][57]-
MMCM_DRP[72] bit 14MAIN[6][29][56]-
MMCM_DRP[72] bit 15MAIN[6][28][56]-
MMCM_DRP[73] bit 0MAIN[6][29][55]-
MMCM_DRP[73] bit 1MAIN[6][28][55]-
MMCM_DRP[73] bit 2MAIN[6][29][54]-
MMCM_DRP[73] bit 3MAIN[6][28][54]-
MMCM_DRP[73] bit 4MAIN[6][29][53]-
MMCM_DRP[73] bit 5MAIN[6][28][53]-
MMCM_DRP[73] bit 6MAIN[6][29][52]-
MMCM_DRP[73] bit 7MAIN[6][28][52]-
MMCM_DRP[73] bit 8MAIN[6][29][51]-
MMCM_DRP[73] bit 9MAIN[6][28][51]-
MMCM_DRP[73] bit 10MAIN[6][29][50]-
MMCM_DRP[73] bit 11MAIN[6][28][50]-
MMCM_DRP[73] bit 12MAIN[6][29][49]-
MMCM_DRP[73] bit 13MAIN[6][28][49]-
MMCM_DRP[73] bit 14MAIN[6][29][48]-
MMCM_DRP[73] bit 15MAIN[6][28][48]-
MMCM_DRP[74] bit 0MAIN[6][29][47]-
MMCM_DRP[74] bit 1MAIN[6][28][47]-
MMCM_DRP[74] bit 2MAIN[6][29][46]-
MMCM_DRP[74] bit 3MAIN[6][28][46]-
MMCM_DRP[74] bit 4MAIN[6][29][45]-
MMCM_DRP[74] bit 5MAIN[6][28][45]-
MMCM_DRP[74] bit 6MAIN[6][29][44]-
MMCM_DRP[74] bit 7MAIN[6][28][44]-
MMCM_DRP[74] bit 8MAIN[6][29][43]-
MMCM_DRP[74] bit 9MAIN[6][28][43]-
MMCM_DRP[74] bit 10MAIN[6][29][42]-
MMCM_DRP[74] bit 11MAIN[6][28][42]-
MMCM_DRP[74] bit 12MAIN[6][29][41]-
MMCM_DRP[74] bit 13MAIN[6][28][41]-
MMCM_DRP[74] bit 14MAIN[6][29][40]-
MMCM_DRP[74] bit 15MAIN[6][28][40]-
MMCM_DRP[75] bit 0MAIN[6][29][39]-
MMCM_DRP[75] bit 1MAIN[6][28][39]-
MMCM_DRP[75] bit 2MAIN[6][29][38]-
MMCM_DRP[75] bit 3MAIN[6][28][38]-
MMCM_DRP[75] bit 4MAIN[6][29][37]-
MMCM_DRP[75] bit 5MAIN[6][28][37]-
MMCM_DRP[75] bit 6MAIN[6][29][36]-
MMCM_DRP[75] bit 7MAIN[6][28][36]-
MMCM_DRP[75] bit 8MAIN[6][29][35]-
MMCM_DRP[75] bit 9MAIN[6][28][35]-
MMCM_DRP[75] bit 10MAIN[6][29][34]-
MMCM_DRP[75] bit 11MAIN[6][28][34]-
MMCM_DRP[75] bit 12MAIN[6][29][33]-
MMCM_DRP[75] bit 13MAIN[6][28][33]-
MMCM_DRP[75] bit 14MAIN[6][29][32]-
MMCM_DRP[75] bit 15MAIN[6][28][32]-
MMCM_DRP[76] bit 0MAIN[6][29][31]-
MMCM_DRP[76] bit 1MAIN[6][28][31]-
MMCM_DRP[76] bit 2MAIN[6][29][30]-
MMCM_DRP[76] bit 3MAIN[6][28][30]-
MMCM_DRP[76] bit 4MAIN[6][29][29]-
MMCM_DRP[76] bit 5MAIN[6][28][29]-
MMCM_DRP[76] bit 6MAIN[6][29][28]-
MMCM_DRP[76] bit 7MAIN[6][28][28]-
MMCM_DRP[76] bit 8MAIN[6][29][27]-
MMCM_DRP[76] bit 9MAIN[6][28][27]-
MMCM_DRP[76] bit 10MAIN[6][29][26]-
MMCM_DRP[76] bit 11MAIN[6][28][26]-
MMCM_DRP[76] bit 12MAIN[6][29][25]-
MMCM_DRP[76] bit 13MAIN[6][28][25]-
MMCM_DRP[76] bit 14MAIN[6][29][24]-
MMCM_DRP[76] bit 15MAIN[6][28][24]-
MMCM_DRP[77] bit 0MAIN[6][29][23]-
MMCM_DRP[77] bit 1MAIN[6][28][23]-
MMCM_DRP[77] bit 2MAIN[6][29][22]-
MMCM_DRP[77] bit 3MAIN[6][28][22]-
MMCM_DRP[77] bit 4MAIN[6][29][21]-
MMCM_DRP[77] bit 5MAIN[6][28][21]-
MMCM_DRP[77] bit 6MAIN[6][29][20]-
MMCM_DRP[77] bit 7MAIN[6][28][20]-
MMCM_DRP[77] bit 8MAIN[6][29][19]-
MMCM_DRP[77] bit 9MAIN[6][28][19]-
MMCM_DRP[77] bit 10MAIN[6][29][18]-
MMCM_DRP[77] bit 11MAIN[6][28][18]-
MMCM_DRP[77] bit 12MAIN[6][29][17]-
MMCM_DRP[77] bit 13MAIN[6][28][17]-
MMCM_DRP[77] bit 14MAIN[6][29][16]-
MMCM_DRP[77] bit 15MAIN[6][28][16]-
MMCM_DRP[78] bit 0MAIN[6][29][15]-
MMCM_DRP[78] bit 1MAIN[6][28][15]-
MMCM_DRP[78] bit 2MAIN[6][29][14]-
MMCM_DRP[78] bit 3MAIN[6][28][14]-
MMCM_DRP[78] bit 4MAIN[6][29][13]-
MMCM_DRP[78] bit 5MAIN[6][28][13]-
MMCM_DRP[78] bit 6MAIN[6][29][12]-
MMCM_DRP[78] bit 7MAIN[6][28][12]-
MMCM_DRP[78] bit 8MAIN[6][29][11]-
MMCM_DRP[78] bit 9MAIN[6][28][11]-
MMCM_DRP[78] bit 10MAIN[6][29][10]-
MMCM_DRP[78] bit 11MAIN[6][28][10]-
MMCM_DRP[78] bit 12MAIN[6][29][9]-
MMCM_DRP[78] bit 13MAIN[6][28][9]-
MMCM_DRP[78] bit 14MAIN[6][29][8]-
MMCM_DRP[78] bit 15MAIN[6][28][8]-
MMCM_DRP[79] bit 0MAIN[6][29][7]-
MMCM_DRP[79] bit 1MAIN[6][28][7]-
MMCM_DRP[79] bit 2MAIN[6][29][6]-
MMCM_DRP[79] bit 3MAIN[6][28][6]-
MMCM_DRP[79] bit 4MAIN[6][29][5]-
MMCM_DRP[79] bit 5MAIN[6][28][5]-
MMCM_DRP[79] bit 6MAIN[6][29][4]-
MMCM_DRP[79] bit 7MAIN[6][28][4]-
MMCM_DRP[79] bit 8MAIN[6][29][3]-
MMCM_DRP[79] bit 9MAIN[6][28][3]-
MMCM_DRP[79] bit 10MAIN[6][29][2]-
MMCM_DRP[79] bit 11MAIN[6][28][2]-
MMCM_DRP[79] bit 12MAIN[6][29][1]-
MMCM_DRP[79] bit 13MAIN[6][28][1]-
MMCM_DRP[79] bit 14MAIN[6][29][0]-
MMCM_DRP[79] bit 15MAIN[6][28][0]-
MMCM_DRP[80] bit 0MAIN[5][29][63]-
MMCM_DRP[80] bit 1MAIN[5][28][63]-
MMCM_DRP[80] bit 2MAIN[5][29][62]-
MMCM_DRP[80] bit 3MAIN[5][28][62]-
MMCM_DRP[80] bit 4MAIN[5][29][61]-
MMCM_DRP[80] bit 5MAIN[5][28][61]-
MMCM_DRP[80] bit 6MAIN[5][29][60]-
MMCM_DRP[80] bit 7MAIN[5][28][60]-
MMCM_DRP[80] bit 8MAIN[5][29][59]-
MMCM_DRP[80] bit 9MAIN[5][28][59]-
MMCM_DRP[80] bit 10MAIN[5][29][58]-
MMCM_DRP[80] bit 11MAIN[5][28][58]-
MMCM_DRP[80] bit 12MAIN[5][29][57]-
MMCM_DRP[80] bit 13MAIN[5][28][57]-
MMCM_DRP[80] bit 14MAIN[5][29][56]-
MMCM_DRP[80] bit 15MAIN[5][28][56]-
MMCM_DRP[81] bit 0MAIN[5][29][55]-
MMCM_DRP[81] bit 1MAIN[5][28][55]-
MMCM_DRP[81] bit 2MAIN[5][29][54]-
MMCM_DRP[81] bit 3MAIN[5][28][54]-
MMCM_DRP[81] bit 4MAIN[5][29][53]-
MMCM_DRP[81] bit 5MAIN[5][28][53]-
MMCM_DRP[81] bit 6MAIN[5][29][52]-
MMCM_DRP[81] bit 7MAIN[5][28][52]-
MMCM_DRP[81] bit 8MAIN[5][29][51]-
MMCM_DRP[81] bit 9MAIN[5][28][51]-
MMCM_DRP[81] bit 10MAIN[5][29][50]-
MMCM_DRP[81] bit 11MAIN[5][28][50]-
MMCM_DRP[81] bit 12MAIN[5][29][49]-
MMCM_DRP[81] bit 13MAIN[5][28][49]-
MMCM_DRP[81] bit 14MAIN[5][29][48]-
MMCM_DRP[81] bit 15MAIN[5][28][48]-
MMCM_DRP[82] bit 0MAIN[5][29][47]-
MMCM_DRP[82] bit 1MAIN[5][28][47]-
MMCM_DRP[82] bit 2MAIN[5][29][46]-
MMCM_DRP[82] bit 3MAIN[5][28][46]-
MMCM_DRP[82] bit 4MAIN[5][29][45]-
MMCM_DRP[82] bit 5MAIN[5][28][45]-
MMCM_DRP[82] bit 6MAIN[5][29][44]-
MMCM_DRP[82] bit 7MAIN[5][28][44]-
MMCM_DRP[82] bit 8MAIN[5][29][43]-
MMCM_DRP[82] bit 9MAIN[5][28][43]-
MMCM_DRP[82] bit 10MAIN[5][29][42]-
MMCM_DRP[82] bit 11MAIN[5][28][42]-
MMCM_DRP[82] bit 12MAIN[5][29][41]-
MMCM_DRP[82] bit 13MAIN[5][28][41]-
MMCM_DRP[82] bit 14MAIN[5][29][40]-
MMCM_DRP[82] bit 15MAIN[5][28][40]-
MMCM_DRP[83] bit 0MAIN[5][29][39]-
MMCM_DRP[83] bit 1MAIN[5][28][39]-
MMCM_DRP[83] bit 2MAIN[5][29][38]-
MMCM_DRP[83] bit 3MAIN[5][28][38]-
MMCM_DRP[83] bit 4MAIN[5][29][37]-
MMCM_DRP[83] bit 5MAIN[5][28][37]-
MMCM_DRP[83] bit 6MAIN[5][29][36]-
MMCM_DRP[83] bit 7MAIN[5][28][36]-
MMCM_DRP[83] bit 8MAIN[5][29][35]-
MMCM_DRP[83] bit 9MAIN[5][28][35]-
MMCM_DRP[83] bit 10MAIN[5][29][34]-
MMCM_DRP[83] bit 11MAIN[5][28][34]-
MMCM_DRP[83] bit 12MAIN[5][29][33]-
MMCM_DRP[83] bit 13MAIN[5][28][33]-
MMCM_DRP[83] bit 14MAIN[5][29][32]-
MMCM_DRP[83] bit 15MAIN[5][28][32]-
MMCM_DRP[84] bit 0MAIN[5][29][31]-
MMCM_DRP[84] bit 1MAIN[5][28][31]-
MMCM_DRP[84] bit 2MAIN[5][29][30]-
MMCM_DRP[84] bit 3MAIN[5][28][30]-
MMCM_DRP[84] bit 4MAIN[5][29][29]-
MMCM_DRP[84] bit 5MAIN[5][28][29]-
MMCM_DRP[84] bit 6MAIN[5][29][28]-
MMCM_DRP[84] bit 7MAIN[5][28][28]-
MMCM_DRP[84] bit 8MAIN[5][29][27]-
MMCM_DRP[84] bit 9MAIN[5][28][27]-
MMCM_DRP[84] bit 10MAIN[5][29][26]-
MMCM_DRP[84] bit 11MAIN[5][28][26]-
MMCM_DRP[84] bit 12MAIN[5][29][25]-
MMCM_DRP[84] bit 13MAIN[5][28][25]-
MMCM_DRP[84] bit 14MAIN[5][29][24]-
MMCM_DRP[84] bit 15MAIN[5][28][24]-
MMCM_DRP[85] bit 0MAIN[5][29][23]-
MMCM_DRP[85] bit 1MAIN[5][28][23]-
MMCM_DRP[85] bit 2MAIN[5][29][22]-
MMCM_DRP[85] bit 3MAIN[5][28][22]-
MMCM_DRP[85] bit 4MAIN[5][29][21]-
MMCM_DRP[85] bit 5MAIN[5][28][21]-
MMCM_DRP[85] bit 6MAIN[5][29][20]-
MMCM_DRP[85] bit 7MAIN[5][28][20]-
MMCM_DRP[85] bit 8MAIN[5][29][19]-
MMCM_DRP[85] bit 9MAIN[5][28][19]-
MMCM_DRP[85] bit 10MAIN[5][29][18]-
MMCM_DRP[85] bit 11MAIN[5][28][18]-
MMCM_DRP[85] bit 12MAIN[5][29][17]-
MMCM_DRP[85] bit 13MAIN[5][28][17]-
MMCM_DRP[85] bit 14MAIN[5][29][16]-
MMCM_DRP[85] bit 15MAIN[5][28][16]-
MMCM_DRP[86] bit 0MAIN[5][29][15]-
MMCM_DRP[86] bit 1MAIN[5][28][15]-
MMCM_DRP[86] bit 2MAIN[5][29][14]-
MMCM_DRP[86] bit 3MAIN[5][28][14]-
MMCM_DRP[86] bit 4MAIN[5][29][13]-
MMCM_DRP[86] bit 5MAIN[5][28][13]-
MMCM_DRP[86] bit 6MAIN[5][29][12]-
MMCM_DRP[86] bit 7MAIN[5][28][12]-
MMCM_DRP[86] bit 8MAIN[5][29][11]-
MMCM_DRP[86] bit 9MAIN[5][28][11]-
MMCM_DRP[86] bit 10MAIN[5][29][10]-
MMCM_DRP[86] bit 11MAIN[5][28][10]-
MMCM_DRP[86] bit 12MAIN[5][29][9]-
MMCM_DRP[86] bit 13MAIN[5][28][9]-
MMCM_DRP[86] bit 14MAIN[5][29][8]-
MMCM_DRP[86] bit 15MAIN[5][28][8]-
MMCM_DRP[87] bit 0MAIN[5][29][7]-
MMCM_DRP[87] bit 1MAIN[5][28][7]-
MMCM_DRP[87] bit 2MAIN[5][29][6]-
MMCM_DRP[87] bit 3MAIN[5][28][6]-
MMCM_DRP[87] bit 4MAIN[5][29][5]-
MMCM_DRP[87] bit 5MAIN[5][28][5]-
MMCM_DRP[87] bit 6MAIN[5][29][4]-
MMCM_DRP[87] bit 7MAIN[5][28][4]-
MMCM_DRP[87] bit 8MAIN[5][29][3]-
MMCM_DRP[87] bit 9MAIN[5][28][3]-
MMCM_DRP[87] bit 10MAIN[5][29][2]-
MMCM_DRP[87] bit 11MAIN[5][28][2]-
MMCM_DRP[87] bit 12MAIN[5][29][1]-
MMCM_DRP[87] bit 13MAIN[5][28][1]-
MMCM_DRP[87] bit 14MAIN[5][29][0]-
MMCM_DRP[87] bit 15MAIN[5][28][0]-
MMCM_DRP[88] bit 0MAIN[4][29][63]-
MMCM_DRP[88] bit 1MAIN[4][28][63]-
MMCM_DRP[88] bit 2MAIN[4][29][62]-
MMCM_DRP[88] bit 3MAIN[4][28][62]-
MMCM_DRP[88] bit 4MAIN[4][29][61]-
MMCM_DRP[88] bit 5MAIN[4][28][61]-
MMCM_DRP[88] bit 6MAIN[4][29][60]-
MMCM_DRP[88] bit 7MAIN[4][28][60]-
MMCM_DRP[88] bit 8MAIN[4][29][59]-
MMCM_DRP[88] bit 9MAIN[4][28][59]-
MMCM_DRP[88] bit 10MAIN[4][29][58]-
MMCM_DRP[88] bit 11MAIN[4][28][58]-
MMCM_DRP[88] bit 12MAIN[4][29][57]-
MMCM_DRP[88] bit 13MAIN[4][28][57]-
MMCM_DRP[88] bit 14MAIN[4][29][56]-
MMCM_DRP[88] bit 15MAIN[4][28][56]-
MMCM_DRP[89] bit 0MAIN[4][29][55]-
MMCM_DRP[89] bit 1MAIN[4][28][55]-
MMCM_DRP[89] bit 2MAIN[4][29][54]-
MMCM_DRP[89] bit 3MAIN[4][28][54]-
MMCM_DRP[89] bit 4MAIN[4][29][53]-
MMCM_DRP[89] bit 5MAIN[4][28][53]-
MMCM_DRP[89] bit 6MAIN[4][29][52]-
MMCM_DRP[89] bit 7MAIN[4][28][52]-
MMCM_DRP[89] bit 8MAIN[4][29][51]-
MMCM_DRP[89] bit 9MAIN[4][28][51]-
MMCM_DRP[89] bit 10MAIN[4][29][50]-
MMCM_DRP[89] bit 11MAIN[4][28][50]-
MMCM_DRP[89] bit 12MAIN[4][29][49]-
MMCM_DRP[89] bit 13MAIN[4][28][49]-
MMCM_DRP[89] bit 14MAIN[4][29][48]-
MMCM_DRP[89] bit 15MAIN[4][28][48]-
MMCM_DRP[90] bit 0MAIN[4][29][47]-
MMCM_DRP[90] bit 1MAIN[4][28][47]-
MMCM_DRP[90] bit 2MAIN[4][29][46]-
MMCM_DRP[90] bit 3MAIN[4][28][46]-
MMCM_DRP[90] bit 4MAIN[4][29][45]-
MMCM_DRP[90] bit 5MAIN[4][28][45]-
MMCM_DRP[90] bit 6MAIN[4][29][44]-
MMCM_DRP[90] bit 7MAIN[4][28][44]-
MMCM_DRP[90] bit 8MAIN[4][29][43]-
MMCM_DRP[90] bit 9MAIN[4][28][43]-
MMCM_DRP[90] bit 10MAIN[4][29][42]-
MMCM_DRP[90] bit 11MAIN[4][28][42]-
MMCM_DRP[90] bit 12MAIN[4][29][41]-
MMCM_DRP[90] bit 13MAIN[4][28][41]-
MMCM_DRP[90] bit 14MAIN[4][29][40]-
MMCM_DRP[90] bit 15MAIN[4][28][40]-
MMCM_DRP[91] bit 0MAIN[4][29][39]-
MMCM_DRP[91] bit 1MAIN[4][28][39]-
MMCM_DRP[91] bit 2MAIN[4][29][38]-
MMCM_DRP[91] bit 3MAIN[4][28][38]-
MMCM_DRP[91] bit 4MAIN[4][29][37]-
MMCM_DRP[91] bit 5MAIN[4][28][37]-
MMCM_DRP[91] bit 6MAIN[4][29][36]-
MMCM_DRP[91] bit 7MAIN[4][28][36]-
MMCM_DRP[91] bit 8MAIN[4][29][35]-
MMCM_DRP[91] bit 9MAIN[4][28][35]-
MMCM_DRP[91] bit 10MAIN[4][29][34]-
MMCM_DRP[91] bit 11MAIN[4][28][34]-
MMCM_DRP[91] bit 12MAIN[4][29][33]-
MMCM_DRP[91] bit 13MAIN[4][28][33]-
MMCM_DRP[91] bit 14MAIN[4][29][32]-
MMCM_DRP[91] bit 15MAIN[4][28][32]-
MMCM_DRP[92] bit 0MAIN[4][29][31]-
MMCM_DRP[92] bit 1MAIN[4][28][31]-
MMCM_DRP[92] bit 2MAIN[4][29][30]-
MMCM_DRP[92] bit 3MAIN[4][28][30]-
MMCM_DRP[92] bit 4MAIN[4][29][29]-
MMCM_DRP[92] bit 5MAIN[4][28][29]-
MMCM_DRP[92] bit 6MAIN[4][29][28]-
MMCM_DRP[92] bit 7MAIN[4][28][28]-
MMCM_DRP[92] bit 8MAIN[4][29][27]-
MMCM_DRP[92] bit 9MAIN[4][28][27]-
MMCM_DRP[92] bit 10MAIN[4][29][26]-
MMCM_DRP[92] bit 11MAIN[4][28][26]-
MMCM_DRP[92] bit 12MAIN[4][29][25]-
MMCM_DRP[92] bit 13MAIN[4][28][25]-
MMCM_DRP[92] bit 14MAIN[4][29][24]-
MMCM_DRP[92] bit 15MAIN[4][28][24]-
MMCM_DRP[93] bit 0MAIN[4][29][23]-
MMCM_DRP[93] bit 1MAIN[4][28][23]-
MMCM_DRP[93] bit 2MAIN[4][29][22]-
MMCM_DRP[93] bit 3MAIN[4][28][22]-
MMCM_DRP[93] bit 4MAIN[4][29][21]-
MMCM_DRP[93] bit 5MAIN[4][28][21]-
MMCM_DRP[93] bit 6MAIN[4][29][20]-
MMCM_DRP[93] bit 7MAIN[4][28][20]-
MMCM_DRP[93] bit 8MAIN[4][29][19]-
MMCM_DRP[93] bit 9MAIN[4][28][19]-
MMCM_DRP[93] bit 10MAIN[4][29][18]-
MMCM_DRP[93] bit 11MAIN[4][28][18]-
MMCM_DRP[93] bit 12MAIN[4][29][17]-
MMCM_DRP[93] bit 13MAIN[4][28][17]-
MMCM_DRP[93] bit 14MAIN[4][29][16]-
MMCM_DRP[93] bit 15MAIN[4][28][16]-
MMCM_DRP[94] bit 0MAIN[4][29][15]-
MMCM_DRP[94] bit 1MAIN[4][28][15]-
MMCM_DRP[94] bit 2MAIN[4][29][14]-
MMCM_DRP[94] bit 3MAIN[4][28][14]-
MMCM_DRP[94] bit 4MAIN[4][29][13]-
MMCM_DRP[94] bit 5MAIN[4][28][13]-
MMCM_DRP[94] bit 6MAIN[4][29][12]-
MMCM_DRP[94] bit 7MAIN[4][28][12]-
MMCM_DRP[94] bit 8MAIN[4][29][11]-
MMCM_DRP[94] bit 9MAIN[4][28][11]-
MMCM_DRP[94] bit 10MAIN[4][29][10]-
MMCM_DRP[94] bit 11MAIN[4][28][10]-
MMCM_DRP[94] bit 12MAIN[4][29][9]-
MMCM_DRP[94] bit 13MAIN[4][28][9]-
MMCM_DRP[94] bit 14MAIN[4][29][8]-
MMCM_DRP[94] bit 15MAIN[4][28][8]-
MMCM_DRP[95] bit 0MAIN[4][29][7]-
MMCM_DRP[95] bit 1MAIN[4][28][7]-
MMCM_DRP[95] bit 2MAIN[4][29][6]-
MMCM_DRP[95] bit 3MAIN[4][28][6]-
MMCM_DRP[95] bit 4MAIN[4][29][5]-
MMCM_DRP[95] bit 5MAIN[4][28][5]-
MMCM_DRP[95] bit 6MAIN[4][29][4]-
MMCM_DRP[95] bit 7MAIN[4][28][4]-
MMCM_DRP[95] bit 8MAIN[4][29][3]-
MMCM_DRP[95] bit 9MAIN[4][28][3]-
MMCM_DRP[95] bit 10MAIN[4][29][2]-
MMCM_DRP[95] bit 11MAIN[4][28][2]-
MMCM_DRP[95] bit 12MAIN[4][29][1]-
MMCM_DRP[95] bit 13MAIN[4][28][1]-
MMCM_DRP[95] bit 14MAIN[4][29][0]-
MMCM_DRP[95] bit 15MAIN[4][28][0]-
MMCM_DRP[96] bit 0MAIN[3][29][63]-
MMCM_DRP[96] bit 1MAIN[3][28][63]-
MMCM_DRP[96] bit 2MAIN[3][29][62]-
MMCM_DRP[96] bit 3MAIN[3][28][62]-
MMCM_DRP[96] bit 4MAIN[3][29][61]-
MMCM_DRP[96] bit 5MAIN[3][28][61]-
MMCM_DRP[96] bit 6MAIN[3][29][60]-
MMCM_DRP[96] bit 7MAIN[3][28][60]-
MMCM_DRP[96] bit 8MAIN[3][29][59]-
MMCM_DRP[96] bit 9MAIN[3][28][59]-
MMCM_DRP[96] bit 10MAIN[3][29][58]-
MMCM_DRP[96] bit 11MAIN[3][28][58]-
MMCM_DRP[96] bit 12MAIN[3][29][57]-
MMCM_DRP[96] bit 13MAIN[3][28][57]-
MMCM_DRP[96] bit 14MAIN[3][29][56]-
MMCM_DRP[96] bit 15MAIN[3][28][56]-
MMCM_DRP[97] bit 0MAIN[3][29][55]-
MMCM_DRP[97] bit 1MAIN[3][28][55]-
MMCM_DRP[97] bit 2MAIN[3][29][54]-
MMCM_DRP[97] bit 3MAIN[3][28][54]-
MMCM_DRP[97] bit 4MAIN[3][29][53]-
MMCM_DRP[97] bit 5MAIN[3][28][53]-
MMCM_DRP[97] bit 6MAIN[3][29][52]-
MMCM_DRP[97] bit 7MAIN[3][28][52]-
MMCM_DRP[97] bit 8MAIN[3][29][51]-
MMCM_DRP[97] bit 9MAIN[3][28][51]-
MMCM_DRP[97] bit 10MAIN[3][29][50]-
MMCM_DRP[97] bit 11MAIN[3][28][50]-
MMCM_DRP[97] bit 12MAIN[3][29][49]-
MMCM_DRP[97] bit 13MAIN[3][28][49]-
MMCM_DRP[97] bit 14MAIN[3][29][48]-
MMCM_DRP[97] bit 15MAIN[3][28][48]-
MMCM_DRP[98] bit 0MAIN[3][29][47]-
MMCM_DRP[98] bit 1MAIN[3][28][47]-
MMCM_DRP[98] bit 2MAIN[3][29][46]-
MMCM_DRP[98] bit 3MAIN[3][28][46]-
MMCM_DRP[98] bit 4MAIN[3][29][45]-
MMCM_DRP[98] bit 5MAIN[3][28][45]-
MMCM_DRP[98] bit 6MAIN[3][29][44]-
MMCM_DRP[98] bit 7MAIN[3][28][44]-
MMCM_DRP[98] bit 8MAIN[3][29][43]-
MMCM_DRP[98] bit 9MAIN[3][28][43]-
MMCM_DRP[98] bit 10MAIN[3][29][42]-
MMCM_DRP[98] bit 11MAIN[3][28][42]-
MMCM_DRP[98] bit 12MAIN[3][29][41]-
MMCM_DRP[98] bit 13MAIN[3][28][41]-
MMCM_DRP[98] bit 14MAIN[3][29][40]-
MMCM_DRP[98] bit 15MAIN[3][28][40]-
MMCM_DRP[99] bit 0MAIN[3][29][39]-
MMCM_DRP[99] bit 1MAIN[3][28][39]-
MMCM_DRP[99] bit 2MAIN[3][29][38]-
MMCM_DRP[99] bit 3MAIN[3][28][38]-
MMCM_DRP[99] bit 4MAIN[3][29][37]-
MMCM_DRP[99] bit 5MAIN[3][28][37]-
MMCM_DRP[99] bit 6MAIN[3][29][36]-
MMCM_DRP[99] bit 7MAIN[3][28][36]-
MMCM_DRP[99] bit 8MAIN[3][29][35]-
MMCM_DRP[99] bit 9MAIN[3][28][35]-
MMCM_DRP[99] bit 10MAIN[3][29][34]-
MMCM_DRP[99] bit 11MAIN[3][28][34]-
MMCM_DRP[99] bit 12MAIN[3][29][33]-
MMCM_DRP[99] bit 13MAIN[3][28][33]-
MMCM_DRP[99] bit 14MAIN[3][29][32]-
MMCM_DRP[99] bit 15MAIN[3][28][32]-
MMCM_DRP[100] bit 0MAIN[3][29][31]-
MMCM_DRP[100] bit 1MAIN[3][28][31]-
MMCM_DRP[100] bit 2MAIN[3][29][30]-
MMCM_DRP[100] bit 3MAIN[3][28][30]-
MMCM_DRP[100] bit 4MAIN[3][29][29]-
MMCM_DRP[100] bit 5MAIN[3][28][29]-
MMCM_DRP[100] bit 6MAIN[3][29][28]-
MMCM_DRP[100] bit 7MAIN[3][28][28]-
MMCM_DRP[100] bit 8MAIN[3][29][27]-
MMCM_DRP[100] bit 9MAIN[3][28][27]-
MMCM_DRP[100] bit 10MAIN[3][29][26]-
MMCM_DRP[100] bit 11MAIN[3][28][26]-
MMCM_DRP[100] bit 12MAIN[3][29][25]-
MMCM_DRP[100] bit 13MAIN[3][28][25]-
MMCM_DRP[100] bit 14MAIN[3][29][24]-
MMCM_DRP[100] bit 15MAIN[3][28][24]-
MMCM_DRP[101] bit 0MAIN[3][29][23]-
MMCM_DRP[101] bit 1MAIN[3][28][23]-
MMCM_DRP[101] bit 2MAIN[3][29][22]-
MMCM_DRP[101] bit 3MAIN[3][28][22]-
MMCM_DRP[101] bit 4MAIN[3][29][21]-
MMCM_DRP[101] bit 5MAIN[3][28][21]-
MMCM_DRP[101] bit 6MAIN[3][29][20]-
MMCM_DRP[101] bit 7MAIN[3][28][20]-
MMCM_DRP[101] bit 8MAIN[3][29][19]-
MMCM_DRP[101] bit 9MAIN[3][28][19]-
MMCM_DRP[101] bit 10MAIN[3][29][18]-
MMCM_DRP[101] bit 11MAIN[3][28][18]-
MMCM_DRP[101] bit 12MAIN[3][29][17]-
MMCM_DRP[101] bit 13MAIN[3][28][17]-
MMCM_DRP[101] bit 14MAIN[3][29][16]-
MMCM_DRP[101] bit 15MAIN[3][28][16]-
MMCM_DRP[102] bit 0MAIN[3][29][15]-
MMCM_DRP[102] bit 1MAIN[3][28][15]-
MMCM_DRP[102] bit 2MAIN[3][29][14]-
MMCM_DRP[102] bit 3MAIN[3][28][14]-
MMCM_DRP[102] bit 4MAIN[3][29][13]-
MMCM_DRP[102] bit 5MAIN[3][28][13]-
MMCM_DRP[102] bit 6MAIN[3][29][12]-
MMCM_DRP[102] bit 7MAIN[3][28][12]-
MMCM_DRP[102] bit 8MAIN[3][29][11]-
MMCM_DRP[102] bit 9MAIN[3][28][11]-
MMCM_DRP[102] bit 10MAIN[3][29][10]-
MMCM_DRP[102] bit 11MAIN[3][28][10]-
MMCM_DRP[102] bit 12MAIN[3][29][9]-
MMCM_DRP[102] bit 13MAIN[3][28][9]-
MMCM_DRP[102] bit 14MAIN[3][29][8]-
MMCM_DRP[102] bit 15MAIN[3][28][8]-
MMCM_DRP[103] bit 0MAIN[3][29][7]-
MMCM_DRP[103] bit 1MAIN[3][28][7]-
MMCM_DRP[103] bit 2MAIN[3][29][6]-
MMCM_DRP[103] bit 3MAIN[3][28][6]-
MMCM_DRP[103] bit 4MAIN[3][29][5]-
MMCM_DRP[103] bit 5MAIN[3][28][5]-
MMCM_DRP[103] bit 6MAIN[3][29][4]-
MMCM_DRP[103] bit 7MAIN[3][28][4]-
MMCM_DRP[103] bit 8MAIN[3][29][3]-
MMCM_DRP[103] bit 9MAIN[3][28][3]-
MMCM_DRP[103] bit 10MAIN[3][29][2]-
MMCM_DRP[103] bit 11MAIN[3][28][2]-
MMCM_DRP[103] bit 12MAIN[3][29][1]-
MMCM_DRP[103] bit 13MAIN[3][28][1]-
MMCM_DRP[103] bit 14MAIN[3][29][0]-
MMCM_DRP[103] bit 15MAIN[3][28][0]-
MMCM_DRP[104] bit 0MAIN[2][29][63]-
MMCM_DRP[104] bit 1MAIN[2][28][63]-
MMCM_DRP[104] bit 2MAIN[2][29][62]-
MMCM_DRP[104] bit 3MAIN[2][28][62]-
MMCM_DRP[104] bit 4MAIN[2][29][61]-
MMCM_DRP[104] bit 5MAIN[2][28][61]-
MMCM_DRP[104] bit 6MAIN[2][29][60]-
MMCM_DRP[104] bit 7MAIN[2][28][60]-
MMCM_DRP[104] bit 8MAIN[2][29][59]-
MMCM_DRP[104] bit 9MAIN[2][28][59]-
MMCM_DRP[104] bit 10MAIN[2][29][58]-
MMCM_DRP[104] bit 11MAIN[2][28][58]-
MMCM_DRP[104] bit 12MAIN[2][29][57]-
MMCM_DRP[104] bit 13MAIN[2][28][57]-
MMCM_DRP[104] bit 14MAIN[2][29][56]-
MMCM_DRP[104] bit 15MAIN[2][28][56]-
MMCM_DRP[105] bit 0MAIN[2][29][55]-
MMCM_DRP[105] bit 1MAIN[2][28][55]-
MMCM_DRP[105] bit 2MAIN[2][29][54]-
MMCM_DRP[105] bit 3MAIN[2][28][54]-
MMCM_DRP[105] bit 4MAIN[2][29][53]-
MMCM_DRP[105] bit 5MAIN[2][28][53]-
MMCM_DRP[105] bit 6MAIN[2][29][52]-
MMCM_DRP[105] bit 7MAIN[2][28][52]-
MMCM_DRP[105] bit 8MAIN[2][29][51]-
MMCM_DRP[105] bit 9MAIN[2][28][51]-
MMCM_DRP[105] bit 10MAIN[2][29][50]-
MMCM_DRP[105] bit 11MAIN[2][28][50]-
MMCM_DRP[105] bit 12MAIN[2][29][49]-
MMCM_DRP[105] bit 13MAIN[2][28][49]-
MMCM_DRP[105] bit 14MAIN[2][29][48]-
MMCM_DRP[105] bit 15MAIN[2][28][48]-
MMCM_DRP[106] bit 0MAIN[2][29][47]-
MMCM_DRP[106] bit 1MAIN[2][28][47]-
MMCM_DRP[106] bit 2MAIN[2][29][46]-
MMCM_DRP[106] bit 3MAIN[2][28][46]-
MMCM_DRP[106] bit 4MAIN[2][29][45]-
MMCM_DRP[106] bit 5MAIN[2][28][45]-
MMCM_DRP[106] bit 6MAIN[2][29][44]-
MMCM_DRP[106] bit 7MAIN[2][28][44]-
MMCM_DRP[106] bit 8MAIN[2][29][43]-
MMCM_DRP[106] bit 9MAIN[2][28][43]-
MMCM_DRP[106] bit 10MAIN[2][29][42]-
MMCM_DRP[106] bit 11MAIN[2][28][42]-
MMCM_DRP[106] bit 12MAIN[2][29][41]-
MMCM_DRP[106] bit 13MAIN[2][28][41]-
MMCM_DRP[106] bit 14MAIN[2][29][40]-
MMCM_DRP[106] bit 15MAIN[2][28][40]-
MMCM_DRP[107] bit 0MAIN[2][29][39]-
MMCM_DRP[107] bit 1MAIN[2][28][39]-
MMCM_DRP[107] bit 2MAIN[2][29][38]-
MMCM_DRP[107] bit 3MAIN[2][28][38]-
MMCM_DRP[107] bit 4MAIN[2][29][37]-
MMCM_DRP[107] bit 5MAIN[2][28][37]-
MMCM_DRP[107] bit 6MAIN[2][29][36]-
MMCM_DRP[107] bit 7MAIN[2][28][36]-
MMCM_DRP[107] bit 8MAIN[2][29][35]-
MMCM_DRP[107] bit 9MAIN[2][28][35]-
MMCM_DRP[107] bit 10MAIN[2][29][34]-
MMCM_DRP[107] bit 11MAIN[2][28][34]-
MMCM_DRP[107] bit 12MAIN[2][29][33]-
MMCM_DRP[107] bit 13MAIN[2][28][33]-
MMCM_DRP[107] bit 14MAIN[2][29][32]-
MMCM_DRP[107] bit 15MAIN[2][28][32]-
MMCM_DRP[108] bit 0MAIN[2][29][31]-
MMCM_DRP[108] bit 1MAIN[2][28][31]-
MMCM_DRP[108] bit 2MAIN[2][29][30]-
MMCM_DRP[108] bit 3MAIN[2][28][30]-
MMCM_DRP[108] bit 4MAIN[2][29][29]-
MMCM_DRP[108] bit 5MAIN[2][28][29]-
MMCM_DRP[108] bit 6MAIN[2][29][28]-
MMCM_DRP[108] bit 7MAIN[2][28][28]-
MMCM_DRP[108] bit 8MAIN[2][29][27]-
MMCM_DRP[108] bit 9MAIN[2][28][27]-
MMCM_DRP[108] bit 10MAIN[2][29][26]-
MMCM_DRP[108] bit 11MAIN[2][28][26]-
MMCM_DRP[108] bit 12MAIN[2][29][25]-
MMCM_DRP[108] bit 13MAIN[2][28][25]-
MMCM_DRP[108] bit 14MAIN[2][29][24]-
MMCM_DRP[108] bit 15MAIN[2][28][24]-
MMCM_DRP[109] bit 0MAIN[2][29][23]-
MMCM_DRP[109] bit 1MAIN[2][28][23]-
MMCM_DRP[109] bit 2MAIN[2][29][22]-
MMCM_DRP[109] bit 3MAIN[2][28][22]-
MMCM_DRP[109] bit 4MAIN[2][29][21]-
MMCM_DRP[109] bit 5MAIN[2][28][21]-
MMCM_DRP[109] bit 6MAIN[2][29][20]-
MMCM_DRP[109] bit 7MAIN[2][28][20]-
MMCM_DRP[109] bit 8MAIN[2][29][19]-
MMCM_DRP[109] bit 9MAIN[2][28][19]-
MMCM_DRP[109] bit 10MAIN[2][29][18]-
MMCM_DRP[109] bit 11MAIN[2][28][18]-
MMCM_DRP[109] bit 12MAIN[2][29][17]-
MMCM_DRP[109] bit 13MAIN[2][28][17]-
MMCM_DRP[109] bit 14MAIN[2][29][16]-
MMCM_DRP[109] bit 15MAIN[2][28][16]-
MMCM_DRP[110] bit 0MAIN[2][29][15]-
MMCM_DRP[110] bit 1MAIN[2][28][15]-
MMCM_DRP[110] bit 2MAIN[2][29][14]-
MMCM_DRP[110] bit 3MAIN[2][28][14]-
MMCM_DRP[110] bit 4MAIN[2][29][13]-
MMCM_DRP[110] bit 5MAIN[2][28][13]-
MMCM_DRP[110] bit 6MAIN[2][29][12]-
MMCM_DRP[110] bit 7MAIN[2][28][12]-
MMCM_DRP[110] bit 8MAIN[2][29][11]-
MMCM_DRP[110] bit 9MAIN[2][28][11]-
MMCM_DRP[110] bit 10MAIN[2][29][10]-
MMCM_DRP[110] bit 11MAIN[2][28][10]-
MMCM_DRP[110] bit 12MAIN[2][29][9]-
MMCM_DRP[110] bit 13MAIN[2][28][9]-
MMCM_DRP[110] bit 14MAIN[2][29][8]-
MMCM_DRP[110] bit 15MAIN[2][28][8]-
MMCM_DRP[111] bit 0MAIN[2][29][7]-
MMCM_DRP[111] bit 1MAIN[2][28][7]-
MMCM_DRP[111] bit 2MAIN[2][29][6]-
MMCM_DRP[111] bit 3MAIN[2][28][6]-
MMCM_DRP[111] bit 4MAIN[2][29][5]-
MMCM_DRP[111] bit 5MAIN[2][28][5]-
MMCM_DRP[111] bit 6MAIN[2][29][4]-
MMCM_DRP[111] bit 7MAIN[2][28][4]-
MMCM_DRP[111] bit 8MAIN[2][29][3]-
MMCM_DRP[111] bit 9MAIN[2][28][3]-
MMCM_DRP[111] bit 10MAIN[2][29][2]-
MMCM_DRP[111] bit 11MAIN[2][28][2]-
MMCM_DRP[111] bit 12MAIN[2][29][1]-
MMCM_DRP[111] bit 13MAIN[2][28][1]-
MMCM_DRP[111] bit 14MAIN[2][29][0]-
MMCM_DRP[111] bit 15MAIN[2][28][0]-
MMCM_DRP[112] bit 0MAIN[1][29][63]-
MMCM_DRP[112] bit 1MAIN[1][28][63]-
MMCM_DRP[112] bit 2MAIN[1][29][62]-
MMCM_DRP[112] bit 3MAIN[1][28][62]-
MMCM_DRP[112] bit 4MAIN[1][29][61]-
MMCM_DRP[112] bit 5MAIN[1][28][61]-
MMCM_DRP[112] bit 6MAIN[1][29][60]-
MMCM_DRP[112] bit 7MAIN[1][28][60]-
MMCM_DRP[112] bit 8MAIN[1][29][59]-
MMCM_DRP[112] bit 9MAIN[1][28][59]-
MMCM_DRP[112] bit 10MAIN[1][29][58]-
MMCM_DRP[112] bit 11MAIN[1][28][58]-
MMCM_DRP[112] bit 12MAIN[1][29][57]-
MMCM_DRP[112] bit 13MAIN[1][28][57]-
MMCM_DRP[112] bit 14MAIN[1][29][56]-
MMCM_DRP[112] bit 15MAIN[1][28][56]-
MMCM_DRP[113] bit 0MAIN[1][29][55]-
MMCM_DRP[113] bit 1MAIN[1][28][55]-
MMCM_DRP[113] bit 2MAIN[1][29][54]-
MMCM_DRP[113] bit 3MAIN[1][28][54]-
MMCM_DRP[113] bit 4MAIN[1][29][53]-
MMCM_DRP[113] bit 5MAIN[1][28][53]-
MMCM_DRP[113] bit 6MAIN[1][29][52]-
MMCM_DRP[113] bit 7MAIN[1][28][52]-
MMCM_DRP[113] bit 8MAIN[1][29][51]-
MMCM_DRP[113] bit 9MAIN[1][28][51]-
MMCM_DRP[113] bit 10MAIN[1][29][50]-
MMCM_DRP[113] bit 11MAIN[1][28][50]-
MMCM_DRP[113] bit 12MAIN[1][29][49]-
MMCM_DRP[113] bit 13MAIN[1][28][49]-
MMCM_DRP[113] bit 14MAIN[1][29][48]-
MMCM_DRP[113] bit 15MAIN[1][28][48]-
MMCM_DRP[114] bit 0MAIN[1][29][47]-
MMCM_DRP[114] bit 1MAIN[1][28][47]-
MMCM_DRP[114] bit 2MAIN[1][29][46]-
MMCM_DRP[114] bit 3MAIN[1][28][46]-
MMCM_DRP[114] bit 4MAIN[1][29][45]-
MMCM_DRP[114] bit 5MAIN[1][28][45]-
MMCM_DRP[114] bit 6MAIN[1][29][44]-
MMCM_DRP[114] bit 7MAIN[1][28][44]-
MMCM_DRP[114] bit 8MAIN[1][29][43]-
MMCM_DRP[114] bit 9MAIN[1][28][43]-
MMCM_DRP[114] bit 10MAIN[1][29][42]-
MMCM_DRP[114] bit 11MAIN[1][28][42]-
MMCM_DRP[114] bit 12MAIN[1][29][41]-
MMCM_DRP[114] bit 13MAIN[1][28][41]-
MMCM_DRP[114] bit 14MAIN[1][29][40]-
MMCM_DRP[114] bit 15MAIN[1][28][40]-
MMCM_DRP[115] bit 0MAIN[1][29][39]-
MMCM_DRP[115] bit 1MAIN[1][28][39]-
MMCM_DRP[115] bit 2MAIN[1][29][38]-
MMCM_DRP[115] bit 3MAIN[1][28][38]-
MMCM_DRP[115] bit 4MAIN[1][29][37]-
MMCM_DRP[115] bit 5MAIN[1][28][37]-
MMCM_DRP[115] bit 6MAIN[1][29][36]-
MMCM_DRP[115] bit 7MAIN[1][28][36]-
MMCM_DRP[115] bit 8MAIN[1][29][35]-
MMCM_DRP[115] bit 9MAIN[1][28][35]-
MMCM_DRP[115] bit 10MAIN[1][29][34]-
MMCM_DRP[115] bit 11MAIN[1][28][34]-
MMCM_DRP[115] bit 12MAIN[1][29][33]-
MMCM_DRP[115] bit 13MAIN[1][28][33]-
MMCM_DRP[115] bit 14MAIN[1][29][32]-
MMCM_DRP[115] bit 15MAIN[1][28][32]-
MMCM_DRP[116] bit 0MAIN[1][29][31]-
MMCM_DRP[116] bit 1MAIN[1][28][31]-
MMCM_DRP[116] bit 2MAIN[1][29][30]-
MMCM_DRP[116] bit 3MAIN[1][28][30]-
MMCM_DRP[116] bit 4MAIN[1][29][29]-
MMCM_DRP[116] bit 5MAIN[1][28][29]-
MMCM_DRP[116] bit 6MAIN[1][29][28]-
MMCM_DRP[116] bit 7MAIN[1][28][28]-
MMCM_DRP[116] bit 8MAIN[1][29][27]-
MMCM_DRP[116] bit 9MAIN[1][28][27]-
MMCM_DRP[116] bit 10MAIN[1][29][26]-
MMCM_DRP[116] bit 11MAIN[1][28][26]-
MMCM_DRP[116] bit 12MAIN[1][29][25]-
MMCM_DRP[116] bit 13MAIN[1][28][25]-
MMCM_DRP[116] bit 14MAIN[1][29][24]-
MMCM_DRP[116] bit 15MAIN[1][28][24]-
MMCM_DRP[117] bit 0MAIN[1][29][23]-
MMCM_DRP[117] bit 1MAIN[1][28][23]-
MMCM_DRP[117] bit 2MAIN[1][29][22]-
MMCM_DRP[117] bit 3MAIN[1][28][22]-
MMCM_DRP[117] bit 4MAIN[1][29][21]-
MMCM_DRP[117] bit 5MAIN[1][28][21]-
MMCM_DRP[117] bit 6MAIN[1][29][20]-
MMCM_DRP[117] bit 7MAIN[1][28][20]-
MMCM_DRP[117] bit 8MAIN[1][29][19]-
MMCM_DRP[117] bit 9MAIN[1][28][19]-
MMCM_DRP[117] bit 10MAIN[1][29][18]-
MMCM_DRP[117] bit 11MAIN[1][28][18]-
MMCM_DRP[117] bit 12MAIN[1][29][17]-
MMCM_DRP[117] bit 13MAIN[1][28][17]-
MMCM_DRP[117] bit 14MAIN[1][29][16]-
MMCM_DRP[117] bit 15MAIN[1][28][16]-
MMCM_DRP[118] bit 0MAIN[1][29][15]-
MMCM_DRP[118] bit 1MAIN[1][28][15]-
MMCM_DRP[118] bit 2MAIN[1][29][14]-
MMCM_DRP[118] bit 3MAIN[1][28][14]-
MMCM_DRP[118] bit 4MAIN[1][29][13]-
MMCM_DRP[118] bit 5MAIN[1][28][13]-
MMCM_DRP[118] bit 6MAIN[1][29][12]-
MMCM_DRP[118] bit 7MAIN[1][28][12]-
MMCM_DRP[118] bit 8MAIN[1][29][11]-
MMCM_DRP[118] bit 9MAIN[1][28][11]-
MMCM_DRP[118] bit 10MAIN[1][29][10]-
MMCM_DRP[118] bit 11MAIN[1][28][10]-
MMCM_DRP[118] bit 12MAIN[1][29][9]-
MMCM_DRP[118] bit 13MAIN[1][28][9]-
MMCM_DRP[118] bit 14MAIN[1][29][8]-
MMCM_DRP[118] bit 15MAIN[1][28][8]-
MMCM_DRP[119] bit 0MAIN[1][29][7]-
MMCM_DRP[119] bit 1MAIN[1][28][7]-
MMCM_DRP[119] bit 2MAIN[1][29][6]-
MMCM_DRP[119] bit 3MAIN[1][28][6]-
MMCM_DRP[119] bit 4MAIN[1][29][5]-
MMCM_DRP[119] bit 5MAIN[1][28][5]-
MMCM_DRP[119] bit 6MAIN[1][29][4]-
MMCM_DRP[119] bit 7MAIN[1][28][4]-
MMCM_DRP[119] bit 8MAIN[1][29][3]-
MMCM_DRP[119] bit 9MAIN[1][28][3]-
MMCM_DRP[119] bit 10MAIN[1][29][2]-
MMCM_DRP[119] bit 11MAIN[1][28][2]-
MMCM_DRP[119] bit 12MAIN[1][29][1]-
MMCM_DRP[119] bit 13MAIN[1][28][1]-
MMCM_DRP[119] bit 14MAIN[1][29][0]-
MMCM_DRP[119] bit 15MAIN[1][28][0]-
MMCM_DRP[120] bit 0MAIN[0][29][63]-
MMCM_DRP[120] bit 1MAIN[0][28][63]-
MMCM_DRP[120] bit 2MAIN[0][29][62]-
MMCM_DRP[120] bit 3MAIN[0][28][62]-
MMCM_DRP[120] bit 4MAIN[0][29][61]-
MMCM_DRP[120] bit 5MAIN[0][28][61]-
MMCM_DRP[120] bit 6MAIN[0][29][60]-
MMCM_DRP[120] bit 7MAIN[0][28][60]-
MMCM_DRP[120] bit 8MAIN[0][29][59]-
MMCM_DRP[120] bit 9MAIN[0][28][59]-
MMCM_DRP[120] bit 10MAIN[0][29][58]-
MMCM_DRP[120] bit 11MAIN[0][28][58]-
MMCM_DRP[120] bit 12MAIN[0][29][57]-
MMCM_DRP[120] bit 13MAIN[0][28][57]-
MMCM_DRP[120] bit 14MAIN[0][29][56]-
MMCM_DRP[120] bit 15MAIN[0][28][56]-
MMCM_DRP[121] bit 0MAIN[0][29][55]-
MMCM_DRP[121] bit 1MAIN[0][28][55]-
MMCM_DRP[121] bit 2MAIN[0][29][54]-
MMCM_DRP[121] bit 3MAIN[0][28][54]-
MMCM_DRP[121] bit 4MAIN[0][29][53]-
MMCM_DRP[121] bit 5MAIN[0][28][53]-
MMCM_DRP[121] bit 6MAIN[0][29][52]-
MMCM_DRP[121] bit 7MAIN[0][28][52]-
MMCM_DRP[121] bit 8MAIN[0][29][51]-
MMCM_DRP[121] bit 9MAIN[0][28][51]-
MMCM_DRP[121] bit 10MAIN[0][29][50]-
MMCM_DRP[121] bit 11MAIN[0][28][50]-
MMCM_DRP[121] bit 12MAIN[0][29][49]-
MMCM_DRP[121] bit 13MAIN[0][28][49]-
MMCM_DRP[121] bit 14MAIN[0][29][48]-
MMCM_DRP[121] bit 15MAIN[0][28][48]-
MMCM_DRP[122] bit 0MAIN[0][29][47]-
MMCM_DRP[122] bit 1MAIN[0][28][47]-
MMCM_DRP[122] bit 2MAIN[0][29][46]-
MMCM_DRP[122] bit 3MAIN[0][28][46]-
MMCM_DRP[122] bit 4MAIN[0][29][45]-
MMCM_DRP[122] bit 5MAIN[0][28][45]-
MMCM_DRP[122] bit 6MAIN[0][29][44]-
MMCM_DRP[122] bit 7MAIN[0][28][44]-
MMCM_DRP[122] bit 8MAIN[0][29][43]-
MMCM_DRP[122] bit 9MAIN[0][28][43]-
MMCM_DRP[122] bit 10MAIN[0][29][42]-
MMCM_DRP[122] bit 11MAIN[0][28][42]-
MMCM_DRP[122] bit 12MAIN[0][29][41]-
MMCM_DRP[122] bit 13MAIN[0][28][41]-
MMCM_DRP[122] bit 14MAIN[0][29][40]-
MMCM_DRP[122] bit 15MAIN[0][28][40]-
MMCM_DRP[123] bit 0MAIN[0][29][39]-
MMCM_DRP[123] bit 1MAIN[0][28][39]-
MMCM_DRP[123] bit 2MAIN[0][29][38]-
MMCM_DRP[123] bit 3MAIN[0][28][38]-
MMCM_DRP[123] bit 4MAIN[0][29][37]-
MMCM_DRP[123] bit 5MAIN[0][28][37]-
MMCM_DRP[123] bit 6MAIN[0][29][36]-
MMCM_DRP[123] bit 7MAIN[0][28][36]-
MMCM_DRP[123] bit 8MAIN[0][29][35]-
MMCM_DRP[123] bit 9MAIN[0][28][35]-
MMCM_DRP[123] bit 10MAIN[0][29][34]-
MMCM_DRP[123] bit 11MAIN[0][28][34]-
MMCM_DRP[123] bit 12MAIN[0][29][33]-
MMCM_DRP[123] bit 13MAIN[0][28][33]-
MMCM_DRP[123] bit 14MAIN[0][29][32]-
MMCM_DRP[123] bit 15MAIN[0][28][32]-
MMCM_DRP[124] bit 0MAIN[0][29][31]-
MMCM_DRP[124] bit 1MAIN[0][28][31]-
MMCM_DRP[124] bit 2MAIN[0][29][30]-
MMCM_DRP[124] bit 3MAIN[0][28][30]-
MMCM_DRP[124] bit 4MAIN[0][29][29]-
MMCM_DRP[124] bit 5MAIN[0][28][29]-
MMCM_DRP[124] bit 6MAIN[0][29][28]-
MMCM_DRP[124] bit 7MAIN[0][28][28]-
MMCM_DRP[124] bit 8MAIN[0][29][27]-
MMCM_DRP[124] bit 9MAIN[0][28][27]-
MMCM_DRP[124] bit 10MAIN[0][29][26]-
MMCM_DRP[124] bit 11MAIN[0][28][26]-
MMCM_DRP[124] bit 12MAIN[0][29][25]-
MMCM_DRP[124] bit 13MAIN[0][28][25]-
MMCM_DRP[124] bit 14MAIN[0][29][24]-
MMCM_DRP[124] bit 15MAIN[0][28][24]-
MMCM_DRP[125] bit 0MAIN[0][29][23]-
MMCM_DRP[125] bit 1MAIN[0][28][23]-
MMCM_DRP[125] bit 2MAIN[0][29][22]-
MMCM_DRP[125] bit 3MAIN[0][28][22]-
MMCM_DRP[125] bit 4MAIN[0][29][21]-
MMCM_DRP[125] bit 5MAIN[0][28][21]-
MMCM_DRP[125] bit 6MAIN[0][29][20]-
MMCM_DRP[125] bit 7MAIN[0][28][20]-
MMCM_DRP[125] bit 8MAIN[0][29][19]-
MMCM_DRP[125] bit 9MAIN[0][28][19]-
MMCM_DRP[125] bit 10MAIN[0][29][18]-
MMCM_DRP[125] bit 11MAIN[0][28][18]-
MMCM_DRP[125] bit 12MAIN[0][29][17]-
MMCM_DRP[125] bit 13MAIN[0][28][17]-
MMCM_DRP[125] bit 14MAIN[0][29][16]-
MMCM_DRP[125] bit 15MAIN[0][28][16]-
MMCM_DRP[126] bit 0MAIN[0][29][15]-
MMCM_DRP[126] bit 1MAIN[0][28][15]-
MMCM_DRP[126] bit 2MAIN[0][29][14]-
MMCM_DRP[126] bit 3MAIN[0][28][14]-
MMCM_DRP[126] bit 4MAIN[0][29][13]-
MMCM_DRP[126] bit 5MAIN[0][28][13]-
MMCM_DRP[126] bit 6MAIN[0][29][12]-
MMCM_DRP[126] bit 7MAIN[0][28][12]-
MMCM_DRP[126] bit 8MAIN[0][29][11]-
MMCM_DRP[126] bit 9MAIN[0][28][11]-
MMCM_DRP[126] bit 10MAIN[0][29][10]-
MMCM_DRP[126] bit 11MAIN[0][28][10]-
MMCM_DRP[126] bit 12MAIN[0][29][9]-
MMCM_DRP[126] bit 13MAIN[0][28][9]-
MMCM_DRP[126] bit 14MAIN[0][29][8]-
MMCM_DRP[126] bit 15MAIN[0][28][8]-
MMCM_DRP[127] bit 0MAIN[0][29][7]-
MMCM_DRP[127] bit 1MAIN[0][28][7]-
MMCM_DRP[127] bit 2MAIN[0][29][6]-
MMCM_DRP[127] bit 3MAIN[0][28][6]-
MMCM_DRP[127] bit 4MAIN[0][29][5]-
MMCM_DRP[127] bit 5MAIN[0][28][5]-
MMCM_DRP[127] bit 6MAIN[0][29][4]-
MMCM_DRP[127] bit 7MAIN[0][28][4]-
MMCM_DRP[127] bit 8MAIN[0][29][3]-
MMCM_DRP[127] bit 9MAIN[0][28][3]-
MMCM_DRP[127] bit 10MAIN[0][29][2]-
MMCM_DRP[127] bit 11MAIN[0][28][2]-
MMCM_DRP[127] bit 12MAIN[0][29][1]-
MMCM_DRP[127] bit 13MAIN[0][28][1]-
MMCM_DRP[127] bit 14MAIN[0][29][0]-
MMCM_DRP[127] bit 15MAIN[0][28][0]-
PLL_DRP[0] bit 0-MAIN[37][28][0]
PLL_DRP[0] bit 1-MAIN[37][29][0]
PLL_DRP[0] bit 2-MAIN[37][28][1]
PLL_DRP[0] bit 3-MAIN[37][29][1]
PLL_DRP[0] bit 4-MAIN[37][28][2]
PLL_DRP[0] bit 5-MAIN[37][29][2]
PLL_DRP[0] bit 6-MAIN[37][28][3]
PLL_DRP[0] bit 7-MAIN[37][29][3]
PLL_DRP[0] bit 8-MAIN[37][28][4]
PLL_DRP[0] bit 9-MAIN[37][29][4]
PLL_DRP[0] bit 10-MAIN[37][28][5]
PLL_DRP[0] bit 11-MAIN[37][29][5]
PLL_DRP[0] bit 12-MAIN[37][28][6]
PLL_DRP[0] bit 13-MAIN[37][29][6]
PLL_DRP[0] bit 14-MAIN[37][28][7]
PLL_DRP[0] bit 15-MAIN[37][29][7]
PLL_DRP[1] bit 0-MAIN[37][28][8]
PLL_DRP[1] bit 1-MAIN[37][29][8]
PLL_DRP[1] bit 2-MAIN[37][28][9]
PLL_DRP[1] bit 3-MAIN[37][29][9]
PLL_DRP[1] bit 4-MAIN[37][28][10]
PLL_DRP[1] bit 5-MAIN[37][29][10]
PLL_DRP[1] bit 6-MAIN[37][28][11]
PLL_DRP[1] bit 7-MAIN[37][29][11]
PLL_DRP[1] bit 8-MAIN[37][28][12]
PLL_DRP[1] bit 9-MAIN[37][29][12]
PLL_DRP[1] bit 10-MAIN[37][28][13]
PLL_DRP[1] bit 11-MAIN[37][29][13]
PLL_DRP[1] bit 12-MAIN[37][28][14]
PLL_DRP[1] bit 13-MAIN[37][29][14]
PLL_DRP[1] bit 14-MAIN[37][28][15]
PLL_DRP[1] bit 15-MAIN[37][29][15]
PLL_DRP[2] bit 0-MAIN[37][28][16]
PLL_DRP[2] bit 1-MAIN[37][29][16]
PLL_DRP[2] bit 2-MAIN[37][28][17]
PLL_DRP[2] bit 3-MAIN[37][29][17]
PLL_DRP[2] bit 4-MAIN[37][28][18]
PLL_DRP[2] bit 5-MAIN[37][29][18]
PLL_DRP[2] bit 6-MAIN[37][28][19]
PLL_DRP[2] bit 7-MAIN[37][29][19]
PLL_DRP[2] bit 8-MAIN[37][28][20]
PLL_DRP[2] bit 9-MAIN[37][29][20]
PLL_DRP[2] bit 10-MAIN[37][28][21]
PLL_DRP[2] bit 11-MAIN[37][29][21]
PLL_DRP[2] bit 12-MAIN[37][28][22]
PLL_DRP[2] bit 13-MAIN[37][29][22]
PLL_DRP[2] bit 14-MAIN[37][28][23]
PLL_DRP[2] bit 15-MAIN[37][29][23]
PLL_DRP[3] bit 0-MAIN[37][28][24]
PLL_DRP[3] bit 1-MAIN[37][29][24]
PLL_DRP[3] bit 2-MAIN[37][28][25]
PLL_DRP[3] bit 3-MAIN[37][29][25]
PLL_DRP[3] bit 4-MAIN[37][28][26]
PLL_DRP[3] bit 5-MAIN[37][29][26]
PLL_DRP[3] bit 6-MAIN[37][28][27]
PLL_DRP[3] bit 7-MAIN[37][29][27]
PLL_DRP[3] bit 8-MAIN[37][28][28]
PLL_DRP[3] bit 9-MAIN[37][29][28]
PLL_DRP[3] bit 10-MAIN[37][28][29]
PLL_DRP[3] bit 11-MAIN[37][29][29]
PLL_DRP[3] bit 12-MAIN[37][28][30]
PLL_DRP[3] bit 13-MAIN[37][29][30]
PLL_DRP[3] bit 14-MAIN[37][28][31]
PLL_DRP[3] bit 15-MAIN[37][29][31]
PLL_DRP[4] bit 0-MAIN[37][28][32]
PLL_DRP[4] bit 1-MAIN[37][29][32]
PLL_DRP[4] bit 2-MAIN[37][28][33]
PLL_DRP[4] bit 3-MAIN[37][29][33]
PLL_DRP[4] bit 4-MAIN[37][28][34]
PLL_DRP[4] bit 5-MAIN[37][29][34]
PLL_DRP[4] bit 6-MAIN[37][28][35]
PLL_DRP[4] bit 7-MAIN[37][29][35]
PLL_DRP[4] bit 8-MAIN[37][28][36]
PLL_DRP[4] bit 9-MAIN[37][29][36]
PLL_DRP[4] bit 10-MAIN[37][28][37]
PLL_DRP[4] bit 11-MAIN[37][29][37]
PLL_DRP[4] bit 12-MAIN[37][28][38]
PLL_DRP[4] bit 13-MAIN[37][29][38]
PLL_DRP[4] bit 14-MAIN[37][28][39]
PLL_DRP[4] bit 15-MAIN[37][29][39]
PLL_DRP[5] bit 0-MAIN[37][28][40]
PLL_DRP[5] bit 1-MAIN[37][29][40]
PLL_DRP[5] bit 2-MAIN[37][28][41]
PLL_DRP[5] bit 3-MAIN[37][29][41]
PLL_DRP[5] bit 4-MAIN[37][28][42]
PLL_DRP[5] bit 5-MAIN[37][29][42]
PLL_DRP[5] bit 6-MAIN[37][28][43]
PLL_DRP[5] bit 7-MAIN[37][29][43]
PLL_DRP[5] bit 8-MAIN[37][28][44]
PLL_DRP[5] bit 9-MAIN[37][29][44]
PLL_DRP[5] bit 10-MAIN[37][28][45]
PLL_DRP[5] bit 11-MAIN[37][29][45]
PLL_DRP[5] bit 12-MAIN[37][28][46]
PLL_DRP[5] bit 13-MAIN[37][29][46]
PLL_DRP[5] bit 14-MAIN[37][28][47]
PLL_DRP[5] bit 15-MAIN[37][29][47]
PLL_DRP[6] bit 0-MAIN[37][28][48]
PLL_DRP[6] bit 1-MAIN[37][29][48]
PLL_DRP[6] bit 2-MAIN[37][28][49]
PLL_DRP[6] bit 3-MAIN[37][29][49]
PLL_DRP[6] bit 4-MAIN[37][28][50]
PLL_DRP[6] bit 5-MAIN[37][29][50]
PLL_DRP[6] bit 6-MAIN[37][28][51]
PLL_DRP[6] bit 7-MAIN[37][29][51]
PLL_DRP[6] bit 8-MAIN[37][28][52]
PLL_DRP[6] bit 9-MAIN[37][29][52]
PLL_DRP[6] bit 10-MAIN[37][28][53]
PLL_DRP[6] bit 11-MAIN[37][29][53]
PLL_DRP[6] bit 12-MAIN[37][28][54]
PLL_DRP[6] bit 13-MAIN[37][29][54]
PLL_DRP[6] bit 14-MAIN[37][28][55]
PLL_DRP[6] bit 15-MAIN[37][29][55]
PLL_DRP[7] bit 0-MAIN[37][28][56]
PLL_DRP[7] bit 1-MAIN[37][29][56]
PLL_DRP[7] bit 2-MAIN[37][28][57]
PLL_DRP[7] bit 3-MAIN[37][29][57]
PLL_DRP[7] bit 4-MAIN[37][28][58]
PLL_DRP[7] bit 5-MAIN[37][29][58]
PLL_DRP[7] bit 6-MAIN[37][28][59]
PLL_DRP[7] bit 7-MAIN[37][29][59]
PLL_DRP[7] bit 8-MAIN[37][28][60]
PLL_DRP[7] bit 9-MAIN[37][29][60]
PLL_DRP[7] bit 10-MAIN[37][28][61]
PLL_DRP[7] bit 11-MAIN[37][29][61]
PLL_DRP[7] bit 12-MAIN[37][28][62]
PLL_DRP[7] bit 13-MAIN[37][29][62]
PLL_DRP[7] bit 14-MAIN[37][28][63]
PLL_DRP[7] bit 15-MAIN[37][29][63]
PLL_DRP[8] bit 0-MAIN[38][28][0]
PLL_DRP[8] bit 1-MAIN[38][29][0]
PLL_DRP[8] bit 2-MAIN[38][28][1]
PLL_DRP[8] bit 3-MAIN[38][29][1]
PLL_DRP[8] bit 4-MAIN[38][28][2]
PLL_DRP[8] bit 5-MAIN[38][29][2]
PLL_DRP[8] bit 6-MAIN[38][28][3]
PLL_DRP[8] bit 7-MAIN[38][29][3]
PLL_DRP[8] bit 8-MAIN[38][28][4]
PLL_DRP[8] bit 9-MAIN[38][29][4]
PLL_DRP[8] bit 10-MAIN[38][28][5]
PLL_DRP[8] bit 11-MAIN[38][29][5]
PLL_DRP[8] bit 12-MAIN[38][28][6]
PLL_DRP[8] bit 13-MAIN[38][29][6]
PLL_DRP[8] bit 14-MAIN[38][28][7]
PLL_DRP[8] bit 15-MAIN[38][29][7]
PLL_DRP[9] bit 0-MAIN[38][28][8]
PLL_DRP[9] bit 1-MAIN[38][29][8]
PLL_DRP[9] bit 2-MAIN[38][28][9]
PLL_DRP[9] bit 3-MAIN[38][29][9]
PLL_DRP[9] bit 4-MAIN[38][28][10]
PLL_DRP[9] bit 5-MAIN[38][29][10]
PLL_DRP[9] bit 6-MAIN[38][28][11]
PLL_DRP[9] bit 7-MAIN[38][29][11]
PLL_DRP[9] bit 8-MAIN[38][28][12]
PLL_DRP[9] bit 9-MAIN[38][29][12]
PLL_DRP[9] bit 10-MAIN[38][28][13]
PLL_DRP[9] bit 11-MAIN[38][29][13]
PLL_DRP[9] bit 12-MAIN[38][28][14]
PLL_DRP[9] bit 13-MAIN[38][29][14]
PLL_DRP[9] bit 14-MAIN[38][28][15]
PLL_DRP[9] bit 15-MAIN[38][29][15]
PLL_DRP[10] bit 0-MAIN[38][28][16]
PLL_DRP[10] bit 1-MAIN[38][29][16]
PLL_DRP[10] bit 2-MAIN[38][28][17]
PLL_DRP[10] bit 3-MAIN[38][29][17]
PLL_DRP[10] bit 4-MAIN[38][28][18]
PLL_DRP[10] bit 5-MAIN[38][29][18]
PLL_DRP[10] bit 6-MAIN[38][28][19]
PLL_DRP[10] bit 7-MAIN[38][29][19]
PLL_DRP[10] bit 8-MAIN[38][28][20]
PLL_DRP[10] bit 9-MAIN[38][29][20]
PLL_DRP[10] bit 10-MAIN[38][28][21]
PLL_DRP[10] bit 11-MAIN[38][29][21]
PLL_DRP[10] bit 12-MAIN[38][28][22]
PLL_DRP[10] bit 13-MAIN[38][29][22]
PLL_DRP[10] bit 14-MAIN[38][28][23]
PLL_DRP[10] bit 15-MAIN[38][29][23]
PLL_DRP[11] bit 0-MAIN[38][28][24]
PLL_DRP[11] bit 1-MAIN[38][29][24]
PLL_DRP[11] bit 2-MAIN[38][28][25]
PLL_DRP[11] bit 3-MAIN[38][29][25]
PLL_DRP[11] bit 4-MAIN[38][28][26]
PLL_DRP[11] bit 5-MAIN[38][29][26]
PLL_DRP[11] bit 6-MAIN[38][28][27]
PLL_DRP[11] bit 7-MAIN[38][29][27]
PLL_DRP[11] bit 8-MAIN[38][28][28]
PLL_DRP[11] bit 9-MAIN[38][29][28]
PLL_DRP[11] bit 10-MAIN[38][28][29]
PLL_DRP[11] bit 11-MAIN[38][29][29]
PLL_DRP[11] bit 12-MAIN[38][28][30]
PLL_DRP[11] bit 13-MAIN[38][29][30]
PLL_DRP[11] bit 14-MAIN[38][28][31]
PLL_DRP[11] bit 15-MAIN[38][29][31]
PLL_DRP[12] bit 0-MAIN[38][28][32]
PLL_DRP[12] bit 1-MAIN[38][29][32]
PLL_DRP[12] bit 2-MAIN[38][28][33]
PLL_DRP[12] bit 3-MAIN[38][29][33]
PLL_DRP[12] bit 4-MAIN[38][28][34]
PLL_DRP[12] bit 5-MAIN[38][29][34]
PLL_DRP[12] bit 6-MAIN[38][28][35]
PLL_DRP[12] bit 7-MAIN[38][29][35]
PLL_DRP[12] bit 8-MAIN[38][28][36]
PLL_DRP[12] bit 9-MAIN[38][29][36]
PLL_DRP[12] bit 10-MAIN[38][28][37]
PLL_DRP[12] bit 11-MAIN[38][29][37]
PLL_DRP[12] bit 12-MAIN[38][28][38]
PLL_DRP[12] bit 13-MAIN[38][29][38]
PLL_DRP[12] bit 14-MAIN[38][28][39]
PLL_DRP[12] bit 15-MAIN[38][29][39]
PLL_DRP[13] bit 0-MAIN[38][28][40]
PLL_DRP[13] bit 1-MAIN[38][29][40]
PLL_DRP[13] bit 2-MAIN[38][28][41]
PLL_DRP[13] bit 3-MAIN[38][29][41]
PLL_DRP[13] bit 4-MAIN[38][28][42]
PLL_DRP[13] bit 5-MAIN[38][29][42]
PLL_DRP[13] bit 6-MAIN[38][28][43]
PLL_DRP[13] bit 7-MAIN[38][29][43]
PLL_DRP[13] bit 8-MAIN[38][28][44]
PLL_DRP[13] bit 9-MAIN[38][29][44]
PLL_DRP[13] bit 10-MAIN[38][28][45]
PLL_DRP[13] bit 11-MAIN[38][29][45]
PLL_DRP[13] bit 12-MAIN[38][28][46]
PLL_DRP[13] bit 13-MAIN[38][29][46]
PLL_DRP[13] bit 14-MAIN[38][28][47]
PLL_DRP[13] bit 15-MAIN[38][29][47]
PLL_DRP[14] bit 0-MAIN[38][28][48]
PLL_DRP[14] bit 1-MAIN[38][29][48]
PLL_DRP[14] bit 2-MAIN[38][28][49]
PLL_DRP[14] bit 3-MAIN[38][29][49]
PLL_DRP[14] bit 4-MAIN[38][28][50]
PLL_DRP[14] bit 5-MAIN[38][29][50]
PLL_DRP[14] bit 6-MAIN[38][28][51]
PLL_DRP[14] bit 7-MAIN[38][29][51]
PLL_DRP[14] bit 8-MAIN[38][28][52]
PLL_DRP[14] bit 9-MAIN[38][29][52]
PLL_DRP[14] bit 10-MAIN[38][28][53]
PLL_DRP[14] bit 11-MAIN[38][29][53]
PLL_DRP[14] bit 12-MAIN[38][28][54]
PLL_DRP[14] bit 13-MAIN[38][29][54]
PLL_DRP[14] bit 14-MAIN[38][28][55]
PLL_DRP[14] bit 15-MAIN[38][29][55]
PLL_DRP[15] bit 0-MAIN[38][28][56]
PLL_DRP[15] bit 1-MAIN[38][29][56]
PLL_DRP[15] bit 2-MAIN[38][28][57]
PLL_DRP[15] bit 3-MAIN[38][29][57]
PLL_DRP[15] bit 4-MAIN[38][28][58]
PLL_DRP[15] bit 5-MAIN[38][29][58]
PLL_DRP[15] bit 6-MAIN[38][28][59]
PLL_DRP[15] bit 7-MAIN[38][29][59]
PLL_DRP[15] bit 8-MAIN[38][28][60]
PLL_DRP[15] bit 9-MAIN[38][29][60]
PLL_DRP[15] bit 10-MAIN[38][28][61]
PLL_DRP[15] bit 11-MAIN[38][29][61]
PLL_DRP[15] bit 12-MAIN[38][28][62]
PLL_DRP[15] bit 13-MAIN[38][29][62]
PLL_DRP[15] bit 14-MAIN[38][28][63]
PLL_DRP[15] bit 15-MAIN[38][29][63]
PLL_DRP[16] bit 0-MAIN[39][28][0]
PLL_DRP[16] bit 1-MAIN[39][29][0]
PLL_DRP[16] bit 2-MAIN[39][28][1]
PLL_DRP[16] bit 3-MAIN[39][29][1]
PLL_DRP[16] bit 4-MAIN[39][28][2]
PLL_DRP[16] bit 5-MAIN[39][29][2]
PLL_DRP[16] bit 6-MAIN[39][28][3]
PLL_DRP[16] bit 7-MAIN[39][29][3]
PLL_DRP[16] bit 8-MAIN[39][28][4]
PLL_DRP[16] bit 9-MAIN[39][29][4]
PLL_DRP[16] bit 10-MAIN[39][28][5]
PLL_DRP[16] bit 11-MAIN[39][29][5]
PLL_DRP[16] bit 12-MAIN[39][28][6]
PLL_DRP[16] bit 13-MAIN[39][29][6]
PLL_DRP[16] bit 14-MAIN[39][28][7]
PLL_DRP[16] bit 15-MAIN[39][29][7]
PLL_DRP[17] bit 0-MAIN[39][28][8]
PLL_DRP[17] bit 1-MAIN[39][29][8]
PLL_DRP[17] bit 2-MAIN[39][28][9]
PLL_DRP[17] bit 3-MAIN[39][29][9]
PLL_DRP[17] bit 4-MAIN[39][28][10]
PLL_DRP[17] bit 5-MAIN[39][29][10]
PLL_DRP[17] bit 6-MAIN[39][28][11]
PLL_DRP[17] bit 7-MAIN[39][29][11]
PLL_DRP[17] bit 8-MAIN[39][28][12]
PLL_DRP[17] bit 9-MAIN[39][29][12]
PLL_DRP[17] bit 10-MAIN[39][28][13]
PLL_DRP[17] bit 11-MAIN[39][29][13]
PLL_DRP[17] bit 12-MAIN[39][28][14]
PLL_DRP[17] bit 13-MAIN[39][29][14]
PLL_DRP[17] bit 14-MAIN[39][28][15]
PLL_DRP[17] bit 15-MAIN[39][29][15]
PLL_DRP[18] bit 0-MAIN[39][28][16]
PLL_DRP[18] bit 1-MAIN[39][29][16]
PLL_DRP[18] bit 2-MAIN[39][28][17]
PLL_DRP[18] bit 3-MAIN[39][29][17]
PLL_DRP[18] bit 4-MAIN[39][28][18]
PLL_DRP[18] bit 5-MAIN[39][29][18]
PLL_DRP[18] bit 6-MAIN[39][28][19]
PLL_DRP[18] bit 7-MAIN[39][29][19]
PLL_DRP[18] bit 8-MAIN[39][28][20]
PLL_DRP[18] bit 9-MAIN[39][29][20]
PLL_DRP[18] bit 10-MAIN[39][28][21]
PLL_DRP[18] bit 11-MAIN[39][29][21]
PLL_DRP[18] bit 12-MAIN[39][28][22]
PLL_DRP[18] bit 13-MAIN[39][29][22]
PLL_DRP[18] bit 14-MAIN[39][28][23]
PLL_DRP[18] bit 15-MAIN[39][29][23]
PLL_DRP[19] bit 0-MAIN[39][28][24]
PLL_DRP[19] bit 1-MAIN[39][29][24]
PLL_DRP[19] bit 2-MAIN[39][28][25]
PLL_DRP[19] bit 3-MAIN[39][29][25]
PLL_DRP[19] bit 4-MAIN[39][28][26]
PLL_DRP[19] bit 5-MAIN[39][29][26]
PLL_DRP[19] bit 6-MAIN[39][28][27]
PLL_DRP[19] bit 7-MAIN[39][29][27]
PLL_DRP[19] bit 8-MAIN[39][28][28]
PLL_DRP[19] bit 9-MAIN[39][29][28]
PLL_DRP[19] bit 10-MAIN[39][28][29]
PLL_DRP[19] bit 11-MAIN[39][29][29]
PLL_DRP[19] bit 12-MAIN[39][28][30]
PLL_DRP[19] bit 13-MAIN[39][29][30]
PLL_DRP[19] bit 14-MAIN[39][28][31]
PLL_DRP[19] bit 15-MAIN[39][29][31]
PLL_DRP[20] bit 0-MAIN[39][28][32]
PLL_DRP[20] bit 1-MAIN[39][29][32]
PLL_DRP[20] bit 2-MAIN[39][28][33]
PLL_DRP[20] bit 3-MAIN[39][29][33]
PLL_DRP[20] bit 4-MAIN[39][28][34]
PLL_DRP[20] bit 5-MAIN[39][29][34]
PLL_DRP[20] bit 6-MAIN[39][28][35]
PLL_DRP[20] bit 7-MAIN[39][29][35]
PLL_DRP[20] bit 8-MAIN[39][28][36]
PLL_DRP[20] bit 9-MAIN[39][29][36]
PLL_DRP[20] bit 10-MAIN[39][28][37]
PLL_DRP[20] bit 11-MAIN[39][29][37]
PLL_DRP[20] bit 12-MAIN[39][28][38]
PLL_DRP[20] bit 13-MAIN[39][29][38]
PLL_DRP[20] bit 14-MAIN[39][28][39]
PLL_DRP[20] bit 15-MAIN[39][29][39]
PLL_DRP[21] bit 0-MAIN[39][28][40]
PLL_DRP[21] bit 1-MAIN[39][29][40]
PLL_DRP[21] bit 2-MAIN[39][28][41]
PLL_DRP[21] bit 3-MAIN[39][29][41]
PLL_DRP[21] bit 4-MAIN[39][28][42]
PLL_DRP[21] bit 5-MAIN[39][29][42]
PLL_DRP[21] bit 6-MAIN[39][28][43]
PLL_DRP[21] bit 7-MAIN[39][29][43]
PLL_DRP[21] bit 8-MAIN[39][28][44]
PLL_DRP[21] bit 9-MAIN[39][29][44]
PLL_DRP[21] bit 10-MAIN[39][28][45]
PLL_DRP[21] bit 11-MAIN[39][29][45]
PLL_DRP[21] bit 12-MAIN[39][28][46]
PLL_DRP[21] bit 13-MAIN[39][29][46]
PLL_DRP[21] bit 14-MAIN[39][28][47]
PLL_DRP[21] bit 15-MAIN[39][29][47]
PLL_DRP[22] bit 0-MAIN[39][28][48]
PLL_DRP[22] bit 1-MAIN[39][29][48]
PLL_DRP[22] bit 2-MAIN[39][28][49]
PLL_DRP[22] bit 3-MAIN[39][29][49]
PLL_DRP[22] bit 4-MAIN[39][28][50]
PLL_DRP[22] bit 5-MAIN[39][29][50]
PLL_DRP[22] bit 6-MAIN[39][28][51]
PLL_DRP[22] bit 7-MAIN[39][29][51]
PLL_DRP[22] bit 8-MAIN[39][28][52]
PLL_DRP[22] bit 9-MAIN[39][29][52]
PLL_DRP[22] bit 10-MAIN[39][28][53]
PLL_DRP[22] bit 11-MAIN[39][29][53]
PLL_DRP[22] bit 12-MAIN[39][28][54]
PLL_DRP[22] bit 13-MAIN[39][29][54]
PLL_DRP[22] bit 14-MAIN[39][28][55]
PLL_DRP[22] bit 15-MAIN[39][29][55]
PLL_DRP[23] bit 0-MAIN[39][28][56]
PLL_DRP[23] bit 1-MAIN[39][29][56]
PLL_DRP[23] bit 2-MAIN[39][28][57]
PLL_DRP[23] bit 3-MAIN[39][29][57]
PLL_DRP[23] bit 4-MAIN[39][28][58]
PLL_DRP[23] bit 5-MAIN[39][29][58]
PLL_DRP[23] bit 6-MAIN[39][28][59]
PLL_DRP[23] bit 7-MAIN[39][29][59]
PLL_DRP[23] bit 8-MAIN[39][28][60]
PLL_DRP[23] bit 9-MAIN[39][29][60]
PLL_DRP[23] bit 10-MAIN[39][28][61]
PLL_DRP[23] bit 11-MAIN[39][29][61]
PLL_DRP[23] bit 12-MAIN[39][28][62]
PLL_DRP[23] bit 13-MAIN[39][29][62]
PLL_DRP[23] bit 14-MAIN[39][28][63]
PLL_DRP[23] bit 15-MAIN[39][29][63]
PLL_DRP[24] bit 0-MAIN[40][28][0]
PLL_DRP[24] bit 1-MAIN[40][29][0]
PLL_DRP[24] bit 2-MAIN[40][28][1]
PLL_DRP[24] bit 3-MAIN[40][29][1]
PLL_DRP[24] bit 4-MAIN[40][28][2]
PLL_DRP[24] bit 5-MAIN[40][29][2]
PLL_DRP[24] bit 6-MAIN[40][28][3]
PLL_DRP[24] bit 7-MAIN[40][29][3]
PLL_DRP[24] bit 8-MAIN[40][28][4]
PLL_DRP[24] bit 9-MAIN[40][29][4]
PLL_DRP[24] bit 10-MAIN[40][28][5]
PLL_DRP[24] bit 11-MAIN[40][29][5]
PLL_DRP[24] bit 12-MAIN[40][28][6]
PLL_DRP[24] bit 13-MAIN[40][29][6]
PLL_DRP[24] bit 14-MAIN[40][28][7]
PLL_DRP[24] bit 15-MAIN[40][29][7]
PLL_DRP[25] bit 0-MAIN[40][28][8]
PLL_DRP[25] bit 1-MAIN[40][29][8]
PLL_DRP[25] bit 2-MAIN[40][28][9]
PLL_DRP[25] bit 3-MAIN[40][29][9]
PLL_DRP[25] bit 4-MAIN[40][28][10]
PLL_DRP[25] bit 5-MAIN[40][29][10]
PLL_DRP[25] bit 6-MAIN[40][28][11]
PLL_DRP[25] bit 7-MAIN[40][29][11]
PLL_DRP[25] bit 8-MAIN[40][28][12]
PLL_DRP[25] bit 9-MAIN[40][29][12]
PLL_DRP[25] bit 10-MAIN[40][28][13]
PLL_DRP[25] bit 11-MAIN[40][29][13]
PLL_DRP[25] bit 12-MAIN[40][28][14]
PLL_DRP[25] bit 13-MAIN[40][29][14]
PLL_DRP[25] bit 14-MAIN[40][28][15]
PLL_DRP[25] bit 15-MAIN[40][29][15]
PLL_DRP[26] bit 0-MAIN[40][28][16]
PLL_DRP[26] bit 1-MAIN[40][29][16]
PLL_DRP[26] bit 2-MAIN[40][28][17]
PLL_DRP[26] bit 3-MAIN[40][29][17]
PLL_DRP[26] bit 4-MAIN[40][28][18]
PLL_DRP[26] bit 5-MAIN[40][29][18]
PLL_DRP[26] bit 6-MAIN[40][28][19]
PLL_DRP[26] bit 7-MAIN[40][29][19]
PLL_DRP[26] bit 8-MAIN[40][28][20]
PLL_DRP[26] bit 9-MAIN[40][29][20]
PLL_DRP[26] bit 10-MAIN[40][28][21]
PLL_DRP[26] bit 11-MAIN[40][29][21]
PLL_DRP[26] bit 12-MAIN[40][28][22]
PLL_DRP[26] bit 13-MAIN[40][29][22]
PLL_DRP[26] bit 14-MAIN[40][28][23]
PLL_DRP[26] bit 15-MAIN[40][29][23]
PLL_DRP[27] bit 0-MAIN[40][28][24]
PLL_DRP[27] bit 1-MAIN[40][29][24]
PLL_DRP[27] bit 2-MAIN[40][28][25]
PLL_DRP[27] bit 3-MAIN[40][29][25]
PLL_DRP[27] bit 4-MAIN[40][28][26]
PLL_DRP[27] bit 5-MAIN[40][29][26]
PLL_DRP[27] bit 6-MAIN[40][28][27]
PLL_DRP[27] bit 7-MAIN[40][29][27]
PLL_DRP[27] bit 8-MAIN[40][28][28]
PLL_DRP[27] bit 9-MAIN[40][29][28]
PLL_DRP[27] bit 10-MAIN[40][28][29]
PLL_DRP[27] bit 11-MAIN[40][29][29]
PLL_DRP[27] bit 12-MAIN[40][28][30]
PLL_DRP[27] bit 13-MAIN[40][29][30]
PLL_DRP[27] bit 14-MAIN[40][28][31]
PLL_DRP[27] bit 15-MAIN[40][29][31]
PLL_DRP[28] bit 0-MAIN[40][28][32]
PLL_DRP[28] bit 1-MAIN[40][29][32]
PLL_DRP[28] bit 2-MAIN[40][28][33]
PLL_DRP[28] bit 3-MAIN[40][29][33]
PLL_DRP[28] bit 4-MAIN[40][28][34]
PLL_DRP[28] bit 5-MAIN[40][29][34]
PLL_DRP[28] bit 6-MAIN[40][28][35]
PLL_DRP[28] bit 7-MAIN[40][29][35]
PLL_DRP[28] bit 8-MAIN[40][28][36]
PLL_DRP[28] bit 9-MAIN[40][29][36]
PLL_DRP[28] bit 10-MAIN[40][28][37]
PLL_DRP[28] bit 11-MAIN[40][29][37]
PLL_DRP[28] bit 12-MAIN[40][28][38]
PLL_DRP[28] bit 13-MAIN[40][29][38]
PLL_DRP[28] bit 14-MAIN[40][28][39]
PLL_DRP[28] bit 15-MAIN[40][29][39]
PLL_DRP[29] bit 0-MAIN[40][28][40]
PLL_DRP[29] bit 1-MAIN[40][29][40]
PLL_DRP[29] bit 2-MAIN[40][28][41]
PLL_DRP[29] bit 3-MAIN[40][29][41]
PLL_DRP[29] bit 4-MAIN[40][28][42]
PLL_DRP[29] bit 5-MAIN[40][29][42]
PLL_DRP[29] bit 6-MAIN[40][28][43]
PLL_DRP[29] bit 7-MAIN[40][29][43]
PLL_DRP[29] bit 8-MAIN[40][28][44]
PLL_DRP[29] bit 9-MAIN[40][29][44]
PLL_DRP[29] bit 10-MAIN[40][28][45]
PLL_DRP[29] bit 11-MAIN[40][29][45]
PLL_DRP[29] bit 12-MAIN[40][28][46]
PLL_DRP[29] bit 13-MAIN[40][29][46]
PLL_DRP[29] bit 14-MAIN[40][28][47]
PLL_DRP[29] bit 15-MAIN[40][29][47]
PLL_DRP[30] bit 0-MAIN[40][28][48]
PLL_DRP[30] bit 1-MAIN[40][29][48]
PLL_DRP[30] bit 2-MAIN[40][28][49]
PLL_DRP[30] bit 3-MAIN[40][29][49]
PLL_DRP[30] bit 4-MAIN[40][28][50]
PLL_DRP[30] bit 5-MAIN[40][29][50]
PLL_DRP[30] bit 6-MAIN[40][28][51]
PLL_DRP[30] bit 7-MAIN[40][29][51]
PLL_DRP[30] bit 8-MAIN[40][28][52]
PLL_DRP[30] bit 9-MAIN[40][29][52]
PLL_DRP[30] bit 10-MAIN[40][28][53]
PLL_DRP[30] bit 11-MAIN[40][29][53]
PLL_DRP[30] bit 12-MAIN[40][28][54]
PLL_DRP[30] bit 13-MAIN[40][29][54]
PLL_DRP[30] bit 14-MAIN[40][28][55]
PLL_DRP[30] bit 15-MAIN[40][29][55]
PLL_DRP[31] bit 0-MAIN[40][28][56]
PLL_DRP[31] bit 1-MAIN[40][29][56]
PLL_DRP[31] bit 2-MAIN[40][28][57]
PLL_DRP[31] bit 3-MAIN[40][29][57]
PLL_DRP[31] bit 4-MAIN[40][28][58]
PLL_DRP[31] bit 5-MAIN[40][29][58]
PLL_DRP[31] bit 6-MAIN[40][28][59]
PLL_DRP[31] bit 7-MAIN[40][29][59]
PLL_DRP[31] bit 8-MAIN[40][28][60]
PLL_DRP[31] bit 9-MAIN[40][29][60]
PLL_DRP[31] bit 10-MAIN[40][28][61]
PLL_DRP[31] bit 11-MAIN[40][29][61]
PLL_DRP[31] bit 12-MAIN[40][28][62]
PLL_DRP[31] bit 13-MAIN[40][29][62]
PLL_DRP[31] bit 14-MAIN[40][28][63]
PLL_DRP[31] bit 15-MAIN[40][29][63]
PLL_DRP[32] bit 0-MAIN[41][28][0]
PLL_DRP[32] bit 1-MAIN[41][29][0]
PLL_DRP[32] bit 2-MAIN[41][28][1]
PLL_DRP[32] bit 3-MAIN[41][29][1]
PLL_DRP[32] bit 4-MAIN[41][28][2]
PLL_DRP[32] bit 5-MAIN[41][29][2]
PLL_DRP[32] bit 6-MAIN[41][28][3]
PLL_DRP[32] bit 7-MAIN[41][29][3]
PLL_DRP[32] bit 8-MAIN[41][28][4]
PLL_DRP[32] bit 9-MAIN[41][29][4]
PLL_DRP[32] bit 10-MAIN[41][28][5]
PLL_DRP[32] bit 11-MAIN[41][29][5]
PLL_DRP[32] bit 12-MAIN[41][28][6]
PLL_DRP[32] bit 13-MAIN[41][29][6]
PLL_DRP[32] bit 14-MAIN[41][28][7]
PLL_DRP[32] bit 15-MAIN[41][29][7]
PLL_DRP[33] bit 0-MAIN[41][28][8]
PLL_DRP[33] bit 1-MAIN[41][29][8]
PLL_DRP[33] bit 2-MAIN[41][28][9]
PLL_DRP[33] bit 3-MAIN[41][29][9]
PLL_DRP[33] bit 4-MAIN[41][28][10]
PLL_DRP[33] bit 5-MAIN[41][29][10]
PLL_DRP[33] bit 6-MAIN[41][28][11]
PLL_DRP[33] bit 7-MAIN[41][29][11]
PLL_DRP[33] bit 8-MAIN[41][28][12]
PLL_DRP[33] bit 9-MAIN[41][29][12]
PLL_DRP[33] bit 10-MAIN[41][28][13]
PLL_DRP[33] bit 11-MAIN[41][29][13]
PLL_DRP[33] bit 12-MAIN[41][28][14]
PLL_DRP[33] bit 13-MAIN[41][29][14]
PLL_DRP[33] bit 14-MAIN[41][28][15]
PLL_DRP[33] bit 15-MAIN[41][29][15]
PLL_DRP[34] bit 0-MAIN[41][28][16]
PLL_DRP[34] bit 1-MAIN[41][29][16]
PLL_DRP[34] bit 2-MAIN[41][28][17]
PLL_DRP[34] bit 3-MAIN[41][29][17]
PLL_DRP[34] bit 4-MAIN[41][28][18]
PLL_DRP[34] bit 5-MAIN[41][29][18]
PLL_DRP[34] bit 6-MAIN[41][28][19]
PLL_DRP[34] bit 7-MAIN[41][29][19]
PLL_DRP[34] bit 8-MAIN[41][28][20]
PLL_DRP[34] bit 9-MAIN[41][29][20]
PLL_DRP[34] bit 10-MAIN[41][28][21]
PLL_DRP[34] bit 11-MAIN[41][29][21]
PLL_DRP[34] bit 12-MAIN[41][28][22]
PLL_DRP[34] bit 13-MAIN[41][29][22]
PLL_DRP[34] bit 14-MAIN[41][28][23]
PLL_DRP[34] bit 15-MAIN[41][29][23]
PLL_DRP[35] bit 0-MAIN[41][28][24]
PLL_DRP[35] bit 1-MAIN[41][29][24]
PLL_DRP[35] bit 2-MAIN[41][28][25]
PLL_DRP[35] bit 3-MAIN[41][29][25]
PLL_DRP[35] bit 4-MAIN[41][28][26]
PLL_DRP[35] bit 5-MAIN[41][29][26]
PLL_DRP[35] bit 6-MAIN[41][28][27]
PLL_DRP[35] bit 7-MAIN[41][29][27]
PLL_DRP[35] bit 8-MAIN[41][28][28]
PLL_DRP[35] bit 9-MAIN[41][29][28]
PLL_DRP[35] bit 10-MAIN[41][28][29]
PLL_DRP[35] bit 11-MAIN[41][29][29]
PLL_DRP[35] bit 12-MAIN[41][28][30]
PLL_DRP[35] bit 13-MAIN[41][29][30]
PLL_DRP[35] bit 14-MAIN[41][28][31]
PLL_DRP[35] bit 15-MAIN[41][29][31]
PLL_DRP[36] bit 0-MAIN[41][28][32]
PLL_DRP[36] bit 1-MAIN[41][29][32]
PLL_DRP[36] bit 2-MAIN[41][28][33]
PLL_DRP[36] bit 3-MAIN[41][29][33]
PLL_DRP[36] bit 4-MAIN[41][28][34]
PLL_DRP[36] bit 5-MAIN[41][29][34]
PLL_DRP[36] bit 6-MAIN[41][28][35]
PLL_DRP[36] bit 7-MAIN[41][29][35]
PLL_DRP[36] bit 8-MAIN[41][28][36]
PLL_DRP[36] bit 9-MAIN[41][29][36]
PLL_DRP[36] bit 10-MAIN[41][28][37]
PLL_DRP[36] bit 11-MAIN[41][29][37]
PLL_DRP[36] bit 12-MAIN[41][28][38]
PLL_DRP[36] bit 13-MAIN[41][29][38]
PLL_DRP[36] bit 14-MAIN[41][28][39]
PLL_DRP[36] bit 15-MAIN[41][29][39]
PLL_DRP[37] bit 0-MAIN[41][28][40]
PLL_DRP[37] bit 1-MAIN[41][29][40]
PLL_DRP[37] bit 2-MAIN[41][28][41]
PLL_DRP[37] bit 3-MAIN[41][29][41]
PLL_DRP[37] bit 4-MAIN[41][28][42]
PLL_DRP[37] bit 5-MAIN[41][29][42]
PLL_DRP[37] bit 6-MAIN[41][28][43]
PLL_DRP[37] bit 7-MAIN[41][29][43]
PLL_DRP[37] bit 8-MAIN[41][28][44]
PLL_DRP[37] bit 9-MAIN[41][29][44]
PLL_DRP[37] bit 10-MAIN[41][28][45]
PLL_DRP[37] bit 11-MAIN[41][29][45]
PLL_DRP[37] bit 12-MAIN[41][28][46]
PLL_DRP[37] bit 13-MAIN[41][29][46]
PLL_DRP[37] bit 14-MAIN[41][28][47]
PLL_DRP[37] bit 15-MAIN[41][29][47]
PLL_DRP[38] bit 0-MAIN[41][28][48]
PLL_DRP[38] bit 1-MAIN[41][29][48]
PLL_DRP[38] bit 2-MAIN[41][28][49]
PLL_DRP[38] bit 3-MAIN[41][29][49]
PLL_DRP[38] bit 4-MAIN[41][28][50]
PLL_DRP[38] bit 5-MAIN[41][29][50]
PLL_DRP[38] bit 6-MAIN[41][28][51]
PLL_DRP[38] bit 7-MAIN[41][29][51]
PLL_DRP[38] bit 8-MAIN[41][28][52]
PLL_DRP[38] bit 9-MAIN[41][29][52]
PLL_DRP[38] bit 10-MAIN[41][28][53]
PLL_DRP[38] bit 11-MAIN[41][29][53]
PLL_DRP[38] bit 12-MAIN[41][28][54]
PLL_DRP[38] bit 13-MAIN[41][29][54]
PLL_DRP[38] bit 14-MAIN[41][28][55]
PLL_DRP[38] bit 15-MAIN[41][29][55]
PLL_DRP[39] bit 0-MAIN[41][28][56]
PLL_DRP[39] bit 1-MAIN[41][29][56]
PLL_DRP[39] bit 2-MAIN[41][28][57]
PLL_DRP[39] bit 3-MAIN[41][29][57]
PLL_DRP[39] bit 4-MAIN[41][28][58]
PLL_DRP[39] bit 5-MAIN[41][29][58]
PLL_DRP[39] bit 6-MAIN[41][28][59]
PLL_DRP[39] bit 7-MAIN[41][29][59]
PLL_DRP[39] bit 8-MAIN[41][28][60]
PLL_DRP[39] bit 9-MAIN[41][29][60]
PLL_DRP[39] bit 10-MAIN[41][28][61]
PLL_DRP[39] bit 11-MAIN[41][29][61]
PLL_DRP[39] bit 12-MAIN[41][28][62]
PLL_DRP[39] bit 13-MAIN[41][29][62]
PLL_DRP[39] bit 14-MAIN[41][28][63]
PLL_DRP[39] bit 15-MAIN[41][29][63]
PLL_DRP[40] bit 0-MAIN[42][28][0]
PLL_DRP[40] bit 1-MAIN[42][29][0]
PLL_DRP[40] bit 2-MAIN[42][28][1]
PLL_DRP[40] bit 3-MAIN[42][29][1]
PLL_DRP[40] bit 4-MAIN[42][28][2]
PLL_DRP[40] bit 5-MAIN[42][29][2]
PLL_DRP[40] bit 6-MAIN[42][28][3]
PLL_DRP[40] bit 7-MAIN[42][29][3]
PLL_DRP[40] bit 8-MAIN[42][28][4]
PLL_DRP[40] bit 9-MAIN[42][29][4]
PLL_DRP[40] bit 10-MAIN[42][28][5]
PLL_DRP[40] bit 11-MAIN[42][29][5]
PLL_DRP[40] bit 12-MAIN[42][28][6]
PLL_DRP[40] bit 13-MAIN[42][29][6]
PLL_DRP[40] bit 14-MAIN[42][28][7]
PLL_DRP[40] bit 15-MAIN[42][29][7]
PLL_DRP[41] bit 0-MAIN[42][28][8]
PLL_DRP[41] bit 1-MAIN[42][29][8]
PLL_DRP[41] bit 2-MAIN[42][28][9]
PLL_DRP[41] bit 3-MAIN[42][29][9]
PLL_DRP[41] bit 4-MAIN[42][28][10]
PLL_DRP[41] bit 5-MAIN[42][29][10]
PLL_DRP[41] bit 6-MAIN[42][28][11]
PLL_DRP[41] bit 7-MAIN[42][29][11]
PLL_DRP[41] bit 8-MAIN[42][28][12]
PLL_DRP[41] bit 9-MAIN[42][29][12]
PLL_DRP[41] bit 10-MAIN[42][28][13]
PLL_DRP[41] bit 11-MAIN[42][29][13]
PLL_DRP[41] bit 12-MAIN[42][28][14]
PLL_DRP[41] bit 13-MAIN[42][29][14]
PLL_DRP[41] bit 14-MAIN[42][28][15]
PLL_DRP[41] bit 15-MAIN[42][29][15]
PLL_DRP[42] bit 0-MAIN[42][28][16]
PLL_DRP[42] bit 1-MAIN[42][29][16]
PLL_DRP[42] bit 2-MAIN[42][28][17]
PLL_DRP[42] bit 3-MAIN[42][29][17]
PLL_DRP[42] bit 4-MAIN[42][28][18]
PLL_DRP[42] bit 5-MAIN[42][29][18]
PLL_DRP[42] bit 6-MAIN[42][28][19]
PLL_DRP[42] bit 7-MAIN[42][29][19]
PLL_DRP[42] bit 8-MAIN[42][28][20]
PLL_DRP[42] bit 9-MAIN[42][29][20]
PLL_DRP[42] bit 10-MAIN[42][28][21]
PLL_DRP[42] bit 11-MAIN[42][29][21]
PLL_DRP[42] bit 12-MAIN[42][28][22]
PLL_DRP[42] bit 13-MAIN[42][29][22]
PLL_DRP[42] bit 14-MAIN[42][28][23]
PLL_DRP[42] bit 15-MAIN[42][29][23]
PLL_DRP[43] bit 0-MAIN[42][28][24]
PLL_DRP[43] bit 1-MAIN[42][29][24]
PLL_DRP[43] bit 2-MAIN[42][28][25]
PLL_DRP[43] bit 3-MAIN[42][29][25]
PLL_DRP[43] bit 4-MAIN[42][28][26]
PLL_DRP[43] bit 5-MAIN[42][29][26]
PLL_DRP[43] bit 6-MAIN[42][28][27]
PLL_DRP[43] bit 7-MAIN[42][29][27]
PLL_DRP[43] bit 8-MAIN[42][28][28]
PLL_DRP[43] bit 9-MAIN[42][29][28]
PLL_DRP[43] bit 10-MAIN[42][28][29]
PLL_DRP[43] bit 11-MAIN[42][29][29]
PLL_DRP[43] bit 12-MAIN[42][28][30]
PLL_DRP[43] bit 13-MAIN[42][29][30]
PLL_DRP[43] bit 14-MAIN[42][28][31]
PLL_DRP[43] bit 15-MAIN[42][29][31]
PLL_DRP[44] bit 0-MAIN[42][28][32]
PLL_DRP[44] bit 1-MAIN[42][29][32]
PLL_DRP[44] bit 2-MAIN[42][28][33]
PLL_DRP[44] bit 3-MAIN[42][29][33]
PLL_DRP[44] bit 4-MAIN[42][28][34]
PLL_DRP[44] bit 5-MAIN[42][29][34]
PLL_DRP[44] bit 6-MAIN[42][28][35]
PLL_DRP[44] bit 7-MAIN[42][29][35]
PLL_DRP[44] bit 8-MAIN[42][28][36]
PLL_DRP[44] bit 9-MAIN[42][29][36]
PLL_DRP[44] bit 10-MAIN[42][28][37]
PLL_DRP[44] bit 11-MAIN[42][29][37]
PLL_DRP[44] bit 12-MAIN[42][28][38]
PLL_DRP[44] bit 13-MAIN[42][29][38]
PLL_DRP[44] bit 14-MAIN[42][28][39]
PLL_DRP[44] bit 15-MAIN[42][29][39]
PLL_DRP[45] bit 0-MAIN[42][28][40]
PLL_DRP[45] bit 1-MAIN[42][29][40]
PLL_DRP[45] bit 2-MAIN[42][28][41]
PLL_DRP[45] bit 3-MAIN[42][29][41]
PLL_DRP[45] bit 4-MAIN[42][28][42]
PLL_DRP[45] bit 5-MAIN[42][29][42]
PLL_DRP[45] bit 6-MAIN[42][28][43]
PLL_DRP[45] bit 7-MAIN[42][29][43]
PLL_DRP[45] bit 8-MAIN[42][28][44]
PLL_DRP[45] bit 9-MAIN[42][29][44]
PLL_DRP[45] bit 10-MAIN[42][28][45]
PLL_DRP[45] bit 11-MAIN[42][29][45]
PLL_DRP[45] bit 12-MAIN[42][28][46]
PLL_DRP[45] bit 13-MAIN[42][29][46]
PLL_DRP[45] bit 14-MAIN[42][28][47]
PLL_DRP[45] bit 15-MAIN[42][29][47]
PLL_DRP[46] bit 0-MAIN[42][28][48]
PLL_DRP[46] bit 1-MAIN[42][29][48]
PLL_DRP[46] bit 2-MAIN[42][28][49]
PLL_DRP[46] bit 3-MAIN[42][29][49]
PLL_DRP[46] bit 4-MAIN[42][28][50]
PLL_DRP[46] bit 5-MAIN[42][29][50]
PLL_DRP[46] bit 6-MAIN[42][28][51]
PLL_DRP[46] bit 7-MAIN[42][29][51]
PLL_DRP[46] bit 8-MAIN[42][28][52]
PLL_DRP[46] bit 9-MAIN[42][29][52]
PLL_DRP[46] bit 10-MAIN[42][28][53]
PLL_DRP[46] bit 11-MAIN[42][29][53]
PLL_DRP[46] bit 12-MAIN[42][28][54]
PLL_DRP[46] bit 13-MAIN[42][29][54]
PLL_DRP[46] bit 14-MAIN[42][28][55]
PLL_DRP[46] bit 15-MAIN[42][29][55]
PLL_DRP[47] bit 0-MAIN[42][28][56]
PLL_DRP[47] bit 1-MAIN[42][29][56]
PLL_DRP[47] bit 2-MAIN[42][28][57]
PLL_DRP[47] bit 3-MAIN[42][29][57]
PLL_DRP[47] bit 4-MAIN[42][28][58]
PLL_DRP[47] bit 5-MAIN[42][29][58]
PLL_DRP[47] bit 6-MAIN[42][28][59]
PLL_DRP[47] bit 7-MAIN[42][29][59]
PLL_DRP[47] bit 8-MAIN[42][28][60]
PLL_DRP[47] bit 9-MAIN[42][29][60]
PLL_DRP[47] bit 10-MAIN[42][28][61]
PLL_DRP[47] bit 11-MAIN[42][29][61]
PLL_DRP[47] bit 12-MAIN[42][28][62]
PLL_DRP[47] bit 13-MAIN[42][29][62]
PLL_DRP[47] bit 14-MAIN[42][28][63]
PLL_DRP[47] bit 15-MAIN[42][29][63]
PLL_DRP[48] bit 0-MAIN[43][28][0]
PLL_DRP[48] bit 1-MAIN[43][29][0]
PLL_DRP[48] bit 2-MAIN[43][28][1]
PLL_DRP[48] bit 3-MAIN[43][29][1]
PLL_DRP[48] bit 4-MAIN[43][28][2]
PLL_DRP[48] bit 5-MAIN[43][29][2]
PLL_DRP[48] bit 6-MAIN[43][28][3]
PLL_DRP[48] bit 7-MAIN[43][29][3]
PLL_DRP[48] bit 8-MAIN[43][28][4]
PLL_DRP[48] bit 9-MAIN[43][29][4]
PLL_DRP[48] bit 10-MAIN[43][28][5]
PLL_DRP[48] bit 11-MAIN[43][29][5]
PLL_DRP[48] bit 12-MAIN[43][28][6]
PLL_DRP[48] bit 13-MAIN[43][29][6]
PLL_DRP[48] bit 14-MAIN[43][28][7]
PLL_DRP[48] bit 15-MAIN[43][29][7]
PLL_DRP[49] bit 0-MAIN[43][28][8]
PLL_DRP[49] bit 1-MAIN[43][29][8]
PLL_DRP[49] bit 2-MAIN[43][28][9]
PLL_DRP[49] bit 3-MAIN[43][29][9]
PLL_DRP[49] bit 4-MAIN[43][28][10]
PLL_DRP[49] bit 5-MAIN[43][29][10]
PLL_DRP[49] bit 6-MAIN[43][28][11]
PLL_DRP[49] bit 7-MAIN[43][29][11]
PLL_DRP[49] bit 8-MAIN[43][28][12]
PLL_DRP[49] bit 9-MAIN[43][29][12]
PLL_DRP[49] bit 10-MAIN[43][28][13]
PLL_DRP[49] bit 11-MAIN[43][29][13]
PLL_DRP[49] bit 12-MAIN[43][28][14]
PLL_DRP[49] bit 13-MAIN[43][29][14]
PLL_DRP[49] bit 14-MAIN[43][28][15]
PLL_DRP[49] bit 15-MAIN[43][29][15]
PLL_DRP[50] bit 0-MAIN[43][28][16]
PLL_DRP[50] bit 1-MAIN[43][29][16]
PLL_DRP[50] bit 2-MAIN[43][28][17]
PLL_DRP[50] bit 3-MAIN[43][29][17]
PLL_DRP[50] bit 4-MAIN[43][28][18]
PLL_DRP[50] bit 5-MAIN[43][29][18]
PLL_DRP[50] bit 6-MAIN[43][28][19]
PLL_DRP[50] bit 7-MAIN[43][29][19]
PLL_DRP[50] bit 8-MAIN[43][28][20]
PLL_DRP[50] bit 9-MAIN[43][29][20]
PLL_DRP[50] bit 10-MAIN[43][28][21]
PLL_DRP[50] bit 11-MAIN[43][29][21]
PLL_DRP[50] bit 12-MAIN[43][28][22]
PLL_DRP[50] bit 13-MAIN[43][29][22]
PLL_DRP[50] bit 14-MAIN[43][28][23]
PLL_DRP[50] bit 15-MAIN[43][29][23]
PLL_DRP[51] bit 0-MAIN[43][28][24]
PLL_DRP[51] bit 1-MAIN[43][29][24]
PLL_DRP[51] bit 2-MAIN[43][28][25]
PLL_DRP[51] bit 3-MAIN[43][29][25]
PLL_DRP[51] bit 4-MAIN[43][28][26]
PLL_DRP[51] bit 5-MAIN[43][29][26]
PLL_DRP[51] bit 6-MAIN[43][28][27]
PLL_DRP[51] bit 7-MAIN[43][29][27]
PLL_DRP[51] bit 8-MAIN[43][28][28]
PLL_DRP[51] bit 9-MAIN[43][29][28]
PLL_DRP[51] bit 10-MAIN[43][28][29]
PLL_DRP[51] bit 11-MAIN[43][29][29]
PLL_DRP[51] bit 12-MAIN[43][28][30]
PLL_DRP[51] bit 13-MAIN[43][29][30]
PLL_DRP[51] bit 14-MAIN[43][28][31]
PLL_DRP[51] bit 15-MAIN[43][29][31]
PLL_DRP[52] bit 0-MAIN[43][28][32]
PLL_DRP[52] bit 1-MAIN[43][29][32]
PLL_DRP[52] bit 2-MAIN[43][28][33]
PLL_DRP[52] bit 3-MAIN[43][29][33]
PLL_DRP[52] bit 4-MAIN[43][28][34]
PLL_DRP[52] bit 5-MAIN[43][29][34]
PLL_DRP[52] bit 6-MAIN[43][28][35]
PLL_DRP[52] bit 7-MAIN[43][29][35]
PLL_DRP[52] bit 8-MAIN[43][28][36]
PLL_DRP[52] bit 9-MAIN[43][29][36]
PLL_DRP[52] bit 10-MAIN[43][28][37]
PLL_DRP[52] bit 11-MAIN[43][29][37]
PLL_DRP[52] bit 12-MAIN[43][28][38]
PLL_DRP[52] bit 13-MAIN[43][29][38]
PLL_DRP[52] bit 14-MAIN[43][28][39]
PLL_DRP[52] bit 15-MAIN[43][29][39]
PLL_DRP[53] bit 0-MAIN[43][28][40]
PLL_DRP[53] bit 1-MAIN[43][29][40]
PLL_DRP[53] bit 2-MAIN[43][28][41]
PLL_DRP[53] bit 3-MAIN[43][29][41]
PLL_DRP[53] bit 4-MAIN[43][28][42]
PLL_DRP[53] bit 5-MAIN[43][29][42]
PLL_DRP[53] bit 6-MAIN[43][28][43]
PLL_DRP[53] bit 7-MAIN[43][29][43]
PLL_DRP[53] bit 8-MAIN[43][28][44]
PLL_DRP[53] bit 9-MAIN[43][29][44]
PLL_DRP[53] bit 10-MAIN[43][28][45]
PLL_DRP[53] bit 11-MAIN[43][29][45]
PLL_DRP[53] bit 12-MAIN[43][28][46]
PLL_DRP[53] bit 13-MAIN[43][29][46]
PLL_DRP[53] bit 14-MAIN[43][28][47]
PLL_DRP[53] bit 15-MAIN[43][29][47]
PLL_DRP[54] bit 0-MAIN[43][28][48]
PLL_DRP[54] bit 1-MAIN[43][29][48]
PLL_DRP[54] bit 2-MAIN[43][28][49]
PLL_DRP[54] bit 3-MAIN[43][29][49]
PLL_DRP[54] bit 4-MAIN[43][28][50]
PLL_DRP[54] bit 5-MAIN[43][29][50]
PLL_DRP[54] bit 6-MAIN[43][28][51]
PLL_DRP[54] bit 7-MAIN[43][29][51]
PLL_DRP[54] bit 8-MAIN[43][28][52]
PLL_DRP[54] bit 9-MAIN[43][29][52]
PLL_DRP[54] bit 10-MAIN[43][28][53]
PLL_DRP[54] bit 11-MAIN[43][29][53]
PLL_DRP[54] bit 12-MAIN[43][28][54]
PLL_DRP[54] bit 13-MAIN[43][29][54]
PLL_DRP[54] bit 14-MAIN[43][28][55]
PLL_DRP[54] bit 15-MAIN[43][29][55]
PLL_DRP[55] bit 0-MAIN[43][28][56]
PLL_DRP[55] bit 1-MAIN[43][29][56]
PLL_DRP[55] bit 2-MAIN[43][28][57]
PLL_DRP[55] bit 3-MAIN[43][29][57]
PLL_DRP[55] bit 4-MAIN[43][28][58]
PLL_DRP[55] bit 5-MAIN[43][29][58]
PLL_DRP[55] bit 6-MAIN[43][28][59]
PLL_DRP[55] bit 7-MAIN[43][29][59]
PLL_DRP[55] bit 8-MAIN[43][28][60]
PLL_DRP[55] bit 9-MAIN[43][29][60]
PLL_DRP[55] bit 10-MAIN[43][28][61]
PLL_DRP[55] bit 11-MAIN[43][29][61]
PLL_DRP[55] bit 12-MAIN[43][28][62]
PLL_DRP[55] bit 13-MAIN[43][29][62]
PLL_DRP[55] bit 14-MAIN[43][28][63]
PLL_DRP[55] bit 15-MAIN[43][29][63]
PLL_DRP[56] bit 0-MAIN[44][28][0]
PLL_DRP[56] bit 1-MAIN[44][29][0]
PLL_DRP[56] bit 2-MAIN[44][28][1]
PLL_DRP[56] bit 3-MAIN[44][29][1]
PLL_DRP[56] bit 4-MAIN[44][28][2]
PLL_DRP[56] bit 5-MAIN[44][29][2]
PLL_DRP[56] bit 6-MAIN[44][28][3]
PLL_DRP[56] bit 7-MAIN[44][29][3]
PLL_DRP[56] bit 8-MAIN[44][28][4]
PLL_DRP[56] bit 9-MAIN[44][29][4]
PLL_DRP[56] bit 10-MAIN[44][28][5]
PLL_DRP[56] bit 11-MAIN[44][29][5]
PLL_DRP[56] bit 12-MAIN[44][28][6]
PLL_DRP[56] bit 13-MAIN[44][29][6]
PLL_DRP[56] bit 14-MAIN[44][28][7]
PLL_DRP[56] bit 15-MAIN[44][29][7]
PLL_DRP[57] bit 0-MAIN[44][28][8]
PLL_DRP[57] bit 1-MAIN[44][29][8]
PLL_DRP[57] bit 2-MAIN[44][28][9]
PLL_DRP[57] bit 3-MAIN[44][29][9]
PLL_DRP[57] bit 4-MAIN[44][28][10]
PLL_DRP[57] bit 5-MAIN[44][29][10]
PLL_DRP[57] bit 6-MAIN[44][28][11]
PLL_DRP[57] bit 7-MAIN[44][29][11]
PLL_DRP[57] bit 8-MAIN[44][28][12]
PLL_DRP[57] bit 9-MAIN[44][29][12]
PLL_DRP[57] bit 10-MAIN[44][28][13]
PLL_DRP[57] bit 11-MAIN[44][29][13]
PLL_DRP[57] bit 12-MAIN[44][28][14]
PLL_DRP[57] bit 13-MAIN[44][29][14]
PLL_DRP[57] bit 14-MAIN[44][28][15]
PLL_DRP[57] bit 15-MAIN[44][29][15]
PLL_DRP[58] bit 0-MAIN[44][28][16]
PLL_DRP[58] bit 1-MAIN[44][29][16]
PLL_DRP[58] bit 2-MAIN[44][28][17]
PLL_DRP[58] bit 3-MAIN[44][29][17]
PLL_DRP[58] bit 4-MAIN[44][28][18]
PLL_DRP[58] bit 5-MAIN[44][29][18]
PLL_DRP[58] bit 6-MAIN[44][28][19]
PLL_DRP[58] bit 7-MAIN[44][29][19]
PLL_DRP[58] bit 8-MAIN[44][28][20]
PLL_DRP[58] bit 9-MAIN[44][29][20]
PLL_DRP[58] bit 10-MAIN[44][28][21]
PLL_DRP[58] bit 11-MAIN[44][29][21]
PLL_DRP[58] bit 12-MAIN[44][28][22]
PLL_DRP[58] bit 13-MAIN[44][29][22]
PLL_DRP[58] bit 14-MAIN[44][28][23]
PLL_DRP[58] bit 15-MAIN[44][29][23]
PLL_DRP[59] bit 0-MAIN[44][28][24]
PLL_DRP[59] bit 1-MAIN[44][29][24]
PLL_DRP[59] bit 2-MAIN[44][28][25]
PLL_DRP[59] bit 3-MAIN[44][29][25]
PLL_DRP[59] bit 4-MAIN[44][28][26]
PLL_DRP[59] bit 5-MAIN[44][29][26]
PLL_DRP[59] bit 6-MAIN[44][28][27]
PLL_DRP[59] bit 7-MAIN[44][29][27]
PLL_DRP[59] bit 8-MAIN[44][28][28]
PLL_DRP[59] bit 9-MAIN[44][29][28]
PLL_DRP[59] bit 10-MAIN[44][28][29]
PLL_DRP[59] bit 11-MAIN[44][29][29]
PLL_DRP[59] bit 12-MAIN[44][28][30]
PLL_DRP[59] bit 13-MAIN[44][29][30]
PLL_DRP[59] bit 14-MAIN[44][28][31]
PLL_DRP[59] bit 15-MAIN[44][29][31]
PLL_DRP[60] bit 0-MAIN[44][28][32]
PLL_DRP[60] bit 1-MAIN[44][29][32]
PLL_DRP[60] bit 2-MAIN[44][28][33]
PLL_DRP[60] bit 3-MAIN[44][29][33]
PLL_DRP[60] bit 4-MAIN[44][28][34]
PLL_DRP[60] bit 5-MAIN[44][29][34]
PLL_DRP[60] bit 6-MAIN[44][28][35]
PLL_DRP[60] bit 7-MAIN[44][29][35]
PLL_DRP[60] bit 8-MAIN[44][28][36]
PLL_DRP[60] bit 9-MAIN[44][29][36]
PLL_DRP[60] bit 10-MAIN[44][28][37]
PLL_DRP[60] bit 11-MAIN[44][29][37]
PLL_DRP[60] bit 12-MAIN[44][28][38]
PLL_DRP[60] bit 13-MAIN[44][29][38]
PLL_DRP[60] bit 14-MAIN[44][28][39]
PLL_DRP[60] bit 15-MAIN[44][29][39]
PLL_DRP[61] bit 0-MAIN[44][28][40]
PLL_DRP[61] bit 1-MAIN[44][29][40]
PLL_DRP[61] bit 2-MAIN[44][28][41]
PLL_DRP[61] bit 3-MAIN[44][29][41]
PLL_DRP[61] bit 4-MAIN[44][28][42]
PLL_DRP[61] bit 5-MAIN[44][29][42]
PLL_DRP[61] bit 6-MAIN[44][28][43]
PLL_DRP[61] bit 7-MAIN[44][29][43]
PLL_DRP[61] bit 8-MAIN[44][28][44]
PLL_DRP[61] bit 9-MAIN[44][29][44]
PLL_DRP[61] bit 10-MAIN[44][28][45]
PLL_DRP[61] bit 11-MAIN[44][29][45]
PLL_DRP[61] bit 12-MAIN[44][28][46]
PLL_DRP[61] bit 13-MAIN[44][29][46]
PLL_DRP[61] bit 14-MAIN[44][28][47]
PLL_DRP[61] bit 15-MAIN[44][29][47]
PLL_DRP[62] bit 0-MAIN[44][28][48]
PLL_DRP[62] bit 1-MAIN[44][29][48]
PLL_DRP[62] bit 2-MAIN[44][28][49]
PLL_DRP[62] bit 3-MAIN[44][29][49]
PLL_DRP[62] bit 4-MAIN[44][28][50]
PLL_DRP[62] bit 5-MAIN[44][29][50]
PLL_DRP[62] bit 6-MAIN[44][28][51]
PLL_DRP[62] bit 7-MAIN[44][29][51]
PLL_DRP[62] bit 8-MAIN[44][28][52]
PLL_DRP[62] bit 9-MAIN[44][29][52]
PLL_DRP[62] bit 10-MAIN[44][28][53]
PLL_DRP[62] bit 11-MAIN[44][29][53]
PLL_DRP[62] bit 12-MAIN[44][28][54]
PLL_DRP[62] bit 13-MAIN[44][29][54]
PLL_DRP[62] bit 14-MAIN[44][28][55]
PLL_DRP[62] bit 15-MAIN[44][29][55]
PLL_DRP[63] bit 0-MAIN[44][28][56]
PLL_DRP[63] bit 1-MAIN[44][29][56]
PLL_DRP[63] bit 2-MAIN[44][28][57]
PLL_DRP[63] bit 3-MAIN[44][29][57]
PLL_DRP[63] bit 4-MAIN[44][28][58]
PLL_DRP[63] bit 5-MAIN[44][29][58]
PLL_DRP[63] bit 6-MAIN[44][28][59]
PLL_DRP[63] bit 7-MAIN[44][29][59]
PLL_DRP[63] bit 8-MAIN[44][28][60]
PLL_DRP[63] bit 9-MAIN[44][29][60]
PLL_DRP[63] bit 10-MAIN[44][28][61]
PLL_DRP[63] bit 11-MAIN[44][29][61]
PLL_DRP[63] bit 12-MAIN[44][28][62]
PLL_DRP[63] bit 13-MAIN[44][29][62]
PLL_DRP[63] bit 14-MAIN[44][28][63]
PLL_DRP[63] bit 15-MAIN[44][29][63]
PLL_DRP[64] bit 0-MAIN[45][28][0]
PLL_DRP[64] bit 1-MAIN[45][29][0]
PLL_DRP[64] bit 2-MAIN[45][28][1]
PLL_DRP[64] bit 3-MAIN[45][29][1]
PLL_DRP[64] bit 4-MAIN[45][28][2]
PLL_DRP[64] bit 5-MAIN[45][29][2]
PLL_DRP[64] bit 6-MAIN[45][28][3]
PLL_DRP[64] bit 7-MAIN[45][29][3]
PLL_DRP[64] bit 8-MAIN[45][28][4]
PLL_DRP[64] bit 9-MAIN[45][29][4]
PLL_DRP[64] bit 10-MAIN[45][28][5]
PLL_DRP[64] bit 11-MAIN[45][29][5]
PLL_DRP[64] bit 12-MAIN[45][28][6]
PLL_DRP[64] bit 13-MAIN[45][29][6]
PLL_DRP[64] bit 14-MAIN[45][28][7]
PLL_DRP[64] bit 15-MAIN[45][29][7]
PLL_DRP[65] bit 0-MAIN[45][28][8]
PLL_DRP[65] bit 1-MAIN[45][29][8]
PLL_DRP[65] bit 2-MAIN[45][28][9]
PLL_DRP[65] bit 3-MAIN[45][29][9]
PLL_DRP[65] bit 4-MAIN[45][28][10]
PLL_DRP[65] bit 5-MAIN[45][29][10]
PLL_DRP[65] bit 6-MAIN[45][28][11]
PLL_DRP[65] bit 7-MAIN[45][29][11]
PLL_DRP[65] bit 8-MAIN[45][28][12]
PLL_DRP[65] bit 9-MAIN[45][29][12]
PLL_DRP[65] bit 10-MAIN[45][28][13]
PLL_DRP[65] bit 11-MAIN[45][29][13]
PLL_DRP[65] bit 12-MAIN[45][28][14]
PLL_DRP[65] bit 13-MAIN[45][29][14]
PLL_DRP[65] bit 14-MAIN[45][28][15]
PLL_DRP[65] bit 15-MAIN[45][29][15]
PLL_DRP[66] bit 0-MAIN[45][28][16]
PLL_DRP[66] bit 1-MAIN[45][29][16]
PLL_DRP[66] bit 2-MAIN[45][28][17]
PLL_DRP[66] bit 3-MAIN[45][29][17]
PLL_DRP[66] bit 4-MAIN[45][28][18]
PLL_DRP[66] bit 5-MAIN[45][29][18]
PLL_DRP[66] bit 6-MAIN[45][28][19]
PLL_DRP[66] bit 7-MAIN[45][29][19]
PLL_DRP[66] bit 8-MAIN[45][28][20]
PLL_DRP[66] bit 9-MAIN[45][29][20]
PLL_DRP[66] bit 10-MAIN[45][28][21]
PLL_DRP[66] bit 11-MAIN[45][29][21]
PLL_DRP[66] bit 12-MAIN[45][28][22]
PLL_DRP[66] bit 13-MAIN[45][29][22]
PLL_DRP[66] bit 14-MAIN[45][28][23]
PLL_DRP[66] bit 15-MAIN[45][29][23]
PLL_DRP[67] bit 0-MAIN[45][28][24]
PLL_DRP[67] bit 1-MAIN[45][29][24]
PLL_DRP[67] bit 2-MAIN[45][28][25]
PLL_DRP[67] bit 3-MAIN[45][29][25]
PLL_DRP[67] bit 4-MAIN[45][28][26]
PLL_DRP[67] bit 5-MAIN[45][29][26]
PLL_DRP[67] bit 6-MAIN[45][28][27]
PLL_DRP[67] bit 7-MAIN[45][29][27]
PLL_DRP[67] bit 8-MAIN[45][28][28]
PLL_DRP[67] bit 9-MAIN[45][29][28]
PLL_DRP[67] bit 10-MAIN[45][28][29]
PLL_DRP[67] bit 11-MAIN[45][29][29]
PLL_DRP[67] bit 12-MAIN[45][28][30]
PLL_DRP[67] bit 13-MAIN[45][29][30]
PLL_DRP[67] bit 14-MAIN[45][28][31]
PLL_DRP[67] bit 15-MAIN[45][29][31]
PLL_DRP[68] bit 0-MAIN[45][28][32]
PLL_DRP[68] bit 1-MAIN[45][29][32]
PLL_DRP[68] bit 2-MAIN[45][28][33]
PLL_DRP[68] bit 3-MAIN[45][29][33]
PLL_DRP[68] bit 4-MAIN[45][28][34]
PLL_DRP[68] bit 5-MAIN[45][29][34]
PLL_DRP[68] bit 6-MAIN[45][28][35]
PLL_DRP[68] bit 7-MAIN[45][29][35]
PLL_DRP[68] bit 8-MAIN[45][28][36]
PLL_DRP[68] bit 9-MAIN[45][29][36]
PLL_DRP[68] bit 10-MAIN[45][28][37]
PLL_DRP[68] bit 11-MAIN[45][29][37]
PLL_DRP[68] bit 12-MAIN[45][28][38]
PLL_DRP[68] bit 13-MAIN[45][29][38]
PLL_DRP[68] bit 14-MAIN[45][28][39]
PLL_DRP[68] bit 15-MAIN[45][29][39]
PLL_DRP[69] bit 0-MAIN[45][28][40]
PLL_DRP[69] bit 1-MAIN[45][29][40]
PLL_DRP[69] bit 2-MAIN[45][28][41]
PLL_DRP[69] bit 3-MAIN[45][29][41]
PLL_DRP[69] bit 4-MAIN[45][28][42]
PLL_DRP[69] bit 5-MAIN[45][29][42]
PLL_DRP[69] bit 6-MAIN[45][28][43]
PLL_DRP[69] bit 7-MAIN[45][29][43]
PLL_DRP[69] bit 8-MAIN[45][28][44]
PLL_DRP[69] bit 9-MAIN[45][29][44]
PLL_DRP[69] bit 10-MAIN[45][28][45]
PLL_DRP[69] bit 11-MAIN[45][29][45]
PLL_DRP[69] bit 12-MAIN[45][28][46]
PLL_DRP[69] bit 13-MAIN[45][29][46]
PLL_DRP[69] bit 14-MAIN[45][28][47]
PLL_DRP[69] bit 15-MAIN[45][29][47]
PLL_DRP[70] bit 0-MAIN[45][28][48]
PLL_DRP[70] bit 1-MAIN[45][29][48]
PLL_DRP[70] bit 2-MAIN[45][28][49]
PLL_DRP[70] bit 3-MAIN[45][29][49]
PLL_DRP[70] bit 4-MAIN[45][28][50]
PLL_DRP[70] bit 5-MAIN[45][29][50]
PLL_DRP[70] bit 6-MAIN[45][28][51]
PLL_DRP[70] bit 7-MAIN[45][29][51]
PLL_DRP[70] bit 8-MAIN[45][28][52]
PLL_DRP[70] bit 9-MAIN[45][29][52]
PLL_DRP[70] bit 10-MAIN[45][28][53]
PLL_DRP[70] bit 11-MAIN[45][29][53]
PLL_DRP[70] bit 12-MAIN[45][28][54]
PLL_DRP[70] bit 13-MAIN[45][29][54]
PLL_DRP[70] bit 14-MAIN[45][28][55]
PLL_DRP[70] bit 15-MAIN[45][29][55]
PLL_DRP[71] bit 0-MAIN[45][28][56]
PLL_DRP[71] bit 1-MAIN[45][29][56]
PLL_DRP[71] bit 2-MAIN[45][28][57]
PLL_DRP[71] bit 3-MAIN[45][29][57]
PLL_DRP[71] bit 4-MAIN[45][28][58]
PLL_DRP[71] bit 5-MAIN[45][29][58]
PLL_DRP[71] bit 6-MAIN[45][28][59]
PLL_DRP[71] bit 7-MAIN[45][29][59]
PLL_DRP[71] bit 8-MAIN[45][28][60]
PLL_DRP[71] bit 9-MAIN[45][29][60]
PLL_DRP[71] bit 10-MAIN[45][28][61]
PLL_DRP[71] bit 11-MAIN[45][29][61]
PLL_DRP[71] bit 12-MAIN[45][28][62]
PLL_DRP[71] bit 13-MAIN[45][29][62]
PLL_DRP[71] bit 14-MAIN[45][28][63]
PLL_DRP[71] bit 15-MAIN[45][29][63]
PLL_DRP[72] bit 0-MAIN[46][28][0]
PLL_DRP[72] bit 1-MAIN[46][29][0]
PLL_DRP[72] bit 2-MAIN[46][28][1]
PLL_DRP[72] bit 3-MAIN[46][29][1]
PLL_DRP[72] bit 4-MAIN[46][28][2]
PLL_DRP[72] bit 5-MAIN[46][29][2]
PLL_DRP[72] bit 6-MAIN[46][28][3]
PLL_DRP[72] bit 7-MAIN[46][29][3]
PLL_DRP[72] bit 8-MAIN[46][28][4]
PLL_DRP[72] bit 9-MAIN[46][29][4]
PLL_DRP[72] bit 10-MAIN[46][28][5]
PLL_DRP[72] bit 11-MAIN[46][29][5]
PLL_DRP[72] bit 12-MAIN[46][28][6]
PLL_DRP[72] bit 13-MAIN[46][29][6]
PLL_DRP[72] bit 14-MAIN[46][28][7]
PLL_DRP[72] bit 15-MAIN[46][29][7]
PLL_DRP[73] bit 0-MAIN[46][28][8]
PLL_DRP[73] bit 1-MAIN[46][29][8]
PLL_DRP[73] bit 2-MAIN[46][28][9]
PLL_DRP[73] bit 3-MAIN[46][29][9]
PLL_DRP[73] bit 4-MAIN[46][28][10]
PLL_DRP[73] bit 5-MAIN[46][29][10]
PLL_DRP[73] bit 6-MAIN[46][28][11]
PLL_DRP[73] bit 7-MAIN[46][29][11]
PLL_DRP[73] bit 8-MAIN[46][28][12]
PLL_DRP[73] bit 9-MAIN[46][29][12]
PLL_DRP[73] bit 10-MAIN[46][28][13]
PLL_DRP[73] bit 11-MAIN[46][29][13]
PLL_DRP[73] bit 12-MAIN[46][28][14]
PLL_DRP[73] bit 13-MAIN[46][29][14]
PLL_DRP[73] bit 14-MAIN[46][28][15]
PLL_DRP[73] bit 15-MAIN[46][29][15]
PLL_DRP[74] bit 0-MAIN[46][28][16]
PLL_DRP[74] bit 1-MAIN[46][29][16]
PLL_DRP[74] bit 2-MAIN[46][28][17]
PLL_DRP[74] bit 3-MAIN[46][29][17]
PLL_DRP[74] bit 4-MAIN[46][28][18]
PLL_DRP[74] bit 5-MAIN[46][29][18]
PLL_DRP[74] bit 6-MAIN[46][28][19]
PLL_DRP[74] bit 7-MAIN[46][29][19]
PLL_DRP[74] bit 8-MAIN[46][28][20]
PLL_DRP[74] bit 9-MAIN[46][29][20]
PLL_DRP[74] bit 10-MAIN[46][28][21]
PLL_DRP[74] bit 11-MAIN[46][29][21]
PLL_DRP[74] bit 12-MAIN[46][28][22]
PLL_DRP[74] bit 13-MAIN[46][29][22]
PLL_DRP[74] bit 14-MAIN[46][28][23]
PLL_DRP[74] bit 15-MAIN[46][29][23]
PLL_DRP[75] bit 0-MAIN[46][28][24]
PLL_DRP[75] bit 1-MAIN[46][29][24]
PLL_DRP[75] bit 2-MAIN[46][28][25]
PLL_DRP[75] bit 3-MAIN[46][29][25]
PLL_DRP[75] bit 4-MAIN[46][28][26]
PLL_DRP[75] bit 5-MAIN[46][29][26]
PLL_DRP[75] bit 6-MAIN[46][28][27]
PLL_DRP[75] bit 7-MAIN[46][29][27]
PLL_DRP[75] bit 8-MAIN[46][28][28]
PLL_DRP[75] bit 9-MAIN[46][29][28]
PLL_DRP[75] bit 10-MAIN[46][28][29]
PLL_DRP[75] bit 11-MAIN[46][29][29]
PLL_DRP[75] bit 12-MAIN[46][28][30]
PLL_DRP[75] bit 13-MAIN[46][29][30]
PLL_DRP[75] bit 14-MAIN[46][28][31]
PLL_DRP[75] bit 15-MAIN[46][29][31]
PLL_DRP[76] bit 0-MAIN[46][28][32]
PLL_DRP[76] bit 1-MAIN[46][29][32]
PLL_DRP[76] bit 2-MAIN[46][28][33]
PLL_DRP[76] bit 3-MAIN[46][29][33]
PLL_DRP[76] bit 4-MAIN[46][28][34]
PLL_DRP[76] bit 5-MAIN[46][29][34]
PLL_DRP[76] bit 6-MAIN[46][28][35]
PLL_DRP[76] bit 7-MAIN[46][29][35]
PLL_DRP[76] bit 8-MAIN[46][28][36]
PLL_DRP[76] bit 9-MAIN[46][29][36]
PLL_DRP[76] bit 10-MAIN[46][28][37]
PLL_DRP[76] bit 11-MAIN[46][29][37]
PLL_DRP[76] bit 12-MAIN[46][28][38]
PLL_DRP[76] bit 13-MAIN[46][29][38]
PLL_DRP[76] bit 14-MAIN[46][28][39]
PLL_DRP[76] bit 15-MAIN[46][29][39]
PLL_DRP[77] bit 0-MAIN[46][28][40]
PLL_DRP[77] bit 1-MAIN[46][29][40]
PLL_DRP[77] bit 2-MAIN[46][28][41]
PLL_DRP[77] bit 3-MAIN[46][29][41]
PLL_DRP[77] bit 4-MAIN[46][28][42]
PLL_DRP[77] bit 5-MAIN[46][29][42]
PLL_DRP[77] bit 6-MAIN[46][28][43]
PLL_DRP[77] bit 7-MAIN[46][29][43]
PLL_DRP[77] bit 8-MAIN[46][28][44]
PLL_DRP[77] bit 9-MAIN[46][29][44]
PLL_DRP[77] bit 10-MAIN[46][28][45]
PLL_DRP[77] bit 11-MAIN[46][29][45]
PLL_DRP[77] bit 12-MAIN[46][28][46]
PLL_DRP[77] bit 13-MAIN[46][29][46]
PLL_DRP[77] bit 14-MAIN[46][28][47]
PLL_DRP[77] bit 15-MAIN[46][29][47]
PLL_DRP[78] bit 0-MAIN[46][28][48]
PLL_DRP[78] bit 1-MAIN[46][29][48]
PLL_DRP[78] bit 2-MAIN[46][28][49]
PLL_DRP[78] bit 3-MAIN[46][29][49]
PLL_DRP[78] bit 4-MAIN[46][28][50]
PLL_DRP[78] bit 5-MAIN[46][29][50]
PLL_DRP[78] bit 6-MAIN[46][28][51]
PLL_DRP[78] bit 7-MAIN[46][29][51]
PLL_DRP[78] bit 8-MAIN[46][28][52]
PLL_DRP[78] bit 9-MAIN[46][29][52]
PLL_DRP[78] bit 10-MAIN[46][28][53]
PLL_DRP[78] bit 11-MAIN[46][29][53]
PLL_DRP[78] bit 12-MAIN[46][28][54]
PLL_DRP[78] bit 13-MAIN[46][29][54]
PLL_DRP[78] bit 14-MAIN[46][28][55]
PLL_DRP[78] bit 15-MAIN[46][29][55]
PLL_DRP[79] bit 0-MAIN[46][28][56]
PLL_DRP[79] bit 1-MAIN[46][29][56]
PLL_DRP[79] bit 2-MAIN[46][28][57]
PLL_DRP[79] bit 3-MAIN[46][29][57]
PLL_DRP[79] bit 4-MAIN[46][28][58]
PLL_DRP[79] bit 5-MAIN[46][29][58]
PLL_DRP[79] bit 6-MAIN[46][28][59]
PLL_DRP[79] bit 7-MAIN[46][29][59]
PLL_DRP[79] bit 8-MAIN[46][28][60]
PLL_DRP[79] bit 9-MAIN[46][29][60]
PLL_DRP[79] bit 10-MAIN[46][28][61]
PLL_DRP[79] bit 11-MAIN[46][29][61]
PLL_DRP[79] bit 12-MAIN[46][28][62]
PLL_DRP[79] bit 13-MAIN[46][29][62]
PLL_DRP[79] bit 14-MAIN[46][28][63]
PLL_DRP[79] bit 15-MAIN[46][29][63]
PLL_DRP[80] bit 0-MAIN[47][28][0]
PLL_DRP[80] bit 1-MAIN[47][29][0]
PLL_DRP[80] bit 2-MAIN[47][28][1]
PLL_DRP[80] bit 3-MAIN[47][29][1]
PLL_DRP[80] bit 4-MAIN[47][28][2]
PLL_DRP[80] bit 5-MAIN[47][29][2]
PLL_DRP[80] bit 6-MAIN[47][28][3]
PLL_DRP[80] bit 7-MAIN[47][29][3]
PLL_DRP[80] bit 8-MAIN[47][28][4]
PLL_DRP[80] bit 9-MAIN[47][29][4]
PLL_DRP[80] bit 10-MAIN[47][28][5]
PLL_DRP[80] bit 11-MAIN[47][29][5]
PLL_DRP[80] bit 12-MAIN[47][28][6]
PLL_DRP[80] bit 13-MAIN[47][29][6]
PLL_DRP[80] bit 14-MAIN[47][28][7]
PLL_DRP[80] bit 15-MAIN[47][29][7]
PLL_DRP[81] bit 0-MAIN[47][28][8]
PLL_DRP[81] bit 1-MAIN[47][29][8]
PLL_DRP[81] bit 2-MAIN[47][28][9]
PLL_DRP[81] bit 3-MAIN[47][29][9]
PLL_DRP[81] bit 4-MAIN[47][28][10]
PLL_DRP[81] bit 5-MAIN[47][29][10]
PLL_DRP[81] bit 6-MAIN[47][28][11]
PLL_DRP[81] bit 7-MAIN[47][29][11]
PLL_DRP[81] bit 8-MAIN[47][28][12]
PLL_DRP[81] bit 9-MAIN[47][29][12]
PLL_DRP[81] bit 10-MAIN[47][28][13]
PLL_DRP[81] bit 11-MAIN[47][29][13]
PLL_DRP[81] bit 12-MAIN[47][28][14]
PLL_DRP[81] bit 13-MAIN[47][29][14]
PLL_DRP[81] bit 14-MAIN[47][28][15]
PLL_DRP[81] bit 15-MAIN[47][29][15]
PLL_DRP[82] bit 0-MAIN[47][28][16]
PLL_DRP[82] bit 1-MAIN[47][29][16]
PLL_DRP[82] bit 2-MAIN[47][28][17]
PLL_DRP[82] bit 3-MAIN[47][29][17]
PLL_DRP[82] bit 4-MAIN[47][28][18]
PLL_DRP[82] bit 5-MAIN[47][29][18]
PLL_DRP[82] bit 6-MAIN[47][28][19]
PLL_DRP[82] bit 7-MAIN[47][29][19]
PLL_DRP[82] bit 8-MAIN[47][28][20]
PLL_DRP[82] bit 9-MAIN[47][29][20]
PLL_DRP[82] bit 10-MAIN[47][28][21]
PLL_DRP[82] bit 11-MAIN[47][29][21]
PLL_DRP[82] bit 12-MAIN[47][28][22]
PLL_DRP[82] bit 13-MAIN[47][29][22]
PLL_DRP[82] bit 14-MAIN[47][28][23]
PLL_DRP[82] bit 15-MAIN[47][29][23]
PLL_DRP[83] bit 0-MAIN[47][28][24]
PLL_DRP[83] bit 1-MAIN[47][29][24]
PLL_DRP[83] bit 2-MAIN[47][28][25]
PLL_DRP[83] bit 3-MAIN[47][29][25]
PLL_DRP[83] bit 4-MAIN[47][28][26]
PLL_DRP[83] bit 5-MAIN[47][29][26]
PLL_DRP[83] bit 6-MAIN[47][28][27]
PLL_DRP[83] bit 7-MAIN[47][29][27]
PLL_DRP[83] bit 8-MAIN[47][28][28]
PLL_DRP[83] bit 9-MAIN[47][29][28]
PLL_DRP[83] bit 10-MAIN[47][28][29]
PLL_DRP[83] bit 11-MAIN[47][29][29]
PLL_DRP[83] bit 12-MAIN[47][28][30]
PLL_DRP[83] bit 13-MAIN[47][29][30]
PLL_DRP[83] bit 14-MAIN[47][28][31]
PLL_DRP[83] bit 15-MAIN[47][29][31]
PLL_DRP[84] bit 0-MAIN[47][28][32]
PLL_DRP[84] bit 1-MAIN[47][29][32]
PLL_DRP[84] bit 2-MAIN[47][28][33]
PLL_DRP[84] bit 3-MAIN[47][29][33]
PLL_DRP[84] bit 4-MAIN[47][28][34]
PLL_DRP[84] bit 5-MAIN[47][29][34]
PLL_DRP[84] bit 6-MAIN[47][28][35]
PLL_DRP[84] bit 7-MAIN[47][29][35]
PLL_DRP[84] bit 8-MAIN[47][28][36]
PLL_DRP[84] bit 9-MAIN[47][29][36]
PLL_DRP[84] bit 10-MAIN[47][28][37]
PLL_DRP[84] bit 11-MAIN[47][29][37]
PLL_DRP[84] bit 12-MAIN[47][28][38]
PLL_DRP[84] bit 13-MAIN[47][29][38]
PLL_DRP[84] bit 14-MAIN[47][28][39]
PLL_DRP[84] bit 15-MAIN[47][29][39]
PLL_DRP[85] bit 0-MAIN[47][28][40]
PLL_DRP[85] bit 1-MAIN[47][29][40]
PLL_DRP[85] bit 2-MAIN[47][28][41]
PLL_DRP[85] bit 3-MAIN[47][29][41]
PLL_DRP[85] bit 4-MAIN[47][28][42]
PLL_DRP[85] bit 5-MAIN[47][29][42]
PLL_DRP[85] bit 6-MAIN[47][28][43]
PLL_DRP[85] bit 7-MAIN[47][29][43]
PLL_DRP[85] bit 8-MAIN[47][28][44]
PLL_DRP[85] bit 9-MAIN[47][29][44]
PLL_DRP[85] bit 10-MAIN[47][28][45]
PLL_DRP[85] bit 11-MAIN[47][29][45]
PLL_DRP[85] bit 12-MAIN[47][28][46]
PLL_DRP[85] bit 13-MAIN[47][29][46]
PLL_DRP[85] bit 14-MAIN[47][28][47]
PLL_DRP[85] bit 15-MAIN[47][29][47]
PLL_DRP[86] bit 0-MAIN[47][28][48]
PLL_DRP[86] bit 1-MAIN[47][29][48]
PLL_DRP[86] bit 2-MAIN[47][28][49]
PLL_DRP[86] bit 3-MAIN[47][29][49]
PLL_DRP[86] bit 4-MAIN[47][28][50]
PLL_DRP[86] bit 5-MAIN[47][29][50]
PLL_DRP[86] bit 6-MAIN[47][28][51]
PLL_DRP[86] bit 7-MAIN[47][29][51]
PLL_DRP[86] bit 8-MAIN[47][28][52]
PLL_DRP[86] bit 9-MAIN[47][29][52]
PLL_DRP[86] bit 10-MAIN[47][28][53]
PLL_DRP[86] bit 11-MAIN[47][29][53]
PLL_DRP[86] bit 12-MAIN[47][28][54]
PLL_DRP[86] bit 13-MAIN[47][29][54]
PLL_DRP[86] bit 14-MAIN[47][28][55]
PLL_DRP[86] bit 15-MAIN[47][29][55]
PLL_DRP[87] bit 0-MAIN[47][28][56]
PLL_DRP[87] bit 1-MAIN[47][29][56]
PLL_DRP[87] bit 2-MAIN[47][28][57]
PLL_DRP[87] bit 3-MAIN[47][29][57]
PLL_DRP[87] bit 4-MAIN[47][28][58]
PLL_DRP[87] bit 5-MAIN[47][29][58]
PLL_DRP[87] bit 6-MAIN[47][28][59]
PLL_DRP[87] bit 7-MAIN[47][29][59]
PLL_DRP[87] bit 8-MAIN[47][28][60]
PLL_DRP[87] bit 9-MAIN[47][29][60]
PLL_DRP[87] bit 10-MAIN[47][28][61]
PLL_DRP[87] bit 11-MAIN[47][29][61]
PLL_DRP[87] bit 12-MAIN[47][28][62]
PLL_DRP[87] bit 13-MAIN[47][29][62]
PLL_DRP[87] bit 14-MAIN[47][28][63]
PLL_DRP[87] bit 15-MAIN[47][29][63]
PLL_DRP[88] bit 0-MAIN[48][28][0]
PLL_DRP[88] bit 1-MAIN[48][29][0]
PLL_DRP[88] bit 2-MAIN[48][28][1]
PLL_DRP[88] bit 3-MAIN[48][29][1]
PLL_DRP[88] bit 4-MAIN[48][28][2]
PLL_DRP[88] bit 5-MAIN[48][29][2]
PLL_DRP[88] bit 6-MAIN[48][28][3]
PLL_DRP[88] bit 7-MAIN[48][29][3]
PLL_DRP[88] bit 8-MAIN[48][28][4]
PLL_DRP[88] bit 9-MAIN[48][29][4]
PLL_DRP[88] bit 10-MAIN[48][28][5]
PLL_DRP[88] bit 11-MAIN[48][29][5]
PLL_DRP[88] bit 12-MAIN[48][28][6]
PLL_DRP[88] bit 13-MAIN[48][29][6]
PLL_DRP[88] bit 14-MAIN[48][28][7]
PLL_DRP[88] bit 15-MAIN[48][29][7]
PLL_DRP[89] bit 0-MAIN[48][28][8]
PLL_DRP[89] bit 1-MAIN[48][29][8]
PLL_DRP[89] bit 2-MAIN[48][28][9]
PLL_DRP[89] bit 3-MAIN[48][29][9]
PLL_DRP[89] bit 4-MAIN[48][28][10]
PLL_DRP[89] bit 5-MAIN[48][29][10]
PLL_DRP[89] bit 6-MAIN[48][28][11]
PLL_DRP[89] bit 7-MAIN[48][29][11]
PLL_DRP[89] bit 8-MAIN[48][28][12]
PLL_DRP[89] bit 9-MAIN[48][29][12]
PLL_DRP[89] bit 10-MAIN[48][28][13]
PLL_DRP[89] bit 11-MAIN[48][29][13]
PLL_DRP[89] bit 12-MAIN[48][28][14]
PLL_DRP[89] bit 13-MAIN[48][29][14]
PLL_DRP[89] bit 14-MAIN[48][28][15]
PLL_DRP[89] bit 15-MAIN[48][29][15]
PLL_DRP[90] bit 0-MAIN[48][28][16]
PLL_DRP[90] bit 1-MAIN[48][29][16]
PLL_DRP[90] bit 2-MAIN[48][28][17]
PLL_DRP[90] bit 3-MAIN[48][29][17]
PLL_DRP[90] bit 4-MAIN[48][28][18]
PLL_DRP[90] bit 5-MAIN[48][29][18]
PLL_DRP[90] bit 6-MAIN[48][28][19]
PLL_DRP[90] bit 7-MAIN[48][29][19]
PLL_DRP[90] bit 8-MAIN[48][28][20]
PLL_DRP[90] bit 9-MAIN[48][29][20]
PLL_DRP[90] bit 10-MAIN[48][28][21]
PLL_DRP[90] bit 11-MAIN[48][29][21]
PLL_DRP[90] bit 12-MAIN[48][28][22]
PLL_DRP[90] bit 13-MAIN[48][29][22]
PLL_DRP[90] bit 14-MAIN[48][28][23]
PLL_DRP[90] bit 15-MAIN[48][29][23]
PLL_DRP[91] bit 0-MAIN[48][28][24]
PLL_DRP[91] bit 1-MAIN[48][29][24]
PLL_DRP[91] bit 2-MAIN[48][28][25]
PLL_DRP[91] bit 3-MAIN[48][29][25]
PLL_DRP[91] bit 4-MAIN[48][28][26]
PLL_DRP[91] bit 5-MAIN[48][29][26]
PLL_DRP[91] bit 6-MAIN[48][28][27]
PLL_DRP[91] bit 7-MAIN[48][29][27]
PLL_DRP[91] bit 8-MAIN[48][28][28]
PLL_DRP[91] bit 9-MAIN[48][29][28]
PLL_DRP[91] bit 10-MAIN[48][28][29]
PLL_DRP[91] bit 11-MAIN[48][29][29]
PLL_DRP[91] bit 12-MAIN[48][28][30]
PLL_DRP[91] bit 13-MAIN[48][29][30]
PLL_DRP[91] bit 14-MAIN[48][28][31]
PLL_DRP[91] bit 15-MAIN[48][29][31]
PLL_DRP[92] bit 0-MAIN[48][28][32]
PLL_DRP[92] bit 1-MAIN[48][29][32]
PLL_DRP[92] bit 2-MAIN[48][28][33]
PLL_DRP[92] bit 3-MAIN[48][29][33]
PLL_DRP[92] bit 4-MAIN[48][28][34]
PLL_DRP[92] bit 5-MAIN[48][29][34]
PLL_DRP[92] bit 6-MAIN[48][28][35]
PLL_DRP[92] bit 7-MAIN[48][29][35]
PLL_DRP[92] bit 8-MAIN[48][28][36]
PLL_DRP[92] bit 9-MAIN[48][29][36]
PLL_DRP[92] bit 10-MAIN[48][28][37]
PLL_DRP[92] bit 11-MAIN[48][29][37]
PLL_DRP[92] bit 12-MAIN[48][28][38]
PLL_DRP[92] bit 13-MAIN[48][29][38]
PLL_DRP[92] bit 14-MAIN[48][28][39]
PLL_DRP[92] bit 15-MAIN[48][29][39]
PLL_DRP[93] bit 0-MAIN[48][28][40]
PLL_DRP[93] bit 1-MAIN[48][29][40]
PLL_DRP[93] bit 2-MAIN[48][28][41]
PLL_DRP[93] bit 3-MAIN[48][29][41]
PLL_DRP[93] bit 4-MAIN[48][28][42]
PLL_DRP[93] bit 5-MAIN[48][29][42]
PLL_DRP[93] bit 6-MAIN[48][28][43]
PLL_DRP[93] bit 7-MAIN[48][29][43]
PLL_DRP[93] bit 8-MAIN[48][28][44]
PLL_DRP[93] bit 9-MAIN[48][29][44]
PLL_DRP[93] bit 10-MAIN[48][28][45]
PLL_DRP[93] bit 11-MAIN[48][29][45]
PLL_DRP[93] bit 12-MAIN[48][28][46]
PLL_DRP[93] bit 13-MAIN[48][29][46]
PLL_DRP[93] bit 14-MAIN[48][28][47]
PLL_DRP[93] bit 15-MAIN[48][29][47]
PLL_DRP[94] bit 0-MAIN[48][28][48]
PLL_DRP[94] bit 1-MAIN[48][29][48]
PLL_DRP[94] bit 2-MAIN[48][28][49]
PLL_DRP[94] bit 3-MAIN[48][29][49]
PLL_DRP[94] bit 4-MAIN[48][28][50]
PLL_DRP[94] bit 5-MAIN[48][29][50]
PLL_DRP[94] bit 6-MAIN[48][28][51]
PLL_DRP[94] bit 7-MAIN[48][29][51]
PLL_DRP[94] bit 8-MAIN[48][28][52]
PLL_DRP[94] bit 9-MAIN[48][29][52]
PLL_DRP[94] bit 10-MAIN[48][28][53]
PLL_DRP[94] bit 11-MAIN[48][29][53]
PLL_DRP[94] bit 12-MAIN[48][28][54]
PLL_DRP[94] bit 13-MAIN[48][29][54]
PLL_DRP[94] bit 14-MAIN[48][28][55]
PLL_DRP[94] bit 15-MAIN[48][29][55]
PLL_DRP[95] bit 0-MAIN[48][28][56]
PLL_DRP[95] bit 1-MAIN[48][29][56]
PLL_DRP[95] bit 2-MAIN[48][28][57]
PLL_DRP[95] bit 3-MAIN[48][29][57]
PLL_DRP[95] bit 4-MAIN[48][28][58]
PLL_DRP[95] bit 5-MAIN[48][29][58]
PLL_DRP[95] bit 6-MAIN[48][28][59]
PLL_DRP[95] bit 7-MAIN[48][29][59]
PLL_DRP[95] bit 8-MAIN[48][28][60]
PLL_DRP[95] bit 9-MAIN[48][29][60]
PLL_DRP[95] bit 10-MAIN[48][28][61]
PLL_DRP[95] bit 11-MAIN[48][29][61]
PLL_DRP[95] bit 12-MAIN[48][28][62]
PLL_DRP[95] bit 13-MAIN[48][29][62]
PLL_DRP[95] bit 14-MAIN[48][28][63]
PLL_DRP[95] bit 15-MAIN[48][29][63]
PLL_DRP[96] bit 0-MAIN[49][28][0]
PLL_DRP[96] bit 1-MAIN[49][29][0]
PLL_DRP[96] bit 2-MAIN[49][28][1]
PLL_DRP[96] bit 3-MAIN[49][29][1]
PLL_DRP[96] bit 4-MAIN[49][28][2]
PLL_DRP[96] bit 5-MAIN[49][29][2]
PLL_DRP[96] bit 6-MAIN[49][28][3]
PLL_DRP[96] bit 7-MAIN[49][29][3]
PLL_DRP[96] bit 8-MAIN[49][28][4]
PLL_DRP[96] bit 9-MAIN[49][29][4]
PLL_DRP[96] bit 10-MAIN[49][28][5]
PLL_DRP[96] bit 11-MAIN[49][29][5]
PLL_DRP[96] bit 12-MAIN[49][28][6]
PLL_DRP[96] bit 13-MAIN[49][29][6]
PLL_DRP[96] bit 14-MAIN[49][28][7]
PLL_DRP[96] bit 15-MAIN[49][29][7]
PLL_DRP[97] bit 0-MAIN[49][28][8]
PLL_DRP[97] bit 1-MAIN[49][29][8]
PLL_DRP[97] bit 2-MAIN[49][28][9]
PLL_DRP[97] bit 3-MAIN[49][29][9]
PLL_DRP[97] bit 4-MAIN[49][28][10]
PLL_DRP[97] bit 5-MAIN[49][29][10]
PLL_DRP[97] bit 6-MAIN[49][28][11]
PLL_DRP[97] bit 7-MAIN[49][29][11]
PLL_DRP[97] bit 8-MAIN[49][28][12]
PLL_DRP[97] bit 9-MAIN[49][29][12]
PLL_DRP[97] bit 10-MAIN[49][28][13]
PLL_DRP[97] bit 11-MAIN[49][29][13]
PLL_DRP[97] bit 12-MAIN[49][28][14]
PLL_DRP[97] bit 13-MAIN[49][29][14]
PLL_DRP[97] bit 14-MAIN[49][28][15]
PLL_DRP[97] bit 15-MAIN[49][29][15]
PLL_DRP[98] bit 0-MAIN[49][28][16]
PLL_DRP[98] bit 1-MAIN[49][29][16]
PLL_DRP[98] bit 2-MAIN[49][28][17]
PLL_DRP[98] bit 3-MAIN[49][29][17]
PLL_DRP[98] bit 4-MAIN[49][28][18]
PLL_DRP[98] bit 5-MAIN[49][29][18]
PLL_DRP[98] bit 6-MAIN[49][28][19]
PLL_DRP[98] bit 7-MAIN[49][29][19]
PLL_DRP[98] bit 8-MAIN[49][28][20]
PLL_DRP[98] bit 9-MAIN[49][29][20]
PLL_DRP[98] bit 10-MAIN[49][28][21]
PLL_DRP[98] bit 11-MAIN[49][29][21]
PLL_DRP[98] bit 12-MAIN[49][28][22]
PLL_DRP[98] bit 13-MAIN[49][29][22]
PLL_DRP[98] bit 14-MAIN[49][28][23]
PLL_DRP[98] bit 15-MAIN[49][29][23]
PLL_DRP[99] bit 0-MAIN[49][28][24]
PLL_DRP[99] bit 1-MAIN[49][29][24]
PLL_DRP[99] bit 2-MAIN[49][28][25]
PLL_DRP[99] bit 3-MAIN[49][29][25]
PLL_DRP[99] bit 4-MAIN[49][28][26]
PLL_DRP[99] bit 5-MAIN[49][29][26]
PLL_DRP[99] bit 6-MAIN[49][28][27]
PLL_DRP[99] bit 7-MAIN[49][29][27]
PLL_DRP[99] bit 8-MAIN[49][28][28]
PLL_DRP[99] bit 9-MAIN[49][29][28]
PLL_DRP[99] bit 10-MAIN[49][28][29]
PLL_DRP[99] bit 11-MAIN[49][29][29]
PLL_DRP[99] bit 12-MAIN[49][28][30]
PLL_DRP[99] bit 13-MAIN[49][29][30]
PLL_DRP[99] bit 14-MAIN[49][28][31]
PLL_DRP[99] bit 15-MAIN[49][29][31]
PLL_DRP[100] bit 0-MAIN[49][28][32]
PLL_DRP[100] bit 1-MAIN[49][29][32]
PLL_DRP[100] bit 2-MAIN[49][28][33]
PLL_DRP[100] bit 3-MAIN[49][29][33]
PLL_DRP[100] bit 4-MAIN[49][28][34]
PLL_DRP[100] bit 5-MAIN[49][29][34]
PLL_DRP[100] bit 6-MAIN[49][28][35]
PLL_DRP[100] bit 7-MAIN[49][29][35]
PLL_DRP[100] bit 8-MAIN[49][28][36]
PLL_DRP[100] bit 9-MAIN[49][29][36]
PLL_DRP[100] bit 10-MAIN[49][28][37]
PLL_DRP[100] bit 11-MAIN[49][29][37]
PLL_DRP[100] bit 12-MAIN[49][28][38]
PLL_DRP[100] bit 13-MAIN[49][29][38]
PLL_DRP[100] bit 14-MAIN[49][28][39]
PLL_DRP[100] bit 15-MAIN[49][29][39]
PLL_DRP[101] bit 0-MAIN[49][28][40]
PLL_DRP[101] bit 1-MAIN[49][29][40]
PLL_DRP[101] bit 2-MAIN[49][28][41]
PLL_DRP[101] bit 3-MAIN[49][29][41]
PLL_DRP[101] bit 4-MAIN[49][28][42]
PLL_DRP[101] bit 5-MAIN[49][29][42]
PLL_DRP[101] bit 6-MAIN[49][28][43]
PLL_DRP[101] bit 7-MAIN[49][29][43]
PLL_DRP[101] bit 8-MAIN[49][28][44]
PLL_DRP[101] bit 9-MAIN[49][29][44]
PLL_DRP[101] bit 10-MAIN[49][28][45]
PLL_DRP[101] bit 11-MAIN[49][29][45]
PLL_DRP[101] bit 12-MAIN[49][28][46]
PLL_DRP[101] bit 13-MAIN[49][29][46]
PLL_DRP[101] bit 14-MAIN[49][28][47]
PLL_DRP[101] bit 15-MAIN[49][29][47]
PLL_DRP[102] bit 0-MAIN[49][28][48]
PLL_DRP[102] bit 1-MAIN[49][29][48]
PLL_DRP[102] bit 2-MAIN[49][28][49]
PLL_DRP[102] bit 3-MAIN[49][29][49]
PLL_DRP[102] bit 4-MAIN[49][28][50]
PLL_DRP[102] bit 5-MAIN[49][29][50]
PLL_DRP[102] bit 6-MAIN[49][28][51]
PLL_DRP[102] bit 7-MAIN[49][29][51]
PLL_DRP[102] bit 8-MAIN[49][28][52]
PLL_DRP[102] bit 9-MAIN[49][29][52]
PLL_DRP[102] bit 10-MAIN[49][28][53]
PLL_DRP[102] bit 11-MAIN[49][29][53]
PLL_DRP[102] bit 12-MAIN[49][28][54]
PLL_DRP[102] bit 13-MAIN[49][29][54]
PLL_DRP[102] bit 14-MAIN[49][28][55]
PLL_DRP[102] bit 15-MAIN[49][29][55]
PLL_DRP[103] bit 0-MAIN[49][28][56]
PLL_DRP[103] bit 1-MAIN[49][29][56]
PLL_DRP[103] bit 2-MAIN[49][28][57]
PLL_DRP[103] bit 3-MAIN[49][29][57]
PLL_DRP[103] bit 4-MAIN[49][28][58]
PLL_DRP[103] bit 5-MAIN[49][29][58]
PLL_DRP[103] bit 6-MAIN[49][28][59]
PLL_DRP[103] bit 7-MAIN[49][29][59]
PLL_DRP[103] bit 8-MAIN[49][28][60]
PLL_DRP[103] bit 9-MAIN[49][29][60]
PLL_DRP[103] bit 10-MAIN[49][28][61]
PLL_DRP[103] bit 11-MAIN[49][29][61]
PLL_DRP[103] bit 12-MAIN[49][28][62]
PLL_DRP[103] bit 13-MAIN[49][29][62]
PLL_DRP[103] bit 14-MAIN[49][28][63]
PLL_DRP[103] bit 15-MAIN[49][29][63]
ENABLEMAIN[1][29][31]MAIN[48][28][32]
STARTUP_WAITMAIN[1][29][30]MAIN[48][28][33]
DIRECT_PATH_CNTRLMAIN[15][28][22]MAIN[37][29][41]
GTS_WAITMAIN[1][28][30]MAIN[48][29][33]
EN_VCO_DIV1MAIN[11][28][47]MAIN[41][29][16]
EN_VCO_DIV6MAIN[11][29][47]MAIN[41][28][16]
HVLF_CNT_TEST_ENMAIN[6][29][25]MAIN[46][28][38]
IN_DLY_ENMAIN[15][29][22]MAIN[37][28][41]
VLF_HIGH_DIS_BMAIN[7][28][44]MAIN[45][29][19]
VLF_HIGH_PWDN_BMAIN[7][29][15]MAIN[45][28][48]
TMUX_MUX_SEL bit 0MAIN[15][29][24]MAIN[37][28][39]
TMUX_MUX_SEL bit 1MAIN[15][28][24]MAIN[37][29][39]
CONTROL_0 bit 0MAIN[1][29][15]MAIN[48][28][48]
CONTROL_0 bit 1MAIN[1][28][15]MAIN[48][29][48]
CONTROL_0 bit 2MAIN[1][29][14]MAIN[48][28][49]
CONTROL_0 bit 3MAIN[1][28][14]MAIN[48][29][49]
CONTROL_0 bit 4MAIN[1][29][13]MAIN[48][28][50]
CONTROL_0 bit 5MAIN[1][28][13]MAIN[48][29][50]
CONTROL_0 bit 6MAIN[1][29][12]MAIN[48][28][51]
CONTROL_0 bit 7MAIN[1][28][12]MAIN[48][29][51]
CONTROL_0 bit 8MAIN[1][29][11]MAIN[48][28][52]
CONTROL_0 bit 9MAIN[1][28][11]MAIN[48][29][52]
CONTROL_0 bit 10MAIN[1][29][10]MAIN[48][28][53]
CONTROL_0 bit 11MAIN[1][28][10]MAIN[48][29][53]
CONTROL_0 bit 12MAIN[1][29][9]MAIN[48][28][54]
CONTROL_0 bit 13MAIN[1][28][9]MAIN[48][29][54]
CONTROL_0 bit 14MAIN[1][29][8]MAIN[48][28][55]
CONTROL_0 bit 15MAIN[1][28][8]MAIN[48][29][55]
CONTROL_1 bit 0MAIN[1][29][7]MAIN[48][28][56]
CONTROL_1 bit 1MAIN[1][28][7]MAIN[48][29][56]
CONTROL_1 bit 2MAIN[1][29][6]MAIN[48][28][57]
CONTROL_1 bit 3MAIN[1][28][6]MAIN[48][29][57]
CONTROL_1 bit 4MAIN[1][29][5]MAIN[48][28][58]
CONTROL_1 bit 5MAIN[1][28][5]MAIN[48][29][58]
CONTROL_1 bit 6MAIN[1][29][4]MAIN[48][28][59]
CONTROL_1 bit 7MAIN[1][28][4]MAIN[48][29][59]
CONTROL_1 bit 8MAIN[1][29][3]MAIN[48][28][60]
CONTROL_1 bit 9MAIN[1][28][3]MAIN[48][29][60]
CONTROL_1 bit 10MAIN[1][29][2]MAIN[48][28][61]
CONTROL_1 bit 11MAIN[1][28][2]MAIN[48][29][61]
CONTROL_1 bit 12MAIN[1][29][1]MAIN[48][28][62]
CONTROL_1 bit 13MAIN[1][28][1]MAIN[48][29][62]
CONTROL_1 bit 14MAIN[1][29][0]MAIN[48][28][63]
CONTROL_1 bit 15MAIN[1][28][0]MAIN[48][29][63]
CONTROL_2 bit 0MAIN[0][29][63]MAIN[49][28][0]
CONTROL_2 bit 1MAIN[0][28][63]MAIN[49][29][0]
CONTROL_2 bit 2MAIN[0][29][62]MAIN[49][28][1]
CONTROL_2 bit 3MAIN[0][28][62]MAIN[49][29][1]
CONTROL_2 bit 4MAIN[0][29][61]MAIN[49][28][2]
CONTROL_2 bit 5MAIN[0][28][61]MAIN[49][29][2]
CONTROL_2 bit 6MAIN[0][29][60]MAIN[49][28][3]
CONTROL_2 bit 7MAIN[0][28][60]MAIN[49][29][3]
CONTROL_2 bit 8MAIN[0][29][59]MAIN[49][28][4]
CONTROL_2 bit 9MAIN[0][28][59]MAIN[49][29][4]
CONTROL_2 bit 10MAIN[0][29][58]MAIN[49][28][5]
CONTROL_2 bit 11MAIN[0][28][58]MAIN[49][29][5]
CONTROL_2 bit 12MAIN[0][29][57]MAIN[49][28][6]
CONTROL_2 bit 13MAIN[0][28][57]MAIN[49][29][6]
CONTROL_2 bit 14MAIN[0][29][56]MAIN[49][28][7]
CONTROL_2 bit 15MAIN[0][28][56]MAIN[49][29][7]
CONTROL_3 bit 0MAIN[0][29][55]MAIN[49][28][8]
CONTROL_3 bit 1MAIN[0][28][55]MAIN[49][29][8]
CONTROL_3 bit 2MAIN[0][29][54]MAIN[49][28][9]
CONTROL_3 bit 3MAIN[0][28][54]MAIN[49][29][9]
CONTROL_3 bit 4MAIN[0][29][53]MAIN[49][28][10]
CONTROL_3 bit 5MAIN[0][28][53]MAIN[49][29][10]
CONTROL_3 bit 6MAIN[0][29][52]MAIN[49][28][11]
CONTROL_3 bit 7MAIN[0][28][52]MAIN[49][29][11]
CONTROL_3 bit 8MAIN[0][29][51]MAIN[49][28][12]
CONTROL_3 bit 9MAIN[0][28][51]MAIN[49][29][12]
CONTROL_3 bit 10MAIN[0][29][50]MAIN[49][28][13]
CONTROL_3 bit 11MAIN[0][28][50]MAIN[49][29][13]
CONTROL_3 bit 12MAIN[0][29][49]MAIN[49][28][14]
CONTROL_3 bit 13MAIN[0][28][49]MAIN[49][29][14]
CONTROL_3 bit 14MAIN[0][29][48]MAIN[49][28][15]
CONTROL_3 bit 15MAIN[0][28][48]MAIN[49][29][15]
CONTROL_4 bit 0MAIN[0][29][47]MAIN[49][28][16]
CONTROL_4 bit 1MAIN[0][28][47]MAIN[49][29][16]
CONTROL_4 bit 2MAIN[0][29][46]MAIN[49][28][17]
CONTROL_4 bit 3MAIN[0][28][46]MAIN[49][29][17]
CONTROL_4 bit 4MAIN[0][29][45]MAIN[49][28][18]
CONTROL_4 bit 5MAIN[0][28][45]MAIN[49][29][18]
CONTROL_4 bit 6MAIN[0][29][44]MAIN[49][28][19]
CONTROL_4 bit 7MAIN[0][28][44]MAIN[49][29][19]
CONTROL_4 bit 8MAIN[0][29][43]MAIN[49][28][20]
CONTROL_4 bit 9MAIN[0][28][43]MAIN[49][29][20]
CONTROL_4 bit 10MAIN[0][29][42]MAIN[49][28][21]
CONTROL_4 bit 11MAIN[0][28][42]MAIN[49][29][21]
CONTROL_4 bit 12MAIN[0][29][41]MAIN[49][28][22]
CONTROL_4 bit 13MAIN[0][28][41]MAIN[49][29][22]
CONTROL_4 bit 14MAIN[0][29][40]MAIN[49][28][23]
CONTROL_4 bit 15MAIN[0][28][40]MAIN[49][29][23]
CONTROL_5 bit 0MAIN[0][29][39]MAIN[49][28][24]
CONTROL_5 bit 1MAIN[0][28][39]MAIN[49][29][24]
CONTROL_5 bit 2MAIN[0][29][38]MAIN[49][28][25]
CONTROL_5 bit 3MAIN[0][28][38]MAIN[49][29][25]
CONTROL_5 bit 4MAIN[0][29][37]MAIN[49][28][26]
CONTROL_5 bit 5MAIN[0][28][37]MAIN[49][29][26]
CONTROL_5 bit 6MAIN[0][29][36]MAIN[49][28][27]
CONTROL_5 bit 7MAIN[0][28][36]MAIN[49][29][27]
CONTROL_5 bit 8MAIN[0][29][35]MAIN[49][28][28]
CONTROL_5 bit 9MAIN[0][28][35]MAIN[49][29][28]
CONTROL_5 bit 10MAIN[0][29][34]MAIN[49][28][29]
CONTROL_5 bit 11MAIN[0][28][34]MAIN[49][29][29]
CONTROL_5 bit 12MAIN[0][29][33]MAIN[49][28][30]
CONTROL_5 bit 13MAIN[0][28][33]MAIN[49][29][30]
CONTROL_5 bit 14MAIN[0][29][32]MAIN[49][28][31]
CONTROL_5 bit 15MAIN[0][28][32]MAIN[49][29][31]
CONTROL_6 bit 0MAIN[0][29][31]MAIN[49][28][32]
CONTROL_6 bit 1MAIN[0][28][31]MAIN[49][29][32]
CONTROL_6 bit 2MAIN[0][29][30]MAIN[49][28][33]
CONTROL_6 bit 3MAIN[0][28][30]MAIN[49][29][33]
CONTROL_6 bit 4MAIN[0][29][29]MAIN[49][28][34]
CONTROL_6 bit 5MAIN[0][28][29]MAIN[49][29][34]
CONTROL_6 bit 6MAIN[0][29][28]MAIN[49][28][35]
CONTROL_6 bit 7MAIN[0][28][28]MAIN[49][29][35]
CONTROL_6 bit 8MAIN[0][29][27]MAIN[49][28][36]
CONTROL_6 bit 9MAIN[0][28][27]MAIN[49][29][36]
CONTROL_6 bit 10MAIN[0][29][26]MAIN[49][28][37]
CONTROL_6 bit 11MAIN[0][28][26]MAIN[49][29][37]
CONTROL_6 bit 12MAIN[0][29][25]MAIN[49][28][38]
CONTROL_6 bit 13MAIN[0][28][25]MAIN[49][29][38]
CONTROL_6 bit 14MAIN[0][29][24]MAIN[49][28][39]
CONTROL_6 bit 15MAIN[0][28][24]MAIN[49][29][39]
CONTROL_7 bit 0MAIN[0][29][23]MAIN[49][28][40]
CONTROL_7 bit 1MAIN[0][28][23]MAIN[49][29][40]
CONTROL_7 bit 2MAIN[0][29][22]MAIN[49][28][41]
CONTROL_7 bit 3MAIN[0][28][22]MAIN[49][29][41]
CONTROL_7 bit 4MAIN[0][29][21]MAIN[49][28][42]
CONTROL_7 bit 5MAIN[0][28][21]MAIN[49][29][42]
CONTROL_7 bit 6MAIN[0][29][20]MAIN[49][28][43]
CONTROL_7 bit 7MAIN[0][28][20]MAIN[49][29][43]
CONTROL_7 bit 8MAIN[0][29][19]MAIN[49][28][44]
CONTROL_7 bit 9MAIN[0][28][19]MAIN[49][29][44]
CONTROL_7 bit 10MAIN[0][29][18]MAIN[49][28][45]
CONTROL_7 bit 11MAIN[0][28][18]MAIN[49][29][45]
CONTROL_7 bit 12MAIN[0][29][17]MAIN[49][28][46]
CONTROL_7 bit 13MAIN[0][28][17]MAIN[49][29][46]
CONTROL_7 bit 14MAIN[0][29][16]MAIN[49][28][47]
CONTROL_7 bit 15MAIN[0][28][16]MAIN[49][29][47]
ANALOG_MISC bit 0MAIN[11][28][14]MAIN[41][29][49]
ANALOG_MISC bit 1MAIN[11][29][13]MAIN[41][28][50]
ANALOG_MISC bit 2MAIN[11][28][12]MAIN[41][29][51]
ANALOG_MISC bit 3MAIN[11][29][11]MAIN[41][28][52]
CP_BIAS_TRIP_SET bit 0MAIN[6][28][12]MAIN[46][29][51]
CP_RES bit 0MAIN[6][28][14]MAIN[46][29][49]
CP_RES bit 1MAIN[6][29][13]MAIN[46][28][50]
V7_AVDD_COMP_SET bit 0MAIN[6][28][44]MAIN[46][29][19]
V7_AVDD_COMP_SET bit 1MAIN[6][29][43]MAIN[46][28][20]
V7_AVDD_COMP_SET bit 2MAIN[6][28][43]MAIN[46][29][20]
AVDD_VBG_PD bit 0MAIN[6][29][45]MAIN[46][28][18]
AVDD_VBG_PD bit 1MAIN[6][28][45]MAIN[46][29][18]
AVDD_VBG_PD bit 2MAIN[6][29][44]MAIN[46][28][19]
AVDD_VBG_SEL bit 0MAIN[6][29][47]MAIN[46][28][16]
AVDD_VBG_SEL bit 1MAIN[6][28][47]MAIN[46][29][16]
AVDD_VBG_SEL bit 2MAIN[6][29][46]MAIN[46][28][17]
AVDD_VBG_SEL bit 3MAIN[6][28][46]MAIN[46][29][17]
V7_DVDD_COMP_SET bit 0MAIN[12][28][4]MAIN[40][29][59]
V7_DVDD_COMP_SET bit 1MAIN[12][29][3]MAIN[40][28][60]
V7_DVDD_COMP_SET bit 2MAIN[12][28][3]MAIN[40][29][60]
DVDD_VBG_PD bit 0MAIN[12][29][5]MAIN[40][28][58]
DVDD_VBG_PD bit 1MAIN[12][28][5]MAIN[40][29][58]
DVDD_VBG_PD bit 2MAIN[12][29][4]MAIN[40][28][59]
DVDD_VBG_SEL bit 0MAIN[12][29][7]MAIN[40][28][56]
DVDD_VBG_SEL bit 1MAIN[12][28][7]MAIN[40][29][56]
DVDD_VBG_SEL bit 2MAIN[12][29][6]MAIN[40][28][57]
DVDD_VBG_SEL bit 3MAIN[12][28][6]MAIN[40][29][57]
IN_DLY_MX_CVDD bit 0MAIN[15][29][60]MAIN[37][28][3]
IN_DLY_MX_CVDD bit 1MAIN[15][28][60]MAIN[37][29][3]
IN_DLY_MX_CVDD bit 2MAIN[15][29][59]MAIN[37][28][4]
IN_DLY_MX_CVDD bit 3MAIN[15][28][59]MAIN[37][29][4]
IN_DLY_MX_CVDD bit 4MAIN[15][29][58]MAIN[37][28][5]
IN_DLY_MX_CVDD bit 5MAIN[15][28][58]MAIN[37][29][5]
IN_DLY_MX_DVDD bit 0MAIN[15][29][21]MAIN[37][28][42]
IN_DLY_MX_DVDD bit 1MAIN[15][28][21]MAIN[37][29][42]
IN_DLY_MX_DVDD bit 2MAIN[15][29][20]MAIN[37][28][43]
IN_DLY_MX_DVDD bit 3MAIN[15][28][20]MAIN[37][29][43]
IN_DLY_MX_DVDD bit 4MAIN[15][29][19]MAIN[37][28][44]
IN_DLY_MX_DVDD bit 5MAIN[15][28][19]MAIN[37][29][44]
LF_NEN bit 0MAIN[7][29][41]MAIN[45][28][22]
LF_NEN bit 1MAIN[7][28][40]MAIN[45][29][23]
LF_PEN bit 0MAIN[7][29][43]MAIN[45][28][20]
LF_PEN bit 1MAIN[7][28][42]MAIN[45][29][21]
MAN_LF bit 0MAIN[7][29][47]MAIN[45][28][16]
MAN_LF bit 1MAIN[7][28][46]MAIN[45][29][17]
MAN_LF bit 2MAIN[7][29][45]MAIN[45][28][18]
PFD bit 0MAIN[12][29][21]MAIN[40][28][42]
PFD bit 1MAIN[12][28][21]MAIN[40][29][42]
PFD bit 2MAIN[12][29][20]MAIN[40][28][43]
PFD bit 3MAIN[12][28][20]MAIN[40][29][43]
PFD bit 4MAIN[12][29][19]MAIN[40][28][44]
PFD bit 5MAIN[12][28][19]MAIN[40][29][44]
PFD bit 6MAIN[12][29][18]MAIN[40][28][45]
CP bit 0MAIN[6][29][11]MAIN[46][28][52]
CP bit 1MAIN[6][28][10]MAIN[46][29][53]
CP bit 2MAIN[6][29][9]MAIN[46][28][54]
CP bit 3MAIN[6][28][8]MAIN[46][29][55]
HROW_DLY_SET bit 0MAIN[15][29][57]MAIN[37][28][6]
HROW_DLY_SET bit 1MAIN[15][28][57]MAIN[37][29][6]
HROW_DLY_SET bit 2MAIN[15][29][56]MAIN[37][28][7]
HVLF_CNT_TEST bit 0MAIN[6][29][31]MAIN[46][28][32]
HVLF_CNT_TEST bit 1MAIN[6][28][30]MAIN[46][29][33]
HVLF_CNT_TEST bit 2MAIN[6][29][29]MAIN[46][28][34]
HVLF_CNT_TEST bit 3MAIN[6][28][28]MAIN[46][29][35]
HVLF_CNT_TEST bit 4MAIN[6][29][27]MAIN[46][28][36]
HVLF_CNT_TEST bit 5MAIN[6][28][26]MAIN[46][29][37]
LFHF bit 0MAIN[6][29][5]MAIN[46][28][58]
LFHF bit 1MAIN[6][28][4]MAIN[46][29][59]
LOCK_CNT bit 0MAIN[12][29][63]MAIN[40][28][0]
LOCK_CNT bit 1MAIN[12][28][63]MAIN[40][29][0]
LOCK_CNT bit 2MAIN[12][29][62]MAIN[40][28][1]
LOCK_CNT bit 3MAIN[12][28][62]MAIN[40][29][1]
LOCK_CNT bit 4MAIN[12][29][61]MAIN[40][28][2]
LOCK_CNT bit 5MAIN[12][28][61]MAIN[40][29][2]
LOCK_CNT bit 6MAIN[12][29][60]MAIN[40][28][3]
LOCK_CNT bit 7MAIN[12][28][60]MAIN[40][29][3]
LOCK_CNT bit 8MAIN[12][29][59]MAIN[40][28][4]
LOCK_CNT bit 9MAIN[12][28][59]MAIN[40][29][4]
LOCK_FB_DLY bit 0MAIN[12][29][50]MAIN[40][28][13]
LOCK_FB_DLY bit 1MAIN[12][28][50]MAIN[40][29][13]
LOCK_FB_DLY bit 2MAIN[12][29][49]MAIN[40][28][14]
LOCK_FB_DLY bit 3MAIN[12][28][49]MAIN[40][29][14]
LOCK_FB_DLY bit 4MAIN[12][29][48]MAIN[40][28][15]
LOCK_REF_DLY bit 0MAIN[12][29][42]MAIN[40][28][21]
LOCK_REF_DLY bit 1MAIN[12][28][42]MAIN[40][29][21]
LOCK_REF_DLY bit 2MAIN[12][29][41]MAIN[40][28][22]
LOCK_REF_DLY bit 3MAIN[12][28][41]MAIN[40][29][22]
LOCK_REF_DLY bit 4MAIN[12][29][40]MAIN[40][28][23]
LOCK_SAT_HIGH bit 0MAIN[12][29][47]MAIN[40][28][16]
LOCK_SAT_HIGH bit 1MAIN[12][28][47]MAIN[40][29][16]
LOCK_SAT_HIGH bit 2MAIN[12][29][46]MAIN[40][28][17]
LOCK_SAT_HIGH bit 3MAIN[12][28][46]MAIN[40][29][17]
LOCK_SAT_HIGH bit 4MAIN[12][29][45]MAIN[40][28][18]
LOCK_SAT_HIGH bit 5MAIN[12][28][45]MAIN[40][29][18]
LOCK_SAT_HIGH bit 6MAIN[12][29][44]MAIN[40][28][19]
LOCK_SAT_HIGH bit 7MAIN[12][28][44]MAIN[40][29][19]
LOCK_SAT_HIGH bit 8MAIN[12][29][43]MAIN[40][28][20]
LOCK_SAT_HIGH bit 9MAIN[12][28][43]MAIN[40][29][20]
RES bit 0MAIN[6][29][3]MAIN[46][28][60]
RES bit 1MAIN[6][28][2]MAIN[46][29][61]
RES bit 2MAIN[6][29][1]MAIN[46][28][62]
RES bit 3MAIN[6][28][0]MAIN[46][29][63]
UNLOCK_CNT bit 0MAIN[12][29][55]MAIN[40][28][8]
UNLOCK_CNT bit 1MAIN[12][28][55]MAIN[40][29][8]
UNLOCK_CNT bit 2MAIN[12][29][54]MAIN[40][28][9]
UNLOCK_CNT bit 3MAIN[12][28][54]MAIN[40][29][9]
UNLOCK_CNT bit 4MAIN[12][29][53]MAIN[40][28][10]
UNLOCK_CNT bit 5MAIN[12][28][53]MAIN[40][29][10]
UNLOCK_CNT bit 6MAIN[12][29][52]MAIN[40][28][11]
UNLOCK_CNT bit 7MAIN[12][28][52]MAIN[40][29][11]
UNLOCK_CNT bit 8MAIN[12][29][51]MAIN[40][28][12]
UNLOCK_CNT bit 9MAIN[12][28][51]MAIN[40][29][12]
V7_IN_DLY_SET bit 0MAIN[15][29][18]MAIN[37][28][45]
V7_IN_DLY_SET bit 1MAIN[15][28][18]MAIN[37][29][45]
V7_IN_DLY_SET bit 2MAIN[15][29][17]MAIN[37][28][46]
V7_IN_DLY_SET bit 3MAIN[15][28][17]MAIN[37][29][46]
V7_IN_DLY_SET bit 4MAIN[15][29][16]MAIN[37][28][47]
V7_IN_DLY_SET bit 5MAIN[15][28][16]MAIN[37][29][47]
SYNTH_CLK_DIV bit 0MAIN[15][29][47]MAIN[37][28][16]
SYNTH_CLK_DIV bit 1MAIN[15][28][47]MAIN[37][29][16]
INTERP_EN bit 0MAIN[10][29][63]-
INTERP_EN bit 1MAIN[10][28][62]-
INTERP_EN bit 2MAIN[10][29][61]-
INTERP_EN bit 3MAIN[10][28][60]-
INTERP_EN bit 4MAIN[10][29][59]-
INTERP_EN bit 5MAIN[10][28][58]-
INTERP_EN bit 6MAIN[10][29][57]-
INTERP_EN bit 7MAIN[10][28][56]-
LF_LOW_SELMAIN[7][29][39]MAIN[45][28][24]
SEL_HV_NMOSMAIN[6][29][50]MAIN[46][28][13]
SEL_LV_NMOSMAIN[12][29][8]MAIN[40][28][55]
SUP_SEL_AREGMAIN[6][28][48]MAIN[46][29][15]
SUP_SEL_DREGMAIN[12][28][8]MAIN[40][29][55]
EN_CURR_SINK bit 0MAIN[6][28][49]MAIN[46][29][14]
EN_CURR_SINK bit 1MAIN[6][29][48]MAIN[46][28][15]
FREQ_COMP bit 0MAIN[12][28][40]MAIN[40][29][23]
FREQ_COMP bit 1MAIN[12][29][39]MAIN[40][28][24]
SKEW_FLOP_INV bit 0MAIN[15][29][39]MAIN[37][28][24]
SKEW_FLOP_INV bit 1MAIN[15][28][39]MAIN[37][29][24]
SKEW_FLOP_INV bit 2MAIN[15][29][38]MAIN[37][28][25]
SKEW_FLOP_INV bit 3MAIN[15][28][38]MAIN[37][29][25]
SPARE_ANALOG bit 0MAIN[7][29][31]MAIN[45][28][32]
SPARE_ANALOG bit 1MAIN[7][28][30]MAIN[45][29][33]
SPARE_ANALOG bit 2MAIN[7][29][29]MAIN[45][28][34]
SPARE_ANALOG bit 3MAIN[7][28][28]MAIN[45][29][35]
SPARE_ANALOG bit 4MAIN[7][29][27]MAIN[45][28][36]
SPARE_DIGITAL bit 0MAIN[12][29][31]MAIN[40][28][32]
SPARE_DIGITAL bit 1MAIN[12][28][31]MAIN[40][29][32]
SPARE_DIGITAL bit 2MAIN[12][29][30]MAIN[40][28][33]
SPARE_DIGITAL bit 3MAIN[12][28][30]MAIN[40][29][33]
SPARE_DIGITAL bit 4MAIN[12][29][29]MAIN[40][28][34]
VREF_START bit 0MAIN[7][28][18]MAIN[45][29][45]
VREF_START bit 1MAIN[7][29][17]MAIN[45][28][46]
MVDD_SEL bit 0MAIN[6][28][50]MAIN[46][29][13]
MVDD_SEL bit 1MAIN[6][29][49]MAIN[46][28][14]
CLKBURST_ENABLEMAIN[15][29][25]-
CLKBURST_REPEATMAIN[15][28][25]-
CLKBURST_CNT bit 0MAIN[15][29][27]-
CLKBURST_CNT bit 1MAIN[15][28][27]-
CLKBURST_CNT bit 2MAIN[15][29][26]-
CLKBURST_CNT bit 3MAIN[15][28][26]-
SEL_SLIPDMAIN[12][28][18]-
INTERP_TESTMAIN[11][29][46]-
SS_ENMAIN[1][28][31]-
SS_STEPS bit 0MAIN[15][29][31]-
SS_STEPS bit 1MAIN[15][28][31]-
SS_STEPS bit 2MAIN[15][29][30]-
SS_STEPS_INIT bit 0MAIN[15][28][30]-
SS_STEPS_INIT bit 1MAIN[15][29][29]-
SS_STEPS_INIT bit 2MAIN[15][28][29]-
CLKOUT0_ENMAIN[14][29][57]MAIN[38][28][6]
CLKOUT0_NOCOUNTMAIN[14][29][52]MAIN[38][28][11]
CLKOUT0_EDGEMAIN[14][28][52]MAIN[38][29][11]
CLKOUT0_DT bit 0MAIN[14][29][55]MAIN[38][28][8]
CLKOUT0_DT bit 1MAIN[14][28][55]MAIN[38][29][8]
CLKOUT0_DT bit 2MAIN[14][29][54]MAIN[38][28][9]
CLKOUT0_DT bit 3MAIN[14][28][54]MAIN[38][29][9]
CLKOUT0_DT bit 4MAIN[14][29][53]MAIN[38][28][10]
CLKOUT0_DT bit 5MAIN[14][28][53]MAIN[38][29][10]
CLKOUT0_HT bit 0MAIN[14][29][60]MAIN[38][28][3]
CLKOUT0_HT bit 1MAIN[14][28][60]MAIN[38][29][3]
CLKOUT0_HT bit 2MAIN[14][29][59]MAIN[38][28][4]
CLKOUT0_HT bit 3MAIN[14][28][59]MAIN[38][29][4]
CLKOUT0_HT bit 4MAIN[14][29][58]MAIN[38][28][5]
CLKOUT0_HT bit 5MAIN[14][28][58]MAIN[38][29][5]
CLKOUT0_LT bit 0MAIN[14][29][63]MAIN[38][28][0]
CLKOUT0_LT bit 1MAIN[14][28][63]MAIN[38][29][0]
CLKOUT0_LT bit 2MAIN[14][29][62]MAIN[38][28][1]
CLKOUT0_LT bit 3MAIN[14][28][62]MAIN[38][29][1]
CLKOUT0_LT bit 4MAIN[14][29][61]MAIN[38][28][2]
CLKOUT0_LT bit 5MAIN[14][28][61]MAIN[38][29][2]
CLKOUT0_MX bit 0MAIN[14][29][51]MAIN[38][28][12]
CLKOUT0_MX bit 1MAIN[14][28][51]MAIN[38][29][12]
CLKOUT0_PM bit 0-MAIN[38][29][6]
CLKOUT0_PM bit 1-MAIN[38][28][7]
CLKOUT0_PM bit 2-MAIN[38][29][7]
CLKOUT0_USE_FINE_PSMAIN[14][29][51]-
CLKOUT1_ENMAIN[14][29][41]MAIN[38][28][22]
CLKOUT1_NOCOUNTMAIN[14][29][36]MAIN[38][28][27]
CLKOUT1_EDGEMAIN[14][28][36]MAIN[38][29][27]
CLKOUT1_DT bit 0MAIN[14][29][39]MAIN[38][28][24]
CLKOUT1_DT bit 1MAIN[14][28][39]MAIN[38][29][24]
CLKOUT1_DT bit 2MAIN[14][29][38]MAIN[38][28][25]
CLKOUT1_DT bit 3MAIN[14][28][38]MAIN[38][29][25]
CLKOUT1_DT bit 4MAIN[14][29][37]MAIN[38][28][26]
CLKOUT1_DT bit 5MAIN[14][28][37]MAIN[38][29][26]
CLKOUT1_HT bit 0MAIN[14][29][44]MAIN[38][28][19]
CLKOUT1_HT bit 1MAIN[14][28][44]MAIN[38][29][19]
CLKOUT1_HT bit 2MAIN[14][29][43]MAIN[38][28][20]
CLKOUT1_HT bit 3MAIN[14][28][43]MAIN[38][29][20]
CLKOUT1_HT bit 4MAIN[14][29][42]MAIN[38][28][21]
CLKOUT1_HT bit 5MAIN[14][28][42]MAIN[38][29][21]
CLKOUT1_LT bit 0MAIN[14][29][47]MAIN[38][28][16]
CLKOUT1_LT bit 1MAIN[14][28][47]MAIN[38][29][16]
CLKOUT1_LT bit 2MAIN[14][29][46]MAIN[38][28][17]
CLKOUT1_LT bit 3MAIN[14][28][46]MAIN[38][29][17]
CLKOUT1_LT bit 4MAIN[14][29][45]MAIN[38][28][18]
CLKOUT1_LT bit 5MAIN[14][28][45]MAIN[38][29][18]
CLKOUT1_MX bit 0MAIN[14][29][35]MAIN[38][28][28]
CLKOUT1_MX bit 1MAIN[14][28][35]MAIN[38][29][28]
CLKOUT1_PM bit 0MAIN[14][28][41]MAIN[38][29][22]
CLKOUT1_PM bit 1MAIN[14][29][40]MAIN[38][28][23]
CLKOUT1_PM bit 2MAIN[14][28][40]MAIN[38][29][23]
CLKOUT1_USE_FINE_PSMAIN[14][29][35]-
CLKOUT2_ENMAIN[14][29][25]MAIN[38][28][38]
CLKOUT2_NOCOUNTMAIN[14][29][20]MAIN[38][28][43]
CLKOUT2_EDGEMAIN[14][28][20]MAIN[38][29][43]
CLKOUT2_DT bit 0MAIN[14][29][23]MAIN[38][28][40]
CLKOUT2_DT bit 1MAIN[14][28][23]MAIN[38][29][40]
CLKOUT2_DT bit 2MAIN[14][29][22]MAIN[38][28][41]
CLKOUT2_DT bit 3MAIN[14][28][22]MAIN[38][29][41]
CLKOUT2_DT bit 4MAIN[14][29][21]MAIN[38][28][42]
CLKOUT2_DT bit 5MAIN[14][28][21]MAIN[38][29][42]
CLKOUT2_HT bit 0MAIN[14][29][28]MAIN[38][28][35]
CLKOUT2_HT bit 1MAIN[14][28][28]MAIN[38][29][35]
CLKOUT2_HT bit 2MAIN[14][29][27]MAIN[38][28][36]
CLKOUT2_HT bit 3MAIN[14][28][27]MAIN[38][29][36]
CLKOUT2_HT bit 4MAIN[14][29][26]MAIN[38][28][37]
CLKOUT2_HT bit 5MAIN[14][28][26]MAIN[38][29][37]
CLKOUT2_LT bit 0MAIN[14][29][31]MAIN[38][28][32]
CLKOUT2_LT bit 1MAIN[14][28][31]MAIN[38][29][32]
CLKOUT2_LT bit 2MAIN[14][29][30]MAIN[38][28][33]
CLKOUT2_LT bit 3MAIN[14][28][30]MAIN[38][29][33]
CLKOUT2_LT bit 4MAIN[14][29][29]MAIN[38][28][34]
CLKOUT2_LT bit 5MAIN[14][28][29]MAIN[38][29][34]
CLKOUT2_MX bit 0MAIN[14][29][19]MAIN[38][28][44]
CLKOUT2_MX bit 1MAIN[14][28][19]MAIN[38][29][44]
CLKOUT2_PM bit 0MAIN[14][28][25]MAIN[38][29][38]
CLKOUT2_PM bit 1MAIN[14][29][24]MAIN[38][28][39]
CLKOUT2_PM bit 2MAIN[14][28][24]MAIN[38][29][39]
CLKOUT2_USE_FINE_PSMAIN[14][29][19]-
CLKOUT3_ENMAIN[14][29][9]MAIN[38][28][54]
CLKOUT3_NOCOUNTMAIN[14][29][4]MAIN[38][28][59]
CLKOUT3_EDGEMAIN[14][28][4]MAIN[38][29][59]
CLKOUT3_DT bit 0MAIN[14][29][7]MAIN[38][28][56]
CLKOUT3_DT bit 1MAIN[14][28][7]MAIN[38][29][56]
CLKOUT3_DT bit 2MAIN[14][29][6]MAIN[38][28][57]
CLKOUT3_DT bit 3MAIN[14][28][6]MAIN[38][29][57]
CLKOUT3_DT bit 4MAIN[14][29][5]MAIN[38][28][58]
CLKOUT3_DT bit 5MAIN[14][28][5]MAIN[38][29][58]
CLKOUT3_HT bit 0MAIN[14][29][12]MAIN[38][28][51]
CLKOUT3_HT bit 1MAIN[14][28][12]MAIN[38][29][51]
CLKOUT3_HT bit 2MAIN[14][29][11]MAIN[38][28][52]
CLKOUT3_HT bit 3MAIN[14][28][11]MAIN[38][29][52]
CLKOUT3_HT bit 4MAIN[14][29][10]MAIN[38][28][53]
CLKOUT3_HT bit 5MAIN[14][28][10]MAIN[38][29][53]
CLKOUT3_LT bit 0MAIN[14][29][15]MAIN[38][28][48]
CLKOUT3_LT bit 1MAIN[14][28][15]MAIN[38][29][48]
CLKOUT3_LT bit 2MAIN[14][29][14]MAIN[38][28][49]
CLKOUT3_LT bit 3MAIN[14][28][14]MAIN[38][29][49]
CLKOUT3_LT bit 4MAIN[14][29][13]MAIN[38][28][50]
CLKOUT3_LT bit 5MAIN[14][28][13]MAIN[38][29][50]
CLKOUT3_MX bit 0MAIN[14][29][3]MAIN[38][28][60]
CLKOUT3_MX bit 1MAIN[14][28][3]MAIN[38][29][60]
CLKOUT3_PM bit 0MAIN[14][28][9]MAIN[38][29][54]
CLKOUT3_PM bit 1MAIN[14][29][8]MAIN[38][28][55]
CLKOUT3_PM bit 2MAIN[14][28][8]MAIN[38][29][55]
CLKOUT3_USE_FINE_PSMAIN[14][29][3]-
CLKOUT4_ENMAIN[13][29][57]MAIN[39][28][6]
CLKOUT4_NOCOUNTMAIN[13][29][52]MAIN[39][28][11]
CLKOUT4_EDGEMAIN[13][28][52]MAIN[39][29][11]
CLKOUT4_DT bit 0MAIN[13][29][55]MAIN[39][28][8]
CLKOUT4_DT bit 1MAIN[13][28][55]MAIN[39][29][8]
CLKOUT4_DT bit 2MAIN[13][29][54]MAIN[39][28][9]
CLKOUT4_DT bit 3MAIN[13][28][54]MAIN[39][29][9]
CLKOUT4_DT bit 4MAIN[13][29][53]MAIN[39][28][10]
CLKOUT4_DT bit 5MAIN[13][28][53]MAIN[39][29][10]
CLKOUT4_HT bit 0MAIN[13][29][60]MAIN[39][28][3]
CLKOUT4_HT bit 1MAIN[13][28][60]MAIN[39][29][3]
CLKOUT4_HT bit 2MAIN[13][29][59]MAIN[39][28][4]
CLKOUT4_HT bit 3MAIN[13][28][59]MAIN[39][29][4]
CLKOUT4_HT bit 4MAIN[13][29][58]MAIN[39][28][5]
CLKOUT4_HT bit 5MAIN[13][28][58]MAIN[39][29][5]
CLKOUT4_LT bit 0MAIN[13][29][63]MAIN[39][28][0]
CLKOUT4_LT bit 1MAIN[13][28][63]MAIN[39][29][0]
CLKOUT4_LT bit 2MAIN[13][29][62]MAIN[39][28][1]
CLKOUT4_LT bit 3MAIN[13][28][62]MAIN[39][29][1]
CLKOUT4_LT bit 4MAIN[13][29][61]MAIN[39][28][2]
CLKOUT4_LT bit 5MAIN[13][28][61]MAIN[39][29][2]
CLKOUT4_MX bit 0MAIN[13][29][51]MAIN[39][28][12]
CLKOUT4_MX bit 1MAIN[13][28][51]MAIN[39][29][12]
CLKOUT4_PM bit 0MAIN[13][28][57]MAIN[39][29][6]
CLKOUT4_PM bit 1MAIN[13][29][56]MAIN[39][28][7]
CLKOUT4_PM bit 2MAIN[13][28][56]MAIN[39][29][7]
CLKOUT4_USE_FINE_PSMAIN[13][29][51]-
CLKOUT5_ENMAIN[15][29][9]MAIN[37][28][54]
CLKOUT5_NOCOUNTMAIN[15][29][4]MAIN[37][28][59]
CLKOUT5_EDGEMAIN[15][28][4]MAIN[37][29][59]
CLKOUT5_DT bit 0MAIN[15][29][7]MAIN[37][28][56]
CLKOUT5_DT bit 1MAIN[15][28][7]MAIN[37][29][56]
CLKOUT5_DT bit 2MAIN[15][29][6]MAIN[37][28][57]
CLKOUT5_DT bit 3MAIN[15][28][6]MAIN[37][29][57]
CLKOUT5_DT bit 4MAIN[15][29][5]MAIN[37][28][58]
CLKOUT5_DT bit 5MAIN[15][28][5]MAIN[37][29][58]
CLKOUT5_HT bit 0MAIN[15][29][12]MAIN[37][28][51]
CLKOUT5_HT bit 1MAIN[15][28][12]MAIN[37][29][51]
CLKOUT5_HT bit 2MAIN[15][29][11]MAIN[37][28][52]
CLKOUT5_HT bit 3MAIN[15][28][11]MAIN[37][29][52]
CLKOUT5_HT bit 4MAIN[15][29][10]MAIN[37][28][53]
CLKOUT5_HT bit 5MAIN[15][28][10]MAIN[37][29][53]
CLKOUT5_LT bit 0MAIN[15][29][15]MAIN[37][28][48]
CLKOUT5_LT bit 1MAIN[15][28][15]MAIN[37][29][48]
CLKOUT5_LT bit 2MAIN[15][29][14]MAIN[37][28][49]
CLKOUT5_LT bit 3MAIN[15][28][14]MAIN[37][29][49]
CLKOUT5_LT bit 4MAIN[15][29][13]MAIN[37][28][50]
CLKOUT5_LT bit 5MAIN[15][28][13]MAIN[37][29][50]
CLKOUT5_MX bit 0MAIN[15][29][3]MAIN[37][28][60]
CLKOUT5_MX bit 1MAIN[15][28][3]MAIN[37][29][60]
CLKOUT5_PM bit 0MAIN[15][28][9]MAIN[37][29][54]
CLKOUT5_PM bit 1MAIN[15][29][8]MAIN[37][28][55]
CLKOUT5_PM bit 2MAIN[15][28][8]MAIN[37][29][55]
CLKOUT5_USE_FINE_PSMAIN[15][29][3]-
CLKOUT6_ENMAIN[13][29][41]-
CLKOUT6_NOCOUNTMAIN[13][29][36]-
CLKOUT6_EDGEMAIN[13][28][36]-
CLKOUT6_DT bit 0MAIN[13][29][39]-
CLKOUT6_DT bit 1MAIN[13][28][39]-
CLKOUT6_DT bit 2MAIN[13][29][38]-
CLKOUT6_DT bit 3MAIN[13][28][38]-
CLKOUT6_DT bit 4MAIN[13][29][37]-
CLKOUT6_DT bit 5MAIN[13][28][37]-
CLKOUT6_HT bit 0MAIN[13][29][44]-
CLKOUT6_HT bit 1MAIN[13][28][44]-
CLKOUT6_HT bit 2MAIN[13][29][43]-
CLKOUT6_HT bit 3MAIN[13][28][43]-
CLKOUT6_HT bit 4MAIN[13][29][42]-
CLKOUT6_HT bit 5MAIN[13][28][42]-
CLKOUT6_LT bit 0MAIN[13][29][47]-
CLKOUT6_LT bit 1MAIN[13][28][47]-
CLKOUT6_LT bit 2MAIN[13][29][46]-
CLKOUT6_LT bit 3MAIN[13][28][46]-
CLKOUT6_LT bit 4MAIN[13][29][45]-
CLKOUT6_LT bit 5MAIN[13][28][45]-
CLKOUT6_MX bit 0MAIN[13][29][35]-
CLKOUT6_MX bit 1MAIN[13][28][35]-
CLKOUT6_PM bit 0MAIN[13][28][41]-
CLKOUT6_PM bit 1MAIN[13][29][40]-
CLKOUT6_PM bit 2MAIN[13][28][40]-
CLKOUT6_USE_FINE_PSMAIN[13][29][35]-
CLKOUT0_PM_RISE bit 0MAIN[14][28][57]-
CLKOUT0_PM_RISE bit 1MAIN[14][29][56]-
CLKOUT0_PM_RISE bit 2MAIN[14][28][56]-
CLKOUT0_PM_FALL bit 0MAIN[15][28][2]-
CLKOUT0_PM_FALL bit 1MAIN[15][29][1]-
CLKOUT0_PM_FALL bit 2MAIN[15][28][1]-
CLKFBOUT_ENMAIN[13][29][25]MAIN[39][28][38]
CLKFBOUT_NOCOUNTMAIN[13][29][20]MAIN[39][28][43]
CLKFBOUT_EDGEMAIN[13][28][20]MAIN[39][29][43]
CLKFBOUT_DT bit 0MAIN[13][29][23]MAIN[39][28][40]
CLKFBOUT_DT bit 1MAIN[13][28][23]MAIN[39][29][40]
CLKFBOUT_DT bit 2MAIN[13][29][22]MAIN[39][28][41]
CLKFBOUT_DT bit 3MAIN[13][28][22]MAIN[39][29][41]
CLKFBOUT_DT bit 4MAIN[13][29][21]MAIN[39][28][42]
CLKFBOUT_DT bit 5MAIN[13][28][21]MAIN[39][29][42]
CLKFBOUT_HT bit 0MAIN[13][29][28]MAIN[39][28][35]
CLKFBOUT_HT bit 1MAIN[13][28][28]MAIN[39][29][35]
CLKFBOUT_HT bit 2MAIN[13][29][27]MAIN[39][28][36]
CLKFBOUT_HT bit 3MAIN[13][28][27]MAIN[39][29][36]
CLKFBOUT_HT bit 4MAIN[13][29][26]MAIN[39][28][37]
CLKFBOUT_HT bit 5MAIN[13][28][26]MAIN[39][29][37]
CLKFBOUT_LT bit 0MAIN[13][29][31]MAIN[39][28][32]
CLKFBOUT_LT bit 1MAIN[13][28][31]MAIN[39][29][32]
CLKFBOUT_LT bit 2MAIN[13][29][30]MAIN[39][28][33]
CLKFBOUT_LT bit 3MAIN[13][28][30]MAIN[39][29][33]
CLKFBOUT_LT bit 4MAIN[13][29][29]MAIN[39][28][34]
CLKFBOUT_LT bit 5MAIN[13][28][29]MAIN[39][29][34]
CLKFBOUT_MX bit 0MAIN[13][29][19]MAIN[39][28][44]
CLKFBOUT_MX bit 1MAIN[13][28][19]MAIN[39][29][44]
CLKFBOUT_PM bit 0-MAIN[39][29][38]
CLKFBOUT_PM bit 1-MAIN[39][28][39]
CLKFBOUT_PM bit 2-MAIN[39][29][39]
CLKFBOUT_PM_RISE bit 0MAIN[13][28][25]-
CLKFBOUT_PM_RISE bit 1MAIN[13][29][24]-
CLKFBOUT_PM_RISE bit 2MAIN[13][28][24]-
CLKFBOUT_PM_FALL bit 0MAIN[13][28][34]-
CLKFBOUT_PM_FALL bit 1MAIN[13][29][33]-
CLKFBOUT_PM_FALL bit 2MAIN[13][28][33]-
CLKFBOUT_USE_FINE_PSMAIN[13][29][19]-
CLKOUT0_FRAC_ENMAIN[14][28][50]-
CLKOUT0_FRAC bit 0MAIN[14][29][49]-
CLKOUT0_FRAC bit 1MAIN[14][28][49]-
CLKOUT0_FRAC bit 2MAIN[14][29][48]-
CLKFBOUT_FRAC_ENMAIN[13][28][18]-
CLKFBOUT_FRAC bit 0MAIN[13][29][17]-
CLKFBOUT_FRAC bit 1MAIN[13][28][17]-
CLKFBOUT_FRAC bit 2MAIN[13][29][16]-
CLKOUT4_CASCADEMAIN[13][28][51]-
FINE_PS_FRAC bit 0MAIN[1][28][29]-
FINE_PS_FRAC bit 1MAIN[1][29][28]-
FINE_PS_FRAC bit 2MAIN[1][28][28]-
FINE_PS_FRAC bit 3MAIN[1][29][27]-
FINE_PS_FRAC bit 4MAIN[1][28][27]-
FINE_PS_FRAC bit 5MAIN[1][29][26]-
CLKOUT0_FRAC_WF_RISEMAIN[14][29][50]-
CLKOUT0_FRAC_WF_FALLMAIN[15][29][2]-
CLKFBOUT_FRAC_WF_RISEMAIN[13][29][18]-
CLKFBOUT_FRAC_WF_FALLMAIN[13][29][34]-
DIVCLK_NOCOUNTMAIN[13][29][9]MAIN[39][28][54]
DIVCLK_EDGEMAIN[13][28][9]MAIN[39][29][54]
DIVCLK_HT bit 0MAIN[13][29][12]MAIN[39][28][51]
DIVCLK_HT bit 1MAIN[13][28][12]MAIN[39][29][51]
DIVCLK_HT bit 2MAIN[13][29][11]MAIN[39][28][52]
DIVCLK_HT bit 3MAIN[13][28][11]MAIN[39][29][52]
DIVCLK_HT bit 4MAIN[13][29][10]MAIN[39][28][53]
DIVCLK_HT bit 5MAIN[13][28][10]MAIN[39][29][53]
DIVCLK_LT bit 0MAIN[13][29][15]MAIN[39][28][48]
DIVCLK_LT bit 1MAIN[13][28][15]MAIN[39][29][48]
DIVCLK_LT bit 2MAIN[13][29][14]MAIN[39][28][49]
DIVCLK_LT bit 3MAIN[13][28][14]MAIN[39][29][49]
DIVCLK_LT bit 4MAIN[13][29][13]MAIN[39][28][50]
DIVCLK_LT bit 5MAIN[13][28][13]MAIN[39][29][50]
CLKFBIN_NOCOUNTMAIN[13][29][1]MAIN[39][28][62]
CLKFBIN_EDGEMAIN[13][28][1]MAIN[39][29][62]
CLKFBIN_HT bit 0MAIN[13][29][4]MAIN[39][28][59]
CLKFBIN_HT bit 1MAIN[13][28][4]MAIN[39][29][59]
CLKFBIN_HT bit 2MAIN[13][29][3]MAIN[39][28][60]
CLKFBIN_HT bit 3MAIN[13][28][3]MAIN[39][29][60]
CLKFBIN_HT bit 4MAIN[13][29][2]MAIN[39][28][61]
CLKFBIN_HT bit 5MAIN[13][28][2]MAIN[39][29][61]
CLKFBIN_LT bit 0MAIN[13][29][7]MAIN[39][28][56]
CLKFBIN_LT bit 1MAIN[13][28][7]MAIN[39][29][56]
CLKFBIN_LT bit 2MAIN[13][29][6]MAIN[39][28][57]
CLKFBIN_LT bit 3MAIN[13][28][6]MAIN[39][29][57]
CLKFBIN_LT bit 4MAIN[13][29][5]MAIN[39][28][58]
CLKFBIN_LT bit 5MAIN[13][28][5]MAIN[39][29][58]

Bels PHASER_IN

virtex7 CMT bel PHASER_IN pins
PinDirectionPHASER_IN[0]PHASER_IN[1]PHASER_IN[2]PHASER_IN[3]
FREQREFCLKinCELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]
MEMREFCLKinCELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]
SYNCINinCELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]
PHASEREFCLKinCELL[25].IMUX_PHASER_IN_PHASEREFCLK[0]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2]CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3]
SYSCLKinCELL[18].IMUX_CLK[0]CELL[22].IMUX_CLK[0]CELL[29].IMUX_CLK[0]CELL[33].IMUX_CLK[0]
RSTinCELL[20].IMUX_IMUX[12] invert by MAIN[18][28][59]CELL[23].IMUX_IMUX[47] invert by MAIN[22][28][27]CELL[29].IMUX_IMUX[11] invert by MAIN[28][28][59]CELL[32].IMUX_IMUX[39] invert by MAIN[32][28][27]
DIVIDERSTinCELL[18].IMUX_IMUX[19]CELL[23].IMUX_IMUX[19]CELL[27].IMUX_IMUX[19]CELL[31].IMUX_IMUX[19]
BURSTPENDINGinCELL[20].IMUX_IMUX[18]CELL[23].IMUX_IMUX[27]CELL[28].IMUX_IMUX[9]CELL[32].IMUX_IMUX[2]
EDGEADVinCELL[20].IMUX_IMUX[34]CELL[23].IMUX_IMUX[14]CELL[29].IMUX_IMUX[41]CELL[32].IMUX_IMUX[14]
RANKSEL[0]inCELL[20].IMUX_IMUX[27]CELL[23].IMUX_IMUX[15]CELL[29].IMUX_IMUX[34]CELL[32].IMUX_IMUX[15]
RANKSEL[1]inCELL[20].IMUX_IMUX[43]CELL[23].IMUX_IMUX[31]CELL[29].IMUX_IMUX[3]CELL[32].IMUX_IMUX[23]
ENCALIB[0]inCELL[20].IMUX_IMUX[11]CELL[23].IMUX_IMUX[30]CELL[29].IMUX_IMUX[2]CELL[32].IMUX_IMUX[30]
ENCALIB[1]inCELL[20].IMUX_IMUX[19]CELL[23].IMUX_IMUX[46]CELL[29].IMUX_IMUX[18]CELL[32].IMUX_IMUX[46]
ENSTG1inCELL[18].IMUX_IMUX[31]CELL[23].IMUX_IMUX[4]CELL[29].IMUX_IMUX[8]CELL[32].IMUX_IMUX[34]
ENSTG1ADJUSTBinCELL[19].IMUX_IMUX[39]CELL[23].IMUX_IMUX[45]CELL[29].IMUX_IMUX[17]CELL[32].IMUX_IMUX[45]
RSTDQSFINDinCELL[19].IMUX_IMUX[8]CELL[23].IMUX_IMUX[0]CELL[28].IMUX_IMUX[0]CELL[32].IMUX_IMUX[8]
SELCALORSTG1inCELL[20].IMUX_IMUX[10]CELL[23].IMUX_IMUX[11]CELL[28].IMUX_IMUX[1]CELL[32].IMUX_IMUX[41]
FINEENABLEinCELL[19].IMUX_IMUX[30]CELL[23].IMUX_IMUX[44]CELL[29].IMUX_IMUX[32]CELL[31].IMUX_IMUX[46]
FINEINCinCELL[19].IMUX_IMUX[14]CELL[22].IMUX_IMUX[47]CELL[28].IMUX_IMUX[47]CELL[31].IMUX_IMUX[30]
COUNTERLOADENinCELL[19].IMUX_IMUX[45]CELL[22].IMUX_IMUX[31]CELL[28].IMUX_IMUX[31]CELL[31].IMUX_IMUX[14]
COUNTERLOADVAL[0]inCELL[19].IMUX_IMUX[11]CELL[22].IMUX_IMUX[44]CELL[28].IMUX_IMUX[44]CELL[32].IMUX_IMUX[19]
COUNTERLOADVAL[1]inCELL[19].IMUX_IMUX[19]CELL[22].IMUX_IMUX[13]CELL[28].IMUX_IMUX[13]CELL[32].IMUX_IMUX[27]
COUNTERLOADVAL[2]inCELL[19].IMUX_IMUX[27]CELL[22].IMUX_IMUX[29]CELL[28].IMUX_IMUX[29]CELL[32].IMUX_IMUX[43]
COUNTERLOADVAL[3]inCELL[19].IMUX_IMUX[43]CELL[22].IMUX_IMUX[45]CELL[28].IMUX_IMUX[45]CELL[32].IMUX_IMUX[12]
COUNTERLOADVAL[4]inCELL[19].IMUX_IMUX[12]CELL[22].IMUX_IMUX[14]CELL[28].IMUX_IMUX[14]CELL[32].IMUX_IMUX[28]
COUNTERLOADVAL[5]inCELL[19].IMUX_IMUX[28]CELL[22].IMUX_IMUX[30]CELL[28].IMUX_IMUX[30]CELL[32].IMUX_IMUX[44]
COUNTERREADENinCELL[19].IMUX_IMUX[29]CELL[22].IMUX_IMUX[23]CELL[28].IMUX_IMUX[23]CELL[31].IMUX_IMUX[45]
STG1INCDECinCELL[18].IMUX_IMUX[47]CELL[23].IMUX_IMUX[20]CELL[29].IMUX_IMUX[24]CELL[32].IMUX_IMUX[11]
STG1LOADinCELL[18].IMUX_IMUX[23]CELL[23].IMUX_IMUX[43]CELL[28].IMUX_IMUX[20]CELL[32].IMUX_IMUX[18]
STG1READinCELL[18].IMUX_IMUX[15]CELL[22].IMUX_IMUX[20]CELL[28].IMUX_IMUX[4]CELL[30].IMUX_IMUX[47]
STG1REGL[0]inCELL[19].IMUX_IMUX[0]CELL[22].IMUX_IMUX[41]CELL[28].IMUX_IMUX[17]CELL[30].IMUX_IMUX[44]
STG1REGL[1]inCELL[19].IMUX_IMUX[16]CELL[22].IMUX_IMUX[2]CELL[28].IMUX_IMUX[41]CELL[30].IMUX_IMUX[13]
STG1REGL[2]inCELL[19].IMUX_IMUX[32]CELL[22].IMUX_IMUX[18]CELL[28].IMUX_IMUX[2]CELL[30].IMUX_IMUX[29]
STG1REGL[3]inCELL[19].IMUX_IMUX[9]CELL[22].IMUX_IMUX[34]CELL[28].IMUX_IMUX[18]CELL[30].IMUX_IMUX[45]
STG1REGL[4]inCELL[19].IMUX_IMUX[33]CELL[22].IMUX_IMUX[3]CELL[28].IMUX_IMUX[34]CELL[30].IMUX_IMUX[14]
STG1REGL[5]inCELL[19].IMUX_IMUX[41]CELL[22].IMUX_IMUX[11]CELL[28].IMUX_IMUX[3]CELL[30].IMUX_IMUX[30]
STG1REGL[6]inCELL[19].IMUX_IMUX[10]CELL[22].IMUX_IMUX[27]CELL[28].IMUX_IMUX[11]CELL[30].IMUX_IMUX[46]
STG1REGL[7]inCELL[19].IMUX_IMUX[18]CELL[22].IMUX_IMUX[43]CELL[28].IMUX_IMUX[27]CELL[30].IMUX_IMUX[15]
STG1REGL[8]inCELL[19].IMUX_IMUX[34]CELL[22].IMUX_IMUX[4]CELL[28].IMUX_IMUX[43]CELL[30].IMUX_IMUX[31]
TESTIN[0]inCELL[18].IMUX_IMUX[43]CELL[22].IMUX_IMUX[8]CELL[27].IMUX_IMUX[43]CELL[31].IMUX_IMUX[11]
TESTIN[1]inCELL[18].IMUX_IMUX[4]CELL[22].IMUX_IMUX[24]CELL[27].IMUX_IMUX[4]CELL[31].IMUX_IMUX[27]
TESTIN[2]inCELL[18].IMUX_IMUX[20]CELL[22].IMUX_IMUX[32]CELL[27].IMUX_IMUX[20]CELL[31].IMUX_IMUX[43]
TESTIN[3]inCELL[18].IMUX_IMUX[44]CELL[22].IMUX_IMUX[1]CELL[27].IMUX_IMUX[44]CELL[31].IMUX_IMUX[12]
TESTIN[4]inCELL[18].IMUX_IMUX[13]CELL[23].IMUX_IMUX[8]CELL[27].IMUX_IMUX[13]CELL[31].IMUX_IMUX[20]
TESTIN[5]inCELL[18].IMUX_IMUX[29]CELL[23].IMUX_IMUX[24]CELL[27].IMUX_IMUX[29]CELL[31].IMUX_IMUX[28]
TESTIN[6]inCELL[18].IMUX_IMUX[45]CELL[23].IMUX_IMUX[32]CELL[27].IMUX_IMUX[45]CELL[31].IMUX_IMUX[44]
TESTIN[7]inCELL[18].IMUX_IMUX[14]CELL[23].IMUX_IMUX[1]CELL[27].IMUX_IMUX[14]CELL[31].IMUX_IMUX[21]
TESTIN[8]inCELL[20].IMUX_IMUX[0]CELL[23].IMUX_IMUX[9]CELL[27].IMUX_IMUX[30]CELL[31].IMUX_IMUX[29]
TESTIN[9]inCELL[20].IMUX_IMUX[16]CELL[23].IMUX_IMUX[41]CELL[27].IMUX_IMUX[46]CELL[32].IMUX_IMUX[0]
TESTIN[10]inCELL[20].IMUX_IMUX[32]CELL[23].IMUX_IMUX[2]CELL[27].IMUX_IMUX[15]CELL[32].IMUX_IMUX[16]
TESTIN[11]inCELL[20].IMUX_IMUX[9]CELL[23].IMUX_IMUX[18]CELL[28].IMUX_IMUX[8]CELL[32].IMUX_IMUX[32]
TESTIN[12]inCELL[20].IMUX_IMUX[41]CELL[23].IMUX_IMUX[34]CELL[28].IMUX_IMUX[24]CELL[32].IMUX_IMUX[9]
TESTIN[13]inCELL[20].IMUX_IMUX[2]CELL[23].IMUX_IMUX[3]CELL[28].IMUX_IMUX[32]CELL[32].IMUX_IMUX[33]
SCANCLKinCELL[18].IMUX_CLK[1]CELL[22].IMUX_CLK[1]CELL[29].IMUX_CLK[1]CELL[33].IMUX_CLK[1]
SCANMODEBinCELL[19].IMUX_IMUX[15]CELL[23].IMUX_IMUX[29]CELL[29].IMUX_IMUX[9]CELL[31].IMUX_IMUX[31]
SCANENBinCELL[18].IMUX_IMUX[46]CELL[22].IMUX_IMUX[17]CELL[27].IMUX_IMUX[47]CELL[30].IMUX_IMUX[20]
SCANINinCELL[18].IMUX_IMUX[30]CELL[22].IMUX_IMUX[9]CELL[27].IMUX_IMUX[31]CELL[30].IMUX_IMUX[4]
RCLKoutCELL[25].OUT_PHASER_IN_RCLK[0]CELL[25].OUT_PHASER_IN_RCLK[1]CELL[25].OUT_PHASER_IN_RCLK[2]CELL[25].OUT_PHASER_IN_RCLK[3]
ICLKoutCELL[7].PHASER_ICLKCELL[19].PHASER_ICLKCELL[31].PHASER_ICLKCELL[43].PHASER_ICLK
ICLKDIVoutCELL[7].PHASER_ICLKDIVCELL[19].PHASER_ICLKDIVCELL[31].PHASER_ICLKDIVCELL[43].PHASER_ICLKDIV
WRENABLEoutCELL[7].PHASER_IWRENCELL[19].PHASER_IWRENCELL[31].PHASER_IWRENCELL[43].PHASER_IWREN
ISERDESRSToutCELL[18].OUT_BEL[18]CELL[22].OUT_BEL[6]CELL[28].OUT_BEL[10]CELL[33].OUT_BEL[18]
PHASELOCKEDoutCELL[18].OUT_BEL[17]CELL[22].OUT_BEL[17]CELL[27].OUT_BEL[17]CELL[31].OUT_BEL[17]
DQSFOUNDoutCELL[18].OUT_BEL[23]CELL[22].OUT_BEL[16]CELL[28].OUT_BEL[6]CELL[33].OUT_BEL[23]
DQSOUTOFRANGEoutCELL[20].OUT_BEL[18]CELL[23].OUT_BEL[14]CELL[28].OUT_BEL[15]CELL[31].OUT_BEL[9]
FINEOVERFLOWoutCELL[19].OUT_BEL[1]CELL[22].OUT_BEL[3]CELL[27].OUT_BEL[2]CELL[31].OUT_BEL[6]
COUNTERREADVAL[0]outCELL[18].OUT_BEL[15]CELL[23].OUT_BEL[2]CELL[27].OUT_BEL[15]CELL[31].OUT_BEL[15]
COUNTERREADVAL[1]outCELL[18].OUT_BEL[3]CELL[23].OUT_BEL[15]CELL[27].OUT_BEL[3]CELL[31].OUT_BEL[21]
COUNTERREADVAL[2]outCELL[18].OUT_BEL[21]CELL[23].OUT_BEL[3]CELL[27].OUT_BEL[21]CELL[32].OUT_BEL[18]
COUNTERREADVAL[3]outCELL[18].OUT_BEL[7]CELL[23].OUT_BEL[21]CELL[27].OUT_BEL[7]CELL[32].OUT_BEL[1]
COUNTERREADVAL[4]outCELL[19].OUT_BEL[6]CELL[24].OUT_BEL[10]CELL[28].OUT_BEL[3]CELL[32].OUT_BEL[9]
COUNTERREADVAL[5]outCELL[19].OUT_BEL[16]CELL[24].OUT_BEL[6]CELL[28].OUT_BEL[21]CELL[32].OUT_BEL[6]
STG1OVERFLOWoutCELL[19].OUT_BEL[17]CELL[22].OUT_BEL[7]CELL[29].OUT_BEL[16]CELL[32].OUT_BEL[17]
STG1REGR[0]outCELL[18].OUT_BEL[10]CELL[22].OUT_BEL[14]CELL[28].OUT_BEL[16]CELL[33].OUT_BEL[10]
STG1REGR[1]outCELL[18].OUT_BEL[6]CELL[22].OUT_BEL[2]CELL[28].OUT_BEL[14]CELL[33].OUT_BEL[6]
STG1REGR[2]outCELL[18].OUT_BEL[16]CELL[22].OUT_BEL[15]CELL[28].OUT_BEL[2]CELL[33].OUT_BEL[16]
STG1REGR[3]outCELL[18].OUT_BEL[14]CELL[23].OUT_BEL[23]CELL[29].OUT_BEL[18]CELL[33].OUT_BEL[14]
STG1REGR[4]outCELL[18].OUT_BEL[2]CELL[23].OUT_BEL[10]CELL[29].OUT_BEL[23]CELL[33].OUT_BEL[2]
STG1REGR[5]outCELL[19].OUT_BEL[4]CELL[23].OUT_BEL[6]CELL[29].OUT_BEL[10]CELL[33].OUT_BEL[15]
STG1REGR[6]outCELL[19].OUT_BEL[18]CELL[23].OUT_BEL[16]CELL[29].OUT_BEL[6]CELL[33].OUT_BEL[3]
STG1REGR[7]outCELL[19].OUT_BEL[0]CELL[24].OUT_BEL[18]CELL[30].OUT_BEL[18]CELL[33].OUT_BEL[21]
STG1REGR[8]outCELL[20].OUT_BEL[4]CELL[24].OUT_BEL[23]CELL[30].OUT_BEL[23]CELL[33].OUT_BEL[7]
TESTOUT[0]outCELL[17].OUT_BEL[2]CELL[21].OUT_BEL[7]CELL[27].OUT_BEL[6]CELL[30].OUT_BEL[7]
TESTOUT[1]outCELL[17].OUT_BEL[3]CELL[21].OUT_BEL[17]CELL[27].OUT_BEL[16]CELL[30].OUT_BEL[17]
TESTOUT[2]outCELL[17].OUT_BEL[21]CELL[22].OUT_BEL[23]CELL[28].OUT_BEL[18]CELL[31].OUT_BEL[0]
TESTOUT[3]outCELL[17].OUT_BEL[7]CELL[22].OUT_BEL[10]CELL[28].OUT_BEL[23]CELL[32].OUT_BEL[4]
SCANOUToutCELL[17].OUT_BEL[17]CELL[23].OUT_BEL[18]CELL[27].OUT_BEL[14]CELL[31].OUT_BEL[1]
virtex7 CMT bel PHASER_IN attribute bits
AttributePHASER_IN[0]PHASER_IN[1]PHASER_IN[2]PHASER_IN[3]
BURST_MODEMAIN[19][29][26]MAIN[22][29][58]MAIN[29][29][26]MAIN[32][29][58]
CLKOUT_DIV[enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV]
CLKOUT_DIV_ST bit 0MAIN[19][29][54]MAIN[23][29][22]MAIN[29][29][54]MAIN[33][29][22]
CLKOUT_DIV_ST bit 1MAIN[19][28][55]MAIN[23][28][23]MAIN[29][28][55]MAIN[33][28][23]
CLKOUT_DIV_ST bit 2MAIN[19][29][55]MAIN[23][29][23]MAIN[29][29][55]MAIN[33][29][23]
CLKOUT_DIV_ST bit 3MAIN[19][28][56]MAIN[23][28][24]MAIN[29][28][56]MAIN[33][28][24]
CTL_MODE[enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE]
DQS_AUTO_RECAL bit 0MAIN[18][28][49]MAIN[22][28][17]MAIN[28][28][49]MAIN[32][28][17]
DQS_BIAS_MODEMAIN[18][29][49]MAIN[22][29][17]MAIN[28][29][49]MAIN[32][29][17]
DQS_FIND_PATTERN bit 0MAIN[19][28][22]MAIN[22][28][54]MAIN[29][28][22]MAIN[32][28][54]
DQS_FIND_PATTERN bit 1MAIN[19][29][22]MAIN[22][29][54]MAIN[29][29][22]MAIN[32][29][54]
DQS_FIND_PATTERN bit 2MAIN[19][28][23]MAIN[22][28][55]MAIN[29][28][23]MAIN[32][28][55]
EN_ISERDES_RSTMAIN[18][29][55]MAIN[22][29][23]MAIN[28][29][55]MAIN[32][29][23]
EN_TEST_RINGMAIN[19][29][23]MAIN[22][29][55]MAIN[29][29][23]MAIN[32][29][55]
FINE_DELAY bit 0MAIN[19][28][51]MAIN[23][28][19]MAIN[29][28][51]MAIN[33][28][19]
FINE_DELAY bit 1MAIN[19][29][51]MAIN[23][29][19]MAIN[29][29][51]MAIN[33][29][19]
FINE_DELAY bit 2MAIN[19][28][52]MAIN[23][28][20]MAIN[29][28][52]MAIN[33][28][20]
FINE_DELAY bit 3MAIN[19][29][52]MAIN[23][29][20]MAIN[29][29][52]MAIN[33][29][20]
FINE_DELAY bit 4MAIN[19][28][53]MAIN[23][28][21]MAIN[29][28][53]MAIN[33][28][21]
FINE_DELAY bit 5MAIN[19][29][53]MAIN[23][29][21]MAIN[29][29][53]MAIN[33][29][21]
FREQ_REF_DIV[enum: PHASER_IN_FREQ_REF_DIV][enum: PHASER_IN_FREQ_REF_DIV][enum: PHASER_IN_FREQ_REF_DIV][enum: PHASER_IN_FREQ_REF_DIV]
HALF_CYCLE_ADJMAIN[18][28][60]MAIN[22][28][28]MAIN[28][28][60]MAIN[32][28][28]
ICLK_TO_RCLK_BYPASSMAIN[18][28][56]MAIN[22][28][24]MAIN[28][28][56]MAIN[32][28][24]
OUTPUT_CLK_SRC[enum: PHASER_IN_OUTPUT_CLK_SRC][enum: PHASER_IN_OUTPUT_CLK_SRC][enum: PHASER_IN_OUTPUT_CLK_SRC][enum: PHASER_IN_OUTPUT_CLK_SRC]
PD_REVERSE[enum: PHASER_IN_PD_REVERSE][enum: PHASER_IN_PD_REVERSE][enum: PHASER_IN_PD_REVERSE][enum: PHASER_IN_PD_REVERSE]
PHASER_IN_ENMAIN[18][28][55]MAIN[22][28][23]MAIN[28][28][55]MAIN[32][28][23]
RD_ADDR_INIT bit 0MAIN[18][28][51]MAIN[22][28][19]MAIN[28][28][51]MAIN[32][28][19]
RD_ADDR_INIT bit 1MAIN[18][29][51]MAIN[22][29][19]MAIN[28][29][51]MAIN[32][29][19]
REG_OPT_1 bit 0MAIN[18][28][50]MAIN[22][28][18]MAIN[28][28][50]MAIN[32][28][18]
REG_OPT_2 bit 0MAIN[18][29][61]MAIN[22][29][29]MAIN[28][29][61]MAIN[32][29][29]
REG_OPT_4 bit 0MAIN[18][29][50]MAIN[22][29][18]MAIN[28][29][50]MAIN[32][29][18]
RST_SEL bit 0MAIN[18][28][61]MAIN[22][28][29]MAIN[28][28][61]MAIN[32][28][29]
SEL_CLK_OFFSET bit 0MAIN[18][29][52]MAIN[22][29][20]MAIN[28][29][52]MAIN[32][29][20]
SEL_CLK_OFFSET bit 1MAIN[18][28][53]MAIN[22][28][21]MAIN[28][28][53]MAIN[32][28][21]
SEL_CLK_OFFSET bit 2MAIN[18][29][60]MAIN[22][29][28]MAIN[28][29][60]MAIN[32][29][28]
SEL_OUT bit 0MAIN[18][28][52]MAIN[22][28][20]MAIN[28][28][52]MAIN[32][28][20]
STG1_PD_UPDATE[enum: PHASER_IN_STG1_PD_UPDATE][enum: PHASER_IN_STG1_PD_UPDATE][enum: PHASER_IN_STG1_PD_UPDATE][enum: PHASER_IN_STG1_PD_UPDATE]
SYNC_IN_DIV_RSTMAIN[19][28][54]MAIN[23][28][22]MAIN[29][28][54]MAIN[33][28][22]
TEST_BP bit 0MAIN[18][29][48]MAIN[22][29][16]MAIN[28][29][48]MAIN[32][29][16]
UPDATE_NONACTIVEMAIN[18][28][48]MAIN[22][28][16]MAIN[28][28][48]MAIN[32][28][16]
WR_CYCLESMAIN[18][29][54]MAIN[22][29][22]MAIN[28][29][54]MAIN[32][29][22]
virtex7 CMT enum PHASER_CLKOUT_DIV
PHASER_IN[0].CLKOUT_DIVMAIN[19][28][58]MAIN[19][29][57]MAIN[19][28][57]MAIN[19][29][56]MAIN[19][28][26]MAIN[19][29][25]MAIN[19][28][25]MAIN[19][29][24]
PHASER_IN[1].CLKOUT_DIVMAIN[23][28][26]MAIN[23][29][25]MAIN[23][28][25]MAIN[23][29][24]MAIN[22][28][58]MAIN[22][29][57]MAIN[22][28][57]MAIN[22][29][56]
PHASER_IN[2].CLKOUT_DIVMAIN[29][28][58]MAIN[29][29][57]MAIN[29][28][57]MAIN[29][29][56]MAIN[29][28][26]MAIN[29][29][25]MAIN[29][28][25]MAIN[29][29][24]
PHASER_IN[3].CLKOUT_DIVMAIN[33][28][26]MAIN[33][29][25]MAIN[33][28][25]MAIN[33][29][24]MAIN[32][28][58]MAIN[32][29][57]MAIN[32][28][57]MAIN[32][29][56]
NONE00000000
_200010000
_300010001
_400100010
_500100011
_600110100
_700110101
_801000110
_901000111
_1001011000
_1101011001
_1201101010
_1301101011
_1401111100
_1501111101
_1610001110
virtex7 CMT enum PHASER_CTL_MODE
PHASER_IN[0].CTL_MODEMAIN[19][28][24]
PHASER_IN[1].CTL_MODEMAIN[22][28][56]
PHASER_IN[2].CTL_MODEMAIN[29][28][24]
PHASER_IN[3].CTL_MODEMAIN[32][28][56]
SOFT0
HARD1
virtex7 CMT enum PHASER_IN_FREQ_REF_DIV
PHASER_IN[0].FREQ_REF_DIVMAIN[19][29][21]MAIN[19][28][21]
PHASER_IN[1].FREQ_REF_DIVMAIN[22][29][53]MAIN[22][28][53]
PHASER_IN[2].FREQ_REF_DIVMAIN[29][29][21]MAIN[29][28][21]
PHASER_IN[3].FREQ_REF_DIVMAIN[32][29][53]MAIN[32][28][53]
NONE00
DIV201
DIV410
virtex7 CMT enum PHASER_IN_OUTPUT_CLK_SRC
PHASER_IN[0].OUTPUT_CLK_SRCMAIN[18][28][57]MAIN[18][29][56]MAIN[18][28][54]MAIN[18][29][53]
PHASER_IN[1].OUTPUT_CLK_SRCMAIN[22][28][25]MAIN[22][29][24]MAIN[22][28][22]MAIN[22][29][21]
PHASER_IN[2].OUTPUT_CLK_SRCMAIN[28][28][57]MAIN[28][29][56]MAIN[28][28][54]MAIN[28][29][53]
PHASER_IN[3].OUTPUT_CLK_SRCMAIN[32][28][25]MAIN[32][29][24]MAIN[32][28][22]MAIN[32][29][21]
PHASE_REF0000
MEM_REF1000
FREQ_REF0010
DELAYED_REF0100
DELAYED_PHASE_REF1100
DELAYED_MEM_REF0101
virtex7 CMT enum PHASER_IN_PD_REVERSE
PHASER_IN[0].PD_REVERSEMAIN[19][28][20]MAIN[19][29][19]MAIN[19][28][19]
PHASER_IN[1].PD_REVERSEMAIN[22][28][52]MAIN[22][29][51]MAIN[22][28][51]
PHASER_IN[2].PD_REVERSEMAIN[29][28][20]MAIN[29][29][19]MAIN[29][28][19]
PHASER_IN[3].PD_REVERSEMAIN[32][28][52]MAIN[32][29][51]MAIN[32][28][51]
_1000
_2001
_3010
_4011
_5100
_6101
_7110
_8111
virtex7 CMT enum PHASER_IN_STG1_PD_UPDATE
PHASER_IN[0].STG1_PD_UPDATEMAIN[18][29][58]MAIN[18][28][58]MAIN[18][29][57]
PHASER_IN[1].STG1_PD_UPDATEMAIN[22][29][26]MAIN[22][28][26]MAIN[22][29][25]
PHASER_IN[2].STG1_PD_UPDATEMAIN[28][29][58]MAIN[28][28][58]MAIN[28][29][57]
PHASER_IN[3].STG1_PD_UPDATEMAIN[32][29][26]MAIN[32][28][26]MAIN[32][29][25]
_2000
_3001
_4010
_5011
_6100
_7101
_8110
_9111

Bels PHASER_OUT

virtex7 CMT bel PHASER_OUT pins
PinDirectionPHASER_OUT[0]PHASER_OUT[1]PHASER_OUT[2]PHASER_OUT[3]
FREQREFCLKinCELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]CELL[25].IMUX_PHASER_REFMUX[0]
MEMREFCLKinCELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]CELL[25].IMUX_PHASER_REFMUX[1]
SYNCINinCELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]CELL[25].IMUX_PHASER_REFMUX[2]
PHASEREFCLKinCELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2]CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3]
SYSCLKinCELL[17].IMUX_CLK[0]CELL[21].IMUX_CLK[0]CELL[27].IMUX_CLK[0]CELL[30].IMUX_CLK[0]
RSTinCELL[18].IMUX_IMUX[27] invert by MAIN[18][28][0]CELL[21].IMUX_IMUX[47] invert by MAIN[21][28][32]CELL[27].IMUX_IMUX[27] invert by MAIN[28][28][0]CELL[31].IMUX_IMUX[34] invert by MAIN[31][28][32]
DIVIDERSTinCELL[17].IMUX_IMUX[0]CELL[21].IMUX_IMUX[0]CELL[27].IMUX_IMUX[0]CELL[29].IMUX_IMUX[19]
BURSTPENDINGinCELL[18].IMUX_IMUX[3]CELL[21].IMUX_IMUX[23]CELL[27].IMUX_IMUX[3]CELL[31].IMUX_IMUX[2]
EDGEADVinCELL[18].IMUX_IMUX[2]CELL[21].IMUX_IMUX[30]CELL[27].IMUX_IMUX[2]CELL[31].IMUX_IMUX[9]
ENCALIB[0]inCELL[18].IMUX_IMUX[18]CELL[21].IMUX_IMUX[46]CELL[27].IMUX_IMUX[18]CELL[31].IMUX_IMUX[17]
ENCALIB[1]inCELL[18].IMUX_IMUX[34]CELL[21].IMUX_IMUX[15]CELL[27].IMUX_IMUX[34]CELL[31].IMUX_IMUX[41]
SELFINEOCLKDELAYinCELL[18].IMUX_IMUX[0]CELL[20].IMUX_IMUX[20]CELL[26].IMUX_IMUX[0]CELL[30].IMUX_IMUX[0]
FINEENABLEinCELL[18].IMUX_IMUX[1]CELL[21].IMUX_IMUX[29]CELL[27].IMUX_IMUX[1]CELL[31].IMUX_IMUX[8]
FINEINCinCELL[18].IMUX_IMUX[32]CELL[21].IMUX_IMUX[13]CELL[26].IMUX_IMUX[47]CELL[30].IMUX_IMUX[43]
COARSEENABLEinCELL[18].IMUX_IMUX[41]CELL[21].IMUX_IMUX[14]CELL[27].IMUX_IMUX[41]CELL[31].IMUX_IMUX[32]
COARSEINCinCELL[18].IMUX_IMUX[9]CELL[21].IMUX_IMUX[45]CELL[27].IMUX_IMUX[9]CELL[31].IMUX_IMUX[16]
COUNTERLOADENinCELL[17].IMUX_IMUX[47]CELL[20].IMUX_IMUX[39]CELL[26].IMUX_IMUX[31]CELL[30].IMUX_IMUX[27]
COUNTERLOADVAL[0]inCELL[17].IMUX_IMUX[13]CELL[20].IMUX_IMUX[44]CELL[26].IMUX_IMUX[20]CELL[30].IMUX_IMUX[1]
COUNTERLOADVAL[1]inCELL[17].IMUX_IMUX[29]CELL[20].IMUX_IMUX[21]CELL[26].IMUX_IMUX[44]CELL[30].IMUX_IMUX[9]
COUNTERLOADVAL[2]inCELL[17].IMUX_IMUX[45]CELL[20].IMUX_IMUX[29]CELL[26].IMUX_IMUX[13]CELL[30].IMUX_IMUX[17]
COUNTERLOADVAL[3]inCELL[17].IMUX_IMUX[14]CELL[20].IMUX_IMUX[45]CELL[26].IMUX_IMUX[29]CELL[30].IMUX_IMUX[41]
COUNTERLOADVAL[4]inCELL[17].IMUX_IMUX[30]CELL[20].IMUX_IMUX[14]CELL[26].IMUX_IMUX[45]CELL[30].IMUX_IMUX[2]
COUNTERLOADVAL[5]inCELL[17].IMUX_IMUX[46]CELL[20].IMUX_IMUX[30]CELL[26].IMUX_IMUX[14]CELL[30].IMUX_IMUX[18]
COUNTERLOADVAL[6]inCELL[17].IMUX_IMUX[15]CELL[20].IMUX_IMUX[46]CELL[26].IMUX_IMUX[30]CELL[30].IMUX_IMUX[34]
COUNTERLOADVAL[7]inCELL[17].IMUX_IMUX[23]CELL[20].IMUX_IMUX[15]CELL[26].IMUX_IMUX[46]CELL[30].IMUX_IMUX[3]
COUNTERLOADVAL[8]inCELL[17].IMUX_IMUX[25]CELL[21].IMUX_IMUX[25]CELL[27].IMUX_IMUX[17]CELL[29].IMUX_IMUX[37]
COUNTERREADENinCELL[17].IMUX_IMUX[31]CELL[20].IMUX_IMUX[23]CELL[26].IMUX_IMUX[15]CELL[30].IMUX_IMUX[11]
TESTIN[0]inCELL[17].IMUX_IMUX[8]CELL[21].IMUX_IMUX[8]CELL[26].IMUX_IMUX[8]CELL[29].IMUX_IMUX[27]
TESTIN[1]inCELL[17].IMUX_IMUX[24]CELL[21].IMUX_IMUX[24]CELL[26].IMUX_IMUX[24]CELL[29].IMUX_IMUX[43]
TESTIN[2]inCELL[17].IMUX_IMUX[32]CELL[21].IMUX_IMUX[32]CELL[26].IMUX_IMUX[32]CELL[29].IMUX_IMUX[4]
TESTIN[3]inCELL[17].IMUX_IMUX[1]CELL[21].IMUX_IMUX[1]CELL[26].IMUX_IMUX[1]CELL[29].IMUX_IMUX[20]
TESTIN[4]inCELL[17].IMUX_IMUX[17]CELL[21].IMUX_IMUX[9]CELL[26].IMUX_IMUX[9]CELL[29].IMUX_IMUX[44]
TESTIN[5]inCELL[17].IMUX_IMUX[33]CELL[21].IMUX_IMUX[17]CELL[26].IMUX_IMUX[17]CELL[29].IMUX_IMUX[13]
TESTIN[6]inCELL[17].IMUX_IMUX[41]CELL[21].IMUX_IMUX[41]CELL[26].IMUX_IMUX[41]CELL[29].IMUX_IMUX[29]
TESTIN[7]inCELL[17].IMUX_IMUX[2]CELL[21].IMUX_IMUX[2]CELL[26].IMUX_IMUX[2]CELL[29].IMUX_IMUX[45]
TESTIN[8]inCELL[17].IMUX_IMUX[18]CELL[21].IMUX_IMUX[18]CELL[26].IMUX_IMUX[18]CELL[29].IMUX_IMUX[14]
TESTIN[9]inCELL[17].IMUX_IMUX[34]CELL[21].IMUX_IMUX[34]CELL[26].IMUX_IMUX[34]CELL[29].IMUX_IMUX[30]
TESTIN[10]inCELL[17].IMUX_IMUX[3]CELL[21].IMUX_IMUX[3]CELL[26].IMUX_IMUX[3]CELL[29].IMUX_IMUX[46]
TESTIN[11]inCELL[17].IMUX_IMUX[27]CELL[21].IMUX_IMUX[11]CELL[26].IMUX_IMUX[11]CELL[29].IMUX_IMUX[15]
TESTIN[12]inCELL[17].IMUX_IMUX[43]CELL[21].IMUX_IMUX[27]CELL[26].IMUX_IMUX[27]CELL[29].IMUX_IMUX[23]
TESTIN[13]inCELL[17].IMUX_IMUX[4]CELL[21].IMUX_IMUX[43]CELL[27].IMUX_IMUX[8]CELL[30].IMUX_IMUX[8]
TESTIN[14]inCELL[18].IMUX_IMUX[8]CELL[21].IMUX_IMUX[4]CELL[27].IMUX_IMUX[24]CELL[30].IMUX_IMUX[24]
TESTIN[15]inCELL[18].IMUX_IMUX[24]CELL[21].IMUX_IMUX[20]CELL[27].IMUX_IMUX[32]CELL[30].IMUX_IMUX[32]
SCANCLKinCELL[17].IMUX_CLK[1]CELL[21].IMUX_CLK[1]CELL[27].IMUX_CLK[1]CELL[30].IMUX_CLK[1]
SCANENBinCELL[17].IMUX_IMUX[44]CELL[20].IMUX_IMUX[28]CELL[26].IMUX_IMUX[4]CELL[29].IMUX_IMUX[47]
SCANMODEBinCELL[17].IMUX_IMUX[16]CELL[21].IMUX_IMUX[16]CELL[27].IMUX_IMUX[16]CELL[29].IMUX_IMUX[35]
SCANINinCELL[17].IMUX_IMUX[20]CELL[21].IMUX_IMUX[44]CELL[26].IMUX_IMUX[43]CELL[29].IMUX_IMUX[31]
OCLKoutCELL[7].PHASER_OCLKCELL[19].PHASER_OCLKCELL[31].PHASER_OCLKCELL[43].PHASER_OCLK
OCLKDELAYEDoutIO[8].PHASER_OCLK90IO[20].PHASER_OCLK90IO[32].PHASER_OCLK90IO[44].PHASER_OCLK90
OCLKDIVoutCELL[7].PHASER_OCLKDIVCELL[19].PHASER_OCLKDIVCELL[31].PHASER_OCLKDIVCELL[43].PHASER_OCLKDIV
RDENABLEoutCELL[7].PHASER_ORDENCELL[19].PHASER_ORDENCELL[31].PHASER_ORDENCELL[43].PHASER_ORDEN
OSERDESRSToutCELL[16].OUT_BEL[14]CELL[21].OUT_BEL[6]CELL[27].OUT_BEL[10]CELL[30].OUT_BEL[16]
CTSBUS[0]outCELL[8].OUT_BEL[14]CELL[20].OUT_BEL[14]CELL[32].OUT_BEL[14]CELL[44].OUT_BEL[14]
CTSBUS[1]outCELL[8].OUT_BEL[23]CELL[20].OUT_BEL[23]CELL[32].OUT_BEL[23]CELL[44].OUT_BEL[23]
DQSBUS[0]outCELL[8].OUT_BEL[0]CELL[20].OUT_BEL[0]CELL[32].OUT_BEL[0]CELL[44].OUT_BEL[0]
DQSBUS[1]outCELL[8].OUT_BEL[5]CELL[20].OUT_BEL[5]CELL[32].OUT_BEL[5]CELL[44].OUT_BEL[5]
DTSBUS[0]outCELL[7].OUT_BEL[14]CELL[19].OUT_BEL[14]CELL[31].OUT_BEL[14]CELL[43].OUT_BEL[14]
DTSBUS[1]outCELL[7].OUT_BEL[23]CELL[19].OUT_BEL[23]CELL[31].OUT_BEL[23]CELL[43].OUT_BEL[23]
FINEOVERFLOWoutCELL[17].OUT_BEL[23]CELL[22].OUT_BEL[18]CELL[26].OUT_BEL[2]CELL[31].OUT_BEL[18]
COARSEOVERFLOWoutCELL[16].OUT_BEL[2]CELL[21].OUT_BEL[14]CELL[25].OUT_BEL[15]CELL[30].OUT_BEL[14]
COUNTERREADVAL[0]outCELL[16].OUT_BEL[3]CELL[20].OUT_BEL[6]CELL[25].OUT_BEL[3]CELL[29].OUT_BEL[3]
COUNTERREADVAL[1]outCELL[16].OUT_BEL[21]CELL[20].OUT_BEL[16]CELL[25].OUT_BEL[21]CELL[29].OUT_BEL[21]
COUNTERREADVAL[2]outCELL[16].OUT_BEL[7]CELL[20].OUT_BEL[15]CELL[25].OUT_BEL[7]CELL[29].OUT_BEL[7]
COUNTERREADVAL[3]outCELL[16].OUT_BEL[17]CELL[20].OUT_BEL[17]CELL[25].OUT_BEL[17]CELL[29].OUT_BEL[17]
COUNTERREADVAL[4]outCELL[17].OUT_BEL[10]CELL[21].OUT_BEL[2]CELL[26].OUT_BEL[15]CELL[30].OUT_BEL[2]
COUNTERREADVAL[5]outCELL[17].OUT_BEL[6]CELL[21].OUT_BEL[15]CELL[26].OUT_BEL[3]CELL[30].OUT_BEL[15]
COUNTERREADVAL[6]outCELL[17].OUT_BEL[16]CELL[21].OUT_BEL[3]CELL[26].OUT_BEL[21]CELL[30].OUT_BEL[3]
COUNTERREADVAL[7]outCELL[17].OUT_BEL[14]CELL[21].OUT_BEL[21]CELL[26].OUT_BEL[7]CELL[30].OUT_BEL[21]
COUNTERREADVAL[8]outCELL[16].OUT_BEL[16]CELL[21].OUT_BEL[10]CELL[27].OUT_BEL[23]CELL[30].OUT_BEL[6]
TESTOUT[0]outCELL[16].OUT_BEL[18]CELL[20].OUT_BEL[1]CELL[26].OUT_BEL[6]CELL[29].OUT_BEL[14]
TESTOUT[1]outCELL[16].OUT_BEL[23]CELL[20].OUT_BEL[9]CELL[26].OUT_BEL[16]CELL[29].OUT_BEL[2]
TESTOUT[2]outCELL[16].OUT_BEL[10]CELL[21].OUT_BEL[18]CELL[26].OUT_BEL[14]CELL[29].OUT_BEL[15]
TESTOUT[3]outCELL[16].OUT_BEL[6]CELL[21].OUT_BEL[23]CELL[27].OUT_BEL[18]CELL[30].OUT_BEL[10]
SCANOUToutCELL[17].OUT_BEL[18]CELL[21].OUT_BEL[16]CELL[25].OUT_BEL[2]CELL[31].OUT_BEL[4]
virtex7 CMT bel PHASER_OUT attribute bits
AttributePHASER_OUT[0]PHASER_OUT[1]PHASER_OUT[2]PHASER_OUT[3]
CLKOUT_DIV[enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV][enum: PHASER_CLKOUT_DIV]
CLKOUT_DIV_ST bit 0MAIN[18][28][9]MAIN[21][28][41]MAIN[28][28][9]MAIN[31][28][41]
CLKOUT_DIV_ST bit 1MAIN[18][29][9]MAIN[21][29][41]MAIN[28][29][9]MAIN[31][29][41]
CLKOUT_DIV_ST bit 2MAIN[18][28][10]MAIN[21][28][42]MAIN[28][28][10]MAIN[31][28][42]
CLKOUT_DIV_ST bit 3MAIN[18][29][10]MAIN[21][29][42]MAIN[28][29][10]MAIN[31][29][42]
COARSE_BYPASSMAIN[17][29][23]MAIN[20][29][55]MAIN[27][29][23]MAIN[30][29][55]
COARSE_DELAY bit 0MAIN[18][29][2]MAIN[21][29][34]MAIN[28][29][2]MAIN[31][29][34]
COARSE_DELAY bit 1MAIN[18][28][3]MAIN[21][28][35]MAIN[28][28][3]MAIN[31][28][35]
COARSE_DELAY bit 2MAIN[18][29][3]MAIN[21][29][35]MAIN[28][29][3]MAIN[31][29][35]
COARSE_DELAY bit 3MAIN[18][28][4]MAIN[21][28][36]MAIN[28][28][4]MAIN[31][28][36]
COARSE_DELAY bit 4MAIN[18][29][4]MAIN[21][29][36]MAIN[28][29][4]MAIN[31][29][36]
COARSE_DELAY bit 5MAIN[18][28][5]MAIN[21][28][37]MAIN[28][28][5]MAIN[31][28][37]
CTL_MODE[enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE][enum: PHASER_CTL_MODE]
DATA_CTL_NMAIN[17][28][29]MAIN[20][28][61]MAIN[27][28][29]MAIN[30][28][61]
DATA_RD_CYCLESMAIN[17][29][21]MAIN[20][29][53]MAIN[27][29][21]MAIN[30][29][53]
EN_OSERDES_RSTMAIN[17][28][23]MAIN[20][28][55]MAIN[27][28][23]MAIN[30][28][55]
EN_TEST_RINGMAIN[17][29][28]MAIN[20][29][60]MAIN[27][29][28]MAIN[30][29][60]
FINE_DELAY bit 0MAIN[18][29][5]MAIN[21][29][37]MAIN[28][29][5]MAIN[31][29][37]
FINE_DELAY bit 1MAIN[18][28][6]MAIN[21][28][38]MAIN[28][28][6]MAIN[31][28][38]
FINE_DELAY bit 2MAIN[18][29][6]MAIN[21][29][38]MAIN[28][29][6]MAIN[31][29][38]
FINE_DELAY bit 3MAIN[18][28][7]MAIN[21][28][39]MAIN[28][28][7]MAIN[31][28][39]
FINE_DELAY bit 4MAIN[18][29][7]MAIN[21][29][39]MAIN[28][29][7]MAIN[31][29][39]
FINE_DELAY bit 5MAIN[18][28][8]MAIN[21][28][40]MAIN[28][28][8]MAIN[31][28][40]
OCLKDELAY_INVMAIN[17][28][22]MAIN[20][28][54]MAIN[27][28][22]MAIN[30][28][54]
OCLK_DELAY bit 0MAIN[17][29][25]MAIN[20][29][57]MAIN[27][29][25]MAIN[30][29][57]
OCLK_DELAY bit 1MAIN[17][28][26]MAIN[20][28][58]MAIN[27][28][26]MAIN[30][28][58]
OCLK_DELAY bit 2MAIN[17][29][26]MAIN[20][29][58]MAIN[27][29][26]MAIN[30][29][58]
OCLK_DELAY bit 3MAIN[17][28][27]MAIN[20][28][59]MAIN[27][28][27]MAIN[30][28][59]
OCLK_DELAY bit 4MAIN[17][29][27]MAIN[20][29][59]MAIN[27][29][27]MAIN[30][29][59]
OCLK_DELAY bit 5MAIN[17][28][28]MAIN[20][28][60]MAIN[27][28][28]MAIN[30][28][60]
OUTPUT_CLK_SRC[enum: PHASER_OUT_OUTPUT_CLK_SRC][enum: PHASER_OUT_OUTPUT_CLK_SRC][enum: PHASER_OUT_OUTPUT_CLK_SRC][enum: PHASER_OUT_OUTPUT_CLK_SRC]
PHASER_OUT_ENMAIN[17][29][22]MAIN[20][29][54]MAIN[27][29][22]MAIN[30][29][54]
STG1_BYPASS[enum: PHASER_OUT_STG1_BYPASS][enum: PHASER_OUT_STG1_BYPASS][enum: PHASER_OUT_STG1_BYPASS][enum: PHASER_OUT_STG1_BYPASS]
SYNC_IN_DIV_RSTMAIN[18][29][8]MAIN[21][29][40]MAIN[28][29][8]MAIN[31][29][40]
TEST_OPT bit 0MAIN[17][28][16]MAIN[20][28][48]MAIN[27][28][16]MAIN[30][28][48]
TEST_OPT bit 1MAIN[17][29][16]MAIN[20][29][48]MAIN[27][29][16]MAIN[30][29][48]
TEST_OPT bit 2MAIN[17][28][17]MAIN[20][28][49]MAIN[27][28][17]MAIN[30][28][49]
TEST_OPT bit 3MAIN[17][29][17]MAIN[20][29][49]MAIN[27][29][17]MAIN[30][29][49]
TEST_OPT bit 4MAIN[17][28][18]MAIN[20][28][50]MAIN[27][28][18]MAIN[30][28][50]
TEST_OPT bit 5MAIN[17][29][18]MAIN[20][29][50]MAIN[27][29][18]MAIN[30][29][50]
TEST_OPT bit 6MAIN[17][28][19]MAIN[20][28][51]MAIN[27][28][19]MAIN[30][28][51]
TEST_OPT bit 7MAIN[17][29][19]MAIN[20][29][51]MAIN[27][29][19]MAIN[30][29][51]
TEST_OPT bit 8MAIN[17][28][20]MAIN[20][28][52]MAIN[27][28][20]MAIN[30][28][52]
TEST_OPT bit 9MAIN[17][29][20]MAIN[20][29][52]MAIN[27][29][20]MAIN[30][29][52]
TEST_OPT bit 10MAIN[17][28][21]MAIN[20][28][53]MAIN[27][28][21]MAIN[30][28][53]
virtex7 CMT enum PHASER_CLKOUT_DIV
PHASER_OUT[0].CLKOUT_DIVMAIN[18][29][12]MAIN[18][28][12]MAIN[18][29][11]MAIN[18][28][11]MAIN[17][29][31]MAIN[17][28][31]MAIN[17][29][30]MAIN[17][28][30]
PHASER_OUT[1].CLKOUT_DIVMAIN[21][29][44]MAIN[21][28][44]MAIN[21][29][43]MAIN[21][28][43]MAIN[20][29][63]MAIN[20][28][63]MAIN[20][29][62]MAIN[20][28][62]
PHASER_OUT[2].CLKOUT_DIVMAIN[28][29][12]MAIN[28][28][12]MAIN[28][29][11]MAIN[28][28][11]MAIN[27][29][31]MAIN[27][28][31]MAIN[27][29][30]MAIN[27][28][30]
PHASER_OUT[3].CLKOUT_DIVMAIN[31][29][44]MAIN[31][28][44]MAIN[31][29][43]MAIN[31][28][43]MAIN[30][29][63]MAIN[30][28][63]MAIN[30][29][62]MAIN[30][28][62]
NONE00000000
_200010000
_300010001
_400100010
_500100011
_600110100
_700110101
_801000110
_901000111
_1001011000
_1101011001
_1201101010
_1301101011
_1401111100
_1501111101
_1610001110
virtex7 CMT enum PHASER_CTL_MODE
PHASER_OUT[0].CTL_MODEMAIN[17][29][29]
PHASER_OUT[1].CTL_MODEMAIN[20][29][61]
PHASER_OUT[2].CTL_MODEMAIN[27][29][29]
PHASER_OUT[3].CTL_MODEMAIN[30][29][61]
SOFT0
HARD1
virtex7 CMT enum PHASER_OUT_OUTPUT_CLK_SRC
PHASER_OUT[0].OUTPUT_CLK_SRCMAIN[17][29][24]MAIN[17][28][24]
PHASER_OUT[1].OUTPUT_CLK_SRCMAIN[20][29][56]MAIN[20][28][56]
PHASER_OUT[2].OUTPUT_CLK_SRCMAIN[27][29][24]MAIN[27][28][24]
PHASER_OUT[3].OUTPUT_CLK_SRCMAIN[30][29][56]MAIN[30][28][56]
PHASE_REF00
FREQ_REF10
DELAYED_REF01
DELAYED_PHASE_REF11
virtex7 CMT enum PHASER_OUT_STG1_BYPASS
PHASER_OUT[0].STG1_BYPASSMAIN[17][28][25]
PHASER_OUT[1].STG1_BYPASSMAIN[20][28][57]
PHASER_OUT[2].STG1_BYPASSMAIN[27][28][25]
PHASER_OUT[3].STG1_BYPASSMAIN[30][28][57]
PHASE_REF0
FREQ_REF1

Bels PHASER_REF

virtex7 CMT bel PHASER_REF pins
PinDirectionPHASER_REF
CLKINinCELL[25].IMUX_PHASER_REFMUX[0]
PWRDWNinCELL[25].IMUX_IMUX[45] invert by MAIN[26][28][24]
RSTinCELL[25].IMUX_IMUX[15] invert by MAIN[26][28][16]
TESTIN[0]inCELL[25].IMUX_IMUX[8]
TESTIN[1]inCELL[25].IMUX_IMUX[32]
TESTIN[2]inCELL[25].IMUX_IMUX[1]
TESTIN[3]inCELL[25].IMUX_IMUX[41]
TESTIN[4]inCELL[25].IMUX_IMUX[18]
TESTIN[5]inCELL[25].IMUX_IMUX[3]
TESTIN[6]inCELL[25].IMUX_IMUX[4]
TESTIN[7]inCELL[25].IMUX_IMUX[13]
CLKOUToutCELL[25].OUT_PHASER_REF_CLKOUT
TMUXOUToutCELL[25].OUT_PHASER_REF_TMUXOUT
LOCKEDoutCELL[25].OUT_BEL[14]
TESTOUT[0]outCELL[26].OUT_BEL[18]
TESTOUT[1]outCELL[26].OUT_BEL[23]
TESTOUT[2]outCELL[26].OUT_BEL[10]
TESTOUT[3]outCELL[25].OUT_BEL[18]
TESTOUT[4]outCELL[25].OUT_BEL[23]
TESTOUT[5]outCELL[25].OUT_BEL[10]
TESTOUT[6]outCELL[25].OUT_BEL[6]
TESTOUT[7]outCELL[25].OUT_BEL[16]
virtex7 CMT bel PHASER_REF attribute bits
AttributePHASER_REF
PHASER_REF_ENMAIN[26][29][24]
SEL_SLIPDMAIN[26][28][3]
SUP_SEL_AREGMAIN[26][29][7]
AVDD_COMP_SET bit 0MAIN[26][29][62]
AVDD_COMP_SET bit 1MAIN[26][28][63]
AVDD_COMP_SET bit 2MAIN[26][29][63]
AVDD_VBG_PD bit 0MAIN[26][28][61]
AVDD_VBG_PD bit 1MAIN[26][29][61]
AVDD_VBG_PD bit 2MAIN[26][28][62]
AVDD_VBG_SEL bit 0MAIN[26][28][59]
AVDD_VBG_SEL bit 1MAIN[26][29][59]
AVDD_VBG_SEL bit 2MAIN[26][28][60]
AVDD_VBG_SEL bit 3MAIN[26][29][60]
CP bit 0MAIN[26][28][57]
CP bit 1MAIN[26][29][57]
CP bit 2MAIN[26][28][58]
CP bit 3MAIN[26][29][58]
CP_BIAS_TRIP_SET bit 0MAIN[26][29][1]
CP_RES bit 0MAIN[26][28][56]
CP_RES bit 1MAIN[26][29][56]
LF_NEN bit 0MAIN[26][28][31]
LF_NEN bit 1MAIN[26][29][31]
LF_PEN bit 0MAIN[26][28][30]
LF_PEN bit 1MAIN[26][29][30]
MAN_LF bit 0MAIN[26][29][16]
MAN_LF bit 1MAIN[26][28][17]
MAN_LF bit 2MAIN[26][29][17]
PFD bit 0MAIN[26][28][18]
PFD bit 1MAIN[26][29][18]
PFD bit 2MAIN[26][28][19]
PFD bit 3MAIN[26][29][19]
PFD bit 4MAIN[26][28][20]
PFD bit 5MAIN[26][29][20]
PFD bit 6MAIN[26][28][21]
PHASER_REF_MISC bit 0MAIN[26][28][0]
PHASER_REF_MISC bit 1MAIN[26][29][0]
PHASER_REF_MISC bit 2MAIN[26][28][1]
SEL_LF_HIGH bit 0MAIN[26][28][6]
SEL_LF_HIGH bit 1MAIN[26][29][6]
SEL_LF_HIGH bit 2MAIN[26][28][7]
TMUX_MUX_SEL bit 0MAIN[26][28][2]
TMUX_MUX_SEL bit 1MAIN[26][29][2]
CONTROL_0 bit 0MAIN[26][28][48]
CONTROL_0 bit 1MAIN[26][29][48]
CONTROL_0 bit 2MAIN[26][28][49]
CONTROL_0 bit 3MAIN[26][29][49]
CONTROL_0 bit 4MAIN[26][28][50]
CONTROL_0 bit 5MAIN[26][29][50]
CONTROL_0 bit 6MAIN[26][28][51]
CONTROL_0 bit 7MAIN[26][29][51]
CONTROL_0 bit 8MAIN[26][28][52]
CONTROL_0 bit 9MAIN[26][29][52]
CONTROL_0 bit 10MAIN[26][28][53]
CONTROL_0 bit 11MAIN[26][29][53]
CONTROL_0 bit 12MAIN[26][28][54]
CONTROL_0 bit 13MAIN[26][29][54]
CONTROL_0 bit 14MAIN[26][28][55]
CONTROL_0 bit 15MAIN[26][29][55]
CONTROL_1 bit 0MAIN[26][28][40]
CONTROL_1 bit 1MAIN[26][29][40]
CONTROL_1 bit 2MAIN[26][28][41]
CONTROL_1 bit 3MAIN[26][29][41]
CONTROL_1 bit 4MAIN[26][28][42]
CONTROL_1 bit 5MAIN[26][29][42]
CONTROL_1 bit 6MAIN[26][28][43]
CONTROL_1 bit 7MAIN[26][29][43]
CONTROL_1 bit 8MAIN[26][28][44]
CONTROL_1 bit 9MAIN[26][29][44]
CONTROL_1 bit 10MAIN[26][28][45]
CONTROL_1 bit 11MAIN[26][29][45]
CONTROL_1 bit 12MAIN[26][28][46]
CONTROL_1 bit 13MAIN[26][29][46]
CONTROL_1 bit 14MAIN[26][28][47]
CONTROL_1 bit 15MAIN[26][29][47]
CONTROL_2 bit 0MAIN[26][28][32]
CONTROL_2 bit 1MAIN[26][29][32]
CONTROL_2 bit 2MAIN[26][28][33]
CONTROL_2 bit 3MAIN[26][29][33]
CONTROL_2 bit 4MAIN[26][28][34]
CONTROL_2 bit 5MAIN[26][29][34]
CONTROL_2 bit 6MAIN[26][28][35]
CONTROL_2 bit 7MAIN[26][29][35]
CONTROL_2 bit 8MAIN[26][28][36]
CONTROL_2 bit 9MAIN[26][29][36]
CONTROL_2 bit 10MAIN[26][28][37]
CONTROL_2 bit 11MAIN[26][29][37]
CONTROL_2 bit 12MAIN[26][28][38]
CONTROL_2 bit 13MAIN[26][29][38]
CONTROL_2 bit 14MAIN[26][28][39]
CONTROL_2 bit 15MAIN[26][29][39]
CONTROL_3 bit 0MAIN[26][28][8]
CONTROL_3 bit 1MAIN[26][29][8]
CONTROL_3 bit 2MAIN[26][28][9]
CONTROL_3 bit 3MAIN[26][29][9]
CONTROL_3 bit 4MAIN[26][28][10]
CONTROL_3 bit 5MAIN[26][29][10]
CONTROL_3 bit 6MAIN[26][28][11]
CONTROL_3 bit 7MAIN[26][29][11]
CONTROL_3 bit 8MAIN[26][28][12]
CONTROL_3 bit 9MAIN[26][29][12]
CONTROL_3 bit 10MAIN[26][28][13]
CONTROL_3 bit 11MAIN[26][29][13]
CONTROL_3 bit 12MAIN[26][28][14]
CONTROL_3 bit 13MAIN[26][29][14]
CONTROL_3 bit 14MAIN[26][28][15]
CONTROL_3 bit 15MAIN[26][29][15]
CONTROL_4 bit 0MAIN[27][28][0]
CONTROL_4 bit 1MAIN[27][29][0]
CONTROL_4 bit 2MAIN[27][28][1]
CONTROL_4 bit 3MAIN[27][29][1]
CONTROL_4 bit 4MAIN[27][28][2]
CONTROL_4 bit 5MAIN[27][29][2]
CONTROL_4 bit 6MAIN[27][28][3]
CONTROL_4 bit 7MAIN[27][29][3]
CONTROL_4 bit 8MAIN[27][28][4]
CONTROL_4 bit 9MAIN[27][29][4]
CONTROL_4 bit 10MAIN[27][28][5]
CONTROL_4 bit 11MAIN[27][29][5]
CONTROL_4 bit 12MAIN[27][28][6]
CONTROL_4 bit 13MAIN[27][29][6]
CONTROL_4 bit 14MAIN[27][28][7]
CONTROL_4 bit 15MAIN[27][29][7]
CONTROL_5 bit 0MAIN[27][28][8]
CONTROL_5 bit 1MAIN[27][29][8]
CONTROL_5 bit 2MAIN[27][28][9]
CONTROL_5 bit 3MAIN[27][29][9]
CONTROL_5 bit 4MAIN[27][28][10]
CONTROL_5 bit 5MAIN[27][29][10]
CONTROL_5 bit 6MAIN[27][28][11]
CONTROL_5 bit 7MAIN[27][29][11]
CONTROL_5 bit 8MAIN[27][28][12]
CONTROL_5 bit 9MAIN[27][29][12]
CONTROL_5 bit 10MAIN[27][28][13]
CONTROL_5 bit 11MAIN[27][29][13]
CONTROL_5 bit 12MAIN[27][28][14]
CONTROL_5 bit 13MAIN[27][29][14]
CONTROL_5 bit 14MAIN[27][28][15]
CONTROL_5 bit 15MAIN[27][29][15]
LOCK_CNT bit 0MAIN[26][28][25]
LOCK_CNT bit 1MAIN[26][29][25]
LOCK_CNT bit 2MAIN[26][28][26]
LOCK_CNT bit 3MAIN[26][29][26]
LOCK_CNT bit 4MAIN[26][28][27]
LOCK_CNT bit 5MAIN[26][29][27]
LOCK_CNT bit 6MAIN[26][28][28]
LOCK_CNT bit 7MAIN[26][29][28]
LOCK_CNT bit 8MAIN[26][28][29]
LOCK_CNT bit 9MAIN[26][29][29]
LOCK_FB_DLY bit 0MAIN[26][29][21]
LOCK_FB_DLY bit 1MAIN[26][28][22]
LOCK_FB_DLY bit 2MAIN[26][29][22]
LOCK_FB_DLY bit 3MAIN[26][28][23]
LOCK_FB_DLY bit 4MAIN[26][29][23]
LOCK_REF_DLY bit 0MAIN[26][29][3]
LOCK_REF_DLY bit 1MAIN[26][28][4]
LOCK_REF_DLY bit 2MAIN[26][29][4]
LOCK_REF_DLY bit 3MAIN[26][28][5]
LOCK_REF_DLY bit 4MAIN[26][29][5]

Bels PHY_CONTROL

virtex7 CMT bel PHY_CONTROL pins
PinDirectionPHY_CONTROL
MEMREFCLKinCELL[25].IMUX_PHASER_REFMUX[1]
SYNCINinCELL[25].IMUX_PHASER_REFMUX[2]
PHYCTLMSTREMPTYinCELL[25].CMT_SYNC_BB
PHYCLKinCELL[35].IMUX_CLK[0]
RESETinCELL[36].IMUX_IMUX[11]
PLLLOCKinCELL[34].IMUX_IMUX[43]
REFDLLLOCKinCELL[35].IMUX_IMUX[4]
READCALIBENABLEinCELL[35].IMUX_IMUX[29]
WRITECALIBENABLEinCELL[35].IMUX_IMUX[22]
PHYCTLWD[0]inCELL[34].IMUX_IMUX[4]
PHYCTLWD[1]inCELL[34].IMUX_IMUX[20]
PHYCTLWD[2]inCELL[34].IMUX_IMUX[44]
PHYCTLWD[3]inCELL[34].IMUX_IMUX[13]
PHYCTLWD[4]inCELL[34].IMUX_IMUX[45]
PHYCTLWD[5]inCELL[34].IMUX_IMUX[14]
PHYCTLWD[6]inCELL[34].IMUX_IMUX[30]
PHYCTLWD[7]inCELL[34].IMUX_IMUX[46]
PHYCTLWD[8]inCELL[34].IMUX_IMUX[15]
PHYCTLWD[9]inCELL[34].IMUX_IMUX[31]
PHYCTLWD[10]inCELL[34].IMUX_IMUX[47]
PHYCTLWD[11]inCELL[35].IMUX_IMUX[20]
PHYCTLWD[12]inCELL[35].IMUX_IMUX[44]
PHYCTLWD[13]inCELL[35].IMUX_IMUX[13]
PHYCTLWD[14]inCELL[35].IMUX_IMUX[45]
PHYCTLWD[15]inCELL[35].IMUX_IMUX[14]
PHYCTLWD[16]inCELL[35].IMUX_IMUX[30]
PHYCTLWD[17]inCELL[35].IMUX_IMUX[46]
PHYCTLWD[18]inCELL[35].IMUX_IMUX[15]
PHYCTLWD[19]inCELL[35].IMUX_IMUX[31]
PHYCTLWD[20]inCELL[35].IMUX_IMUX[47]
PHYCTLWD[21]inCELL[36].IMUX_IMUX[43]
PHYCTLWD[22]inCELL[36].IMUX_IMUX[4]
PHYCTLWD[23]inCELL[36].IMUX_IMUX[20]
PHYCTLWD[24]inCELL[36].IMUX_IMUX[44]
PHYCTLWD[25]inCELL[36].IMUX_IMUX[13]
PHYCTLWD[26]inCELL[36].IMUX_IMUX[45]
PHYCTLWD[27]inCELL[36].IMUX_IMUX[14]
PHYCTLWD[28]inCELL[36].IMUX_IMUX[30]
PHYCTLWD[29]inCELL[36].IMUX_IMUX[46]
PHYCTLWD[30]inCELL[36].IMUX_IMUX[15]
PHYCTLWD[31]inCELL[36].IMUX_IMUX[31]
PHYCTLWRENABLEinCELL[36].IMUX_IMUX[47]
SCANENABLENinCELL[35].IMUX_IMUX[9]
TESTSELECT[0]inCELL[35].IMUX_IMUX[41]
TESTSELECT[1]inCELL[35].IMUX_IMUX[2]
TESTSELECT[2]inCELL[35].IMUX_IMUX[18]
TESTINPUT[0]inCELL[34].IMUX_IMUX[8]
TESTINPUT[1]inCELL[34].IMUX_IMUX[24]
TESTINPUT[2]inCELL[34].IMUX_IMUX[32]
TESTINPUT[3]inCELL[34].IMUX_IMUX[1]
TESTINPUT[4]inCELL[34].IMUX_IMUX[9]
TESTINPUT[5]inCELL[34].IMUX_IMUX[41]
TESTINPUT[6]inCELL[34].IMUX_IMUX[2]
TESTINPUT[7]inCELL[34].IMUX_IMUX[18]
TESTINPUT[8]inCELL[34].IMUX_IMUX[34]
TESTINPUT[9]inCELL[34].IMUX_IMUX[3]
TESTINPUT[10]inCELL[34].IMUX_IMUX[11]
TESTINPUT[11]inCELL[34].IMUX_IMUX[27]
TESTINPUT[12]inCELL[35].IMUX_IMUX[3]
TESTINPUT[13]inCELL[35].IMUX_IMUX[11]
TESTINPUT[14]inCELL[35].IMUX_IMUX[27]
TESTINPUT[15]inCELL[35].IMUX_IMUX[43]
PHYCTLEMPTYoutCELL[25].OUT_PHY_PHYCTLEMPTY
AUXOUTPUT[0]outCELL[34].OUT_BEL[3]
AUXOUTPUT[1]outCELL[34].OUT_BEL[21]
AUXOUTPUT[2]outCELL[35].OUT_BEL[17]
AUXOUTPUT[3]outCELL[36].OUT_BEL[17]
PHYCTLALMOSTFULLoutCELL[34].OUT_BEL[7]
PHYCTLFULLoutCELL[34].OUT_BEL[17]
PHYCTLREADYoutCELL[33].OUT_BEL[17]
TESTOUTPUT[0]outCELL[34].OUT_BEL[18]
TESTOUTPUT[1]outCELL[34].OUT_BEL[23]
TESTOUTPUT[2]outCELL[34].OUT_BEL[10]
TESTOUTPUT[3]outCELL[34].OUT_BEL[6]
TESTOUTPUT[4]outCELL[34].OUT_BEL[16]
TESTOUTPUT[5]outCELL[34].OUT_BEL[14]
TESTOUTPUT[6]outCELL[34].OUT_BEL[2]
TESTOUTPUT[7]outCELL[34].OUT_BEL[15]
TESTOUTPUT[8]outCELL[35].OUT_BEL[6]
TESTOUTPUT[9]outCELL[35].OUT_BEL[16]
TESTOUTPUT[10]outCELL[35].OUT_BEL[14]
TESTOUTPUT[11]outCELL[35].OUT_BEL[2]
TESTOUTPUT[12]outCELL[35].OUT_BEL[15]
TESTOUTPUT[13]outCELL[35].OUT_BEL[3]
TESTOUTPUT[14]outCELL[35].OUT_BEL[21]
TESTOUTPUT[15]outCELL[35].OUT_BEL[7]
virtex7 CMT bel PHY_CONTROL attribute bits
AttributePHY_CONTROL
AO_TOGGLE bit 0MAIN[34][28][54]
AO_TOGGLE bit 1MAIN[34][29][54]
AO_TOGGLE bit 2MAIN[34][28][55]
AO_TOGGLE bit 3MAIN[34][29][55]
AO_WRLVL_EN bit 0MAIN[35][29][13]
AO_WRLVL_EN bit 1MAIN[35][28][14]
AO_WRLVL_EN bit 2MAIN[35][29][14]
AO_WRLVL_EN bit 3MAIN[35][28][15]
BURST_MODEMAIN[35][28][46]
CLK_RATIO[enum: PHY_CONTROL_CLK_RATIO]
CMD_OFFSET bit 0MAIN[34][28][56]
CMD_OFFSET bit 1MAIN[34][29][56]
CMD_OFFSET bit 2MAIN[34][28][57]
CMD_OFFSET bit 3MAIN[34][29][57]
CMD_OFFSET bit 4MAIN[34][28][58]
CMD_OFFSET bit 5MAIN[34][29][58]
CO_DURATION bit 0MAIN[35][28][12]
CO_DURATION bit 1MAIN[35][29][12]
CO_DURATION bit 2MAIN[35][28][13]
DATA_CTL_A_NMAIN[35][28][44]
DATA_CTL_B_NMAIN[35][29][44]
DATA_CTL_C_NMAIN[35][28][45]
DATA_CTL_D_NMAIN[35][29][45]
DISABLE_SEQ_MATCHMAIN[34][28][15]
DI_DURATION bit 0MAIN[34][29][45]
DI_DURATION bit 1MAIN[34][28][46]
DI_DURATION bit 2MAIN[34][29][46]
DO_DURATION bit 0MAIN[34][28][12]
DO_DURATION bit 1MAIN[34][29][12]
DO_DURATION bit 2MAIN[34][28][13]
EVENTS_DELAY bit 0MAIN[34][28][51]
EVENTS_DELAY bit 1MAIN[34][29][51]
EVENTS_DELAY bit 2MAIN[34][28][52]
EVENTS_DELAY bit 3MAIN[34][29][52]
EVENTS_DELAY bit 4MAIN[34][28][53]
EVENTS_DELAY bit 5MAIN[34][29][53]
FOUR_WINDOW_CLOCKS bit 0MAIN[34][28][48]
FOUR_WINDOW_CLOCKS bit 1MAIN[34][29][48]
FOUR_WINDOW_CLOCKS bit 2MAIN[34][28][49]
FOUR_WINDOW_CLOCKS bit 3MAIN[34][29][49]
FOUR_WINDOW_CLOCKS bit 4MAIN[34][28][50]
FOUR_WINDOW_CLOCKS bit 5MAIN[34][29][50]
MULTI_REGIONMAIN[34][28][14]
PHY_COUNT_ENABLEMAIN[35][29][15]
RD_CMD_OFFSET_0 bit 0MAIN[34][28][3]
RD_CMD_OFFSET_0 bit 1MAIN[34][29][3]
RD_CMD_OFFSET_0 bit 2MAIN[34][28][4]
RD_CMD_OFFSET_0 bit 3MAIN[34][29][4]
RD_CMD_OFFSET_0 bit 4MAIN[34][28][5]
RD_CMD_OFFSET_0 bit 5MAIN[34][29][5]
RD_CMD_OFFSET_1 bit 0MAIN[34][28][35]
RD_CMD_OFFSET_1 bit 1MAIN[34][29][35]
RD_CMD_OFFSET_1 bit 2MAIN[34][28][36]
RD_CMD_OFFSET_1 bit 3MAIN[34][29][36]
RD_CMD_OFFSET_1 bit 4MAIN[34][28][37]
RD_CMD_OFFSET_1 bit 5MAIN[34][29][37]
RD_CMD_OFFSET_2 bit 0MAIN[35][28][3]
RD_CMD_OFFSET_2 bit 1MAIN[35][29][3]
RD_CMD_OFFSET_2 bit 2MAIN[35][28][4]
RD_CMD_OFFSET_2 bit 3MAIN[35][29][4]
RD_CMD_OFFSET_2 bit 4MAIN[35][28][5]
RD_CMD_OFFSET_2 bit 5MAIN[35][29][5]
RD_CMD_OFFSET_3 bit 0MAIN[35][28][35]
RD_CMD_OFFSET_3 bit 1MAIN[35][29][35]
RD_CMD_OFFSET_3 bit 2MAIN[35][28][36]
RD_CMD_OFFSET_3 bit 3MAIN[35][29][36]
RD_CMD_OFFSET_3 bit 4MAIN[35][28][37]
RD_CMD_OFFSET_3 bit 5MAIN[35][29][37]
RD_DURATION_0 bit 0MAIN[34][28][0]
RD_DURATION_0 bit 1MAIN[34][29][0]
RD_DURATION_0 bit 2MAIN[34][28][1]
RD_DURATION_0 bit 3MAIN[34][29][1]
RD_DURATION_0 bit 4MAIN[34][28][2]
RD_DURATION_0 bit 5MAIN[34][29][2]
RD_DURATION_1 bit 0MAIN[34][28][32]
RD_DURATION_1 bit 1MAIN[34][29][32]
RD_DURATION_1 bit 2MAIN[34][28][33]
RD_DURATION_1 bit 3MAIN[34][29][33]
RD_DURATION_1 bit 4MAIN[34][28][34]
RD_DURATION_1 bit 5MAIN[34][29][34]
RD_DURATION_2 bit 0MAIN[35][28][0]
RD_DURATION_2 bit 1MAIN[35][29][0]
RD_DURATION_2 bit 2MAIN[35][28][1]
RD_DURATION_2 bit 3MAIN[35][29][1]
RD_DURATION_2 bit 4MAIN[35][28][2]
RD_DURATION_2 bit 5MAIN[35][29][2]
RD_DURATION_3 bit 0MAIN[35][28][32]
RD_DURATION_3 bit 1MAIN[35][29][32]
RD_DURATION_3 bit 2MAIN[35][28][33]
RD_DURATION_3 bit 3MAIN[35][29][33]
RD_DURATION_3 bit 4MAIN[35][28][34]
RD_DURATION_3 bit 5MAIN[35][29][34]
SPARE bit 0MAIN[34][29][13]
SYNC_MODEMAIN[34][29][14]
WR_CMD_OFFSET_0 bit 0MAIN[34][28][9]
WR_CMD_OFFSET_0 bit 1MAIN[34][29][9]
WR_CMD_OFFSET_0 bit 2MAIN[34][28][10]
WR_CMD_OFFSET_0 bit 3MAIN[34][29][10]
WR_CMD_OFFSET_0 bit 4MAIN[34][28][11]
WR_CMD_OFFSET_0 bit 5MAIN[34][29][11]
WR_CMD_OFFSET_1 bit 0MAIN[34][28][41]
WR_CMD_OFFSET_1 bit 1MAIN[34][29][41]
WR_CMD_OFFSET_1 bit 2MAIN[34][28][42]
WR_CMD_OFFSET_1 bit 3MAIN[34][29][42]
WR_CMD_OFFSET_1 bit 4MAIN[34][28][43]
WR_CMD_OFFSET_1 bit 5MAIN[34][29][43]
WR_CMD_OFFSET_2 bit 0MAIN[35][28][9]
WR_CMD_OFFSET_2 bit 1MAIN[35][29][9]
WR_CMD_OFFSET_2 bit 2MAIN[35][28][10]
WR_CMD_OFFSET_2 bit 3MAIN[35][29][10]
WR_CMD_OFFSET_2 bit 4MAIN[35][28][11]
WR_CMD_OFFSET_2 bit 5MAIN[35][29][11]
WR_CMD_OFFSET_3 bit 0MAIN[35][28][41]
WR_CMD_OFFSET_3 bit 1MAIN[35][29][41]
WR_CMD_OFFSET_3 bit 2MAIN[35][28][42]
WR_CMD_OFFSET_3 bit 3MAIN[35][29][42]
WR_CMD_OFFSET_3 bit 4MAIN[35][28][43]
WR_CMD_OFFSET_3 bit 5MAIN[35][29][43]
WR_DURATION_0 bit 0MAIN[34][28][6]
WR_DURATION_0 bit 1MAIN[34][29][6]
WR_DURATION_0 bit 2MAIN[34][28][7]
WR_DURATION_0 bit 3MAIN[34][29][7]
WR_DURATION_0 bit 4MAIN[34][28][8]
WR_DURATION_0 bit 5MAIN[34][29][8]
WR_DURATION_1 bit 0MAIN[34][28][38]
WR_DURATION_1 bit 1MAIN[34][29][38]
WR_DURATION_1 bit 2MAIN[34][28][39]
WR_DURATION_1 bit 3MAIN[34][29][39]
WR_DURATION_1 bit 4MAIN[34][28][40]
WR_DURATION_1 bit 5MAIN[34][29][40]
WR_DURATION_2 bit 0MAIN[35][28][6]
WR_DURATION_2 bit 1MAIN[35][29][6]
WR_DURATION_2 bit 2MAIN[35][28][7]
WR_DURATION_2 bit 3MAIN[35][29][7]
WR_DURATION_2 bit 4MAIN[35][28][8]
WR_DURATION_2 bit 5MAIN[35][29][8]
WR_DURATION_3 bit 0MAIN[35][28][38]
WR_DURATION_3 bit 1MAIN[35][29][38]
WR_DURATION_3 bit 2MAIN[35][28][39]
WR_DURATION_3 bit 3MAIN[35][29][39]
WR_DURATION_3 bit 4MAIN[35][28][40]
WR_DURATION_3 bit 5MAIN[35][29][40]
virtex7 CMT enum PHY_CONTROL_CLK_RATIO
PHY_CONTROL.CLK_RATIOMAIN[34][28][45]MAIN[34][29][44]MAIN[34][28][44]
_1000
_2001
_4010
_8100

Bels BUFHCE

virtex7 CMT bel BUFHCE pins
PinDirectionBUFMRCE[0]BUFMRCE[1]
IinCELL[25].IMUX_BUFMRCE[0]CELL[25].IMUX_BUFMRCE[1]
CEinCELL[25].IMUX_IMUX[0] invert by !HCLK[28][28]CELL[25].IMUX_IMUX[16] invert by !HCLK[29][28]
OoutCELL[25].VMRCLK[0]CELL[25].VMRCLK[1]
virtex7 CMT bel BUFHCE attribute bits
AttributeBUFMRCE[0]BUFMRCE[1]
ENABLEHCLK[28][27]HCLK[29][27]
INIT_OUT bit 0HCLK[28][29]HCLK[29][29]
CE_TYPE[enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE]
virtex7 CMT enum BUFHCE_CE_TYPE
BUFMRCE[0].CE_TYPEHCLK[28][31]
BUFMRCE[1].CE_TYPEHCLK[29][31]
SYNC0
ASYNC1

Bel wires

virtex7 CMT bel wires
WirePins
CELL[0].IMUX_CLK[0]PLL[0].DCLK
CELL[0].IMUX_IMUX[0]PLL[0].DI[0]
CELL[0].IMUX_IMUX[1]PLL[0].DI[2]
CELL[0].IMUX_IMUX[2]PLL[0].DI[4]
CELL[0].IMUX_IMUX[3]PLL[0].DI[6]
CELL[0].IMUX_IMUX[4]PLL[0].DI[8]
CELL[0].IMUX_IMUX[5]PLL[0].DI[10]
CELL[0].IMUX_IMUX[6]PLL[0].DI[12]
CELL[0].IMUX_IMUX[7]PLL[0].DI[14]
CELL[0].IMUX_IMUX[32]PLL[0].DI[1]
CELL[0].IMUX_IMUX[33]PLL[0].DI[3]
CELL[0].IMUX_IMUX[34]PLL[0].DI[5]
CELL[0].IMUX_IMUX[35]PLL[0].DI[7]
CELL[0].IMUX_IMUX[36]PLL[0].DI[9]
CELL[0].IMUX_IMUX[37]PLL[0].DI[11]
CELL[0].IMUX_IMUX[38]PLL[0].DI[13]
CELL[0].IMUX_IMUX[39]PLL[0].DI[15]
CELL[0].OUT_BEL[0]PLL[0].DO[2]
CELL[0].OUT_BEL[2]PLL[0].DO[10]
CELL[0].OUT_BEL[5]PLL[0].DO[6]
CELL[0].OUT_BEL[7]PLL[0].DO[14]
CELL[0].OUT_BEL[8]PLL[0].DO[0]
CELL[0].OUT_BEL[10]PLL[0].DO[8]
CELL[0].OUT_BEL[13]PLL[0].DO[4]
CELL[0].OUT_BEL[15]PLL[0].DO[12]
CELL[0].OUT_BEL[16]PLL[0].DO[9]
CELL[0].OUT_BEL[17]PLL[0].DO[15]
CELL[0].OUT_BEL[18]PLL[0].DO[1]
CELL[0].OUT_BEL[19]PLL[0].DO[7]
CELL[0].OUT_BEL[20]PLL[0].DO[11]
CELL[0].OUT_BEL[21]PLL[0].DO[13]
CELL[0].OUT_BEL[22]PLL[0].DO[3]
CELL[0].OUT_BEL[23]PLL[0].DO[5]
CELL[1].IMUX_CLK[0]PLL[0].PSCLK
CELL[1].IMUX_IMUX[0]PLL[0].DADDR[0]
CELL[1].IMUX_IMUX[1]PLL[0].DADDR[1]
CELL[1].IMUX_IMUX[2]PLL[0].DADDR[2]
CELL[1].IMUX_IMUX[3]PLL[0].DADDR[4]
CELL[1].IMUX_IMUX[15]PLL[0].DEN
CELL[1].IMUX_IMUX[22]PLL[0].DWE
CELL[1].IMUX_IMUX[34]PLL[0].DADDR[3]
CELL[1].IMUX_IMUX[35]PLL[0].DADDR[5]
CELL[1].IMUX_IMUX[44]PLL[0].DADDR[6]
CELL[1].IMUX_IMUX[47]PLL[0].PWRDWN
CELL[1].OUT_BEL[16]PLL[0].DRDY
CELL[1].OUT_BEL[18]PLL[0].LOCKED
CELL[1].OUT_BEL[21]PLL[0].PSDONE
CELL[2].IMUX_IMUX[0]PLL[0].CLKINSEL
CELL[2].IMUX_IMUX[1]PLL[0].PSEN
CELL[2].IMUX_IMUX[2]PLL[0].PSINCDEC
CELL[2].IMUX_IMUX[34]PLL[0].RST
CELL[2].OUT_BEL[16]PLL[0].CLKFBSTOPPED
CELL[2].OUT_BEL[18]PLL[0].CLKINSTOPPED
CELL[3].IMUX_IMUX[3]PLL[0].TESTIN[2]
CELL[3].IMUX_IMUX[15]PLL[0].TESTIN[7]
CELL[3].IMUX_IMUX[16]PLL[0].TESTIN[0]
CELL[3].IMUX_IMUX[30]PLL[0].TESTIN[6]
CELL[3].IMUX_IMUX[41]PLL[0].TESTIN[1]
CELL[3].IMUX_IMUX[43]PLL[0].TESTIN[3]
CELL[3].IMUX_IMUX[44]PLL[0].TESTIN[4]
CELL[3].IMUX_IMUX[45]PLL[0].TESTIN[5]
CELL[3].OUT_BEL[2]PLL[0].TESTOUT[3]
CELL[3].OUT_BEL[7]PLL[0].TESTOUT[6]
CELL[3].OUT_BEL[10]PLL[0].TESTOUT[2]
CELL[3].OUT_BEL[15]PLL[0].TESTOUT[4]
CELL[3].OUT_BEL[17]PLL[0].TESTOUT[7]
CELL[3].OUT_BEL[18]PLL[0].TESTOUT[0]
CELL[3].OUT_BEL[21]PLL[0].TESTOUT[5]
CELL[3].OUT_BEL[23]PLL[0].TESTOUT[1]
CELL[4].IMUX_IMUX[3]PLL[0].TESTIN[10]
CELL[4].IMUX_IMUX[15]PLL[0].TESTIN[15]
CELL[4].IMUX_IMUX[16]PLL[0].TESTIN[8]
CELL[4].IMUX_IMUX[30]PLL[0].TESTIN[14]
CELL[4].IMUX_IMUX[41]PLL[0].TESTIN[9]
CELL[4].IMUX_IMUX[43]PLL[0].TESTIN[11]
CELL[4].IMUX_IMUX[44]PLL[0].TESTIN[12]
CELL[4].IMUX_IMUX[45]PLL[0].TESTIN[13]
CELL[4].OUT_BEL[2]PLL[0].TESTOUT[11]
CELL[4].OUT_BEL[7]PLL[0].TESTOUT[14]
CELL[4].OUT_BEL[10]PLL[0].TESTOUT[10]
CELL[4].OUT_BEL[15]PLL[0].TESTOUT[12]
CELL[4].OUT_BEL[17]PLL[0].TESTOUT[15]
CELL[4].OUT_BEL[18]PLL[0].TESTOUT[8]
CELL[4].OUT_BEL[21]PLL[0].TESTOUT[13]
CELL[4].OUT_BEL[23]PLL[0].TESTOUT[9]
CELL[5].IMUX_IMUX[3]PLL[0].TESTIN[18]
CELL[5].IMUX_IMUX[15]PLL[0].TESTIN[23]
CELL[5].IMUX_IMUX[16]PLL[0].TESTIN[16]
CELL[5].IMUX_IMUX[30]PLL[0].TESTIN[22]
CELL[5].IMUX_IMUX[41]PLL[0].TESTIN[17]
CELL[5].IMUX_IMUX[43]PLL[0].TESTIN[19]
CELL[5].IMUX_IMUX[44]PLL[0].TESTIN[20]
CELL[5].IMUX_IMUX[45]PLL[0].TESTIN[21]
CELL[5].OUT_BEL[2]PLL[0].TESTOUT[19]
CELL[5].OUT_BEL[7]PLL[0].TESTOUT[22]
CELL[5].OUT_BEL[10]PLL[0].TESTOUT[18]
CELL[5].OUT_BEL[15]PLL[0].TESTOUT[20]
CELL[5].OUT_BEL[17]PLL[0].TESTOUT[23]
CELL[5].OUT_BEL[18]PLL[0].TESTOUT[16]
CELL[5].OUT_BEL[21]PLL[0].TESTOUT[21]
CELL[5].OUT_BEL[23]PLL[0].TESTOUT[17]
CELL[6].IMUX_IMUX[3]PLL[0].TESTIN[26]
CELL[6].IMUX_IMUX[15]PLL[0].TESTIN[31]
CELL[6].IMUX_IMUX[16]PLL[0].TESTIN[24]
CELL[6].IMUX_IMUX[30]PLL[0].TESTIN[30]
CELL[6].IMUX_IMUX[41]PLL[0].TESTIN[25]
CELL[6].IMUX_IMUX[43]PLL[0].TESTIN[27]
CELL[6].IMUX_IMUX[44]PLL[0].TESTIN[28]
CELL[6].IMUX_IMUX[45]PLL[0].TESTIN[29]
CELL[6].OUT_BEL[2]PLL[0].TESTOUT[27]
CELL[6].OUT_BEL[7]PLL[0].TESTOUT[30]
CELL[6].OUT_BEL[10]PLL[0].TESTOUT[26]
CELL[6].OUT_BEL[15]PLL[0].TESTOUT[28]
CELL[6].OUT_BEL[17]PLL[0].TESTOUT[31]
CELL[6].OUT_BEL[18]PLL[0].TESTOUT[24]
CELL[6].OUT_BEL[21]PLL[0].TESTOUT[29]
CELL[6].OUT_BEL[23]PLL[0].TESTOUT[25]
CELL[7].OUT_BEL[1]PLL[0].TESTOUT[33]
CELL[7].OUT_BEL[6]PLL[0].TESTOUT[35]
CELL[7].OUT_BEL[9]PLL[0].TESTOUT[34]
CELL[7].OUT_BEL[14]PHASER_OUT[0].DTSBUS[0]
CELL[7].OUT_BEL[15]PLL[0].TESTOUT[37]
CELL[7].OUT_BEL[16]PLL[0].TESTOUT[36]
CELL[7].OUT_BEL[17]PLL[0].TESTOUT[39]
CELL[7].OUT_BEL[18]PLL[0].TESTOUT[32]
CELL[7].OUT_BEL[21]PLL[0].TESTOUT[38]
CELL[7].OUT_BEL[23]PHASER_OUT[0].DTSBUS[1]
CELL[7].PHASER_ICLKPHASER_IN[0].ICLK
CELL[7].PHASER_ICLKDIVPHASER_IN[0].ICLKDIV
CELL[7].PHASER_IWRENPHASER_IN[0].WRENABLE
CELL[7].PHASER_OCLKPHASER_OUT[0].OCLK
CELL[7].PHASER_OCLKDIVPHASER_OUT[0].OCLKDIV
CELL[7].PHASER_ORDENPHASER_OUT[0].RDENABLE
CELL[8].OUT_BEL[0]PHASER_OUT[0].DQSBUS[0]
CELL[8].OUT_BEL[1]PLL[0].TESTOUT[42]
CELL[8].OUT_BEL[4]PLL[0].TESTOUT[40]
CELL[8].OUT_BEL[5]PHASER_OUT[0].DQSBUS[1]
CELL[8].OUT_BEL[6]PLL[0].TESTOUT[44]
CELL[8].OUT_BEL[9]PLL[0].TESTOUT[43]
CELL[8].OUT_BEL[14]PHASER_OUT[0].CTSBUS[0]
CELL[8].OUT_BEL[15]PLL[0].TESTOUT[46]
CELL[8].OUT_BEL[16]PLL[0].TESTOUT[45]
CELL[8].OUT_BEL[17]PLL[0].TESTOUT[47]
CELL[8].OUT_BEL[18]PLL[0].TESTOUT[41]
CELL[8].OUT_BEL[23]PHASER_OUT[0].CTSBUS[1]
CELL[9].OUT_BEL[2]PLL[0].TESTOUT[51]
CELL[9].OUT_BEL[7]PLL[0].TESTOUT[54]
CELL[9].OUT_BEL[10]PLL[0].TESTOUT[50]
CELL[9].OUT_BEL[15]PLL[0].TESTOUT[52]
CELL[9].OUT_BEL[17]PLL[0].TESTOUT[55]
CELL[9].OUT_BEL[18]PLL[0].TESTOUT[48]
CELL[9].OUT_BEL[21]PLL[0].TESTOUT[53]
CELL[9].OUT_BEL[23]PLL[0].TESTOUT[49]
CELL[10].OUT_BEL[2]PLL[0].TESTOUT[59]
CELL[10].OUT_BEL[7]PLL[0].TESTOUT[62]
CELL[10].OUT_BEL[10]PLL[0].TESTOUT[58]
CELL[10].OUT_BEL[15]PLL[0].TESTOUT[60]
CELL[10].OUT_BEL[17]PLL[0].TESTOUT[63]
CELL[10].OUT_BEL[18]PLL[0].TESTOUT[56]
CELL[10].OUT_BEL[21]PLL[0].TESTOUT[61]
CELL[10].OUT_BEL[23]PLL[0].TESTOUT[57]
CELL[16].OUT_BEL[2]PHASER_OUT[0].COARSEOVERFLOW
CELL[16].OUT_BEL[3]PHASER_OUT[0].COUNTERREADVAL[0]
CELL[16].OUT_BEL[6]PHASER_OUT[0].TESTOUT[3]
CELL[16].OUT_BEL[7]PHASER_OUT[0].COUNTERREADVAL[2]
CELL[16].OUT_BEL[10]PHASER_OUT[0].TESTOUT[2]
CELL[16].OUT_BEL[14]PHASER_OUT[0].OSERDESRST
CELL[16].OUT_BEL[16]PHASER_OUT[0].COUNTERREADVAL[8]
CELL[16].OUT_BEL[17]PHASER_OUT[0].COUNTERREADVAL[3]
CELL[16].OUT_BEL[18]PHASER_OUT[0].TESTOUT[0]
CELL[16].OUT_BEL[21]PHASER_OUT[0].COUNTERREADVAL[1]
CELL[16].OUT_BEL[23]PHASER_OUT[0].TESTOUT[1]
CELL[17].IMUX_CLK[0]PHASER_OUT[0].SYSCLK
CELL[17].IMUX_CLK[1]PHASER_OUT[0].SCANCLK
CELL[17].IMUX_IMUX[0]PHASER_OUT[0].DIVIDERST
CELL[17].IMUX_IMUX[1]PHASER_OUT[0].TESTIN[3]
CELL[17].IMUX_IMUX[2]PHASER_OUT[0].TESTIN[7]
CELL[17].IMUX_IMUX[3]PHASER_OUT[0].TESTIN[10]
CELL[17].IMUX_IMUX[4]PHASER_OUT[0].TESTIN[13]
CELL[17].IMUX_IMUX[8]PHASER_OUT[0].TESTIN[0]
CELL[17].IMUX_IMUX[13]PHASER_OUT[0].COUNTERLOADVAL[0]
CELL[17].IMUX_IMUX[14]PHASER_OUT[0].COUNTERLOADVAL[3]
CELL[17].IMUX_IMUX[15]PHASER_OUT[0].COUNTERLOADVAL[6]
CELL[17].IMUX_IMUX[16]PHASER_OUT[0].SCANMODEB
CELL[17].IMUX_IMUX[17]PHASER_OUT[0].TESTIN[4]
CELL[17].IMUX_IMUX[18]PHASER_OUT[0].TESTIN[8]
CELL[17].IMUX_IMUX[20]PHASER_OUT[0].SCANIN
CELL[17].IMUX_IMUX[23]PHASER_OUT[0].COUNTERLOADVAL[7]
CELL[17].IMUX_IMUX[24]PHASER_OUT[0].TESTIN[1]
CELL[17].IMUX_IMUX[25]PHASER_OUT[0].COUNTERLOADVAL[8]
CELL[17].IMUX_IMUX[27]PHASER_OUT[0].TESTIN[11]
CELL[17].IMUX_IMUX[29]PHASER_OUT[0].COUNTERLOADVAL[1]
CELL[17].IMUX_IMUX[30]PHASER_OUT[0].COUNTERLOADVAL[4]
CELL[17].IMUX_IMUX[31]PHASER_OUT[0].COUNTERREADEN
CELL[17].IMUX_IMUX[32]PHASER_OUT[0].TESTIN[2]
CELL[17].IMUX_IMUX[33]PHASER_OUT[0].TESTIN[5]
CELL[17].IMUX_IMUX[34]PHASER_OUT[0].TESTIN[9]
CELL[17].IMUX_IMUX[41]PHASER_OUT[0].TESTIN[6]
CELL[17].IMUX_IMUX[43]PHASER_OUT[0].TESTIN[12]
CELL[17].IMUX_IMUX[44]PHASER_OUT[0].SCANENB
CELL[17].IMUX_IMUX[45]PHASER_OUT[0].COUNTERLOADVAL[2]
CELL[17].IMUX_IMUX[46]PHASER_OUT[0].COUNTERLOADVAL[5]
CELL[17].IMUX_IMUX[47]PHASER_OUT[0].COUNTERLOADEN
CELL[17].OUT_BEL[2]PHASER_IN[0].TESTOUT[0]
CELL[17].OUT_BEL[3]PHASER_IN[0].TESTOUT[1]
CELL[17].OUT_BEL[6]PHASER_OUT[0].COUNTERREADVAL[5]
CELL[17].OUT_BEL[7]PHASER_IN[0].TESTOUT[3]
CELL[17].OUT_BEL[10]PHASER_OUT[0].COUNTERREADVAL[4]
CELL[17].OUT_BEL[14]PHASER_OUT[0].COUNTERREADVAL[7]
CELL[17].OUT_BEL[16]PHASER_OUT[0].COUNTERREADVAL[6]
CELL[17].OUT_BEL[17]PHASER_IN[0].SCANOUT
CELL[17].OUT_BEL[18]PHASER_OUT[0].SCANOUT
CELL[17].OUT_BEL[21]PHASER_IN[0].TESTOUT[2]
CELL[17].OUT_BEL[23]PHASER_OUT[0].FINEOVERFLOW
CELL[18].IMUX_CLK[0]PHASER_IN[0].SYSCLK
CELL[18].IMUX_CLK[1]PHASER_IN[0].SCANCLK
CELL[18].IMUX_IMUX[0]PHASER_OUT[0].SELFINEOCLKDELAY
CELL[18].IMUX_IMUX[1]PHASER_OUT[0].FINEENABLE
CELL[18].IMUX_IMUX[2]PHASER_OUT[0].EDGEADV
CELL[18].IMUX_IMUX[3]PHASER_OUT[0].BURSTPENDING
CELL[18].IMUX_IMUX[4]PHASER_IN[0].TESTIN[1]
CELL[18].IMUX_IMUX[8]PHASER_OUT[0].TESTIN[14]
CELL[18].IMUX_IMUX[9]PHASER_OUT[0].COARSEINC
CELL[18].IMUX_IMUX[13]PHASER_IN[0].TESTIN[4]
CELL[18].IMUX_IMUX[14]PHASER_IN[0].TESTIN[7]
CELL[18].IMUX_IMUX[15]PHASER_IN[0].STG1READ
CELL[18].IMUX_IMUX[18]PHASER_OUT[0].ENCALIB[0]
CELL[18].IMUX_IMUX[19]PHASER_IN[0].DIVIDERST
CELL[18].IMUX_IMUX[20]PHASER_IN[0].TESTIN[2]
CELL[18].IMUX_IMUX[23]PHASER_IN[0].STG1LOAD
CELL[18].IMUX_IMUX[24]PHASER_OUT[0].TESTIN[15]
CELL[18].IMUX_IMUX[27]PHASER_OUT[0].RST
CELL[18].IMUX_IMUX[29]PHASER_IN[0].TESTIN[5]
CELL[18].IMUX_IMUX[30]PHASER_IN[0].SCANIN
CELL[18].IMUX_IMUX[31]PHASER_IN[0].ENSTG1
CELL[18].IMUX_IMUX[32]PHASER_OUT[0].FINEINC
CELL[18].IMUX_IMUX[34]PHASER_OUT[0].ENCALIB[1]
CELL[18].IMUX_IMUX[41]PHASER_OUT[0].COARSEENABLE
CELL[18].IMUX_IMUX[43]PHASER_IN[0].TESTIN[0]
CELL[18].IMUX_IMUX[44]PHASER_IN[0].TESTIN[3]
CELL[18].IMUX_IMUX[45]PHASER_IN[0].TESTIN[6]
CELL[18].IMUX_IMUX[46]PHASER_IN[0].SCANENB
CELL[18].IMUX_IMUX[47]PHASER_IN[0].STG1INCDEC
CELL[18].OUT_BEL[2]PHASER_IN[0].STG1REGR[4]
CELL[18].OUT_BEL[3]PHASER_IN[0].COUNTERREADVAL[1]
CELL[18].OUT_BEL[6]PHASER_IN[0].STG1REGR[1]
CELL[18].OUT_BEL[7]PHASER_IN[0].COUNTERREADVAL[3]
CELL[18].OUT_BEL[10]PHASER_IN[0].STG1REGR[0]
CELL[18].OUT_BEL[14]PHASER_IN[0].STG1REGR[3]
CELL[18].OUT_BEL[15]PHASER_IN[0].COUNTERREADVAL[0]
CELL[18].OUT_BEL[16]PHASER_IN[0].STG1REGR[2]
CELL[18].OUT_BEL[17]PHASER_IN[0].PHASELOCKED
CELL[18].OUT_BEL[18]PHASER_IN[0].ISERDESRST
CELL[18].OUT_BEL[21]PHASER_IN[0].COUNTERREADVAL[2]
CELL[18].OUT_BEL[23]PHASER_IN[0].DQSFOUND
CELL[19].IMUX_IMUX[0]PHASER_IN[0].STG1REGL[0]
CELL[19].IMUX_IMUX[8]PHASER_IN[0].RSTDQSFIND
CELL[19].IMUX_IMUX[9]PHASER_IN[0].STG1REGL[3]
CELL[19].IMUX_IMUX[10]PHASER_IN[0].STG1REGL[6]
CELL[19].IMUX_IMUX[11]PHASER_IN[0].COUNTERLOADVAL[0]
CELL[19].IMUX_IMUX[12]PHASER_IN[0].COUNTERLOADVAL[4]
CELL[19].IMUX_IMUX[14]PHASER_IN[0].FINEINC
CELL[19].IMUX_IMUX[15]PHASER_IN[0].SCANMODEB
CELL[19].IMUX_IMUX[16]PHASER_IN[0].STG1REGL[1]
CELL[19].IMUX_IMUX[18]PHASER_IN[0].STG1REGL[7]
CELL[19].IMUX_IMUX[19]PHASER_IN[0].COUNTERLOADVAL[1]
CELL[19].IMUX_IMUX[27]PHASER_IN[0].COUNTERLOADVAL[2]
CELL[19].IMUX_IMUX[28]PHASER_IN[0].COUNTERLOADVAL[5]
CELL[19].IMUX_IMUX[29]PHASER_IN[0].COUNTERREADEN
CELL[19].IMUX_IMUX[30]PHASER_IN[0].FINEENABLE
CELL[19].IMUX_IMUX[32]PHASER_IN[0].STG1REGL[2]
CELL[19].IMUX_IMUX[33]PHASER_IN[0].STG1REGL[4]
CELL[19].IMUX_IMUX[34]PHASER_IN[0].STG1REGL[8]
CELL[19].IMUX_IMUX[39]PHASER_IN[0].ENSTG1ADJUSTB
CELL[19].IMUX_IMUX[41]PHASER_IN[0].STG1REGL[5]
CELL[19].IMUX_IMUX[43]PHASER_IN[0].COUNTERLOADVAL[3]
CELL[19].IMUX_IMUX[45]PHASER_IN[0].COUNTERLOADEN
CELL[19].OUT_BEL[0]PHASER_IN[0].STG1REGR[7]
CELL[19].OUT_BEL[1]PHASER_IN[0].FINEOVERFLOW
CELL[19].OUT_BEL[4]PHASER_IN[0].STG1REGR[5]
CELL[19].OUT_BEL[6]PHASER_IN[0].COUNTERREADVAL[4]
CELL[19].OUT_BEL[14]PHASER_OUT[1].DTSBUS[0]
CELL[19].OUT_BEL[16]PHASER_IN[0].COUNTERREADVAL[5]
CELL[19].OUT_BEL[17]PHASER_IN[0].STG1OVERFLOW
CELL[19].OUT_BEL[18]PHASER_IN[0].STG1REGR[6]
CELL[19].OUT_BEL[23]PHASER_OUT[1].DTSBUS[1]
CELL[19].PHASER_ICLKPHASER_IN[1].ICLK
CELL[19].PHASER_ICLKDIVPHASER_IN[1].ICLKDIV
CELL[19].PHASER_IWRENPHASER_IN[1].WRENABLE
CELL[19].PHASER_OCLKPHASER_OUT[1].OCLK
CELL[19].PHASER_OCLKDIVPHASER_OUT[1].OCLKDIV
CELL[19].PHASER_ORDENPHASER_OUT[1].RDENABLE
CELL[20].IMUX_IMUX[0]PHASER_IN[0].TESTIN[8]
CELL[20].IMUX_IMUX[2]PHASER_IN[0].TESTIN[13]
CELL[20].IMUX_IMUX[9]PHASER_IN[0].TESTIN[11]
CELL[20].IMUX_IMUX[10]PHASER_IN[0].SELCALORSTG1
CELL[20].IMUX_IMUX[11]PHASER_IN[0].ENCALIB[0]
CELL[20].IMUX_IMUX[12]PHASER_IN[0].RST
CELL[20].IMUX_IMUX[14]PHASER_OUT[1].COUNTERLOADVAL[4]
CELL[20].IMUX_IMUX[15]PHASER_OUT[1].COUNTERLOADVAL[7]
CELL[20].IMUX_IMUX[16]PHASER_IN[0].TESTIN[9]
CELL[20].IMUX_IMUX[18]PHASER_IN[0].BURSTPENDING
CELL[20].IMUX_IMUX[19]PHASER_IN[0].ENCALIB[1]
CELL[20].IMUX_IMUX[20]PHASER_OUT[1].SELFINEOCLKDELAY
CELL[20].IMUX_IMUX[21]PHASER_OUT[1].COUNTERLOADVAL[1]
CELL[20].IMUX_IMUX[23]PHASER_OUT[1].COUNTERREADEN
CELL[20].IMUX_IMUX[27]PHASER_IN[0].RANKSEL[0]
CELL[20].IMUX_IMUX[28]PHASER_OUT[1].SCANENB
CELL[20].IMUX_IMUX[29]PHASER_OUT[1].COUNTERLOADVAL[2]
CELL[20].IMUX_IMUX[30]PHASER_OUT[1].COUNTERLOADVAL[5]
CELL[20].IMUX_IMUX[32]PHASER_IN[0].TESTIN[10]
CELL[20].IMUX_IMUX[34]PHASER_IN[0].EDGEADV
CELL[20].IMUX_IMUX[39]PHASER_OUT[1].COUNTERLOADEN
CELL[20].IMUX_IMUX[41]PHASER_IN[0].TESTIN[12]
CELL[20].IMUX_IMUX[43]PHASER_IN[0].RANKSEL[1]
CELL[20].IMUX_IMUX[44]PHASER_OUT[1].COUNTERLOADVAL[0]
CELL[20].IMUX_IMUX[45]PHASER_OUT[1].COUNTERLOADVAL[3]
CELL[20].IMUX_IMUX[46]PHASER_OUT[1].COUNTERLOADVAL[6]
CELL[20].OUT_BEL[0]PHASER_OUT[1].DQSBUS[0]
CELL[20].OUT_BEL[1]PHASER_OUT[1].TESTOUT[0]
CELL[20].OUT_BEL[4]PHASER_IN[0].STG1REGR[8]
CELL[20].OUT_BEL[5]PHASER_OUT[1].DQSBUS[1]
CELL[20].OUT_BEL[6]PHASER_OUT[1].COUNTERREADVAL[0]
CELL[20].OUT_BEL[9]PHASER_OUT[1].TESTOUT[1]
CELL[20].OUT_BEL[14]PHASER_OUT[1].CTSBUS[0]
CELL[20].OUT_BEL[15]PHASER_OUT[1].COUNTERREADVAL[2]
CELL[20].OUT_BEL[16]PHASER_OUT[1].COUNTERREADVAL[1]
CELL[20].OUT_BEL[17]PHASER_OUT[1].COUNTERREADVAL[3]
CELL[20].OUT_BEL[18]PHASER_IN[0].DQSOUTOFRANGE
CELL[20].OUT_BEL[23]PHASER_OUT[1].CTSBUS[1]
CELL[21].IMUX_CLK[0]PHASER_OUT[1].SYSCLK
CELL[21].IMUX_CLK[1]PHASER_OUT[1].SCANCLK
CELL[21].IMUX_IMUX[0]PHASER_OUT[1].DIVIDERST
CELL[21].IMUX_IMUX[1]PHASER_OUT[1].TESTIN[3]
CELL[21].IMUX_IMUX[2]PHASER_OUT[1].TESTIN[7]
CELL[21].IMUX_IMUX[3]PHASER_OUT[1].TESTIN[10]
CELL[21].IMUX_IMUX[4]PHASER_OUT[1].TESTIN[14]
CELL[21].IMUX_IMUX[8]PHASER_OUT[1].TESTIN[0]
CELL[21].IMUX_IMUX[9]PHASER_OUT[1].TESTIN[4]
CELL[21].IMUX_IMUX[11]PHASER_OUT[1].TESTIN[11]
CELL[21].IMUX_IMUX[13]PHASER_OUT[1].FINEINC
CELL[21].IMUX_IMUX[14]PHASER_OUT[1].COARSEENABLE
CELL[21].IMUX_IMUX[15]PHASER_OUT[1].ENCALIB[1]
CELL[21].IMUX_IMUX[16]PHASER_OUT[1].SCANMODEB
CELL[21].IMUX_IMUX[17]PHASER_OUT[1].TESTIN[5]
CELL[21].IMUX_IMUX[18]PHASER_OUT[1].TESTIN[8]
CELL[21].IMUX_IMUX[20]PHASER_OUT[1].TESTIN[15]
CELL[21].IMUX_IMUX[23]PHASER_OUT[1].BURSTPENDING
CELL[21].IMUX_IMUX[24]PHASER_OUT[1].TESTIN[1]
CELL[21].IMUX_IMUX[25]PHASER_OUT[1].COUNTERLOADVAL[8]
CELL[21].IMUX_IMUX[27]PHASER_OUT[1].TESTIN[12]
CELL[21].IMUX_IMUX[29]PHASER_OUT[1].FINEENABLE
CELL[21].IMUX_IMUX[30]PHASER_OUT[1].EDGEADV
CELL[21].IMUX_IMUX[32]PHASER_OUT[1].TESTIN[2]
CELL[21].IMUX_IMUX[34]PHASER_OUT[1].TESTIN[9]
CELL[21].IMUX_IMUX[41]PHASER_OUT[1].TESTIN[6]
CELL[21].IMUX_IMUX[43]PHASER_OUT[1].TESTIN[13]
CELL[21].IMUX_IMUX[44]PHASER_OUT[1].SCANIN
CELL[21].IMUX_IMUX[45]PHASER_OUT[1].COARSEINC
CELL[21].IMUX_IMUX[46]PHASER_OUT[1].ENCALIB[0]
CELL[21].IMUX_IMUX[47]PHASER_OUT[1].RST
CELL[21].OUT_BEL[2]PHASER_OUT[1].COUNTERREADVAL[4]
CELL[21].OUT_BEL[3]PHASER_OUT[1].COUNTERREADVAL[6]
CELL[21].OUT_BEL[6]PHASER_OUT[1].OSERDESRST
CELL[21].OUT_BEL[7]PHASER_IN[1].TESTOUT[0]
CELL[21].OUT_BEL[10]PHASER_OUT[1].COUNTERREADVAL[8]
CELL[21].OUT_BEL[14]PHASER_OUT[1].COARSEOVERFLOW
CELL[21].OUT_BEL[15]PHASER_OUT[1].COUNTERREADVAL[5]
CELL[21].OUT_BEL[16]PHASER_OUT[1].SCANOUT
CELL[21].OUT_BEL[17]PHASER_IN[1].TESTOUT[1]
CELL[21].OUT_BEL[18]PHASER_OUT[1].TESTOUT[2]
CELL[21].OUT_BEL[21]PHASER_OUT[1].COUNTERREADVAL[7]
CELL[21].OUT_BEL[23]PHASER_OUT[1].TESTOUT[3]
CELL[22].IMUX_CLK[0]PHASER_IN[1].SYSCLK
CELL[22].IMUX_CLK[1]PHASER_IN[1].SCANCLK
CELL[22].IMUX_IMUX[1]PHASER_IN[1].TESTIN[3]
CELL[22].IMUX_IMUX[2]PHASER_IN[1].STG1REGL[1]
CELL[22].IMUX_IMUX[3]PHASER_IN[1].STG1REGL[4]
CELL[22].IMUX_IMUX[4]PHASER_IN[1].STG1REGL[8]
CELL[22].IMUX_IMUX[8]PHASER_IN[1].TESTIN[0]
CELL[22].IMUX_IMUX[9]PHASER_IN[1].SCANIN
CELL[22].IMUX_IMUX[11]PHASER_IN[1].STG1REGL[5]
CELL[22].IMUX_IMUX[13]PHASER_IN[1].COUNTERLOADVAL[1]
CELL[22].IMUX_IMUX[14]PHASER_IN[1].COUNTERLOADVAL[4]
CELL[22].IMUX_IMUX[17]PHASER_IN[1].SCANENB
CELL[22].IMUX_IMUX[18]PHASER_IN[1].STG1REGL[2]
CELL[22].IMUX_IMUX[20]PHASER_IN[1].STG1READ
CELL[22].IMUX_IMUX[23]PHASER_IN[1].COUNTERREADEN
CELL[22].IMUX_IMUX[24]PHASER_IN[1].TESTIN[1]
CELL[22].IMUX_IMUX[27]PHASER_IN[1].STG1REGL[6]
CELL[22].IMUX_IMUX[29]PHASER_IN[1].COUNTERLOADVAL[2]
CELL[22].IMUX_IMUX[30]PHASER_IN[1].COUNTERLOADVAL[5]
CELL[22].IMUX_IMUX[31]PHASER_IN[1].COUNTERLOADEN
CELL[22].IMUX_IMUX[32]PHASER_IN[1].TESTIN[2]
CELL[22].IMUX_IMUX[34]PHASER_IN[1].STG1REGL[3]
CELL[22].IMUX_IMUX[41]PHASER_IN[1].STG1REGL[0]
CELL[22].IMUX_IMUX[43]PHASER_IN[1].STG1REGL[7]
CELL[22].IMUX_IMUX[44]PHASER_IN[1].COUNTERLOADVAL[0]
CELL[22].IMUX_IMUX[45]PHASER_IN[1].COUNTERLOADVAL[3]
CELL[22].IMUX_IMUX[47]PHASER_IN[1].FINEINC
CELL[22].OUT_BEL[2]PHASER_IN[1].STG1REGR[1]
CELL[22].OUT_BEL[3]PHASER_IN[1].FINEOVERFLOW
CELL[22].OUT_BEL[6]PHASER_IN[1].ISERDESRST
CELL[22].OUT_BEL[7]PHASER_IN[1].STG1OVERFLOW
CELL[22].OUT_BEL[10]PHASER_IN[1].TESTOUT[3]
CELL[22].OUT_BEL[14]PHASER_IN[1].STG1REGR[0]
CELL[22].OUT_BEL[15]PHASER_IN[1].STG1REGR[2]
CELL[22].OUT_BEL[16]PHASER_IN[1].DQSFOUND
CELL[22].OUT_BEL[17]PHASER_IN[1].PHASELOCKED
CELL[22].OUT_BEL[18]PHASER_OUT[1].FINEOVERFLOW
CELL[22].OUT_BEL[23]PHASER_IN[1].TESTOUT[2]
CELL[23].IMUX_IMUX[0]PHASER_IN[1].RSTDQSFIND
CELL[23].IMUX_IMUX[1]PHASER_IN[1].TESTIN[7]
CELL[23].IMUX_IMUX[2]PHASER_IN[1].TESTIN[10]
CELL[23].IMUX_IMUX[3]PHASER_IN[1].TESTIN[13]
CELL[23].IMUX_IMUX[4]PHASER_IN[1].ENSTG1
CELL[23].IMUX_IMUX[8]PHASER_IN[1].TESTIN[4]
CELL[23].IMUX_IMUX[9]PHASER_IN[1].TESTIN[8]
CELL[23].IMUX_IMUX[11]PHASER_IN[1].SELCALORSTG1
CELL[23].IMUX_IMUX[14]PHASER_IN[1].EDGEADV
CELL[23].IMUX_IMUX[15]PHASER_IN[1].RANKSEL[0]
CELL[23].IMUX_IMUX[18]PHASER_IN[1].TESTIN[11]
CELL[23].IMUX_IMUX[19]PHASER_IN[1].DIVIDERST
CELL[23].IMUX_IMUX[20]PHASER_IN[1].STG1INCDEC
CELL[23].IMUX_IMUX[24]PHASER_IN[1].TESTIN[5]
CELL[23].IMUX_IMUX[27]PHASER_IN[1].BURSTPENDING
CELL[23].IMUX_IMUX[29]PHASER_IN[1].SCANMODEB
CELL[23].IMUX_IMUX[30]PHASER_IN[1].ENCALIB[0]
CELL[23].IMUX_IMUX[31]PHASER_IN[1].RANKSEL[1]
CELL[23].IMUX_IMUX[32]PHASER_IN[1].TESTIN[6]
CELL[23].IMUX_IMUX[34]PHASER_IN[1].TESTIN[12]
CELL[23].IMUX_IMUX[41]PHASER_IN[1].TESTIN[9]
CELL[23].IMUX_IMUX[43]PHASER_IN[1].STG1LOAD
CELL[23].IMUX_IMUX[44]PHASER_IN[1].FINEENABLE
CELL[23].IMUX_IMUX[45]PHASER_IN[1].ENSTG1ADJUSTB
CELL[23].IMUX_IMUX[46]PHASER_IN[1].ENCALIB[1]
CELL[23].IMUX_IMUX[47]PHASER_IN[1].RST
CELL[23].OUT_BEL[2]PHASER_IN[1].COUNTERREADVAL[0]
CELL[23].OUT_BEL[3]PHASER_IN[1].COUNTERREADVAL[2]
CELL[23].OUT_BEL[6]PHASER_IN[1].STG1REGR[5]
CELL[23].OUT_BEL[10]PHASER_IN[1].STG1REGR[4]
CELL[23].OUT_BEL[14]PHASER_IN[1].DQSOUTOFRANGE
CELL[23].OUT_BEL[15]PHASER_IN[1].COUNTERREADVAL[1]
CELL[23].OUT_BEL[16]PHASER_IN[1].STG1REGR[6]
CELL[23].OUT_BEL[18]PHASER_IN[1].SCANOUT
CELL[23].OUT_BEL[21]PHASER_IN[1].COUNTERREADVAL[3]
CELL[23].OUT_BEL[23]PHASER_IN[1].STG1REGR[3]
CELL[24].OUT_BEL[6]PHASER_IN[1].COUNTERREADVAL[5]
CELL[24].OUT_BEL[10]PHASER_IN[1].COUNTERREADVAL[4]
CELL[24].OUT_BEL[18]PHASER_IN[1].STG1REGR[7]
CELL[24].OUT_BEL[23]PHASER_IN[1].STG1REGR[8]
CELL[25].IMUX_IMUX[0]BUFMRCE[0].CE
CELL[25].IMUX_IMUX[1]PHASER_REF.TESTIN[2]
CELL[25].IMUX_IMUX[3]PHASER_REF.TESTIN[5]
CELL[25].IMUX_IMUX[4]PHASER_REF.TESTIN[6]
CELL[25].IMUX_IMUX[8]PHASER_REF.TESTIN[0]
CELL[25].IMUX_IMUX[13]PHASER_REF.TESTIN[7]
CELL[25].IMUX_IMUX[15]PHASER_REF.RST
CELL[25].IMUX_IMUX[16]BUFMRCE[1].CE
CELL[25].IMUX_IMUX[18]PHASER_REF.TESTIN[4]
CELL[25].IMUX_IMUX[32]PHASER_REF.TESTIN[1]
CELL[25].IMUX_IMUX[41]PHASER_REF.TESTIN[3]
CELL[25].IMUX_IMUX[45]PHASER_REF.PWRDWN
CELL[25].OUT_BEL[2]PHASER_OUT[2].SCANOUT
CELL[25].OUT_BEL[3]PHASER_OUT[2].COUNTERREADVAL[0]
CELL[25].OUT_BEL[6]PHASER_REF.TESTOUT[6]
CELL[25].OUT_BEL[7]PHASER_OUT[2].COUNTERREADVAL[2]
CELL[25].OUT_BEL[10]PHASER_REF.TESTOUT[5]
CELL[25].OUT_BEL[14]PHASER_REF.LOCKED
CELL[25].OUT_BEL[15]PHASER_OUT[2].COARSEOVERFLOW
CELL[25].OUT_BEL[16]PHASER_REF.TESTOUT[7]
CELL[25].OUT_BEL[17]PHASER_OUT[2].COUNTERREADVAL[3]
CELL[25].OUT_BEL[18]PHASER_REF.TESTOUT[3]
CELL[25].OUT_BEL[21]PHASER_OUT[2].COUNTERREADVAL[1]
CELL[25].OUT_BEL[23]PHASER_REF.TESTOUT[4]
CELL[25].CMT_SYNC_BBPHY_CONTROL.PHYCTLMSTREMPTY
CELL[25].IMUX_BUFMRCE[0]BUFMRCE[0].I
CELL[25].IMUX_BUFMRCE[1]BUFMRCE[1].I
CELL[25].IMUX_PLL_CLKIN1[0]PLL[0].CLKIN1
CELL[25].IMUX_PLL_CLKIN1[1]PLL[1].CLKIN1
CELL[25].IMUX_PLL_CLKIN2[0]PLL[0].CLKIN2
CELL[25].IMUX_PLL_CLKIN2[1]PLL[1].CLKIN2
CELL[25].IMUX_PLL_CLKFB[0]PLL[0].CLKFBIN
CELL[25].IMUX_PLL_CLKFB[1]PLL[1].CLKFBIN
CELL[25].OUT_PLL_S[0]PLL[0].CLKOUT0
CELL[25].OUT_PLL_S[1]PLL[0].CLKOUT0B
CELL[25].OUT_PLL_S[2]PLL[0].CLKOUT1
CELL[25].OUT_PLL_S[3]PLL[0].CLKOUT1B
CELL[25].OUT_PLL_S[4]PLL[0].CLKOUT2
CELL[25].OUT_PLL_S[5]PLL[0].CLKOUT2B
CELL[25].OUT_PLL_S[6]PLL[0].CLKOUT3
CELL[25].OUT_PLL_S[7]PLL[0].CLKOUT3B
CELL[25].OUT_PLL_S[8]PLL[0].CLKOUT4
CELL[25].OUT_PLL_S[9]PLL[0].CLKOUT5
CELL[25].OUT_PLL_S[10]PLL[0].CLKOUT6
CELL[25].OUT_PLL_S[11]PLL[0].CLKFBOUT
CELL[25].OUT_PLL_S[12]PLL[0].CLKFBOUTB
CELL[25].OUT_PLL_S[13]PLL[0].TMUXOUT
CELL[25].OUT_PLL_N[0]PLL[1].CLKOUT0
CELL[25].OUT_PLL_N[1]PLL[1].CLKOUT1
CELL[25].OUT_PLL_N[2]PLL[1].CLKOUT2
CELL[25].OUT_PLL_N[3]PLL[1].CLKOUT3
CELL[25].OUT_PLL_N[4]PLL[1].CLKOUT4
CELL[25].OUT_PLL_N[5]PLL[1].CLKOUT5
CELL[25].OUT_PLL_N[6]PLL[1].CLKFBOUT
CELL[25].OUT_PLL_N[7]PLL[1].TMUXOUT
CELL[25].IMUX_PHASER_REFMUX[0]PHASER_IN[0].FREQREFCLK, PHASER_IN[1].FREQREFCLK, PHASER_IN[2].FREQREFCLK, PHASER_IN[3].FREQREFCLK, PHASER_OUT[0].FREQREFCLK, PHASER_OUT[1].FREQREFCLK, PHASER_OUT[2].FREQREFCLK, PHASER_OUT[3].FREQREFCLK, PHASER_REF.CLKIN
CELL[25].IMUX_PHASER_REFMUX[1]PHASER_IN[0].MEMREFCLK, PHASER_IN[1].MEMREFCLK, PHASER_IN[2].MEMREFCLK, PHASER_IN[3].MEMREFCLK, PHASER_OUT[0].MEMREFCLK, PHASER_OUT[1].MEMREFCLK, PHASER_OUT[2].MEMREFCLK, PHASER_OUT[3].MEMREFCLK, PHY_CONTROL.MEMREFCLK
CELL[25].IMUX_PHASER_REFMUX[2]PHASER_IN[0].SYNCIN, PHASER_IN[1].SYNCIN, PHASER_IN[2].SYNCIN, PHASER_IN[3].SYNCIN, PHASER_OUT[0].SYNCIN, PHASER_OUT[1].SYNCIN, PHASER_OUT[2].SYNCIN, PHASER_OUT[3].SYNCIN, PHY_CONTROL.SYNCIN
CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0]PHASER_IN[0].PHASEREFCLK
CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1]PHASER_IN[1].PHASEREFCLK
CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2]PHASER_IN[2].PHASEREFCLK
CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3]PHASER_IN[3].PHASEREFCLK
CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0]PHASER_OUT[0].PHASEREFCLK
CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1]PHASER_OUT[1].PHASEREFCLK
CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2]PHASER_OUT[2].PHASEREFCLK
CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3]PHASER_OUT[3].PHASEREFCLK
CELL[25].OUT_PHASER_REF_CLKOUTPHASER_REF.CLKOUT
CELL[25].OUT_PHASER_REF_TMUXOUTPHASER_REF.TMUXOUT
CELL[25].OUT_PHASER_IN_RCLK[0]PHASER_IN[0].RCLK
CELL[25].OUT_PHASER_IN_RCLK[1]PHASER_IN[1].RCLK
CELL[25].OUT_PHASER_IN_RCLK[2]PHASER_IN[2].RCLK
CELL[25].OUT_PHASER_IN_RCLK[3]PHASER_IN[3].RCLK
CELL[25].OUT_PHY_PHYCTLEMPTYPHY_CONTROL.PHYCTLEMPTY
CELL[25].VMRCLK[0]BUFMRCE[0].O
CELL[25].VMRCLK[1]BUFMRCE[1].O
CELL[26].IMUX_IMUX[0]PHASER_OUT[2].SELFINEOCLKDELAY
CELL[26].IMUX_IMUX[1]PHASER_OUT[2].TESTIN[3]
CELL[26].IMUX_IMUX[2]PHASER_OUT[2].TESTIN[7]
CELL[26].IMUX_IMUX[3]PHASER_OUT[2].TESTIN[10]
CELL[26].IMUX_IMUX[4]PHASER_OUT[2].SCANENB
CELL[26].IMUX_IMUX[8]PHASER_OUT[2].TESTIN[0]
CELL[26].IMUX_IMUX[9]PHASER_OUT[2].TESTIN[4]
CELL[26].IMUX_IMUX[11]PHASER_OUT[2].TESTIN[11]
CELL[26].IMUX_IMUX[13]PHASER_OUT[2].COUNTERLOADVAL[2]
CELL[26].IMUX_IMUX[14]PHASER_OUT[2].COUNTERLOADVAL[5]
CELL[26].IMUX_IMUX[15]PHASER_OUT[2].COUNTERREADEN
CELL[26].IMUX_IMUX[17]PHASER_OUT[2].TESTIN[5]
CELL[26].IMUX_IMUX[18]PHASER_OUT[2].TESTIN[8]
CELL[26].IMUX_IMUX[20]PHASER_OUT[2].COUNTERLOADVAL[0]
CELL[26].IMUX_IMUX[24]PHASER_OUT[2].TESTIN[1]
CELL[26].IMUX_IMUX[27]PHASER_OUT[2].TESTIN[12]
CELL[26].IMUX_IMUX[29]PHASER_OUT[2].COUNTERLOADVAL[3]
CELL[26].IMUX_IMUX[30]PHASER_OUT[2].COUNTERLOADVAL[6]
CELL[26].IMUX_IMUX[31]PHASER_OUT[2].COUNTERLOADEN
CELL[26].IMUX_IMUX[32]PHASER_OUT[2].TESTIN[2]
CELL[26].IMUX_IMUX[34]PHASER_OUT[2].TESTIN[9]
CELL[26].IMUX_IMUX[41]PHASER_OUT[2].TESTIN[6]
CELL[26].IMUX_IMUX[43]PHASER_OUT[2].SCANIN
CELL[26].IMUX_IMUX[44]PHASER_OUT[2].COUNTERLOADVAL[1]
CELL[26].IMUX_IMUX[45]PHASER_OUT[2].COUNTERLOADVAL[4]
CELL[26].IMUX_IMUX[46]PHASER_OUT[2].COUNTERLOADVAL[7]
CELL[26].IMUX_IMUX[47]PHASER_OUT[2].FINEINC
CELL[26].OUT_BEL[2]PHASER_OUT[2].FINEOVERFLOW
CELL[26].OUT_BEL[3]PHASER_OUT[2].COUNTERREADVAL[5]
CELL[26].OUT_BEL[6]PHASER_OUT[2].TESTOUT[0]
CELL[26].OUT_BEL[7]PHASER_OUT[2].COUNTERREADVAL[7]
CELL[26].OUT_BEL[10]PHASER_REF.TESTOUT[2]
CELL[26].OUT_BEL[14]PHASER_OUT[2].TESTOUT[2]
CELL[26].OUT_BEL[15]PHASER_OUT[2].COUNTERREADVAL[4]
CELL[26].OUT_BEL[16]PHASER_OUT[2].TESTOUT[1]
CELL[26].OUT_BEL[18]PHASER_REF.TESTOUT[0]
CELL[26].OUT_BEL[21]PHASER_OUT[2].COUNTERREADVAL[6]
CELL[26].OUT_BEL[23]PHASER_REF.TESTOUT[1]
CELL[27].IMUX_CLK[0]PHASER_OUT[2].SYSCLK
CELL[27].IMUX_CLK[1]PHASER_OUT[2].SCANCLK
CELL[27].IMUX_IMUX[0]PHASER_OUT[2].DIVIDERST
CELL[27].IMUX_IMUX[1]PHASER_OUT[2].FINEENABLE
CELL[27].IMUX_IMUX[2]PHASER_OUT[2].EDGEADV
CELL[27].IMUX_IMUX[3]PHASER_OUT[2].BURSTPENDING
CELL[27].IMUX_IMUX[4]PHASER_IN[2].TESTIN[1]
CELL[27].IMUX_IMUX[8]PHASER_OUT[2].TESTIN[13]
CELL[27].IMUX_IMUX[9]PHASER_OUT[2].COARSEINC
CELL[27].IMUX_IMUX[13]PHASER_IN[2].TESTIN[4]
CELL[27].IMUX_IMUX[14]PHASER_IN[2].TESTIN[7]
CELL[27].IMUX_IMUX[15]PHASER_IN[2].TESTIN[10]
CELL[27].IMUX_IMUX[16]PHASER_OUT[2].SCANMODEB
CELL[27].IMUX_IMUX[17]PHASER_OUT[2].COUNTERLOADVAL[8]
CELL[27].IMUX_IMUX[18]PHASER_OUT[2].ENCALIB[0]
CELL[27].IMUX_IMUX[19]PHASER_IN[2].DIVIDERST
CELL[27].IMUX_IMUX[20]PHASER_IN[2].TESTIN[2]
CELL[27].IMUX_IMUX[24]PHASER_OUT[2].TESTIN[14]
CELL[27].IMUX_IMUX[27]PHASER_OUT[2].RST
CELL[27].IMUX_IMUX[29]PHASER_IN[2].TESTIN[5]
CELL[27].IMUX_IMUX[30]PHASER_IN[2].TESTIN[8]
CELL[27].IMUX_IMUX[31]PHASER_IN[2].SCANIN
CELL[27].IMUX_IMUX[32]PHASER_OUT[2].TESTIN[15]
CELL[27].IMUX_IMUX[34]PHASER_OUT[2].ENCALIB[1]
CELL[27].IMUX_IMUX[41]PHASER_OUT[2].COARSEENABLE
CELL[27].IMUX_IMUX[43]PHASER_IN[2].TESTIN[0]
CELL[27].IMUX_IMUX[44]PHASER_IN[2].TESTIN[3]
CELL[27].IMUX_IMUX[45]PHASER_IN[2].TESTIN[6]
CELL[27].IMUX_IMUX[46]PHASER_IN[2].TESTIN[9]
CELL[27].IMUX_IMUX[47]PHASER_IN[2].SCANENB
CELL[27].OUT_BEL[2]PHASER_IN[2].FINEOVERFLOW
CELL[27].OUT_BEL[3]PHASER_IN[2].COUNTERREADVAL[1]
CELL[27].OUT_BEL[6]PHASER_IN[2].TESTOUT[0]
CELL[27].OUT_BEL[7]PHASER_IN[2].COUNTERREADVAL[3]
CELL[27].OUT_BEL[10]PHASER_OUT[2].OSERDESRST
CELL[27].OUT_BEL[14]PHASER_IN[2].SCANOUT
CELL[27].OUT_BEL[15]PHASER_IN[2].COUNTERREADVAL[0]
CELL[27].OUT_BEL[16]PHASER_IN[2].TESTOUT[1]
CELL[27].OUT_BEL[17]PHASER_IN[2].PHASELOCKED
CELL[27].OUT_BEL[18]PHASER_OUT[2].TESTOUT[3]
CELL[27].OUT_BEL[21]PHASER_IN[2].COUNTERREADVAL[2]
CELL[27].OUT_BEL[23]PHASER_OUT[2].COUNTERREADVAL[8]
CELL[28].IMUX_IMUX[0]PHASER_IN[2].RSTDQSFIND
CELL[28].IMUX_IMUX[1]PHASER_IN[2].SELCALORSTG1
CELL[28].IMUX_IMUX[2]PHASER_IN[2].STG1REGL[2]
CELL[28].IMUX_IMUX[3]PHASER_IN[2].STG1REGL[5]
CELL[28].IMUX_IMUX[4]PHASER_IN[2].STG1READ
CELL[28].IMUX_IMUX[8]PHASER_IN[2].TESTIN[11]
CELL[28].IMUX_IMUX[9]PHASER_IN[2].BURSTPENDING
CELL[28].IMUX_IMUX[11]PHASER_IN[2].STG1REGL[6]
CELL[28].IMUX_IMUX[13]PHASER_IN[2].COUNTERLOADVAL[1]
CELL[28].IMUX_IMUX[14]PHASER_IN[2].COUNTERLOADVAL[4]
CELL[28].IMUX_IMUX[17]PHASER_IN[2].STG1REGL[0]
CELL[28].IMUX_IMUX[18]PHASER_IN[2].STG1REGL[3]
CELL[28].IMUX_IMUX[20]PHASER_IN[2].STG1LOAD
CELL[28].IMUX_IMUX[23]PHASER_IN[2].COUNTERREADEN
CELL[28].IMUX_IMUX[24]PHASER_IN[2].TESTIN[12]
CELL[28].IMUX_IMUX[27]PHASER_IN[2].STG1REGL[7]
CELL[28].IMUX_IMUX[29]PHASER_IN[2].COUNTERLOADVAL[2]
CELL[28].IMUX_IMUX[30]PHASER_IN[2].COUNTERLOADVAL[5]
CELL[28].IMUX_IMUX[31]PHASER_IN[2].COUNTERLOADEN
CELL[28].IMUX_IMUX[32]PHASER_IN[2].TESTIN[13]
CELL[28].IMUX_IMUX[34]PHASER_IN[2].STG1REGL[4]
CELL[28].IMUX_IMUX[41]PHASER_IN[2].STG1REGL[1]
CELL[28].IMUX_IMUX[43]PHASER_IN[2].STG1REGL[8]
CELL[28].IMUX_IMUX[44]PHASER_IN[2].COUNTERLOADVAL[0]
CELL[28].IMUX_IMUX[45]PHASER_IN[2].COUNTERLOADVAL[3]
CELL[28].IMUX_IMUX[47]PHASER_IN[2].FINEINC
CELL[28].OUT_BEL[2]PHASER_IN[2].STG1REGR[2]
CELL[28].OUT_BEL[3]PHASER_IN[2].COUNTERREADVAL[4]
CELL[28].OUT_BEL[6]PHASER_IN[2].DQSFOUND
CELL[28].OUT_BEL[10]PHASER_IN[2].ISERDESRST
CELL[28].OUT_BEL[14]PHASER_IN[2].STG1REGR[1]
CELL[28].OUT_BEL[15]PHASER_IN[2].DQSOUTOFRANGE
CELL[28].OUT_BEL[16]PHASER_IN[2].STG1REGR[0]
CELL[28].OUT_BEL[18]PHASER_IN[2].TESTOUT[2]
CELL[28].OUT_BEL[21]PHASER_IN[2].COUNTERREADVAL[5]
CELL[28].OUT_BEL[23]PHASER_IN[2].TESTOUT[3]
CELL[29].IMUX_CLK[0]PHASER_IN[2].SYSCLK
CELL[29].IMUX_CLK[1]PHASER_IN[2].SCANCLK
CELL[29].IMUX_IMUX[2]PHASER_IN[2].ENCALIB[0]
CELL[29].IMUX_IMUX[3]PHASER_IN[2].RANKSEL[1]
CELL[29].IMUX_IMUX[4]PHASER_OUT[3].TESTIN[2]
CELL[29].IMUX_IMUX[8]PHASER_IN[2].ENSTG1
CELL[29].IMUX_IMUX[9]PHASER_IN[2].SCANMODEB
CELL[29].IMUX_IMUX[11]PHASER_IN[2].RST
CELL[29].IMUX_IMUX[13]PHASER_OUT[3].TESTIN[5]
CELL[29].IMUX_IMUX[14]PHASER_OUT[3].TESTIN[8]
CELL[29].IMUX_IMUX[15]PHASER_OUT[3].TESTIN[11]
CELL[29].IMUX_IMUX[17]PHASER_IN[2].ENSTG1ADJUSTB
CELL[29].IMUX_IMUX[18]PHASER_IN[2].ENCALIB[1]
CELL[29].IMUX_IMUX[19]PHASER_OUT[3].DIVIDERST
CELL[29].IMUX_IMUX[20]PHASER_OUT[3].TESTIN[3]
CELL[29].IMUX_IMUX[23]PHASER_OUT[3].TESTIN[12]
CELL[29].IMUX_IMUX[24]PHASER_IN[2].STG1INCDEC
CELL[29].IMUX_IMUX[27]PHASER_OUT[3].TESTIN[0]
CELL[29].IMUX_IMUX[29]PHASER_OUT[3].TESTIN[6]
CELL[29].IMUX_IMUX[30]PHASER_OUT[3].TESTIN[9]
CELL[29].IMUX_IMUX[31]PHASER_OUT[3].SCANIN
CELL[29].IMUX_IMUX[32]PHASER_IN[2].FINEENABLE
CELL[29].IMUX_IMUX[34]PHASER_IN[2].RANKSEL[0]
CELL[29].IMUX_IMUX[35]PHASER_OUT[3].SCANMODEB
CELL[29].IMUX_IMUX[37]PHASER_OUT[3].COUNTERLOADVAL[8]
CELL[29].IMUX_IMUX[41]PHASER_IN[2].EDGEADV
CELL[29].IMUX_IMUX[43]PHASER_OUT[3].TESTIN[1]
CELL[29].IMUX_IMUX[44]PHASER_OUT[3].TESTIN[4]
CELL[29].IMUX_IMUX[45]PHASER_OUT[3].TESTIN[7]
CELL[29].IMUX_IMUX[46]PHASER_OUT[3].TESTIN[10]
CELL[29].IMUX_IMUX[47]PHASER_OUT[3].SCANENB
CELL[29].OUT_BEL[2]PHASER_OUT[3].TESTOUT[1]
CELL[29].OUT_BEL[3]PHASER_OUT[3].COUNTERREADVAL[0]
CELL[29].OUT_BEL[6]PHASER_IN[2].STG1REGR[6]
CELL[29].OUT_BEL[7]PHASER_OUT[3].COUNTERREADVAL[2]
CELL[29].OUT_BEL[10]PHASER_IN[2].STG1REGR[5]
CELL[29].OUT_BEL[14]PHASER_OUT[3].TESTOUT[0]
CELL[29].OUT_BEL[15]PHASER_OUT[3].TESTOUT[2]
CELL[29].OUT_BEL[16]PHASER_IN[2].STG1OVERFLOW
CELL[29].OUT_BEL[17]PHASER_OUT[3].COUNTERREADVAL[3]
CELL[29].OUT_BEL[18]PHASER_IN[2].STG1REGR[3]
CELL[29].OUT_BEL[21]PHASER_OUT[3].COUNTERREADVAL[1]
CELL[29].OUT_BEL[23]PHASER_IN[2].STG1REGR[4]
CELL[30].IMUX_CLK[0]PHASER_OUT[3].SYSCLK
CELL[30].IMUX_CLK[1]PHASER_OUT[3].SCANCLK
CELL[30].IMUX_IMUX[0]PHASER_OUT[3].SELFINEOCLKDELAY
CELL[30].IMUX_IMUX[1]PHASER_OUT[3].COUNTERLOADVAL[0]
CELL[30].IMUX_IMUX[2]PHASER_OUT[3].COUNTERLOADVAL[4]
CELL[30].IMUX_IMUX[3]PHASER_OUT[3].COUNTERLOADVAL[7]
CELL[30].IMUX_IMUX[4]PHASER_IN[3].SCANIN
CELL[30].IMUX_IMUX[8]PHASER_OUT[3].TESTIN[13]
CELL[30].IMUX_IMUX[9]PHASER_OUT[3].COUNTERLOADVAL[1]
CELL[30].IMUX_IMUX[11]PHASER_OUT[3].COUNTERREADEN
CELL[30].IMUX_IMUX[13]PHASER_IN[3].STG1REGL[1]
CELL[30].IMUX_IMUX[14]PHASER_IN[3].STG1REGL[4]
CELL[30].IMUX_IMUX[15]PHASER_IN[3].STG1REGL[7]
CELL[30].IMUX_IMUX[17]PHASER_OUT[3].COUNTERLOADVAL[2]
CELL[30].IMUX_IMUX[18]PHASER_OUT[3].COUNTERLOADVAL[5]
CELL[30].IMUX_IMUX[20]PHASER_IN[3].SCANENB
CELL[30].IMUX_IMUX[24]PHASER_OUT[3].TESTIN[14]
CELL[30].IMUX_IMUX[27]PHASER_OUT[3].COUNTERLOADEN
CELL[30].IMUX_IMUX[29]PHASER_IN[3].STG1REGL[2]
CELL[30].IMUX_IMUX[30]PHASER_IN[3].STG1REGL[5]
CELL[30].IMUX_IMUX[31]PHASER_IN[3].STG1REGL[8]
CELL[30].IMUX_IMUX[32]PHASER_OUT[3].TESTIN[15]
CELL[30].IMUX_IMUX[34]PHASER_OUT[3].COUNTERLOADVAL[6]
CELL[30].IMUX_IMUX[41]PHASER_OUT[3].COUNTERLOADVAL[3]
CELL[30].IMUX_IMUX[43]PHASER_OUT[3].FINEINC
CELL[30].IMUX_IMUX[44]PHASER_IN[3].STG1REGL[0]
CELL[30].IMUX_IMUX[45]PHASER_IN[3].STG1REGL[3]
CELL[30].IMUX_IMUX[46]PHASER_IN[3].STG1REGL[6]
CELL[30].IMUX_IMUX[47]PHASER_IN[3].STG1READ
CELL[30].OUT_BEL[2]PHASER_OUT[3].COUNTERREADVAL[4]
CELL[30].OUT_BEL[3]PHASER_OUT[3].COUNTERREADVAL[6]
CELL[30].OUT_BEL[6]PHASER_OUT[3].COUNTERREADVAL[8]
CELL[30].OUT_BEL[7]PHASER_IN[3].TESTOUT[0]
CELL[30].OUT_BEL[10]PHASER_OUT[3].TESTOUT[3]
CELL[30].OUT_BEL[14]PHASER_OUT[3].COARSEOVERFLOW
CELL[30].OUT_BEL[15]PHASER_OUT[3].COUNTERREADVAL[5]
CELL[30].OUT_BEL[16]PHASER_OUT[3].OSERDESRST
CELL[30].OUT_BEL[17]PHASER_IN[3].TESTOUT[1]
CELL[30].OUT_BEL[18]PHASER_IN[2].STG1REGR[7]
CELL[30].OUT_BEL[21]PHASER_OUT[3].COUNTERREADVAL[7]
CELL[30].OUT_BEL[23]PHASER_IN[2].STG1REGR[8]
CELL[31].IMUX_IMUX[2]PHASER_OUT[3].BURSTPENDING
CELL[31].IMUX_IMUX[8]PHASER_OUT[3].FINEENABLE
CELL[31].IMUX_IMUX[9]PHASER_OUT[3].EDGEADV
CELL[31].IMUX_IMUX[11]PHASER_IN[3].TESTIN[0]
CELL[31].IMUX_IMUX[12]PHASER_IN[3].TESTIN[3]
CELL[31].IMUX_IMUX[14]PHASER_IN[3].COUNTERLOADEN
CELL[31].IMUX_IMUX[16]PHASER_OUT[3].COARSEINC
CELL[31].IMUX_IMUX[17]PHASER_OUT[3].ENCALIB[0]
CELL[31].IMUX_IMUX[19]PHASER_IN[3].DIVIDERST
CELL[31].IMUX_IMUX[20]PHASER_IN[3].TESTIN[4]
CELL[31].IMUX_IMUX[21]PHASER_IN[3].TESTIN[7]
CELL[31].IMUX_IMUX[27]PHASER_IN[3].TESTIN[1]
CELL[31].IMUX_IMUX[28]PHASER_IN[3].TESTIN[5]
CELL[31].IMUX_IMUX[29]PHASER_IN[3].TESTIN[8]
CELL[31].IMUX_IMUX[30]PHASER_IN[3].FINEINC
CELL[31].IMUX_IMUX[31]PHASER_IN[3].SCANMODEB
CELL[31].IMUX_IMUX[32]PHASER_OUT[3].COARSEENABLE
CELL[31].IMUX_IMUX[34]PHASER_OUT[3].RST
CELL[31].IMUX_IMUX[41]PHASER_OUT[3].ENCALIB[1]
CELL[31].IMUX_IMUX[43]PHASER_IN[3].TESTIN[2]
CELL[31].IMUX_IMUX[44]PHASER_IN[3].TESTIN[6]
CELL[31].IMUX_IMUX[45]PHASER_IN[3].COUNTERREADEN
CELL[31].IMUX_IMUX[46]PHASER_IN[3].FINEENABLE
CELL[31].OUT_BEL[0]PHASER_IN[3].TESTOUT[2]
CELL[31].OUT_BEL[1]PHASER_IN[3].SCANOUT
CELL[31].OUT_BEL[4]PHASER_OUT[3].SCANOUT
CELL[31].OUT_BEL[6]PHASER_IN[3].FINEOVERFLOW
CELL[31].OUT_BEL[9]PHASER_IN[3].DQSOUTOFRANGE
CELL[31].OUT_BEL[14]PHASER_OUT[2].DTSBUS[0]
CELL[31].OUT_BEL[15]PHASER_IN[3].COUNTERREADVAL[0]
CELL[31].OUT_BEL[17]PHASER_IN[3].PHASELOCKED
CELL[31].OUT_BEL[18]PHASER_OUT[3].FINEOVERFLOW
CELL[31].OUT_BEL[21]PHASER_IN[3].COUNTERREADVAL[1]
CELL[31].OUT_BEL[23]PHASER_OUT[2].DTSBUS[1]
CELL[31].PHASER_ICLKPHASER_IN[2].ICLK
CELL[31].PHASER_ICLKDIVPHASER_IN[2].ICLKDIV
CELL[31].PHASER_IWRENPHASER_IN[2].WRENABLE
CELL[31].PHASER_OCLKPHASER_OUT[2].OCLK
CELL[31].PHASER_OCLKDIVPHASER_OUT[2].OCLKDIV
CELL[31].PHASER_ORDENPHASER_OUT[2].RDENABLE
CELL[32].IMUX_IMUX[0]PHASER_IN[3].TESTIN[9]
CELL[32].IMUX_IMUX[2]PHASER_IN[3].BURSTPENDING
CELL[32].IMUX_IMUX[8]PHASER_IN[3].RSTDQSFIND
CELL[32].IMUX_IMUX[9]PHASER_IN[3].TESTIN[12]
CELL[32].IMUX_IMUX[11]PHASER_IN[3].STG1INCDEC
CELL[32].IMUX_IMUX[12]PHASER_IN[3].COUNTERLOADVAL[3]
CELL[32].IMUX_IMUX[14]PHASER_IN[3].EDGEADV
CELL[32].IMUX_IMUX[15]PHASER_IN[3].RANKSEL[0]
CELL[32].IMUX_IMUX[16]PHASER_IN[3].TESTIN[10]
CELL[32].IMUX_IMUX[18]PHASER_IN[3].STG1LOAD
CELL[32].IMUX_IMUX[19]PHASER_IN[3].COUNTERLOADVAL[0]
CELL[32].IMUX_IMUX[23]PHASER_IN[3].RANKSEL[1]
CELL[32].IMUX_IMUX[27]PHASER_IN[3].COUNTERLOADVAL[1]
CELL[32].IMUX_IMUX[28]PHASER_IN[3].COUNTERLOADVAL[4]
CELL[32].IMUX_IMUX[30]PHASER_IN[3].ENCALIB[0]
CELL[32].IMUX_IMUX[32]PHASER_IN[3].TESTIN[11]
CELL[32].IMUX_IMUX[33]PHASER_IN[3].TESTIN[13]
CELL[32].IMUX_IMUX[34]PHASER_IN[3].ENSTG1
CELL[32].IMUX_IMUX[39]PHASER_IN[3].RST
CELL[32].IMUX_IMUX[41]PHASER_IN[3].SELCALORSTG1
CELL[32].IMUX_IMUX[43]PHASER_IN[3].COUNTERLOADVAL[2]
CELL[32].IMUX_IMUX[44]PHASER_IN[3].COUNTERLOADVAL[5]
CELL[32].IMUX_IMUX[45]PHASER_IN[3].ENSTG1ADJUSTB
CELL[32].IMUX_IMUX[46]PHASER_IN[3].ENCALIB[1]
CELL[32].OUT_BEL[0]PHASER_OUT[2].DQSBUS[0]
CELL[32].OUT_BEL[1]PHASER_IN[3].COUNTERREADVAL[3]
CELL[32].OUT_BEL[4]PHASER_IN[3].TESTOUT[3]
CELL[32].OUT_BEL[5]PHASER_OUT[2].DQSBUS[1]
CELL[32].OUT_BEL[6]PHASER_IN[3].COUNTERREADVAL[5]
CELL[32].OUT_BEL[9]PHASER_IN[3].COUNTERREADVAL[4]
CELL[32].OUT_BEL[14]PHASER_OUT[2].CTSBUS[0]
CELL[32].OUT_BEL[17]PHASER_IN[3].STG1OVERFLOW
CELL[32].OUT_BEL[18]PHASER_IN[3].COUNTERREADVAL[2]
CELL[32].OUT_BEL[23]PHASER_OUT[2].CTSBUS[1]
CELL[33].IMUX_CLK[0]PHASER_IN[3].SYSCLK
CELL[33].IMUX_CLK[1]PHASER_IN[3].SCANCLK
CELL[33].OUT_BEL[2]PHASER_IN[3].STG1REGR[4]
CELL[33].OUT_BEL[3]PHASER_IN[3].STG1REGR[6]
CELL[33].OUT_BEL[6]PHASER_IN[3].STG1REGR[1]
CELL[33].OUT_BEL[7]PHASER_IN[3].STG1REGR[8]
CELL[33].OUT_BEL[10]PHASER_IN[3].STG1REGR[0]
CELL[33].OUT_BEL[14]PHASER_IN[3].STG1REGR[3]
CELL[33].OUT_BEL[15]PHASER_IN[3].STG1REGR[5]
CELL[33].OUT_BEL[16]PHASER_IN[3].STG1REGR[2]
CELL[33].OUT_BEL[17]PHY_CONTROL.PHYCTLREADY
CELL[33].OUT_BEL[18]PHASER_IN[3].ISERDESRST
CELL[33].OUT_BEL[21]PHASER_IN[3].STG1REGR[7]
CELL[33].OUT_BEL[23]PHASER_IN[3].DQSFOUND
CELL[34].IMUX_IMUX[1]PHY_CONTROL.TESTINPUT[3]
CELL[34].IMUX_IMUX[2]PHY_CONTROL.TESTINPUT[6]
CELL[34].IMUX_IMUX[3]PHY_CONTROL.TESTINPUT[9]
CELL[34].IMUX_IMUX[4]PHY_CONTROL.PHYCTLWD[0]
CELL[34].IMUX_IMUX[8]PHY_CONTROL.TESTINPUT[0]
CELL[34].IMUX_IMUX[9]PHY_CONTROL.TESTINPUT[4]
CELL[34].IMUX_IMUX[11]PHY_CONTROL.TESTINPUT[10]
CELL[34].IMUX_IMUX[13]PHY_CONTROL.PHYCTLWD[3]
CELL[34].IMUX_IMUX[14]PHY_CONTROL.PHYCTLWD[5]
CELL[34].IMUX_IMUX[15]PHY_CONTROL.PHYCTLWD[8]
CELL[34].IMUX_IMUX[18]PHY_CONTROL.TESTINPUT[7]
CELL[34].IMUX_IMUX[20]PHY_CONTROL.PHYCTLWD[1]
CELL[34].IMUX_IMUX[24]PHY_CONTROL.TESTINPUT[1]
CELL[34].IMUX_IMUX[27]PHY_CONTROL.TESTINPUT[11]
CELL[34].IMUX_IMUX[30]PHY_CONTROL.PHYCTLWD[6]
CELL[34].IMUX_IMUX[31]PHY_CONTROL.PHYCTLWD[9]
CELL[34].IMUX_IMUX[32]PHY_CONTROL.TESTINPUT[2]
CELL[34].IMUX_IMUX[34]PHY_CONTROL.TESTINPUT[8]
CELL[34].IMUX_IMUX[41]PHY_CONTROL.TESTINPUT[5]
CELL[34].IMUX_IMUX[43]PHY_CONTROL.PLLLOCK
CELL[34].IMUX_IMUX[44]PHY_CONTROL.PHYCTLWD[2]
CELL[34].IMUX_IMUX[45]PHY_CONTROL.PHYCTLWD[4]
CELL[34].IMUX_IMUX[46]PHY_CONTROL.PHYCTLWD[7]
CELL[34].IMUX_IMUX[47]PHY_CONTROL.PHYCTLWD[10]
CELL[34].OUT_BEL[2]PHY_CONTROL.TESTOUTPUT[6]
CELL[34].OUT_BEL[3]PHY_CONTROL.AUXOUTPUT[0]
CELL[34].OUT_BEL[6]PHY_CONTROL.TESTOUTPUT[3]
CELL[34].OUT_BEL[7]PHY_CONTROL.PHYCTLALMOSTFULL
CELL[34].OUT_BEL[10]PHY_CONTROL.TESTOUTPUT[2]
CELL[34].OUT_BEL[14]PHY_CONTROL.TESTOUTPUT[5]
CELL[34].OUT_BEL[15]PHY_CONTROL.TESTOUTPUT[7]
CELL[34].OUT_BEL[16]PHY_CONTROL.TESTOUTPUT[4]
CELL[34].OUT_BEL[17]PHY_CONTROL.PHYCTLFULL
CELL[34].OUT_BEL[18]PHY_CONTROL.TESTOUTPUT[0]
CELL[34].OUT_BEL[21]PHY_CONTROL.AUXOUTPUT[1]
CELL[34].OUT_BEL[23]PHY_CONTROL.TESTOUTPUT[1]
CELL[35].IMUX_CLK[0]PHY_CONTROL.PHYCLK
CELL[35].IMUX_IMUX[2]PHY_CONTROL.TESTSELECT[1]
CELL[35].IMUX_IMUX[3]PHY_CONTROL.TESTINPUT[12]
CELL[35].IMUX_IMUX[4]PHY_CONTROL.REFDLLLOCK
CELL[35].IMUX_IMUX[9]PHY_CONTROL.SCANENABLEN
CELL[35].IMUX_IMUX[11]PHY_CONTROL.TESTINPUT[13]
CELL[35].IMUX_IMUX[13]PHY_CONTROL.PHYCTLWD[13]
CELL[35].IMUX_IMUX[14]PHY_CONTROL.PHYCTLWD[15]
CELL[35].IMUX_IMUX[15]PHY_CONTROL.PHYCTLWD[18]
CELL[35].IMUX_IMUX[18]PHY_CONTROL.TESTSELECT[2]
CELL[35].IMUX_IMUX[20]PHY_CONTROL.PHYCTLWD[11]
CELL[35].IMUX_IMUX[22]PHY_CONTROL.WRITECALIBENABLE
CELL[35].IMUX_IMUX[27]PHY_CONTROL.TESTINPUT[14]
CELL[35].IMUX_IMUX[29]PHY_CONTROL.READCALIBENABLE
CELL[35].IMUX_IMUX[30]PHY_CONTROL.PHYCTLWD[16]
CELL[35].IMUX_IMUX[31]PHY_CONTROL.PHYCTLWD[19]
CELL[35].IMUX_IMUX[41]PHY_CONTROL.TESTSELECT[0]
CELL[35].IMUX_IMUX[43]PHY_CONTROL.TESTINPUT[15]
CELL[35].IMUX_IMUX[44]PHY_CONTROL.PHYCTLWD[12]
CELL[35].IMUX_IMUX[45]PHY_CONTROL.PHYCTLWD[14]
CELL[35].IMUX_IMUX[46]PHY_CONTROL.PHYCTLWD[17]
CELL[35].IMUX_IMUX[47]PHY_CONTROL.PHYCTLWD[20]
CELL[35].OUT_BEL[2]PHY_CONTROL.TESTOUTPUT[11]
CELL[35].OUT_BEL[3]PHY_CONTROL.TESTOUTPUT[13]
CELL[35].OUT_BEL[6]PHY_CONTROL.TESTOUTPUT[8]
CELL[35].OUT_BEL[7]PHY_CONTROL.TESTOUTPUT[15]
CELL[35].OUT_BEL[14]PHY_CONTROL.TESTOUTPUT[10]
CELL[35].OUT_BEL[15]PHY_CONTROL.TESTOUTPUT[12]
CELL[35].OUT_BEL[16]PHY_CONTROL.TESTOUTPUT[9]
CELL[35].OUT_BEL[17]PHY_CONTROL.AUXOUTPUT[2]
CELL[35].OUT_BEL[21]PHY_CONTROL.TESTOUTPUT[14]
CELL[36].IMUX_IMUX[4]PHY_CONTROL.PHYCTLWD[22]
CELL[36].IMUX_IMUX[11]PHY_CONTROL.RESET
CELL[36].IMUX_IMUX[13]PHY_CONTROL.PHYCTLWD[25]
CELL[36].IMUX_IMUX[14]PHY_CONTROL.PHYCTLWD[27]
CELL[36].IMUX_IMUX[15]PHY_CONTROL.PHYCTLWD[30]
CELL[36].IMUX_IMUX[20]PHY_CONTROL.PHYCTLWD[23]
CELL[36].IMUX_IMUX[30]PHY_CONTROL.PHYCTLWD[28]
CELL[36].IMUX_IMUX[31]PHY_CONTROL.PHYCTLWD[31]
CELL[36].IMUX_IMUX[43]PHY_CONTROL.PHYCTLWD[21]
CELL[36].IMUX_IMUX[44]PHY_CONTROL.PHYCTLWD[24]
CELL[36].IMUX_IMUX[45]PHY_CONTROL.PHYCTLWD[26]
CELL[36].IMUX_IMUX[46]PHY_CONTROL.PHYCTLWD[29]
CELL[36].IMUX_IMUX[47]PHY_CONTROL.PHYCTLWRENABLE
CELL[36].OUT_BEL[17]PHY_CONTROL.AUXOUTPUT[3]
CELL[39].OUT_BEL[2]PLL[1].TESTOUT[60]
CELL[39].OUT_BEL[7]PLL[1].TESTOUT[57]
CELL[39].OUT_BEL[10]PLL[1].TESTOUT[61]
CELL[39].OUT_BEL[15]PLL[1].TESTOUT[59]
CELL[39].OUT_BEL[17]PLL[1].TESTOUT[56]
CELL[39].OUT_BEL[18]PLL[1].TESTOUT[63]
CELL[39].OUT_BEL[21]PLL[1].TESTOUT[58]
CELL[39].OUT_BEL[23]PLL[1].TESTOUT[62]
CELL[40].OUT_BEL[2]PLL[1].TESTOUT[52]
CELL[40].OUT_BEL[7]PLL[1].TESTOUT[49]
CELL[40].OUT_BEL[10]PLL[1].TESTOUT[53]
CELL[40].OUT_BEL[15]PLL[1].TESTOUT[51]
CELL[40].OUT_BEL[17]PLL[1].TESTOUT[48]
CELL[40].OUT_BEL[18]PLL[1].TESTOUT[55]
CELL[40].OUT_BEL[21]PLL[1].TESTOUT[50]
CELL[40].OUT_BEL[23]PLL[1].TESTOUT[54]
CELL[41].OUT_BEL[2]PLL[1].TESTOUT[44]
CELL[41].OUT_BEL[7]PLL[1].TESTOUT[41]
CELL[41].OUT_BEL[10]PLL[1].TESTOUT[45]
CELL[41].OUT_BEL[15]PLL[1].TESTOUT[43]
CELL[41].OUT_BEL[17]PLL[1].TESTOUT[40]
CELL[41].OUT_BEL[18]PLL[1].TESTOUT[47]
CELL[41].OUT_BEL[21]PLL[1].TESTOUT[42]
CELL[41].OUT_BEL[23]PLL[1].TESTOUT[46]
CELL[42].OUT_BEL[2]PLL[1].TESTOUT[36]
CELL[42].OUT_BEL[7]PLL[1].TESTOUT[33]
CELL[42].OUT_BEL[10]PLL[1].TESTOUT[37]
CELL[42].OUT_BEL[15]PLL[1].TESTOUT[35]
CELL[42].OUT_BEL[17]PLL[1].TESTOUT[32]
CELL[42].OUT_BEL[18]PLL[1].TESTOUT[39]
CELL[42].OUT_BEL[21]PLL[1].TESTOUT[34]
CELL[42].OUT_BEL[23]PLL[1].TESTOUT[38]
CELL[43].IMUX_IMUX[11]PLL[1].TESTIN[29]
CELL[43].IMUX_IMUX[15]PLL[1].TESTIN[24]
CELL[43].IMUX_IMUX[16]PLL[1].TESTIN[31]
CELL[43].IMUX_IMUX[30]PLL[1].TESTIN[25]
CELL[43].IMUX_IMUX[41]PLL[1].TESTIN[30]
CELL[43].IMUX_IMUX[43]PLL[1].TESTIN[28]
CELL[43].IMUX_IMUX[44]PLL[1].TESTIN[27]
CELL[43].IMUX_IMUX[45]PLL[1].TESTIN[26]
CELL[43].OUT_BEL[1]PLL[1].TESTOUT[30]
CELL[43].OUT_BEL[6]PLL[1].TESTOUT[28]
CELL[43].OUT_BEL[9]PLL[1].TESTOUT[29]
CELL[43].OUT_BEL[14]PHASER_OUT[3].DTSBUS[0]
CELL[43].OUT_BEL[15]PLL[1].TESTOUT[26]
CELL[43].OUT_BEL[16]PLL[1].TESTOUT[27]
CELL[43].OUT_BEL[17]PLL[1].TESTOUT[24]
CELL[43].OUT_BEL[18]PLL[1].TESTOUT[31]
CELL[43].OUT_BEL[21]PLL[1].TESTOUT[25]
CELL[43].OUT_BEL[23]PHASER_OUT[3].DTSBUS[1]
CELL[43].PHASER_ICLKPHASER_IN[3].ICLK
CELL[43].PHASER_ICLKDIVPHASER_IN[3].ICLKDIV
CELL[43].PHASER_IWRENPHASER_IN[3].WRENABLE
CELL[43].PHASER_OCLKPHASER_OUT[3].OCLK
CELL[43].PHASER_OCLKDIVPHASER_OUT[3].OCLKDIV
CELL[43].PHASER_ORDENPHASER_OUT[3].RDENABLE
CELL[44].IMUX_IMUX[11]PLL[1].TESTIN[21]
CELL[44].IMUX_IMUX[15]PLL[1].TESTIN[16]
CELL[44].IMUX_IMUX[16]PLL[1].TESTIN[23]
CELL[44].IMUX_IMUX[30]PLL[1].TESTIN[17]
CELL[44].IMUX_IMUX[41]PLL[1].TESTIN[22]
CELL[44].IMUX_IMUX[43]PLL[1].TESTIN[20]
CELL[44].IMUX_IMUX[44]PLL[1].TESTIN[19]
CELL[44].IMUX_IMUX[45]PLL[1].TESTIN[18]
CELL[44].OUT_BEL[0]PHASER_OUT[3].DQSBUS[0]
CELL[44].OUT_BEL[1]PLL[1].TESTOUT[21]
CELL[44].OUT_BEL[4]PLL[1].TESTOUT[23]
CELL[44].OUT_BEL[5]PHASER_OUT[3].DQSBUS[1]
CELL[44].OUT_BEL[6]PLL[1].TESTOUT[19]
CELL[44].OUT_BEL[9]PLL[1].TESTOUT[20]
CELL[44].OUT_BEL[14]PHASER_OUT[3].CTSBUS[0]
CELL[44].OUT_BEL[15]PLL[1].TESTOUT[17]
CELL[44].OUT_BEL[16]PLL[1].TESTOUT[18]
CELL[44].OUT_BEL[17]PLL[1].TESTOUT[16]
CELL[44].OUT_BEL[18]PLL[1].TESTOUT[22]
CELL[44].OUT_BEL[23]PHASER_OUT[3].CTSBUS[1]
CELL[45].IMUX_IMUX[3]PLL[1].TESTIN[13]
CELL[45].IMUX_IMUX[15]PLL[1].TESTIN[8]
CELL[45].IMUX_IMUX[16]PLL[1].TESTIN[15]
CELL[45].IMUX_IMUX[30]PLL[1].TESTIN[9]
CELL[45].IMUX_IMUX[41]PLL[1].TESTIN[14]
CELL[45].IMUX_IMUX[43]PLL[1].TESTIN[12]
CELL[45].IMUX_IMUX[44]PLL[1].TESTIN[11]
CELL[45].IMUX_IMUX[45]PLL[1].TESTIN[10]
CELL[45].OUT_BEL[2]PLL[1].TESTOUT[11]
CELL[45].OUT_BEL[7]PLL[1].TESTOUT[9]
CELL[45].OUT_BEL[10]PLL[1].TESTOUT[13]
CELL[45].OUT_BEL[15]PLL[1].TESTOUT[10]
CELL[45].OUT_BEL[16]PLL[1].TESTOUT[12]
CELL[45].OUT_BEL[17]PLL[1].TESTOUT[8]
CELL[45].OUT_BEL[18]PLL[1].TESTOUT[15]
CELL[45].OUT_BEL[23]PLL[1].TESTOUT[14]
CELL[46].IMUX_IMUX[3]PLL[1].TESTIN[5]
CELL[46].IMUX_IMUX[15]PLL[1].TESTIN[0]
CELL[46].IMUX_IMUX[16]PLL[1].TESTIN[7]
CELL[46].IMUX_IMUX[30]PLL[1].TESTIN[1]
CELL[46].IMUX_IMUX[41]PLL[1].TESTIN[6]
CELL[46].IMUX_IMUX[43]PLL[1].TESTIN[4]
CELL[46].IMUX_IMUX[44]PLL[1].TESTIN[3]
CELL[46].IMUX_IMUX[45]PLL[1].TESTIN[2]
CELL[46].OUT_BEL[2]PLL[1].TESTOUT[4]
CELL[46].OUT_BEL[7]PLL[1].TESTOUT[1]
CELL[46].OUT_BEL[10]PLL[1].TESTOUT[5]
CELL[46].OUT_BEL[15]PLL[1].TESTOUT[3]
CELL[46].OUT_BEL[17]PLL[1].TESTOUT[0]
CELL[46].OUT_BEL[18]PLL[1].TESTOUT[7]
CELL[46].OUT_BEL[21]PLL[1].TESTOUT[2]
CELL[46].OUT_BEL[23]PLL[1].TESTOUT[6]
CELL[47].IMUX_IMUX[13]PLL[1].RST
CELL[47].IMUX_IMUX[47]PLL[1].CLKINSEL
CELL[48].IMUX_IMUX[0]PLL[1].PWRDWN
CELL[48].IMUX_IMUX[1]PLL[1].DEN
CELL[48].IMUX_IMUX[2]PLL[1].DWE
CELL[48].IMUX_IMUX[3]PLL[1].DADDR[6]
CELL[48].IMUX_IMUX[13]PLL[1].DADDR[3]
CELL[48].IMUX_IMUX[15]PLL[1].DADDR[1]
CELL[48].IMUX_IMUX[22]PLL[1].DADDR[2]
CELL[48].IMUX_IMUX[35]PLL[1].DADDR[5]
CELL[48].IMUX_IMUX[44]PLL[1].DADDR[4]
CELL[48].IMUX_IMUX[47]PLL[1].DADDR[0]
CELL[48].OUT_BEL[16]PLL[1].DRDY
CELL[48].OUT_BEL[21]PLL[1].LOCKED
CELL[49].IMUX_CLK[0]PLL[1].DCLK
CELL[49].IMUX_IMUX[0]PLL[1].DI[15]
CELL[49].IMUX_IMUX[1]PLL[1].DI[13]
CELL[49].IMUX_IMUX[2]PLL[1].DI[11]
CELL[49].IMUX_IMUX[3]PLL[1].DI[9]
CELL[49].IMUX_IMUX[4]PLL[1].DI[7]
CELL[49].IMUX_IMUX[5]PLL[1].DI[5]
CELL[49].IMUX_IMUX[6]PLL[1].DI[3]
CELL[49].IMUX_IMUX[7]PLL[1].DI[1]
CELL[49].IMUX_IMUX[32]PLL[1].DI[14]
CELL[49].IMUX_IMUX[33]PLL[1].DI[12]
CELL[49].IMUX_IMUX[34]PLL[1].DI[10]
CELL[49].IMUX_IMUX[35]PLL[1].DI[8]
CELL[49].IMUX_IMUX[36]PLL[1].DI[6]
CELL[49].IMUX_IMUX[37]PLL[1].DI[4]
CELL[49].IMUX_IMUX[38]PLL[1].DI[2]
CELL[49].IMUX_IMUX[39]PLL[1].DI[0]
CELL[49].OUT_BEL[0]PLL[1].DO[13]
CELL[49].OUT_BEL[2]PLL[1].DO[5]
CELL[49].OUT_BEL[5]PLL[1].DO[9]
CELL[49].OUT_BEL[7]PLL[1].DO[1]
CELL[49].OUT_BEL[8]PLL[1].DO[15]
CELL[49].OUT_BEL[10]PLL[1].DO[7]
CELL[49].OUT_BEL[13]PLL[1].DO[11]
CELL[49].OUT_BEL[15]PLL[1].DO[3]
CELL[49].OUT_BEL[16]PLL[1].DO[6]
CELL[49].OUT_BEL[17]PLL[1].DO[0]
CELL[49].OUT_BEL[18]PLL[1].DO[14]
CELL[49].OUT_BEL[19]PLL[1].DO[8]
CELL[49].OUT_BEL[20]PLL[1].DO[4]
CELL[49].OUT_BEL[21]PLL[1].DO[2]
CELL[49].OUT_BEL[22]PLL[1].DO[12]
CELL[49].OUT_BEL[23]PLL[1].DO[10]
IO[8].PHASER_OCLK90PHASER_OUT[0].OCLKDELAYED
IO[20].PHASER_OCLK90PHASER_OUT[1].OCLKDELAYED
IO[32].PHASER_OCLK90PHASER_OUT[2].OCLKDELAYED
IO[44].PHASER_OCLK90PHASER_OUT[3].OCLKDELAYED

Bitstream

virtex7 CMT rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 1 PLL[0]: CONTROL_2 bit 1 PLL[0]: MMCM_DRP[120] bit 0 PLL[0]: CONTROL_2 bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 3 PLL[0]: CONTROL_2 bit 3 PLL[0]: MMCM_DRP[120] bit 2 PLL[0]: CONTROL_2 bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 5 PLL[0]: CONTROL_2 bit 5 PLL[0]: MMCM_DRP[120] bit 4 PLL[0]: CONTROL_2 bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 7 PLL[0]: CONTROL_2 bit 7 PLL[0]: MMCM_DRP[120] bit 6 PLL[0]: CONTROL_2 bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 9 PLL[0]: CONTROL_2 bit 9 PLL[0]: MMCM_DRP[120] bit 8 PLL[0]: CONTROL_2 bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 11 PLL[0]: CONTROL_2 bit 11 PLL[0]: MMCM_DRP[120] bit 10 PLL[0]: CONTROL_2 bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 13 PLL[0]: CONTROL_2 bit 13 PLL[0]: MMCM_DRP[120] bit 12 PLL[0]: CONTROL_2 bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 15 PLL[0]: CONTROL_2 bit 15 PLL[0]: MMCM_DRP[120] bit 14 PLL[0]: CONTROL_2 bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 1 PLL[0]: CONTROL_3 bit 1 PLL[0]: MMCM_DRP[121] bit 0 PLL[0]: CONTROL_3 bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 3 PLL[0]: CONTROL_3 bit 3 PLL[0]: MMCM_DRP[121] bit 2 PLL[0]: CONTROL_3 bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 5 PLL[0]: CONTROL_3 bit 5 PLL[0]: MMCM_DRP[121] bit 4 PLL[0]: CONTROL_3 bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 7 PLL[0]: CONTROL_3 bit 7 PLL[0]: MMCM_DRP[121] bit 6 PLL[0]: CONTROL_3 bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 9 PLL[0]: CONTROL_3 bit 9 PLL[0]: MMCM_DRP[121] bit 8 PLL[0]: CONTROL_3 bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 11 PLL[0]: CONTROL_3 bit 11 PLL[0]: MMCM_DRP[121] bit 10 PLL[0]: CONTROL_3 bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 13 PLL[0]: CONTROL_3 bit 13 PLL[0]: MMCM_DRP[121] bit 12 PLL[0]: CONTROL_3 bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 15 PLL[0]: CONTROL_3 bit 15 PLL[0]: MMCM_DRP[121] bit 14 PLL[0]: CONTROL_3 bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 1 PLL[0]: CONTROL_4 bit 1 PLL[0]: MMCM_DRP[122] bit 0 PLL[0]: CONTROL_4 bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 3 PLL[0]: CONTROL_4 bit 3 PLL[0]: MMCM_DRP[122] bit 2 PLL[0]: CONTROL_4 bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 5 PLL[0]: CONTROL_4 bit 5 PLL[0]: MMCM_DRP[122] bit 4 PLL[0]: CONTROL_4 bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 7 PLL[0]: CONTROL_4 bit 7 PLL[0]: MMCM_DRP[122] bit 6 PLL[0]: CONTROL_4 bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 9 PLL[0]: CONTROL_4 bit 9 PLL[0]: MMCM_DRP[122] bit 8 PLL[0]: CONTROL_4 bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 11 PLL[0]: CONTROL_4 bit 11 PLL[0]: MMCM_DRP[122] bit 10 PLL[0]: CONTROL_4 bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 13 PLL[0]: CONTROL_4 bit 13 PLL[0]: MMCM_DRP[122] bit 12 PLL[0]: CONTROL_4 bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 15 PLL[0]: CONTROL_4 bit 15 PLL[0]: MMCM_DRP[122] bit 14 PLL[0]: CONTROL_4 bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 1 PLL[0]: CONTROL_5 bit 1 PLL[0]: MMCM_DRP[123] bit 0 PLL[0]: CONTROL_5 bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 3 PLL[0]: CONTROL_5 bit 3 PLL[0]: MMCM_DRP[123] bit 2 PLL[0]: CONTROL_5 bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 5 PLL[0]: CONTROL_5 bit 5 PLL[0]: MMCM_DRP[123] bit 4 PLL[0]: CONTROL_5 bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 7 PLL[0]: CONTROL_5 bit 7 PLL[0]: MMCM_DRP[123] bit 6 PLL[0]: CONTROL_5 bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 9 PLL[0]: CONTROL_5 bit 9 PLL[0]: MMCM_DRP[123] bit 8 PLL[0]: CONTROL_5 bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 11 PLL[0]: CONTROL_5 bit 11 PLL[0]: MMCM_DRP[123] bit 10 PLL[0]: CONTROL_5 bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 13 PLL[0]: CONTROL_5 bit 13 PLL[0]: MMCM_DRP[123] bit 12 PLL[0]: CONTROL_5 bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 15 PLL[0]: CONTROL_5 bit 15 PLL[0]: MMCM_DRP[123] bit 14 PLL[0]: CONTROL_5 bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 1 PLL[0]: CONTROL_6 bit 1 PLL[0]: MMCM_DRP[124] bit 0 PLL[0]: CONTROL_6 bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 3 PLL[0]: CONTROL_6 bit 3 PLL[0]: MMCM_DRP[124] bit 2 PLL[0]: CONTROL_6 bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 5 PLL[0]: CONTROL_6 bit 5 PLL[0]: MMCM_DRP[124] bit 4 PLL[0]: CONTROL_6 bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 7 PLL[0]: CONTROL_6 bit 7 PLL[0]: MMCM_DRP[124] bit 6 PLL[0]: CONTROL_6 bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 9 PLL[0]: CONTROL_6 bit 9 PLL[0]: MMCM_DRP[124] bit 8 PLL[0]: CONTROL_6 bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 11 PLL[0]: CONTROL_6 bit 11 PLL[0]: MMCM_DRP[124] bit 10 PLL[0]: CONTROL_6 bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 13 PLL[0]: CONTROL_6 bit 13 PLL[0]: MMCM_DRP[124] bit 12 PLL[0]: CONTROL_6 bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 15 PLL[0]: CONTROL_6 bit 15 PLL[0]: MMCM_DRP[124] bit 14 PLL[0]: CONTROL_6 bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 1 PLL[0]: CONTROL_7 bit 1 PLL[0]: MMCM_DRP[125] bit 0 PLL[0]: CONTROL_7 bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 3 PLL[0]: CONTROL_7 bit 3 PLL[0]: MMCM_DRP[125] bit 2 PLL[0]: CONTROL_7 bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 5 PLL[0]: CONTROL_7 bit 5 PLL[0]: MMCM_DRP[125] bit 4 PLL[0]: CONTROL_7 bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 7 PLL[0]: CONTROL_7 bit 7 PLL[0]: MMCM_DRP[125] bit 6 PLL[0]: CONTROL_7 bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 9 PLL[0]: CONTROL_7 bit 9 PLL[0]: MMCM_DRP[125] bit 8 PLL[0]: CONTROL_7 bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 11 PLL[0]: CONTROL_7 bit 11 PLL[0]: MMCM_DRP[125] bit 10 PLL[0]: CONTROL_7 bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 13 PLL[0]: CONTROL_7 bit 13 PLL[0]: MMCM_DRP[125] bit 12 PLL[0]: CONTROL_7 bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 15 PLL[0]: CONTROL_7 bit 15 PLL[0]: MMCM_DRP[125] bit 14 PLL[0]: CONTROL_7 bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 1 PLL[0]: MMCM_DRP[126] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 3 PLL[0]: MMCM_DRP[126] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 5 PLL[0]: MMCM_DRP[126] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 7 PLL[0]: MMCM_DRP[126] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 9 PLL[0]: MMCM_DRP[126] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 11 PLL[0]: MMCM_DRP[126] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 13 PLL[0]: MMCM_DRP[126] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 15 PLL[0]: MMCM_DRP[126] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 1 PLL[0]: MMCM_DRP[127] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 3 PLL[0]: MMCM_DRP[127] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 5 PLL[0]: MMCM_DRP[127] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 7 PLL[0]: MMCM_DRP[127] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 9 PLL[0]: MMCM_DRP[127] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 11 PLL[0]: MMCM_DRP[127] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 13 PLL[0]: MMCM_DRP[127] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 15 PLL[0]: MMCM_DRP[127] bit 14
virtex7 CMT rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 1 PLL[0]: MMCM_DRP[112] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 3 PLL[0]: MMCM_DRP[112] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 5 PLL[0]: MMCM_DRP[112] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 7 PLL[0]: MMCM_DRP[112] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 9 PLL[0]: MMCM_DRP[112] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 11 PLL[0]: MMCM_DRP[112] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 13 PLL[0]: MMCM_DRP[112] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 15 PLL[0]: MMCM_DRP[112] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 1 PLL[0]: MMCM_DRP[113] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 3 PLL[0]: MMCM_DRP[113] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 5 PLL[0]: MMCM_DRP[113] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 7 PLL[0]: MMCM_DRP[113] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 9 PLL[0]: MMCM_DRP[113] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 11 PLL[0]: MMCM_DRP[113] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 13 PLL[0]: MMCM_DRP[113] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 15 PLL[0]: MMCM_DRP[113] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: invert PWRDWN PLL[0]: MMCM_DRP[114] bit 1 PLL[0]: invert RST PLL[0]: MMCM_DRP[114] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: invert PSEN PLL[0]: MMCM_DRP[114] bit 3 PLL[0]: invert PSINCDEC PLL[0]: MMCM_DRP[114] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 5 PLL[0]: invert CLKINSEL PLL[0]: MMCM_DRP[114] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 7 PLL[0]: MMCM_DRP[114] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 9 PLL[0]: MMCM_DRP[114] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 11 PLL[0]: MMCM_DRP[114] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 13 PLL[0]: MMCM_DRP[114] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 15 PLL[0]: MMCM_DRP[114] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 1 PLL[0]: MMCM_DRP[115] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 3 PLL[0]: MMCM_DRP[115] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 5 PLL[0]: MMCM_DRP[115] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 7 PLL[0]: MMCM_DRP[115] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 9 PLL[0]: MMCM_DRP[115] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 11 PLL[0]: MMCM_DRP[115] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 13 PLL[0]: MMCM_DRP[115] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 15 PLL[0]: MMCM_DRP[115] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 1 PLL[0]: SS_EN PLL[0]: MMCM_DRP[116] bit 0 PLL[0]: ENABLE
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 3 PLL[0]: GTS_WAIT PLL[0]: MMCM_DRP[116] bit 2 PLL[0]: STARTUP_WAIT
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 5 PLL[0]: FINE_PS_FRAC bit 0 PLL[0]: MMCM_DRP[116] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 7 PLL[0]: FINE_PS_FRAC bit 2 PLL[0]: MMCM_DRP[116] bit 6 PLL[0]: FINE_PS_FRAC bit 1
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 9 PLL[0]: FINE_PS_FRAC bit 4 PLL[0]: MMCM_DRP[116] bit 8 PLL[0]: FINE_PS_FRAC bit 3
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 11 PLL[0]: MMCM_DRP[116] bit 10 PLL[0]: FINE_PS_FRAC bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 13 PLL[0]: MMCM_DRP[116] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 15 PLL[0]: MMCM_DRP[116] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 1 PLL[0]: MMCM_DRP[117] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 3 PLL[0]: MMCM_DRP[117] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 5 PLL[0]: MMCM_DRP[117] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 7 PLL[0]: MMCM_DRP[117] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 9 PLL[0]: MMCM_DRP[117] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 11 PLL[0]: MMCM_DRP[117] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 13 PLL[0]: MMCM_DRP[117] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 15 PLL[0]: MMCM_DRP[117] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 1 PLL[0]: CONTROL_0 bit 1 PLL[0]: MMCM_DRP[118] bit 0 PLL[0]: CONTROL_0 bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 3 PLL[0]: CONTROL_0 bit 3 PLL[0]: MMCM_DRP[118] bit 2 PLL[0]: CONTROL_0 bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 5 PLL[0]: CONTROL_0 bit 5 PLL[0]: MMCM_DRP[118] bit 4 PLL[0]: CONTROL_0 bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 7 PLL[0]: CONTROL_0 bit 7 PLL[0]: MMCM_DRP[118] bit 6 PLL[0]: CONTROL_0 bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 9 PLL[0]: CONTROL_0 bit 9 PLL[0]: MMCM_DRP[118] bit 8 PLL[0]: CONTROL_0 bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 11 PLL[0]: CONTROL_0 bit 11 PLL[0]: MMCM_DRP[118] bit 10 PLL[0]: CONTROL_0 bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 13 PLL[0]: CONTROL_0 bit 13 PLL[0]: MMCM_DRP[118] bit 12 PLL[0]: CONTROL_0 bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 15 PLL[0]: CONTROL_0 bit 15 PLL[0]: MMCM_DRP[118] bit 14 PLL[0]: CONTROL_0 bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 1 PLL[0]: CONTROL_1 bit 1 PLL[0]: MMCM_DRP[119] bit 0 PLL[0]: CONTROL_1 bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 3 PLL[0]: CONTROL_1 bit 3 PLL[0]: MMCM_DRP[119] bit 2 PLL[0]: CONTROL_1 bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 5 PLL[0]: CONTROL_1 bit 5 PLL[0]: MMCM_DRP[119] bit 4 PLL[0]: CONTROL_1 bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 7 PLL[0]: CONTROL_1 bit 7 PLL[0]: MMCM_DRP[119] bit 6 PLL[0]: CONTROL_1 bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 9 PLL[0]: CONTROL_1 bit 9 PLL[0]: MMCM_DRP[119] bit 8 PLL[0]: CONTROL_1 bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 11 PLL[0]: CONTROL_1 bit 11 PLL[0]: MMCM_DRP[119] bit 10 PLL[0]: CONTROL_1 bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 13 PLL[0]: CONTROL_1 bit 13 PLL[0]: MMCM_DRP[119] bit 12 PLL[0]: CONTROL_1 bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 15 PLL[0]: CONTROL_1 bit 15 PLL[0]: MMCM_DRP[119] bit 14 PLL[0]: CONTROL_1 bit 14
virtex7 CMT rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 1 PLL[0]: MMCM_DRP[104] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 3 PLL[0]: MMCM_DRP[104] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 5 PLL[0]: MMCM_DRP[104] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 7 PLL[0]: MMCM_DRP[104] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 9 PLL[0]: MMCM_DRP[104] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 11 PLL[0]: MMCM_DRP[104] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 13 PLL[0]: MMCM_DRP[104] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 15 PLL[0]: MMCM_DRP[104] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 1 PLL[0]: MMCM_DRP[105] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 3 PLL[0]: MMCM_DRP[105] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 5 PLL[0]: MMCM_DRP[105] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 7 PLL[0]: MMCM_DRP[105] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 9 PLL[0]: MMCM_DRP[105] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 11 PLL[0]: MMCM_DRP[105] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 13 PLL[0]: MMCM_DRP[105] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 15 PLL[0]: MMCM_DRP[105] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 1 PLL[0]: MMCM_DRP[106] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 3 PLL[0]: MMCM_DRP[106] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 5 PLL[0]: MMCM_DRP[106] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 7 PLL[0]: MMCM_DRP[106] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 9 PLL[0]: MMCM_DRP[106] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 11 PLL[0]: MMCM_DRP[106] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 13 PLL[0]: MMCM_DRP[106] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 15 PLL[0]: MMCM_DRP[106] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 1 PLL[0]: MMCM_DRP[107] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 3 PLL[0]: MMCM_DRP[107] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 5 PLL[0]: MMCM_DRP[107] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 7 PLL[0]: MMCM_DRP[107] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 9 PLL[0]: MMCM_DRP[107] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 11 PLL[0]: MMCM_DRP[107] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 13 PLL[0]: MMCM_DRP[107] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 15 PLL[0]: MMCM_DRP[107] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 1 PLL[0]: MMCM_DRP[108] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 3 PLL[0]: MMCM_DRP[108] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 5 PLL[0]: MMCM_DRP[108] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 7 PLL[0]: MMCM_DRP[108] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 9 PLL[0]: MMCM_DRP[108] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 11 PLL[0]: MMCM_DRP[108] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 13 PLL[0]: MMCM_DRP[108] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 15 PLL[0]: MMCM_DRP[108] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 1 PLL[0]: MMCM_DRP[109] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 3 PLL[0]: MMCM_DRP[109] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 5 PLL[0]: MMCM_DRP[109] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 7 PLL[0]: MMCM_DRP[109] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 9 PLL[0]: MMCM_DRP[109] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 11 PLL[0]: MMCM_DRP[109] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 13 PLL[0]: MMCM_DRP[109] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 15 PLL[0]: MMCM_DRP[109] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 1 PLL[0]: MMCM_DRP[110] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 3 PLL[0]: MMCM_DRP[110] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 5 PLL[0]: MMCM_DRP[110] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 7 PLL[0]: MMCM_DRP[110] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 9 PLL[0]: MMCM_DRP[110] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 11 PLL[0]: MMCM_DRP[110] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 13 PLL[0]: MMCM_DRP[110] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 15 PLL[0]: MMCM_DRP[110] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 1 PLL[0]: MMCM_DRP[111] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 3 PLL[0]: MMCM_DRP[111] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 5 PLL[0]: MMCM_DRP[111] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 7 PLL[0]: MMCM_DRP[111] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 9 PLL[0]: MMCM_DRP[111] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 11 PLL[0]: MMCM_DRP[111] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 13 PLL[0]: MMCM_DRP[111] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 15 PLL[0]: MMCM_DRP[111] bit 14
virtex7 CMT rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 1 PLL[0]: MMCM_DRP[96] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 3 PLL[0]: MMCM_DRP[96] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 5 PLL[0]: MMCM_DRP[96] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 7 PLL[0]: MMCM_DRP[96] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 9 PLL[0]: MMCM_DRP[96] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 11 PLL[0]: MMCM_DRP[96] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 13 PLL[0]: MMCM_DRP[96] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 15 PLL[0]: MMCM_DRP[96] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 1 PLL[0]: MMCM_DRP[97] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 3 PLL[0]: MMCM_DRP[97] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 5 PLL[0]: MMCM_DRP[97] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 7 PLL[0]: MMCM_DRP[97] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 9 PLL[0]: MMCM_DRP[97] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 11 PLL[0]: MMCM_DRP[97] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 13 PLL[0]: MMCM_DRP[97] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 15 PLL[0]: MMCM_DRP[97] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 1 PLL[0]: MMCM_DRP[98] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 3 PLL[0]: MMCM_DRP[98] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 5 PLL[0]: MMCM_DRP[98] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 7 PLL[0]: MMCM_DRP[98] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 9 PLL[0]: MMCM_DRP[98] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 11 PLL[0]: MMCM_DRP[98] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 13 PLL[0]: MMCM_DRP[98] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 15 PLL[0]: MMCM_DRP[98] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 1 PLL[0]: MMCM_DRP[99] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 3 PLL[0]: MMCM_DRP[99] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 5 PLL[0]: MMCM_DRP[99] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 7 PLL[0]: MMCM_DRP[99] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 9 PLL[0]: MMCM_DRP[99] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 11 PLL[0]: MMCM_DRP[99] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 13 PLL[0]: MMCM_DRP[99] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 15 PLL[0]: MMCM_DRP[99] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 1 PLL[0]: MMCM_DRP[100] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 3 PLL[0]: MMCM_DRP[100] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 5 PLL[0]: MMCM_DRP[100] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 7 PLL[0]: MMCM_DRP[100] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 9 PLL[0]: MMCM_DRP[100] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 11 PLL[0]: MMCM_DRP[100] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 13 PLL[0]: MMCM_DRP[100] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 15 PLL[0]: MMCM_DRP[100] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 1 PLL[0]: MMCM_DRP[101] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 3 PLL[0]: MMCM_DRP[101] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 5 PLL[0]: MMCM_DRP[101] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 7 PLL[0]: MMCM_DRP[101] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 9 PLL[0]: MMCM_DRP[101] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 11 PLL[0]: MMCM_DRP[101] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 13 PLL[0]: MMCM_DRP[101] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 15 PLL[0]: MMCM_DRP[101] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 1 PLL[0]: MMCM_DRP[102] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 3 PLL[0]: MMCM_DRP[102] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 5 PLL[0]: MMCM_DRP[102] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 7 PLL[0]: MMCM_DRP[102] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 9 PLL[0]: MMCM_DRP[102] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 11 PLL[0]: MMCM_DRP[102] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 13 PLL[0]: MMCM_DRP[102] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 15 PLL[0]: MMCM_DRP[102] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 1 PLL[0]: MMCM_DRP[103] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 3 PLL[0]: MMCM_DRP[103] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 5 PLL[0]: MMCM_DRP[103] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 7 PLL[0]: MMCM_DRP[103] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 9 PLL[0]: MMCM_DRP[103] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 11 PLL[0]: MMCM_DRP[103] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 13 PLL[0]: MMCM_DRP[103] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 15 PLL[0]: MMCM_DRP[103] bit 14
virtex7 CMT rect MAIN[4]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 1 PLL[0]: MMCM_DRP[88] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 3 PLL[0]: MMCM_DRP[88] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 5 PLL[0]: MMCM_DRP[88] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 7 PLL[0]: MMCM_DRP[88] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 9 PLL[0]: MMCM_DRP[88] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 11 PLL[0]: MMCM_DRP[88] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 13 PLL[0]: MMCM_DRP[88] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 15 PLL[0]: MMCM_DRP[88] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 1 PLL[0]: MMCM_DRP[89] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 3 PLL[0]: MMCM_DRP[89] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 5 PLL[0]: MMCM_DRP[89] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 7 PLL[0]: MMCM_DRP[89] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 9 PLL[0]: MMCM_DRP[89] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 11 PLL[0]: MMCM_DRP[89] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 13 PLL[0]: MMCM_DRP[89] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 15 PLL[0]: MMCM_DRP[89] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 1 PLL[0]: MMCM_DRP[90] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 3 PLL[0]: MMCM_DRP[90] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 5 PLL[0]: MMCM_DRP[90] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 7 PLL[0]: MMCM_DRP[90] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 9 PLL[0]: MMCM_DRP[90] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 11 PLL[0]: MMCM_DRP[90] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 13 PLL[0]: MMCM_DRP[90] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 15 PLL[0]: MMCM_DRP[90] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 1 PLL[0]: MMCM_DRP[91] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 3 PLL[0]: MMCM_DRP[91] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 5 PLL[0]: MMCM_DRP[91] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 7 PLL[0]: MMCM_DRP[91] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 9 PLL[0]: MMCM_DRP[91] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 11 PLL[0]: MMCM_DRP[91] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 13 PLL[0]: MMCM_DRP[91] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 15 PLL[0]: MMCM_DRP[91] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 1 PLL[0]: MMCM_DRP[92] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 3 PLL[0]: MMCM_DRP[92] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 5 PLL[0]: MMCM_DRP[92] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 7 PLL[0]: MMCM_DRP[92] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 9 PLL[0]: MMCM_DRP[92] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 11 PLL[0]: MMCM_DRP[92] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 13 PLL[0]: MMCM_DRP[92] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 15 PLL[0]: MMCM_DRP[92] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 1 PLL[0]: MMCM_DRP[93] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 3 PLL[0]: MMCM_DRP[93] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 5 PLL[0]: MMCM_DRP[93] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 7 PLL[0]: MMCM_DRP[93] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 9 PLL[0]: MMCM_DRP[93] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 11 PLL[0]: MMCM_DRP[93] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 13 PLL[0]: MMCM_DRP[93] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 15 PLL[0]: MMCM_DRP[93] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 1 PLL[0]: MMCM_DRP[94] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 3 PLL[0]: MMCM_DRP[94] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 5 PLL[0]: MMCM_DRP[94] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 7 PLL[0]: MMCM_DRP[94] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 9 PLL[0]: MMCM_DRP[94] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 11 PLL[0]: MMCM_DRP[94] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 13 PLL[0]: MMCM_DRP[94] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 15 PLL[0]: MMCM_DRP[94] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 1 PLL[0]: MMCM_DRP[95] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 3 PLL[0]: MMCM_DRP[95] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 5 PLL[0]: MMCM_DRP[95] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 7 PLL[0]: MMCM_DRP[95] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 9 PLL[0]: MMCM_DRP[95] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 11 PLL[0]: MMCM_DRP[95] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 13 PLL[0]: MMCM_DRP[95] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 15 PLL[0]: MMCM_DRP[95] bit 14
virtex7 CMT rect MAIN[5]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 1 PLL[0]: MMCM_DRP[80] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 3 PLL[0]: MMCM_DRP[80] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 5 PLL[0]: MMCM_DRP[80] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 7 PLL[0]: MMCM_DRP[80] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 9 PLL[0]: MMCM_DRP[80] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 11 PLL[0]: MMCM_DRP[80] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 13 PLL[0]: MMCM_DRP[80] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 15 PLL[0]: MMCM_DRP[80] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 1 PLL[0]: MMCM_DRP[81] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 3 PLL[0]: MMCM_DRP[81] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 5 PLL[0]: MMCM_DRP[81] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 7 PLL[0]: MMCM_DRP[81] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 9 PLL[0]: MMCM_DRP[81] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 11 PLL[0]: MMCM_DRP[81] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 13 PLL[0]: MMCM_DRP[81] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 15 PLL[0]: MMCM_DRP[81] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 1 PLL[0]: MMCM_DRP[82] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 3 PLL[0]: MMCM_DRP[82] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 5 PLL[0]: MMCM_DRP[82] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 7 PLL[0]: MMCM_DRP[82] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 9 PLL[0]: MMCM_DRP[82] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 11 PLL[0]: MMCM_DRP[82] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 13 PLL[0]: MMCM_DRP[82] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 15 PLL[0]: MMCM_DRP[82] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 1 PLL[0]: MMCM_DRP[83] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 3 PLL[0]: MMCM_DRP[83] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 5 PLL[0]: MMCM_DRP[83] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 7 PLL[0]: MMCM_DRP[83] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 9 PLL[0]: MMCM_DRP[83] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 11 PLL[0]: MMCM_DRP[83] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 13 PLL[0]: MMCM_DRP[83] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 15 PLL[0]: MMCM_DRP[83] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 1 PLL[0]: MMCM_DRP[84] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 3 PLL[0]: MMCM_DRP[84] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 5 PLL[0]: MMCM_DRP[84] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 7 PLL[0]: MMCM_DRP[84] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 9 PLL[0]: MMCM_DRP[84] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 11 PLL[0]: MMCM_DRP[84] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 13 PLL[0]: MMCM_DRP[84] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 15 PLL[0]: MMCM_DRP[84] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 1 PLL[0]: MMCM_DRP[85] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 3 PLL[0]: MMCM_DRP[85] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 5 PLL[0]: MMCM_DRP[85] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 7 PLL[0]: MMCM_DRP[85] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 9 PLL[0]: MMCM_DRP[85] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 11 PLL[0]: MMCM_DRP[85] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 13 PLL[0]: MMCM_DRP[85] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 15 PLL[0]: MMCM_DRP[85] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 1 PLL[0]: MMCM_DRP[86] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 3 PLL[0]: MMCM_DRP[86] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 5 PLL[0]: MMCM_DRP[86] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 7 PLL[0]: MMCM_DRP[86] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 9 PLL[0]: MMCM_DRP[86] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 11 PLL[0]: MMCM_DRP[86] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 13 PLL[0]: MMCM_DRP[86] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 15 PLL[0]: MMCM_DRP[86] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 1 PLL[0]: MMCM_DRP[87] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 3 PLL[0]: MMCM_DRP[87] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 5 PLL[0]: MMCM_DRP[87] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 7 PLL[0]: MMCM_DRP[87] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 9 PLL[0]: MMCM_DRP[87] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 11 PLL[0]: MMCM_DRP[87] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 13 PLL[0]: MMCM_DRP[87] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 15 PLL[0]: MMCM_DRP[87] bit 14
virtex7 CMT rect MAIN[6]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 1 PLL[0]: MMCM_DRP[72] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 3 PLL[0]: MMCM_DRP[72] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 5 PLL[0]: MMCM_DRP[72] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 7 PLL[0]: MMCM_DRP[72] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 9 PLL[0]: MMCM_DRP[72] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 11 PLL[0]: MMCM_DRP[72] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 13 PLL[0]: MMCM_DRP[72] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 15 PLL[0]: MMCM_DRP[72] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 1 PLL[0]: MMCM_DRP[73] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 3 PLL[0]: MMCM_DRP[73] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 5 PLL[0]: MMCM_DRP[73] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 7 PLL[0]: MMCM_DRP[73] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 9 PLL[0]: MMCM_DRP[73] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 11 PLL[0]: MVDD_SEL bit 0 PLL[0]: MMCM_DRP[73] bit 10 PLL[0]: SEL_HV_NMOS
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 13 PLL[0]: EN_CURR_SINK bit 0 PLL[0]: MMCM_DRP[73] bit 12 PLL[0]: MVDD_SEL bit 1
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 15 PLL[0]: SUP_SEL_AREG PLL[0]: MMCM_DRP[73] bit 14 PLL[0]: EN_CURR_SINK bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 1 PLL[0]: AVDD_VBG_SEL bit 1 PLL[0]: MMCM_DRP[74] bit 0 PLL[0]: AVDD_VBG_SEL bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 3 PLL[0]: AVDD_VBG_SEL bit 3 PLL[0]: MMCM_DRP[74] bit 2 PLL[0]: AVDD_VBG_SEL bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 5 PLL[0]: AVDD_VBG_PD bit 1 PLL[0]: MMCM_DRP[74] bit 4 PLL[0]: AVDD_VBG_PD bit 0
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 7 PLL[0]: V7_AVDD_COMP_SET bit 0 PLL[0]: MMCM_DRP[74] bit 6 PLL[0]: AVDD_VBG_PD bit 2
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 9 PLL[0]: V7_AVDD_COMP_SET bit 2 PLL[0]: MMCM_DRP[74] bit 8 PLL[0]: V7_AVDD_COMP_SET bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 11 PLL[0]: MMCM_DRP[74] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 13 PLL[0]: MMCM_DRP[74] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 15 PLL[0]: MMCM_DRP[74] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 1 PLL[0]: MMCM_DRP[75] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 3 PLL[0]: MMCM_DRP[75] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 5 PLL[0]: MMCM_DRP[75] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 7 PLL[0]: MMCM_DRP[75] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 9 PLL[0]: MMCM_DRP[75] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 11 PLL[0]: MMCM_DRP[75] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 13 PLL[0]: MMCM_DRP[75] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 15 PLL[0]: MMCM_DRP[75] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 1 PLL[0]: MMCM_DRP[76] bit 0 PLL[0]: HVLF_CNT_TEST bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 3 PLL[0]: HVLF_CNT_TEST bit 1 PLL[0]: MMCM_DRP[76] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 5 PLL[0]: MMCM_DRP[76] bit 4 PLL[0]: HVLF_CNT_TEST bit 2
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 7 PLL[0]: HVLF_CNT_TEST bit 3 PLL[0]: MMCM_DRP[76] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 9 PLL[0]: MMCM_DRP[76] bit 8 PLL[0]: HVLF_CNT_TEST bit 4
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 11 PLL[0]: HVLF_CNT_TEST bit 5 PLL[0]: MMCM_DRP[76] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 13 PLL[0]: MMCM_DRP[76] bit 12 PLL[0]: HVLF_CNT_TEST_EN
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 15 PLL[0]: MMCM_DRP[76] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 1 PLL[0]: MMCM_DRP[77] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 3 PLL[0]: MMCM_DRP[77] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 5 PLL[0]: MMCM_DRP[77] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 7 PLL[0]: MMCM_DRP[77] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 9 PLL[0]: MMCM_DRP[77] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 11 PLL[0]: MMCM_DRP[77] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 13 PLL[0]: MMCM_DRP[77] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 15 PLL[0]: MMCM_DRP[77] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 1 PLL[0]: MMCM_DRP[78] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 3 PLL[0]: CP_RES bit 0 PLL[0]: MMCM_DRP[78] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 5 PLL[0]: MMCM_DRP[78] bit 4 PLL[0]: CP_RES bit 1
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 7 PLL[0]: CP_BIAS_TRIP_SET bit 0 PLL[0]: MMCM_DRP[78] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 9 PLL[0]: MMCM_DRP[78] bit 8 PLL[0]: CP bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 11 PLL[0]: CP bit 1 PLL[0]: MMCM_DRP[78] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 13 PLL[0]: MMCM_DRP[78] bit 12 PLL[0]: CP bit 2
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 15 PLL[0]: CP bit 3 PLL[0]: MMCM_DRP[78] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 1 PLL[0]: MMCM_DRP[79] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 3 PLL[0]: MMCM_DRP[79] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 5 PLL[0]: MMCM_DRP[79] bit 4 PLL[0]: LFHF bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 7 PLL[0]: LFHF bit 1 PLL[0]: MMCM_DRP[79] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 9 PLL[0]: MMCM_DRP[79] bit 8 PLL[0]: RES bit 0
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 11 PLL[0]: RES bit 1 PLL[0]: MMCM_DRP[79] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 13 PLL[0]: MMCM_DRP[79] bit 12 PLL[0]: RES bit 2
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 15 PLL[0]: RES bit 3 PLL[0]: MMCM_DRP[79] bit 14
virtex7 CMT rect MAIN[7]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 1 PLL[0]: MMCM_DRP[64] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 3 PLL[0]: MMCM_DRP[64] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 5 PLL[0]: MMCM_DRP[64] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 7 PLL[0]: MMCM_DRP[64] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 9 PLL[0]: MMCM_DRP[64] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 11 PLL[0]: MMCM_DRP[64] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 13 PLL[0]: MMCM_DRP[64] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 15 PLL[0]: MMCM_DRP[64] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 1 PLL[0]: MMCM_DRP[65] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 3 PLL[0]: MMCM_DRP[65] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 5 PLL[0]: MMCM_DRP[65] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 7 PLL[0]: MMCM_DRP[65] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 9 PLL[0]: MMCM_DRP[65] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 11 PLL[0]: MMCM_DRP[65] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 13 PLL[0]: MMCM_DRP[65] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 15 PLL[0]: MMCM_DRP[65] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 1 PLL[0]: MMCM_DRP[66] bit 0 PLL[0]: MAN_LF bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 3 PLL[0]: MAN_LF bit 1 PLL[0]: MMCM_DRP[66] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 5 PLL[0]: MMCM_DRP[66] bit 4 PLL[0]: MAN_LF bit 2
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 7 PLL[0]: VLF_HIGH_DIS_B PLL[0]: MMCM_DRP[66] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 9 PLL[0]: MMCM_DRP[66] bit 8 PLL[0]: LF_PEN bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 11 PLL[0]: LF_PEN bit 1 PLL[0]: MMCM_DRP[66] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 13 PLL[0]: MMCM_DRP[66] bit 12 PLL[0]: LF_NEN bit 0
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 15 PLL[0]: LF_NEN bit 1 PLL[0]: MMCM_DRP[66] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 1 PLL[0]: MMCM_DRP[67] bit 0 PLL[0]: LF_LOW_SEL
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 3 PLL[0]: MMCM_DRP[67] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 5 PLL[0]: MMCM_DRP[67] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 7 PLL[0]: MMCM_DRP[67] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 9 PLL[0]: MMCM_DRP[67] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 11 PLL[0]: MMCM_DRP[67] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 13 PLL[0]: MMCM_DRP[67] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 15 PLL[0]: MMCM_DRP[67] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 1 PLL[0]: MMCM_DRP[68] bit 0 PLL[0]: SPARE_ANALOG bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 3 PLL[0]: SPARE_ANALOG bit 1 PLL[0]: MMCM_DRP[68] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 5 PLL[0]: MMCM_DRP[68] bit 4 PLL[0]: SPARE_ANALOG bit 2
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 7 PLL[0]: SPARE_ANALOG bit 3 PLL[0]: MMCM_DRP[68] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 9 PLL[0]: MMCM_DRP[68] bit 8 PLL[0]: SPARE_ANALOG bit 4
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 11 PLL[0]: MMCM_DRP[68] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 13 PLL[0]: MMCM_DRP[68] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 15 PLL[0]: MMCM_DRP[68] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 1 PLL[0]: MMCM_DRP[69] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 3 PLL[0]: MMCM_DRP[69] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 5 PLL[0]: MMCM_DRP[69] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 7 PLL[0]: MMCM_DRP[69] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 9 PLL[0]: MMCM_DRP[69] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 11 PLL[0]: VREF_START bit 0 PLL[0]: MMCM_DRP[69] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 13 PLL[0]: MMCM_DRP[69] bit 12 PLL[0]: VREF_START bit 1
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 15 PLL[0]: MMCM_DRP[69] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 1 PLL[0]: MMCM_DRP[70] bit 0 PLL[0]: VLF_HIGH_PWDN_B
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 3 PLL[0]: MMCM_DRP[70] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 5 PLL[0]: MMCM_DRP[70] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 7 PLL[0]: MMCM_DRP[70] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 9 PLL[0]: MMCM_DRP[70] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 11 PLL[0]: MMCM_DRP[70] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 13 PLL[0]: MMCM_DRP[70] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 15 PLL[0]: MMCM_DRP[70] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 1 PLL[0]: MMCM_DRP[71] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 3 PLL[0]: MMCM_DRP[71] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 5 PLL[0]: MMCM_DRP[71] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 7 PLL[0]: MMCM_DRP[71] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 9 PLL[0]: MMCM_DRP[71] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 11 PLL[0]: MMCM_DRP[71] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 13 PLL[0]: MMCM_DRP[71] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 15 PLL[0]: MMCM_DRP[71] bit 14
virtex7 CMT rect MAIN[8]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 1 PLL[0]: MMCM_DRP[56] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 3 PLL[0]: MMCM_DRP[56] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 5 PLL[0]: MMCM_DRP[56] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 7 PLL[0]: MMCM_DRP[56] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 9 PLL[0]: MMCM_DRP[56] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 11 PLL[0]: MMCM_DRP[56] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 13 PLL[0]: MMCM_DRP[56] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 15 PLL[0]: MMCM_DRP[56] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 1 PLL[0]: MMCM_DRP[57] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 3 PLL[0]: MMCM_DRP[57] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 5 PLL[0]: MMCM_DRP[57] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 7 PLL[0]: MMCM_DRP[57] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 9 PLL[0]: MMCM_DRP[57] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 11 PLL[0]: MMCM_DRP[57] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 13 PLL[0]: MMCM_DRP[57] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 15 PLL[0]: MMCM_DRP[57] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 1 PLL[0]: MMCM_DRP[58] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 3 PLL[0]: MMCM_DRP[58] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 5 PLL[0]: MMCM_DRP[58] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 7 PLL[0]: MMCM_DRP[58] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 9 PLL[0]: MMCM_DRP[58] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 11 PLL[0]: MMCM_DRP[58] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 13 PLL[0]: MMCM_DRP[58] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 15 PLL[0]: MMCM_DRP[58] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 1 PLL[0]: MMCM_DRP[59] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 3 PLL[0]: MMCM_DRP[59] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 5 PLL[0]: MMCM_DRP[59] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 7 PLL[0]: MMCM_DRP[59] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 9 PLL[0]: MMCM_DRP[59] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 11 PLL[0]: MMCM_DRP[59] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 13 PLL[0]: MMCM_DRP[59] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 15 PLL[0]: MMCM_DRP[59] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 1 PLL[0]: MMCM_DRP[60] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 3 PLL[0]: MMCM_DRP[60] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 5 PLL[0]: MMCM_DRP[60] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 7 PLL[0]: MMCM_DRP[60] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 9 PLL[0]: MMCM_DRP[60] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 11 PLL[0]: MMCM_DRP[60] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 13 PLL[0]: MMCM_DRP[60] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 15 PLL[0]: MMCM_DRP[60] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 1 PLL[0]: MMCM_DRP[61] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 3 PLL[0]: MMCM_DRP[61] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 5 PLL[0]: MMCM_DRP[61] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 7 PLL[0]: MMCM_DRP[61] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 9 PLL[0]: MMCM_DRP[61] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 11 PLL[0]: MMCM_DRP[61] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 13 PLL[0]: MMCM_DRP[61] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 15 PLL[0]: MMCM_DRP[61] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 1 PLL[0]: MMCM_DRP[62] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 3 PLL[0]: MMCM_DRP[62] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 5 PLL[0]: MMCM_DRP[62] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 7 PLL[0]: MMCM_DRP[62] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 9 PLL[0]: MMCM_DRP[62] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 11 PLL[0]: MMCM_DRP[62] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 13 PLL[0]: MMCM_DRP[62] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 15 PLL[0]: MMCM_DRP[62] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 1 PLL[0]: MMCM_DRP[63] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 3 PLL[0]: MMCM_DRP[63] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 5 PLL[0]: MMCM_DRP[63] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 7 PLL[0]: MMCM_DRP[63] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 9 PLL[0]: MMCM_DRP[63] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 11 PLL[0]: MMCM_DRP[63] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 13 PLL[0]: MMCM_DRP[63] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 15 PLL[0]: MMCM_DRP[63] bit 14
virtex7 CMT rect MAIN[9]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 1 PLL[0]: MMCM_DRP[48] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 3 PLL[0]: MMCM_DRP[48] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 5 PLL[0]: MMCM_DRP[48] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 7 PLL[0]: MMCM_DRP[48] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 9 PLL[0]: MMCM_DRP[48] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 11 PLL[0]: MMCM_DRP[48] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 13 PLL[0]: MMCM_DRP[48] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 15 PLL[0]: MMCM_DRP[48] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 1 PLL[0]: MMCM_DRP[49] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 3 PLL[0]: MMCM_DRP[49] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 5 PLL[0]: MMCM_DRP[49] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 7 PLL[0]: MMCM_DRP[49] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 9 PLL[0]: MMCM_DRP[49] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 11 PLL[0]: MMCM_DRP[49] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 13 PLL[0]: MMCM_DRP[49] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 15 PLL[0]: MMCM_DRP[49] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 1 PLL[0]: MMCM_DRP[50] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 3 PLL[0]: MMCM_DRP[50] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 5 PLL[0]: MMCM_DRP[50] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 7 PLL[0]: MMCM_DRP[50] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 9 PLL[0]: MMCM_DRP[50] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 11 PLL[0]: MMCM_DRP[50] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 13 PLL[0]: MMCM_DRP[50] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 15 PLL[0]: MMCM_DRP[50] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 1 PLL[0]: MMCM_DRP[51] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 3 PLL[0]: MMCM_DRP[51] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 5 PLL[0]: MMCM_DRP[51] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 7 PLL[0]: MMCM_DRP[51] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 9 PLL[0]: MMCM_DRP[51] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 11 PLL[0]: MMCM_DRP[51] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 13 PLL[0]: MMCM_DRP[51] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 15 PLL[0]: MMCM_DRP[51] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 1 PLL[0]: MMCM_DRP[52] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 3 PLL[0]: MMCM_DRP[52] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 5 PLL[0]: MMCM_DRP[52] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 7 PLL[0]: MMCM_DRP[52] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 9 PLL[0]: MMCM_DRP[52] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 11 PLL[0]: MMCM_DRP[52] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 13 PLL[0]: MMCM_DRP[52] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 15 PLL[0]: MMCM_DRP[52] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 1 PLL[0]: MMCM_DRP[53] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 3 PLL[0]: MMCM_DRP[53] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 5 PLL[0]: MMCM_DRP[53] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 7 PLL[0]: MMCM_DRP[53] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 9 PLL[0]: MMCM_DRP[53] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 11 PLL[0]: MMCM_DRP[53] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 13 PLL[0]: MMCM_DRP[53] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 15 PLL[0]: MMCM_DRP[53] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 1 PLL[0]: MMCM_DRP[54] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 3 PLL[0]: MMCM_DRP[54] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 5 PLL[0]: MMCM_DRP[54] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 7 PLL[0]: MMCM_DRP[54] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 9 PLL[0]: MMCM_DRP[54] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 11 PLL[0]: MMCM_DRP[54] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 13 PLL[0]: MMCM_DRP[54] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 15 PLL[0]: MMCM_DRP[54] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 1 PLL[0]: MMCM_DRP[55] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 3 PLL[0]: MMCM_DRP[55] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 5 PLL[0]: MMCM_DRP[55] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 7 PLL[0]: MMCM_DRP[55] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 9 PLL[0]: MMCM_DRP[55] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 11 PLL[0]: MMCM_DRP[55] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 13 PLL[0]: MMCM_DRP[55] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 15 PLL[0]: MMCM_DRP[55] bit 14
virtex7 CMT rect MAIN[10]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 1 PLL[0]: MMCM_DRP[40] bit 0 PLL[0]: INTERP_EN bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 3 PLL[0]: INTERP_EN bit 1 PLL[0]: MMCM_DRP[40] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 5 PLL[0]: MMCM_DRP[40] bit 4 PLL[0]: INTERP_EN bit 2
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 7 PLL[0]: INTERP_EN bit 3 PLL[0]: MMCM_DRP[40] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 9 PLL[0]: MMCM_DRP[40] bit 8 PLL[0]: INTERP_EN bit 4
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 11 PLL[0]: INTERP_EN bit 5 PLL[0]: MMCM_DRP[40] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 13 PLL[0]: MMCM_DRP[40] bit 12 PLL[0]: INTERP_EN bit 6
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 15 PLL[0]: INTERP_EN bit 7 PLL[0]: MMCM_DRP[40] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 1 PLL[0]: MMCM_DRP[41] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 3 PLL[0]: MMCM_DRP[41] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 5 PLL[0]: MMCM_DRP[41] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 7 PLL[0]: MMCM_DRP[41] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 9 PLL[0]: MMCM_DRP[41] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 11 PLL[0]: MMCM_DRP[41] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 13 PLL[0]: MMCM_DRP[41] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 15 PLL[0]: MMCM_DRP[41] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 1 PLL[0]: MMCM_DRP[42] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 3 PLL[0]: MMCM_DRP[42] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 5 PLL[0]: MMCM_DRP[42] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 7 PLL[0]: MMCM_DRP[42] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 9 PLL[0]: MMCM_DRP[42] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 11 PLL[0]: MMCM_DRP[42] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 13 PLL[0]: MMCM_DRP[42] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 15 PLL[0]: MMCM_DRP[42] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 1 PLL[0]: MMCM_DRP[43] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 3 PLL[0]: MMCM_DRP[43] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 5 PLL[0]: MMCM_DRP[43] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 7 PLL[0]: MMCM_DRP[43] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 9 PLL[0]: MMCM_DRP[43] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 11 PLL[0]: MMCM_DRP[43] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 13 PLL[0]: MMCM_DRP[43] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 15 PLL[0]: MMCM_DRP[43] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 1 PLL[0]: MMCM_DRP[44] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 3 PLL[0]: MMCM_DRP[44] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 5 PLL[0]: MMCM_DRP[44] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 7 PLL[0]: MMCM_DRP[44] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 9 PLL[0]: MMCM_DRP[44] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 11 PLL[0]: MMCM_DRP[44] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 13 PLL[0]: MMCM_DRP[44] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 15 PLL[0]: MMCM_DRP[44] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 1 PLL[0]: MMCM_DRP[45] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 3 PLL[0]: MMCM_DRP[45] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 5 PLL[0]: MMCM_DRP[45] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 7 PLL[0]: MMCM_DRP[45] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 9 PLL[0]: MMCM_DRP[45] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 11 PLL[0]: MMCM_DRP[45] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 13 PLL[0]: MMCM_DRP[45] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 15 PLL[0]: MMCM_DRP[45] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 1 PLL[0]: MMCM_DRP[46] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 3 PLL[0]: MMCM_DRP[46] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 5 PLL[0]: MMCM_DRP[46] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 7 PLL[0]: MMCM_DRP[46] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 9 PLL[0]: MMCM_DRP[46] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 11 PLL[0]: MMCM_DRP[46] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 13 PLL[0]: MMCM_DRP[46] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 15 PLL[0]: MMCM_DRP[46] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 1 PLL[0]: MMCM_DRP[47] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 3 PLL[0]: MMCM_DRP[47] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 5 PLL[0]: MMCM_DRP[47] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 7 PLL[0]: MMCM_DRP[47] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 9 PLL[0]: MMCM_DRP[47] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 11 PLL[0]: MMCM_DRP[47] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 13 PLL[0]: MMCM_DRP[47] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 15 PLL[0]: MMCM_DRP[47] bit 14
virtex7 CMT rect MAIN[11]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 1 PLL[0]: MMCM_DRP[32] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 3 PLL[0]: MMCM_DRP[32] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 5 PLL[0]: MMCM_DRP[32] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 7 PLL[0]: MMCM_DRP[32] bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 9 PLL[0]: MMCM_DRP[32] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 11 PLL[0]: MMCM_DRP[32] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 13 PLL[0]: MMCM_DRP[32] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 15 PLL[0]: MMCM_DRP[32] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 1 PLL[0]: MMCM_DRP[33] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 3 PLL[0]: MMCM_DRP[33] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 5 PLL[0]: MMCM_DRP[33] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 7 PLL[0]: MMCM_DRP[33] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 9 PLL[0]: MMCM_DRP[33] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 11 PLL[0]: MMCM_DRP[33] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 13 PLL[0]: MMCM_DRP[33] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 15 PLL[0]: MMCM_DRP[33] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 1 PLL[0]: EN_VCO_DIV1 PLL[0]: MMCM_DRP[34] bit 0 PLL[0]: EN_VCO_DIV6
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 3 PLL[0]: MMCM_DRP[34] bit 2 PLL[0]: INTERP_TEST
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 5 PLL[0]: MMCM_DRP[34] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 7 PLL[0]: MMCM_DRP[34] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 9 PLL[0]: MMCM_DRP[34] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 11 PLL[0]: MMCM_DRP[34] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 13 PLL[0]: MMCM_DRP[34] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 15 PLL[0]: MMCM_DRP[34] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 1 PLL[0]: MMCM_DRP[35] bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 3 PLL[0]: MMCM_DRP[35] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 5 PLL[0]: MMCM_DRP[35] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 7 PLL[0]: MMCM_DRP[35] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 9 PLL[0]: MMCM_DRP[35] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 11 PLL[0]: MMCM_DRP[35] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 13 PLL[0]: MMCM_DRP[35] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 15 PLL[0]: MMCM_DRP[35] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 1 PLL[0]: MMCM_DRP[36] bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 3 PLL[0]: MMCM_DRP[36] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 5 PLL[0]: MMCM_DRP[36] bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 7 PLL[0]: MMCM_DRP[36] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 9 PLL[0]: MMCM_DRP[36] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 11 PLL[0]: MMCM_DRP[36] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 13 PLL[0]: MMCM_DRP[36] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 15 PLL[0]: MMCM_DRP[36] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 1 PLL[0]: MMCM_DRP[37] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 3 PLL[0]: MMCM_DRP[37] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 5 PLL[0]: MMCM_DRP[37] bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 7 PLL[0]: MMCM_DRP[37] bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 9 PLL[0]: MMCM_DRP[37] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 11 PLL[0]: MMCM_DRP[37] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 13 PLL[0]: MMCM_DRP[37] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 15 PLL[0]: MMCM_DRP[37] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 1 PLL[0]: MMCM_DRP[38] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 3 PLL[0]: ANALOG_MISC bit 0 PLL[0]: MMCM_DRP[38] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 5 PLL[0]: MMCM_DRP[38] bit 4 PLL[0]: ANALOG_MISC bit 1
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 7 PLL[0]: ANALOG_MISC bit 2 PLL[0]: MMCM_DRP[38] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 9 PLL[0]: MMCM_DRP[38] bit 8 PLL[0]: ANALOG_MISC bit 3
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 11 PLL[0]: MMCM_DRP[38] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 13 PLL[0]: MMCM_DRP[38] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 15 PLL[0]: MMCM_DRP[38] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 1 PLL[0]: MMCM_DRP[39] bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 3 PLL[0]: MMCM_DRP[39] bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 5 PLL[0]: MMCM_DRP[39] bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 7 PLL[0]: MMCM_DRP[39] bit 6
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 9 PLL[0]: MMCM_DRP[39] bit 8
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 11 PLL[0]: MMCM_DRP[39] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 13 PLL[0]: MMCM_DRP[39] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 15 PLL[0]: MMCM_DRP[39] bit 14
virtex7 CMT rect MAIN[12]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 1 PLL[0]: LOCK_CNT bit 1 PLL[0]: MMCM_DRP[24] bit 0 PLL[0]: LOCK_CNT bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 3 PLL[0]: LOCK_CNT bit 3 PLL[0]: MMCM_DRP[24] bit 2 PLL[0]: LOCK_CNT bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 5 PLL[0]: LOCK_CNT bit 5 PLL[0]: MMCM_DRP[24] bit 4 PLL[0]: LOCK_CNT bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 7 PLL[0]: LOCK_CNT bit 7 PLL[0]: MMCM_DRP[24] bit 6 PLL[0]: LOCK_CNT bit 6
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 9 PLL[0]: LOCK_CNT bit 9 PLL[0]: MMCM_DRP[24] bit 8 PLL[0]: LOCK_CNT bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 11 PLL[0]: MMCM_DRP[24] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 13 PLL[0]: MMCM_DRP[24] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 15 PLL[0]: MMCM_DRP[24] bit 14
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 1 PLL[0]: UNLOCK_CNT bit 1 PLL[0]: MMCM_DRP[25] bit 0 PLL[0]: UNLOCK_CNT bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 3 PLL[0]: UNLOCK_CNT bit 3 PLL[0]: MMCM_DRP[25] bit 2 PLL[0]: UNLOCK_CNT bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 5 PLL[0]: UNLOCK_CNT bit 5 PLL[0]: MMCM_DRP[25] bit 4 PLL[0]: UNLOCK_CNT bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 7 PLL[0]: UNLOCK_CNT bit 7 PLL[0]: MMCM_DRP[25] bit 6 PLL[0]: UNLOCK_CNT bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 9 PLL[0]: UNLOCK_CNT bit 9 PLL[0]: MMCM_DRP[25] bit 8 PLL[0]: UNLOCK_CNT bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 11 PLL[0]: LOCK_FB_DLY bit 1 PLL[0]: MMCM_DRP[25] bit 10 PLL[0]: LOCK_FB_DLY bit 0
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 13 PLL[0]: LOCK_FB_DLY bit 3 PLL[0]: MMCM_DRP[25] bit 12 PLL[0]: LOCK_FB_DLY bit 2
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 15 PLL[0]: MMCM_DRP[25] bit 14 PLL[0]: LOCK_FB_DLY bit 4
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 1 PLL[0]: LOCK_SAT_HIGH bit 1 PLL[0]: MMCM_DRP[26] bit 0 PLL[0]: LOCK_SAT_HIGH bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 3 PLL[0]: LOCK_SAT_HIGH bit 3 PLL[0]: MMCM_DRP[26] bit 2 PLL[0]: LOCK_SAT_HIGH bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 5 PLL[0]: LOCK_SAT_HIGH bit 5 PLL[0]: MMCM_DRP[26] bit 4 PLL[0]: LOCK_SAT_HIGH bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 7 PLL[0]: LOCK_SAT_HIGH bit 7 PLL[0]: MMCM_DRP[26] bit 6 PLL[0]: LOCK_SAT_HIGH bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 9 PLL[0]: LOCK_SAT_HIGH bit 9 PLL[0]: MMCM_DRP[26] bit 8 PLL[0]: LOCK_SAT_HIGH bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 11 PLL[0]: LOCK_REF_DLY bit 1 PLL[0]: MMCM_DRP[26] bit 10 PLL[0]: LOCK_REF_DLY bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 13 PLL[0]: LOCK_REF_DLY bit 3 PLL[0]: MMCM_DRP[26] bit 12 PLL[0]: LOCK_REF_DLY bit 2
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 15 PLL[0]: FREQ_COMP bit 0 PLL[0]: MMCM_DRP[26] bit 14 PLL[0]: LOCK_REF_DLY bit 4
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 1 PLL[0]: MMCM_DRP[27] bit 0 PLL[0]: FREQ_COMP bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 3 PLL[0]: MMCM_DRP[27] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 5 PLL[0]: MMCM_DRP[27] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 7 PLL[0]: MMCM_DRP[27] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 9 PLL[0]: MMCM_DRP[27] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 11 PLL[0]: MMCM_DRP[27] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 13 PLL[0]: MMCM_DRP[27] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 15 PLL[0]: MMCM_DRP[27] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 1 PLL[0]: SPARE_DIGITAL bit 1 PLL[0]: MMCM_DRP[28] bit 0 PLL[0]: SPARE_DIGITAL bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 3 PLL[0]: SPARE_DIGITAL bit 3 PLL[0]: MMCM_DRP[28] bit 2 PLL[0]: SPARE_DIGITAL bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 5 PLL[0]: MMCM_DRP[28] bit 4 PLL[0]: SPARE_DIGITAL bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 7 PLL[0]: MMCM_DRP[28] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 9 PLL[0]: MMCM_DRP[28] bit 8
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 11 PLL[0]: MMCM_DRP[28] bit 10
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 13 PLL[0]: MMCM_DRP[28] bit 12
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 15 PLL[0]: MMCM_DRP[28] bit 14
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 1 PLL[0]: MMCM_DRP[29] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 3 PLL[0]: MMCM_DRP[29] bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 5 PLL[0]: PFD bit 1 PLL[0]: MMCM_DRP[29] bit 4 PLL[0]: PFD bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 7 PLL[0]: PFD bit 3 PLL[0]: MMCM_DRP[29] bit 6 PLL[0]: PFD bit 2
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 9 PLL[0]: PFD bit 5 PLL[0]: MMCM_DRP[29] bit 8 PLL[0]: PFD bit 4
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 11 PLL[0]: SEL_SLIPD PLL[0]: MMCM_DRP[29] bit 10 PLL[0]: PFD bit 6
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 13 PLL[0]: MMCM_DRP[29] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 15 PLL[0]: MMCM_DRP[29] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 1 PLL[0]: MMCM_DRP[30] bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 3 PLL[0]: MMCM_DRP[30] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 5 PLL[0]: MMCM_DRP[30] bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 7 PLL[0]: MMCM_DRP[30] bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 9 PLL[0]: MMCM_DRP[30] bit 8
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 11 PLL[0]: MMCM_DRP[30] bit 10
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 13 PLL[0]: MMCM_DRP[30] bit 12
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 15 PLL[0]: SUP_SEL_DREG PLL[0]: MMCM_DRP[30] bit 14 PLL[0]: SEL_LV_NMOS
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 1 PLL[0]: DVDD_VBG_SEL bit 1 PLL[0]: MMCM_DRP[31] bit 0 PLL[0]: DVDD_VBG_SEL bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 3 PLL[0]: DVDD_VBG_SEL bit 3 PLL[0]: MMCM_DRP[31] bit 2 PLL[0]: DVDD_VBG_SEL bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 5 PLL[0]: DVDD_VBG_PD bit 1 PLL[0]: MMCM_DRP[31] bit 4 PLL[0]: DVDD_VBG_PD bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 7 PLL[0]: V7_DVDD_COMP_SET bit 0 PLL[0]: MMCM_DRP[31] bit 6 PLL[0]: DVDD_VBG_PD bit 2
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 9 PLL[0]: V7_DVDD_COMP_SET bit 2 PLL[0]: MMCM_DRP[31] bit 8 PLL[0]: V7_DVDD_COMP_SET bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 11 PLL[0]: MMCM_DRP[31] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 13 PLL[0]: MMCM_DRP[31] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 15 PLL[0]: MMCM_DRP[31] bit 14
virtex7 CMT rect MAIN[13]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 1 PLL[0]: CLKOUT4_LT bit 1 PLL[0]: MMCM_DRP[16] bit 0 PLL[0]: CLKOUT4_LT bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 3 PLL[0]: CLKOUT4_LT bit 3 PLL[0]: MMCM_DRP[16] bit 2 PLL[0]: CLKOUT4_LT bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 5 PLL[0]: CLKOUT4_LT bit 5 PLL[0]: MMCM_DRP[16] bit 4 PLL[0]: CLKOUT4_LT bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 7 PLL[0]: CLKOUT4_HT bit 1 PLL[0]: MMCM_DRP[16] bit 6 PLL[0]: CLKOUT4_HT bit 0
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 9 PLL[0]: CLKOUT4_HT bit 3 PLL[0]: MMCM_DRP[16] bit 8 PLL[0]: CLKOUT4_HT bit 2
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 11 PLL[0]: CLKOUT4_HT bit 5 PLL[0]: MMCM_DRP[16] bit 10 PLL[0]: CLKOUT4_HT bit 4
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 13 PLL[0]: CLKOUT4_PM bit 0 PLL[0]: MMCM_DRP[16] bit 12 PLL[0]: CLKOUT4_EN
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 15 PLL[0]: CLKOUT4_PM bit 2 PLL[0]: MMCM_DRP[16] bit 14 PLL[0]: CLKOUT4_PM bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 1 PLL[0]: CLKOUT4_DT bit 1 PLL[0]: MMCM_DRP[17] bit 0 PLL[0]: CLKOUT4_DT bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 3 PLL[0]: CLKOUT4_DT bit 3 PLL[0]: MMCM_DRP[17] bit 2 PLL[0]: CLKOUT4_DT bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 5 PLL[0]: CLKOUT4_DT bit 5 PLL[0]: MMCM_DRP[17] bit 4 PLL[0]: CLKOUT4_DT bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 7 PLL[0]: CLKOUT4_EDGE PLL[0]: MMCM_DRP[17] bit 6 PLL[0]: CLKOUT4_NOCOUNT
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 9 PLL[0]: CLKOUT4_MX bit 1 PLL[0]: CLKOUT4_CASCADE PLL[0]: MMCM_DRP[17] bit 8 PLL[0]: CLKOUT4_MX bit 0 PLL[0]: CLKOUT4_USE_FINE_PS
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 11 PLL[0]: MMCM_DRP[17] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 13 PLL[0]: MMCM_DRP[17] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 15 PLL[0]: MMCM_DRP[17] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 1 PLL[0]: CLKOUT6_LT bit 1 PLL[0]: MMCM_DRP[18] bit 0 PLL[0]: CLKOUT6_LT bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 3 PLL[0]: CLKOUT6_LT bit 3 PLL[0]: MMCM_DRP[18] bit 2 PLL[0]: CLKOUT6_LT bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 5 PLL[0]: CLKOUT6_LT bit 5 PLL[0]: MMCM_DRP[18] bit 4 PLL[0]: CLKOUT6_LT bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 7 PLL[0]: CLKOUT6_HT bit 1 PLL[0]: MMCM_DRP[18] bit 6 PLL[0]: CLKOUT6_HT bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 9 PLL[0]: CLKOUT6_HT bit 3 PLL[0]: MMCM_DRP[18] bit 8 PLL[0]: CLKOUT6_HT bit 2
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 11 PLL[0]: CLKOUT6_HT bit 5 PLL[0]: MMCM_DRP[18] bit 10 PLL[0]: CLKOUT6_HT bit 4
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 13 PLL[0]: CLKOUT6_PM bit 0 PLL[0]: MMCM_DRP[18] bit 12 PLL[0]: CLKOUT6_EN
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 15 PLL[0]: CLKOUT6_PM bit 2 PLL[0]: MMCM_DRP[18] bit 14 PLL[0]: CLKOUT6_PM bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 1 PLL[0]: CLKOUT6_DT bit 1 PLL[0]: MMCM_DRP[19] bit 0 PLL[0]: CLKOUT6_DT bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 3 PLL[0]: CLKOUT6_DT bit 3 PLL[0]: MMCM_DRP[19] bit 2 PLL[0]: CLKOUT6_DT bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 5 PLL[0]: CLKOUT6_DT bit 5 PLL[0]: MMCM_DRP[19] bit 4 PLL[0]: CLKOUT6_DT bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 7 PLL[0]: CLKOUT6_EDGE PLL[0]: MMCM_DRP[19] bit 6 PLL[0]: CLKOUT6_NOCOUNT
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 9 PLL[0]: CLKOUT6_MX bit 1 PLL[0]: MMCM_DRP[19] bit 8 PLL[0]: CLKOUT6_MX bit 0 PLL[0]: CLKOUT6_USE_FINE_PS
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 11 PLL[0]: CLKFBOUT_PM_FALL bit 0 PLL[0]: MMCM_DRP[19] bit 10 PLL[0]: CLKFBOUT_FRAC_WF_FALL
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 13 PLL[0]: CLKFBOUT_PM_FALL bit 2 PLL[0]: MMCM_DRP[19] bit 12 PLL[0]: CLKFBOUT_PM_FALL bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 15 PLL[0]: MMCM_DRP[19] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 1 PLL[0]: CLKFBOUT_LT bit 1 PLL[0]: MMCM_DRP[20] bit 0 PLL[0]: CLKFBOUT_LT bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 3 PLL[0]: CLKFBOUT_LT bit 3 PLL[0]: MMCM_DRP[20] bit 2 PLL[0]: CLKFBOUT_LT bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 5 PLL[0]: CLKFBOUT_LT bit 5 PLL[0]: MMCM_DRP[20] bit 4 PLL[0]: CLKFBOUT_LT bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 7 PLL[0]: CLKFBOUT_HT bit 1 PLL[0]: MMCM_DRP[20] bit 6 PLL[0]: CLKFBOUT_HT bit 0
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 9 PLL[0]: CLKFBOUT_HT bit 3 PLL[0]: MMCM_DRP[20] bit 8 PLL[0]: CLKFBOUT_HT bit 2
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 11 PLL[0]: CLKFBOUT_HT bit 5 PLL[0]: MMCM_DRP[20] bit 10 PLL[0]: CLKFBOUT_HT bit 4
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 13 PLL[0]: CLKFBOUT_PM_RISE bit 0 PLL[0]: MMCM_DRP[20] bit 12 PLL[0]: CLKFBOUT_EN
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 15 PLL[0]: CLKFBOUT_PM_RISE bit 2 PLL[0]: MMCM_DRP[20] bit 14 PLL[0]: CLKFBOUT_PM_RISE bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 1 PLL[0]: CLKFBOUT_DT bit 1 PLL[0]: MMCM_DRP[21] bit 0 PLL[0]: CLKFBOUT_DT bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 3 PLL[0]: CLKFBOUT_DT bit 3 PLL[0]: MMCM_DRP[21] bit 2 PLL[0]: CLKFBOUT_DT bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 5 PLL[0]: CLKFBOUT_DT bit 5 PLL[0]: MMCM_DRP[21] bit 4 PLL[0]: CLKFBOUT_DT bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 7 PLL[0]: CLKFBOUT_EDGE PLL[0]: MMCM_DRP[21] bit 6 PLL[0]: CLKFBOUT_NOCOUNT
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 9 PLL[0]: CLKFBOUT_MX bit 1 PLL[0]: MMCM_DRP[21] bit 8 PLL[0]: CLKFBOUT_MX bit 0 PLL[0]: CLKFBOUT_USE_FINE_PS
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 11 PLL[0]: CLKFBOUT_FRAC_EN PLL[0]: MMCM_DRP[21] bit 10 PLL[0]: CLKFBOUT_FRAC_WF_RISE
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 13 PLL[0]: CLKFBOUT_FRAC bit 1 PLL[0]: MMCM_DRP[21] bit 12 PLL[0]: CLKFBOUT_FRAC bit 0
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 15 PLL[0]: MMCM_DRP[21] bit 14 PLL[0]: CLKFBOUT_FRAC bit 2
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 1 PLL[0]: DIVCLK_LT bit 1 PLL[0]: MMCM_DRP[22] bit 0 PLL[0]: DIVCLK_LT bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 3 PLL[0]: DIVCLK_LT bit 3 PLL[0]: MMCM_DRP[22] bit 2 PLL[0]: DIVCLK_LT bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 5 PLL[0]: DIVCLK_LT bit 5 PLL[0]: MMCM_DRP[22] bit 4 PLL[0]: DIVCLK_LT bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 7 PLL[0]: DIVCLK_HT bit 1 PLL[0]: MMCM_DRP[22] bit 6 PLL[0]: DIVCLK_HT bit 0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 9 PLL[0]: DIVCLK_HT bit 3 PLL[0]: MMCM_DRP[22] bit 8 PLL[0]: DIVCLK_HT bit 2
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 11 PLL[0]: DIVCLK_HT bit 5 PLL[0]: MMCM_DRP[22] bit 10 PLL[0]: DIVCLK_HT bit 4
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 13 PLL[0]: DIVCLK_EDGE PLL[0]: MMCM_DRP[22] bit 12 PLL[0]: DIVCLK_NOCOUNT
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 15 PLL[0]: MMCM_DRP[22] bit 14
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 1 PLL[0]: CLKFBIN_LT bit 1 PLL[0]: MMCM_DRP[23] bit 0 PLL[0]: CLKFBIN_LT bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 3 PLL[0]: CLKFBIN_LT bit 3 PLL[0]: MMCM_DRP[23] bit 2 PLL[0]: CLKFBIN_LT bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 5 PLL[0]: CLKFBIN_LT bit 5 PLL[0]: MMCM_DRP[23] bit 4 PLL[0]: CLKFBIN_LT bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 7 PLL[0]: CLKFBIN_HT bit 1 PLL[0]: MMCM_DRP[23] bit 6 PLL[0]: CLKFBIN_HT bit 0
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 9 PLL[0]: CLKFBIN_HT bit 3 PLL[0]: MMCM_DRP[23] bit 8 PLL[0]: CLKFBIN_HT bit 2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 11 PLL[0]: CLKFBIN_HT bit 5 PLL[0]: MMCM_DRP[23] bit 10 PLL[0]: CLKFBIN_HT bit 4
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 13 PLL[0]: CLKFBIN_EDGE PLL[0]: MMCM_DRP[23] bit 12 PLL[0]: CLKFBIN_NOCOUNT
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 15 PLL[0]: MMCM_DRP[23] bit 14
virtex7 CMT rect MAIN[14]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 1 PLL[0]: CLKOUT0_LT bit 1 PLL[0]: MMCM_DRP[8] bit 0 PLL[0]: CLKOUT0_LT bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 3 PLL[0]: CLKOUT0_LT bit 3 PLL[0]: MMCM_DRP[8] bit 2 PLL[0]: CLKOUT0_LT bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 5 PLL[0]: CLKOUT0_LT bit 5 PLL[0]: MMCM_DRP[8] bit 4 PLL[0]: CLKOUT0_LT bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 7 PLL[0]: CLKOUT0_HT bit 1 PLL[0]: MMCM_DRP[8] bit 6 PLL[0]: CLKOUT0_HT bit 0
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 9 PLL[0]: CLKOUT0_HT bit 3 PLL[0]: MMCM_DRP[8] bit 8 PLL[0]: CLKOUT0_HT bit 2
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 11 PLL[0]: CLKOUT0_HT bit 5 PLL[0]: MMCM_DRP[8] bit 10 PLL[0]: CLKOUT0_HT bit 4
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 13 PLL[0]: CLKOUT0_PM_RISE bit 0 PLL[0]: MMCM_DRP[8] bit 12 PLL[0]: CLKOUT0_EN
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 15 PLL[0]: CLKOUT0_PM_RISE bit 2 PLL[0]: MMCM_DRP[8] bit 14 PLL[0]: CLKOUT0_PM_RISE bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 1 PLL[0]: CLKOUT0_DT bit 1 PLL[0]: MMCM_DRP[9] bit 0 PLL[0]: CLKOUT0_DT bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 3 PLL[0]: CLKOUT0_DT bit 3 PLL[0]: MMCM_DRP[9] bit 2 PLL[0]: CLKOUT0_DT bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 5 PLL[0]: CLKOUT0_DT bit 5 PLL[0]: MMCM_DRP[9] bit 4 PLL[0]: CLKOUT0_DT bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 7 PLL[0]: CLKOUT0_EDGE PLL[0]: MMCM_DRP[9] bit 6 PLL[0]: CLKOUT0_NOCOUNT
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 9 PLL[0]: CLKOUT0_MX bit 1 PLL[0]: MMCM_DRP[9] bit 8 PLL[0]: CLKOUT0_MX bit 0 PLL[0]: CLKOUT0_USE_FINE_PS
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 11 PLL[0]: CLKOUT0_FRAC_EN PLL[0]: MMCM_DRP[9] bit 10 PLL[0]: CLKOUT0_FRAC_WF_RISE
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 13 PLL[0]: CLKOUT0_FRAC bit 1 PLL[0]: MMCM_DRP[9] bit 12 PLL[0]: CLKOUT0_FRAC bit 0
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 15 PLL[0]: MMCM_DRP[9] bit 14 PLL[0]: CLKOUT0_FRAC bit 2
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 1 PLL[0]: CLKOUT1_LT bit 1 PLL[0]: MMCM_DRP[10] bit 0 PLL[0]: CLKOUT1_LT bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 3 PLL[0]: CLKOUT1_LT bit 3 PLL[0]: MMCM_DRP[10] bit 2 PLL[0]: CLKOUT1_LT bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 5 PLL[0]: CLKOUT1_LT bit 5 PLL[0]: MMCM_DRP[10] bit 4 PLL[0]: CLKOUT1_LT bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 7 PLL[0]: CLKOUT1_HT bit 1 PLL[0]: MMCM_DRP[10] bit 6 PLL[0]: CLKOUT1_HT bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 9 PLL[0]: CLKOUT1_HT bit 3 PLL[0]: MMCM_DRP[10] bit 8 PLL[0]: CLKOUT1_HT bit 2
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 11 PLL[0]: CLKOUT1_HT bit 5 PLL[0]: MMCM_DRP[10] bit 10 PLL[0]: CLKOUT1_HT bit 4
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 13 PLL[0]: CLKOUT1_PM bit 0 PLL[0]: MMCM_DRP[10] bit 12 PLL[0]: CLKOUT1_EN
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 15 PLL[0]: CLKOUT1_PM bit 2 PLL[0]: MMCM_DRP[10] bit 14 PLL[0]: CLKOUT1_PM bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 1 PLL[0]: CLKOUT1_DT bit 1 PLL[0]: MMCM_DRP[11] bit 0 PLL[0]: CLKOUT1_DT bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 3 PLL[0]: CLKOUT1_DT bit 3 PLL[0]: MMCM_DRP[11] bit 2 PLL[0]: CLKOUT1_DT bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 5 PLL[0]: CLKOUT1_DT bit 5 PLL[0]: MMCM_DRP[11] bit 4 PLL[0]: CLKOUT1_DT bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 7 PLL[0]: CLKOUT1_EDGE PLL[0]: MMCM_DRP[11] bit 6 PLL[0]: CLKOUT1_NOCOUNT
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 9 PLL[0]: CLKOUT1_MX bit 1 PLL[0]: MMCM_DRP[11] bit 8 PLL[0]: CLKOUT1_MX bit 0 PLL[0]: CLKOUT1_USE_FINE_PS
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 11 PLL[0]: MMCM_DRP[11] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 13 PLL[0]: MMCM_DRP[11] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 15 PLL[0]: MMCM_DRP[11] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 1 PLL[0]: CLKOUT2_LT bit 1 PLL[0]: MMCM_DRP[12] bit 0 PLL[0]: CLKOUT2_LT bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 3 PLL[0]: CLKOUT2_LT bit 3 PLL[0]: MMCM_DRP[12] bit 2 PLL[0]: CLKOUT2_LT bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 5 PLL[0]: CLKOUT2_LT bit 5 PLL[0]: MMCM_DRP[12] bit 4 PLL[0]: CLKOUT2_LT bit 4
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 7 PLL[0]: CLKOUT2_HT bit 1 PLL[0]: MMCM_DRP[12] bit 6 PLL[0]: CLKOUT2_HT bit 0
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 9 PLL[0]: CLKOUT2_HT bit 3 PLL[0]: MMCM_DRP[12] bit 8 PLL[0]: CLKOUT2_HT bit 2
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 11 PLL[0]: CLKOUT2_HT bit 5 PLL[0]: MMCM_DRP[12] bit 10 PLL[0]: CLKOUT2_HT bit 4
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 13 PLL[0]: CLKOUT2_PM bit 0 PLL[0]: MMCM_DRP[12] bit 12 PLL[0]: CLKOUT2_EN
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 15 PLL[0]: CLKOUT2_PM bit 2 PLL[0]: MMCM_DRP[12] bit 14 PLL[0]: CLKOUT2_PM bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 1 PLL[0]: CLKOUT2_DT bit 1 PLL[0]: MMCM_DRP[13] bit 0 PLL[0]: CLKOUT2_DT bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 3 PLL[0]: CLKOUT2_DT bit 3 PLL[0]: MMCM_DRP[13] bit 2 PLL[0]: CLKOUT2_DT bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 5 PLL[0]: CLKOUT2_DT bit 5 PLL[0]: MMCM_DRP[13] bit 4 PLL[0]: CLKOUT2_DT bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 7 PLL[0]: CLKOUT2_EDGE PLL[0]: MMCM_DRP[13] bit 6 PLL[0]: CLKOUT2_NOCOUNT
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 9 PLL[0]: CLKOUT2_MX bit 1 PLL[0]: MMCM_DRP[13] bit 8 PLL[0]: CLKOUT2_MX bit 0 PLL[0]: CLKOUT2_USE_FINE_PS
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 11 PLL[0]: MMCM_DRP[13] bit 10
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 13 PLL[0]: MMCM_DRP[13] bit 12
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 15 PLL[0]: MMCM_DRP[13] bit 14
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 1 PLL[0]: CLKOUT3_LT bit 1 PLL[0]: MMCM_DRP[14] bit 0 PLL[0]: CLKOUT3_LT bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 3 PLL[0]: CLKOUT3_LT bit 3 PLL[0]: MMCM_DRP[14] bit 2 PLL[0]: CLKOUT3_LT bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 5 PLL[0]: CLKOUT3_LT bit 5 PLL[0]: MMCM_DRP[14] bit 4 PLL[0]: CLKOUT3_LT bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 7 PLL[0]: CLKOUT3_HT bit 1 PLL[0]: MMCM_DRP[14] bit 6 PLL[0]: CLKOUT3_HT bit 0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 9 PLL[0]: CLKOUT3_HT bit 3 PLL[0]: MMCM_DRP[14] bit 8 PLL[0]: CLKOUT3_HT bit 2
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 11 PLL[0]: CLKOUT3_HT bit 5 PLL[0]: MMCM_DRP[14] bit 10 PLL[0]: CLKOUT3_HT bit 4
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 13 PLL[0]: CLKOUT3_PM bit 0 PLL[0]: MMCM_DRP[14] bit 12 PLL[0]: CLKOUT3_EN
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 15 PLL[0]: CLKOUT3_PM bit 2 PLL[0]: MMCM_DRP[14] bit 14 PLL[0]: CLKOUT3_PM bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 1 PLL[0]: CLKOUT3_DT bit 1 PLL[0]: MMCM_DRP[15] bit 0 PLL[0]: CLKOUT3_DT bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 3 PLL[0]: CLKOUT3_DT bit 3 PLL[0]: MMCM_DRP[15] bit 2 PLL[0]: CLKOUT3_DT bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 5 PLL[0]: CLKOUT3_DT bit 5 PLL[0]: MMCM_DRP[15] bit 4 PLL[0]: CLKOUT3_DT bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 7 PLL[0]: CLKOUT3_EDGE PLL[0]: MMCM_DRP[15] bit 6 PLL[0]: CLKOUT3_NOCOUNT
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 9 PLL[0]: CLKOUT3_MX bit 1 PLL[0]: MMCM_DRP[15] bit 8 PLL[0]: CLKOUT3_MX bit 0 PLL[0]: CLKOUT3_USE_FINE_PS
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 11 PLL[0]: MMCM_DRP[15] bit 10
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 13 PLL[0]: MMCM_DRP[15] bit 12
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 15 PLL[0]: MMCM_DRP[15] bit 14
virtex7 CMT rect MAIN[15]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[1] bit 3 PLL[0]: MMCM_DRP[0] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[0] bit 3 PLL[0]: MMCM_DRP[0] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[3] bit 3 PLL[0]: MMCM_DRP[0] bit 3 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[2] bit 3 PLL[0]: MMCM_DRP[0] bit 2
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 5 PLL[0]: MMCM_DRP[0] bit 4
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 7 PLL[0]: IN_DLY_MX_CVDD bit 1 PLL[0]: MMCM_DRP[0] bit 6 PLL[0]: IN_DLY_MX_CVDD bit 0
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 9 PLL[0]: IN_DLY_MX_CVDD bit 3 PLL[0]: MMCM_DRP[0] bit 8 PLL[0]: IN_DLY_MX_CVDD bit 2
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 11 PLL[0]: IN_DLY_MX_CVDD bit 5 PLL[0]: MMCM_DRP[0] bit 10 PLL[0]: IN_DLY_MX_CVDD bit 4
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 13 PLL[0]: HROW_DLY_SET bit 1 PLL[0]: MMCM_DRP[0] bit 12 PLL[0]: HROW_DLY_SET bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[0] bit 0 PLL[0]: MMCM_DRP[0] bit 15 PLL[0]: MMCM_DRP[0] bit 14 PLL[0]: HROW_DLY_SET bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[0] bit 1 PLL[0]: MMCM_DRP[1] bit 1 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[0] bit 2 PLL[0]: MMCM_DRP[1] bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[0] bit 2 PLL[0]: MMCM_DRP[1] bit 3 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[0] bit 0 PLL[0]: MMCM_DRP[1] bit 2
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[0] bit 0 PLL[0]: MMCM_DRP[1] bit 5 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[0] bit 1 PLL[0]: MMCM_DRP[1] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[0] bit 1 PLL[0]: MMCM_DRP[1] bit 7 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[0] bit 2 PLL[0]: MMCM_DRP[1] bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_S[1] ← CELL[25].OUT_PLL_S[2] PLL[0]: MMCM_DRP[1] bit 9 SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_S[0] ← CELL[25].OUT_PLL_S[0] PLL[0]: MMCM_DRP[1] bit 8
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_S[3] ← CELL[25].OUT_PLL_S[6] PLL[0]: MMCM_DRP[1] bit 11 SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_S[2] ← CELL[25].OUT_PLL_S[4] PLL[0]: MMCM_DRP[1] bit 10
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[1] bit 13 PLL[0]: MMCM_DRP[1] bit 12
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[1] bit 15 PLL[0]: MMCM_DRP[1] bit 14
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 1 PLL[0]: SYNTH_CLK_DIV bit 1 PLL[0]: MMCM_DRP[2] bit 0 PLL[0]: SYNTH_CLK_DIV bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 3 PLL[0]: MMCM_DRP[2] bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 5 PLL[0]: MMCM_DRP[2] bit 4
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 7 PLL[0]: MMCM_DRP[2] bit 6
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 9 PLL[0]: MMCM_DRP[2] bit 8
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 11 PLL[0]: MMCM_DRP[2] bit 10
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 13 PLL[0]: MMCM_DRP[2] bit 12
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 15 PLL[0]: MMCM_DRP[2] bit 14
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 1 PLL[0]: SKEW_FLOP_INV bit 1 PLL[0]: MMCM_DRP[3] bit 0 PLL[0]: SKEW_FLOP_INV bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 3 PLL[0]: SKEW_FLOP_INV bit 3 PLL[0]: MMCM_DRP[3] bit 2 PLL[0]: SKEW_FLOP_INV bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[0] bit 1 PLL[0]: MMCM_DRP[3] bit 5 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[0] bit 2 PLL[0]: MMCM_DRP[3] bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[1] bit 2 PLL[0]: MMCM_DRP[3] bit 7 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[0] bit 0 PLL[0]: MMCM_DRP[3] bit 6
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[1] bit 0 PLL[0]: MMCM_DRP[3] bit 9 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[1] bit 1 PLL[0]: MMCM_DRP[3] bit 8
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[2] bit 1 PLL[0]: MMCM_DRP[3] bit 11 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[2] bit 2 PLL[0]: MMCM_DRP[3] bit 10
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[3] bit 2 PLL[0]: MMCM_DRP[3] bit 13 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[2] bit 0 PLL[0]: MMCM_DRP[3] bit 12
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_PERF[3] bit 0 PLL[0]: MMCM_DRP[3] bit 15 SPEC_INT: mux CELL[25].OMUX_PLL_PERF[3] bit 1 PLL[0]: MMCM_DRP[3] bit 14
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 1 PLL[0]: SS_STEPS bit 1 PLL[0]: MMCM_DRP[4] bit 0 PLL[0]: SS_STEPS bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 3 PLL[0]: SS_STEPS_INIT bit 0 PLL[0]: MMCM_DRP[4] bit 2 PLL[0]: SS_STEPS bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 5 PLL[0]: SS_STEPS_INIT bit 2 PLL[0]: MMCM_DRP[4] bit 4 PLL[0]: SS_STEPS_INIT bit 1
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 7 PLL[0]: MMCM_DRP[4] bit 6
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 9 PLL[0]: CLKBURST_CNT bit 1 PLL[0]: MMCM_DRP[4] bit 8 PLL[0]: CLKBURST_CNT bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 11 PLL[0]: CLKBURST_CNT bit 3 PLL[0]: MMCM_DRP[4] bit 10 PLL[0]: CLKBURST_CNT bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 13 PLL[0]: CLKBURST_REPEAT PLL[0]: MMCM_DRP[4] bit 12 PLL[0]: CLKBURST_ENABLE
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 15 PLL[0]: TMUX_MUX_SEL bit 1 PLL[0]: MMCM_DRP[4] bit 14 PLL[0]: TMUX_MUX_SEL bit 0
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 1 PLL[0]: MMCM_DRP[5] bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 3 PLL[0]: DIRECT_PATH_CNTRL PLL[0]: MMCM_DRP[5] bit 2 PLL[0]: IN_DLY_EN
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 5 PLL[0]: IN_DLY_MX_DVDD bit 1 PLL[0]: MMCM_DRP[5] bit 4 PLL[0]: IN_DLY_MX_DVDD bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 7 PLL[0]: IN_DLY_MX_DVDD bit 3 PLL[0]: MMCM_DRP[5] bit 6 PLL[0]: IN_DLY_MX_DVDD bit 2
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 9 PLL[0]: IN_DLY_MX_DVDD bit 5 PLL[0]: MMCM_DRP[5] bit 8 PLL[0]: IN_DLY_MX_DVDD bit 4
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 11 PLL[0]: V7_IN_DLY_SET bit 1 PLL[0]: MMCM_DRP[5] bit 10 PLL[0]: V7_IN_DLY_SET bit 0
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 13 PLL[0]: V7_IN_DLY_SET bit 3 PLL[0]: MMCM_DRP[5] bit 12 PLL[0]: V7_IN_DLY_SET bit 2
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 15 PLL[0]: V7_IN_DLY_SET bit 5 PLL[0]: MMCM_DRP[5] bit 14 PLL[0]: V7_IN_DLY_SET bit 4
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 1 PLL[0]: CLKOUT5_LT bit 1 PLL[0]: MMCM_DRP[6] bit 0 PLL[0]: CLKOUT5_LT bit 0
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 3 PLL[0]: CLKOUT5_LT bit 3 PLL[0]: MMCM_DRP[6] bit 2 PLL[0]: CLKOUT5_LT bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 5 PLL[0]: CLKOUT5_LT bit 5 PLL[0]: MMCM_DRP[6] bit 4 PLL[0]: CLKOUT5_LT bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 7 PLL[0]: CLKOUT5_HT bit 1 PLL[0]: MMCM_DRP[6] bit 6 PLL[0]: CLKOUT5_HT bit 0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 9 PLL[0]: CLKOUT5_HT bit 3 PLL[0]: MMCM_DRP[6] bit 8 PLL[0]: CLKOUT5_HT bit 2
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 11 PLL[0]: CLKOUT5_HT bit 5 PLL[0]: MMCM_DRP[6] bit 10 PLL[0]: CLKOUT5_HT bit 4
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 13 PLL[0]: CLKOUT5_PM bit 0 PLL[0]: MMCM_DRP[6] bit 12 PLL[0]: CLKOUT5_EN
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 15 PLL[0]: CLKOUT5_PM bit 2 PLL[0]: MMCM_DRP[6] bit 14 PLL[0]: CLKOUT5_PM bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 1 PLL[0]: CLKOUT5_DT bit 1 PLL[0]: MMCM_DRP[7] bit 0 PLL[0]: CLKOUT5_DT bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 3 PLL[0]: CLKOUT5_DT bit 3 PLL[0]: MMCM_DRP[7] bit 2 PLL[0]: CLKOUT5_DT bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 5 PLL[0]: CLKOUT5_DT bit 5 PLL[0]: MMCM_DRP[7] bit 4 PLL[0]: CLKOUT5_DT bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 7 PLL[0]: CLKOUT5_EDGE PLL[0]: MMCM_DRP[7] bit 6 PLL[0]: CLKOUT5_NOCOUNT
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 9 PLL[0]: CLKOUT5_MX bit 1 PLL[0]: MMCM_DRP[7] bit 8 PLL[0]: CLKOUT5_MX bit 0 PLL[0]: CLKOUT5_USE_FINE_PS
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 11 PLL[0]: CLKOUT0_PM_FALL bit 0 PLL[0]: MMCM_DRP[7] bit 10 PLL[0]: CLKOUT0_FRAC_WF_FALL
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 13 PLL[0]: CLKOUT0_PM_FALL bit 2 PLL[0]: MMCM_DRP[7] bit 12 PLL[0]: CLKOUT0_PM_FALL bit 1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 15 PLL[0]: MMCM_DRP[7] bit 14
virtex7 CMT rect MAIN[16]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[3] bit 1 -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[2] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[3] bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[1] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[2] bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[0] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[1] bit 0
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_S[0] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[3] bit 0 -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[2] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 5
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[1] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 5
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[0] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 5
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 2 SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[3]) bit 1
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 2 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[2]) bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[1]) bit 1
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 3 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[0]) bit 1
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 3 SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[3] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 3 SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[2] bit 1
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 3 SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[1] bit 1
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 1 SPEC_INT: mux CELL[25].CMT_FREQ_BB_S[0] bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[3]) bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[2]) bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[1]) bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_S[0]) bit 0
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CMT_SYNC_BB ← CELL[25].CMT_SYNC_BB_S -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CMT_SYNC_BB_S ← CELL[25].CMT_SYNC_BB SPEC_INT: wire support (CELL[25].CMT_SYNC_BB) bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 1 -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 1 SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 1
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 2
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_SYNC_BB_S) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 2
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[17]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV bit 2 PHASER_OUT[0]: CLKOUT_DIV bit 3
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV bit 0 PHASER_OUT[0]: CLKOUT_DIV bit 1
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: DATA_CTL_N PHASER_OUT[0]: CTL_MODE bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: OCLK_DELAY bit 5 PHASER_OUT[0]: EN_TEST_RING
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: OCLK_DELAY bit 3 PHASER_OUT[0]: OCLK_DELAY bit 4
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: OCLK_DELAY bit 1 PHASER_OUT[0]: OCLK_DELAY bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: STG1_BYPASS bit 0 PHASER_OUT[0]: OCLK_DELAY bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: OUTPUT_CLK_SRC bit 0 PHASER_OUT[0]: OUTPUT_CLK_SRC bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: EN_OSERDES_RST PHASER_OUT[0]: COARSE_BYPASS
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: OCLKDELAY_INV PHASER_OUT[0]: PHASER_OUT_EN
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 10 PHASER_OUT[0]: DATA_RD_CYCLES
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 8 PHASER_OUT[0]: TEST_OPT bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 6 PHASER_OUT[0]: TEST_OPT bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 4 PHASER_OUT[0]: TEST_OPT bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 2 PHASER_OUT[0]: TEST_OPT bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: TEST_OPT bit 0 PHASER_OUT[0]: TEST_OPT bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[18]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: RST_SEL bit 0 PHASER_IN[0]: REG_OPT_2 bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: HALF_CYCLE_ADJ PHASER_IN[0]: SEL_CLK_OFFSET bit 2
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: STG1_PD_UPDATE bit 1 PHASER_IN[0]: STG1_PD_UPDATE bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: OUTPUT_CLK_SRC bit 3 PHASER_IN[0]: STG1_PD_UPDATE bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: ICLK_TO_RCLK_BYPASS PHASER_IN[0]: OUTPUT_CLK_SRC bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: PHASER_IN_EN PHASER_IN[0]: EN_ISERDES_RST
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: OUTPUT_CLK_SRC bit 1 PHASER_IN[0]: WR_CYCLES
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: SEL_CLK_OFFSET bit 1 PHASER_IN[0]: OUTPUT_CLK_SRC bit 0
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: SEL_OUT bit 0 PHASER_IN[0]: SEL_CLK_OFFSET bit 0
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: RD_ADDR_INIT bit 0 PHASER_IN[0]: RD_ADDR_INIT bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: REG_OPT_1 bit 0 PHASER_IN[0]: REG_OPT_4 bit 0
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: DQS_AUTO_RECAL bit 0 PHASER_IN[0]: DQS_BIAS_MODE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: UPDATE_NONACTIVE PHASER_IN[0]: TEST_BP bit 0
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV bit 6 PHASER_OUT[0]: CLKOUT_DIV bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV bit 4 PHASER_OUT[0]: CLKOUT_DIV bit 5
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV_ST bit 2 PHASER_OUT[0]: CLKOUT_DIV_ST bit 3
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: CLKOUT_DIV_ST bit 0 PHASER_OUT[0]: CLKOUT_DIV_ST bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: FINE_DELAY bit 5 PHASER_OUT[0]: SYNC_IN_DIV_RST
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: FINE_DELAY bit 3 PHASER_OUT[0]: FINE_DELAY bit 4
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: FINE_DELAY bit 1 PHASER_OUT[0]: FINE_DELAY bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: COARSE_DELAY bit 5 PHASER_OUT[0]: FINE_DELAY bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: COARSE_DELAY bit 3 PHASER_OUT[0]: COARSE_DELAY bit 4
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: COARSE_DELAY bit 1 PHASER_OUT[0]: COARSE_DELAY bit 2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0] bit 3 PHASER_OUT[0]: COARSE_DELAY bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0] bit 1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[0]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[0] bit 0
virtex7 CMT rect MAIN[19]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV bit 7 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV bit 5 PHASER_IN[0]: CLKOUT_DIV bit 6
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV_ST bit 3 PHASER_IN[0]: CLKOUT_DIV bit 4
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV_ST bit 1 PHASER_IN[0]: CLKOUT_DIV_ST bit 2
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: SYNC_IN_DIV_RST PHASER_IN[0]: CLKOUT_DIV_ST bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: FINE_DELAY bit 4 PHASER_IN[0]: FINE_DELAY bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: FINE_DELAY bit 2 PHASER_IN[0]: FINE_DELAY bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: FINE_DELAY bit 0 PHASER_IN[0]: FINE_DELAY bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0] bit 3 -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[0] bit 1
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV bit 3 PHASER_IN[0]: BURST_MODE
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CLKOUT_DIV bit 1 PHASER_IN[0]: CLKOUT_DIV bit 2
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: CTL_MODE bit 0 PHASER_IN[0]: CLKOUT_DIV bit 0
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: DQS_FIND_PATTERN bit 2 PHASER_IN[0]: EN_TEST_RING
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: DQS_FIND_PATTERN bit 0 PHASER_IN[0]: DQS_FIND_PATTERN bit 1
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: FREQ_REF_DIV bit 0 PHASER_IN[0]: FREQ_REF_DIV bit 1
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: PD_REVERSE bit 2 -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[0]: PD_REVERSE bit 0 PHASER_IN[0]: PD_REVERSE bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[20]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV bit 2 PHASER_OUT[1]: CLKOUT_DIV bit 3
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV bit 0 PHASER_OUT[1]: CLKOUT_DIV bit 1
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: DATA_CTL_N PHASER_OUT[1]: CTL_MODE bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: OCLK_DELAY bit 5 PHASER_OUT[1]: EN_TEST_RING
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: OCLK_DELAY bit 3 PHASER_OUT[1]: OCLK_DELAY bit 4
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: OCLK_DELAY bit 1 PHASER_OUT[1]: OCLK_DELAY bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: STG1_BYPASS bit 0 PHASER_OUT[1]: OCLK_DELAY bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: OUTPUT_CLK_SRC bit 0 PHASER_OUT[1]: OUTPUT_CLK_SRC bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: EN_OSERDES_RST PHASER_OUT[1]: COARSE_BYPASS
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: OCLKDELAY_INV PHASER_OUT[1]: PHASER_OUT_EN
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 10 PHASER_OUT[1]: DATA_RD_CYCLES
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 8 PHASER_OUT[1]: TEST_OPT bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 6 PHASER_OUT[1]: TEST_OPT bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 4 PHASER_OUT[1]: TEST_OPT bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 2 PHASER_OUT[1]: TEST_OPT bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: TEST_OPT bit 0 PHASER_OUT[1]: TEST_OPT bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[21]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV bit 6 PHASER_OUT[1]: CLKOUT_DIV bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV bit 4 PHASER_OUT[1]: CLKOUT_DIV bit 5
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV_ST bit 2 PHASER_OUT[1]: CLKOUT_DIV_ST bit 3
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: CLKOUT_DIV_ST bit 0 PHASER_OUT[1]: CLKOUT_DIV_ST bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: FINE_DELAY bit 5 PHASER_OUT[1]: SYNC_IN_DIV_RST
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: FINE_DELAY bit 3 PHASER_OUT[1]: FINE_DELAY bit 4
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: FINE_DELAY bit 1 PHASER_OUT[1]: FINE_DELAY bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: COARSE_DELAY bit 5 PHASER_OUT[1]: FINE_DELAY bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: COARSE_DELAY bit 3 PHASER_OUT[1]: COARSE_DELAY bit 4
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: COARSE_DELAY bit 1 PHASER_OUT[1]: COARSE_DELAY bit 2
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1] bit 3 PHASER_OUT[1]: COARSE_DELAY bit 0
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1] bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[1]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[1] bit 0
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[22]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1] bit 3 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1] bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV bit 3 PHASER_IN[1]: BURST_MODE
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV bit 1 PHASER_IN[1]: CLKOUT_DIV bit 2
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CTL_MODE bit 0 PHASER_IN[1]: CLKOUT_DIV bit 0
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: DQS_FIND_PATTERN bit 2 PHASER_IN[1]: EN_TEST_RING
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: DQS_FIND_PATTERN bit 0 PHASER_IN[1]: DQS_FIND_PATTERN bit 1
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: FREQ_REF_DIV bit 0 PHASER_IN[1]: FREQ_REF_DIV bit 1
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: PD_REVERSE bit 2 -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: PD_REVERSE bit 0 PHASER_IN[1]: PD_REVERSE bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: RST_SEL bit 0 PHASER_IN[1]: REG_OPT_2 bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: HALF_CYCLE_ADJ PHASER_IN[1]: SEL_CLK_OFFSET bit 2
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[1] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: STG1_PD_UPDATE bit 1 PHASER_IN[1]: STG1_PD_UPDATE bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: OUTPUT_CLK_SRC bit 3 PHASER_IN[1]: STG1_PD_UPDATE bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: ICLK_TO_RCLK_BYPASS PHASER_IN[1]: OUTPUT_CLK_SRC bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: PHASER_IN_EN PHASER_IN[1]: EN_ISERDES_RST
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: OUTPUT_CLK_SRC bit 1 PHASER_IN[1]: WR_CYCLES
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: SEL_CLK_OFFSET bit 1 PHASER_IN[1]: OUTPUT_CLK_SRC bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: SEL_OUT bit 0 PHASER_IN[1]: SEL_CLK_OFFSET bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: RD_ADDR_INIT bit 0 PHASER_IN[1]: RD_ADDR_INIT bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: REG_OPT_1 bit 0 PHASER_IN[1]: REG_OPT_4 bit 0
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: DQS_AUTO_RECAL bit 0 PHASER_IN[1]: DQS_BIAS_MODE
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: UPDATE_NONACTIVE PHASER_IN[1]: TEST_BP bit 0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[23]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV bit 7 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV bit 5 PHASER_IN[1]: CLKOUT_DIV bit 6
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV_ST bit 3 PHASER_IN[1]: CLKOUT_DIV bit 4
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: CLKOUT_DIV_ST bit 1 PHASER_IN[1]: CLKOUT_DIV_ST bit 2
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: SYNC_IN_DIV_RST PHASER_IN[1]: CLKOUT_DIV_ST bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: FINE_DELAY bit 4 PHASER_IN[1]: FINE_DELAY bit 5
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: FINE_DELAY bit 2 PHASER_IN[1]: FINE_DELAY bit 3
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[1]: FINE_DELAY bit 0 PHASER_IN[1]: FINE_DELAY bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[24]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CCIO_CMT[1] ← IO[28].OUT_CLKPAD SPEC_INT: buffer CELL[25].CCIO_CMT[0] ← IO[26].OUT_CLKPAD SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 0
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CCIO_CMT[3] ← IO[24].OUT_CLKPAD SPEC_INT: buffer CELL[25].CCIO_CMT[2] ← IO[22].OUT_CLKPAD SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_CCIO[0] bit 0 SPEC_INT: mux CELL[25].OMUX_CCIO[0] bit 2 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 3 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 3
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_CCIO[1] bit 2 SPEC_INT: mux CELL[25].OMUX_CCIO[0] bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 3 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 3
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 9 SPEC_INT: mux CELL[25].HROW_O[0] bit 8 SPEC_INT: mux CELL[25].HROW_O[1] bit 9 SPEC_INT: mux CELL[25].HROW_O[1] bit 8
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 11 SPEC_INT: mux CELL[25].HROW_O[0] bit 10 SPEC_INT: mux CELL[25].HROW_O[1] bit 11 SPEC_INT: mux CELL[25].HROW_O[1] bit 10
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 13 SPEC_INT: mux CELL[25].HROW_O[0] bit 12 SPEC_INT: mux CELL[25].HROW_O[1] bit 13 SPEC_INT: mux CELL[25].HROW_O[1] bit 12
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 2 SPEC_INT: mux CELL[25].HROW_O[0] bit 3 SPEC_INT: mux CELL[25].HROW_O[1] bit 2 SPEC_INT: mux CELL[25].HROW_O[1] bit 3
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 1 SPEC_INT: mux CELL[25].HROW_O[0] bit 6 SPEC_INT: mux CELL[25].HROW_O[1] bit 1 SPEC_INT: mux CELL[25].HROW_O[1] bit 6
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 5 SPEC_INT: mux CELL[25].HROW_O[0] bit 0 SPEC_INT: mux CELL[25].HROW_O[1] bit 5 SPEC_INT: mux CELL[25].HROW_O[1] bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[0] bit 7 SPEC_INT: mux CELL[25].HROW_O[0] bit 4 SPEC_INT: mux CELL[25].HROW_O[1] bit 7 SPEC_INT: mux CELL[25].HROW_O[1] bit 4
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 9 SPEC_INT: mux CELL[25].HROW_O[2] bit 8 SPEC_INT: mux CELL[25].HROW_O[3] bit 9 SPEC_INT: mux CELL[25].HROW_O[3] bit 8
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 11 SPEC_INT: mux CELL[25].HROW_O[2] bit 10 SPEC_INT: mux CELL[25].HROW_O[3] bit 11 SPEC_INT: mux CELL[25].HROW_O[3] bit 10
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 13 SPEC_INT: mux CELL[25].HROW_O[2] bit 12 SPEC_INT: mux CELL[25].HROW_O[3] bit 13 SPEC_INT: mux CELL[25].HROW_O[3] bit 12
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 2 SPEC_INT: mux CELL[25].HROW_O[2] bit 3 SPEC_INT: mux CELL[25].HROW_O[3] bit 2 SPEC_INT: mux CELL[25].HROW_O[3] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 1 SPEC_INT: mux CELL[25].HROW_O[2] bit 6 SPEC_INT: mux CELL[25].HROW_O[3] bit 1 SPEC_INT: mux CELL[25].HROW_O[3] bit 6
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 5 SPEC_INT: mux CELL[25].HROW_O[2] bit 0 SPEC_INT: mux CELL[25].HROW_O[3] bit 5 SPEC_INT: mux CELL[25].HROW_O[3] bit 0
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[2] bit 7 SPEC_INT: mux CELL[25].HROW_O[2] bit 4 SPEC_INT: mux CELL[25].HROW_O[3] bit 7 SPEC_INT: mux CELL[25].HROW_O[3] bit 4
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 9 SPEC_INT: mux CELL[25].HROW_O[4] bit 8 SPEC_INT: mux CELL[25].HROW_O[5] bit 9 SPEC_INT: mux CELL[25].HROW_O[5] bit 8
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 11 SPEC_INT: mux CELL[25].HROW_O[4] bit 10 SPEC_INT: mux CELL[25].HROW_O[5] bit 11 SPEC_INT: mux CELL[25].HROW_O[5] bit 10
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 13 SPEC_INT: mux CELL[25].HROW_O[4] bit 12 SPEC_INT: mux CELL[25].HROW_O[5] bit 13 SPEC_INT: mux CELL[25].HROW_O[5] bit 12
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 2 SPEC_INT: mux CELL[25].HROW_O[4] bit 3 SPEC_INT: mux CELL[25].HROW_O[5] bit 2 SPEC_INT: mux CELL[25].HROW_O[5] bit 3
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 1 SPEC_INT: mux CELL[25].HROW_O[4] bit 6 SPEC_INT: mux CELL[25].HROW_O[5] bit 1 SPEC_INT: mux CELL[25].HROW_O[5] bit 6
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 5 SPEC_INT: mux CELL[25].HROW_O[4] bit 0 SPEC_INT: mux CELL[25].HROW_O[5] bit 5 SPEC_INT: mux CELL[25].HROW_O[5] bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[4] bit 7 SPEC_INT: mux CELL[25].HROW_O[4] bit 4 SPEC_INT: mux CELL[25].HROW_O[5] bit 7 SPEC_INT: mux CELL[25].HROW_O[5] bit 4
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 9 SPEC_INT: mux CELL[25].HROW_O[6] bit 8 SPEC_INT: buffer CELL[25].PERF_IN_PLL[1] ← CELL[25].OMUX_PLL_PERF[1] SPEC_INT: buffer CELL[25].PERF_IN_PLL[0] ← CELL[25].OMUX_PLL_PERF[0]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 11 SPEC_INT: mux CELL[25].HROW_O[6] bit 10 SPEC_INT: buffer CELL[25].PERF_IN_PLL[3] ← CELL[25].OMUX_PLL_PERF[3] SPEC_INT: buffer CELL[25].PERF_IN_PLL[2] ← CELL[25].OMUX_PLL_PERF[2]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 13 SPEC_INT: mux CELL[25].HROW_O[6] bit 12 SPEC_INT: buffer CELL[25].PERF_IN_PHASER[1] ← CELL[25].OUT_PHASER_IN_RCLK[1] SPEC_INT: buffer CELL[25].PERF_IN_PHASER[0] ← CELL[25].OUT_PHASER_IN_RCLK[0]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 2 SPEC_INT: mux CELL[25].HROW_O[6] bit 3 SPEC_INT: buffer CELL[25].PERF_IN_PHASER[3] ← CELL[25].OUT_PHASER_IN_RCLK[3] SPEC_INT: buffer CELL[25].PERF_IN_PHASER[2] ← CELL[25].OUT_PHASER_IN_RCLK[2]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 1 SPEC_INT: mux CELL[25].HROW_O[6] bit 6 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 5 SPEC_INT: mux CELL[25].HROW_O[6] bit 0 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[6] bit 7 SPEC_INT: mux CELL[25].HROW_O[6] bit 4 - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 1 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 0 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 3 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 2 - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 5 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 4 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 9 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 10 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 7 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 8 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 0 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[0] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 0 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 1 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 1
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 4 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 3 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 4 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 3
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 10 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 5 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 10 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 5
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 8 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 9 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 8 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 9
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[0] bit 7 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[0] bit 7
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 1 SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 0 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 1 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 3 SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 2 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 3 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 2
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 5 SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 4 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 5 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 4
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 7 SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 8 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 7 SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 8
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_CCIO[1] bit 0 SPEC_INT: mux CELL[25].LCLK_CMT_S[0] bit 6 - SPEC_INT: mux CELL[25].LCLK_CMT_S[1] bit 6
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[25]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 6 SPEC_INT: mux CELL[25].OMUX_CCIO[1] bit 1 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 6 -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 8 SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 7 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 8 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 7
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 4 SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 5 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 4 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 5
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 2 SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 3 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 2 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 3
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 0 SPEC_INT: mux CELL[25].LCLK_CMT_N[0] bit 1 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 0 SPEC_INT: mux CELL[25].LCLK_CMT_N[1] bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 7 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 7 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 6
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 9 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 8 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 9 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 8
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 5 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 10 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 5 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 10
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 3 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 4 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 3 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 4
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 1 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 1 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2_HCLK[1] bit 0 - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1_HCLK[1] bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 8 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 7 - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 10 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 9 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 4 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 5 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 3 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 0 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB_HCLK[1] bit 1 - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 4 SPEC_INT: mux CELL[25].HROW_O[13] bit 7 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 0 SPEC_INT: mux CELL[25].HROW_O[13] bit 5 - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 6 SPEC_INT: mux CELL[25].HROW_O[13] bit 1 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 3 SPEC_INT: mux CELL[25].HROW_O[13] bit 2 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 12 SPEC_INT: mux CELL[25].HROW_O[13] bit 13 SPEC_INT: mux CELL[25].OMUX_CCIO[3] bit 0 SPEC_INT: mux CELL[25].OMUX_CCIO[3] bit 1
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 10 SPEC_INT: mux CELL[25].HROW_O[13] bit 11 SPEC_INT: mux CELL[25].OMUX_CCIO[2] bit 1 SPEC_INT: mux CELL[25].OMUX_CCIO[3] bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[13] bit 8 SPEC_INT: mux CELL[25].HROW_O[13] bit 9 SPEC_INT: mux CELL[25].OMUX_CCIO[2] bit 2 SPEC_INT: mux CELL[25].OMUX_CCIO[2] bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 4 SPEC_INT: mux CELL[25].HROW_O[11] bit 7 SPEC_INT: mux CELL[25].HROW_O[12] bit 4 SPEC_INT: mux CELL[25].HROW_O[12] bit 7
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 0 SPEC_INT: mux CELL[25].HROW_O[11] bit 5 SPEC_INT: mux CELL[25].HROW_O[12] bit 0 SPEC_INT: mux CELL[25].HROW_O[12] bit 5
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 6 SPEC_INT: mux CELL[25].HROW_O[11] bit 1 SPEC_INT: mux CELL[25].HROW_O[12] bit 6 SPEC_INT: mux CELL[25].HROW_O[12] bit 1
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 3 SPEC_INT: mux CELL[25].HROW_O[11] bit 2 SPEC_INT: mux CELL[25].HROW_O[12] bit 3 SPEC_INT: mux CELL[25].HROW_O[12] bit 2
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 12 SPEC_INT: mux CELL[25].HROW_O[11] bit 13 SPEC_INT: mux CELL[25].HROW_O[12] bit 12 SPEC_INT: mux CELL[25].HROW_O[12] bit 13
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 10 SPEC_INT: mux CELL[25].HROW_O[11] bit 11 SPEC_INT: mux CELL[25].HROW_O[12] bit 10 SPEC_INT: mux CELL[25].HROW_O[12] bit 11
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[11] bit 8 SPEC_INT: mux CELL[25].HROW_O[11] bit 9 SPEC_INT: mux CELL[25].HROW_O[12] bit 8 SPEC_INT: mux CELL[25].HROW_O[12] bit 9
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 4 SPEC_INT: mux CELL[25].HROW_O[9] bit 7 SPEC_INT: mux CELL[25].HROW_O[10] bit 4 SPEC_INT: mux CELL[25].HROW_O[10] bit 7
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 0 SPEC_INT: mux CELL[25].HROW_O[9] bit 5 SPEC_INT: mux CELL[25].HROW_O[10] bit 0 SPEC_INT: mux CELL[25].HROW_O[10] bit 5
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 6 SPEC_INT: mux CELL[25].HROW_O[9] bit 1 SPEC_INT: mux CELL[25].HROW_O[10] bit 6 SPEC_INT: mux CELL[25].HROW_O[10] bit 1
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 3 SPEC_INT: mux CELL[25].HROW_O[9] bit 2 SPEC_INT: mux CELL[25].HROW_O[10] bit 3 SPEC_INT: mux CELL[25].HROW_O[10] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 12 SPEC_INT: mux CELL[25].HROW_O[9] bit 13 SPEC_INT: mux CELL[25].HROW_O[10] bit 12 SPEC_INT: mux CELL[25].HROW_O[10] bit 13
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 10 SPEC_INT: mux CELL[25].HROW_O[9] bit 11 SPEC_INT: mux CELL[25].HROW_O[10] bit 10 SPEC_INT: mux CELL[25].HROW_O[10] bit 11
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[9] bit 8 SPEC_INT: mux CELL[25].HROW_O[9] bit 9 SPEC_INT: mux CELL[25].HROW_O[10] bit 8 SPEC_INT: mux CELL[25].HROW_O[10] bit 9
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 4 SPEC_INT: mux CELL[25].HROW_O[7] bit 7 SPEC_INT: mux CELL[25].HROW_O[8] bit 4 SPEC_INT: mux CELL[25].HROW_O[8] bit 7
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 0 SPEC_INT: mux CELL[25].HROW_O[7] bit 5 SPEC_INT: mux CELL[25].HROW_O[8] bit 0 SPEC_INT: mux CELL[25].HROW_O[8] bit 5
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 6 SPEC_INT: mux CELL[25].HROW_O[7] bit 1 SPEC_INT: mux CELL[25].HROW_O[8] bit 6 SPEC_INT: mux CELL[25].HROW_O[8] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 3 SPEC_INT: mux CELL[25].HROW_O[7] bit 2 SPEC_INT: mux CELL[25].HROW_O[8] bit 3 SPEC_INT: mux CELL[25].HROW_O[8] bit 2
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 12 SPEC_INT: mux CELL[25].HROW_O[7] bit 13 SPEC_INT: mux CELL[25].HROW_O[8] bit 12 SPEC_INT: mux CELL[25].HROW_O[8] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 10 SPEC_INT: mux CELL[25].HROW_O[7] bit 11 SPEC_INT: mux CELL[25].HROW_O[8] bit 10 SPEC_INT: mux CELL[25].HROW_O[8] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].HROW_O[7] bit 8 SPEC_INT: mux CELL[25].HROW_O[7] bit 9 SPEC_INT: mux CELL[25].HROW_O[8] bit 8 SPEC_INT: mux CELL[25].HROW_O[8] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[3] bit 1 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[3] bit 0 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[0] bit 1 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[0] bit 0
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 6 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 7 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 0 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 1
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 7 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 5 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[1] bit 1 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[1] bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 5 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 6 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[2] bit 1 SPEC_INT: mux CELL[25].OMUX_HCLK_FREQ_BB[2] bit 0
virtex7 CMT rect MAIN[26]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: AVDD_COMP_SET bit 1 PHASER_REF: AVDD_COMP_SET bit 2
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: AVDD_VBG_PD bit 2 PHASER_REF: AVDD_COMP_SET bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: AVDD_VBG_PD bit 0 PHASER_REF: AVDD_VBG_PD bit 1
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: AVDD_VBG_SEL bit 2 PHASER_REF: AVDD_VBG_SEL bit 3
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: AVDD_VBG_SEL bit 0 PHASER_REF: AVDD_VBG_SEL bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CP bit 2 PHASER_REF: CP bit 3
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CP bit 0 PHASER_REF: CP bit 1
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CP_RES bit 0 PHASER_REF: CP_RES bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 14 PHASER_REF: CONTROL_0 bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 12 PHASER_REF: CONTROL_0 bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 10 PHASER_REF: CONTROL_0 bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 8 PHASER_REF: CONTROL_0 bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 6 PHASER_REF: CONTROL_0 bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 4 PHASER_REF: CONTROL_0 bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 2 PHASER_REF: CONTROL_0 bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_0 bit 0 PHASER_REF: CONTROL_0 bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 14 PHASER_REF: CONTROL_1 bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 12 PHASER_REF: CONTROL_1 bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 10 PHASER_REF: CONTROL_1 bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 8 PHASER_REF: CONTROL_1 bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 6 PHASER_REF: CONTROL_1 bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 4 PHASER_REF: CONTROL_1 bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 2 PHASER_REF: CONTROL_1 bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_1 bit 0 PHASER_REF: CONTROL_1 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 14 PHASER_REF: CONTROL_2 bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 12 PHASER_REF: CONTROL_2 bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 10 PHASER_REF: CONTROL_2 bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 8 PHASER_REF: CONTROL_2 bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 6 PHASER_REF: CONTROL_2 bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 4 PHASER_REF: CONTROL_2 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 2 PHASER_REF: CONTROL_2 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_2 bit 0 PHASER_REF: CONTROL_2 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LF_NEN bit 0 PHASER_REF: LF_NEN bit 1
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LF_PEN bit 0 PHASER_REF: LF_PEN bit 1
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_CNT bit 8 PHASER_REF: LOCK_CNT bit 9
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_CNT bit 6 PHASER_REF: LOCK_CNT bit 7
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_CNT bit 4 PHASER_REF: LOCK_CNT bit 5
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_CNT bit 2 PHASER_REF: LOCK_CNT bit 3
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_CNT bit 0 PHASER_REF: LOCK_CNT bit 1
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: invert PWRDWN PHASER_REF: PHASER_REF_EN
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_FB_DLY bit 3 PHASER_REF: LOCK_FB_DLY bit 4
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_FB_DLY bit 1 PHASER_REF: LOCK_FB_DLY bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PFD bit 6 PHASER_REF: LOCK_FB_DLY bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PFD bit 4 PHASER_REF: PFD bit 5
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PFD bit 2 PHASER_REF: PFD bit 3
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PFD bit 0 PHASER_REF: PFD bit 1
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: MAN_LF bit 1 PHASER_REF: MAN_LF bit 2
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: invert RST PHASER_REF: MAN_LF bit 0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 14 PHASER_REF: CONTROL_3 bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 12 PHASER_REF: CONTROL_3 bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 10 PHASER_REF: CONTROL_3 bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 8 PHASER_REF: CONTROL_3 bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 6 PHASER_REF: CONTROL_3 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 4 PHASER_REF: CONTROL_3 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 2 PHASER_REF: CONTROL_3 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_3 bit 0 PHASER_REF: CONTROL_3 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: SEL_LF_HIGH bit 2 PHASER_REF: SUP_SEL_AREG
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: SEL_LF_HIGH bit 0 PHASER_REF: SEL_LF_HIGH bit 1
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_REF_DLY bit 3 PHASER_REF: LOCK_REF_DLY bit 4
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: LOCK_REF_DLY bit 1 PHASER_REF: LOCK_REF_DLY bit 2
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: SEL_SLIPD PHASER_REF: LOCK_REF_DLY bit 0
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: TMUX_MUX_SEL bit 0 PHASER_REF: TMUX_MUX_SEL bit 1
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PHASER_REF_MISC bit 2 PHASER_REF: CP_BIAS_TRIP_SET bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: PHASER_REF_MISC bit 0 PHASER_REF: PHASER_REF_MISC bit 1
virtex7 CMT rect MAIN[27]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV bit 2 PHASER_OUT[2]: CLKOUT_DIV bit 3
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV bit 0 PHASER_OUT[2]: CLKOUT_DIV bit 1
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: DATA_CTL_N PHASER_OUT[2]: CTL_MODE bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: OCLK_DELAY bit 5 PHASER_OUT[2]: EN_TEST_RING
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: OCLK_DELAY bit 3 PHASER_OUT[2]: OCLK_DELAY bit 4
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: OCLK_DELAY bit 1 PHASER_OUT[2]: OCLK_DELAY bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: STG1_BYPASS bit 0 PHASER_OUT[2]: OCLK_DELAY bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: OUTPUT_CLK_SRC bit 0 PHASER_OUT[2]: OUTPUT_CLK_SRC bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: EN_OSERDES_RST PHASER_OUT[2]: COARSE_BYPASS
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: OCLKDELAY_INV PHASER_OUT[2]: PHASER_OUT_EN
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 10 PHASER_OUT[2]: DATA_RD_CYCLES
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 8 PHASER_OUT[2]: TEST_OPT bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 6 PHASER_OUT[2]: TEST_OPT bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 4 PHASER_OUT[2]: TEST_OPT bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 2 PHASER_OUT[2]: TEST_OPT bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: TEST_OPT bit 0 PHASER_OUT[2]: TEST_OPT bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 14 PHASER_REF: CONTROL_5 bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 12 PHASER_REF: CONTROL_5 bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 10 PHASER_REF: CONTROL_5 bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 8 PHASER_REF: CONTROL_5 bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 6 PHASER_REF: CONTROL_5 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 4 PHASER_REF: CONTROL_5 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 2 PHASER_REF: CONTROL_5 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_5 bit 0 PHASER_REF: CONTROL_5 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 14 PHASER_REF: CONTROL_4 bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 12 PHASER_REF: CONTROL_4 bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 10 PHASER_REF: CONTROL_4 bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 8 PHASER_REF: CONTROL_4 bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 6 PHASER_REF: CONTROL_4 bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 4 PHASER_REF: CONTROL_4 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 2 PHASER_REF: CONTROL_4 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_REF: CONTROL_4 bit 0 PHASER_REF: CONTROL_4 bit 1
virtex7 CMT rect MAIN[28]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: RST_SEL bit 0 PHASER_IN[2]: REG_OPT_2 bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: HALF_CYCLE_ADJ PHASER_IN[2]: SEL_CLK_OFFSET bit 2
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: STG1_PD_UPDATE bit 1 PHASER_IN[2]: STG1_PD_UPDATE bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: OUTPUT_CLK_SRC bit 3 PHASER_IN[2]: STG1_PD_UPDATE bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: ICLK_TO_RCLK_BYPASS PHASER_IN[2]: OUTPUT_CLK_SRC bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: PHASER_IN_EN PHASER_IN[2]: EN_ISERDES_RST
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: OUTPUT_CLK_SRC bit 1 PHASER_IN[2]: WR_CYCLES
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: SEL_CLK_OFFSET bit 1 PHASER_IN[2]: OUTPUT_CLK_SRC bit 0
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: SEL_OUT bit 0 PHASER_IN[2]: SEL_CLK_OFFSET bit 0
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: RD_ADDR_INIT bit 0 PHASER_IN[2]: RD_ADDR_INIT bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: REG_OPT_1 bit 0 PHASER_IN[2]: REG_OPT_4 bit 0
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: DQS_AUTO_RECAL bit 0 PHASER_IN[2]: DQS_BIAS_MODE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: UPDATE_NONACTIVE PHASER_IN[2]: TEST_BP bit 0
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV bit 6 PHASER_OUT[2]: CLKOUT_DIV bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV bit 4 PHASER_OUT[2]: CLKOUT_DIV bit 5
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV_ST bit 2 PHASER_OUT[2]: CLKOUT_DIV_ST bit 3
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: CLKOUT_DIV_ST bit 0 PHASER_OUT[2]: CLKOUT_DIV_ST bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: FINE_DELAY bit 5 PHASER_OUT[2]: SYNC_IN_DIV_RST
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: FINE_DELAY bit 3 PHASER_OUT[2]: FINE_DELAY bit 4
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: FINE_DELAY bit 1 PHASER_OUT[2]: FINE_DELAY bit 2
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: COARSE_DELAY bit 5 PHASER_OUT[2]: FINE_DELAY bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: COARSE_DELAY bit 3 PHASER_OUT[2]: COARSE_DELAY bit 4
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: COARSE_DELAY bit 1 PHASER_OUT[2]: COARSE_DELAY bit 2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2] bit 3 PHASER_OUT[2]: COARSE_DELAY bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2] bit 1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[2]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[2] bit 0
virtex7 CMT rect MAIN[29]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV bit 7 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV bit 5 PHASER_IN[2]: CLKOUT_DIV bit 6
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV_ST bit 3 PHASER_IN[2]: CLKOUT_DIV bit 4
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV_ST bit 1 PHASER_IN[2]: CLKOUT_DIV_ST bit 2
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: SYNC_IN_DIV_RST PHASER_IN[2]: CLKOUT_DIV_ST bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: FINE_DELAY bit 4 PHASER_IN[2]: FINE_DELAY bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: FINE_DELAY bit 2 PHASER_IN[2]: FINE_DELAY bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: FINE_DELAY bit 0 PHASER_IN[2]: FINE_DELAY bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2] bit 3 -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[2] bit 1
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV bit 3 PHASER_IN[2]: BURST_MODE
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CLKOUT_DIV bit 1 PHASER_IN[2]: CLKOUT_DIV bit 2
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: CTL_MODE bit 0 PHASER_IN[2]: CLKOUT_DIV bit 0
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: DQS_FIND_PATTERN bit 2 PHASER_IN[2]: EN_TEST_RING
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: DQS_FIND_PATTERN bit 0 PHASER_IN[2]: DQS_FIND_PATTERN bit 1
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: FREQ_REF_DIV bit 0 PHASER_IN[2]: FREQ_REF_DIV bit 1
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: PD_REVERSE bit 2 -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[2]: PD_REVERSE bit 0 PHASER_IN[2]: PD_REVERSE bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[30]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV bit 2 PHASER_OUT[3]: CLKOUT_DIV bit 3
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV bit 0 PHASER_OUT[3]: CLKOUT_DIV bit 1
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: DATA_CTL_N PHASER_OUT[3]: CTL_MODE bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: OCLK_DELAY bit 5 PHASER_OUT[3]: EN_TEST_RING
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: OCLK_DELAY bit 3 PHASER_OUT[3]: OCLK_DELAY bit 4
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: OCLK_DELAY bit 1 PHASER_OUT[3]: OCLK_DELAY bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: STG1_BYPASS bit 0 PHASER_OUT[3]: OCLK_DELAY bit 0
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: OUTPUT_CLK_SRC bit 0 PHASER_OUT[3]: OUTPUT_CLK_SRC bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: EN_OSERDES_RST PHASER_OUT[3]: COARSE_BYPASS
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: OCLKDELAY_INV PHASER_OUT[3]: PHASER_OUT_EN
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 10 PHASER_OUT[3]: DATA_RD_CYCLES
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 8 PHASER_OUT[3]: TEST_OPT bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 6 PHASER_OUT[3]: TEST_OPT bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 4 PHASER_OUT[3]: TEST_OPT bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 2 PHASER_OUT[3]: TEST_OPT bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: TEST_OPT bit 0 PHASER_OUT[3]: TEST_OPT bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[31]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV bit 6 PHASER_OUT[3]: CLKOUT_DIV bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV bit 4 PHASER_OUT[3]: CLKOUT_DIV bit 5
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV_ST bit 2 PHASER_OUT[3]: CLKOUT_DIV_ST bit 3
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: CLKOUT_DIV_ST bit 0 PHASER_OUT[3]: CLKOUT_DIV_ST bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: FINE_DELAY bit 5 PHASER_OUT[3]: SYNC_IN_DIV_RST
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: FINE_DELAY bit 3 PHASER_OUT[3]: FINE_DELAY bit 4
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: FINE_DELAY bit 1 PHASER_OUT[3]: FINE_DELAY bit 2
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: COARSE_DELAY bit 5 PHASER_OUT[3]: FINE_DELAY bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: COARSE_DELAY bit 3 PHASER_OUT[3]: COARSE_DELAY bit 4
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: COARSE_DELAY bit 1 PHASER_OUT[3]: COARSE_DELAY bit 2
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3] bit 3 PHASER_OUT[3]: COARSE_DELAY bit 0
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3] bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_OUT[3]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_OUT_PHASEREFCLK[3] bit 0
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[32]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3] bit 3 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3] bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV bit 3 PHASER_IN[3]: BURST_MODE
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV bit 1 PHASER_IN[3]: CLKOUT_DIV bit 2
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CTL_MODE bit 0 PHASER_IN[3]: CLKOUT_DIV bit 0
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: DQS_FIND_PATTERN bit 2 PHASER_IN[3]: EN_TEST_RING
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: DQS_FIND_PATTERN bit 0 PHASER_IN[3]: DQS_FIND_PATTERN bit 1
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: FREQ_REF_DIV bit 0 PHASER_IN[3]: FREQ_REF_DIV bit 1
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: PD_REVERSE bit 2 -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: PD_REVERSE bit 0 PHASER_IN[3]: PD_REVERSE bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: RST_SEL bit 0 PHASER_IN[3]: REG_OPT_2 bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: HALF_CYCLE_ADJ PHASER_IN[3]: SEL_CLK_OFFSET bit 2
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: invert RST SPEC_INT: mux CELL[25].IMUX_PHASER_IN_PHASEREFCLK[3] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: STG1_PD_UPDATE bit 1 PHASER_IN[3]: STG1_PD_UPDATE bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: OUTPUT_CLK_SRC bit 3 PHASER_IN[3]: STG1_PD_UPDATE bit 0
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: ICLK_TO_RCLK_BYPASS PHASER_IN[3]: OUTPUT_CLK_SRC bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: PHASER_IN_EN PHASER_IN[3]: EN_ISERDES_RST
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: OUTPUT_CLK_SRC bit 1 PHASER_IN[3]: WR_CYCLES
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: SEL_CLK_OFFSET bit 1 PHASER_IN[3]: OUTPUT_CLK_SRC bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: SEL_OUT bit 0 PHASER_IN[3]: SEL_CLK_OFFSET bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: RD_ADDR_INIT bit 0 PHASER_IN[3]: RD_ADDR_INIT bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: REG_OPT_1 bit 0 PHASER_IN[3]: REG_OPT_4 bit 0
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: DQS_AUTO_RECAL bit 0 PHASER_IN[3]: DQS_BIAS_MODE
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: UPDATE_NONACTIVE PHASER_IN[3]: TEST_BP bit 0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[33]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV bit 7 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV bit 5 PHASER_IN[3]: CLKOUT_DIV bit 6
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV_ST bit 3 PHASER_IN[3]: CLKOUT_DIV bit 4
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: CLKOUT_DIV_ST bit 1 PHASER_IN[3]: CLKOUT_DIV_ST bit 2
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: SYNC_IN_DIV_RST PHASER_IN[3]: CLKOUT_DIV_ST bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: FINE_DELAY bit 4 PHASER_IN[3]: FINE_DELAY bit 5
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: FINE_DELAY bit 2 PHASER_IN[3]: FINE_DELAY bit 3
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHASER_IN[3]: FINE_DELAY bit 0 PHASER_IN[3]: FINE_DELAY bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[34]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CMD_OFFSET bit 4 PHY_CONTROL: CMD_OFFSET bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CMD_OFFSET bit 2 PHY_CONTROL: CMD_OFFSET bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CMD_OFFSET bit 0 PHY_CONTROL: CMD_OFFSET bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: AO_TOGGLE bit 2 PHY_CONTROL: AO_TOGGLE bit 3
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: AO_TOGGLE bit 0 PHY_CONTROL: AO_TOGGLE bit 1
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: EVENTS_DELAY bit 4 PHY_CONTROL: EVENTS_DELAY bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: EVENTS_DELAY bit 2 PHY_CONTROL: EVENTS_DELAY bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: EVENTS_DELAY bit 0 PHY_CONTROL: EVENTS_DELAY bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 4 PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 2 PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 0 PHY_CONTROL: FOUR_WINDOW_CLOCKS bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DI_DURATION bit 1 PHY_CONTROL: DI_DURATION bit 2
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CLK_RATIO bit 2 PHY_CONTROL: DI_DURATION bit 0
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CLK_RATIO bit 0 PHY_CONTROL: CLK_RATIO bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_1 bit 4 PHY_CONTROL: WR_CMD_OFFSET_1 bit 5
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_1 bit 2 PHY_CONTROL: WR_CMD_OFFSET_1 bit 3
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_1 bit 0 PHY_CONTROL: WR_CMD_OFFSET_1 bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_1 bit 4 PHY_CONTROL: WR_DURATION_1 bit 5
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_1 bit 2 PHY_CONTROL: WR_DURATION_1 bit 3
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_1 bit 0 PHY_CONTROL: WR_DURATION_1 bit 1
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_1 bit 4 PHY_CONTROL: RD_CMD_OFFSET_1 bit 5
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_1 bit 2 PHY_CONTROL: RD_CMD_OFFSET_1 bit 3
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_1 bit 0 PHY_CONTROL: RD_CMD_OFFSET_1 bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_1 bit 4 PHY_CONTROL: RD_DURATION_1 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_1 bit 2 PHY_CONTROL: RD_DURATION_1 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_1 bit 0 PHY_CONTROL: RD_DURATION_1 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DISABLE_SEQ_MATCH -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: MULTI_REGION PHY_CONTROL: SYNC_MODE
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DO_DURATION bit 2 PHY_CONTROL: SPARE bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DO_DURATION bit 0 PHY_CONTROL: DO_DURATION bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_0 bit 4 PHY_CONTROL: WR_CMD_OFFSET_0 bit 5
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_0 bit 2 PHY_CONTROL: WR_CMD_OFFSET_0 bit 3
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_0 bit 0 PHY_CONTROL: WR_CMD_OFFSET_0 bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_0 bit 4 PHY_CONTROL: WR_DURATION_0 bit 5
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_0 bit 2 PHY_CONTROL: WR_DURATION_0 bit 3
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_0 bit 0 PHY_CONTROL: WR_DURATION_0 bit 1
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_0 bit 4 PHY_CONTROL: RD_CMD_OFFSET_0 bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_0 bit 2 PHY_CONTROL: RD_CMD_OFFSET_0 bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_0 bit 0 PHY_CONTROL: RD_CMD_OFFSET_0 bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_0 bit 4 PHY_CONTROL: RD_DURATION_0 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_0 bit 2 PHY_CONTROL: RD_DURATION_0 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_0 bit 0 PHY_CONTROL: RD_DURATION_0 bit 1
virtex7 CMT rect MAIN[35]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: BURST_MODE -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DATA_CTL_C_N PHY_CONTROL: DATA_CTL_D_N
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: DATA_CTL_A_N PHY_CONTROL: DATA_CTL_B_N
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_3 bit 4 PHY_CONTROL: WR_CMD_OFFSET_3 bit 5
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_3 bit 2 PHY_CONTROL: WR_CMD_OFFSET_3 bit 3
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_3 bit 0 PHY_CONTROL: WR_CMD_OFFSET_3 bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_3 bit 4 PHY_CONTROL: WR_DURATION_3 bit 5
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_3 bit 2 PHY_CONTROL: WR_DURATION_3 bit 3
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_3 bit 0 PHY_CONTROL: WR_DURATION_3 bit 1
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_3 bit 4 PHY_CONTROL: RD_CMD_OFFSET_3 bit 5
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_3 bit 2 PHY_CONTROL: RD_CMD_OFFSET_3 bit 3
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_3 bit 0 PHY_CONTROL: RD_CMD_OFFSET_3 bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_3 bit 4 PHY_CONTROL: RD_DURATION_3 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_3 bit 2 PHY_CONTROL: RD_DURATION_3 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_3 bit 0 PHY_CONTROL: RD_DURATION_3 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: AO_WRLVL_EN bit 3 PHY_CONTROL: PHY_COUNT_ENABLE
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: AO_WRLVL_EN bit 1 PHY_CONTROL: AO_WRLVL_EN bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CO_DURATION bit 2 PHY_CONTROL: AO_WRLVL_EN bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: CO_DURATION bit 0 PHY_CONTROL: CO_DURATION bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_2 bit 4 PHY_CONTROL: WR_CMD_OFFSET_2 bit 5
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_2 bit 2 PHY_CONTROL: WR_CMD_OFFSET_2 bit 3
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_CMD_OFFSET_2 bit 0 PHY_CONTROL: WR_CMD_OFFSET_2 bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_2 bit 4 PHY_CONTROL: WR_DURATION_2 bit 5
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_2 bit 2 PHY_CONTROL: WR_DURATION_2 bit 3
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: WR_DURATION_2 bit 0 PHY_CONTROL: WR_DURATION_2 bit 1
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_2 bit 4 PHY_CONTROL: RD_CMD_OFFSET_2 bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_2 bit 2 PHY_CONTROL: RD_CMD_OFFSET_2 bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_CMD_OFFSET_2 bit 0 PHY_CONTROL: RD_CMD_OFFSET_2 bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_2 bit 4 PHY_CONTROL: RD_DURATION_2 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_2 bit 2 PHY_CONTROL: RD_DURATION_2 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PHY_CONTROL: RD_DURATION_2 bit 0 PHY_CONTROL: RD_DURATION_2 bit 1
virtex7 CMT rect MAIN[36]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[3] bit 1 -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[2] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[3] bit 0
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[1] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[2] bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[0] bit 1 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[1] bit 0
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[2] bit 2 SPEC_INT: mux CELL[25].OMUX_PLL_FREQ_BB_N[0] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[2] bit 0 SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[2] bit 1
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 4 SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[1] bit 2
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 4 SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[3] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 4 SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[2] bit 1
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 4 SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[1] bit 1
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[3]) bit 1 SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[0] bit 1
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[2]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 6
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[1]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 6
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[0]) bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 6
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[3] bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 6
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[2] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 6
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[1] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 6
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB_N[0] bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 6
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[3]) bit 0 SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 6
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[2]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 5
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[1]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 5
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB_N[0]) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[1] bit 1 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 5
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CMT_SYNC_BB ← CELL[25].OUT_PHY_PHYCTLEMPTY SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[1] bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CMT_SYNC_BB_N ← CELL[25].CMT_SYNC_BB SPEC_INT: wire support (CELL[25].CMT_SYNC_BB) bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CMT_SYNC_BB ← CELL[25].CMT_SYNC_BB_N SPEC_INT: wire support (CELL[25].CMT_SYNC_BB_N) bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[0] bit 1 SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[0] bit 2
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[3] bit 2 SPEC_INT: mux CELL[25].IMUX_PHASER_REFMUX[0] bit 0
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].CMT_FREQ_BB[1] bit 2 SPEC_INT: mux CELL[25].CMT_FREQ_BB[2] bit 2
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[3]) bit 4 SPEC_INT: mux CELL[25].CMT_FREQ_BB[0] bit 2
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[1]) bit 4 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[2]) bit 4
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: wire support (CELL[25].CMT_SYNC_BB) bit 0 SPEC_INT: wire support (CELL[25].CMT_FREQ_BB[0]) bit 4
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT rect MAIN[37]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 14 PLL[1]: PLL_DRP[7] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 12 PLL[1]: PLL_DRP[7] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 10 PLL[1]: PLL_DRP[7] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 8 PLL[1]: CLKOUT5_MX bit 0 PLL[1]: PLL_DRP[7] bit 9 PLL[1]: CLKOUT5_MX bit 1
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 6 PLL[1]: CLKOUT5_NOCOUNT PLL[1]: PLL_DRP[7] bit 7 PLL[1]: CLKOUT5_EDGE
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 4 PLL[1]: CLKOUT5_DT bit 4 PLL[1]: PLL_DRP[7] bit 5 PLL[1]: CLKOUT5_DT bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 2 PLL[1]: CLKOUT5_DT bit 2 PLL[1]: PLL_DRP[7] bit 3 PLL[1]: CLKOUT5_DT bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[7] bit 0 PLL[1]: CLKOUT5_DT bit 0 PLL[1]: PLL_DRP[7] bit 1 PLL[1]: CLKOUT5_DT bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 14 PLL[1]: CLKOUT5_PM bit 1 PLL[1]: PLL_DRP[6] bit 15 PLL[1]: CLKOUT5_PM bit 2
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 12 PLL[1]: CLKOUT5_EN PLL[1]: PLL_DRP[6] bit 13 PLL[1]: CLKOUT5_PM bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 10 PLL[1]: CLKOUT5_HT bit 4 PLL[1]: PLL_DRP[6] bit 11 PLL[1]: CLKOUT5_HT bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 8 PLL[1]: CLKOUT5_HT bit 2 PLL[1]: PLL_DRP[6] bit 9 PLL[1]: CLKOUT5_HT bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 6 PLL[1]: CLKOUT5_HT bit 0 PLL[1]: PLL_DRP[6] bit 7 PLL[1]: CLKOUT5_HT bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 4 PLL[1]: CLKOUT5_LT bit 4 PLL[1]: PLL_DRP[6] bit 5 PLL[1]: CLKOUT5_LT bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 2 PLL[1]: CLKOUT5_LT bit 2 PLL[1]: PLL_DRP[6] bit 3 PLL[1]: CLKOUT5_LT bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[6] bit 0 PLL[1]: CLKOUT5_LT bit 0 PLL[1]: PLL_DRP[6] bit 1 PLL[1]: CLKOUT5_LT bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 14 PLL[1]: V7_IN_DLY_SET bit 4 PLL[1]: PLL_DRP[5] bit 15 PLL[1]: V7_IN_DLY_SET bit 5
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 12 PLL[1]: V7_IN_DLY_SET bit 2 PLL[1]: PLL_DRP[5] bit 13 PLL[1]: V7_IN_DLY_SET bit 3
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 10 PLL[1]: V7_IN_DLY_SET bit 0 PLL[1]: PLL_DRP[5] bit 11 PLL[1]: V7_IN_DLY_SET bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 8 PLL[1]: IN_DLY_MX_DVDD bit 4 PLL[1]: PLL_DRP[5] bit 9 PLL[1]: IN_DLY_MX_DVDD bit 5
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 6 PLL[1]: IN_DLY_MX_DVDD bit 2 PLL[1]: PLL_DRP[5] bit 7 PLL[1]: IN_DLY_MX_DVDD bit 3
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 4 PLL[1]: IN_DLY_MX_DVDD bit 0 PLL[1]: PLL_DRP[5] bit 5 PLL[1]: IN_DLY_MX_DVDD bit 1
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 2 PLL[1]: IN_DLY_EN PLL[1]: PLL_DRP[5] bit 3 PLL[1]: DIRECT_PATH_CNTRL
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[5] bit 0 PLL[1]: PLL_DRP[5] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 14 PLL[1]: TMUX_MUX_SEL bit 0 PLL[1]: PLL_DRP[4] bit 15 PLL[1]: TMUX_MUX_SEL bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 12 PLL[1]: PLL_DRP[4] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 10 PLL[1]: PLL_DRP[4] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 8 PLL[1]: PLL_DRP[4] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 6 PLL[1]: PLL_DRP[4] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 4 PLL[1]: PLL_DRP[4] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 2 PLL[1]: PLL_DRP[4] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[4] bit 0 PLL[1]: PLL_DRP[4] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 14 PLL[1]: PLL_DRP[3] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 12 PLL[1]: PLL_DRP[3] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 10 PLL[1]: PLL_DRP[3] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 8 PLL[1]: PLL_DRP[3] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 6 PLL[1]: PLL_DRP[3] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 4 PLL[1]: PLL_DRP[3] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 2 PLL[1]: SKEW_FLOP_INV bit 2 PLL[1]: PLL_DRP[3] bit 3 PLL[1]: SKEW_FLOP_INV bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[3] bit 0 PLL[1]: SKEW_FLOP_INV bit 0 PLL[1]: PLL_DRP[3] bit 1 PLL[1]: SKEW_FLOP_INV bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 14 PLL[1]: PLL_DRP[2] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 12 PLL[1]: PLL_DRP[2] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 10 PLL[1]: PLL_DRP[2] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 8 PLL[1]: PLL_DRP[2] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 6 PLL[1]: PLL_DRP[2] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 4 PLL[1]: PLL_DRP[2] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 2 PLL[1]: PLL_DRP[2] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[2] bit 0 PLL[1]: SYNTH_CLK_DIV bit 0 PLL[1]: PLL_DRP[2] bit 1 PLL[1]: SYNTH_CLK_DIV bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[1] bit 14 PLL[1]: PLL_DRP[1] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[1] bit 12 PLL[1]: PLL_DRP[1] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_N[2] ← CELL[25].OUT_PLL_N[2] PLL[1]: PLL_DRP[1] bit 10 SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_N[3] ← CELL[25].OUT_PLL_N[3] PLL[1]: PLL_DRP[1] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_N[0] ← CELL[25].OUT_PLL_N[0] PLL[1]: PLL_DRP[1] bit 8 SPEC_INT: buffer CELL[25].OUT_PLL_FREQ_BB_N[1] ← CELL[25].OUT_PLL_N[1] PLL[1]: PLL_DRP[1] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[1] bit 1 PLL[1]: PLL_DRP[1] bit 6 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[1] bit 2 PLL[1]: PLL_DRP[1] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[1] bit 2 PLL[1]: PLL_DRP[1] bit 4 SPEC_INT: mux CELL[25].IMUX_PLL_CLKFB[1] bit 0 PLL[1]: PLL_DRP[1] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[1] bit 0 PLL[1]: PLL_DRP[1] bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN1[1] bit 1 PLL[1]: PLL_DRP[1] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[1] bit 1 PLL[1]: PLL_DRP[1] bit 0 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[1] bit 2 PLL[1]: PLL_DRP[1] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 14 PLL[1]: HROW_DLY_SET bit 2 SPEC_INT: mux CELL[25].IMUX_PLL_CLKIN2[1] bit 0 PLL[1]: PLL_DRP[0] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 12 PLL[1]: HROW_DLY_SET bit 0 PLL[1]: PLL_DRP[0] bit 13 PLL[1]: HROW_DLY_SET bit 1
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 10 PLL[1]: IN_DLY_MX_CVDD bit 4 PLL[1]: PLL_DRP[0] bit 11 PLL[1]: IN_DLY_MX_CVDD bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 8 PLL[1]: IN_DLY_MX_CVDD bit 2 PLL[1]: PLL_DRP[0] bit 9 PLL[1]: IN_DLY_MX_CVDD bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 6 PLL[1]: IN_DLY_MX_CVDD bit 0 PLL[1]: PLL_DRP[0] bit 7 PLL[1]: IN_DLY_MX_CVDD bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 4 PLL[1]: PLL_DRP[0] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 2 PLL[1]: PLL_DRP[0] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[0] bit 0 PLL[1]: PLL_DRP[0] bit 1
virtex7 CMT rect MAIN[38]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 14 PLL[1]: PLL_DRP[15] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 12 PLL[1]: PLL_DRP[15] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 10 PLL[1]: PLL_DRP[15] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 8 PLL[1]: CLKOUT3_MX bit 0 PLL[1]: PLL_DRP[15] bit 9 PLL[1]: CLKOUT3_MX bit 1
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 6 PLL[1]: CLKOUT3_NOCOUNT PLL[1]: PLL_DRP[15] bit 7 PLL[1]: CLKOUT3_EDGE
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 4 PLL[1]: CLKOUT3_DT bit 4 PLL[1]: PLL_DRP[15] bit 5 PLL[1]: CLKOUT3_DT bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 2 PLL[1]: CLKOUT3_DT bit 2 PLL[1]: PLL_DRP[15] bit 3 PLL[1]: CLKOUT3_DT bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[15] bit 0 PLL[1]: CLKOUT3_DT bit 0 PLL[1]: PLL_DRP[15] bit 1 PLL[1]: CLKOUT3_DT bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 14 PLL[1]: CLKOUT3_PM bit 1 PLL[1]: PLL_DRP[14] bit 15 PLL[1]: CLKOUT3_PM bit 2
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 12 PLL[1]: CLKOUT3_EN PLL[1]: PLL_DRP[14] bit 13 PLL[1]: CLKOUT3_PM bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 10 PLL[1]: CLKOUT3_HT bit 4 PLL[1]: PLL_DRP[14] bit 11 PLL[1]: CLKOUT3_HT bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 8 PLL[1]: CLKOUT3_HT bit 2 PLL[1]: PLL_DRP[14] bit 9 PLL[1]: CLKOUT3_HT bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 6 PLL[1]: CLKOUT3_HT bit 0 PLL[1]: PLL_DRP[14] bit 7 PLL[1]: CLKOUT3_HT bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 4 PLL[1]: CLKOUT3_LT bit 4 PLL[1]: PLL_DRP[14] bit 5 PLL[1]: CLKOUT3_LT bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 2 PLL[1]: CLKOUT3_LT bit 2 PLL[1]: PLL_DRP[14] bit 3 PLL[1]: CLKOUT3_LT bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[14] bit 0 PLL[1]: CLKOUT3_LT bit 0 PLL[1]: PLL_DRP[14] bit 1 PLL[1]: CLKOUT3_LT bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 14 PLL[1]: PLL_DRP[13] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 12 PLL[1]: PLL_DRP[13] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 10 PLL[1]: PLL_DRP[13] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 8 PLL[1]: CLKOUT2_MX bit 0 PLL[1]: PLL_DRP[13] bit 9 PLL[1]: CLKOUT2_MX bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 6 PLL[1]: CLKOUT2_NOCOUNT PLL[1]: PLL_DRP[13] bit 7 PLL[1]: CLKOUT2_EDGE
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 4 PLL[1]: CLKOUT2_DT bit 4 PLL[1]: PLL_DRP[13] bit 5 PLL[1]: CLKOUT2_DT bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 2 PLL[1]: CLKOUT2_DT bit 2 PLL[1]: PLL_DRP[13] bit 3 PLL[1]: CLKOUT2_DT bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[13] bit 0 PLL[1]: CLKOUT2_DT bit 0 PLL[1]: PLL_DRP[13] bit 1 PLL[1]: CLKOUT2_DT bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 14 PLL[1]: CLKOUT2_PM bit 1 PLL[1]: PLL_DRP[12] bit 15 PLL[1]: CLKOUT2_PM bit 2
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 12 PLL[1]: CLKOUT2_EN PLL[1]: PLL_DRP[12] bit 13 PLL[1]: CLKOUT2_PM bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 10 PLL[1]: CLKOUT2_HT bit 4 PLL[1]: PLL_DRP[12] bit 11 PLL[1]: CLKOUT2_HT bit 5
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 8 PLL[1]: CLKOUT2_HT bit 2 PLL[1]: PLL_DRP[12] bit 9 PLL[1]: CLKOUT2_HT bit 3
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 6 PLL[1]: CLKOUT2_HT bit 0 PLL[1]: PLL_DRP[12] bit 7 PLL[1]: CLKOUT2_HT bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 4 PLL[1]: CLKOUT2_LT bit 4 PLL[1]: PLL_DRP[12] bit 5 PLL[1]: CLKOUT2_LT bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 2 PLL[1]: CLKOUT2_LT bit 2 PLL[1]: PLL_DRP[12] bit 3 PLL[1]: CLKOUT2_LT bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[12] bit 0 PLL[1]: CLKOUT2_LT bit 0 PLL[1]: PLL_DRP[12] bit 1 PLL[1]: CLKOUT2_LT bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 14 PLL[1]: PLL_DRP[11] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 12 PLL[1]: PLL_DRP[11] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 10 PLL[1]: PLL_DRP[11] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 8 PLL[1]: CLKOUT1_MX bit 0 PLL[1]: PLL_DRP[11] bit 9 PLL[1]: CLKOUT1_MX bit 1
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 6 PLL[1]: CLKOUT1_NOCOUNT PLL[1]: PLL_DRP[11] bit 7 PLL[1]: CLKOUT1_EDGE
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 4 PLL[1]: CLKOUT1_DT bit 4 PLL[1]: PLL_DRP[11] bit 5 PLL[1]: CLKOUT1_DT bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 2 PLL[1]: CLKOUT1_DT bit 2 PLL[1]: PLL_DRP[11] bit 3 PLL[1]: CLKOUT1_DT bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[11] bit 0 PLL[1]: CLKOUT1_DT bit 0 PLL[1]: PLL_DRP[11] bit 1 PLL[1]: CLKOUT1_DT bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 14 PLL[1]: CLKOUT1_PM bit 1 PLL[1]: PLL_DRP[10] bit 15 PLL[1]: CLKOUT1_PM bit 2
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 12 PLL[1]: CLKOUT1_EN PLL[1]: PLL_DRP[10] bit 13 PLL[1]: CLKOUT1_PM bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 10 PLL[1]: CLKOUT1_HT bit 4 PLL[1]: PLL_DRP[10] bit 11 PLL[1]: CLKOUT1_HT bit 5
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 8 PLL[1]: CLKOUT1_HT bit 2 PLL[1]: PLL_DRP[10] bit 9 PLL[1]: CLKOUT1_HT bit 3
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 6 PLL[1]: CLKOUT1_HT bit 0 PLL[1]: PLL_DRP[10] bit 7 PLL[1]: CLKOUT1_HT bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 4 PLL[1]: CLKOUT1_LT bit 4 PLL[1]: PLL_DRP[10] bit 5 PLL[1]: CLKOUT1_LT bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 2 PLL[1]: CLKOUT1_LT bit 2 PLL[1]: PLL_DRP[10] bit 3 PLL[1]: CLKOUT1_LT bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[10] bit 0 PLL[1]: CLKOUT1_LT bit 0 PLL[1]: PLL_DRP[10] bit 1 PLL[1]: CLKOUT1_LT bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 14 PLL[1]: PLL_DRP[9] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 12 PLL[1]: PLL_DRP[9] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 10 PLL[1]: PLL_DRP[9] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 8 PLL[1]: CLKOUT0_MX bit 0 PLL[1]: PLL_DRP[9] bit 9 PLL[1]: CLKOUT0_MX bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 6 PLL[1]: CLKOUT0_NOCOUNT PLL[1]: PLL_DRP[9] bit 7 PLL[1]: CLKOUT0_EDGE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 4 PLL[1]: CLKOUT0_DT bit 4 PLL[1]: PLL_DRP[9] bit 5 PLL[1]: CLKOUT0_DT bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 2 PLL[1]: CLKOUT0_DT bit 2 PLL[1]: PLL_DRP[9] bit 3 PLL[1]: CLKOUT0_DT bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[9] bit 0 PLL[1]: CLKOUT0_DT bit 0 PLL[1]: PLL_DRP[9] bit 1 PLL[1]: CLKOUT0_DT bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 14 PLL[1]: CLKOUT0_PM bit 1 PLL[1]: PLL_DRP[8] bit 15 PLL[1]: CLKOUT0_PM bit 2
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 12 PLL[1]: CLKOUT0_EN PLL[1]: PLL_DRP[8] bit 13 PLL[1]: CLKOUT0_PM bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 10 PLL[1]: CLKOUT0_HT bit 4 PLL[1]: PLL_DRP[8] bit 11 PLL[1]: CLKOUT0_HT bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 8 PLL[1]: CLKOUT0_HT bit 2 PLL[1]: PLL_DRP[8] bit 9 PLL[1]: CLKOUT0_HT bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 6 PLL[1]: CLKOUT0_HT bit 0 PLL[1]: PLL_DRP[8] bit 7 PLL[1]: CLKOUT0_HT bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 4 PLL[1]: CLKOUT0_LT bit 4 PLL[1]: PLL_DRP[8] bit 5 PLL[1]: CLKOUT0_LT bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 2 PLL[1]: CLKOUT0_LT bit 2 PLL[1]: PLL_DRP[8] bit 3 PLL[1]: CLKOUT0_LT bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[8] bit 0 PLL[1]: CLKOUT0_LT bit 0 PLL[1]: PLL_DRP[8] bit 1 PLL[1]: CLKOUT0_LT bit 1
virtex7 CMT rect MAIN[39]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 14 PLL[1]: PLL_DRP[23] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 12 PLL[1]: CLKFBIN_NOCOUNT PLL[1]: PLL_DRP[23] bit 13 PLL[1]: CLKFBIN_EDGE
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 10 PLL[1]: CLKFBIN_HT bit 4 PLL[1]: PLL_DRP[23] bit 11 PLL[1]: CLKFBIN_HT bit 5
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 8 PLL[1]: CLKFBIN_HT bit 2 PLL[1]: PLL_DRP[23] bit 9 PLL[1]: CLKFBIN_HT bit 3
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 6 PLL[1]: CLKFBIN_HT bit 0 PLL[1]: PLL_DRP[23] bit 7 PLL[1]: CLKFBIN_HT bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 4 PLL[1]: CLKFBIN_LT bit 4 PLL[1]: PLL_DRP[23] bit 5 PLL[1]: CLKFBIN_LT bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 2 PLL[1]: CLKFBIN_LT bit 2 PLL[1]: PLL_DRP[23] bit 3 PLL[1]: CLKFBIN_LT bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[23] bit 0 PLL[1]: CLKFBIN_LT bit 0 PLL[1]: PLL_DRP[23] bit 1 PLL[1]: CLKFBIN_LT bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 14 PLL[1]: PLL_DRP[22] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 12 PLL[1]: DIVCLK_NOCOUNT PLL[1]: PLL_DRP[22] bit 13 PLL[1]: DIVCLK_EDGE
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 10 PLL[1]: DIVCLK_HT bit 4 PLL[1]: PLL_DRP[22] bit 11 PLL[1]: DIVCLK_HT bit 5
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 8 PLL[1]: DIVCLK_HT bit 2 PLL[1]: PLL_DRP[22] bit 9 PLL[1]: DIVCLK_HT bit 3
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 6 PLL[1]: DIVCLK_HT bit 0 PLL[1]: PLL_DRP[22] bit 7 PLL[1]: DIVCLK_HT bit 1
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 4 PLL[1]: DIVCLK_LT bit 4 PLL[1]: PLL_DRP[22] bit 5 PLL[1]: DIVCLK_LT bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 2 PLL[1]: DIVCLK_LT bit 2 PLL[1]: PLL_DRP[22] bit 3 PLL[1]: DIVCLK_LT bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[22] bit 0 PLL[1]: DIVCLK_LT bit 0 PLL[1]: PLL_DRP[22] bit 1 PLL[1]: DIVCLK_LT bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 14 PLL[1]: PLL_DRP[21] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 12 PLL[1]: PLL_DRP[21] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 10 PLL[1]: PLL_DRP[21] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 8 PLL[1]: CLKFBOUT_MX bit 0 PLL[1]: PLL_DRP[21] bit 9 PLL[1]: CLKFBOUT_MX bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 6 PLL[1]: CLKFBOUT_NOCOUNT PLL[1]: PLL_DRP[21] bit 7 PLL[1]: CLKFBOUT_EDGE
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 4 PLL[1]: CLKFBOUT_DT bit 4 PLL[1]: PLL_DRP[21] bit 5 PLL[1]: CLKFBOUT_DT bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 2 PLL[1]: CLKFBOUT_DT bit 2 PLL[1]: PLL_DRP[21] bit 3 PLL[1]: CLKFBOUT_DT bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[21] bit 0 PLL[1]: CLKFBOUT_DT bit 0 PLL[1]: PLL_DRP[21] bit 1 PLL[1]: CLKFBOUT_DT bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 14 PLL[1]: CLKFBOUT_PM bit 1 PLL[1]: PLL_DRP[20] bit 15 PLL[1]: CLKFBOUT_PM bit 2
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 12 PLL[1]: CLKFBOUT_EN PLL[1]: PLL_DRP[20] bit 13 PLL[1]: CLKFBOUT_PM bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 10 PLL[1]: CLKFBOUT_HT bit 4 PLL[1]: PLL_DRP[20] bit 11 PLL[1]: CLKFBOUT_HT bit 5
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 8 PLL[1]: CLKFBOUT_HT bit 2 PLL[1]: PLL_DRP[20] bit 9 PLL[1]: CLKFBOUT_HT bit 3
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 6 PLL[1]: CLKFBOUT_HT bit 0 PLL[1]: PLL_DRP[20] bit 7 PLL[1]: CLKFBOUT_HT bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 4 PLL[1]: CLKFBOUT_LT bit 4 PLL[1]: PLL_DRP[20] bit 5 PLL[1]: CLKFBOUT_LT bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 2 PLL[1]: CLKFBOUT_LT bit 2 PLL[1]: PLL_DRP[20] bit 3 PLL[1]: CLKFBOUT_LT bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[20] bit 0 PLL[1]: CLKFBOUT_LT bit 0 PLL[1]: PLL_DRP[20] bit 1 PLL[1]: CLKFBOUT_LT bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 14 PLL[1]: PLL_DRP[19] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 12 PLL[1]: PLL_DRP[19] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 10 PLL[1]: PLL_DRP[19] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 8 PLL[1]: PLL_DRP[19] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 6 PLL[1]: PLL_DRP[19] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 4 PLL[1]: PLL_DRP[19] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 2 PLL[1]: PLL_DRP[19] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[19] bit 0 PLL[1]: PLL_DRP[19] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 14 PLL[1]: PLL_DRP[18] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 12 PLL[1]: PLL_DRP[18] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 10 PLL[1]: PLL_DRP[18] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 8 PLL[1]: PLL_DRP[18] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 6 PLL[1]: PLL_DRP[18] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 4 PLL[1]: PLL_DRP[18] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 2 PLL[1]: PLL_DRP[18] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[18] bit 0 PLL[1]: PLL_DRP[18] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 14 PLL[1]: PLL_DRP[17] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 12 PLL[1]: PLL_DRP[17] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 10 PLL[1]: PLL_DRP[17] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 8 PLL[1]: CLKOUT4_MX bit 0 PLL[1]: PLL_DRP[17] bit 9 PLL[1]: CLKOUT4_MX bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 6 PLL[1]: CLKOUT4_NOCOUNT PLL[1]: PLL_DRP[17] bit 7 PLL[1]: CLKOUT4_EDGE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 4 PLL[1]: CLKOUT4_DT bit 4 PLL[1]: PLL_DRP[17] bit 5 PLL[1]: CLKOUT4_DT bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 2 PLL[1]: CLKOUT4_DT bit 2 PLL[1]: PLL_DRP[17] bit 3 PLL[1]: CLKOUT4_DT bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[17] bit 0 PLL[1]: CLKOUT4_DT bit 0 PLL[1]: PLL_DRP[17] bit 1 PLL[1]: CLKOUT4_DT bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 14 PLL[1]: CLKOUT4_PM bit 1 PLL[1]: PLL_DRP[16] bit 15 PLL[1]: CLKOUT4_PM bit 2
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 12 PLL[1]: CLKOUT4_EN PLL[1]: PLL_DRP[16] bit 13 PLL[1]: CLKOUT4_PM bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 10 PLL[1]: CLKOUT4_HT bit 4 PLL[1]: PLL_DRP[16] bit 11 PLL[1]: CLKOUT4_HT bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 8 PLL[1]: CLKOUT4_HT bit 2 PLL[1]: PLL_DRP[16] bit 9 PLL[1]: CLKOUT4_HT bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 6 PLL[1]: CLKOUT4_HT bit 0 PLL[1]: PLL_DRP[16] bit 7 PLL[1]: CLKOUT4_HT bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 4 PLL[1]: CLKOUT4_LT bit 4 PLL[1]: PLL_DRP[16] bit 5 PLL[1]: CLKOUT4_LT bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 2 PLL[1]: CLKOUT4_LT bit 2 PLL[1]: PLL_DRP[16] bit 3 PLL[1]: CLKOUT4_LT bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[16] bit 0 PLL[1]: CLKOUT4_LT bit 0 PLL[1]: PLL_DRP[16] bit 1 PLL[1]: CLKOUT4_LT bit 1
virtex7 CMT rect MAIN[40]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 14 PLL[1]: PLL_DRP[31] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 12 PLL[1]: PLL_DRP[31] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 10 PLL[1]: PLL_DRP[31] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 8 PLL[1]: V7_DVDD_COMP_SET bit 1 PLL[1]: PLL_DRP[31] bit 9 PLL[1]: V7_DVDD_COMP_SET bit 2
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 6 PLL[1]: DVDD_VBG_PD bit 2 PLL[1]: PLL_DRP[31] bit 7 PLL[1]: V7_DVDD_COMP_SET bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 4 PLL[1]: DVDD_VBG_PD bit 0 PLL[1]: PLL_DRP[31] bit 5 PLL[1]: DVDD_VBG_PD bit 1
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 2 PLL[1]: DVDD_VBG_SEL bit 2 PLL[1]: PLL_DRP[31] bit 3 PLL[1]: DVDD_VBG_SEL bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[31] bit 0 PLL[1]: DVDD_VBG_SEL bit 0 PLL[1]: PLL_DRP[31] bit 1 PLL[1]: DVDD_VBG_SEL bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 14 PLL[1]: SEL_LV_NMOS PLL[1]: PLL_DRP[30] bit 15 PLL[1]: SUP_SEL_DREG
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 12 PLL[1]: PLL_DRP[30] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 10 PLL[1]: PLL_DRP[30] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 8 PLL[1]: PLL_DRP[30] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 6 PLL[1]: PLL_DRP[30] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 4 PLL[1]: PLL_DRP[30] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 2 PLL[1]: PLL_DRP[30] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[30] bit 0 PLL[1]: PLL_DRP[30] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 14 PLL[1]: PLL_DRP[29] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 12 PLL[1]: PLL_DRP[29] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 10 PLL[1]: PFD bit 6 PLL[1]: PLL_DRP[29] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 8 PLL[1]: PFD bit 4 PLL[1]: PLL_DRP[29] bit 9 PLL[1]: PFD bit 5
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 6 PLL[1]: PFD bit 2 PLL[1]: PLL_DRP[29] bit 7 PLL[1]: PFD bit 3
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 4 PLL[1]: PFD bit 0 PLL[1]: PLL_DRP[29] bit 5 PLL[1]: PFD bit 1
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 2 PLL[1]: PLL_DRP[29] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[29] bit 0 PLL[1]: PLL_DRP[29] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 14 PLL[1]: PLL_DRP[28] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 12 PLL[1]: PLL_DRP[28] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 10 PLL[1]: PLL_DRP[28] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 8 PLL[1]: PLL_DRP[28] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 6 PLL[1]: PLL_DRP[28] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 4 PLL[1]: SPARE_DIGITAL bit 4 PLL[1]: PLL_DRP[28] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 2 PLL[1]: SPARE_DIGITAL bit 2 PLL[1]: PLL_DRP[28] bit 3 PLL[1]: SPARE_DIGITAL bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[28] bit 0 PLL[1]: SPARE_DIGITAL bit 0 PLL[1]: PLL_DRP[28] bit 1 PLL[1]: SPARE_DIGITAL bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 14 PLL[1]: PLL_DRP[27] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 12 PLL[1]: PLL_DRP[27] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 10 PLL[1]: PLL_DRP[27] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 8 PLL[1]: PLL_DRP[27] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 6 PLL[1]: PLL_DRP[27] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 4 PLL[1]: PLL_DRP[27] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 2 PLL[1]: PLL_DRP[27] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[27] bit 0 PLL[1]: FREQ_COMP bit 1 PLL[1]: PLL_DRP[27] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 14 PLL[1]: LOCK_REF_DLY bit 4 PLL[1]: PLL_DRP[26] bit 15 PLL[1]: FREQ_COMP bit 0
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 12 PLL[1]: LOCK_REF_DLY bit 2 PLL[1]: PLL_DRP[26] bit 13 PLL[1]: LOCK_REF_DLY bit 3
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 10 PLL[1]: LOCK_REF_DLY bit 0 PLL[1]: PLL_DRP[26] bit 11 PLL[1]: LOCK_REF_DLY bit 1
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 8 PLL[1]: LOCK_SAT_HIGH bit 8 PLL[1]: PLL_DRP[26] bit 9 PLL[1]: LOCK_SAT_HIGH bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 6 PLL[1]: LOCK_SAT_HIGH bit 6 PLL[1]: PLL_DRP[26] bit 7 PLL[1]: LOCK_SAT_HIGH bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 4 PLL[1]: LOCK_SAT_HIGH bit 4 PLL[1]: PLL_DRP[26] bit 5 PLL[1]: LOCK_SAT_HIGH bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 2 PLL[1]: LOCK_SAT_HIGH bit 2 PLL[1]: PLL_DRP[26] bit 3 PLL[1]: LOCK_SAT_HIGH bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[26] bit 0 PLL[1]: LOCK_SAT_HIGH bit 0 PLL[1]: PLL_DRP[26] bit 1 PLL[1]: LOCK_SAT_HIGH bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 14 PLL[1]: LOCK_FB_DLY bit 4 PLL[1]: PLL_DRP[25] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 12 PLL[1]: LOCK_FB_DLY bit 2 PLL[1]: PLL_DRP[25] bit 13 PLL[1]: LOCK_FB_DLY bit 3
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 10 PLL[1]: LOCK_FB_DLY bit 0 PLL[1]: PLL_DRP[25] bit 11 PLL[1]: LOCK_FB_DLY bit 1
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 8 PLL[1]: UNLOCK_CNT bit 8 PLL[1]: PLL_DRP[25] bit 9 PLL[1]: UNLOCK_CNT bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 6 PLL[1]: UNLOCK_CNT bit 6 PLL[1]: PLL_DRP[25] bit 7 PLL[1]: UNLOCK_CNT bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 4 PLL[1]: UNLOCK_CNT bit 4 PLL[1]: PLL_DRP[25] bit 5 PLL[1]: UNLOCK_CNT bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 2 PLL[1]: UNLOCK_CNT bit 2 PLL[1]: PLL_DRP[25] bit 3 PLL[1]: UNLOCK_CNT bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[25] bit 0 PLL[1]: UNLOCK_CNT bit 0 PLL[1]: PLL_DRP[25] bit 1 PLL[1]: UNLOCK_CNT bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 14 PLL[1]: PLL_DRP[24] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 12 PLL[1]: PLL_DRP[24] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 10 PLL[1]: PLL_DRP[24] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 8 PLL[1]: LOCK_CNT bit 8 PLL[1]: PLL_DRP[24] bit 9 PLL[1]: LOCK_CNT bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 6 PLL[1]: LOCK_CNT bit 6 PLL[1]: PLL_DRP[24] bit 7 PLL[1]: LOCK_CNT bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 4 PLL[1]: LOCK_CNT bit 4 PLL[1]: PLL_DRP[24] bit 5 PLL[1]: LOCK_CNT bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 2 PLL[1]: LOCK_CNT bit 2 PLL[1]: PLL_DRP[24] bit 3 PLL[1]: LOCK_CNT bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[24] bit 0 PLL[1]: LOCK_CNT bit 0 PLL[1]: PLL_DRP[24] bit 1 PLL[1]: LOCK_CNT bit 1
virtex7 CMT rect MAIN[41]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 14 PLL[1]: PLL_DRP[39] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 12 PLL[1]: PLL_DRP[39] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 10 PLL[1]: PLL_DRP[39] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 8 PLL[1]: PLL_DRP[39] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 6 PLL[1]: PLL_DRP[39] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 4 PLL[1]: PLL_DRP[39] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 2 PLL[1]: PLL_DRP[39] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[39] bit 0 PLL[1]: PLL_DRP[39] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 14 PLL[1]: PLL_DRP[38] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 12 PLL[1]: PLL_DRP[38] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 10 PLL[1]: PLL_DRP[38] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 8 PLL[1]: ANALOG_MISC bit 3 PLL[1]: PLL_DRP[38] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 6 PLL[1]: PLL_DRP[38] bit 7 PLL[1]: ANALOG_MISC bit 2
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 4 PLL[1]: ANALOG_MISC bit 1 PLL[1]: PLL_DRP[38] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 2 PLL[1]: PLL_DRP[38] bit 3 PLL[1]: ANALOG_MISC bit 0
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[38] bit 0 PLL[1]: PLL_DRP[38] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 14 PLL[1]: PLL_DRP[37] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 12 PLL[1]: PLL_DRP[37] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 10 PLL[1]: PLL_DRP[37] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 8 PLL[1]: PLL_DRP[37] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 6 PLL[1]: PLL_DRP[37] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 4 PLL[1]: PLL_DRP[37] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 2 PLL[1]: PLL_DRP[37] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[37] bit 0 PLL[1]: PLL_DRP[37] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 14 PLL[1]: PLL_DRP[36] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 12 PLL[1]: PLL_DRP[36] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 10 PLL[1]: PLL_DRP[36] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 8 PLL[1]: PLL_DRP[36] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 6 PLL[1]: PLL_DRP[36] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 4 PLL[1]: PLL_DRP[36] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 2 PLL[1]: PLL_DRP[36] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[36] bit 0 PLL[1]: PLL_DRP[36] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 14 PLL[1]: PLL_DRP[35] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 12 PLL[1]: PLL_DRP[35] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 10 PLL[1]: PLL_DRP[35] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 8 PLL[1]: PLL_DRP[35] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 6 PLL[1]: PLL_DRP[35] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 4 PLL[1]: PLL_DRP[35] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 2 PLL[1]: PLL_DRP[35] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[35] bit 0 PLL[1]: PLL_DRP[35] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 14 PLL[1]: PLL_DRP[34] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 12 PLL[1]: PLL_DRP[34] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 10 PLL[1]: PLL_DRP[34] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 8 PLL[1]: PLL_DRP[34] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 6 PLL[1]: PLL_DRP[34] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 4 PLL[1]: PLL_DRP[34] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 2 PLL[1]: PLL_DRP[34] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[34] bit 0 PLL[1]: EN_VCO_DIV6 PLL[1]: PLL_DRP[34] bit 1 PLL[1]: EN_VCO_DIV1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 14 PLL[1]: PLL_DRP[33] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 12 PLL[1]: PLL_DRP[33] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 10 PLL[1]: PLL_DRP[33] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 8 PLL[1]: PLL_DRP[33] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 6 PLL[1]: PLL_DRP[33] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 4 PLL[1]: PLL_DRP[33] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 2 PLL[1]: PLL_DRP[33] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[33] bit 0 PLL[1]: PLL_DRP[33] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 14 PLL[1]: PLL_DRP[32] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 12 PLL[1]: PLL_DRP[32] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 10 PLL[1]: PLL_DRP[32] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 8 PLL[1]: PLL_DRP[32] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 6 PLL[1]: PLL_DRP[32] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 4 PLL[1]: PLL_DRP[32] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 2 PLL[1]: PLL_DRP[32] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[32] bit 0 PLL[1]: PLL_DRP[32] bit 1
virtex7 CMT rect MAIN[42]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 14 PLL[1]: PLL_DRP[47] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 12 PLL[1]: PLL_DRP[47] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 10 PLL[1]: PLL_DRP[47] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 8 PLL[1]: PLL_DRP[47] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 6 PLL[1]: PLL_DRP[47] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 4 PLL[1]: PLL_DRP[47] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 2 PLL[1]: PLL_DRP[47] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[47] bit 0 PLL[1]: PLL_DRP[47] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 14 PLL[1]: PLL_DRP[46] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 12 PLL[1]: PLL_DRP[46] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 10 PLL[1]: PLL_DRP[46] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 8 PLL[1]: PLL_DRP[46] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 6 PLL[1]: PLL_DRP[46] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 4 PLL[1]: PLL_DRP[46] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 2 PLL[1]: PLL_DRP[46] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[46] bit 0 PLL[1]: PLL_DRP[46] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 14 PLL[1]: PLL_DRP[45] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 12 PLL[1]: PLL_DRP[45] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 10 PLL[1]: PLL_DRP[45] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 8 PLL[1]: PLL_DRP[45] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 6 PLL[1]: PLL_DRP[45] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 4 PLL[1]: PLL_DRP[45] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 2 PLL[1]: PLL_DRP[45] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[45] bit 0 PLL[1]: PLL_DRP[45] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 14 PLL[1]: PLL_DRP[44] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 12 PLL[1]: PLL_DRP[44] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 10 PLL[1]: PLL_DRP[44] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 8 PLL[1]: PLL_DRP[44] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 6 PLL[1]: PLL_DRP[44] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 4 PLL[1]: PLL_DRP[44] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 2 PLL[1]: PLL_DRP[44] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[44] bit 0 PLL[1]: PLL_DRP[44] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 14 PLL[1]: PLL_DRP[43] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 12 PLL[1]: PLL_DRP[43] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 10 PLL[1]: PLL_DRP[43] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 8 PLL[1]: PLL_DRP[43] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 6 PLL[1]: PLL_DRP[43] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 4 PLL[1]: PLL_DRP[43] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 2 PLL[1]: PLL_DRP[43] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[43] bit 0 PLL[1]: PLL_DRP[43] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 14 PLL[1]: PLL_DRP[42] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 12 PLL[1]: PLL_DRP[42] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 10 PLL[1]: PLL_DRP[42] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 8 PLL[1]: PLL_DRP[42] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 6 PLL[1]: PLL_DRP[42] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 4 PLL[1]: PLL_DRP[42] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 2 PLL[1]: PLL_DRP[42] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[42] bit 0 PLL[1]: PLL_DRP[42] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 14 PLL[1]: PLL_DRP[41] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 12 PLL[1]: PLL_DRP[41] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 10 PLL[1]: PLL_DRP[41] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 8 PLL[1]: PLL_DRP[41] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 6 PLL[1]: PLL_DRP[41] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 4 PLL[1]: PLL_DRP[41] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 2 PLL[1]: PLL_DRP[41] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[41] bit 0 PLL[1]: PLL_DRP[41] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 14 PLL[1]: PLL_DRP[40] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 12 PLL[1]: PLL_DRP[40] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 10 PLL[1]: PLL_DRP[40] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 8 PLL[1]: PLL_DRP[40] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 6 PLL[1]: PLL_DRP[40] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 4 PLL[1]: PLL_DRP[40] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 2 PLL[1]: PLL_DRP[40] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[40] bit 0 PLL[1]: PLL_DRP[40] bit 1
virtex7 CMT rect MAIN[43]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 14 PLL[1]: PLL_DRP[55] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 12 PLL[1]: PLL_DRP[55] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 10 PLL[1]: PLL_DRP[55] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 8 PLL[1]: PLL_DRP[55] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 6 PLL[1]: PLL_DRP[55] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 4 PLL[1]: PLL_DRP[55] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 2 PLL[1]: PLL_DRP[55] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[55] bit 0 PLL[1]: PLL_DRP[55] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 14 PLL[1]: PLL_DRP[54] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 12 PLL[1]: PLL_DRP[54] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 10 PLL[1]: PLL_DRP[54] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 8 PLL[1]: PLL_DRP[54] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 6 PLL[1]: PLL_DRP[54] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 4 PLL[1]: PLL_DRP[54] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 2 PLL[1]: PLL_DRP[54] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[54] bit 0 PLL[1]: PLL_DRP[54] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 14 PLL[1]: PLL_DRP[53] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 12 PLL[1]: PLL_DRP[53] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 10 PLL[1]: PLL_DRP[53] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 8 PLL[1]: PLL_DRP[53] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 6 PLL[1]: PLL_DRP[53] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 4 PLL[1]: PLL_DRP[53] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 2 PLL[1]: PLL_DRP[53] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[53] bit 0 PLL[1]: PLL_DRP[53] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 14 PLL[1]: PLL_DRP[52] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 12 PLL[1]: PLL_DRP[52] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 10 PLL[1]: PLL_DRP[52] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 8 PLL[1]: PLL_DRP[52] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 6 PLL[1]: PLL_DRP[52] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 4 PLL[1]: PLL_DRP[52] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 2 PLL[1]: PLL_DRP[52] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[52] bit 0 PLL[1]: PLL_DRP[52] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 14 PLL[1]: PLL_DRP[51] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 12 PLL[1]: PLL_DRP[51] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 10 PLL[1]: PLL_DRP[51] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 8 PLL[1]: PLL_DRP[51] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 6 PLL[1]: PLL_DRP[51] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 4 PLL[1]: PLL_DRP[51] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 2 PLL[1]: PLL_DRP[51] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[51] bit 0 PLL[1]: PLL_DRP[51] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 14 PLL[1]: PLL_DRP[50] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 12 PLL[1]: PLL_DRP[50] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 10 PLL[1]: PLL_DRP[50] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 8 PLL[1]: PLL_DRP[50] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 6 PLL[1]: PLL_DRP[50] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 4 PLL[1]: PLL_DRP[50] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 2 PLL[1]: PLL_DRP[50] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[50] bit 0 PLL[1]: PLL_DRP[50] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 14 PLL[1]: PLL_DRP[49] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 12 PLL[1]: PLL_DRP[49] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 10 PLL[1]: PLL_DRP[49] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 8 PLL[1]: PLL_DRP[49] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 6 PLL[1]: PLL_DRP[49] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 4 PLL[1]: PLL_DRP[49] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 2 PLL[1]: PLL_DRP[49] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[49] bit 0 PLL[1]: PLL_DRP[49] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 14 PLL[1]: PLL_DRP[48] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 12 PLL[1]: PLL_DRP[48] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 10 PLL[1]: PLL_DRP[48] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 8 PLL[1]: PLL_DRP[48] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 6 PLL[1]: PLL_DRP[48] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 4 PLL[1]: PLL_DRP[48] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 2 PLL[1]: PLL_DRP[48] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[48] bit 0 PLL[1]: PLL_DRP[48] bit 1
virtex7 CMT rect MAIN[44]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 14 PLL[1]: PLL_DRP[63] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 12 PLL[1]: PLL_DRP[63] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 10 PLL[1]: PLL_DRP[63] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 8 PLL[1]: PLL_DRP[63] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 6 PLL[1]: PLL_DRP[63] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 4 PLL[1]: PLL_DRP[63] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 2 PLL[1]: PLL_DRP[63] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[63] bit 0 PLL[1]: PLL_DRP[63] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 14 PLL[1]: PLL_DRP[62] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 12 PLL[1]: PLL_DRP[62] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 10 PLL[1]: PLL_DRP[62] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 8 PLL[1]: PLL_DRP[62] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 6 PLL[1]: PLL_DRP[62] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 4 PLL[1]: PLL_DRP[62] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 2 PLL[1]: PLL_DRP[62] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[62] bit 0 PLL[1]: PLL_DRP[62] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 14 PLL[1]: PLL_DRP[61] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 12 PLL[1]: PLL_DRP[61] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 10 PLL[1]: PLL_DRP[61] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 8 PLL[1]: PLL_DRP[61] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 6 PLL[1]: PLL_DRP[61] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 4 PLL[1]: PLL_DRP[61] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 2 PLL[1]: PLL_DRP[61] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[61] bit 0 PLL[1]: PLL_DRP[61] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 14 PLL[1]: PLL_DRP[60] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 12 PLL[1]: PLL_DRP[60] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 10 PLL[1]: PLL_DRP[60] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 8 PLL[1]: PLL_DRP[60] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 6 PLL[1]: PLL_DRP[60] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 4 PLL[1]: PLL_DRP[60] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 2 PLL[1]: PLL_DRP[60] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[60] bit 0 PLL[1]: PLL_DRP[60] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 14 PLL[1]: PLL_DRP[59] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 12 PLL[1]: PLL_DRP[59] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 10 PLL[1]: PLL_DRP[59] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 8 PLL[1]: PLL_DRP[59] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 6 PLL[1]: PLL_DRP[59] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 4 PLL[1]: PLL_DRP[59] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 2 PLL[1]: PLL_DRP[59] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[59] bit 0 PLL[1]: PLL_DRP[59] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 14 PLL[1]: PLL_DRP[58] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 12 PLL[1]: PLL_DRP[58] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 10 PLL[1]: PLL_DRP[58] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 8 PLL[1]: PLL_DRP[58] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 6 PLL[1]: PLL_DRP[58] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 4 PLL[1]: PLL_DRP[58] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 2 PLL[1]: PLL_DRP[58] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[58] bit 0 PLL[1]: PLL_DRP[58] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 14 PLL[1]: PLL_DRP[57] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 12 PLL[1]: PLL_DRP[57] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 10 PLL[1]: PLL_DRP[57] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 8 PLL[1]: PLL_DRP[57] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 6 PLL[1]: PLL_DRP[57] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 4 PLL[1]: PLL_DRP[57] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 2 PLL[1]: PLL_DRP[57] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[57] bit 0 PLL[1]: PLL_DRP[57] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 14 PLL[1]: PLL_DRP[56] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 12 PLL[1]: PLL_DRP[56] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 10 PLL[1]: PLL_DRP[56] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 8 PLL[1]: PLL_DRP[56] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 6 PLL[1]: PLL_DRP[56] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 4 PLL[1]: PLL_DRP[56] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 2 PLL[1]: PLL_DRP[56] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[56] bit 0 PLL[1]: PLL_DRP[56] bit 1
virtex7 CMT rect MAIN[45]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 14 PLL[1]: PLL_DRP[71] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 12 PLL[1]: PLL_DRP[71] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 10 PLL[1]: PLL_DRP[71] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 8 PLL[1]: PLL_DRP[71] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 6 PLL[1]: PLL_DRP[71] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 4 PLL[1]: PLL_DRP[71] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 2 PLL[1]: PLL_DRP[71] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[71] bit 0 PLL[1]: PLL_DRP[71] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 14 PLL[1]: PLL_DRP[70] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 12 PLL[1]: PLL_DRP[70] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 10 PLL[1]: PLL_DRP[70] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 8 PLL[1]: PLL_DRP[70] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 6 PLL[1]: PLL_DRP[70] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 4 PLL[1]: PLL_DRP[70] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 2 PLL[1]: PLL_DRP[70] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[70] bit 0 PLL[1]: VLF_HIGH_PWDN_B PLL[1]: PLL_DRP[70] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 14 PLL[1]: PLL_DRP[69] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 12 PLL[1]: VREF_START bit 1 PLL[1]: PLL_DRP[69] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 10 PLL[1]: PLL_DRP[69] bit 11 PLL[1]: VREF_START bit 0
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 8 PLL[1]: PLL_DRP[69] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 6 PLL[1]: PLL_DRP[69] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 4 PLL[1]: PLL_DRP[69] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 2 PLL[1]: PLL_DRP[69] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[69] bit 0 PLL[1]: PLL_DRP[69] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 14 PLL[1]: PLL_DRP[68] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 12 PLL[1]: PLL_DRP[68] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 10 PLL[1]: PLL_DRP[68] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 8 PLL[1]: SPARE_ANALOG bit 4 PLL[1]: PLL_DRP[68] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 6 PLL[1]: PLL_DRP[68] bit 7 PLL[1]: SPARE_ANALOG bit 3
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 4 PLL[1]: SPARE_ANALOG bit 2 PLL[1]: PLL_DRP[68] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 2 PLL[1]: PLL_DRP[68] bit 3 PLL[1]: SPARE_ANALOG bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[68] bit 0 PLL[1]: SPARE_ANALOG bit 0 PLL[1]: PLL_DRP[68] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 14 PLL[1]: PLL_DRP[67] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 12 PLL[1]: PLL_DRP[67] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 10 PLL[1]: PLL_DRP[67] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 8 PLL[1]: PLL_DRP[67] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 6 PLL[1]: PLL_DRP[67] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 4 PLL[1]: PLL_DRP[67] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 2 PLL[1]: PLL_DRP[67] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[67] bit 0 PLL[1]: LF_LOW_SEL PLL[1]: PLL_DRP[67] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 14 PLL[1]: PLL_DRP[66] bit 15 PLL[1]: LF_NEN bit 1
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 12 PLL[1]: LF_NEN bit 0 PLL[1]: PLL_DRP[66] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 10 PLL[1]: PLL_DRP[66] bit 11 PLL[1]: LF_PEN bit 1
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 8 PLL[1]: LF_PEN bit 0 PLL[1]: PLL_DRP[66] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 6 PLL[1]: PLL_DRP[66] bit 7 PLL[1]: VLF_HIGH_DIS_B
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 4 PLL[1]: MAN_LF bit 2 PLL[1]: PLL_DRP[66] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 2 PLL[1]: PLL_DRP[66] bit 3 PLL[1]: MAN_LF bit 1
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[66] bit 0 PLL[1]: MAN_LF bit 0 PLL[1]: PLL_DRP[66] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 14 PLL[1]: PLL_DRP[65] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 12 PLL[1]: PLL_DRP[65] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 10 PLL[1]: PLL_DRP[65] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 8 PLL[1]: PLL_DRP[65] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 6 PLL[1]: PLL_DRP[65] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 4 PLL[1]: PLL_DRP[65] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 2 PLL[1]: PLL_DRP[65] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[65] bit 0 PLL[1]: PLL_DRP[65] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 14 PLL[1]: PLL_DRP[64] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 12 PLL[1]: PLL_DRP[64] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 10 PLL[1]: PLL_DRP[64] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 8 PLL[1]: PLL_DRP[64] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 6 PLL[1]: PLL_DRP[64] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 4 PLL[1]: PLL_DRP[64] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 2 PLL[1]: PLL_DRP[64] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[64] bit 0 PLL[1]: PLL_DRP[64] bit 1
virtex7 CMT rect MAIN[46]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 14 PLL[1]: PLL_DRP[79] bit 15 PLL[1]: RES bit 3
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 12 PLL[1]: RES bit 2 PLL[1]: PLL_DRP[79] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 10 PLL[1]: PLL_DRP[79] bit 11 PLL[1]: RES bit 1
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 8 PLL[1]: RES bit 0 PLL[1]: PLL_DRP[79] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 6 PLL[1]: PLL_DRP[79] bit 7 PLL[1]: LFHF bit 1
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 4 PLL[1]: LFHF bit 0 PLL[1]: PLL_DRP[79] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 2 PLL[1]: PLL_DRP[79] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[79] bit 0 PLL[1]: PLL_DRP[79] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 14 PLL[1]: PLL_DRP[78] bit 15 PLL[1]: CP bit 3
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 12 PLL[1]: CP bit 2 PLL[1]: PLL_DRP[78] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 10 PLL[1]: PLL_DRP[78] bit 11 PLL[1]: CP bit 1
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 8 PLL[1]: CP bit 0 PLL[1]: PLL_DRP[78] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 6 PLL[1]: PLL_DRP[78] bit 7 PLL[1]: CP_BIAS_TRIP_SET bit 0
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 4 PLL[1]: CP_RES bit 1 PLL[1]: PLL_DRP[78] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 2 PLL[1]: PLL_DRP[78] bit 3 PLL[1]: CP_RES bit 0
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[78] bit 0 PLL[1]: PLL_DRP[78] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 14 PLL[1]: PLL_DRP[77] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 12 PLL[1]: PLL_DRP[77] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 10 PLL[1]: PLL_DRP[77] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 8 PLL[1]: PLL_DRP[77] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 6 PLL[1]: PLL_DRP[77] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 4 PLL[1]: PLL_DRP[77] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 2 PLL[1]: PLL_DRP[77] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[77] bit 0 PLL[1]: PLL_DRP[77] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 14 PLL[1]: PLL_DRP[76] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 12 PLL[1]: HVLF_CNT_TEST_EN PLL[1]: PLL_DRP[76] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 10 PLL[1]: PLL_DRP[76] bit 11 PLL[1]: HVLF_CNT_TEST bit 5
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 8 PLL[1]: HVLF_CNT_TEST bit 4 PLL[1]: PLL_DRP[76] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 6 PLL[1]: PLL_DRP[76] bit 7 PLL[1]: HVLF_CNT_TEST bit 3
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 4 PLL[1]: HVLF_CNT_TEST bit 2 PLL[1]: PLL_DRP[76] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 2 PLL[1]: PLL_DRP[76] bit 3 PLL[1]: HVLF_CNT_TEST bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[76] bit 0 PLL[1]: HVLF_CNT_TEST bit 0 PLL[1]: PLL_DRP[76] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 14 PLL[1]: PLL_DRP[75] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 12 PLL[1]: PLL_DRP[75] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 10 PLL[1]: PLL_DRP[75] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 8 PLL[1]: PLL_DRP[75] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 6 PLL[1]: PLL_DRP[75] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 4 PLL[1]: PLL_DRP[75] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 2 PLL[1]: PLL_DRP[75] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[75] bit 0 PLL[1]: PLL_DRP[75] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 14 PLL[1]: PLL_DRP[74] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 12 PLL[1]: PLL_DRP[74] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 10 PLL[1]: PLL_DRP[74] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 8 PLL[1]: V7_AVDD_COMP_SET bit 1 PLL[1]: PLL_DRP[74] bit 9 PLL[1]: V7_AVDD_COMP_SET bit 2
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 6 PLL[1]: AVDD_VBG_PD bit 2 PLL[1]: PLL_DRP[74] bit 7 PLL[1]: V7_AVDD_COMP_SET bit 0
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 4 PLL[1]: AVDD_VBG_PD bit 0 PLL[1]: PLL_DRP[74] bit 5 PLL[1]: AVDD_VBG_PD bit 1
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 2 PLL[1]: AVDD_VBG_SEL bit 2 PLL[1]: PLL_DRP[74] bit 3 PLL[1]: AVDD_VBG_SEL bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[74] bit 0 PLL[1]: AVDD_VBG_SEL bit 0 PLL[1]: PLL_DRP[74] bit 1 PLL[1]: AVDD_VBG_SEL bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 14 PLL[1]: EN_CURR_SINK bit 1 PLL[1]: PLL_DRP[73] bit 15 PLL[1]: SUP_SEL_AREG
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 12 PLL[1]: MVDD_SEL bit 1 PLL[1]: PLL_DRP[73] bit 13 PLL[1]: EN_CURR_SINK bit 0
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 10 PLL[1]: SEL_HV_NMOS PLL[1]: PLL_DRP[73] bit 11 PLL[1]: MVDD_SEL bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 8 PLL[1]: PLL_DRP[73] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 6 PLL[1]: PLL_DRP[73] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 4 PLL[1]: PLL_DRP[73] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 2 PLL[1]: PLL_DRP[73] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[73] bit 0 PLL[1]: PLL_DRP[73] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 14 PLL[1]: PLL_DRP[72] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 12 PLL[1]: PLL_DRP[72] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 10 PLL[1]: PLL_DRP[72] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 8 PLL[1]: PLL_DRP[72] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 6 PLL[1]: PLL_DRP[72] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 4 PLL[1]: PLL_DRP[72] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 2 PLL[1]: PLL_DRP[72] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[72] bit 0 PLL[1]: PLL_DRP[72] bit 1
virtex7 CMT rect MAIN[47]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 14 PLL[1]: PLL_DRP[87] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 12 PLL[1]: PLL_DRP[87] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 10 PLL[1]: PLL_DRP[87] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 8 PLL[1]: PLL_DRP[87] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 6 PLL[1]: PLL_DRP[87] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 4 PLL[1]: PLL_DRP[87] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 2 PLL[1]: PLL_DRP[87] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[87] bit 0 PLL[1]: PLL_DRP[87] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 14 PLL[1]: PLL_DRP[86] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 12 PLL[1]: PLL_DRP[86] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 10 PLL[1]: PLL_DRP[86] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 8 PLL[1]: PLL_DRP[86] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 6 PLL[1]: PLL_DRP[86] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 4 PLL[1]: PLL_DRP[86] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 2 PLL[1]: PLL_DRP[86] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[86] bit 0 PLL[1]: PLL_DRP[86] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 14 PLL[1]: PLL_DRP[85] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 12 PLL[1]: PLL_DRP[85] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 10 PLL[1]: PLL_DRP[85] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 8 PLL[1]: PLL_DRP[85] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 6 PLL[1]: PLL_DRP[85] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 4 PLL[1]: PLL_DRP[85] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 2 PLL[1]: PLL_DRP[85] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[85] bit 0 PLL[1]: PLL_DRP[85] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 14 PLL[1]: PLL_DRP[84] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 12 PLL[1]: PLL_DRP[84] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 10 PLL[1]: PLL_DRP[84] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 8 PLL[1]: PLL_DRP[84] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 6 PLL[1]: PLL_DRP[84] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 4 PLL[1]: PLL_DRP[84] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 2 PLL[1]: PLL_DRP[84] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[84] bit 0 PLL[1]: PLL_DRP[84] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 14 PLL[1]: PLL_DRP[83] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 12 PLL[1]: PLL_DRP[83] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 10 PLL[1]: PLL_DRP[83] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 8 PLL[1]: PLL_DRP[83] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 6 PLL[1]: PLL_DRP[83] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 4 PLL[1]: PLL_DRP[83] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 2 PLL[1]: PLL_DRP[83] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[83] bit 0 PLL[1]: PLL_DRP[83] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 14 PLL[1]: PLL_DRP[82] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 12 PLL[1]: PLL_DRP[82] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 10 PLL[1]: PLL_DRP[82] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 8 PLL[1]: PLL_DRP[82] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 6 PLL[1]: PLL_DRP[82] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 4 PLL[1]: PLL_DRP[82] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 2 PLL[1]: PLL_DRP[82] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[82] bit 0 PLL[1]: PLL_DRP[82] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 14 PLL[1]: PLL_DRP[81] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 12 PLL[1]: PLL_DRP[81] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 10 PLL[1]: PLL_DRP[81] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 8 PLL[1]: PLL_DRP[81] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 6 PLL[1]: PLL_DRP[81] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 4 PLL[1]: PLL_DRP[81] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 2 PLL[1]: PLL_DRP[81] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[81] bit 0 PLL[1]: PLL_DRP[81] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 14 PLL[1]: PLL_DRP[80] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 12 PLL[1]: PLL_DRP[80] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 10 PLL[1]: PLL_DRP[80] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 8 PLL[1]: PLL_DRP[80] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 6 PLL[1]: PLL_DRP[80] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 4 PLL[1]: PLL_DRP[80] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 2 PLL[1]: PLL_DRP[80] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[80] bit 0 PLL[1]: PLL_DRP[80] bit 1
virtex7 CMT rect MAIN[48]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 14 PLL[1]: CONTROL_1 bit 14 PLL[1]: PLL_DRP[95] bit 15 PLL[1]: CONTROL_1 bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 12 PLL[1]: CONTROL_1 bit 12 PLL[1]: PLL_DRP[95] bit 13 PLL[1]: CONTROL_1 bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 10 PLL[1]: CONTROL_1 bit 10 PLL[1]: PLL_DRP[95] bit 11 PLL[1]: CONTROL_1 bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 8 PLL[1]: CONTROL_1 bit 8 PLL[1]: PLL_DRP[95] bit 9 PLL[1]: CONTROL_1 bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 6 PLL[1]: CONTROL_1 bit 6 PLL[1]: PLL_DRP[95] bit 7 PLL[1]: CONTROL_1 bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 4 PLL[1]: CONTROL_1 bit 4 PLL[1]: PLL_DRP[95] bit 5 PLL[1]: CONTROL_1 bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 2 PLL[1]: CONTROL_1 bit 2 PLL[1]: PLL_DRP[95] bit 3 PLL[1]: CONTROL_1 bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[95] bit 0 PLL[1]: CONTROL_1 bit 0 PLL[1]: PLL_DRP[95] bit 1 PLL[1]: CONTROL_1 bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 14 PLL[1]: CONTROL_0 bit 14 PLL[1]: PLL_DRP[94] bit 15 PLL[1]: CONTROL_0 bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 12 PLL[1]: CONTROL_0 bit 12 PLL[1]: PLL_DRP[94] bit 13 PLL[1]: CONTROL_0 bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 10 PLL[1]: CONTROL_0 bit 10 PLL[1]: PLL_DRP[94] bit 11 PLL[1]: CONTROL_0 bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 8 PLL[1]: CONTROL_0 bit 8 PLL[1]: PLL_DRP[94] bit 9 PLL[1]: CONTROL_0 bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 6 PLL[1]: CONTROL_0 bit 6 PLL[1]: PLL_DRP[94] bit 7 PLL[1]: CONTROL_0 bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 4 PLL[1]: CONTROL_0 bit 4 PLL[1]: PLL_DRP[94] bit 5 PLL[1]: CONTROL_0 bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 2 PLL[1]: CONTROL_0 bit 2 PLL[1]: PLL_DRP[94] bit 3 PLL[1]: CONTROL_0 bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[94] bit 0 PLL[1]: CONTROL_0 bit 0 PLL[1]: PLL_DRP[94] bit 1 PLL[1]: CONTROL_0 bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 14 PLL[1]: PLL_DRP[93] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 12 PLL[1]: PLL_DRP[93] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 10 PLL[1]: PLL_DRP[93] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 8 PLL[1]: PLL_DRP[93] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 6 PLL[1]: PLL_DRP[93] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 4 PLL[1]: PLL_DRP[93] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 2 PLL[1]: PLL_DRP[93] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[93] bit 0 PLL[1]: PLL_DRP[93] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 14 PLL[1]: PLL_DRP[92] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 12 PLL[1]: PLL_DRP[92] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 10 PLL[1]: PLL_DRP[92] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 8 PLL[1]: PLL_DRP[92] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 6 PLL[1]: PLL_DRP[92] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 4 PLL[1]: PLL_DRP[92] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 2 PLL[1]: STARTUP_WAIT PLL[1]: PLL_DRP[92] bit 3 PLL[1]: GTS_WAIT
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[92] bit 0 PLL[1]: ENABLE PLL[1]: PLL_DRP[92] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 14 PLL[1]: PLL_DRP[91] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 12 PLL[1]: PLL_DRP[91] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 10 PLL[1]: PLL_DRP[91] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 8 PLL[1]: PLL_DRP[91] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 6 PLL[1]: PLL_DRP[91] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 4 PLL[1]: PLL_DRP[91] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 2 PLL[1]: PLL_DRP[91] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[91] bit 0 PLL[1]: PLL_DRP[91] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 14 PLL[1]: PLL_DRP[90] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 12 PLL[1]: PLL_DRP[90] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 10 PLL[1]: PLL_DRP[90] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 8 PLL[1]: PLL_DRP[90] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 6 PLL[1]: PLL_DRP[90] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: invert CLKINSEL PLL[1]: PLL_DRP[90] bit 4 PLL[1]: PLL_DRP[90] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[90] bit 2 PLL[1]: PLL_DRP[90] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: invert RST PLL[1]: PLL_DRP[90] bit 0 PLL[1]: invert PWRDWN PLL[1]: PLL_DRP[90] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 14 PLL[1]: PLL_DRP[89] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 12 PLL[1]: PLL_DRP[89] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 10 PLL[1]: PLL_DRP[89] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 8 PLL[1]: PLL_DRP[89] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 6 PLL[1]: PLL_DRP[89] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 4 PLL[1]: PLL_DRP[89] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 2 PLL[1]: PLL_DRP[89] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[89] bit 0 PLL[1]: PLL_DRP[89] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 14 PLL[1]: PLL_DRP[88] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 12 PLL[1]: PLL_DRP[88] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 10 PLL[1]: PLL_DRP[88] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 8 PLL[1]: PLL_DRP[88] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 6 PLL[1]: PLL_DRP[88] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 4 PLL[1]: PLL_DRP[88] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 2 PLL[1]: PLL_DRP[88] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[88] bit 0 PLL[1]: PLL_DRP[88] bit 1
virtex7 CMT rect MAIN[49]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 14 PLL[1]: PLL_DRP[103] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 12 PLL[1]: PLL_DRP[103] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 10 PLL[1]: PLL_DRP[103] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 8 PLL[1]: PLL_DRP[103] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 6 PLL[1]: PLL_DRP[103] bit 7
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 4 PLL[1]: PLL_DRP[103] bit 5
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 2 PLL[1]: PLL_DRP[103] bit 3
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[103] bit 0 PLL[1]: PLL_DRP[103] bit 1
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 14 PLL[1]: PLL_DRP[102] bit 15
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 12 PLL[1]: PLL_DRP[102] bit 13
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 10 PLL[1]: PLL_DRP[102] bit 11
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 8 PLL[1]: PLL_DRP[102] bit 9
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 6 PLL[1]: PLL_DRP[102] bit 7
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 4 PLL[1]: PLL_DRP[102] bit 5
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 2 PLL[1]: PLL_DRP[102] bit 3
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[102] bit 0 PLL[1]: PLL_DRP[102] bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 14 PLL[1]: CONTROL_7 bit 14 PLL[1]: PLL_DRP[101] bit 15 PLL[1]: CONTROL_7 bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 12 PLL[1]: CONTROL_7 bit 12 PLL[1]: PLL_DRP[101] bit 13 PLL[1]: CONTROL_7 bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 10 PLL[1]: CONTROL_7 bit 10 PLL[1]: PLL_DRP[101] bit 11 PLL[1]: CONTROL_7 bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 8 PLL[1]: CONTROL_7 bit 8 PLL[1]: PLL_DRP[101] bit 9 PLL[1]: CONTROL_7 bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 6 PLL[1]: CONTROL_7 bit 6 PLL[1]: PLL_DRP[101] bit 7 PLL[1]: CONTROL_7 bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 4 PLL[1]: CONTROL_7 bit 4 PLL[1]: PLL_DRP[101] bit 5 PLL[1]: CONTROL_7 bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 2 PLL[1]: CONTROL_7 bit 2 PLL[1]: PLL_DRP[101] bit 3 PLL[1]: CONTROL_7 bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[101] bit 0 PLL[1]: CONTROL_7 bit 0 PLL[1]: PLL_DRP[101] bit 1 PLL[1]: CONTROL_7 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 14 PLL[1]: CONTROL_6 bit 14 PLL[1]: PLL_DRP[100] bit 15 PLL[1]: CONTROL_6 bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 12 PLL[1]: CONTROL_6 bit 12 PLL[1]: PLL_DRP[100] bit 13 PLL[1]: CONTROL_6 bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 10 PLL[1]: CONTROL_6 bit 10 PLL[1]: PLL_DRP[100] bit 11 PLL[1]: CONTROL_6 bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 8 PLL[1]: CONTROL_6 bit 8 PLL[1]: PLL_DRP[100] bit 9 PLL[1]: CONTROL_6 bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 6 PLL[1]: CONTROL_6 bit 6 PLL[1]: PLL_DRP[100] bit 7 PLL[1]: CONTROL_6 bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 4 PLL[1]: CONTROL_6 bit 4 PLL[1]: PLL_DRP[100] bit 5 PLL[1]: CONTROL_6 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 2 PLL[1]: CONTROL_6 bit 2 PLL[1]: PLL_DRP[100] bit 3 PLL[1]: CONTROL_6 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[100] bit 0 PLL[1]: CONTROL_6 bit 0 PLL[1]: PLL_DRP[100] bit 1 PLL[1]: CONTROL_6 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 14 PLL[1]: CONTROL_5 bit 14 PLL[1]: PLL_DRP[99] bit 15 PLL[1]: CONTROL_5 bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 12 PLL[1]: CONTROL_5 bit 12 PLL[1]: PLL_DRP[99] bit 13 PLL[1]: CONTROL_5 bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 10 PLL[1]: CONTROL_5 bit 10 PLL[1]: PLL_DRP[99] bit 11 PLL[1]: CONTROL_5 bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 8 PLL[1]: CONTROL_5 bit 8 PLL[1]: PLL_DRP[99] bit 9 PLL[1]: CONTROL_5 bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 6 PLL[1]: CONTROL_5 bit 6 PLL[1]: PLL_DRP[99] bit 7 PLL[1]: CONTROL_5 bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 4 PLL[1]: CONTROL_5 bit 4 PLL[1]: PLL_DRP[99] bit 5 PLL[1]: CONTROL_5 bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 2 PLL[1]: CONTROL_5 bit 2 PLL[1]: PLL_DRP[99] bit 3 PLL[1]: CONTROL_5 bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[99] bit 0 PLL[1]: CONTROL_5 bit 0 PLL[1]: PLL_DRP[99] bit 1 PLL[1]: CONTROL_5 bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 14 PLL[1]: CONTROL_4 bit 14 PLL[1]: PLL_DRP[98] bit 15 PLL[1]: CONTROL_4 bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 12 PLL[1]: CONTROL_4 bit 12 PLL[1]: PLL_DRP[98] bit 13 PLL[1]: CONTROL_4 bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 10 PLL[1]: CONTROL_4 bit 10 PLL[1]: PLL_DRP[98] bit 11 PLL[1]: CONTROL_4 bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 8 PLL[1]: CONTROL_4 bit 8 PLL[1]: PLL_DRP[98] bit 9 PLL[1]: CONTROL_4 bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 6 PLL[1]: CONTROL_4 bit 6 PLL[1]: PLL_DRP[98] bit 7 PLL[1]: CONTROL_4 bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 4 PLL[1]: CONTROL_4 bit 4 PLL[1]: PLL_DRP[98] bit 5 PLL[1]: CONTROL_4 bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 2 PLL[1]: CONTROL_4 bit 2 PLL[1]: PLL_DRP[98] bit 3 PLL[1]: CONTROL_4 bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[98] bit 0 PLL[1]: CONTROL_4 bit 0 PLL[1]: PLL_DRP[98] bit 1 PLL[1]: CONTROL_4 bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 14 PLL[1]: CONTROL_3 bit 14 PLL[1]: PLL_DRP[97] bit 15 PLL[1]: CONTROL_3 bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 12 PLL[1]: CONTROL_3 bit 12 PLL[1]: PLL_DRP[97] bit 13 PLL[1]: CONTROL_3 bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 10 PLL[1]: CONTROL_3 bit 10 PLL[1]: PLL_DRP[97] bit 11 PLL[1]: CONTROL_3 bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 8 PLL[1]: CONTROL_3 bit 8 PLL[1]: PLL_DRP[97] bit 9 PLL[1]: CONTROL_3 bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 6 PLL[1]: CONTROL_3 bit 6 PLL[1]: PLL_DRP[97] bit 7 PLL[1]: CONTROL_3 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 4 PLL[1]: CONTROL_3 bit 4 PLL[1]: PLL_DRP[97] bit 5 PLL[1]: CONTROL_3 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 2 PLL[1]: CONTROL_3 bit 2 PLL[1]: PLL_DRP[97] bit 3 PLL[1]: CONTROL_3 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[97] bit 0 PLL[1]: CONTROL_3 bit 0 PLL[1]: PLL_DRP[97] bit 1 PLL[1]: CONTROL_3 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 14 PLL[1]: CONTROL_2 bit 14 PLL[1]: PLL_DRP[96] bit 15 PLL[1]: CONTROL_2 bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 12 PLL[1]: CONTROL_2 bit 12 PLL[1]: PLL_DRP[96] bit 13 PLL[1]: CONTROL_2 bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 10 PLL[1]: CONTROL_2 bit 10 PLL[1]: PLL_DRP[96] bit 11 PLL[1]: CONTROL_2 bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 8 PLL[1]: CONTROL_2 bit 8 PLL[1]: PLL_DRP[96] bit 9 PLL[1]: CONTROL_2 bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 6 PLL[1]: CONTROL_2 bit 6 PLL[1]: PLL_DRP[96] bit 7 PLL[1]: CONTROL_2 bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 4 PLL[1]: CONTROL_2 bit 4 PLL[1]: PLL_DRP[96] bit 5 PLL[1]: CONTROL_2 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 2 PLL[1]: CONTROL_2 bit 2 PLL[1]: PLL_DRP[96] bit 3 PLL[1]: CONTROL_2 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: PLL_DRP[96] bit 0 PLL[1]: CONTROL_2 bit 0 PLL[1]: PLL_DRP[96] bit 1 PLL[1]: CONTROL_2 bit 1
virtex7 CMT rect HCLK
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 3 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 4 BUFMRCE[0]: CE_TYPE bit 0 BUFMRCE[1]: CE_TYPE bit 0
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 4 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 8 - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 8 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 3 BUFMRCE[0]: INIT_OUT bit 0 BUFMRCE[1]: INIT_OUT bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 2 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[0] bit 9 BUFMRCE[0]: !invert CE BUFMRCE[1]: !invert CE
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 2 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 9 BUFMRCE[0]: ENABLE BUFMRCE[1]: ENABLE
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 0 SPEC_INT: mux CELL[25].IMUX_BUFMRCE[1] bit 1 SPEC_INT: buffer CELL[25].HCLK_CMT[10] ← CELL[25].HCLK_ROW[10] SPEC_INT: buffer CELL[25].HCLK_CMT[11] ← CELL[25].HCLK_ROW[11]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].HCLK_CMT[1] ← CELL[25].HCLK_ROW[1] SPEC_INT: buffer CELL[25].HCLK_CMT[0] ← CELL[25].HCLK_ROW[0] SPEC_INT: buffer CELL[25].HROW_I_CMT[12] ← CELL[25].HROW_I[12] SPEC_INT: buffer CELL[25].HROW_I_CMT[13] ← CELL[25].HROW_I[13]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].HCLK_CMT[3] ← CELL[25].HCLK_ROW[3] SPEC_INT: buffer CELL[25].HCLK_CMT[2] ← CELL[25].HCLK_ROW[2] SPEC_INT: buffer CELL[25].HROW_I_CMT[10] ← CELL[25].HROW_I[10] SPEC_INT: buffer CELL[25].HROW_I_CMT[11] ← CELL[25].HROW_I[11]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].HCLK_CMT[5] ← CELL[25].HCLK_ROW[5] SPEC_INT: buffer CELL[25].HCLK_CMT[4] ← CELL[25].HCLK_ROW[4] SPEC_INT: buffer CELL[25].HROW_I_CMT[8] ← CELL[25].HROW_I[8] SPEC_INT: buffer CELL[25].HROW_I_CMT[9] ← CELL[25].HROW_I[9]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].HCLK_CMT[7] ← CELL[25].HCLK_ROW[7] SPEC_INT: buffer CELL[25].HCLK_CMT[6] ← CELL[25].HCLK_ROW[6] SPEC_INT: buffer CELL[25].HROW_I_CMT[6] ← CELL[25].HROW_I[6] SPEC_INT: buffer CELL[25].HROW_I_CMT[7] ← CELL[25].HROW_I[7]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].HCLK_CMT[9] ← CELL[25].HCLK_ROW[9] SPEC_INT: buffer CELL[25].HCLK_CMT[8] ← CELL[25].HCLK_ROW[8] SPEC_INT: buffer CELL[25].HROW_I_CMT[4] ← CELL[25].HROW_I[4] SPEC_INT: buffer CELL[25].HROW_I_CMT[5] ← CELL[25].HROW_I[5]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IO[25].PERF[0] bit 3 SPEC_INT: mux IO[25].PERF[1] bit 3 SPEC_INT: mux IO[25].PERF[2] bit 3 SPEC_INT: mux IO[25].PERF[3] bit 3
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IO[25].PERF[1] bit 4 SPEC_INT: mux IO[25].PERF[0] bit 4 SPEC_INT: mux IO[25].PERF[3] bit 4 SPEC_INT: mux IO[25].PERF[2] bit 4
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IO[25].PERF[0] bit 2 SPEC_INT: mux IO[25].PERF[1] bit 2 SPEC_INT: mux IO[25].PERF[2] bit 2 SPEC_INT: mux IO[25].PERF[3] bit 2
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IO[25].PERF[0] bit 1 SPEC_INT: mux IO[25].PERF[1] bit 1 SPEC_INT: mux IO[25].PERF[2] bit 1 SPEC_INT: mux IO[25].PERF[3] bit 1
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IO[25].PERF[0] bit 0 SPEC_INT: mux IO[25].PERF[1] bit 0 SPEC_INT: mux IO[25].PERF[2] bit 0 SPEC_INT: mux IO[25].PERF[3] bit 0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CKINT_CMT[2] ← CELL[25].IMUX_CLK[0] SPEC_INT: buffer CELL[25].CKINT_CMT[3] ← CELL[25].IMUX_CLK[1] SPEC_INT: buffer CELL[25].RCLK_CMT[2] ← CELL[25].RCLK_ROW[2] SPEC_INT: buffer CELL[25].RCLK_CMT[3] ← CELL[25].RCLK_ROW[3]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[25].CKINT_CMT[0] ← CELL[24].IMUX_CLK[0] SPEC_INT: buffer CELL[25].CKINT_CMT[1] ← CELL[24].IMUX_CLK[1] SPEC_INT: buffer CELL[25].RCLK_CMT[0] ← CELL[25].RCLK_ROW[0] SPEC_INT: buffer CELL[25].RCLK_CMT[1] ← CELL[25].RCLK_ROW[1]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CMT_FIFO

Cells: 12

Switchbox CMT_FIFO_INT

virtex7 CMT_FIFO switchbox CMT_FIFO_INT muxes FIFO_ORDCLK
BitsDestination
MAIN[6][26][34]CELL[6].FIFO_ORDCLK
Source
0CELL[7].IMUX_CLK[0]
1CELL[6].PHASER_OCLKDIV
virtex7 CMT_FIFO switchbox CMT_FIFO_INT muxes FIFO_ORDEN
BitsDestination
MAIN[6][27][29]CELL[6].FIFO_ORDEN
Source
0CELL[7].IMUX_IMUX[6]
1CELL[6].PHASER_ORDEN
virtex7 CMT_FIFO switchbox CMT_FIFO_INT muxes FIFO_IWRCLK
BitsDestination
MAIN[7][26][34]CELL[6].FIFO_IWRCLK
Source
0CELL[6].IMUX_CLK[1]
1CELL[6].PHASER_ICLKDIV
virtex7 CMT_FIFO switchbox CMT_FIFO_INT muxes FIFO_IWREN
BitsDestination
MAIN[7][27][29]CELL[6].FIFO_IWREN
Source
0CELL[6].IMUX_IMUX[7]
1CELL[6].PHASER_IWREN

Bels IN_FIFO

virtex7 CMT_FIFO bel IN_FIFO pins
PinDirectionIN_FIFO
RDCLKinCELL[7].IMUX_CLK[1]
RDENinCELL[7].IMUX_IMUX[7]
WRCLKinCELL[6].FIFO_IWRCLK
WRENinCELL[6].FIFO_IWREN
RESETinCELL[7].IMUX_IMUX[5]
D0[0]inCELL[0].IMUX_IMUX[26]
D0[1]inCELL[0].IMUX_IMUX[40]
D0[2]inCELL[0].IMUX_IMUX[36]
D0[3]inCELL[0].IMUX_IMUX[42]
D1[0]inCELL[1].IMUX_IMUX[26]
D1[1]inCELL[1].IMUX_IMUX[40]
D1[2]inCELL[1].IMUX_IMUX[36]
D1[3]inCELL[1].IMUX_IMUX[42]
D2[0]inCELL[2].IMUX_IMUX[26]
D2[1]inCELL[2].IMUX_IMUX[40]
D2[2]inCELL[2].IMUX_IMUX[36]
D2[3]inCELL[2].IMUX_IMUX[42]
D3[0]inCELL[3].IMUX_IMUX[26]
D3[1]inCELL[3].IMUX_IMUX[40]
D3[2]inCELL[3].IMUX_IMUX[36]
D3[3]inCELL[3].IMUX_IMUX[42]
D4[0]inCELL[4].IMUX_IMUX[26]
D4[1]inCELL[4].IMUX_IMUX[40]
D4[2]inCELL[4].IMUX_IMUX[36]
D4[3]inCELL[4].IMUX_IMUX[42]
D5[0]inCELL[5].IMUX_IMUX[26]
D5[1]inCELL[5].IMUX_IMUX[40]
D5[2]inCELL[5].IMUX_IMUX[36]
D5[3]inCELL[5].IMUX_IMUX[42]
D5[4]inCELL[6].IMUX_IMUX[26]
D5[5]inCELL[6].IMUX_IMUX[40]
D5[6]inCELL[6].IMUX_IMUX[36]
D5[7]inCELL[6].IMUX_IMUX[42]
D6[0]inCELL[8].IMUX_IMUX[26]
D6[1]inCELL[8].IMUX_IMUX[40]
D6[2]inCELL[8].IMUX_IMUX[36]
D6[3]inCELL[8].IMUX_IMUX[42]
D6[4]inCELL[7].IMUX_IMUX[26]
D6[5]inCELL[7].IMUX_IMUX[40]
D6[6]inCELL[7].IMUX_IMUX[36]
D6[7]inCELL[7].IMUX_IMUX[42]
D7[0]inCELL[9].IMUX_IMUX[26]
D7[1]inCELL[9].IMUX_IMUX[40]
D7[2]inCELL[9].IMUX_IMUX[36]
D7[3]inCELL[9].IMUX_IMUX[42]
D8[0]inCELL[10].IMUX_IMUX[26]
D8[1]inCELL[10].IMUX_IMUX[40]
D8[2]inCELL[10].IMUX_IMUX[36]
D8[3]inCELL[10].IMUX_IMUX[42]
D9[0]inCELL[11].IMUX_IMUX[26]
D9[1]inCELL[11].IMUX_IMUX[40]
D9[2]inCELL[11].IMUX_IMUX[36]
D9[3]inCELL[11].IMUX_IMUX[42]
TESTMODEBinCELL[7].IMUX_IMUX[4]
TESTREADDISBinCELL[7].IMUX_IMUX[13]
TESTWRITEDISBinCELL[7].IMUX_IMUX[47]
SCANENBinCELL[7].IMUX_IMUX[3]
SCANIN[0]inCELL[7].IMUX_IMUX[35]
SCANIN[1]inCELL[7].IMUX_IMUX[25]
SCANIN[2]inCELL[7].IMUX_IMUX[1]
SCANIN[3]inCELL[7].IMUX_IMUX[24]
EMPTYoutCELL[7].OUT_BEL[10]
FULLoutCELL[7].OUT_BEL[2]
ALMOSTEMPTYoutCELL[7].OUT_BEL[3]
ALMOSTFULLoutCELL[7].OUT_BEL[7]
Q0[0]outCELL[0].OUT_BEL[0]
Q0[1]outCELL[0].OUT_BEL[4]
Q0[2]outCELL[0].OUT_BEL[5]
Q0[3]outCELL[0].OUT_BEL[1]
Q0[4]outCELL[0].OUT_BEL[12]
Q0[5]outCELL[0].OUT_BEL[8]
Q0[6]outCELL[0].OUT_BEL[9]
Q0[7]outCELL[0].OUT_BEL[13]
Q1[0]outCELL[1].OUT_BEL[0]
Q1[1]outCELL[1].OUT_BEL[4]
Q1[2]outCELL[1].OUT_BEL[5]
Q1[3]outCELL[1].OUT_BEL[1]
Q1[4]outCELL[1].OUT_BEL[12]
Q1[5]outCELL[1].OUT_BEL[8]
Q1[6]outCELL[1].OUT_BEL[9]
Q1[7]outCELL[1].OUT_BEL[13]
Q2[0]outCELL[2].OUT_BEL[0]
Q2[1]outCELL[2].OUT_BEL[4]
Q2[2]outCELL[2].OUT_BEL[5]
Q2[3]outCELL[2].OUT_BEL[1]
Q2[4]outCELL[2].OUT_BEL[12]
Q2[5]outCELL[2].OUT_BEL[8]
Q2[6]outCELL[2].OUT_BEL[9]
Q2[7]outCELL[2].OUT_BEL[13]
Q3[0]outCELL[3].OUT_BEL[0]
Q3[1]outCELL[3].OUT_BEL[4]
Q3[2]outCELL[3].OUT_BEL[5]
Q3[3]outCELL[3].OUT_BEL[1]
Q3[4]outCELL[3].OUT_BEL[12]
Q3[5]outCELL[3].OUT_BEL[8]
Q3[6]outCELL[3].OUT_BEL[9]
Q3[7]outCELL[3].OUT_BEL[13]
Q4[0]outCELL[4].OUT_BEL[0]
Q4[1]outCELL[4].OUT_BEL[4]
Q4[2]outCELL[4].OUT_BEL[5]
Q4[3]outCELL[4].OUT_BEL[1]
Q4[4]outCELL[4].OUT_BEL[12]
Q4[5]outCELL[4].OUT_BEL[8]
Q4[6]outCELL[4].OUT_BEL[9]
Q4[7]outCELL[4].OUT_BEL[13]
Q5[0]outCELL[5].OUT_BEL[0]
Q5[1]outCELL[5].OUT_BEL[4]
Q5[2]outCELL[5].OUT_BEL[5]
Q5[3]outCELL[5].OUT_BEL[1]
Q5[4]outCELL[5].OUT_BEL[12]
Q5[5]outCELL[5].OUT_BEL[8]
Q5[6]outCELL[5].OUT_BEL[9]
Q5[7]outCELL[5].OUT_BEL[13]
Q6[0]outCELL[8].OUT_BEL[0]
Q6[1]outCELL[8].OUT_BEL[4]
Q6[2]outCELL[8].OUT_BEL[5]
Q6[3]outCELL[8].OUT_BEL[1]
Q6[4]outCELL[8].OUT_BEL[12]
Q6[5]outCELL[8].OUT_BEL[8]
Q6[6]outCELL[8].OUT_BEL[9]
Q6[7]outCELL[8].OUT_BEL[13]
Q7[0]outCELL[9].OUT_BEL[0]
Q7[1]outCELL[9].OUT_BEL[4]
Q7[2]outCELL[9].OUT_BEL[5]
Q7[3]outCELL[9].OUT_BEL[1]
Q7[4]outCELL[9].OUT_BEL[12]
Q7[5]outCELL[9].OUT_BEL[8]
Q7[6]outCELL[9].OUT_BEL[9]
Q7[7]outCELL[9].OUT_BEL[13]
Q8[0]outCELL[10].OUT_BEL[0]
Q8[1]outCELL[10].OUT_BEL[4]
Q8[2]outCELL[10].OUT_BEL[5]
Q8[3]outCELL[10].OUT_BEL[1]
Q8[4]outCELL[10].OUT_BEL[12]
Q8[5]outCELL[10].OUT_BEL[8]
Q8[6]outCELL[10].OUT_BEL[9]
Q8[7]outCELL[10].OUT_BEL[13]
Q9[0]outCELL[11].OUT_BEL[0]
Q9[1]outCELL[11].OUT_BEL[4]
Q9[2]outCELL[11].OUT_BEL[5]
Q9[3]outCELL[11].OUT_BEL[1]
Q9[4]outCELL[11].OUT_BEL[12]
Q9[5]outCELL[11].OUT_BEL[8]
Q9[6]outCELL[11].OUT_BEL[9]
Q9[7]outCELL[11].OUT_BEL[13]
SCANOUT[0]outCELL[7].OUT_BEL[21]
SCANOUT[1]outCELL[7].OUT_BEL[13]
SCANOUT[2]outCELL[7].OUT_BEL[12]
SCANOUT[3]outCELL[7].OUT_BEL[8]
virtex7 CMT_FIFO bel IN_FIFO attribute bits
AttributeIN_FIFO
ALMOST_EMPTY_VALUE[enum: IO_FIFO_WATERMARK]
ALMOST_FULL_VALUE[enum: IO_FIFO_WATERMARK]
ARRAY_MODE[enum: IN_FIFO_ARRAY_MODE]
SLOW_RD_CLKMAIN[7][27][3]
SLOW_WR_CLKMAIN[7][27][2]
SYNCHRONOUS_MODEMAIN[7][26][3]
SPARE bit 0MAIN[7][26][1]
SPARE bit 1MAIN[7][27][1]
SPARE bit 2MAIN[7][26][2]
SPARE bit 3MAIN[7][27][4]
virtex7 CMT_FIFO enum IO_FIFO_WATERMARK
IN_FIFO.ALMOST_EMPTY_VALUEMAIN[7][27][60]MAIN[7][27][58]MAIN[7][26][61]MAIN[7][26][58]
IN_FIFO.ALMOST_FULL_VALUEMAIN[7][27][32]MAIN[7][27][30]MAIN[7][26][33]MAIN[7][26][30]
NONE0000
_10011
_21111
virtex7 CMT_FIFO enum IN_FIFO_ARRAY_MODE
IN_FIFO.ARRAY_MODEMAIN[7][26][4]
ARRAY_MODE_4_X_40
ARRAY_MODE_4_X_81

Bels OUT_FIFO

virtex7 CMT_FIFO bel OUT_FIFO pins
PinDirectionOUT_FIFO
RDCLKinCELL[6].FIFO_ORDCLK
RDENinCELL[6].FIFO_ORDEN
WRCLKinCELL[6].IMUX_CLK[0]
WRENinCELL[6].IMUX_IMUX[6]
RESETinCELL[6].IMUX_IMUX[5]
D0[0]inCELL[0].IMUX_IMUX[28]
D0[1]inCELL[0].IMUX_IMUX[21]
D0[2]inCELL[0].IMUX_IMUX[39]
D0[3]inCELL[0].IMUX_IMUX[38]
D0[4]inCELL[0].IMUX_IMUX[12]
D0[5]inCELL[0].IMUX_IMUX[5]
D0[6]inCELL[0].IMUX_IMUX[7]
D0[7]inCELL[0].IMUX_IMUX[6]
D1[0]inCELL[1].IMUX_IMUX[28]
D1[1]inCELL[1].IMUX_IMUX[21]
D1[2]inCELL[1].IMUX_IMUX[39]
D1[3]inCELL[1].IMUX_IMUX[38]
D1[4]inCELL[1].IMUX_IMUX[12]
D1[5]inCELL[1].IMUX_IMUX[5]
D1[6]inCELL[1].IMUX_IMUX[7]
D1[7]inCELL[1].IMUX_IMUX[6]
D2[0]inCELL[2].IMUX_IMUX[28]
D2[1]inCELL[2].IMUX_IMUX[21]
D2[2]inCELL[2].IMUX_IMUX[39]
D2[3]inCELL[2].IMUX_IMUX[38]
D2[4]inCELL[2].IMUX_IMUX[12]
D2[5]inCELL[2].IMUX_IMUX[5]
D2[6]inCELL[2].IMUX_IMUX[7]
D2[7]inCELL[2].IMUX_IMUX[6]
D3[0]inCELL[3].IMUX_IMUX[28]
D3[1]inCELL[3].IMUX_IMUX[21]
D3[2]inCELL[3].IMUX_IMUX[39]
D3[3]inCELL[3].IMUX_IMUX[38]
D3[4]inCELL[3].IMUX_IMUX[12]
D3[5]inCELL[3].IMUX_IMUX[5]
D3[6]inCELL[3].IMUX_IMUX[7]
D3[7]inCELL[3].IMUX_IMUX[6]
D4[0]inCELL[4].IMUX_IMUX[28]
D4[1]inCELL[4].IMUX_IMUX[21]
D4[2]inCELL[4].IMUX_IMUX[39]
D4[3]inCELL[4].IMUX_IMUX[38]
D4[4]inCELL[4].IMUX_IMUX[12]
D4[5]inCELL[4].IMUX_IMUX[5]
D4[6]inCELL[4].IMUX_IMUX[7]
D4[7]inCELL[4].IMUX_IMUX[6]
D5[0]inCELL[5].IMUX_IMUX[28]
D5[1]inCELL[5].IMUX_IMUX[21]
D5[2]inCELL[5].IMUX_IMUX[39]
D5[3]inCELL[5].IMUX_IMUX[38]
D5[4]inCELL[5].IMUX_IMUX[12]
D5[5]inCELL[5].IMUX_IMUX[5]
D5[6]inCELL[5].IMUX_IMUX[7]
D5[7]inCELL[5].IMUX_IMUX[6]
D6[0]inCELL[8].IMUX_IMUX[28]
D6[1]inCELL[8].IMUX_IMUX[21]
D6[2]inCELL[8].IMUX_IMUX[39]
D6[3]inCELL[8].IMUX_IMUX[38]
D6[4]inCELL[8].IMUX_IMUX[12]
D6[5]inCELL[8].IMUX_IMUX[5]
D6[6]inCELL[8].IMUX_IMUX[7]
D6[7]inCELL[8].IMUX_IMUX[6]
D7[0]inCELL[9].IMUX_IMUX[28]
D7[1]inCELL[9].IMUX_IMUX[21]
D7[2]inCELL[9].IMUX_IMUX[39]
D7[3]inCELL[9].IMUX_IMUX[38]
D7[4]inCELL[9].IMUX_IMUX[12]
D7[5]inCELL[9].IMUX_IMUX[5]
D7[6]inCELL[9].IMUX_IMUX[7]
D7[7]inCELL[9].IMUX_IMUX[6]
D8[0]inCELL[10].IMUX_IMUX[28]
D8[1]inCELL[10].IMUX_IMUX[21]
D8[2]inCELL[10].IMUX_IMUX[39]
D8[3]inCELL[10].IMUX_IMUX[38]
D8[4]inCELL[10].IMUX_IMUX[12]
D8[5]inCELL[10].IMUX_IMUX[5]
D8[6]inCELL[10].IMUX_IMUX[7]
D8[7]inCELL[10].IMUX_IMUX[6]
D9[0]inCELL[11].IMUX_IMUX[28]
D9[1]inCELL[11].IMUX_IMUX[21]
D9[2]inCELL[11].IMUX_IMUX[39]
D9[3]inCELL[11].IMUX_IMUX[38]
D9[4]inCELL[11].IMUX_IMUX[12]
D9[5]inCELL[11].IMUX_IMUX[5]
D9[6]inCELL[11].IMUX_IMUX[7]
D9[7]inCELL[11].IMUX_IMUX[6]
TESTMODEBinCELL[6].IMUX_IMUX[4]
TESTREADDISBinCELL[6].IMUX_IMUX[13]
TESTWRITEDISBinCELL[6].IMUX_IMUX[47]
SCANENBinCELL[6].IMUX_IMUX[3]
SCANIN[0]inCELL[6].IMUX_IMUX[35]
SCANIN[1]inCELL[6].IMUX_IMUX[25]
SCANIN[2]inCELL[6].IMUX_IMUX[1]
SCANIN[3]inCELL[6].IMUX_IMUX[24]
EMPTYoutCELL[6].OUT_BEL[10]
FULLoutCELL[6].OUT_BEL[2]
ALMOSTEMPTYoutCELL[6].OUT_BEL[3]
ALMOSTFULLoutCELL[6].OUT_BEL[7]
Q0[0]outCELL[0].OUT_BEL[22]
Q0[1]outCELL[0].OUT_BEL[19]
Q0[2]outCELL[0].OUT_BEL[11]
Q0[3]outCELL[0].OUT_BEL[20]
Q1[0]outCELL[1].OUT_BEL[22]
Q1[1]outCELL[1].OUT_BEL[19]
Q1[2]outCELL[1].OUT_BEL[11]
Q1[3]outCELL[1].OUT_BEL[20]
Q2[0]outCELL[2].OUT_BEL[22]
Q2[1]outCELL[2].OUT_BEL[19]
Q2[2]outCELL[2].OUT_BEL[11]
Q2[3]outCELL[2].OUT_BEL[20]
Q3[0]outCELL[3].OUT_BEL[22]
Q3[1]outCELL[3].OUT_BEL[19]
Q3[2]outCELL[3].OUT_BEL[11]
Q3[3]outCELL[3].OUT_BEL[20]
Q4[0]outCELL[4].OUT_BEL[22]
Q4[1]outCELL[4].OUT_BEL[19]
Q4[2]outCELL[4].OUT_BEL[11]
Q4[3]outCELL[4].OUT_BEL[20]
Q5[0]outCELL[5].OUT_BEL[22]
Q5[1]outCELL[5].OUT_BEL[19]
Q5[2]outCELL[5].OUT_BEL[11]
Q5[3]outCELL[5].OUT_BEL[20]
Q5[4]outCELL[6].OUT_BEL[22]
Q5[5]outCELL[6].OUT_BEL[19]
Q5[6]outCELL[6].OUT_BEL[11]
Q5[7]outCELL[6].OUT_BEL[20]
Q6[0]outCELL[8].OUT_BEL[22]
Q6[1]outCELL[8].OUT_BEL[19]
Q6[2]outCELL[8].OUT_BEL[11]
Q6[3]outCELL[8].OUT_BEL[20]
Q6[4]outCELL[7].OUT_BEL[22]
Q6[5]outCELL[7].OUT_BEL[19]
Q6[6]outCELL[7].OUT_BEL[11]
Q6[7]outCELL[7].OUT_BEL[20]
Q7[0]outCELL[9].OUT_BEL[22]
Q7[1]outCELL[9].OUT_BEL[19]
Q7[2]outCELL[9].OUT_BEL[11]
Q7[3]outCELL[9].OUT_BEL[20]
Q8[0]outCELL[10].OUT_BEL[22]
Q8[1]outCELL[10].OUT_BEL[19]
Q8[2]outCELL[10].OUT_BEL[11]
Q8[3]outCELL[10].OUT_BEL[20]
Q9[0]outCELL[11].OUT_BEL[22]
Q9[1]outCELL[11].OUT_BEL[19]
Q9[2]outCELL[11].OUT_BEL[11]
Q9[3]outCELL[11].OUT_BEL[20]
SCANOUT[0]outCELL[6].OUT_BEL[5]
SCANOUT[1]outCELL[6].OUT_BEL[13]
SCANOUT[2]outCELL[6].OUT_BEL[12]
SCANOUT[3]outCELL[6].OUT_BEL[8]
virtex7 CMT_FIFO bel OUT_FIFO attribute bits
AttributeOUT_FIFO
ALMOST_EMPTY_VALUE[enum: IO_FIFO_WATERMARK]
ALMOST_FULL_VALUE[enum: IO_FIFO_WATERMARK]
ARRAY_MODE[enum: OUT_FIFO_ARRAY_MODE]
OUTPUT_DISABLEMAIN[6][26][1]
SLOW_RD_CLKMAIN[6][26][4]
SLOW_WR_CLKMAIN[6][26][3]
SYNCHRONOUS_MODEMAIN[6][27][3]
SPARE bit 0MAIN[6][27][1]
SPARE bit 1MAIN[6][26][2]
SPARE bit 2MAIN[6][27][2]
SPARE bit 3MAIN[6][26][5]
virtex7 CMT_FIFO enum IO_FIFO_WATERMARK
OUT_FIFO.ALMOST_EMPTY_VALUEMAIN[6][27][60]MAIN[6][27][58]MAIN[6][26][61]MAIN[6][26][58]
OUT_FIFO.ALMOST_FULL_VALUEMAIN[6][27][32]MAIN[6][27][30]MAIN[6][26][33]MAIN[6][26][30]
NONE0000
_10011
_21111
virtex7 CMT_FIFO enum OUT_FIFO_ARRAY_MODE
OUT_FIFO.ARRAY_MODEMAIN[6][27][4]
ARRAY_MODE_4_X_40
ARRAY_MODE_8_X_41

Bel wires

virtex7 CMT_FIFO bel wires
WirePins
CELL[0].IMUX_IMUX[5]OUT_FIFO.D0[5]
CELL[0].IMUX_IMUX[6]OUT_FIFO.D0[7]
CELL[0].IMUX_IMUX[7]OUT_FIFO.D0[6]
CELL[0].IMUX_IMUX[12]OUT_FIFO.D0[4]
CELL[0].IMUX_IMUX[21]OUT_FIFO.D0[1]
CELL[0].IMUX_IMUX[26]IN_FIFO.D0[0]
CELL[0].IMUX_IMUX[28]OUT_FIFO.D0[0]
CELL[0].IMUX_IMUX[36]IN_FIFO.D0[2]
CELL[0].IMUX_IMUX[38]OUT_FIFO.D0[3]
CELL[0].IMUX_IMUX[39]OUT_FIFO.D0[2]
CELL[0].IMUX_IMUX[40]IN_FIFO.D0[1]
CELL[0].IMUX_IMUX[42]IN_FIFO.D0[3]
CELL[0].OUT_BEL[0]IN_FIFO.Q0[0]
CELL[0].OUT_BEL[1]IN_FIFO.Q0[3]
CELL[0].OUT_BEL[4]IN_FIFO.Q0[1]
CELL[0].OUT_BEL[5]IN_FIFO.Q0[2]
CELL[0].OUT_BEL[8]IN_FIFO.Q0[5]
CELL[0].OUT_BEL[9]IN_FIFO.Q0[6]
CELL[0].OUT_BEL[11]OUT_FIFO.Q0[2]
CELL[0].OUT_BEL[12]IN_FIFO.Q0[4]
CELL[0].OUT_BEL[13]IN_FIFO.Q0[7]
CELL[0].OUT_BEL[19]OUT_FIFO.Q0[1]
CELL[0].OUT_BEL[20]OUT_FIFO.Q0[3]
CELL[0].OUT_BEL[22]OUT_FIFO.Q0[0]
CELL[1].IMUX_IMUX[5]OUT_FIFO.D1[5]
CELL[1].IMUX_IMUX[6]OUT_FIFO.D1[7]
CELL[1].IMUX_IMUX[7]OUT_FIFO.D1[6]
CELL[1].IMUX_IMUX[12]OUT_FIFO.D1[4]
CELL[1].IMUX_IMUX[21]OUT_FIFO.D1[1]
CELL[1].IMUX_IMUX[26]IN_FIFO.D1[0]
CELL[1].IMUX_IMUX[28]OUT_FIFO.D1[0]
CELL[1].IMUX_IMUX[36]IN_FIFO.D1[2]
CELL[1].IMUX_IMUX[38]OUT_FIFO.D1[3]
CELL[1].IMUX_IMUX[39]OUT_FIFO.D1[2]
CELL[1].IMUX_IMUX[40]IN_FIFO.D1[1]
CELL[1].IMUX_IMUX[42]IN_FIFO.D1[3]
CELL[1].OUT_BEL[0]IN_FIFO.Q1[0]
CELL[1].OUT_BEL[1]IN_FIFO.Q1[3]
CELL[1].OUT_BEL[4]IN_FIFO.Q1[1]
CELL[1].OUT_BEL[5]IN_FIFO.Q1[2]
CELL[1].OUT_BEL[8]IN_FIFO.Q1[5]
CELL[1].OUT_BEL[9]IN_FIFO.Q1[6]
CELL[1].OUT_BEL[11]OUT_FIFO.Q1[2]
CELL[1].OUT_BEL[12]IN_FIFO.Q1[4]
CELL[1].OUT_BEL[13]IN_FIFO.Q1[7]
CELL[1].OUT_BEL[19]OUT_FIFO.Q1[1]
CELL[1].OUT_BEL[20]OUT_FIFO.Q1[3]
CELL[1].OUT_BEL[22]OUT_FIFO.Q1[0]
CELL[2].IMUX_IMUX[5]OUT_FIFO.D2[5]
CELL[2].IMUX_IMUX[6]OUT_FIFO.D2[7]
CELL[2].IMUX_IMUX[7]OUT_FIFO.D2[6]
CELL[2].IMUX_IMUX[12]OUT_FIFO.D2[4]
CELL[2].IMUX_IMUX[21]OUT_FIFO.D2[1]
CELL[2].IMUX_IMUX[26]IN_FIFO.D2[0]
CELL[2].IMUX_IMUX[28]OUT_FIFO.D2[0]
CELL[2].IMUX_IMUX[36]IN_FIFO.D2[2]
CELL[2].IMUX_IMUX[38]OUT_FIFO.D2[3]
CELL[2].IMUX_IMUX[39]OUT_FIFO.D2[2]
CELL[2].IMUX_IMUX[40]IN_FIFO.D2[1]
CELL[2].IMUX_IMUX[42]IN_FIFO.D2[3]
CELL[2].OUT_BEL[0]IN_FIFO.Q2[0]
CELL[2].OUT_BEL[1]IN_FIFO.Q2[3]
CELL[2].OUT_BEL[4]IN_FIFO.Q2[1]
CELL[2].OUT_BEL[5]IN_FIFO.Q2[2]
CELL[2].OUT_BEL[8]IN_FIFO.Q2[5]
CELL[2].OUT_BEL[9]IN_FIFO.Q2[6]
CELL[2].OUT_BEL[11]OUT_FIFO.Q2[2]
CELL[2].OUT_BEL[12]IN_FIFO.Q2[4]
CELL[2].OUT_BEL[13]IN_FIFO.Q2[7]
CELL[2].OUT_BEL[19]OUT_FIFO.Q2[1]
CELL[2].OUT_BEL[20]OUT_FIFO.Q2[3]
CELL[2].OUT_BEL[22]OUT_FIFO.Q2[0]
CELL[3].IMUX_IMUX[5]OUT_FIFO.D3[5]
CELL[3].IMUX_IMUX[6]OUT_FIFO.D3[7]
CELL[3].IMUX_IMUX[7]OUT_FIFO.D3[6]
CELL[3].IMUX_IMUX[12]OUT_FIFO.D3[4]
CELL[3].IMUX_IMUX[21]OUT_FIFO.D3[1]
CELL[3].IMUX_IMUX[26]IN_FIFO.D3[0]
CELL[3].IMUX_IMUX[28]OUT_FIFO.D3[0]
CELL[3].IMUX_IMUX[36]IN_FIFO.D3[2]
CELL[3].IMUX_IMUX[38]OUT_FIFO.D3[3]
CELL[3].IMUX_IMUX[39]OUT_FIFO.D3[2]
CELL[3].IMUX_IMUX[40]IN_FIFO.D3[1]
CELL[3].IMUX_IMUX[42]IN_FIFO.D3[3]
CELL[3].OUT_BEL[0]IN_FIFO.Q3[0]
CELL[3].OUT_BEL[1]IN_FIFO.Q3[3]
CELL[3].OUT_BEL[4]IN_FIFO.Q3[1]
CELL[3].OUT_BEL[5]IN_FIFO.Q3[2]
CELL[3].OUT_BEL[8]IN_FIFO.Q3[5]
CELL[3].OUT_BEL[9]IN_FIFO.Q3[6]
CELL[3].OUT_BEL[11]OUT_FIFO.Q3[2]
CELL[3].OUT_BEL[12]IN_FIFO.Q3[4]
CELL[3].OUT_BEL[13]IN_FIFO.Q3[7]
CELL[3].OUT_BEL[19]OUT_FIFO.Q3[1]
CELL[3].OUT_BEL[20]OUT_FIFO.Q3[3]
CELL[3].OUT_BEL[22]OUT_FIFO.Q3[0]
CELL[4].IMUX_IMUX[5]OUT_FIFO.D4[5]
CELL[4].IMUX_IMUX[6]OUT_FIFO.D4[7]
CELL[4].IMUX_IMUX[7]OUT_FIFO.D4[6]
CELL[4].IMUX_IMUX[12]OUT_FIFO.D4[4]
CELL[4].IMUX_IMUX[21]OUT_FIFO.D4[1]
CELL[4].IMUX_IMUX[26]IN_FIFO.D4[0]
CELL[4].IMUX_IMUX[28]OUT_FIFO.D4[0]
CELL[4].IMUX_IMUX[36]IN_FIFO.D4[2]
CELL[4].IMUX_IMUX[38]OUT_FIFO.D4[3]
CELL[4].IMUX_IMUX[39]OUT_FIFO.D4[2]
CELL[4].IMUX_IMUX[40]IN_FIFO.D4[1]
CELL[4].IMUX_IMUX[42]IN_FIFO.D4[3]
CELL[4].OUT_BEL[0]IN_FIFO.Q4[0]
CELL[4].OUT_BEL[1]IN_FIFO.Q4[3]
CELL[4].OUT_BEL[4]IN_FIFO.Q4[1]
CELL[4].OUT_BEL[5]IN_FIFO.Q4[2]
CELL[4].OUT_BEL[8]IN_FIFO.Q4[5]
CELL[4].OUT_BEL[9]IN_FIFO.Q4[6]
CELL[4].OUT_BEL[11]OUT_FIFO.Q4[2]
CELL[4].OUT_BEL[12]IN_FIFO.Q4[4]
CELL[4].OUT_BEL[13]IN_FIFO.Q4[7]
CELL[4].OUT_BEL[19]OUT_FIFO.Q4[1]
CELL[4].OUT_BEL[20]OUT_FIFO.Q4[3]
CELL[4].OUT_BEL[22]OUT_FIFO.Q4[0]
CELL[5].IMUX_IMUX[5]OUT_FIFO.D5[5]
CELL[5].IMUX_IMUX[6]OUT_FIFO.D5[7]
CELL[5].IMUX_IMUX[7]OUT_FIFO.D5[6]
CELL[5].IMUX_IMUX[12]OUT_FIFO.D5[4]
CELL[5].IMUX_IMUX[21]OUT_FIFO.D5[1]
CELL[5].IMUX_IMUX[26]IN_FIFO.D5[0]
CELL[5].IMUX_IMUX[28]OUT_FIFO.D5[0]
CELL[5].IMUX_IMUX[36]IN_FIFO.D5[2]
CELL[5].IMUX_IMUX[38]OUT_FIFO.D5[3]
CELL[5].IMUX_IMUX[39]OUT_FIFO.D5[2]
CELL[5].IMUX_IMUX[40]IN_FIFO.D5[1]
CELL[5].IMUX_IMUX[42]IN_FIFO.D5[3]
CELL[5].OUT_BEL[0]IN_FIFO.Q5[0]
CELL[5].OUT_BEL[1]IN_FIFO.Q5[3]
CELL[5].OUT_BEL[4]IN_FIFO.Q5[1]
CELL[5].OUT_BEL[5]IN_FIFO.Q5[2]
CELL[5].OUT_BEL[8]IN_FIFO.Q5[5]
CELL[5].OUT_BEL[9]IN_FIFO.Q5[6]
CELL[5].OUT_BEL[11]OUT_FIFO.Q5[2]
CELL[5].OUT_BEL[12]IN_FIFO.Q5[4]
CELL[5].OUT_BEL[13]IN_FIFO.Q5[7]
CELL[5].OUT_BEL[19]OUT_FIFO.Q5[1]
CELL[5].OUT_BEL[20]OUT_FIFO.Q5[3]
CELL[5].OUT_BEL[22]OUT_FIFO.Q5[0]
CELL[6].IMUX_CLK[0]OUT_FIFO.WRCLK
CELL[6].IMUX_IMUX[1]OUT_FIFO.SCANIN[2]
CELL[6].IMUX_IMUX[3]OUT_FIFO.SCANENB
CELL[6].IMUX_IMUX[4]OUT_FIFO.TESTMODEB
CELL[6].IMUX_IMUX[5]OUT_FIFO.RESET
CELL[6].IMUX_IMUX[6]OUT_FIFO.WREN
CELL[6].IMUX_IMUX[13]OUT_FIFO.TESTREADDISB
CELL[6].IMUX_IMUX[24]OUT_FIFO.SCANIN[3]
CELL[6].IMUX_IMUX[25]OUT_FIFO.SCANIN[1]
CELL[6].IMUX_IMUX[26]IN_FIFO.D5[4]
CELL[6].IMUX_IMUX[35]OUT_FIFO.SCANIN[0]
CELL[6].IMUX_IMUX[36]IN_FIFO.D5[6]
CELL[6].IMUX_IMUX[40]IN_FIFO.D5[5]
CELL[6].IMUX_IMUX[42]IN_FIFO.D5[7]
CELL[6].IMUX_IMUX[47]OUT_FIFO.TESTWRITEDISB
CELL[6].OUT_BEL[2]OUT_FIFO.FULL
CELL[6].OUT_BEL[3]OUT_FIFO.ALMOSTEMPTY
CELL[6].OUT_BEL[5]OUT_FIFO.SCANOUT[0]
CELL[6].OUT_BEL[7]OUT_FIFO.ALMOSTFULL
CELL[6].OUT_BEL[8]OUT_FIFO.SCANOUT[3]
CELL[6].OUT_BEL[10]OUT_FIFO.EMPTY
CELL[6].OUT_BEL[11]OUT_FIFO.Q5[6]
CELL[6].OUT_BEL[12]OUT_FIFO.SCANOUT[2]
CELL[6].OUT_BEL[13]OUT_FIFO.SCANOUT[1]
CELL[6].OUT_BEL[19]OUT_FIFO.Q5[5]
CELL[6].OUT_BEL[20]OUT_FIFO.Q5[7]
CELL[6].OUT_BEL[22]OUT_FIFO.Q5[4]
CELL[6].FIFO_ORDCLKOUT_FIFO.RDCLK
CELL[6].FIFO_ORDENOUT_FIFO.RDEN
CELL[6].FIFO_IWRCLKIN_FIFO.WRCLK
CELL[6].FIFO_IWRENIN_FIFO.WREN
CELL[7].IMUX_CLK[1]IN_FIFO.RDCLK
CELL[7].IMUX_IMUX[1]IN_FIFO.SCANIN[2]
CELL[7].IMUX_IMUX[3]IN_FIFO.SCANENB
CELL[7].IMUX_IMUX[4]IN_FIFO.TESTMODEB
CELL[7].IMUX_IMUX[5]IN_FIFO.RESET
CELL[7].IMUX_IMUX[7]IN_FIFO.RDEN
CELL[7].IMUX_IMUX[13]IN_FIFO.TESTREADDISB
CELL[7].IMUX_IMUX[24]IN_FIFO.SCANIN[3]
CELL[7].IMUX_IMUX[25]IN_FIFO.SCANIN[1]
CELL[7].IMUX_IMUX[26]IN_FIFO.D6[4]
CELL[7].IMUX_IMUX[35]IN_FIFO.SCANIN[0]
CELL[7].IMUX_IMUX[36]IN_FIFO.D6[6]
CELL[7].IMUX_IMUX[40]IN_FIFO.D6[5]
CELL[7].IMUX_IMUX[42]IN_FIFO.D6[7]
CELL[7].IMUX_IMUX[47]IN_FIFO.TESTWRITEDISB
CELL[7].OUT_BEL[2]IN_FIFO.FULL
CELL[7].OUT_BEL[3]IN_FIFO.ALMOSTEMPTY
CELL[7].OUT_BEL[7]IN_FIFO.ALMOSTFULL
CELL[7].OUT_BEL[8]IN_FIFO.SCANOUT[3]
CELL[7].OUT_BEL[10]IN_FIFO.EMPTY
CELL[7].OUT_BEL[11]OUT_FIFO.Q6[6]
CELL[7].OUT_BEL[12]IN_FIFO.SCANOUT[2]
CELL[7].OUT_BEL[13]IN_FIFO.SCANOUT[1]
CELL[7].OUT_BEL[19]OUT_FIFO.Q6[5]
CELL[7].OUT_BEL[20]OUT_FIFO.Q6[7]
CELL[7].OUT_BEL[21]IN_FIFO.SCANOUT[0]
CELL[7].OUT_BEL[22]OUT_FIFO.Q6[4]
CELL[8].IMUX_IMUX[5]OUT_FIFO.D6[5]
CELL[8].IMUX_IMUX[6]OUT_FIFO.D6[7]
CELL[8].IMUX_IMUX[7]OUT_FIFO.D6[6]
CELL[8].IMUX_IMUX[12]OUT_FIFO.D6[4]
CELL[8].IMUX_IMUX[21]OUT_FIFO.D6[1]
CELL[8].IMUX_IMUX[26]IN_FIFO.D6[0]
CELL[8].IMUX_IMUX[28]OUT_FIFO.D6[0]
CELL[8].IMUX_IMUX[36]IN_FIFO.D6[2]
CELL[8].IMUX_IMUX[38]OUT_FIFO.D6[3]
CELL[8].IMUX_IMUX[39]OUT_FIFO.D6[2]
CELL[8].IMUX_IMUX[40]IN_FIFO.D6[1]
CELL[8].IMUX_IMUX[42]IN_FIFO.D6[3]
CELL[8].OUT_BEL[0]IN_FIFO.Q6[0]
CELL[8].OUT_BEL[1]IN_FIFO.Q6[3]
CELL[8].OUT_BEL[4]IN_FIFO.Q6[1]
CELL[8].OUT_BEL[5]IN_FIFO.Q6[2]
CELL[8].OUT_BEL[8]IN_FIFO.Q6[5]
CELL[8].OUT_BEL[9]IN_FIFO.Q6[6]
CELL[8].OUT_BEL[11]OUT_FIFO.Q6[2]
CELL[8].OUT_BEL[12]IN_FIFO.Q6[4]
CELL[8].OUT_BEL[13]IN_FIFO.Q6[7]
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CELL[9].IMUX_IMUX[5]OUT_FIFO.D7[5]
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CELL[9].IMUX_IMUX[36]IN_FIFO.D7[2]
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CELL[9].OUT_BEL[12]IN_FIFO.Q7[4]
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CELL[9].OUT_BEL[20]OUT_FIFO.Q7[3]
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CELL[10].IMUX_IMUX[5]OUT_FIFO.D8[5]
CELL[10].IMUX_IMUX[6]OUT_FIFO.D8[7]
CELL[10].IMUX_IMUX[7]OUT_FIFO.D8[6]
CELL[10].IMUX_IMUX[12]OUT_FIFO.D8[4]
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CELL[10].IMUX_IMUX[26]IN_FIFO.D8[0]
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CELL[10].IMUX_IMUX[36]IN_FIFO.D8[2]
CELL[10].IMUX_IMUX[38]OUT_FIFO.D8[3]
CELL[10].IMUX_IMUX[39]OUT_FIFO.D8[2]
CELL[10].IMUX_IMUX[40]IN_FIFO.D8[1]
CELL[10].IMUX_IMUX[42]IN_FIFO.D8[3]
CELL[10].OUT_BEL[0]IN_FIFO.Q8[0]
CELL[10].OUT_BEL[1]IN_FIFO.Q8[3]
CELL[10].OUT_BEL[4]IN_FIFO.Q8[1]
CELL[10].OUT_BEL[5]IN_FIFO.Q8[2]
CELL[10].OUT_BEL[8]IN_FIFO.Q8[5]
CELL[10].OUT_BEL[9]IN_FIFO.Q8[6]
CELL[10].OUT_BEL[11]OUT_FIFO.Q8[2]
CELL[10].OUT_BEL[12]IN_FIFO.Q8[4]
CELL[10].OUT_BEL[13]IN_FIFO.Q8[7]
CELL[10].OUT_BEL[19]OUT_FIFO.Q8[1]
CELL[10].OUT_BEL[20]OUT_FIFO.Q8[3]
CELL[10].OUT_BEL[22]OUT_FIFO.Q8[0]
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CELL[11].IMUX_IMUX[26]IN_FIFO.D9[0]
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CELL[11].OUT_BEL[9]IN_FIFO.Q9[6]
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CELL[11].OUT_BEL[13]IN_FIFO.Q9[7]
CELL[11].OUT_BEL[19]OUT_FIFO.Q9[1]
CELL[11].OUT_BEL[20]OUT_FIFO.Q9[3]
CELL[11].OUT_BEL[22]OUT_FIFO.Q9[0]

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virtex7 CMT_FIFO rect MAIN[0]
BitFrame
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT_FIFO rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT_FIFO rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_EMPTY_VALUE bit 1 - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_EMPTY_VALUE bit 3 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_EMPTY_VALUE bit 0 OUT_FIFO: ALMOST_EMPTY_VALUE bit 2 - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - CMT_FIFO_INT: mux CELL[6].FIFO_ORDCLK bit 0 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_FULL_VALUE bit 1 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_FULL_VALUE bit 3 - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: ALMOST_FULL_VALUE bit 0 OUT_FIFO: ALMOST_FULL_VALUE bit 2 - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - CMT_FIFO_INT: mux CELL[6].FIFO_ORDEN bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: SPARE bit 3 - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: SLOW_RD_CLK OUT_FIFO: ARRAY_MODE bit 0 - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: SLOW_WR_CLK OUT_FIFO: SYNCHRONOUS_MODE - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: SPARE bit 1 OUT_FIFO: SPARE bit 2 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - OUT_FIFO: OUTPUT_DISABLE OUT_FIFO: SPARE bit 0 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_EMPTY_VALUE bit 1 - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_EMPTY_VALUE bit 3 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_EMPTY_VALUE bit 0 IN_FIFO: ALMOST_EMPTY_VALUE bit 2 - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - CMT_FIFO_INT: mux CELL[6].FIFO_IWRCLK bit 0 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_FULL_VALUE bit 1 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_FULL_VALUE bit 3 - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ALMOST_FULL_VALUE bit 0 IN_FIFO: ALMOST_FULL_VALUE bit 2 - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - CMT_FIFO_INT: mux CELL[6].FIFO_IWREN bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: ARRAY_MODE bit 0 IN_FIFO: SPARE bit 3 - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: SYNCHRONOUS_MODE IN_FIFO: SLOW_RD_CLK - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: SPARE bit 2 IN_FIFO: SLOW_WR_CLK - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - IN_FIFO: SPARE bit 0 IN_FIFO: SPARE bit 1 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT_FIFO rect MAIN[10]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CMT_FIFO rect MAIN[11]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Table PLL_MULT

virtex7 table PLL_MULT
Row PLL_CP_LOW PLL_CP_HIGH PLL_CP_SS PLL_RES_LOW PLL_RES_HIGH PLL_RES_SS PLL_LFHF_LOW PLL_LFHF_HIGH PLL_LFHF_SS LOCK_REF_DLY LOCK_FB_DLY LOCK_CNT LOCK_SAT_HIGH UNLOCK_CNT
MMCM_1 0b0000 0b0000 0b0000 0b0000 0b0000 0b0000 0b00 0b00 0b00 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
MMCM_2 0b0010 0b0100 0b0010 0b1111 0b1111 0b1111 0b00 0b00 0b11 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
MMCM_3 0b0010 0b0101 0b0010 0b1111 0b1011 0b1111 0b00 0b00 0b11 0b01000 0b01000 0b1111101000 0b1111101001 0b0000000001
MMCM_4 0b0010 0b0111 0b0010 0b1111 0b0111 0b1111 0b00 0b00 0b11 0b01011 0b01011 0b1111101000 0b1111101001 0b0000000001
MMCM_5 0b0010 0b1101 0b0010 0b0111 0b0111 0b0111 0b00 0b00 0b11 0b01110 0b01110 0b1111101000 0b1111101001 0b0000000001
MMCM_6 0b0010 0b1110 0b0010 0b1011 0b1011 0b1011 0b00 0b00 0b11 0b10001 0b10001 0b1111101000 0b1111101001 0b0000000001
MMCM_7 0b0010 0b1110 0b0010 0b1101 0b1101 0b1101 0b00 0b00 0b11 0b10011 0b10011 0b1111101000 0b1111101001 0b0000000001
MMCM_8 0b0010 0b1111 0b0010 0b0011 0b0011 0b0011 0b00 0b00 0b11 0b10110 0b10110 0b1111101000 0b1111101001 0b0000000001
MMCM_9 0b0010 0b1110 0b0010 0b0101 0b0101 0b0101 0b00 0b00 0b11 0b11001 0b11001 0b1111101000 0b1111101001 0b0000000001
MMCM_10 0b0010 0b1111 0b0010 0b0101 0b0101 0b0101 0b00 0b00 0b11 0b11100 0b11100 0b1111101000 0b1111101001 0b0000000001
MMCM_11 0b0010 0b1111 0b0010 0b1001 0b1001 0b1001 0b00 0b00 0b11 0b11111 0b11111 0b1110000100 0b1111101001 0b0000000001
MMCM_12 0b0010 0b1101 0b0010 0b1110 0b0001 0b1110 0b00 0b00 0b11 0b11111 0b11111 0b1100111001 0b1111101001 0b0000000001
MMCM_13 0b0010 0b1111 0b0010 0b1110 0b1001 0b1110 0b00 0b00 0b11 0b11111 0b11111 0b1011101110 0b1111101001 0b0000000001
MMCM_14 0b0010 0b1111 0b0010 0b1110 0b1001 0b1110 0b00 0b00 0b11 0b11111 0b11111 0b1010111100 0b1111101001 0b0000000001
MMCM_15 0b0010 0b1111 0b0010 0b1110 0b1001 0b1110 0b00 0b00 0b11 0b11111 0b11111 0b1010001010 0b1111101001 0b0000000001
MMCM_16 0b0010 0b1111 0b0010 0b0001 0b1001 0b0001 0b00 0b00 0b11 0b11111 0b11111 0b1001110001 0b1111101001 0b0000000001
MMCM_17 0b0010 0b1111 0b0010 0b0001 0b0101 0b0001 0b00 0b00 0b11 0b11111 0b11111 0b1000111111 0b1111101001 0b0000000001
MMCM_18 0b0010 0b1111 0b0010 0b0001 0b0101 0b0001 0b00 0b00 0b11 0b11111 0b11111 0b1000100110 0b1111101001 0b0000000001
MMCM_19 0b0010 0b1100 0b0010 0b0110 0b0001 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b1000001101 0b1111101001 0b0000000001
MMCM_20 0b0010 0b1100 0b0010 0b0110 0b0001 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0111110100 0b1111101001 0b0000000001
MMCM_21 0b0010 0b1100 0b0010 0b0110 0b0001 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0111011011 0b1111101001 0b0000000001
MMCM_22 0b0010 0b0101 0b0010 0b0110 0b1100 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0111000010 0b1111101001 0b0000000001
MMCM_23 0b0010 0b0101 0b0010 0b0110 0b1100 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0110101001 0b1111101001 0b0000000001
MMCM_24 0b0010 0b0101 0b0010 0b0110 0b1100 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
MMCM_25 0b0010 0b0101 0b0010 0b0110 0b1100 0b0110 0b00 0b00 0b11 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
MMCM_26 0b0010 0b0011 0b0010 0b1010 0b0100 0b1010 0b00 0b00 0b11 0b11111 0b11111 0b0101110111 0b1111101001 0b0000000001
MMCM_27 0b0010 0b0011 0b0010 0b1010 0b0100 0b1010 0b00 0b00 0b11 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
MMCM_28 0b0010 0b0011 0b0010 0b1010 0b0100 0b1010 0b00 0b00 0b11 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
MMCM_29 0b0010 0b0011 0b0010 0b1010 0b0100 0b1010 0b00 0b00 0b11 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
MMCM_30 0b0010 0b0011 0b0010 0b1010 0b0100 0b1010 0b00 0b00 0b11 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
MMCM_31 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_32 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_33 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_34 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_35 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_36 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_37 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_38 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_39 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_40 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_41 0b0010 0b0011 0b0010 0b1100 0b0100 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_42 0b0010 0b0010 0b0010 0b1100 0b1000 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_43 0b0010 0b0010 0b0010 0b1100 0b1000 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_44 0b0010 0b0010 0b0010 0b1100 0b1000 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_45 0b0010 0b0010 0b0010 0b1100 0b1000 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_46 0b0010 0b0010 0b0010 0b1100 0b1000 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_47 0b0010 0b0111 0b0010 0b1100 0b0001 0b1100 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_48 0b0010 0b0111 0b0010 0b0010 0b0001 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_49 0b0010 0b0100 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_50 0b0010 0b0100 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_51 0b0010 0b0100 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_52 0b0010 0b0100 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_53 0b0010 0b0110 0b0010 0b0010 0b0001 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_54 0b0010 0b0110 0b0010 0b0010 0b0001 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_55 0b0010 0b0101 0b0010 0b0010 0b0110 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_56 0b0010 0b0101 0b0010 0b0010 0b0110 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_57 0b0010 0b0101 0b0010 0b0010 0b0110 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_58 0b0010 0b0010 0b0010 0b0010 0b0100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_59 0b0010 0b0010 0b0010 0b0010 0b0100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_60 0b0010 0b0010 0b0010 0b0010 0b0100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_61 0b0010 0b0010 0b0010 0b0010 0b0100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_62 0b0010 0b0100 0b0010 0b0010 0b1010 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_63 0b0010 0b0011 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_64 0b0010 0b0011 0b0010 0b0010 0b1100 0b0010 0b00 0b00 0b11 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_1 0b0000 0b0000 - 0b0000 0b0000 - 0b00 0b00 - 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
PLL_2 0b0010 0b0011 - 0b1111 0b0111 - 0b00 0b00 - 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
PLL_3 0b0010 0b0101 - 0b0111 0b1111 - 0b00 0b00 - 0b01000 0b01000 0b1111101000 0b1111101001 0b0000000001
PLL_4 0b0010 0b0111 - 0b1101 0b1111 - 0b00 0b00 - 0b01011 0b01011 0b1111101000 0b1111101001 0b0000000001
PLL_5 0b0010 0b0111 - 0b0101 0b1011 - 0b00 0b00 - 0b01110 0b01110 0b1111101000 0b1111101001 0b0000000001
PLL_6 0b0010 0b1101 - 0b0101 0b0111 - 0b00 0b00 - 0b10001 0b10001 0b1111101000 0b1111101001 0b0000000001
PLL_7 0b0010 0b1110 - 0b1001 0b1011 - 0b00 0b00 - 0b10011 0b10011 0b1111101000 0b1111101001 0b0000000001
PLL_8 0b0010 0b1110 - 0b1110 0b1101 - 0b00 0b00 - 0b10110 0b10110 0b1111101000 0b1111101001 0b0000000001
PLL_9 0b0010 0b1111 - 0b1110 0b1101 - 0b00 0b00 - 0b11001 0b11001 0b1111101000 0b1111101001 0b0000000001
PLL_10 0b0010 0b1111 - 0b0001 0b0111 - 0b00 0b00 - 0b11100 0b11100 0b1111101000 0b1111101001 0b0000000001
PLL_11 0b0010 0b1111 - 0b0001 0b1011 - 0b00 0b00 - 0b11111 0b11111 0b1110000100 0b1111101001 0b0000000001
PLL_12 0b0010 0b1111 - 0b0110 0b1101 - 0b00 0b00 - 0b11111 0b11111 0b1100111001 0b1111101001 0b0000000001
PLL_13 0b0010 0b1111 - 0b0110 0b0011 - 0b00 0b00 - 0b11111 0b11111 0b1011101110 0b1111101001 0b0000000001
PLL_14 0b0010 0b1110 - 0b0110 0b0101 - 0b00 0b00 - 0b11111 0b11111 0b1010111100 0b1111101001 0b0000000001
PLL_15 0b0010 0b1111 - 0b0110 0b0101 - 0b00 0b00 - 0b11111 0b11111 0b1010001010 0b1111101001 0b0000000001
PLL_16 0b0010 0b1111 - 0b1010 0b0101 - 0b00 0b00 - 0b11111 0b11111 0b1001110001 0b1111101001 0b0000000001
PLL_17 0b0010 0b1111 - 0b1010 0b0101 - 0b00 0b00 - 0b11111 0b11111 0b1000111111 0b1111101001 0b0000000001
PLL_18 0b0010 0b1111 - 0b1010 0b0101 - 0b00 0b00 - 0b11111 0b11111 0b1000100110 0b1111101001 0b0000000001
PLL_19 0b0010 0b0111 - 0b1010 0b0110 - 0b00 0b00 - 0b11111 0b11111 0b1000001101 0b1111101001 0b0000000001
PLL_20 0b0010 0b0111 - 0b1100 0b0110 - 0b00 0b00 - 0b11111 0b11111 0b0111110100 0b1111101001 0b0000000001
PLL_21 0b0010 0b0111 - 0b1100 0b0110 - 0b00 0b00 - 0b11111 0b11111 0b0111011011 0b1111101001 0b0000000001
PLL_22 0b0010 0b0111 - 0b1100 0b0110 - 0b00 0b00 - 0b11111 0b11111 0b0111000010 0b1111101001 0b0000000001
PLL_23 0b0010 0b0101 - 0b1100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0110101001 0b1111101001 0b0000000001
PLL_24 0b0010 0b0101 - 0b1100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
PLL_25 0b0010 0b0101 - 0b1100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
PLL_26 0b0010 0b1100 - 0b1100 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0101110111 0b1111101001 0b0000000001
PLL_27 0b0010 0b1100 - 0b1100 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
PLL_28 0b0010 0b1100 - 0b1100 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
PLL_29 0b0010 0b1100 - 0b1100 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
PLL_30 0b0010 0b1100 - 0b1100 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
PLL_31 0b0010 0b1100 - 0b0010 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
PLL_32 0b0010 0b1100 - 0b0010 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
PLL_33 0b0010 0b1100 - 0b0010 0b0001 - 0b00 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
PLL_34 0b0010 0b0100 - 0b0010 0b0010 - 0b00 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
PLL_35 0b0010 0b0100 - 0b0010 0b0010 - 0b00 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
PLL_36 0b0010 0b0100 - 0b0010 0b0010 - 0b00 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
PLL_37 0b0010 0b0010 - 0b0010 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_38 0b0010 0b0010 - 0b0010 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_39 0b0010 0b0010 - 0b0010 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_40 0b0010 0b0011 - 0b0010 0b0100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_41 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_42 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_43 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_44 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_45 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_46 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_47 0b0011 0b0010 - 0b1100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_48 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_49 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_50 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_51 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_52 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_53 0b0010 0b0010 - 0b0100 0b1000 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_54 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_55 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_56 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_57 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_58 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_59 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_60 0b0010 0b0100 - 0b0100 0b1100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_61 0b0010 0b0010 - 0b0100 0b0100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_62 0b0010 0b0010 - 0b0100 0b0100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_63 0b0010 0b0010 - 0b0100 0b0100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
PLL_64 0b0010 0b0010 - 0b0100 0b0100 - 0b00 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001