Input/Output

Tile IO_W

Cells: 1

Switchbox INT

xc5200 IO_W switchbox INT permanent buffers
Destination	Source
IO_M_BUF[0]	IO_M[0]
IO_M_BUF[1]	IO_M[1]
IO_M_BUF[2]	IO_M[2]
IO_M_BUF[3]	IO_M[3]
IO_M_BUF[4]	IO_M[4]
IO_M_BUF[5]	IO_M[5]
IO_M_BUF[6]	IO_M[6]
IO_M_BUF[7]	IO_M[7]
IO_M_BUF[8]	IO_M[8]
IO_M_BUF[9]	IO_M[9]
IO_M_BUF[10]	IO_M[10]
IO_M_BUF[11]	IO_M[11]
IO_M_BUF[12]	IO_M[12]
IO_M_BUF[13]	IO_M[13]
IO_M_BUF[14]	IO_M[14]
IO_M_BUF[15]	IO_M[15]
OMUX_BUF[0]	OMUX[0]
OMUX_BUF[1]	OMUX[1]
OMUX_BUF[2]	OMUX[2]
OMUX_BUF[3]	OMUX[3]

xc5200 IO_W switchbox INT pass gates
Destination	Source	Bit
IO_M[0]	LONG_V[0]	!MAIN[2][8]
IO_M[0]	OMUX_BUF[0]	!MAIN[1][2]
IO_M[1]	LONG_V[1]	!MAIN[2][9]
IO_M[1]	OMUX_BUF[1]	!MAIN[1][6]
IO_M[2]	LONG_V[2]	!MAIN[2][26]
IO_M[2]	OMUX_BUF[2]	!MAIN[0][26]
IO_M[3]	LONG_V[3]	!MAIN[2][27]
IO_M[3]	OMUX_BUF[3]	!MAIN[1][18]
IO_M[4]	LONG_V[4]	!MAIN[2][3]
IO_M[4]	OMUX_BUF[1]	!MAIN[0][5]
IO_M[5]	LONG_V[5]	!MAIN[2][14]
IO_M[5]	OMUX_BUF[2]	!MAIN[1][10]
IO_M[6]	LONG_V[6]	!MAIN[2][21]
IO_M[6]	OMUX_BUF[3]	!MAIN[1][14]
IO_M[7]	LONG_V[7]	!MAIN[2][32]
IO_M[7]	OMUX_BUF[0]	!MAIN[1][22]
IO_M[8]	LONG_H[0]	!MAIN[2][5]
IO_M[8]	OMUX_BUF[2]	!MAIN[0][9]
IO_M[9]	LONG_H[1]	!MAIN[2][12]
IO_M[9]	OMUX_BUF[3]	!MAIN[1][31]
IO_M[10]	LONG_H[2]	!MAIN[2][23]
IO_M[10]	OMUX_BUF[0]	!MAIN[0][29]
IO_M[11]	LONG_H[3]	!MAIN[2][30]
IO_M[11]	OMUX_BUF[1]	!MAIN[0][19]
IO_M[12]	LONG_H[4]	!MAIN[2][0]
IO_M[12]	OMUX_BUF[3]	!MAIN[0][13]
IO_M[13]	LONG_H[5]	!MAIN[2][17]
IO_M[13]	OMUX_BUF[0]	!MAIN[0][11]
IO_M[14]	LONG_H[6]	!MAIN[2][18]
IO_M[14]	OMUX_BUF[1]	!MAIN[1][24]
IO_M[15]	LONG_H[7]	!MAIN[1][33]
IO_M[15]	OMUX_BUF[2]	!MAIN[1][26]
LONG_H[0]	OUT_TBUF[0]	!MAIN[2][6]
LONG_H[1]	OUT_TBUF[1]	!MAIN[2][11]
LONG_H[2]	OUT_TBUF[2]	!MAIN[2][24]
LONG_H[3]	OUT_TBUF[3]	!MAIN[2][29]
LONG_H[4]	OUT_TBUF[0]	!MAIN[2][1]
LONG_H[5]	OUT_TBUF[1]	!MAIN[2][16]
LONG_H[6]	OUT_TBUF[2]	!MAIN[2][19]
LONG_H[7]	OUT_TBUF[3]	!MAIN[1][32]
LONG_V[0]	OUT_TBUF[0]	!MAIN[2][7]
LONG_V[1]	OUT_TBUF[1]	!MAIN[2][10]
LONG_V[2]	OUT_TBUF[2]	!MAIN[2][25]
LONG_V[3]	OUT_TBUF[3]	!MAIN[2][28]
LONG_V[4]	OUT_TBUF[0]	!MAIN[2][2]
LONG_V[5]	OUT_TBUF[1]	!MAIN[2][15]
LONG_V[6]	OUT_TBUF[2]	!MAIN[2][20]
LONG_V[7]	OUT_TBUF[3]	!MAIN[2][33]

xc5200 IO_W switchbox INT bidirectional pass gates
Side A	Side B	Bit
IO_M[0]	SINGLE_IO_W_N[0]	!MAIN[0][2]
IO_M[0]	SINGLE_IO_W_S[0]	!MAIN[0][0]
IO_M[0]	DBL_H_W[0]	!MAIN[1][0]
IO_M[1]	SINGLE_E[1]	!MAIN[1][8]
IO_M[1]	SINGLE_IO_W_N[1]	!MAIN[0][8]
IO_M[1]	SINGLE_IO_W_S[1]	!MAIN[0][6]
IO_M[2]	SINGLE_E[2]	!MAIN[0][30]
IO_M[2]	SINGLE_IO_W_N[2]	!MAIN[1][30]
IO_M[2]	SINGLE_IO_W_S[2]	!MAIN[1][27]
IO_M[3]	SINGLE_E[3]	!MAIN[1][16]
IO_M[3]	SINGLE_IO_W_N[3]	!MAIN[0][18]
IO_M[3]	SINGLE_IO_W_S[3]	!MAIN[0][16]
IO_M[4]	SINGLE_E[4]	!MAIN[0][4]
IO_M[4]	SINGLE_IO_W_N[4]	!MAIN[1][5]
IO_M[4]	SINGLE_IO_W_S[4]	!MAIN[1][4]
IO_M[5]	SINGLE_E[5]	!MAIN[1][12]
IO_M[5]	SINGLE_IO_W_N[5]	!MAIN[0][12]
IO_M[5]	SINGLE_IO_W_S[5]	!MAIN[0][10]
IO_M[6]	SINGLE_IO_W_N[6]	!MAIN[0][14]
IO_M[6]	SINGLE_IO_W_S[6]	!MAIN[1][25]
IO_M[6]	DBL_H_W[1]	!MAIN[0][25]
IO_M[7]	SINGLE_E[7]	!MAIN[1][20]
IO_M[7]	SINGLE_IO_W_N[7]	!MAIN[0][22]
IO_M[7]	SINGLE_IO_W_S[7]	!MAIN[0][20]
IO_M[8]	SINGLE_E[8]	!MAIN[0][1]
IO_M[8]	SINGLE_IO_W_N[1]	!MAIN[1][9]
IO_M[8]	SINGLE_IO_W_S[0]	!MAIN[1][1]
IO_M[9]	SINGLE_E[9]	!MAIN[0][7]
IO_M[9]	SINGLE_IO_W_N[2]	!MAIN[0][31]
IO_M[9]	SINGLE_IO_W_S[1]	!MAIN[1][7]
IO_M[10]	SINGLE_E[10]	!MAIN[1][28]
IO_M[10]	SINGLE_IO_W_N[3]	!MAIN[1][29]
IO_M[10]	SINGLE_IO_W_S[2]	!MAIN[0][27]
IO_M[11]	SINGLE_E[11]	!MAIN[0][17]
IO_M[11]	SINGLE_IO_W_N[4]	!MAIN[1][19]
IO_M[11]	SINGLE_IO_W_S[3]	!MAIN[1][17]
IO_M[12]	SINGLE_IO_W_N[5]	!MAIN[1][13]
IO_M[12]	SINGLE_IO_W_S[4]	!MAIN[0][3]
IO_M[12]	DBL_H_M[0]	!MAIN[1][3]
IO_M[13]	SINGLE_IO_W_N[6]	!MAIN[1][15]
IO_M[13]	SINGLE_IO_W_S[5]	!MAIN[1][11]
IO_M[13]	DBL_H_M[1]	!MAIN[0][15]
IO_M[14]	SINGLE_IO_W_N[7]	!MAIN[1][23]
IO_M[14]	SINGLE_IO_W_S[6]	!MAIN[0][24]
IO_M[15]	SINGLE_IO_W_N[0]	!MAIN[0][21]
IO_M[15]	SINGLE_IO_W_S[7]	!MAIN[1][21]

xc5200 IO_W switchbox INT muxes OMUX[0]
Bits							Destination
MAIN[5][15]	MAIN[4][14]	MAIN[3][15]	MAIN[3][14]	MAIN[4][15]	MAIN[5][14]	MAIN[5][16]	OMUX[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes OMUX[1]
Bits							Destination
MAIN[5][12]	MAIN[4][12]	MAIN[4][13]	MAIN[3][11]	MAIN[3][13]	MAIN[5][13]	MAIN[5][11]	OMUX[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[14]
1	0	1	1	1	1	0	OUT_IO_I[2]
1	1	0	1	1	0	1	IO_M_BUF[15]
1	1	0	1	1	1	0	OUT_IO_I[3]
1	1	1	0	1	0	1	IO_M_BUF[8]
1	1	1	0	1	1	0	OUT_IO_I[0]
1	1	1	1	0	0	1	IO_M_BUF[9]
1	1	1	1	0	1	0	OUT_IO_I[1]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes OMUX[2]
Bits							Destination
MAIN[5][18]	MAIN[3][17]	MAIN[4][17]	MAIN[4][16]	MAIN[3][16]	MAIN[5][19]	MAIN[5][17]	OMUX[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes OMUX[3]
Bits							Destination
MAIN[5][20]	MAIN[4][20]	MAIN[3][20]	MAIN[4][18]	MAIN[4][19]	MAIN[3][19]	MAIN[5][21]	OMUX[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_TS
Bits							Destination
MAIN[5][10]	MAIN[4][11]	MAIN[3][10]	MAIN[3][9]	MAIN[4][10]	MAIN[5][9]	MAIN[4][9]	IMUX_TS
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[11]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[10]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_GIN
Bits					Destination
MAIN[5][33]	MAIN[4][32]	MAIN[4][33]	MAIN[5][32]	MAIN[4][31]	IMUX_GIN
					Source
0	0	1	1	1	IO_M_BUF[6]
0	1	0	1	1	IO_M_BUF[7]
0	1	1	0	1	IO_M_BUF[12]
0	1	1	1	0	IO_M_BUF[13]
0	1	1	1	1	TIE_0
1	1	1	1	1	GCLK_SW

xc5200 IO_W switchbox INT muxes IMUX_IO_O[0]
Bits								Destination
MAIN[5][24]	MAIN[3][21]	MAIN[3][22]	MAIN[4][21]	MAIN[4][22]	MAIN[5][22]	MAIN[5][23]	MAIN[6][2]	IMUX_IO_O[0]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_W[0]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_O[1]
Bits								Destination
MAIN[4][23]	MAIN[3][26]	MAIN[3][23]	MAIN[4][24]	MAIN[3][24]	MAIN[5][26]	MAIN[5][25]	MAIN[6][13]	IMUX_IO_O[1]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_W[1]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_O[2]
Bits								Destination
MAIN[3][28]	MAIN[3][27]	MAIN[4][27]	MAIN[3][25]	MAIN[4][26]	MAIN[5][27]	MAIN[5][28]	MAIN[6][18]	IMUX_IO_O[2]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_W[2]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_O[3]
Bits								Destination
MAIN[5][29]	MAIN[4][28]	MAIN[4][29]	MAIN[4][30]	MAIN[3][31]	MAIN[5][31]	MAIN[5][30]	MAIN[6][29]	IMUX_IO_O[3]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	1	IO_M_BUF[10]
1	0	1	1	1	1	0	1	IO_M_BUF[14]
1	1	0	1	1	0	1	1	IO_M_BUF[11]
1	1	0	1	1	1	0	1	IO_M_BUF[15]
1	1	1	0	1	0	1	1	IO_M_BUF[9]
1	1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	1	1	0	0	1	1	IO_M_BUF[8]
1	1	1	1	0	1	0	1	IO_M_BUF[12]
1	1	1	1	1	1	1	0	OMUX_BUF_W[3]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_T[0]
Bits							Destination
MAIN[5][0]	MAIN[3][0]	MAIN[3][1]	MAIN[4][1]	MAIN[4][0]	MAIN[5][1]	MAIN[5][2]	IMUX_IO_T[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_W[1]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[9]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_T[1]
Bits							Destination
MAIN[3][3]	MAIN[4][2]	MAIN[3][4]	MAIN[3][2]	MAIN[4][3]	MAIN[5][3]	MAIN[5][4]	IMUX_IO_T[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_W[2]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[12]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_T[2]
Bits							Destination
MAIN[5][6]	MAIN[3][12]	MAIN[3][6]	MAIN[4][4]	MAIN[4][5]	MAIN[5][5]	MAIN[3][5]	IMUX_IO_T[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[13]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	OMUX_BUF_W[3]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_W switchbox INT muxes IMUX_IO_T[3]
Bits							Destination
MAIN[5][7]	MAIN[4][6]	MAIN[3][8]	MAIN[3][7]	MAIN[4][7]	MAIN[5][8]	MAIN[4][8]	IMUX_IO_T[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_W[0]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[8]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

Switchbox BUFR

xc5200 IO_W switchbox BUFR permanent buffers
Destination	Source
GCLK_W	IMUX_GIN

Bels TBUF

xc5200 IO_W bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
I	in	OMUX_BUF[0]	OMUX_BUF[1]	OMUX_BUF[2]	OMUX_BUF[3]
T	in	IMUX_TS	IMUX_TS	IMUX_TS	IMUX_TS
O	out	OUT_TBUF[0]	OUT_TBUF[1]	OUT_TBUF[2]	OUT_TBUF[3]

xc5200 IO_W bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
T_ENABLE	!MAIN[2][4]	!MAIN[2][13]	!MAIN[2][22]	!MAIN[2][31]

Bels IO

xc5200 IO_W bel IO pins
Pin	Direction	IO[0]	IO[1]	IO[2]	IO[3]
O	in	IMUX_IO_O[0] invert by !MAIN[6][3]	IMUX_IO_O[1] invert by !MAIN[6][12]	IMUX_IO_O[2] invert by !MAIN[6][19]	IMUX_IO_O[3] invert by !MAIN[6][28]
T	in	IMUX_IO_T[0] invert by MAIN[6][1]	IMUX_IO_T[1] invert by MAIN[6][14]	IMUX_IO_T[2] invert by MAIN[6][17]	IMUX_IO_T[3] invert by MAIN[6][30]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]

xc5200 IO_W bel IO attribute bits
Attribute	IO[0]	IO[1]	IO[2]	IO[3]
SLEW	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
DELAY_ENABLE	!MAIN[6][5]	!MAIN[6][10]	!MAIN[6][21]	!MAIN[6][26]
INV_I	!MAIN[6][4]	!MAIN[6][11]	!MAIN[6][20]	!MAIN[6][27]

xc5200 IO_W enum IO_SLEW
IO[0].SLEW	MAIN[6][6]
IO[1].SLEW	MAIN[6][9]
IO[2].SLEW	MAIN[6][22]
IO[3].SLEW	MAIN[6][25]
FAST	1
SLOW	0

xc5200 IO_W enum IO_PULL
IO[0].PULL	MAIN[6][7]	MAIN[6][8]
IO[1].PULL	MAIN[6][15]	MAIN[6][16]
IO[2].PULL	MAIN[6][23]	MAIN[6][24]
IO[3].PULL	MAIN[6][31]	MAIN[6][32]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

Bel wires

xc5200 IO_W bel wires
Wire	Pins
OMUX_BUF[0]	TBUF[0].I
OMUX_BUF[1]	TBUF[1].I
OMUX_BUF[2]	TBUF[2].I
OMUX_BUF[3]	TBUF[3].I
OUT_TBUF[0]	TBUF[0].O
OUT_TBUF[1]	TBUF[1].O
OUT_TBUF[2]	TBUF[2].O
OUT_TBUF[3]	TBUF[3].O
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
IMUX_TS	TBUF[0].T, TBUF[1].T, TBUF[2].T, TBUF[3].T
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T

Bitstream

xc5200 IO_W rect MAIN
Bit	Frame
Bit	F6	F5	F4	F3	F2	F1	F0
B33	-	INT: mux IMUX_GIN bit 4	INT: mux IMUX_GIN bit 2	-	INT: !pass LONG_V[7] ← OUT_TBUF[3]	INT: !pass IO_M[15] ← LONG_H[7]	-
B32	IO[3]: PULL bit 0	INT: mux IMUX_GIN bit 1	INT: mux IMUX_GIN bit 3	-	INT: !pass IO_M[7] ← LONG_V[7]	INT: !pass LONG_H[7] ← OUT_TBUF[3]	-
B31	IO[3]: PULL bit 1	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_GIN bit 0	INT: mux IMUX_IO_O[3] bit 3	TBUF[3]: ! T_ENABLE	INT: !pass IO_M[9] ← OMUX_BUF[3]	INT: !bipass IO_M[9] = SINGLE_IO_W_N[2]
B30	IO[3]: invert T	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[3] bit 4	-	INT: !pass IO_M[11] ← LONG_H[3]	INT: !bipass IO_M[2] = SINGLE_IO_W_N[2]	INT: !bipass IO_M[2] = SINGLE_E[2]
B29	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 5	-	INT: !pass LONG_H[3] ← OUT_TBUF[3]	INT: !bipass IO_M[10] = SINGLE_IO_W_N[3]	INT: !pass IO_M[10] ← OMUX_BUF[0]
B28	IO[3]: !invert O	INT: mux IMUX_IO_O[2] bit 1	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[2] bit 7	INT: !pass LONG_V[3] ← OUT_TBUF[3]	INT: !bipass IO_M[10] = SINGLE_E[10]	-
B27	IO[3]: ! INV_I	INT: mux IMUX_IO_O[2] bit 2	INT: mux IMUX_IO_O[2] bit 5	INT: mux IMUX_IO_O[2] bit 6	INT: !pass IO_M[3] ← LONG_V[3]	INT: !bipass IO_M[2] = SINGLE_IO_W_S[2]	INT: !bipass IO_M[10] = SINGLE_IO_W_S[2]
B26	IO[3]: ! DELAY_ENABLE	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[1] bit 6	INT: !pass IO_M[2] ← LONG_V[2]	INT: !pass IO_M[15] ← OMUX_BUF[2]	INT: !pass IO_M[2] ← OMUX_BUF[2]
B25	IO[3]: SLEW bit 0	INT: mux IMUX_IO_O[1] bit 1	-	INT: mux IMUX_IO_O[2] bit 4	INT: !pass LONG_V[2] ← OUT_TBUF[2]	INT: !bipass IO_M[6] = SINGLE_IO_W_S[6]	INT: !bipass IO_M[6] = DBL_H_W[1]
B24	IO[2]: PULL bit 0	INT: mux IMUX_IO_O[0] bit 7	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[1] bit 3	INT: !pass LONG_H[2] ← OUT_TBUF[2]	INT: !pass IO_M[14] ← OMUX_BUF[1]	INT: !bipass IO_M[14] = SINGLE_IO_W_S[6]
B23	IO[2]: PULL bit 1	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_O[1] bit 7	INT: mux IMUX_IO_O[1] bit 5	INT: !pass IO_M[10] ← LONG_H[2]	INT: !bipass IO_M[14] = SINGLE_IO_W_N[7]	-
B22	IO[2]: SLEW bit 0	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 5	TBUF[2]: ! T_ENABLE	INT: !pass IO_M[7] ← OMUX_BUF[0]	INT: !bipass IO_M[7] = SINGLE_IO_W_N[7]
B21	IO[2]: ! DELAY_ENABLE	INT: mux OMUX[3] bit 0	INT: mux IMUX_IO_O[0] bit 4	INT: mux IMUX_IO_O[0] bit 6	INT: !pass IO_M[6] ← LONG_V[6]	INT: !bipass IO_M[15] = SINGLE_IO_W_S[7]	INT: !bipass IO_M[15] = SINGLE_IO_W_N[0]
B20	IO[2]: ! INV_I	INT: mux OMUX[3] bit 6	INT: mux OMUX[3] bit 5	INT: mux OMUX[3] bit 4	INT: !pass LONG_V[6] ← OUT_TBUF[2]	INT: !bipass IO_M[7] = SINGLE_E[7]	INT: !bipass IO_M[7] = SINGLE_IO_W_S[7]
B19	IO[2]: !invert O	INT: mux OMUX[2] bit 1	INT: mux OMUX[3] bit 2	INT: mux OMUX[3] bit 1	INT: !pass LONG_H[6] ← OUT_TBUF[2]	INT: !bipass IO_M[11] = SINGLE_IO_W_N[4]	INT: !pass IO_M[11] ← OMUX_BUF[1]
B18	INT: mux IMUX_IO_O[2] bit 0	INT: mux OMUX[2] bit 6	INT: mux OMUX[3] bit 3	-	INT: !pass IO_M[14] ← LONG_H[6]	INT: !pass IO_M[3] ← OMUX_BUF[3]	INT: !bipass IO_M[3] = SINGLE_IO_W_N[3]
B17	IO[2]: invert T	INT: mux OMUX[2] bit 0	INT: mux OMUX[2] bit 4	INT: mux OMUX[2] bit 5	INT: !pass IO_M[13] ← LONG_H[5]	INT: !bipass IO_M[11] = SINGLE_IO_W_S[3]	INT: !bipass IO_M[11] = SINGLE_E[11]
B16	IO[1]: PULL bit 0	INT: mux OMUX[0] bit 0	INT: mux OMUX[2] bit 3	INT: mux OMUX[2] bit 2	INT: !pass LONG_H[5] ← OUT_TBUF[1]	INT: !bipass IO_M[3] = SINGLE_E[3]	INT: !bipass IO_M[3] = SINGLE_IO_W_S[3]
B15	IO[1]: PULL bit 1	INT: mux OMUX[0] bit 6	INT: mux OMUX[0] bit 2	INT: mux OMUX[0] bit 4	INT: !pass LONG_V[5] ← OUT_TBUF[1]	INT: !bipass IO_M[13] = SINGLE_IO_W_N[6]	INT: !bipass IO_M[13] = DBL_H_M[1]
B14	IO[1]: invert T	INT: mux OMUX[0] bit 1	INT: mux OMUX[0] bit 5	INT: mux OMUX[0] bit 3	INT: !pass IO_M[5] ← LONG_V[5]	INT: !pass IO_M[6] ← OMUX_BUF[3]	INT: !bipass IO_M[6] = SINGLE_IO_W_N[6]
B13	INT: mux IMUX_IO_O[1] bit 0	INT: mux OMUX[1] bit 1	INT: mux OMUX[1] bit 4	INT: mux OMUX[1] bit 2	TBUF[1]: ! T_ENABLE	INT: !bipass IO_M[12] = SINGLE_IO_W_N[5]	INT: !pass IO_M[12] ← OMUX_BUF[3]
B12	IO[1]: !invert O	INT: mux OMUX[1] bit 6	INT: mux OMUX[1] bit 5	INT: mux IMUX_IO_T[2] bit 5	INT: !pass IO_M[9] ← LONG_H[1]	INT: !bipass IO_M[5] = SINGLE_E[5]	INT: !bipass IO_M[5] = SINGLE_IO_W_N[5]
B11	IO[1]: ! INV_I	INT: mux OMUX[1] bit 0	INT: mux IMUX_TS bit 5	INT: mux OMUX[1] bit 3	INT: !pass LONG_H[1] ← OUT_TBUF[1]	INT: !bipass IO_M[13] = SINGLE_IO_W_S[5]	INT: !pass IO_M[13] ← OMUX_BUF[0]
B10	IO[1]: ! DELAY_ENABLE	INT: mux IMUX_TS bit 6	INT: mux IMUX_TS bit 2	INT: mux IMUX_TS bit 4	INT: !pass LONG_V[1] ← OUT_TBUF[1]	INT: !pass IO_M[5] ← OMUX_BUF[2]	INT: !bipass IO_M[5] = SINGLE_IO_W_S[5]
B9	IO[1]: SLEW bit 0	INT: mux IMUX_TS bit 1	INT: mux IMUX_TS bit 0	INT: mux IMUX_TS bit 3	INT: !pass IO_M[1] ← LONG_V[1]	INT: !bipass IO_M[8] = SINGLE_IO_W_N[1]	INT: !pass IO_M[8] ← OMUX_BUF[2]
B8	IO[0]: PULL bit 0	INT: mux IMUX_IO_T[3] bit 1	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[3] bit 4	INT: !pass IO_M[0] ← LONG_V[0]	INT: !bipass IO_M[1] = SINGLE_E[1]	INT: !bipass IO_M[1] = SINGLE_IO_W_N[1]
B7	IO[0]: PULL bit 1	INT: mux IMUX_IO_T[3] bit 6	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[3] bit 3	INT: !pass LONG_V[0] ← OUT_TBUF[0]	INT: !bipass IO_M[9] = SINGLE_IO_W_S[1]	INT: !bipass IO_M[9] = SINGLE_E[9]
B6	IO[0]: SLEW bit 0	INT: mux IMUX_IO_T[2] bit 6	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 4	INT: !pass LONG_H[0] ← OUT_TBUF[0]	INT: !pass IO_M[1] ← OMUX_BUF[1]	INT: !bipass IO_M[1] = SINGLE_IO_W_S[1]
B5	IO[0]: ! DELAY_ENABLE	INT: mux IMUX_IO_T[2] bit 1	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 0	INT: !pass IO_M[8] ← LONG_H[0]	INT: !bipass IO_M[4] = SINGLE_IO_W_N[4]	INT: !pass IO_M[4] ← OMUX_BUF[1]
B4	IO[0]: ! INV_I	INT: mux IMUX_IO_T[1] bit 0	INT: mux IMUX_IO_T[2] bit 3	INT: mux IMUX_IO_T[1] bit 4	TBUF[0]: ! T_ENABLE	INT: !bipass IO_M[4] = SINGLE_IO_W_S[4]	INT: !bipass IO_M[4] = SINGLE_E[4]
B3	IO[0]: !invert O	INT: mux IMUX_IO_T[1] bit 1	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 6	INT: !pass IO_M[4] ← LONG_V[4]	INT: !bipass IO_M[12] = DBL_H_M[0]	INT: !bipass IO_M[12] = SINGLE_IO_W_S[4]
B2	INT: mux IMUX_IO_O[0] bit 0	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[1] bit 3	INT: !pass LONG_V[4] ← OUT_TBUF[0]	INT: !pass IO_M[0] ← OMUX_BUF[0]	INT: !bipass IO_M[0] = SINGLE_IO_W_N[0]
B1	IO[0]: invert T	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[0] bit 3	INT: mux IMUX_IO_T[0] bit 4	INT: !pass LONG_H[4] ← OUT_TBUF[0]	INT: !bipass IO_M[8] = SINGLE_IO_W_S[0]	INT: !bipass IO_M[8] = SINGLE_E[8]
B0	-	INT: mux IMUX_IO_T[0] bit 6	INT: mux IMUX_IO_T[0] bit 2	INT: mux IMUX_IO_T[0] bit 5	INT: !pass IO_M[12] ← LONG_H[4]	INT: !bipass IO_M[0] = DBL_H_W[0]	INT: !bipass IO_M[0] = SINGLE_IO_W_S[0]

Tile IO_E

Cells: 1

Switchbox INT

xc5200 IO_E switchbox INT permanent buffers
Destination	Source
IO_M_BUF[0]	IO_M[0]
IO_M_BUF[1]	IO_M[1]
IO_M_BUF[2]	IO_M[2]
IO_M_BUF[3]	IO_M[3]
IO_M_BUF[4]	IO_M[4]
IO_M_BUF[5]	IO_M[5]
IO_M_BUF[6]	IO_M[6]
IO_M_BUF[7]	IO_M[7]
IO_M_BUF[8]	IO_M[8]
IO_M_BUF[9]	IO_M[9]
IO_M_BUF[10]	IO_M[10]
IO_M_BUF[11]	IO_M[11]
IO_M_BUF[12]	IO_M[12]
IO_M_BUF[13]	IO_M[13]
IO_M_BUF[14]	IO_M[14]
IO_M_BUF[15]	IO_M[15]
OMUX_BUF[0]	OMUX[0]
OMUX_BUF[1]	OMUX[1]
OMUX_BUF[2]	OMUX[2]
OMUX_BUF[3]	OMUX[3]

xc5200 IO_E switchbox INT pass gates
Destination	Source	Bit
IO_M[0]	LONG_V[0]	!MAIN[4][8]
IO_M[0]	OMUX_BUF[0]	!MAIN[5][2]
IO_M[1]	LONG_V[1]	!MAIN[4][9]
IO_M[1]	OMUX_BUF[1]	!MAIN[5][6]
IO_M[2]	LONG_V[2]	!MAIN[4][26]
IO_M[2]	OMUX_BUF[2]	!MAIN[6][26]
IO_M[3]	LONG_V[3]	!MAIN[4][27]
IO_M[3]	OMUX_BUF[3]	!MAIN[5][18]
IO_M[4]	LONG_V[4]	!MAIN[4][3]
IO_M[4]	OMUX_BUF[1]	!MAIN[6][5]
IO_M[5]	LONG_V[5]	!MAIN[4][14]
IO_M[5]	OMUX_BUF[2]	!MAIN[5][10]
IO_M[6]	LONG_V[6]	!MAIN[4][21]
IO_M[6]	OMUX_BUF[3]	!MAIN[5][14]
IO_M[7]	LONG_V[7]	!MAIN[4][32]
IO_M[7]	OMUX_BUF[0]	!MAIN[5][22]
IO_M[8]	LONG_H[0]	!MAIN[4][5]
IO_M[8]	OMUX_BUF[2]	!MAIN[6][9]
IO_M[9]	LONG_H[1]	!MAIN[4][12]
IO_M[9]	OMUX_BUF[3]	!MAIN[5][31]
IO_M[10]	LONG_H[2]	!MAIN[4][23]
IO_M[10]	OMUX_BUF[0]	!MAIN[6][29]
IO_M[11]	LONG_H[3]	!MAIN[4][30]
IO_M[11]	OMUX_BUF[1]	!MAIN[6][19]
IO_M[12]	LONG_H[4]	!MAIN[4][0]
IO_M[12]	OMUX_BUF[3]	!MAIN[6][13]
IO_M[13]	LONG_H[5]	!MAIN[4][17]
IO_M[13]	OMUX_BUF[0]	!MAIN[6][11]
IO_M[14]	LONG_H[6]	!MAIN[4][18]
IO_M[14]	OMUX_BUF[1]	!MAIN[5][24]
IO_M[15]	LONG_H[7]	!MAIN[5][33]
IO_M[15]	OMUX_BUF[2]	!MAIN[5][26]
LONG_H[0]	OUT_TBUF[0]	!MAIN[4][6]
LONG_H[1]	OUT_TBUF[1]	!MAIN[4][11]
LONG_H[2]	OUT_TBUF[2]	!MAIN[4][24]
LONG_H[3]	OUT_TBUF[3]	!MAIN[4][29]
LONG_H[4]	OUT_TBUF[0]	!MAIN[4][1]
LONG_H[5]	OUT_TBUF[1]	!MAIN[4][16]
LONG_H[6]	OUT_TBUF[2]	!MAIN[4][19]
LONG_H[7]	OUT_TBUF[3]	!MAIN[5][32]
LONG_V[0]	OUT_TBUF[0]	!MAIN[4][7]
LONG_V[1]	OUT_TBUF[1]	!MAIN[4][10]
LONG_V[2]	OUT_TBUF[2]	!MAIN[4][25]
LONG_V[3]	OUT_TBUF[3]	!MAIN[4][28]
LONG_V[4]	OUT_TBUF[0]	!MAIN[4][2]
LONG_V[5]	OUT_TBUF[1]	!MAIN[4][15]
LONG_V[6]	OUT_TBUF[2]	!MAIN[4][20]
LONG_V[7]	OUT_TBUF[3]	!MAIN[4][33]

xc5200 IO_E switchbox INT bidirectional pass gates
Side A	Side B	Bit
IO_M[0]	SINGLE_IO_E_N[0]	!MAIN[6][2]
IO_M[0]	SINGLE_IO_E_S[0]	!MAIN[6][0]
IO_M[0]	DBL_H_E[0]	!MAIN[5][0]
IO_M[1]	SINGLE_W[1]	!MAIN[5][8]
IO_M[1]	SINGLE_IO_E_N[1]	!MAIN[6][8]
IO_M[1]	SINGLE_IO_E_S[1]	!MAIN[6][6]
IO_M[2]	SINGLE_W[2]	!MAIN[6][30]
IO_M[2]	SINGLE_IO_E_N[2]	!MAIN[5][30]
IO_M[2]	SINGLE_IO_E_S[2]	!MAIN[5][27]
IO_M[3]	SINGLE_W[3]	!MAIN[5][16]
IO_M[3]	SINGLE_IO_E_N[3]	!MAIN[6][18]
IO_M[3]	SINGLE_IO_E_S[3]	!MAIN[6][16]
IO_M[4]	SINGLE_W[4]	!MAIN[6][4]
IO_M[4]	SINGLE_IO_E_N[4]	!MAIN[5][5]
IO_M[4]	SINGLE_IO_E_S[4]	!MAIN[5][4]
IO_M[5]	SINGLE_W[5]	!MAIN[5][12]
IO_M[5]	SINGLE_IO_E_N[5]	!MAIN[6][12]
IO_M[5]	SINGLE_IO_E_S[5]	!MAIN[6][10]
IO_M[6]	SINGLE_IO_E_N[6]	!MAIN[6][14]
IO_M[6]	SINGLE_IO_E_S[6]	!MAIN[5][25]
IO_M[6]	DBL_H_E[1]	!MAIN[6][25]
IO_M[7]	SINGLE_W[7]	!MAIN[5][20]
IO_M[7]	SINGLE_IO_E_N[7]	!MAIN[6][22]
IO_M[7]	SINGLE_IO_E_S[7]	!MAIN[6][20]
IO_M[8]	SINGLE_W[8]	!MAIN[6][1]
IO_M[8]	SINGLE_IO_E_N[1]	!MAIN[5][9]
IO_M[8]	SINGLE_IO_E_S[0]	!MAIN[5][1]
IO_M[9]	SINGLE_W[9]	!MAIN[6][7]
IO_M[9]	SINGLE_IO_E_N[2]	!MAIN[6][31]
IO_M[9]	SINGLE_IO_E_S[1]	!MAIN[5][7]
IO_M[10]	SINGLE_W[10]	!MAIN[5][28]
IO_M[10]	SINGLE_IO_E_N[3]	!MAIN[5][29]
IO_M[10]	SINGLE_IO_E_S[2]	!MAIN[6][27]
IO_M[11]	SINGLE_W[11]	!MAIN[6][17]
IO_M[11]	SINGLE_IO_E_N[4]	!MAIN[5][19]
IO_M[11]	SINGLE_IO_E_S[3]	!MAIN[5][17]
IO_M[12]	SINGLE_IO_E_N[5]	!MAIN[5][13]
IO_M[12]	SINGLE_IO_E_S[4]	!MAIN[6][3]
IO_M[12]	DBL_H_M[0]	!MAIN[5][3]
IO_M[13]	SINGLE_IO_E_N[6]	!MAIN[5][15]
IO_M[13]	SINGLE_IO_E_S[5]	!MAIN[5][11]
IO_M[13]	DBL_H_M[1]	!MAIN[6][15]
IO_M[14]	SINGLE_IO_E_N[7]	!MAIN[5][23]
IO_M[14]	SINGLE_IO_E_S[6]	!MAIN[6][24]
IO_M[15]	SINGLE_IO_E_N[0]	!MAIN[6][21]
IO_M[15]	SINGLE_IO_E_S[7]	!MAIN[5][21]

xc5200 IO_E switchbox INT muxes OMUX[0]
Bits							Destination
MAIN[1][15]	MAIN[2][14]	MAIN[3][15]	MAIN[3][14]	MAIN[2][15]	MAIN[1][14]	MAIN[1][16]	OMUX[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes OMUX[1]
Bits							Destination
MAIN[1][12]	MAIN[2][12]	MAIN[2][13]	MAIN[3][11]	MAIN[3][13]	MAIN[1][13]	MAIN[1][11]	OMUX[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[14]
1	0	1	1	1	1	0	OUT_IO_I[2]
1	1	0	1	1	0	1	IO_M_BUF[15]
1	1	0	1	1	1	0	OUT_IO_I[3]
1	1	1	0	1	0	1	IO_M_BUF[8]
1	1	1	0	1	1	0	OUT_IO_I[0]
1	1	1	1	0	0	1	IO_M_BUF[9]
1	1	1	1	0	1	0	OUT_IO_I[1]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes OMUX[2]
Bits							Destination
MAIN[1][18]	MAIN[3][17]	MAIN[2][17]	MAIN[2][16]	MAIN[3][16]	MAIN[1][19]	MAIN[1][17]	OMUX[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes OMUX[3]
Bits							Destination
MAIN[1][20]	MAIN[2][20]	MAIN[3][20]	MAIN[2][18]	MAIN[2][19]	MAIN[3][19]	MAIN[1][21]	OMUX[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_TS
Bits							Destination
MAIN[1][10]	MAIN[2][11]	MAIN[3][10]	MAIN[3][9]	MAIN[2][10]	MAIN[1][9]	MAIN[2][9]	IMUX_TS
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[11]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[10]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_GIN
Bits					Destination
MAIN[1][33]	MAIN[2][32]	MAIN[2][33]	MAIN[1][32]	MAIN[2][31]	IMUX_GIN
					Source
0	0	1	1	1	IO_M_BUF[6]
0	1	0	1	1	IO_M_BUF[7]
0	1	1	0	1	IO_M_BUF[12]
0	1	1	1	0	IO_M_BUF[13]
0	1	1	1	1	TIE_0
1	1	1	1	1	GCLK_NE

xc5200 IO_E switchbox INT muxes IMUX_IO_O[0]
Bits								Destination
MAIN[1][24]	MAIN[3][21]	MAIN[3][22]	MAIN[2][21]	MAIN[2][22]	MAIN[1][22]	MAIN[1][23]	MAIN[0][2]	IMUX_IO_O[0]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_E[0]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_O[1]
Bits								Destination
MAIN[2][23]	MAIN[3][26]	MAIN[3][23]	MAIN[2][24]	MAIN[3][24]	MAIN[1][26]	MAIN[1][25]	MAIN[0][13]	IMUX_IO_O[1]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_E[1]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_O[2]
Bits								Destination
MAIN[3][28]	MAIN[3][27]	MAIN[2][27]	MAIN[3][25]	MAIN[2][26]	MAIN[1][27]	MAIN[1][28]	MAIN[0][18]	IMUX_IO_O[2]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	1	IO_M_BUF[8]
1	0	1	1	1	1	0	1	IO_M_BUF[12]
1	1	0	1	1	0	1	1	IO_M_BUF[9]
1	1	0	1	1	1	0	1	IO_M_BUF[13]
1	1	1	0	1	0	1	1	IO_M_BUF[10]
1	1	1	0	1	1	0	1	IO_M_BUF[14]
1	1	1	1	0	0	1	1	IO_M_BUF[11]
1	1	1	1	0	1	0	1	IO_M_BUF[15]
1	1	1	1	1	1	1	0	OMUX_BUF_E[2]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_O[3]
Bits								Destination
MAIN[1][29]	MAIN[2][28]	MAIN[2][29]	MAIN[2][30]	MAIN[3][31]	MAIN[1][31]	MAIN[1][30]	MAIN[0][29]	IMUX_IO_O[3]
								Source
0	0	1	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	1	IO_M_BUF[10]
1	0	1	1	1	1	0	1	IO_M_BUF[14]
1	1	0	1	1	0	1	1	IO_M_BUF[11]
1	1	0	1	1	1	0	1	IO_M_BUF[15]
1	1	1	0	1	0	1	1	IO_M_BUF[9]
1	1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	1	1	0	0	1	1	IO_M_BUF[8]
1	1	1	1	0	1	0	1	IO_M_BUF[12]
1	1	1	1	1	1	1	0	OMUX_BUF_E[3]
1	1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_T[0]
Bits							Destination
MAIN[1][0]	MAIN[3][0]	MAIN[3][1]	MAIN[2][1]	MAIN[2][0]	MAIN[1][1]	MAIN[1][2]	IMUX_IO_T[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_E[1]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[9]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_T[1]
Bits							Destination
MAIN[3][3]	MAIN[2][2]	MAIN[3][4]	MAIN[3][2]	MAIN[2][3]	MAIN[1][3]	MAIN[1][4]	IMUX_IO_T[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_E[2]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[12]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_T[2]
Bits							Destination
MAIN[1][6]	MAIN[3][12]	MAIN[3][6]	MAIN[2][4]	MAIN[2][5]	MAIN[1][5]	MAIN[3][5]	IMUX_IO_T[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[13]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	OMUX_BUF_E[3]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_E switchbox INT muxes IMUX_IO_T[3]
Bits							Destination
MAIN[1][7]	MAIN[2][6]	MAIN[3][8]	MAIN[3][7]	MAIN[2][7]	MAIN[1][8]	MAIN[2][8]	IMUX_IO_T[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_E[0]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[8]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[15]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	1	1	TIE_0

Switchbox BUFR

xc5200 IO_E switchbox BUFR permanent buffers
Destination	Source
GCLK_E	IMUX_GIN

Bels TBUF

xc5200 IO_E bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
I	in	OMUX_BUF[0]	OMUX_BUF[1]	OMUX_BUF[2]	OMUX_BUF[3]
T	in	IMUX_TS	IMUX_TS	IMUX_TS	IMUX_TS
O	out	OUT_TBUF[0]	OUT_TBUF[1]	OUT_TBUF[2]	OUT_TBUF[3]

xc5200 IO_E bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
T_ENABLE	!MAIN[4][4]	!MAIN[4][13]	!MAIN[4][22]	!MAIN[4][31]

Bels IO

xc5200 IO_E bel IO pins
Pin	Direction	IO[0]	IO[1]	IO[2]	IO[3]
O	in	IMUX_IO_O[0] invert by !MAIN[0][3]	IMUX_IO_O[1] invert by !MAIN[0][12]	IMUX_IO_O[2] invert by !MAIN[0][19]	IMUX_IO_O[3] invert by !MAIN[0][28]
T	in	IMUX_IO_T[0] invert by MAIN[0][1]	IMUX_IO_T[1] invert by MAIN[0][14]	IMUX_IO_T[2] invert by MAIN[0][17]	IMUX_IO_T[3] invert by MAIN[0][30]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]

xc5200 IO_E bel IO attribute bits
Attribute	IO[0]	IO[1]	IO[2]	IO[3]
SLEW	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
DELAY_ENABLE	!MAIN[0][5]	!MAIN[0][10]	!MAIN[0][21]	!MAIN[0][26]
INV_I	!MAIN[0][4]	!MAIN[0][11]	!MAIN[0][20]	!MAIN[0][27]

xc5200 IO_E enum IO_SLEW
IO[0].SLEW	MAIN[0][6]
IO[1].SLEW	MAIN[0][9]
IO[2].SLEW	MAIN[0][22]
IO[3].SLEW	MAIN[0][25]
FAST	1
SLOW	0

xc5200 IO_E enum IO_PULL
IO[0].PULL	MAIN[0][7]	MAIN[0][8]
IO[1].PULL	MAIN[0][15]	MAIN[0][16]
IO[2].PULL	MAIN[0][23]	MAIN[0][24]
IO[3].PULL	MAIN[0][31]	MAIN[0][32]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

Bel wires

xc5200 IO_E bel wires
Wire	Pins
OMUX_BUF[0]	TBUF[0].I
OMUX_BUF[1]	TBUF[1].I
OMUX_BUF[2]	TBUF[2].I
OMUX_BUF[3]	TBUF[3].I
OUT_TBUF[0]	TBUF[0].O
OUT_TBUF[1]	TBUF[1].O
OUT_TBUF[2]	TBUF[2].O
OUT_TBUF[3]	TBUF[3].O
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
IMUX_TS	TBUF[0].T, TBUF[1].T, TBUF[2].T, TBUF[3].T
IMUX_IO_O[0]	IO[0].O
IMUX_IO_O[1]	IO[1].O
IMUX_IO_O[2]	IO[2].O
IMUX_IO_O[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T

Bitstream

xc5200 IO_E rect MAIN
Bit	Frame
Bit	F7	F6	F5	F4	F3	F2	F1	F0
B33	-	-	INT: !pass IO_M[15] ← LONG_H[7]	INT: !pass LONG_V[7] ← OUT_TBUF[3]	-	INT: mux IMUX_GIN bit 2	INT: mux IMUX_GIN bit 4	-
B32	-	-	INT: !pass LONG_H[7] ← OUT_TBUF[3]	INT: !pass IO_M[7] ← LONG_V[7]	-	INT: mux IMUX_GIN bit 3	INT: mux IMUX_GIN bit 1	IO[3]: PULL bit 0
B31	-	INT: !bipass IO_M[9] = SINGLE_IO_E_N[2]	INT: !pass IO_M[9] ← OMUX_BUF[3]	TBUF[3]: ! T_ENABLE	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_GIN bit 0	INT: mux IMUX_IO_O[3] bit 2	IO[3]: PULL bit 1
B30	-	INT: !bipass IO_M[2] = SINGLE_W[2]	INT: !bipass IO_M[2] = SINGLE_IO_E_N[2]	INT: !pass IO_M[11] ← LONG_H[3]	-	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[3] bit 1	IO[3]: invert T
B29	-	INT: !pass IO_M[10] ← OMUX_BUF[0]	INT: !bipass IO_M[10] = SINGLE_IO_E_N[3]	INT: !pass LONG_H[3] ← OUT_TBUF[3]	-	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[3] bit 7	INT: mux IMUX_IO_O[3] bit 0
B28	-	-	INT: !bipass IO_M[10] = SINGLE_W[10]	INT: !pass LONG_V[3] ← OUT_TBUF[3]	INT: mux IMUX_IO_O[2] bit 7	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[2] bit 1	IO[3]: !invert O
B27	-	INT: !bipass IO_M[10] = SINGLE_IO_E_S[2]	INT: !bipass IO_M[2] = SINGLE_IO_E_S[2]	INT: !pass IO_M[3] ← LONG_V[3]	INT: mux IMUX_IO_O[2] bit 6	INT: mux IMUX_IO_O[2] bit 5	INT: mux IMUX_IO_O[2] bit 2	IO[3]: ! INV_I
B26	-	INT: !pass IO_M[2] ← OMUX_BUF[2]	INT: !pass IO_M[15] ← OMUX_BUF[2]	INT: !pass IO_M[2] ← LONG_V[2]	INT: mux IMUX_IO_O[1] bit 6	INT: mux IMUX_IO_O[2] bit 3	INT: mux IMUX_IO_O[1] bit 2	IO[3]: ! DELAY_ENABLE
B25	-	INT: !bipass IO_M[6] = DBL_H_E[1]	INT: !bipass IO_M[6] = SINGLE_IO_E_S[6]	INT: !pass LONG_V[2] ← OUT_TBUF[2]	INT: mux IMUX_IO_O[2] bit 4	-	INT: mux IMUX_IO_O[1] bit 1	IO[3]: SLEW bit 0
B24	-	INT: !bipass IO_M[14] = SINGLE_IO_E_S[6]	INT: !pass IO_M[14] ← OMUX_BUF[1]	INT: !pass LONG_H[2] ← OUT_TBUF[2]	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[0] bit 7	IO[2]: PULL bit 0
B23	-	-	INT: !bipass IO_M[14] = SINGLE_IO_E_N[7]	INT: !pass IO_M[10] ← LONG_H[2]	INT: mux IMUX_IO_O[1] bit 5	INT: mux IMUX_IO_O[1] bit 7	INT: mux IMUX_IO_O[0] bit 1	IO[2]: PULL bit 1
B22	-	INT: !bipass IO_M[7] = SINGLE_IO_E_N[7]	INT: !pass IO_M[7] ← OMUX_BUF[0]	TBUF[2]: ! T_ENABLE	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_O[0] bit 2	IO[2]: SLEW bit 0
B21	-	INT: !bipass IO_M[15] = SINGLE_IO_E_N[0]	INT: !bipass IO_M[15] = SINGLE_IO_E_S[7]	INT: !pass IO_M[6] ← LONG_V[6]	INT: mux IMUX_IO_O[0] bit 6	INT: mux IMUX_IO_O[0] bit 4	INT: mux OMUX[3] bit 0	IO[2]: ! DELAY_ENABLE
B20	-	INT: !bipass IO_M[7] = SINGLE_IO_E_S[7]	INT: !bipass IO_M[7] = SINGLE_W[7]	INT: !pass LONG_V[6] ← OUT_TBUF[2]	INT: mux OMUX[3] bit 4	INT: mux OMUX[3] bit 5	INT: mux OMUX[3] bit 6	IO[2]: ! INV_I
B19	-	INT: !pass IO_M[11] ← OMUX_BUF[1]	INT: !bipass IO_M[11] = SINGLE_IO_E_N[4]	INT: !pass LONG_H[6] ← OUT_TBUF[2]	INT: mux OMUX[3] bit 1	INT: mux OMUX[3] bit 2	INT: mux OMUX[2] bit 1	IO[2]: !invert O
B18	-	INT: !bipass IO_M[3] = SINGLE_IO_E_N[3]	INT: !pass IO_M[3] ← OMUX_BUF[3]	INT: !pass IO_M[14] ← LONG_H[6]	-	INT: mux OMUX[3] bit 3	INT: mux OMUX[2] bit 6	INT: mux IMUX_IO_O[2] bit 0
B17	-	INT: !bipass IO_M[11] = SINGLE_W[11]	INT: !bipass IO_M[11] = SINGLE_IO_E_S[3]	INT: !pass IO_M[13] ← LONG_H[5]	INT: mux OMUX[2] bit 5	INT: mux OMUX[2] bit 4	INT: mux OMUX[2] bit 0	IO[2]: invert T
B16	-	INT: !bipass IO_M[3] = SINGLE_IO_E_S[3]	INT: !bipass IO_M[3] = SINGLE_W[3]	INT: !pass LONG_H[5] ← OUT_TBUF[1]	INT: mux OMUX[2] bit 2	INT: mux OMUX[2] bit 3	INT: mux OMUX[0] bit 0	IO[1]: PULL bit 0
B15	-	INT: !bipass IO_M[13] = DBL_H_M[1]	INT: !bipass IO_M[13] = SINGLE_IO_E_N[6]	INT: !pass LONG_V[5] ← OUT_TBUF[1]	INT: mux OMUX[0] bit 4	INT: mux OMUX[0] bit 2	INT: mux OMUX[0] bit 6	IO[1]: PULL bit 1
B14	-	INT: !bipass IO_M[6] = SINGLE_IO_E_N[6]	INT: !pass IO_M[6] ← OMUX_BUF[3]	INT: !pass IO_M[5] ← LONG_V[5]	INT: mux OMUX[0] bit 3	INT: mux OMUX[0] bit 5	INT: mux OMUX[0] bit 1	IO[1]: invert T
B13	-	INT: !pass IO_M[12] ← OMUX_BUF[3]	INT: !bipass IO_M[12] = SINGLE_IO_E_N[5]	TBUF[1]: ! T_ENABLE	INT: mux OMUX[1] bit 2	INT: mux OMUX[1] bit 4	INT: mux OMUX[1] bit 1	INT: mux IMUX_IO_O[1] bit 0
B12	-	INT: !bipass IO_M[5] = SINGLE_IO_E_N[5]	INT: !bipass IO_M[5] = SINGLE_W[5]	INT: !pass IO_M[9] ← LONG_H[1]	INT: mux IMUX_IO_T[2] bit 5	INT: mux OMUX[1] bit 5	INT: mux OMUX[1] bit 6	IO[1]: !invert O
B11	-	INT: !pass IO_M[13] ← OMUX_BUF[0]	INT: !bipass IO_M[13] = SINGLE_IO_E_S[5]	INT: !pass LONG_H[1] ← OUT_TBUF[1]	INT: mux OMUX[1] bit 3	INT: mux IMUX_TS bit 5	INT: mux OMUX[1] bit 0	IO[1]: ! INV_I
B10	-	INT: !bipass IO_M[5] = SINGLE_IO_E_S[5]	INT: !pass IO_M[5] ← OMUX_BUF[2]	INT: !pass LONG_V[1] ← OUT_TBUF[1]	INT: mux IMUX_TS bit 4	INT: mux IMUX_TS bit 2	INT: mux IMUX_TS bit 6	IO[1]: ! DELAY_ENABLE
B9	-	INT: !pass IO_M[8] ← OMUX_BUF[2]	INT: !bipass IO_M[8] = SINGLE_IO_E_N[1]	INT: !pass IO_M[1] ← LONG_V[1]	INT: mux IMUX_TS bit 3	INT: mux IMUX_TS bit 0	INT: mux IMUX_TS bit 1	IO[1]: SLEW bit 0
B8	-	INT: !bipass IO_M[1] = SINGLE_IO_E_N[1]	INT: !bipass IO_M[1] = SINGLE_W[1]	INT: !pass IO_M[0] ← LONG_V[0]	INT: mux IMUX_IO_T[3] bit 4	INT: mux IMUX_IO_T[3] bit 0	INT: mux IMUX_IO_T[3] bit 1	IO[0]: PULL bit 0
B7	-	INT: !bipass IO_M[9] = SINGLE_W[9]	INT: !bipass IO_M[9] = SINGLE_IO_E_S[1]	INT: !pass LONG_V[0] ← OUT_TBUF[0]	INT: mux IMUX_IO_T[3] bit 3	INT: mux IMUX_IO_T[3] bit 2	INT: mux IMUX_IO_T[3] bit 6	IO[0]: PULL bit 1
B6	-	INT: !bipass IO_M[1] = SINGLE_IO_E_S[1]	INT: !pass IO_M[1] ← OMUX_BUF[1]	INT: !pass LONG_H[0] ← OUT_TBUF[0]	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[3] bit 5	INT: mux IMUX_IO_T[2] bit 6	IO[0]: SLEW bit 0
B5	-	INT: !pass IO_M[4] ← OMUX_BUF[1]	INT: !bipass IO_M[4] = SINGLE_IO_E_N[4]	INT: !pass IO_M[8] ← LONG_H[0]	INT: mux IMUX_IO_T[2] bit 0	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[2] bit 1	IO[0]: ! DELAY_ENABLE
B4	-	INT: !bipass IO_M[4] = SINGLE_W[4]	INT: !bipass IO_M[4] = SINGLE_IO_E_S[4]	TBUF[0]: ! T_ENABLE	INT: mux IMUX_IO_T[1] bit 4	INT: mux IMUX_IO_T[2] bit 3	INT: mux IMUX_IO_T[1] bit 0	IO[0]: ! INV_I
B3	-	INT: !bipass IO_M[12] = SINGLE_IO_E_S[4]	INT: !bipass IO_M[12] = DBL_H_M[0]	INT: !pass IO_M[4] ← LONG_V[4]	INT: mux IMUX_IO_T[1] bit 6	INT: mux IMUX_IO_T[1] bit 2	INT: mux IMUX_IO_T[1] bit 1	IO[0]: !invert O
B2	-	INT: !bipass IO_M[0] = SINGLE_IO_E_N[0]	INT: !pass IO_M[0] ← OMUX_BUF[0]	INT: !pass LONG_V[4] ← OUT_TBUF[0]	INT: mux IMUX_IO_T[1] bit 3	INT: mux IMUX_IO_T[1] bit 5	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_O[0] bit 0
B1	-	INT: !bipass IO_M[8] = SINGLE_W[8]	INT: !bipass IO_M[8] = SINGLE_IO_E_S[0]	INT: !pass LONG_H[4] ← OUT_TBUF[0]	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[0] bit 3	INT: mux IMUX_IO_T[0] bit 1	IO[0]: invert T
B0	-	INT: !bipass IO_M[0] = SINGLE_IO_E_S[0]	INT: !bipass IO_M[0] = DBL_H_E[0]	INT: !pass IO_M[12] ← LONG_H[4]	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[0] bit 2	INT: mux IMUX_IO_T[0] bit 6	-

Tile IO_S

Cells: 1

Switchbox INT

xc5200 IO_S switchbox INT permanent buffers
Destination	Source
IO_M_BUF[0]	IO_M[0]
IO_M_BUF[1]	IO_M[1]
IO_M_BUF[2]	IO_M[2]
IO_M_BUF[3]	IO_M[3]
IO_M_BUF[4]	IO_M[4]
IO_M_BUF[5]	IO_M[5]
IO_M_BUF[6]	IO_M[6]
IO_M_BUF[7]	IO_M[7]
IO_M_BUF[8]	IO_M[8]
IO_M_BUF[9]	IO_M[9]
IO_M_BUF[10]	IO_M[10]
IO_M_BUF[11]	IO_M[11]
IO_M_BUF[12]	IO_M[12]
IO_M_BUF[13]	IO_M[13]
IO_M_BUF[14]	IO_M[14]
IO_M_BUF[15]	IO_M[15]
OMUX_BUF[0]	OMUX[0]
OMUX_BUF[1]	OMUX[1]
OMUX_BUF[2]	OMUX[2]
OMUX_BUF[3]	OMUX[3]

xc5200 IO_S switchbox INT pass gates
Destination	Source	Bit
IO_M[0]	LONG_H[0]	!MAIN[7][10]
IO_M[0]	OMUX_BUF[0]	!MAIN[5][16]
IO_M[1]	LONG_H[1]	MAIN[6][12]
IO_M[1]	OMUX_BUF[1]	!MAIN[5][18]
IO_M[2]	LONG_H[2]	MAIN[6][14]
IO_M[2]	OMUX_BUF[2]	!MAIN[5][12]
IO_M[3]	LONG_H[3]	MAIN[6][17]
IO_M[3]	OMUX_BUF[3]	!MAIN[5][14]
IO_M[4]	LONG_H[4]	MAIN[6][19]
IO_M[4]	OMUX_BUF[1]	!MAIN[5][24]
IO_M[5]	LONG_H[5]	!MAIN[7][21]
IO_M[5]	OMUX_BUF[2]	!MAIN[5][26]
IO_M[6]	LONG_H[6]	!MAIN[7][23]
IO_M[6]	OMUX_BUF[3]	!MAIN[5][20]
IO_M[7]	LONG_H[7]	!MAIN[7][26]
IO_M[7]	OMUX_BUF[0]	!MAIN[5][22]
IO_M[8]	LONG_V[0]	!MAIN[7][11]
IO_M[8]	OMUX_BUF[2]	!MAIN[5][13]
IO_M[9]	LONG_V[1]	!MAIN[7][14]
IO_M[9]	OMUX_BUF[3]	!MAIN[5][15]
IO_M[10]	LONG_V[2]	!MAIN[7][16]
IO_M[10]	OMUX_BUF[0]	!MAIN[5][17]
IO_M[11]	LONG_V[3]	MAIN[6][18]
IO_M[11]	OMUX_BUF[1]	!MAIN[5][19]
IO_M[12]	LONG_V[4]	MAIN[6][20]
IO_M[12]	OMUX_BUF[3]	!MAIN[5][21]
IO_M[13]	LONG_V[5]	MAIN[6][23]
IO_M[13]	OMUX_BUF[0]	!MAIN[5][23]
IO_M[14]	LONG_V[6]	MAIN[6][25]
IO_M[14]	OMUX_BUF[1]	!MAIN[5][25]
IO_M[15]	LONG_V[7]	!MAIN[7][27]
IO_M[15]	OMUX_BUF[2]	!MAIN[5][27]
LONG_H[0]	OUT_TBUF[0]	MAIN[6][10]
LONG_H[1]	OUT_TBUF[1]	MAIN[6][13]
LONG_H[2]	OUT_TBUF[2]	MAIN[6][15]
LONG_H[3]	OUT_TBUF[3]	!MAIN[7][17]
LONG_H[4]	OUT_TBUF[0]	!MAIN[7][19]
LONG_H[5]	OUT_TBUF[1]	!MAIN[7][22]
LONG_H[6]	OUT_TBUF[2]	!MAIN[7][24]
LONG_H[7]	OUT_TBUF[3]	MAIN[6][26]
LONG_V[0]	OUT_TBUF[0]	MAIN[6][11]
LONG_V[1]	OUT_TBUF[1]	!MAIN[7][13]
LONG_V[2]	OUT_TBUF[2]	!MAIN[7][15]
LONG_V[3]	OUT_TBUF[3]	!MAIN[7][18]
LONG_V[4]	OUT_TBUF[0]	!MAIN[7][20]
LONG_V[5]	OUT_TBUF[1]	MAIN[6][22]
LONG_V[6]	OUT_TBUF[2]	MAIN[6][24]
LONG_V[7]	OUT_TBUF[3]	MAIN[6][27]

xc5200 IO_S switchbox INT bidirectional pass gates
Side A	Side B	Bit
IO_M[0]	SINGLE_IO_S_W[0]	!MAIN[10][12]
IO_M[0]	SINGLE_IO_S_E[0]	MAIN[9][12]
IO_M[0]	DBL_V_S[0]	!MAIN[8][13]
IO_M[1]	SINGLE_N[1]	!MAIN[8][15]
IO_M[1]	SINGLE_IO_S_W[1]	!MAIN[10][14]
IO_M[1]	SINGLE_IO_S_E[1]	MAIN[9][14]
IO_M[2]	SINGLE_N[2]	!MAIN[8][17]
IO_M[2]	SINGLE_IO_S_W[2]	!MAIN[10][16]
IO_M[2]	SINGLE_IO_S_E[2]	MAIN[9][16]
IO_M[3]	SINGLE_N[3]	!MAIN[8][19]
IO_M[3]	SINGLE_IO_S_W[3]	!MAIN[10][18]
IO_M[3]	SINGLE_IO_S_E[3]	MAIN[9][18]
IO_M[4]	SINGLE_N[4]	!MAIN[8][21]
IO_M[4]	SINGLE_IO_S_W[4]	!MAIN[10][20]
IO_M[4]	SINGLE_IO_S_E[4]	MAIN[9][20]
IO_M[5]	SINGLE_N[5]	!MAIN[8][23]
IO_M[5]	SINGLE_IO_S_W[5]	!MAIN[10][22]
IO_M[5]	SINGLE_IO_S_E[5]	MAIN[9][22]
IO_M[6]	SINGLE_IO_S_W[6]	!MAIN[10][24]
IO_M[6]	SINGLE_IO_S_E[6]	MAIN[9][24]
IO_M[6]	DBL_V_S[1]	!MAIN[8][25]
IO_M[7]	SINGLE_N[7]	!MAIN[8][27]
IO_M[7]	SINGLE_IO_S_W[7]	!MAIN[10][26]
IO_M[7]	SINGLE_IO_S_E[7]	MAIN[9][26]
IO_M[8]	SINGLE_N[8]	!MAIN[10][13]
IO_M[8]	SINGLE_IO_S_W[1]	!MAIN[8][14]
IO_M[8]	SINGLE_IO_S_E[0]	MAIN[9][13]
IO_M[9]	SINGLE_N[9]	!MAIN[10][15]
IO_M[9]	SINGLE_IO_S_W[2]	!MAIN[8][16]
IO_M[9]	SINGLE_IO_S_E[1]	MAIN[9][15]
IO_M[10]	SINGLE_N[10]	!MAIN[10][17]
IO_M[10]	SINGLE_IO_S_W[3]	!MAIN[8][18]
IO_M[10]	SINGLE_IO_S_E[2]	MAIN[9][17]
IO_M[11]	SINGLE_N[11]	!MAIN[10][19]
IO_M[11]	SINGLE_IO_S_W[4]	!MAIN[8][20]
IO_M[11]	SINGLE_IO_S_E[3]	MAIN[9][19]
IO_M[12]	SINGLE_IO_S_W[5]	!MAIN[8][22]
IO_M[12]	SINGLE_IO_S_E[4]	MAIN[9][21]
IO_M[12]	DBL_V_M[0]	!MAIN[10][21]
IO_M[13]	SINGLE_IO_S_W[6]	!MAIN[8][24]
IO_M[13]	SINGLE_IO_S_E[5]	MAIN[9][23]
IO_M[13]	DBL_V_M[1]	!MAIN[10][23]
IO_M[14]	SINGLE_IO_S_W[7]	!MAIN[8][26]
IO_M[14]	SINGLE_IO_S_E[6]	MAIN[9][25]
IO_M[15]	SINGLE_IO_S_W[0]	!MAIN[8][12]
IO_M[15]	SINGLE_IO_S_E[7]	MAIN[9][27]

xc5200 IO_S switchbox INT muxes OMUX[0]
Bits							Destination
MAIN[1][8]	MAIN[1][13]	MAIN[1][12]	MAIN[1][11]	MAIN[1][10]	MAIN[1][9]	MAIN[1][7]	OMUX[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes OMUX[1]
Bits							Destination
MAIN[0][8]	MAIN[0][11]	MAIN[0][10]	MAIN[0][13]	MAIN[0][12]	MAIN[0][9]	MAIN[0][7]	OMUX[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[14]
1	0	1	1	1	1	0	OUT_IO_I[2]
1	1	0	1	1	0	1	IO_M_BUF[15]
1	1	0	1	1	1	0	OUT_IO_I[3]
1	1	1	0	1	0	1	IO_M_BUF[8]
1	1	1	0	1	1	0	OUT_IO_I[0]
1	1	1	1	0	0	1	IO_M_BUF[9]
1	1	1	1	0	1	0	OUT_IO_I[1]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes OMUX[2]
Bits							Destination
MAIN[3][22]	MAIN[3][27]	MAIN[3][26]	MAIN[3][25]	MAIN[3][24]	MAIN[3][23]	MAIN[3][21]	OMUX[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes OMUX[3]
Bits							Destination
MAIN[2][22]	MAIN[2][27]	MAIN[2][26]	MAIN[2][25]	MAIN[2][24]	MAIN[2][23]	MAIN[2][21]	OMUX[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_TS
Bits							Destination
MAIN[2][6]	MAIN[1][3]	MAIN[1][4]	MAIN[2][5]	MAIN[1][5]	MAIN[1][6]	MAIN[2][4]	IMUX_TS
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	1	0	1	1	IO_M_BUF[6]
0	1	1	1	1	0	1	IO_M_BUF[7]
1	0	1	0	1	1	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[10]
1	1	0	0	1	1	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[11]
1	1	1	0	0	1	1	IO_M_BUF[2]
1	1	1	0	1	0	1	IO_M_BUF[3]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	0	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_GIN
Bits					Destination
MAIN[0][2]	MAIN[0][4]	MAIN[0][3]	MAIN[0][6]	MAIN[0][5]	IMUX_GIN
					Source
0	0	1	1	1	IO_M_BUF[6]
0	1	0	1	1	IO_M_BUF[7]
0	1	1	0	1	IO_M_BUF[12]
0	1	1	1	0	IO_M_BUF[13]
0	1	1	1	1	TIE_0
1	1	1	1	1	GCLK_SE

xc5200 IO_S switchbox INT muxes IMUX_IO_O[0]
Bits							Destination
MAIN[2][18]	MAIN[2][14]	MAIN[2][15]	MAIN[2][16]	MAIN[2][17]	MAIN[2][20]	MAIN[2][19]	IMUX_IO_O[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_O[1]
Bits							Destination
MAIN[3][9]	MAIN[3][13]	MAIN[3][12]	MAIN[3][11]	MAIN[3][10]	MAIN[3][7]	MAIN[3][8]	IMUX_IO_O[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_O[2]
Bits							Destination
MAIN[2][9]	MAIN[2][13]	MAIN[2][12]	MAIN[2][11]	MAIN[2][10]	MAIN[2][7]	MAIN[2][8]	IMUX_IO_O[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_O[3]
Bits							Destination
MAIN[3][20]	MAIN[3][14]	MAIN[3][15]	MAIN[3][16]	MAIN[3][17]	MAIN[3][19]	MAIN[3][18]	IMUX_IO_O[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_O_SN[0]
Bits				Destination
MAIN[9][7]	MAIN[10][7]	MAIN[9][6]	MAIN[8][6]	IMUX_IO_O_SN[0]
				Source
0	0	0	1	OMUX_BUF_S[0]
0	0	1	0	~OMUX_BUF_S[0]
0	1	0	0	IMUX_IO_O[0]
1	0	0	0	~IMUX_IO_O[0]

xc5200 IO_S switchbox INT muxes IMUX_IO_O_SN[1]
Bits				Destination
MAIN[8][7]	MAIN[7][7]	MAIN[5][6]	MAIN[5][4]	IMUX_IO_O_SN[1]
				Source
0	0	0	1	OMUX_BUF_S[1]
0	0	1	0	~OMUX_BUF_S[1]
0	1	0	0	IMUX_IO_O[1]
1	0	0	0	~IMUX_IO_O[1]

xc5200 IO_S switchbox INT muxes IMUX_IO_O_SN[2]
Bits				Destination
MAIN[7][6]	MAIN[7][5]	MAIN[6][5]	MAIN[6][4]	IMUX_IO_O_SN[2]
				Source
0	0	0	1	OMUX_BUF_S[2]
0	0	1	0	~OMUX_BUF_S[2]
0	1	0	0	IMUX_IO_O[2]
1	0	0	0	~IMUX_IO_O[2]

xc5200 IO_S switchbox INT muxes IMUX_IO_O_SN[3]
Bits				Destination
MAIN[8][4]	MAIN[9][4]	MAIN[9][5]	MAIN[8][5]	IMUX_IO_O_SN[3]
				Source
0	0	0	1	OMUX_BUF_S[3]
0	0	1	0	~OMUX_BUF_S[3]
0	1	0	0	IMUX_IO_O[3]
1	0	0	0	~IMUX_IO_O[3]

xc5200 IO_S switchbox INT muxes IMUX_IO_T[0]
Bits							Destination
MAIN[1][21]	MAIN[1][27]	MAIN[1][26]	MAIN[1][25]	MAIN[1][24]	MAIN[1][22]	MAIN[1][23]	IMUX_IO_T[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_S[1]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[9]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_T[1]
Bits							Destination
MAIN[0][21]	MAIN[0][27]	MAIN[0][26]	MAIN[0][25]	MAIN[0][24]	MAIN[0][22]	MAIN[0][23]	IMUX_IO_T[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[10]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[11]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[12]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	OMUX_BUF_S[2]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_T[2]
Bits							Destination
MAIN[1][20]	MAIN[1][14]	MAIN[1][15]	MAIN[1][16]	MAIN[1][17]	MAIN[1][19]	MAIN[1][18]	IMUX_IO_T[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_S[3]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_IO_T[3]
Bits							Destination
MAIN[0][20]	MAIN[0][14]	MAIN[0][15]	MAIN[0][16]	MAIN[0][17]	MAIN[0][19]	MAIN[0][18]	IMUX_IO_T[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[14]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[15]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[8]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	OMUX_BUF_S[0]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_S switchbox INT muxes IMUX_BOT_CIN
Bits	Destination
MAIN[10][25]	IMUX_BOT_CIN
	Source
0	IO_M[14]
1	off

Switchbox BUFR

xc5200 IO_S switchbox BUFR permanent buffers
Destination	Source
GCLK_S	IMUX_GIN

Bels TBUF

xc5200 IO_S bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
I	in	OMUX_BUF[0]	OMUX_BUF[1]	OMUX_BUF[2]	OMUX_BUF[3]
T	in	IMUX_TS	IMUX_TS	IMUX_TS	IMUX_TS
O	out	OUT_TBUF[0]	OUT_TBUF[1]	OUT_TBUF[2]	OUT_TBUF[3]

xc5200 IO_S bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
T_ENABLE	!MAIN[7][12]	MAIN[6][16]	MAIN[6][21]	!MAIN[7][25]

Bels IO

xc5200 IO_S bel IO pins
Pin	Direction	IO[0]	IO[1]	IO[2]	IO[3]
O	in	IMUX_IO_O_SN[0]	IMUX_IO_O_SN[1]	IMUX_IO_O_SN[2]	IMUX_IO_O_SN[3]
T	in	IMUX_IO_T[0] invert by MAIN[5][11]	IMUX_IO_T[1] invert by MAIN[5][8]	IMUX_IO_T[2] invert by MAIN[6][6]	IMUX_IO_T[3] invert by MAIN[10][6]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]

xc5200 IO_S bel IO attribute bits
Attribute	IO[0]	IO[1]	IO[2]	IO[3]
SLEW	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
DELAY_ENABLE	!MAIN[5][9]	!MAIN[5][5]	!MAIN[7][4]	!MAIN[10][4]
INV_I	!MAIN[5][10]	!MAIN[5][7]	!MAIN[6][7]	!MAIN[10][5]

xc5200 IO_S enum IO_SLEW
IO[0].SLEW	MAIN[1][1]
IO[1].SLEW	MAIN[7][9]
IO[2].SLEW	MAIN[9][9]
IO[3].SLEW	MAIN[9][8]
FAST	1
SLOW	0

xc5200 IO_S enum IO_PULL
IO[0].PULL	MAIN[0][1]	MAIN[1][2]
IO[1].PULL	MAIN[7][8]	MAIN[6][8]
IO[2].PULL	MAIN[8][9]	MAIN[8][8]
IO[3].PULL	MAIN[10][11]	MAIN[10][8]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

Bels SCANTEST

xc5200 IO_S bel SCANTEST pins
Pin	Direction	SCANTEST

xc5200 IO_S bel SCANTEST attribute bits
Attribute	SCANTEST
OUT	[enum: SCANTEST_OUT]

xc5200 IO_S enum SCANTEST_OUT
SCANTEST.OUT	MAIN[3][4]	MAIN[3][5]	MAIN[3][6]
XI	0	0	1
YI	0	0	0
ZI	0	1	1
VI	0	1	0
SCANPASS	1	1	1

Bels CIN

xc5200 IO_S bel CIN pins
Pin	Direction	CIN
IN	in	IMUX_BOT_CIN

Bel wires

xc5200 IO_S bel wires
Wire	Pins
OMUX_BUF[0]	TBUF[0].I
OMUX_BUF[1]	TBUF[1].I
OMUX_BUF[2]	TBUF[2].I
OMUX_BUF[3]	TBUF[3].I
OUT_TBUF[0]	TBUF[0].O
OUT_TBUF[1]	TBUF[1].O
OUT_TBUF[2]	TBUF[2].O
OUT_TBUF[3]	TBUF[3].O
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
IMUX_TS	TBUF[0].T, TBUF[1].T, TBUF[2].T, TBUF[3].T
IMUX_IO_O_SN[0]	IO[0].O
IMUX_IO_O_SN[1]	IO[1].O
IMUX_IO_O_SN[2]	IO[2].O
IMUX_IO_O_SN[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T
IMUX_BOT_CIN	CIN.IN

Bitstream

xc5200 IO_S rect MAIN
Bit	Frame
Bit	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B27	-	-	INT: bipass IO_M[15] = SINGLE_IO_S_E[7]	INT: !bipass IO_M[7] = SINGLE_N[7]	INT: !pass IO_M[15] ← LONG_V[7]	INT: pass LONG_V[7] ← OUT_TBUF[3]	INT: !pass IO_M[15] ← OMUX_BUF[2]	-	INT: mux OMUX[2] bit 5	INT: mux OMUX[3] bit 5	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[1] bit 5
B26	-	INT: !bipass IO_M[7] = SINGLE_IO_S_W[7]	INT: bipass IO_M[7] = SINGLE_IO_S_E[7]	INT: !bipass IO_M[14] = SINGLE_IO_S_W[7]	INT: !pass IO_M[7] ← LONG_H[7]	INT: pass LONG_H[7] ← OUT_TBUF[3]	INT: !pass IO_M[5] ← OMUX_BUF[2]	-	INT: mux OMUX[2] bit 4	INT: mux OMUX[3] bit 4	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[1] bit 4
B25	-	INT: mux IMUX_BOT_CIN bit 0	INT: bipass IO_M[14] = SINGLE_IO_S_E[6]	INT: !bipass IO_M[6] = DBL_V_S[1]	TBUF[3]: ! T_ENABLE	INT: pass IO_M[14] ← LONG_V[6]	INT: !pass IO_M[14] ← OMUX_BUF[1]	-	INT: mux OMUX[2] bit 3	INT: mux OMUX[3] bit 3	INT: mux IMUX_IO_T[0] bit 3	INT: mux IMUX_IO_T[1] bit 3
B24	-	INT: !bipass IO_M[6] = SINGLE_IO_S_W[6]	INT: bipass IO_M[6] = SINGLE_IO_S_E[6]	INT: !bipass IO_M[13] = SINGLE_IO_S_W[6]	INT: !pass LONG_H[6] ← OUT_TBUF[2]	INT: pass LONG_V[6] ← OUT_TBUF[2]	INT: !pass IO_M[4] ← OMUX_BUF[1]	-	INT: mux OMUX[2] bit 2	INT: mux OMUX[3] bit 2	INT: mux IMUX_IO_T[0] bit 2	INT: mux IMUX_IO_T[1] bit 2
B23	-	INT: !bipass IO_M[13] = DBL_V_M[1]	INT: bipass IO_M[13] = SINGLE_IO_S_E[5]	INT: !bipass IO_M[5] = SINGLE_N[5]	INT: !pass IO_M[6] ← LONG_H[6]	INT: pass IO_M[13] ← LONG_V[5]	INT: !pass IO_M[13] ← OMUX_BUF[0]	-	INT: mux OMUX[2] bit 1	INT: mux OMUX[3] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[1] bit 0
B22	-	INT: !bipass IO_M[5] = SINGLE_IO_S_W[5]	INT: bipass IO_M[5] = SINGLE_IO_S_E[5]	INT: !bipass IO_M[12] = SINGLE_IO_S_W[5]	INT: !pass LONG_H[5] ← OUT_TBUF[1]	INT: pass LONG_V[5] ← OUT_TBUF[1]	INT: !pass IO_M[7] ← OMUX_BUF[0]	-	INT: mux OMUX[2] bit 6	INT: mux OMUX[3] bit 6	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[1] bit 1
B21	-	INT: !bipass IO_M[12] = DBL_V_M[0]	INT: bipass IO_M[12] = SINGLE_IO_S_E[4]	INT: !bipass IO_M[4] = SINGLE_N[4]	INT: !pass IO_M[5] ← LONG_H[5]	TBUF[2]: T_ENABLE	INT: !pass IO_M[12] ← OMUX_BUF[3]	-	INT: mux OMUX[2] bit 0	INT: mux OMUX[3] bit 0	INT: mux IMUX_IO_T[0] bit 6	INT: mux IMUX_IO_T[1] bit 6
B20	-	INT: !bipass IO_M[4] = SINGLE_IO_S_W[4]	INT: bipass IO_M[4] = SINGLE_IO_S_E[4]	INT: !bipass IO_M[11] = SINGLE_IO_S_W[4]	INT: !pass LONG_V[4] ← OUT_TBUF[0]	INT: pass IO_M[12] ← LONG_V[4]	INT: !pass IO_M[6] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_T[2] bit 6	INT: mux IMUX_IO_T[3] bit 6
B19	-	INT: !bipass IO_M[11] = SINGLE_N[11]	INT: bipass IO_M[11] = SINGLE_IO_S_E[3]	INT: !bipass IO_M[3] = SINGLE_N[3]	INT: !pass LONG_H[4] ← OUT_TBUF[0]	INT: pass IO_M[4] ← LONG_H[4]	INT: !pass IO_M[11] ← OMUX_BUF[1]	-	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[0] bit 0	INT: mux IMUX_IO_T[2] bit 1	INT: mux IMUX_IO_T[3] bit 1
B18	-	INT: !bipass IO_M[3] = SINGLE_IO_S_W[3]	INT: bipass IO_M[3] = SINGLE_IO_S_E[3]	INT: !bipass IO_M[10] = SINGLE_IO_S_W[3]	INT: !pass LONG_V[3] ← OUT_TBUF[3]	INT: pass IO_M[11] ← LONG_V[3]	INT: !pass IO_M[1] ← OMUX_BUF[1]	-	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[0] bit 6	INT: mux IMUX_IO_T[2] bit 0	INT: mux IMUX_IO_T[3] bit 0
B17	-	INT: !bipass IO_M[10] = SINGLE_N[10]	INT: bipass IO_M[10] = SINGLE_IO_S_E[2]	INT: !bipass IO_M[2] = SINGLE_N[2]	INT: !pass LONG_H[3] ← OUT_TBUF[3]	INT: pass IO_M[3] ← LONG_H[3]	INT: !pass IO_M[10] ← OMUX_BUF[0]	-	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[3] bit 2
B16	-	INT: !bipass IO_M[2] = SINGLE_IO_S_W[2]	INT: bipass IO_M[2] = SINGLE_IO_S_E[2]	INT: !bipass IO_M[9] = SINGLE_IO_S_W[2]	INT: !pass IO_M[10] ← LONG_V[2]	TBUF[1]: T_ENABLE	INT: !pass IO_M[0] ← OMUX_BUF[0]	-	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_T[2] bit 3	INT: mux IMUX_IO_T[3] bit 3
B15	-	INT: !bipass IO_M[9] = SINGLE_N[9]	INT: bipass IO_M[9] = SINGLE_IO_S_E[1]	INT: !bipass IO_M[1] = SINGLE_N[1]	INT: !pass LONG_V[2] ← OUT_TBUF[2]	INT: pass LONG_H[2] ← OUT_TBUF[2]	INT: !pass IO_M[9] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[0] bit 4	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[3] bit 4
B14	-	INT: !bipass IO_M[1] = SINGLE_IO_S_W[1]	INT: bipass IO_M[1] = SINGLE_IO_S_E[1]	INT: !bipass IO_M[8] = SINGLE_IO_S_W[1]	INT: !pass IO_M[9] ← LONG_V[1]	INT: pass IO_M[2] ← LONG_H[2]	INT: !pass IO_M[3] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[3] bit 5
B13	-	INT: !bipass IO_M[8] = SINGLE_N[8]	INT: bipass IO_M[8] = SINGLE_IO_S_E[0]	INT: !bipass IO_M[0] = DBL_V_S[0]	INT: !pass LONG_V[1] ← OUT_TBUF[1]	INT: pass LONG_H[1] ← OUT_TBUF[1]	INT: !pass IO_M[8] ← OMUX_BUF[2]	-	INT: mux IMUX_IO_O[1] bit 5	INT: mux IMUX_IO_O[2] bit 5	INT: mux OMUX[0] bit 5	INT: mux OMUX[1] bit 3
B12	-	INT: !bipass IO_M[0] = SINGLE_IO_S_W[0]	INT: bipass IO_M[0] = SINGLE_IO_S_E[0]	INT: !bipass IO_M[15] = SINGLE_IO_S_W[0]	TBUF[0]: ! T_ENABLE	INT: pass IO_M[1] ← LONG_H[1]	INT: !pass IO_M[2] ← OMUX_BUF[2]	-	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[2] bit 4	INT: mux OMUX[0] bit 4	INT: mux OMUX[1] bit 2
B11	-	IO[3]: PULL bit 1	-	-	INT: !pass IO_M[8] ← LONG_V[0]	INT: pass LONG_V[0] ← OUT_TBUF[0]	IO[0]: invert T	-	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[2] bit 3	INT: mux OMUX[0] bit 3	INT: mux OMUX[1] bit 5
B10	-	-	-	-	INT: !pass IO_M[0] ← LONG_H[0]	INT: pass LONG_H[0] ← OUT_TBUF[0]	IO[0]: ! INV_I	-	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[2] bit 2	INT: mux OMUX[0] bit 2	INT: mux OMUX[1] bit 4
B9	-	-	IO[2]: SLEW bit 0	IO[2]: PULL bit 1	IO[1]: SLEW bit 0	-	IO[0]: ! DELAY_ENABLE	-	INT: mux IMUX_IO_O[1] bit 6	INT: mux IMUX_IO_O[2] bit 6	INT: mux OMUX[0] bit 1	INT: mux OMUX[1] bit 1
B8	-	IO[3]: PULL bit 0	IO[3]: SLEW bit 0	IO[2]: PULL bit 0	IO[1]: PULL bit 1	IO[1]: PULL bit 0	IO[1]: invert T	-	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[2] bit 0	INT: mux OMUX[0] bit 6	INT: mux OMUX[1] bit 6
B7	-	INT: mux IMUX_IO_O_SN[0] bit 2	INT: mux IMUX_IO_O_SN[0] bit 3	INT: mux IMUX_IO_O_SN[1] bit 3	INT: mux IMUX_IO_O_SN[1] bit 2	IO[2]: ! INV_I	IO[1]: ! INV_I	-	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[2] bit 1	INT: mux OMUX[0] bit 0	INT: mux OMUX[1] bit 0
B6	-	IO[3]: invert T	INT: mux IMUX_IO_O_SN[0] bit 1	INT: mux IMUX_IO_O_SN[0] bit 0	INT: mux IMUX_IO_O_SN[2] bit 3	IO[2]: invert T	INT: mux IMUX_IO_O_SN[1] bit 1	-	SCANTEST: OUT bit 0	INT: mux IMUX_TS bit 6	INT: mux IMUX_TS bit 1	INT: mux IMUX_GIN bit 1
B5	-	IO[3]: ! INV_I	INT: mux IMUX_IO_O_SN[3] bit 1	INT: mux IMUX_IO_O_SN[3] bit 0	INT: mux IMUX_IO_O_SN[2] bit 2	INT: mux IMUX_IO_O_SN[2] bit 1	IO[1]: ! DELAY_ENABLE	-	SCANTEST: OUT bit 1	INT: mux IMUX_TS bit 3	INT: mux IMUX_TS bit 2	INT: mux IMUX_GIN bit 0
B4	-	IO[3]: ! DELAY_ENABLE	INT: mux IMUX_IO_O_SN[3] bit 2	INT: mux IMUX_IO_O_SN[3] bit 3	IO[2]: ! DELAY_ENABLE	INT: mux IMUX_IO_O_SN[2] bit 0	INT: mux IMUX_IO_O_SN[1] bit 0	-	SCANTEST: OUT bit 2	INT: mux IMUX_TS bit 0	INT: mux IMUX_TS bit 4	INT: mux IMUX_GIN bit 3
B3	-	-	-	-	-	-	-	-	-	-	INT: mux IMUX_TS bit 5	INT: mux IMUX_GIN bit 2
B2	-	-	-	-	-	-	-	-	-	-	IO[0]: PULL bit 0	INT: mux IMUX_GIN bit 4
B1	-	-	-	-	-	-	-	-	-	-	IO[0]: SLEW bit 0	IO[0]: PULL bit 1
B0	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_N

Cells: 1

Switchbox INT

xc5200 IO_N switchbox INT permanent buffers
Destination	Source
IO_M_BUF[0]	IO_M[0]
IO_M_BUF[1]	IO_M[1]
IO_M_BUF[2]	IO_M[2]
IO_M_BUF[3]	IO_M[3]
IO_M_BUF[4]	IO_M[4]
IO_M_BUF[5]	IO_M[5]
IO_M_BUF[6]	IO_M[6]
IO_M_BUF[7]	IO_M[7]
IO_M_BUF[8]	IO_M[8]
IO_M_BUF[9]	IO_M[9]
IO_M_BUF[10]	IO_M[10]
IO_M_BUF[11]	IO_M[11]
IO_M_BUF[12]	IO_M[12]
IO_M_BUF[13]	IO_M[13]
IO_M_BUF[14]	IO_M[14]
IO_M_BUF[15]	IO_M[15]
OMUX_BUF[0]	OMUX[0]
OMUX_BUF[1]	OMUX[1]
OMUX_BUF[2]	OMUX[2]
OMUX_BUF[3]	OMUX[3]

xc5200 IO_N switchbox INT pass gates
Destination	Source	Bit
IO_M[0]	LONG_H[0]	!MAIN[7][17]
IO_M[0]	OMUX_BUF[0]	!MAIN[5][11]
IO_M[1]	LONG_H[1]	MAIN[6][15]
IO_M[1]	OMUX_BUF[1]	!MAIN[5][9]
IO_M[2]	LONG_H[2]	MAIN[6][13]
IO_M[2]	OMUX_BUF[2]	!MAIN[5][15]
IO_M[3]	LONG_H[3]	MAIN[6][10]
IO_M[3]	OMUX_BUF[3]	!MAIN[5][13]
IO_M[4]	LONG_H[4]	MAIN[6][8]
IO_M[4]	OMUX_BUF[1]	!MAIN[5][3]
IO_M[5]	LONG_H[5]	!MAIN[7][6]
IO_M[5]	OMUX_BUF[2]	!MAIN[5][1]
IO_M[6]	LONG_H[6]	!MAIN[7][4]
IO_M[6]	OMUX_BUF[3]	!MAIN[5][7]
IO_M[7]	LONG_H[7]	!MAIN[7][1]
IO_M[7]	OMUX_BUF[0]	!MAIN[5][5]
IO_M[8]	LONG_V[0]	!MAIN[7][16]
IO_M[8]	OMUX_BUF[2]	!MAIN[5][14]
IO_M[9]	LONG_V[1]	!MAIN[7][13]
IO_M[9]	OMUX_BUF[3]	!MAIN[5][12]
IO_M[10]	LONG_V[2]	!MAIN[7][11]
IO_M[10]	OMUX_BUF[0]	!MAIN[5][10]
IO_M[11]	LONG_V[3]	MAIN[6][9]
IO_M[11]	OMUX_BUF[1]	!MAIN[5][8]
IO_M[12]	LONG_V[4]	MAIN[6][7]
IO_M[12]	OMUX_BUF[3]	!MAIN[5][6]
IO_M[13]	LONG_V[5]	MAIN[6][4]
IO_M[13]	OMUX_BUF[0]	!MAIN[5][4]
IO_M[14]	LONG_V[6]	MAIN[6][2]
IO_M[14]	OMUX_BUF[1]	!MAIN[5][2]
IO_M[14]	OUT_TOP_COUT	!MAIN[10][2]
IO_M[15]	LONG_V[7]	!MAIN[7][0]
IO_M[15]	OMUX_BUF[2]	!MAIN[5][0]
LONG_H[0]	OUT_TBUF[0]	MAIN[6][17]
LONG_H[1]	OUT_TBUF[1]	MAIN[6][14]
LONG_H[2]	OUT_TBUF[2]	MAIN[6][12]
LONG_H[3]	OUT_TBUF[3]	!MAIN[7][10]
LONG_H[4]	OUT_TBUF[0]	!MAIN[7][8]
LONG_H[5]	OUT_TBUF[1]	!MAIN[7][5]
LONG_H[6]	OUT_TBUF[2]	!MAIN[7][3]
LONG_H[7]	OUT_TBUF[3]	MAIN[6][1]
LONG_V[0]	OUT_TBUF[0]	MAIN[6][16]
LONG_V[1]	OUT_TBUF[1]	!MAIN[7][14]
LONG_V[2]	OUT_TBUF[2]	!MAIN[7][12]
LONG_V[3]	OUT_TBUF[3]	!MAIN[7][9]
LONG_V[4]	OUT_TBUF[0]	!MAIN[7][7]
LONG_V[5]	OUT_TBUF[1]	MAIN[6][5]
LONG_V[6]	OUT_TBUF[2]	MAIN[6][3]
LONG_V[7]	OUT_TBUF[3]	MAIN[6][0]

xc5200 IO_N switchbox INT bidirectional pass gates
Side A	Side B	Bit
IO_M[0]	SINGLE_IO_N_W[0]	!MAIN[10][15]
IO_M[0]	SINGLE_IO_N_E[0]	MAIN[9][15]
IO_M[0]	DBL_V_N[0]	!MAIN[8][14]
IO_M[1]	SINGLE_S[1]	!MAIN[8][12]
IO_M[1]	SINGLE_IO_N_W[1]	!MAIN[10][13]
IO_M[1]	SINGLE_IO_N_E[1]	MAIN[9][13]
IO_M[2]	SINGLE_S[2]	!MAIN[8][10]
IO_M[2]	SINGLE_IO_N_W[2]	!MAIN[10][11]
IO_M[2]	SINGLE_IO_N_E[2]	MAIN[9][11]
IO_M[3]	SINGLE_S[3]	!MAIN[8][8]
IO_M[3]	SINGLE_IO_N_W[3]	!MAIN[10][9]
IO_M[3]	SINGLE_IO_N_E[3]	MAIN[9][9]
IO_M[4]	SINGLE_S[4]	!MAIN[8][6]
IO_M[4]	SINGLE_IO_N_W[4]	!MAIN[10][7]
IO_M[4]	SINGLE_IO_N_E[4]	MAIN[9][7]
IO_M[5]	SINGLE_S[5]	!MAIN[8][4]
IO_M[5]	SINGLE_IO_N_W[5]	!MAIN[10][5]
IO_M[5]	SINGLE_IO_N_E[5]	MAIN[9][5]
IO_M[6]	SINGLE_IO_N_W[6]	!MAIN[10][3]
IO_M[6]	SINGLE_IO_N_E[6]	MAIN[9][3]
IO_M[6]	DBL_V_N[1]	!MAIN[8][2]
IO_M[7]	SINGLE_S[7]	!MAIN[8][0]
IO_M[7]	SINGLE_IO_N_W[7]	!MAIN[10][1]
IO_M[7]	SINGLE_IO_N_E[7]	MAIN[9][1]
IO_M[8]	SINGLE_S[8]	!MAIN[10][14]
IO_M[8]	SINGLE_IO_N_W[1]	!MAIN[8][13]
IO_M[8]	SINGLE_IO_N_E[0]	MAIN[9][14]
IO_M[9]	SINGLE_S[9]	!MAIN[10][12]
IO_M[9]	SINGLE_IO_N_W[2]	!MAIN[8][11]
IO_M[9]	SINGLE_IO_N_E[1]	MAIN[9][12]
IO_M[10]	SINGLE_S[10]	!MAIN[10][10]
IO_M[10]	SINGLE_IO_N_W[3]	!MAIN[8][9]
IO_M[10]	SINGLE_IO_N_E[2]	MAIN[9][10]
IO_M[11]	SINGLE_S[11]	!MAIN[10][8]
IO_M[11]	SINGLE_IO_N_W[4]	!MAIN[8][7]
IO_M[11]	SINGLE_IO_N_E[3]	MAIN[9][8]
IO_M[12]	SINGLE_IO_N_W[5]	!MAIN[8][5]
IO_M[12]	SINGLE_IO_N_E[4]	MAIN[9][6]
IO_M[12]	DBL_V_M[0]	!MAIN[10][6]
IO_M[13]	SINGLE_IO_N_W[6]	!MAIN[8][3]
IO_M[13]	SINGLE_IO_N_E[5]	MAIN[9][4]
IO_M[13]	DBL_V_M[1]	!MAIN[10][4]
IO_M[14]	SINGLE_IO_N_W[7]	!MAIN[8][1]
IO_M[14]	SINGLE_IO_N_E[6]	MAIN[9][2]
IO_M[15]	SINGLE_IO_N_W[0]	!MAIN[8][15]
IO_M[15]	SINGLE_IO_N_E[7]	MAIN[9][0]

xc5200 IO_N switchbox INT muxes OMUX[0]
Bits							Destination
MAIN[1][19]	MAIN[1][14]	MAIN[1][15]	MAIN[1][16]	MAIN[1][17]	MAIN[1][18]	MAIN[1][20]	OMUX[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes OMUX[1]
Bits							Destination
MAIN[0][19]	MAIN[0][16]	MAIN[0][17]	MAIN[0][14]	MAIN[0][15]	MAIN[0][18]	MAIN[0][20]	OMUX[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[14]
1	0	1	1	1	1	0	OUT_IO_I[2]
1	1	0	1	1	0	1	IO_M_BUF[15]
1	1	0	1	1	1	0	OUT_IO_I[3]
1	1	1	0	1	0	1	IO_M_BUF[8]
1	1	1	0	1	1	0	OUT_IO_I[0]
1	1	1	1	0	0	1	IO_M_BUF[9]
1	1	1	1	0	1	0	OUT_IO_I[1]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes OMUX[2]
Bits							Destination
MAIN[3][5]	MAIN[3][0]	MAIN[3][1]	MAIN[3][2]	MAIN[3][3]	MAIN[3][4]	MAIN[3][6]	OMUX[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes OMUX[3]
Bits							Destination
MAIN[2][5]	MAIN[2][0]	MAIN[2][1]	MAIN[2][2]	MAIN[2][3]	MAIN[2][4]	MAIN[2][6]	OMUX[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[12]
1	0	1	1	1	1	0	OUT_IO_I[0]
1	1	0	1	1	0	1	IO_M_BUF[13]
1	1	0	1	1	1	0	OUT_IO_I[1]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	OUT_IO_I[2]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	OUT_IO_I[3]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_TS
Bits							Destination
MAIN[2][21]	MAIN[1][24]	MAIN[1][23]	MAIN[2][22]	MAIN[1][22]	MAIN[1][21]	MAIN[2][23]	IMUX_TS
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	1	0	1	1	IO_M_BUF[6]
0	1	1	1	1	0	1	IO_M_BUF[7]
1	0	1	0	1	1	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[10]
1	1	0	0	1	1	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[11]
1	1	1	0	0	1	1	IO_M_BUF[2]
1	1	1	0	1	0	1	IO_M_BUF[3]
1	1	1	1	0	1	0	IO_M_BUF[14]
1	1	1	1	1	0	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_GIN
Bits					Destination
MAIN[0][25]	MAIN[0][23]	MAIN[0][24]	MAIN[0][21]	MAIN[0][22]	IMUX_GIN
					Source
0	0	1	1	1	IO_M_BUF[6]
0	1	0	1	1	IO_M_BUF[7]
0	1	1	0	1	IO_M_BUF[12]
0	1	1	1	0	IO_M_BUF[13]
0	1	1	1	1	TIE_0
1	1	1	1	1	GCLK_NW

xc5200 IO_N switchbox INT muxes IMUX_IO_O[0]
Bits							Destination
MAIN[2][9]	MAIN[2][13]	MAIN[2][12]	MAIN[2][11]	MAIN[2][10]	MAIN[2][7]	MAIN[2][8]	IMUX_IO_O[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[4]
0	1	0	1	1	1	1	IO_M_BUF[5]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_O[1]
Bits							Destination
MAIN[3][18]	MAIN[3][14]	MAIN[3][15]	MAIN[3][16]	MAIN[3][17]	MAIN[3][20]	MAIN[3][19]	IMUX_IO_O[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[6]
0	1	1	1	0	1	1	IO_M_BUF[7]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_O[2]
Bits							Destination
MAIN[2][18]	MAIN[2][14]	MAIN[2][15]	MAIN[2][16]	MAIN[2][17]	MAIN[2][20]	MAIN[2][19]	IMUX_IO_O[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[10]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[11]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_O[3]
Bits							Destination
MAIN[3][7]	MAIN[3][13]	MAIN[3][12]	MAIN[3][11]	MAIN[3][10]	MAIN[3][8]	MAIN[3][9]	IMUX_IO_O[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[2]
0	1	0	1	1	1	1	IO_M_BUF[3]
0	1	1	0	1	1	1	IO_M_BUF[4]
0	1	1	1	0	1	1	IO_M_BUF[5]
1	0	1	1	1	0	1	IO_M_BUF[8]
1	0	1	1	1	1	0	IO_M_BUF[12]
1	1	0	1	1	0	1	IO_M_BUF[9]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[14]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[15]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_O_SN[0]
Bits				Destination
MAIN[9][20]	MAIN[10][20]	MAIN[9][21]	MAIN[8][21]	IMUX_IO_O_SN[0]
				Source
0	0	0	1	OMUX_BUF_N[0]
0	0	1	0	~OMUX_BUF_N[0]
0	1	0	0	IMUX_IO_O[0]
1	0	0	0	~IMUX_IO_O[0]

xc5200 IO_N switchbox INT muxes IMUX_IO_O_SN[1]
Bits				Destination
MAIN[8][20]	MAIN[7][20]	MAIN[5][21]	MAIN[5][23]	IMUX_IO_O_SN[1]
				Source
0	0	0	1	OMUX_BUF_N[1]
0	0	1	0	~OMUX_BUF_N[1]
0	1	0	0	IMUX_IO_O[1]
1	0	0	0	~IMUX_IO_O[1]

xc5200 IO_N switchbox INT muxes IMUX_IO_O_SN[2]
Bits				Destination
MAIN[7][21]	MAIN[7][22]	MAIN[6][22]	MAIN[6][23]	IMUX_IO_O_SN[2]
				Source
0	0	0	1	OMUX_BUF_N[2]
0	0	1	0	~OMUX_BUF_N[2]
0	1	0	0	IMUX_IO_O[2]
1	0	0	0	~IMUX_IO_O[2]

xc5200 IO_N switchbox INT muxes IMUX_IO_O_SN[3]
Bits				Destination
MAIN[8][23]	MAIN[9][23]	MAIN[9][22]	MAIN[8][22]	IMUX_IO_O_SN[3]
				Source
0	0	0	1	OMUX_BUF_N[3]
0	0	1	0	~OMUX_BUF_N[3]
0	1	0	0	IMUX_IO_O[3]
1	0	0	0	~IMUX_IO_O[3]

xc5200 IO_N switchbox INT muxes IMUX_IO_T[0]
Bits							Destination
MAIN[1][6]	MAIN[1][0]	MAIN[1][1]	MAIN[1][2]	MAIN[1][3]	MAIN[1][5]	MAIN[1][4]	IMUX_IO_T[0]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_N[1]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[9]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[10]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[11]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_T[1]
Bits							Destination
MAIN[0][6]	MAIN[0][0]	MAIN[0][1]	MAIN[0][2]	MAIN[0][3]	MAIN[0][5]	MAIN[0][4]	IMUX_IO_T[1]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[10]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[11]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[12]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	OMUX_BUF_N[2]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_T[2]
Bits							Destination
MAIN[1][7]	MAIN[1][13]	MAIN[1][12]	MAIN[1][11]	MAIN[1][10]	MAIN[1][8]	MAIN[1][9]	IMUX_IO_T[2]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	OMUX_BUF_N[3]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[13]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[14]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	IO_M_BUF[15]
1	1	1	1	1	1	1	TIE_0

xc5200 IO_N switchbox INT muxes IMUX_IO_T[3]
Bits							Destination
MAIN[0][7]	MAIN[0][13]	MAIN[0][12]	MAIN[0][11]	MAIN[0][10]	MAIN[0][8]	MAIN[0][9]	IMUX_IO_T[3]
							Source
0	0	1	1	1	1	1	IO_M_BUF[0]
0	1	0	1	1	1	1	IO_M_BUF[1]
0	1	1	0	1	1	1	IO_M_BUF[2]
0	1	1	1	0	1	1	IO_M_BUF[3]
1	0	1	1	1	0	1	IO_M_BUF[4]
1	0	1	1	1	1	0	IO_M_BUF[14]
1	1	0	1	1	0	1	IO_M_BUF[5]
1	1	0	1	1	1	0	IO_M_BUF[15]
1	1	1	0	1	0	1	IO_M_BUF[6]
1	1	1	0	1	1	0	IO_M_BUF[8]
1	1	1	1	0	0	1	IO_M_BUF[7]
1	1	1	1	0	1	0	OMUX_BUF_N[0]
1	1	1	1	1	1	1	TIE_0

Switchbox BUFR

xc5200 IO_N switchbox BUFR permanent buffers
Destination	Source
GCLK_N	IMUX_GIN

Bels TBUF

xc5200 IO_N bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
I	in	OMUX_BUF[0]	OMUX_BUF[1]	OMUX_BUF[2]	OMUX_BUF[3]
T	in	IMUX_TS	IMUX_TS	IMUX_TS	IMUX_TS
O	out	OUT_TBUF[0]	OUT_TBUF[1]	OUT_TBUF[2]	OUT_TBUF[3]

xc5200 IO_N bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]	TBUF[2]	TBUF[3]
T_ENABLE	!MAIN[7][15]	MAIN[6][11]	MAIN[6][6]	!MAIN[7][2]

Bels IO

xc5200 IO_N bel IO pins
Pin	Direction	IO[0]	IO[1]	IO[2]	IO[3]
O	in	IMUX_IO_O_SN[0]	IMUX_IO_O_SN[1]	IMUX_IO_O_SN[2]	IMUX_IO_O_SN[3]
T	in	IMUX_IO_T[0] invert by MAIN[5][16]	IMUX_IO_T[1] invert by MAIN[5][19]	IMUX_IO_T[2] invert by MAIN[6][21]	IMUX_IO_T[3] invert by MAIN[10][21]
I	out	OUT_IO_I[0]	OUT_IO_I[1]	OUT_IO_I[2]	OUT_IO_I[3]

xc5200 IO_N bel IO attribute bits
Attribute	IO[0]	IO[1]	IO[2]	IO[3]
SLEW	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]	[enum: IO_SLEW]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
DELAY_ENABLE	!MAIN[5][18]	!MAIN[5][22]	!MAIN[7][23]	!MAIN[10][23]
INV_I	!MAIN[5][17]	!MAIN[5][20]	!MAIN[6][20]	!MAIN[10][22]

xc5200 IO_N enum IO_SLEW
IO[0].SLEW	MAIN[1][26]
IO[1].SLEW	MAIN[7][18]
IO[2].SLEW	MAIN[9][18]
IO[3].SLEW	MAIN[9][19]
FAST	1
SLOW	0

xc5200 IO_N enum IO_PULL
IO[0].PULL	MAIN[0][26]	MAIN[1][25]
IO[1].PULL	MAIN[7][19]	MAIN[6][19]
IO[2].PULL	MAIN[8][18]	MAIN[8][19]
IO[3].PULL	MAIN[10][16]	MAIN[10][19]
NONE	0	1
PULLUP	1	1
PULLDOWN	0	0

Bels COUT

xc5200 IO_N bel COUT pins
Pin	Direction	COUT
OUT	out	OUT_TOP_COUT

Bel wires

xc5200 IO_N bel wires
Wire	Pins
OMUX_BUF[0]	TBUF[0].I
OMUX_BUF[1]	TBUF[1].I
OMUX_BUF[2]	TBUF[2].I
OMUX_BUF[3]	TBUF[3].I
OUT_TBUF[0]	TBUF[0].O
OUT_TBUF[1]	TBUF[1].O
OUT_TBUF[2]	TBUF[2].O
OUT_TBUF[3]	TBUF[3].O
OUT_IO_I[0]	IO[0].I
OUT_IO_I[1]	IO[1].I
OUT_IO_I[2]	IO[2].I
OUT_IO_I[3]	IO[3].I
OUT_TOP_COUT	COUT.OUT
IMUX_TS	TBUF[0].T, TBUF[1].T, TBUF[2].T, TBUF[3].T
IMUX_IO_O_SN[0]	IO[0].O
IMUX_IO_O_SN[1]	IO[1].O
IMUX_IO_O_SN[2]	IO[2].O
IMUX_IO_O_SN[3]	IO[3].O
IMUX_IO_T[0]	IO[0].T
IMUX_IO_T[1]	IO[1].T
IMUX_IO_T[2]	IO[2].T
IMUX_IO_T[3]	IO[3].T

Bitstream

xc5200 IO_N rect MAIN
Bit	Frame
Bit	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B27	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	IO[0]: SLEW bit 0	IO[0]: PULL bit 1
B25	-	-	-	-	-	-	-	-	-	-	IO[0]: PULL bit 0	INT: mux IMUX_GIN bit 4
B24	-	-	-	-	-	-	-	-	-	-	INT: mux IMUX_TS bit 5	INT: mux IMUX_GIN bit 2
B23	-	IO[3]: ! DELAY_ENABLE	INT: mux IMUX_IO_O_SN[3] bit 2	INT: mux IMUX_IO_O_SN[3] bit 3	IO[2]: ! DELAY_ENABLE	INT: mux IMUX_IO_O_SN[2] bit 0	INT: mux IMUX_IO_O_SN[1] bit 0	-	-	INT: mux IMUX_TS bit 0	INT: mux IMUX_TS bit 4	INT: mux IMUX_GIN bit 3
B22	-	IO[3]: ! INV_I	INT: mux IMUX_IO_O_SN[3] bit 1	INT: mux IMUX_IO_O_SN[3] bit 0	INT: mux IMUX_IO_O_SN[2] bit 2	INT: mux IMUX_IO_O_SN[2] bit 1	IO[1]: ! DELAY_ENABLE	-	-	INT: mux IMUX_TS bit 3	INT: mux IMUX_TS bit 2	INT: mux IMUX_GIN bit 0
B21	-	IO[3]: invert T	INT: mux IMUX_IO_O_SN[0] bit 1	INT: mux IMUX_IO_O_SN[0] bit 0	INT: mux IMUX_IO_O_SN[2] bit 3	IO[2]: invert T	INT: mux IMUX_IO_O_SN[1] bit 1	-	-	INT: mux IMUX_TS bit 6	INT: mux IMUX_TS bit 1	INT: mux IMUX_GIN bit 1
B20	-	INT: mux IMUX_IO_O_SN[0] bit 2	INT: mux IMUX_IO_O_SN[0] bit 3	INT: mux IMUX_IO_O_SN[1] bit 3	INT: mux IMUX_IO_O_SN[1] bit 2	IO[2]: ! INV_I	IO[1]: ! INV_I	-	INT: mux IMUX_IO_O[1] bit 1	INT: mux IMUX_IO_O[2] bit 1	INT: mux OMUX[0] bit 0	INT: mux OMUX[1] bit 0
B19	-	IO[3]: PULL bit 0	IO[3]: SLEW bit 0	IO[2]: PULL bit 0	IO[1]: PULL bit 1	IO[1]: PULL bit 0	IO[1]: invert T	-	INT: mux IMUX_IO_O[1] bit 0	INT: mux IMUX_IO_O[2] bit 0	INT: mux OMUX[0] bit 6	INT: mux OMUX[1] bit 6
B18	-	-	IO[2]: SLEW bit 0	IO[2]: PULL bit 1	IO[1]: SLEW bit 0	-	IO[0]: ! DELAY_ENABLE	-	INT: mux IMUX_IO_O[1] bit 6	INT: mux IMUX_IO_O[2] bit 6	INT: mux OMUX[0] bit 1	INT: mux OMUX[1] bit 1
B17	-	-	-	-	INT: !pass IO_M[0] ← LONG_H[0]	INT: pass LONG_H[0] ← OUT_TBUF[0]	IO[0]: ! INV_I	-	INT: mux IMUX_IO_O[1] bit 2	INT: mux IMUX_IO_O[2] bit 2	INT: mux OMUX[0] bit 2	INT: mux OMUX[1] bit 4
B16	-	IO[3]: PULL bit 1	-	-	INT: !pass IO_M[8] ← LONG_V[0]	INT: pass LONG_V[0] ← OUT_TBUF[0]	IO[0]: invert T	-	INT: mux IMUX_IO_O[1] bit 3	INT: mux IMUX_IO_O[2] bit 3	INT: mux OMUX[0] bit 3	INT: mux OMUX[1] bit 5
B15	-	INT: !bipass IO_M[0] = SINGLE_IO_N_W[0]	INT: bipass IO_M[0] = SINGLE_IO_N_E[0]	INT: !bipass IO_M[15] = SINGLE_IO_N_W[0]	TBUF[0]: ! T_ENABLE	INT: pass IO_M[1] ← LONG_H[1]	INT: !pass IO_M[2] ← OMUX_BUF[2]	-	INT: mux IMUX_IO_O[1] bit 4	INT: mux IMUX_IO_O[2] bit 4	INT: mux OMUX[0] bit 4	INT: mux OMUX[1] bit 2
B14	-	INT: !bipass IO_M[8] = SINGLE_S[8]	INT: bipass IO_M[8] = SINGLE_IO_N_E[0]	INT: !bipass IO_M[0] = DBL_V_N[0]	INT: !pass LONG_V[1] ← OUT_TBUF[1]	INT: pass LONG_H[1] ← OUT_TBUF[1]	INT: !pass IO_M[8] ← OMUX_BUF[2]	-	INT: mux IMUX_IO_O[1] bit 5	INT: mux IMUX_IO_O[2] bit 5	INT: mux OMUX[0] bit 5	INT: mux OMUX[1] bit 3
B13	-	INT: !bipass IO_M[1] = SINGLE_IO_N_W[1]	INT: bipass IO_M[1] = SINGLE_IO_N_E[1]	INT: !bipass IO_M[8] = SINGLE_IO_N_W[1]	INT: !pass IO_M[9] ← LONG_V[1]	INT: pass IO_M[2] ← LONG_H[2]	INT: !pass IO_M[3] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 5	INT: mux IMUX_IO_O[0] bit 5	INT: mux IMUX_IO_T[2] bit 5	INT: mux IMUX_IO_T[3] bit 5
B12	-	INT: !bipass IO_M[9] = SINGLE_S[9]	INT: bipass IO_M[9] = SINGLE_IO_N_E[1]	INT: !bipass IO_M[1] = SINGLE_S[1]	INT: !pass LONG_V[2] ← OUT_TBUF[2]	INT: pass LONG_H[2] ← OUT_TBUF[2]	INT: !pass IO_M[9] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 4	INT: mux IMUX_IO_O[0] bit 4	INT: mux IMUX_IO_T[2] bit 4	INT: mux IMUX_IO_T[3] bit 4
B11	-	INT: !bipass IO_M[2] = SINGLE_IO_N_W[2]	INT: bipass IO_M[2] = SINGLE_IO_N_E[2]	INT: !bipass IO_M[9] = SINGLE_IO_N_W[2]	INT: !pass IO_M[10] ← LONG_V[2]	TBUF[1]: T_ENABLE	INT: !pass IO_M[0] ← OMUX_BUF[0]	-	INT: mux IMUX_IO_O[3] bit 3	INT: mux IMUX_IO_O[0] bit 3	INT: mux IMUX_IO_T[2] bit 3	INT: mux IMUX_IO_T[3] bit 3
B10	-	INT: !bipass IO_M[10] = SINGLE_S[10]	INT: bipass IO_M[10] = SINGLE_IO_N_E[2]	INT: !bipass IO_M[2] = SINGLE_S[2]	INT: !pass LONG_H[3] ← OUT_TBUF[3]	INT: pass IO_M[3] ← LONG_H[3]	INT: !pass IO_M[10] ← OMUX_BUF[0]	-	INT: mux IMUX_IO_O[3] bit 2	INT: mux IMUX_IO_O[0] bit 2	INT: mux IMUX_IO_T[2] bit 2	INT: mux IMUX_IO_T[3] bit 2
B9	-	INT: !bipass IO_M[3] = SINGLE_IO_N_W[3]	INT: bipass IO_M[3] = SINGLE_IO_N_E[3]	INT: !bipass IO_M[10] = SINGLE_IO_N_W[3]	INT: !pass LONG_V[3] ← OUT_TBUF[3]	INT: pass IO_M[11] ← LONG_V[3]	INT: !pass IO_M[1] ← OMUX_BUF[1]	-	INT: mux IMUX_IO_O[3] bit 0	INT: mux IMUX_IO_O[0] bit 6	INT: mux IMUX_IO_T[2] bit 0	INT: mux IMUX_IO_T[3] bit 0
B8	-	INT: !bipass IO_M[11] = SINGLE_S[11]	INT: bipass IO_M[11] = SINGLE_IO_N_E[3]	INT: !bipass IO_M[3] = SINGLE_S[3]	INT: !pass LONG_H[4] ← OUT_TBUF[0]	INT: pass IO_M[4] ← LONG_H[4]	INT: !pass IO_M[11] ← OMUX_BUF[1]	-	INT: mux IMUX_IO_O[3] bit 1	INT: mux IMUX_IO_O[0] bit 0	INT: mux IMUX_IO_T[2] bit 1	INT: mux IMUX_IO_T[3] bit 1
B7	-	INT: !bipass IO_M[4] = SINGLE_IO_N_W[4]	INT: bipass IO_M[4] = SINGLE_IO_N_E[4]	INT: !bipass IO_M[11] = SINGLE_IO_N_W[4]	INT: !pass LONG_V[4] ← OUT_TBUF[0]	INT: pass IO_M[12] ← LONG_V[4]	INT: !pass IO_M[6] ← OMUX_BUF[3]	-	INT: mux IMUX_IO_O[3] bit 6	INT: mux IMUX_IO_O[0] bit 1	INT: mux IMUX_IO_T[2] bit 6	INT: mux IMUX_IO_T[3] bit 6
B6	-	INT: !bipass IO_M[12] = DBL_V_M[0]	INT: bipass IO_M[12] = SINGLE_IO_N_E[4]	INT: !bipass IO_M[4] = SINGLE_S[4]	INT: !pass IO_M[5] ← LONG_H[5]	TBUF[2]: T_ENABLE	INT: !pass IO_M[12] ← OMUX_BUF[3]	-	INT: mux OMUX[2] bit 0	INT: mux OMUX[3] bit 0	INT: mux IMUX_IO_T[0] bit 6	INT: mux IMUX_IO_T[1] bit 6
B5	-	INT: !bipass IO_M[5] = SINGLE_IO_N_W[5]	INT: bipass IO_M[5] = SINGLE_IO_N_E[5]	INT: !bipass IO_M[12] = SINGLE_IO_N_W[5]	INT: !pass LONG_H[5] ← OUT_TBUF[1]	INT: pass LONG_V[5] ← OUT_TBUF[1]	INT: !pass IO_M[7] ← OMUX_BUF[0]	-	INT: mux OMUX[2] bit 6	INT: mux OMUX[3] bit 6	INT: mux IMUX_IO_T[0] bit 1	INT: mux IMUX_IO_T[1] bit 1
B4	-	INT: !bipass IO_M[13] = DBL_V_M[1]	INT: bipass IO_M[13] = SINGLE_IO_N_E[5]	INT: !bipass IO_M[5] = SINGLE_S[5]	INT: !pass IO_M[6] ← LONG_H[6]	INT: pass IO_M[13] ← LONG_V[5]	INT: !pass IO_M[13] ← OMUX_BUF[0]	-	INT: mux OMUX[2] bit 1	INT: mux OMUX[3] bit 1	INT: mux IMUX_IO_T[0] bit 0	INT: mux IMUX_IO_T[1] bit 0
B3	-	INT: !bipass IO_M[6] = SINGLE_IO_N_W[6]	INT: bipass IO_M[6] = SINGLE_IO_N_E[6]	INT: !bipass IO_M[13] = SINGLE_IO_N_W[6]	INT: !pass LONG_H[6] ← OUT_TBUF[2]	INT: pass LONG_V[6] ← OUT_TBUF[2]	INT: !pass IO_M[4] ← OMUX_BUF[1]	-	INT: mux OMUX[2] bit 2	INT: mux OMUX[3] bit 2	INT: mux IMUX_IO_T[0] bit 2	INT: mux IMUX_IO_T[1] bit 2
B2	-	INT: !pass IO_M[14] ← OUT_TOP_COUT	INT: bipass IO_M[14] = SINGLE_IO_N_E[6]	INT: !bipass IO_M[6] = DBL_V_N[1]	TBUF[3]: ! T_ENABLE	INT: pass IO_M[14] ← LONG_V[6]	INT: !pass IO_M[14] ← OMUX_BUF[1]	-	INT: mux OMUX[2] bit 3	INT: mux OMUX[3] bit 3	INT: mux IMUX_IO_T[0] bit 3	INT: mux IMUX_IO_T[1] bit 3
B1	-	INT: !bipass IO_M[7] = SINGLE_IO_N_W[7]	INT: bipass IO_M[7] = SINGLE_IO_N_E[7]	INT: !bipass IO_M[14] = SINGLE_IO_N_W[7]	INT: !pass IO_M[7] ← LONG_H[7]	INT: pass LONG_H[7] ← OUT_TBUF[3]	INT: !pass IO_M[5] ← OMUX_BUF[2]	-	INT: mux OMUX[2] bit 4	INT: mux OMUX[3] bit 4	INT: mux IMUX_IO_T[0] bit 4	INT: mux IMUX_IO_T[1] bit 4
B0	-	-	INT: bipass IO_M[15] = SINGLE_IO_N_E[7]	INT: !bipass IO_M[7] = SINGLE_S[7]	INT: !pass IO_M[15] ← LONG_V[7]	INT: pass LONG_V[7] ← OUT_TBUF[3]	INT: !pass IO_M[15] ← OMUX_BUF[2]	-	INT: mux OMUX[2] bit 5	INT: mux OMUX[3] bit 5	INT: mux IMUX_IO_T[0] bit 5	INT: mux IMUX_IO_T[1] bit 5

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