Project Combine

Contents:

  • Xilinx FPGAs
  • SiliconBlue FPGAs
  • Xilinx XC9500, XC9500XL, XC9500XV CPLDs
  • Xilinx XPLA3 CPLDs
    • Introduction
    • Device structure
    • Bitstream structure
    • Database schema
    • Database — chips
      • XCR3032XL
      • XCR3064XL
      • XCR3128XL
      • XCR3256XL
      • XCR3384XL
      • XCR3512XL
    • JTAG interface
  • Xilinx Coolrunner II CPLDs
  • Digilent Adept Programmers
Project Combine
  • Xilinx XPLA3 CPLDs
  • Database — chips
  • View page source

Database — chips

Contents:

  • XCR3032XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
  • XCR3064XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
  • XCR3128XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
  • XCR3256XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
  • XCR3384XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
  • XCR3512XL
    • I/O pins
    • Speed data
    • IMUX bits
    • Global bits
      • JED mapping
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