Xilinx FPGAs

Contents:

• XC5200
  • Configurable Logic Block
  • Input/Output
  • Corners
  • Splitters
• Virtex
  • Configurable Logic Block
  • Block RAM
  • Input/Output
  • Corners
  • Delay Locked Loop
  • PCI Logic
  • Clock interconnect
  • Configuration registers
• Virtex 2
  • Introduction
  • Device geometry
  • General interconnect
  • Configurable Logic Block
  • Block RAM — Virtex 2, Spartan 3
  • Clock interconnect
  • Input / Output
  • Digital Clock Managers
  • Hard PowerPC 405 cores
  • Multi-gigabit transceivers — Virtex 2 Pro
  • Multi-gigabit transceivers — Virtex 2 Pro X
  • Hard PCI logic
  • Corners
  • Configuration registers
• Spartan 3
  • Introduction
  • Device geometry
  • General interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Clock interconnect
  • Input / Output
  • Digital Clock Managers — Spartan 3
  • Digital Clock Managers — Spartan 3E, 3A
  • Corners
  • Configuration registers — Spartan 3, Spartan 3E
  • Configuration registers — Spartan 3A and 3A DSP
• FPGAcore
  • General interconnect
  • Configurable Logic Block
  • Clock interconnect
  • Input / Output
  • Corners
  • Configuration registers
• Spartan 6
  • General interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Clock interconnect
  • Memory Controller Block
  • PCI Express
  • Multi-gigabit transceivers
  • Digital clock manager
  • Phase-locked loop
  • Corners
  • Configuration registers
• Virtex 4
  • Device geometry
  • General Interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Input/Output
  • Configuration Center
  • Clock interconnect
  • Digital Clock Managers
  • Clock Companion Modules
  • Configuration registers
  • System monitor
  • Multi-gigabit transceivers
• Virtex 5
  • Device geometry
  • Interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Input/Output
  • Configuration Center
  • Clock interconnect
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
  • GTP transceivers
  • GTX transceivers
  • Configuration registers
• Virtex 6
  • Device geometry
  • Interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Input/Output
  • Configuration Center
  • Clock interconnect
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
  • GTH transceivers
  • Configuration registers
• Virtex 7
  • Device geometry
  • Interconnect
  • Configurable Logic Block
  • Block RAM
  • DSP
  • Input/Output
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores