Virtex 2

Virtex 2 is a family of SRAM-based FPGAs, the successor to Virtex.

There are three kinds of Virtex 2 FPGAs:

Virtex 2, the base version
Virtex 2 Pro, an upgraded version that adds multi-gigabit transceivers and hard PowerPC 405 cores
Virtex 2 Pro X, a version of Virtex 2 Pro with faster multi-gigabit transceivers

The Virtex 2 FPGAs feature:

a new, fully buffered general interconnect structure
a dedicated clock interconnect with 8 global clocks and BUFGMUX primitives with clock multiplexing
new configurable logic blocks, derived from the Virtex ones
new block RAM tiles, containing:
- 18-kbit block RAM
- 18×18 multiplier blocks
new input-output tiles, with DDR register and DCI (digitally controlled impedance) support
new digital clock managers, a new version of the Virtex DLLs with added frequency synthesis capability
corner tiles, with various global bits of logic:
- BSCAN primitive, allowing access to FPGA fabric via dedicated JTAG instructions
- JTAGPPC primitive (Virtex 2 Pro), for connecting the PowerPC cores to JTAG
- STARTUP primitive, controlling the startup process
- CAPTURE primitive, for user-triggered FF state capture
- ICAP primitive, allowing access to the internal configuration port
- PMV primitive, an internal oscillator used for configuration
- per-IO bank:
  - DCI control blocks
  - LVDS bias generators
a tiny bit of hard PCI logic

The Virtex 2 Pro FPGAs additionally feature:

Device table

TODO: generate this