XC2C32A, XA2C32A

IDCODE part: 0x6e18

FB count: 2

I/O banks: 2

Input-only pads: 1

Has VREF: False

BS cols: 260

IMUX width: 8

BS layout: WIDE

FB rows: 1

MC width: 9

FB rows: 1

Column range	Bits
0..1	transfer
1..10	FB column 0 even MCs
10..122	FB column 0 even PTs
122..138	FB column 0 IMUX
138..250	FB column 0 odd PTs
250..259	FB column 0 odd MCs
259..260	transfer

I/O pins

Function	Bank	Pad distance	xc2c32a-qfg32	xc2c32a-pc44	xc2c32a-vq44, xa2c32a-vq44	xc2c32a-cp56	xc2c32a-di44	xc2c32a-cv64
IDCODE part			0x6e1b	0x6e1d	0x6e1c	0x6e1b	0x6e18	0x6e1a
IPAD0	1	23	P22	P24	P18	D10	P29	D6
IOB_0_0	1	43	-	P44	P38	F1	P5	D2
IOB_0_1	1	42	-	P43	P37	E3	P4	D1
IOB_0_2	1	41	-	P42	P36	E1	P3	C2
IOB_0_3 (GOE1)	1	39	P3	P40	P34	D1	P1	B2
IOB_0_4 (GOE0)	1	38	P2	P39	P33	C1	P44	A1
IOB_0_5 (GOE3)	1	37	P1	P38	P32	A3	P43	C3
IOB_0_6 (GOE2)	1	36	P32	P37	P31	A2	P42	A2
IOB_0_7 (GSR)	1	35	P31	P36	P30	B1	P41	B3
IOB_0_8	1	34	P30	P35	P29	A1	P40	C4
IOB_0_9	1	33	P29	P34	P28	C4	P39	B4
IOB_0_10	1	32	P28	P33	P27	C5	P38	C5
IOB_0_11	1	28	P24	P29	P23	C8	P34	B7
IOB_0_12	1	27	-	P28	P22	A10	P33	C6
IOB_0_13	1	26	P23	P27	P21	B10	P32	B8
IOB_0_14	1	25	-	P26	P20	C10	P31	C7
IOB_0_15	1	24	-	P25	P19	E8	P30	C8
IOB_1_0	0	0	P5	P1	P39	G1	P6	E1
IOB_1_1	0	1	-	P2	P40	F3	P7	E2
IOB_1_2	0	2	-	P3	P41	H1	P8	F1
IOB_1_3	0	3	-	P4	P42	G3	P9	G1
IOB_1_4 (GCLK0)	0	4	P6	P5	P43	J1	P10	F3
IOB_1_5 (GCLK1)	0	5	P7	P6	P44	K1	P11	H1
IOB_1_6 (GCLK2)	0	6	P8	P7	P1	K2	P12	H2
IOB_1_7	0	7	P9	P8	P2	K3	P13	G3
IOB_1_8	0	8	P10	P9	P3	H3	P14	H3
IOB_1_9	0	10	-	P11	P5	K5	P16	G4
IOB_1_10	0	11	-	P12	P6	H5	P17	F4
IOB_1_11	0	13	P13	P14	P8	H8	P19	H6
IOB_1_12	0	17	P17	P18	P12	K8	P23	G7
IOB_1_13	0	18	P18	P19	P13	H10	P24	G8
IOB_1_14	0	19	P19	P20	P14	G10	P25	F7
IOB_1_15	0	21	-	P22	P16	F10	P27	E7
TCK	AUX		P16	P17	P11	K10	P22	F6
TMS	AUX		P15	P16	P10	K9	P21	H7
TDI	AUX		P14	P15	P9	J10	P20	G6
TDO	AUX		P25	P30	P24	A6	P35	D5
GND	-		P11 P21 P26	P10 P23 P31	P17 P25 P4	C7 F8 H4	P15 P28 P36	A5 D8 E4
VCCINT	-		P20	P21	P15	G8	P26	E5
VCCIO0	0		P12	P13	P7	H6	P18	G5
VCCIO1	1		P27	P32	P26	C6	P37	B5
VCCAUX	-		P4	P41	P35	D3	P2	B1
NC	-		-	-	-	A4 A5 A7 A8 A9 C3 D8 E10 H7 K4 K6 K7	-	-

Speed data

Timing parameter	xc2c32a-4	xc2c32a-6	xa2c32a-6	xa2c32a-7
DEL_CLK_Q	600	700	700	700
DEL_D_Q_COMB	300	700	700	700
DEL_D_Q_LATCH	1500	2500	2500	2500
DEL_IBUF_D	1500	2400	2400	2400
DEL_IBUF_FCLK	1300	2000	2000	2000
DEL_IBUF_FOE	1100	2100	2100	1500
DEL_IBUF_FSR	1600	2000	2000	2000
DEL_IBUF_IMUX	1300	1700	1700	1700
DEL_IBUF_PLAIN.LVCMOS18	0	0	0	0
DEL_IBUF_PLAIN.LVCMOS18_ANY	0	0	0	0
DEL_IBUF_PLAIN.LVCMOS25	500	600	600	700
DEL_IBUF_PLAIN.LVCMOS33	500	600	600	800
DEL_IBUF_PLAIN.LVTTL	500	600	600	800
DEL_IBUF_SCHMITT.LVCMOS15	3000	4000	4000	4200
DEL_IBUF_SCHMITT.LVCMOS18	3000	4000	4000	4000
DEL_IBUF_SCHMITT.LVCMOS18_ANY	3000	4000	4000	4000
DEL_IBUF_SCHMITT.LVCMOS25	3000	4000	4000	4000
DEL_IBUF_SCHMITT.LVCMOS33	3000	4000	4000	4000
DEL_IBUF_SCHMITT.LVTTL	3000	4000	4000	4000
DEL_IMUX_CT	1300	1600	1600	1600
DEL_IMUX_OR	600	1600	1600	1600
DEL_IMUX_PT	400	1100	1100	1100
DEL_MC_FOE	700	800	800	200
DEL_OBUF_FAST.LVCMOS15	2600	3000	3000	3000
DEL_OBUF_FAST.LVCMOS18	1800	2000	2000	2000
DEL_OBUF_FAST.LVCMOS18_ANY	1800	2000	2000	2000
DEL_OBUF_FAST.LVCMOS25	2400	2700	2700	2800
DEL_OBUF_FAST.LVCMOS33	2800	3200	3200	3200
DEL_OBUF_FAST.LVTTL	2800	3200	3200	3200
DEL_OBUF_OE	3600	3400	3400	4700
DEL_OBUF_SLOW.LVCMOS15	6600	8000	8000	8000
DEL_OBUF_SLOW.LVCMOS18	5800	7000	7000	7000
DEL_OBUF_SLOW.LVCMOS18_ANY	5800	7000	7000	7000
DEL_OBUF_SLOW.LVCMOS25	6400	7700	7700	8300
DEL_OBUF_SLOW.LVCMOS33	6800	8200	8200	9800
DEL_OBUF_SLOW.LVTTL	6800	8200	8200	9800
DEL_SR_Q	1100	1500	1500	1500
DEL_UIM_IMUX	600	1400	1400	1400
HOLD_CE_CLK	0	0	0	0
HOLD_D_CLK_IBUF_FCLK	200	200	200	200
HOLD_D_CLK_IBUF_PT	400	700	700	700
HOLD_D_CLK_PT_FCLK	200	200	200	200
HOLD_D_CLK_PT_PT	400	700	700	700
SETUP_CE_CLK	700	1700	1700	1700
SETUP_D_CLK_IBUF_FCLK	1500	1800	1800	1800
SETUP_D_CLK_IBUF_PT	1500	1800	1800	1800
SETUP_D_CLK_PT_FCLK	1500	1800	1800	1800
SETUP_D_CLK_PT_PT	1500	1800	1800	1800
WIDTH_CLK	1400	2200	2200	2200
WIDTH_CLK_PT	4000	6000	6000	6000
WIDTH_SR	4000	6000	6000	6000

IMUX bits

Row	Column
Row	0	2	4	6	8	10	12	14
0	X	X	X	X	X	X	X	X
1	X	X	X	X	X	X	X	X
2	X	X	X	X	X	X	X	X
3	X	X	X	X	X	X	X	X
4	X	X	X	X	X	X	X	X
5	X	X	X	X	X	X	X	X
6	X	X	X	X	X	X	X	X
7	X	X	X	X	X	X	X	X
8	X	X	X	X	X	X	X	X
9	X	X	X	X	X	X	X	X
10	X	X	X	X	X	X	X	X
11	X	X	X	X	X	X	X	X
12	X	X	X	X	X	X	X	X
13	X	X	X	X	X	X	X	X
14	X	X	X	X	X	X	X	X
15	X	X	X	X	X	X	X	X
16	X	X	X	X	X	X	X	X
17	X	X	X	X	X	X	X	X
18	X	X	X	X	X	X	X	X
19	X	X	X	X	X	X	X	X
28	X	X	X	X	X	X	X	X
29	X	X	X	X	X	X	X	X
30	X	X	X	X	X	X	X	X
31	X	X	X	X	X	X	X	X
32	X	X	X	X	X	X	X	X
33	X	X	X	X	X	X	X	X
34	X	X	X	X	X	X	X	X
35	X	X	X	X	X	X	X	X
36	X	X	X	X	X	X	X	X
37	X	X	X	X	X	X	X	X
38	X	X	X	X	X	X	X	X
39	X	X	X	X	X	X	X	X
40	X	X	X	X	X	X	X	X
41	X	X	X	X	X	X	X	X
42	X	X	X	X	X	X	X	X
43	X	X	X	X	X	X	X	X
44	X	X	X	X	X	X	X	X
45	X	X	X	X	X	X	X	X
46	X	X	X	X	X	X	X	X
47	X	X	X	X	X	X	X	X

IM[0].MUX	[0, 0]	[0, 2]	[0, 4]	[0, 6]	[0, 8]	[0, 10]	[0, 12]	[0, 14]
IOB_0_0	0	1	1	1	1	1	1	0
IOB_0_10	1	0	1	1	1	1	1	0
IOB_1_5	1	1	0	1	1	1	1	0
MC_0_1	1	1	1	0	1	1	1	0
MC_0_13	1	1	1	1	0	1	1	0
MC_1_9	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[1].MUX	[1, 0]	[1, 2]	[1, 4]	[1, 6]	[1, 8]	[1, 10]	[1, 12]	[1, 14]
IOB_0_1	0	1	1	1	1	1	1	0
IOB_0_11	1	0	1	1	1	1	1	0
IOB_1_6	1	1	0	1	1	1	1	0
MC_0_8	1	1	1	0	1	1	1	0
MC_0_15	1	1	1	1	0	1	1	0
MC_1_12	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[2].MUX	[2, 0]	[2, 2]	[2, 4]	[2, 6]	[2, 8]	[2, 10]	[2, 12]	[2, 14]
IOB_0_2	0	1	1	1	1	1	1	0
IOB_0_12	1	0	1	1	1	1	1	0
IOB_1_13	1	1	0	1	1	1	1	0
MC_0_2	1	1	1	0	1	1	1	0
MC_1_4	1	1	1	1	0	1	1	0
MC_1_11	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[3].MUX	[3, 0]	[3, 2]	[3, 4]	[3, 6]	[3, 8]	[3, 10]	[3, 12]	[3, 14]
IOB_0_3	0	1	1	1	1	1	1	0
IOB_0_13	1	0	1	1	1	1	1	0
IOB_1_9	1	1	0	1	1	1	1	0
MC_0_9	1	1	1	0	1	1	1	0
MC_0_14	1	1	1	1	0	1	1	0
MC_1_6	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[4].MUX	[4, 0]	[4, 2]	[4, 4]	[4, 6]	[4, 8]	[4, 10]	[4, 12]	[4, 14]
IOB_0_4	0	1	1	1	1	1	1	0
IOB_0_14	1	0	1	1	1	1	1	0
IOB_1_11	1	1	0	1	1	1	1	0
MC_0_5	1	1	1	0	1	1	1	0
MC_0_11	1	1	1	1	0	1	1	0
MC_1_10	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[5].MUX	[5, 0]	[5, 2]	[5, 4]	[5, 6]	[5, 8]	[5, 10]	[5, 12]	[5, 14]
IOB_0_5	0	1	1	1	1	1	1	0
IOB_0_15	1	0	1	1	1	1	1	0
IOB_1_14	1	1	0	1	1	1	1	0
MC_0_7	1	1	1	0	1	1	1	0
MC_1_1	1	1	1	1	0	1	1	0
MC_1_7	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[6].MUX	[6, 0]	[6, 2]	[6, 4]	[6, 6]	[6, 8]	[6, 10]	[6, 12]	[6, 14]
IOB_0_6	0	1	1	1	1	1	1	0
IPAD0	1	0	1	1	1	1	1	0
IOB_1_4	1	1	0	1	1	1	1	0
MC_0_0	1	1	1	0	1	1	1	0
MC_1_3	1	1	1	1	0	1	1	0
MC_1_13	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[7].MUX	[7, 0]	[7, 2]	[7, 4]	[7, 6]	[7, 8]	[7, 10]	[7, 12]	[7, 14]
IOB_0_7	0	1	1	1	1	1	1	0
IOB_1_0	1	0	1	1	1	1	1	0
IOB_1_10	1	1	0	1	1	1	1	0
IOB_1_15	1	1	1	0	1	1	1	0
MC_0_12	1	1	1	1	0	1	1	0
MC_1_15	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[8].MUX	[8, 0]	[8, 2]	[8, 4]	[8, 6]	[8, 8]	[8, 10]	[8, 12]	[8, 14]
IOB_0_8	0	1	1	1	1	1	1	0
IOB_1_1	1	0	1	1	1	1	1	0
IOB_1_8	1	1	0	1	1	1	1	0
MC_0_6	1	1	1	0	1	1	1	0
MC_0_10	1	1	1	1	0	1	1	0
MC_1_8	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[9].MUX	[9, 0]	[9, 2]	[9, 4]	[9, 6]	[9, 8]	[9, 10]	[9, 12]	[9, 14]
IOB_0_9	0	1	1	1	1	1	1	0
IOB_1_2	1	0	1	1	1	1	1	0
IOB_1_7	1	1	0	1	1	1	1	0
MC_0_4	1	1	1	0	1	1	1	0
MC_1_2	1	1	1	1	0	1	1	0
MC_1_5	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[10].MUX	[10, 0]	[10, 2]	[10, 4]	[10, 6]	[10, 8]	[10, 10]	[10, 12]	[10, 14]
IOB_0_7	0	1	1	1	1	1	1	0
IOB_1_3	1	0	1	1	1	1	1	0
IOB_1_12	1	1	0	1	1	1	1	0
MC_0_3	1	1	1	0	1	1	1	0
MC_1_0	1	1	1	1	0	1	1	0
MC_1_14	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[11].MUX	[11, 0]	[11, 2]	[11, 4]	[11, 6]	[11, 8]	[11, 10]	[11, 12]	[11, 14]
IOB_0_0	0	1	1	1	1	1	1	0
IOB_0_11	1	0	1	1	1	1	1	0
IOB_1_6	1	1	0	1	1	1	1	0
MC_0_2	1	1	1	0	1	1	1	0
MC_0_14	1	1	1	1	0	1	1	0
MC_1_10	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[12].MUX	[12, 0]	[12, 2]	[12, 4]	[12, 6]	[12, 8]	[12, 10]	[12, 12]	[12, 14]
IOB_0_1	0	1	1	1	1	1	1	0
IOB_0_12	1	0	1	1	1	1	1	0
IOB_1_13	1	1	0	1	1	1	1	0
MC_0_4	1	1	1	0	1	1	1	0
MC_1_1	1	1	1	1	0	1	1	0
MC_1_15	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[13].MUX	[13, 0]	[13, 2]	[13, 4]	[13, 6]	[13, 8]	[13, 10]	[13, 12]	[13, 14]
IOB_0_2	0	1	1	1	1	1	1	0
IOB_1_2	1	0	1	1	1	1	1	0
IOB_1_7	1	1	0	1	1	1	1	0
MC_0_9	1	1	1	0	1	1	1	0
MC_1_0	1	1	1	1	0	1	1	0
MC_1_13	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[14].MUX	[14, 0]	[14, 2]	[14, 4]	[14, 6]	[14, 8]	[14, 10]	[14, 12]	[14, 14]
IOB_0_3	0	1	1	1	1	1	1	0
IOB_0_15	1	0	1	1	1	1	1	0
IOB_1_14	1	1	0	1	1	1	1	0
MC_0_3	1	1	1	0	1	1	1	0
MC_0_11	1	1	1	1	0	1	1	0
MC_1_12	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[15].MUX	[15, 0]	[15, 2]	[15, 4]	[15, 6]	[15, 8]	[15, 10]	[15, 12]	[15, 14]
IOB_0_4	0	1	1	1	1	1	1	0
IOB_1_0	1	0	1	1	1	1	1	0
IOB_1_10	1	1	0	1	1	1	1	0
MC_0_0	1	1	1	0	1	1	1	0
MC_0_15	1	1	1	1	0	1	1	0
MC_1_7	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[16].MUX	[16, 0]	[16, 2]	[16, 4]	[16, 6]	[16, 8]	[16, 10]	[16, 12]	[16, 14]
IOB_0_5	0	1	1	1	1	1	1	0
IOB_1_3	1	0	1	1	1	1	1	0
IOB_1_12	1	1	0	1	1	1	1	0
MC_0_6	1	1	1	0	1	1	1	0
MC_0_12	1	1	1	1	0	1	1	0
MC_1_11	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[17].MUX	[17, 0]	[17, 2]	[17, 4]	[17, 6]	[17, 8]	[17, 10]	[17, 12]	[17, 14]
IOB_0_6	0	1	1	1	1	1	1	0
IOB_0_10	1	0	1	1	1	1	1	0
IOB_1_5	1	1	0	1	1	1	1	0
MC_0_8	1	1	1	0	1	1	1	0
MC_1_2	1	1	1	1	0	1	1	0
MC_1_8	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[18].MUX	[18, 0]	[18, 2]	[18, 4]	[18, 6]	[18, 8]	[18, 10]	[18, 12]	[18, 14]
IOB_0_7	0	1	1	1	1	1	1	0
IPAD0	1	0	1	1	1	1	1	0
IOB_1_4	1	1	0	1	1	1	1	0
MC_0_1	1	1	1	0	1	1	1	0
MC_1_4	1	1	1	1	0	1	1	0
MC_1_14	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[19].MUX	[19, 0]	[19, 2]	[19, 4]	[19, 6]	[19, 8]	[19, 10]	[19, 12]	[19, 14]
IOB_0_8	0	1	1	1	1	1	1	0
IOB_0_14	1	0	1	1	1	1	1	0
IOB_1_11	1	1	0	1	1	1	1	0
IOB_1_15	1	1	1	0	1	1	1	0
MC_0_13	1	1	1	1	0	1	1	0
MC_1_6	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[20].MUX	[28, 0]	[28, 2]	[28, 4]	[28, 6]	[28, 8]	[28, 10]	[28, 12]	[28, 14]
IOB_0_9	0	1	1	1	1	1	1	0
IOB_0_13	1	0	1	1	1	1	1	0
IOB_1_9	1	1	0	1	1	1	1	0
MC_0_7	1	1	1	0	1	1	1	0
MC_0_10	1	1	1	1	0	1	1	0
MC_1_9	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[21].MUX	[29, 0]	[29, 2]	[29, 4]	[29, 6]	[29, 8]	[29, 10]	[29, 12]	[29, 14]
IOB_0_8	0	1	1	1	1	1	1	0
IOB_1_1	1	0	1	1	1	1	1	0
IOB_1_8	1	1	0	1	1	1	1	0
MC_0_5	1	1	1	0	1	1	1	0
MC_1_3	1	1	1	1	0	1	1	0
MC_1_5	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[22].MUX	[30, 0]	[30, 2]	[30, 4]	[30, 6]	[30, 8]	[30, 10]	[30, 12]	[30, 14]
IOB_0_0	0	1	1	1	1	1	1	0
IOB_0_12	1	0	1	1	1	1	1	0
IOB_1_7	1	1	0	1	1	1	1	0
MC_0_3	1	1	1	0	1	1	1	0
MC_0_15	1	1	1	1	0	1	1	0
MC_1_11	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[23].MUX	[31, 0]	[31, 2]	[31, 4]	[31, 6]	[31, 8]	[31, 10]	[31, 12]	[31, 14]
IOB_0_1	0	1	1	1	1	1	1	0
IOB_1_2	1	0	1	1	1	1	1	0
IOB_1_9	1	1	0	1	1	1	1	0
MC_0_6	1	1	1	0	1	1	1	0
MC_1_4	1	1	1	1	0	1	1	0
MC_1_5	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[24].MUX	[32, 0]	[32, 2]	[32, 4]	[32, 6]	[32, 8]	[32, 10]	[32, 12]	[32, 14]
IOB_0_2	0	1	1	1	1	1	1	0
IOB_0_13	1	0	1	1	1	1	1	0
IOB_1_14	1	1	0	1	1	1	1	0
MC_0_5	1	1	1	0	1	1	1	0
MC_1_2	1	1	1	1	0	1	1	0
MC_1_6	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[25].MUX	[33, 0]	[33, 2]	[33, 4]	[33, 6]	[33, 8]	[33, 10]	[33, 12]	[33, 14]
IOB_0_3	0	1	1	1	1	1	1	0
IOB_1_3	1	0	1	1	1	1	1	0
IOB_1_8	1	1	0	1	1	1	1	0
MC_0_0	1	1	1	0	1	1	1	0
MC_1_1	1	1	1	1	0	1	1	0
MC_1_14	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[26].MUX	[34, 0]	[34, 2]	[34, 4]	[34, 6]	[34, 8]	[34, 10]	[34, 12]	[34, 14]
IOB_0_4	0	1	1	1	1	1	1	0
IPAD0	1	0	1	1	1	1	1	0
IOB_1_5	1	1	0	1	1	1	1	0
MC_0_4	1	1	1	0	1	1	1	0
MC_0_12	1	1	1	1	0	1	1	0
MC_1_13	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[27].MUX	[35, 0]	[35, 2]	[35, 4]	[35, 6]	[35, 8]	[35, 10]	[35, 12]	[35, 14]
IOB_0_5	0	1	1	1	1	1	1	0
IOB_1_1	1	0	1	1	1	1	1	0
IOB_1_11	1	1	0	1	1	1	1	0
MC_0_1	1	1	1	0	1	1	1	0
MC_1_0	1	1	1	1	0	1	1	0
MC_1_8	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[28].MUX	[36, 0]	[36, 2]	[36, 4]	[36, 6]	[36, 8]	[36, 10]	[36, 12]	[36, 14]
IOB_0_6	0	1	1	1	1	1	1	0
IOB_0_11	1	0	1	1	1	1	1	0
IOB_1_13	1	1	0	1	1	1	1	0
MC_0_7	1	1	1	0	1	1	1	0
MC_0_13	1	1	1	1	0	1	1	0
MC_1_12	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[29].MUX	[37, 0]	[37, 2]	[37, 4]	[37, 6]	[37, 8]	[37, 10]	[37, 12]	[37, 14]
IOB_0_7	0	1	1	1	1	1	1	0
IOB_0_10	1	0	1	1	1	1	1	0
IOB_1_6	1	1	0	1	1	1	1	0
MC_0_9	1	1	1	0	1	1	1	0
MC_1_3	1	1	1	1	0	1	1	0
MC_1_9	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[30].MUX	[38, 0]	[38, 2]	[38, 4]	[38, 6]	[38, 8]	[38, 10]	[38, 12]	[38, 14]
IOB_0_8	0	1	1	1	1	1	1	0
IOB_1_0	1	0	1	1	1	1	1	0
IOB_1_4	1	1	0	1	1	1	1	0
MC_0_2	1	1	1	0	1	1	1	0
MC_0_11	1	1	1	1	0	1	1	0
MC_1_15	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[31].MUX	[39, 0]	[39, 2]	[39, 4]	[39, 6]	[39, 8]	[39, 10]	[39, 12]	[39, 14]
IOB_0_9	0	1	1	1	1	1	1	0
IOB_0_15	1	0	1	1	1	1	1	0
IOB_1_12	1	1	0	1	1	1	1	0
IOB_1_15	1	1	1	0	1	1	1	0
MC_0_14	1	1	1	1	0	1	1	0
MC_1_7	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[32].MUX	[40, 0]	[40, 2]	[40, 4]	[40, 6]	[40, 8]	[40, 10]	[40, 12]	[40, 14]
IOB_0_9	0	1	1	1	1	1	1	0
IOB_0_14	1	0	1	1	1	1	1	0
IOB_1_10	1	1	0	1	1	1	1	0
MC_0_8	1	1	1	0	1	1	1	0
MC_0_10	1	1	1	1	0	1	1	0
MC_1_10	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[33].MUX	[41, 0]	[41, 2]	[41, 4]	[41, 6]	[41, 8]	[41, 10]	[41, 12]	[41, 14]
IOB_0_0	0	1	1	1	1	1	1	0
IOB_0_13	1	0	1	1	1	1	1	0
IOB_1_8	1	1	0	1	1	1	1	0
MC_0_4	1	1	1	0	1	1	1	0
MC_1_0	1	1	1	1	0	1	1	0
MC_1_12	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[34].MUX	[42, 0]	[42, 2]	[42, 4]	[42, 6]	[42, 8]	[42, 10]	[42, 12]	[42, 14]
IOB_0_1	0	1	1	1	1	1	1	0
IOB_0_15	1	0	1	1	1	1	1	0
IOB_1_11	1	1	0	1	1	1	1	0
MC_0_9	1	1	1	0	1	1	1	0
MC_0_10	1	1	1	1	0	1	1	0
MC_1_11	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[35].MUX	[43, 0]	[43, 2]	[43, 4]	[43, 6]	[43, 8]	[43, 10]	[43, 12]	[43, 14]
IOB_0_2	0	1	1	1	1	1	1	0
IOB_1_3	1	0	1	1	1	1	1	0
IOB_1_10	1	1	0	1	1	1	1	0
MC_0_7	1	1	1	0	1	1	1	0
MC_0_11	1	1	1	1	0	1	1	0
MC_1_5	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[36].MUX	[44, 0]	[44, 2]	[44, 4]	[44, 6]	[44, 8]	[44, 10]	[44, 12]	[44, 14]
IOB_0_3	0	1	1	1	1	1	1	0
IOB_0_14	1	0	1	1	1	1	1	0
IOB_1_5	1	1	0	1	1	1	1	0
MC_0_6	1	1	1	0	1	1	1	0
MC_1_3	1	1	1	1	0	1	1	0
MC_1_7	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[37].MUX	[45, 0]	[45, 2]	[45, 4]	[45, 6]	[45, 8]	[45, 10]	[45, 12]	[45, 14]
IOB_0_4	0	1	1	1	1	1	1	0
IOB_0_11	1	0	1	1	1	1	1	0
IOB_1_9	1	1	0	1	1	1	1	0
MC_0_1	1	1	1	0	1	1	1	0
MC_1_2	1	1	1	1	0	1	1	0
MC_1_15	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[38].MUX	[46, 0]	[46, 2]	[46, 4]	[46, 6]	[46, 8]	[46, 10]	[46, 12]	[46, 14]
IOB_0_5	0	1	1	1	1	1	1	0
IOB_1_0	1	0	1	1	1	1	1	0
IOB_1_6	1	1	0	1	1	1	1	0
MC_0_5	1	1	1	0	1	1	1	0
MC_0_13	1	1	1	1	0	1	1	0
MC_1_14	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

IM[39].MUX	[47, 0]	[47, 2]	[47, 4]	[47, 6]	[47, 8]	[47, 10]	[47, 12]	[47, 14]
IOB_0_6	0	1	1	1	1	1	1	0
IOB_1_2	1	0	1	1	1	1	1	0
IOB_1_12	1	1	0	1	1	1	1	0
MC_0_2	1	1	1	0	1	1	1	0
MC_1_1	1	1	1	1	0	1	1	0
MC_1_9	1	1	1	1	1	0	1	0
VCC	1	1	1	1	1	1	1	1

MC bits

Row	Column
Row	0	1	2	3	4	5	6	7	8
0	X	X	X	X	X	X	X	X	X
1	X	X	X	X	X	X	X	X	X
2	X	X	X	X	X	X	X	X	X

CLK_MUX	[0, 3]	[0, 2]	[0, 0]
FCLK0	0	0	0
FCLK1	0	1	0
FCLK2	1	0	0
PT	1	1	0
CT4	1	1	1

CLK_INV	[0, 1]
Non-inverted	[0]

CLK_DDR	[0, 4]
Non-inverted	[0]

RST_MUX	[0, 6]	[0, 5]
PT	0	0
CT5	0	1
FSR	1	0
GND	1	1

SET_MUX	[0, 8]	[0, 7]
PT	0	0
CT6	0	1
FSR	1	0
GND	1	1

REG_MODE	[1, 1]	[1, 0]
DFF	0	0
TFF	0	1
LATCH	1	0
DFFCE	1	1

IOB_ZIA_MUX	[1, 3]	[1, 2]
IBUF	0	0
REG	0	1
NONE	1	1

MC_ZIA_MUX	[1, 5]	[1, 4]
XOR	0	0
REG	0	1
NONE	1	1

REG_D_MUX	[1, 6]
IBUF	0
XOR	1

IBUF_MODE	[1, 7]
PLAIN	0
SCHMITT	1

XOR_MUX	[2, 0]	[1, 8]
GND	0	0
PT	0	1
PT_INV	1	0
VCC	1	1

MC_IOB_MUX	[2, 1]
REG	0
XOR	1

OE_MUX	[2, 5]	[2, 4]	[2, 3]	[2, 2]
VCC	0	0	0	0
CT7	0	0	0	1
PT	0	0	1	0
FOE0	0	0	1	1
FOE1	0	1	0	0
FOE2	0	1	0	1
FOE3	0	1	1	0
IS_GND	0	1	1	1
OPEN_DRAIN	1	0	0	0
GND	1	1	1	1

IOB_TERM_ENABLE	[2, 6]
Non-inverted	[0]

IOB_SLEW	[2, 7]
FAST	0
SLOW	1

REG_INIT	[2, 8]
Inverted	~[0]

JED mapping

JED offset	Bit
0	CLK_MUX[0]
1	CLK_INV
2	CLK_MUX[1]
3	CLK_MUX[2]
4	CLK_DDR
5	RST_MUX[0]
6	RST_MUX[1]
7	SET_MUX[0]
8	SET_MUX[1]
9	REG_MODE[0]
10	REG_MODE[1]
11	IOB_ZIA_MUX[0]
12	IOB_ZIA_MUX[1]
13	MC_ZIA_MUX[0]
14	MC_ZIA_MUX[1]
15	REG_D_MUX
16	IBUF_MODE
17	XOR_MUX[0]
18	XOR_MUX[1]
19	MC_IOB_MUX
20	OE_MUX[0]
21	OE_MUX[1]
22	OE_MUX[2]
23	OE_MUX[3]
24	IOB_TERM_ENABLE
25	IOB_SLEW
26	REG_INIT

Global bits

Row	Column
Row	1	3	5	7	9	126	127	128	129	130	131	132	133	134	218	219	220	221	222	223	224	225	226	227	228	229	230	231	232	233	234	235	236	237	238	239	240	241	242	243	244	245	246	247	248	249
23	-	-	-	-	-	X	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	X	X	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	X	X	X	X	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
48	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X

FCLK0_ENABLE	[23, 126]
Non-inverted	[0]

FCLK1_ENABLE	[23, 127]
Non-inverted	[0]

FCLK2_ENABLE	[23, 128]
Non-inverted	[0]

FSR_INV	[23, 129]
Inverted	~[0]

FSR_ENABLE	[23, 130]
Non-inverted	[0]

TERM_MODE	[23, 131]
KEEPER	0
PULLUP	1

FOE0_MUX	[24, 127]	[24, 126]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

FOE1_MUX	[24, 129]	[24, 128]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

OBUF_VOLT	[24, 130]
HIGH	0
LOW	1

IPAD0_IBUF_MODE	[24, 131]
PLAIN	0
SCHMITT	1

IPAD0_TERM_ENABLE	[24, 132]
Non-inverted	[0]

FOE2_MUX	[25, 127]	[25, 126]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

FOE3_MUX	[25, 129]	[25, 128]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

IBUF_VOLT	[25, 130]
HIGH	0
LOW	1

BANK0_IBUF_VOLT	[25, 131]
HIGH	0
LOW	1

BANK0_OBUF_VOLT	[25, 132]
HIGH	0
LOW	1

BANK1_IBUF_VOLT	[25, 133]
HIGH	0
LOW	1

BANK1_OBUF_VOLT	[25, 134]
HIGH	0
LOW	1

READ_PROT	[48, 1]	[48, 3]	[48, 5]	[48, 7]
Inverted	~[3]	~[2]	~[1]	~[0]

DONE	[48, 9]
Inverted	~[0]

USERCODE	[49, 249]	[49, 248]	[49, 247]	[49, 246]	[49, 245]	[49, 244]	[49, 243]	[49, 242]	[49, 241]	[49, 240]	[49, 239]	[49, 238]	[49, 237]	[49, 236]	[49, 235]	[49, 234]	[49, 233]	[49, 232]	[49, 231]	[49, 230]	[49, 229]	[49, 228]	[49, 227]	[49, 226]	[49, 225]	[49, 224]	[49, 223]	[49, 222]	[49, 221]	[49, 220]	[49, 219]	[49, 218]
Non-inverted	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

JED mapping

JED offset	Bit
0	FCLK0_ENABLE
1	FCLK1_ENABLE
2	FCLK2_ENABLE
3	FSR_INV
4	FSR_ENABLE
5	FOE0_MUX[0]
6	FOE0_MUX[1]
7	FOE1_MUX[0]
8	FOE1_MUX[1]
9	FOE2_MUX[0]
10	FOE2_MUX[1]
11	FOE3_MUX[0]
12	FOE3_MUX[1]
13	TERM_MODE
14	OBUF_VOLT
15	IBUF_VOLT
16	IPAD0_IBUF_MODE
17	IPAD0_TERM_ENABLE
18	BANK0_IBUF_VOLT
19	BANK0_OBUF_VOLT
20	BANK1_IBUF_VOLT
21	BANK1_OBUF_VOLT