XC2C64

IDCODE part: 0x6c58

FB count: 4

I/O banks: 1

Input-only pads: 0

Has VREF: False

BS cols: 274

IMUX width: 16

BS layout: WIDE

FB rows: 2

MC width: 9

FB rows: 2

Column range	Bits
0..9	FB column 0 even MCs
9..121	FB column 0 even PTs
121..153	FB column 0 IMUX
153..265	FB column 0 odd PTs
265..274	FB column 0 odd MCs

I/O pins

Function	Bank	Pad distance	xc2c64-pc44	xc2c64-vq44	xc2c64-cp56	xc2c64-vq100	xc2c64-di81
IDCODE part			0x6c5a	0x6c5e	0x6c5d	0x6c5c	0x6c58
IOB_0_0	0	80	P44	P38	F1	P13	P11
IOB_0_1	0	79	P43	P37	E3	P12	P10
IOB_0_2	0	78	P42	P36	E1	P11	P9
IOB_0_3	0	77	-	-	-	P10	P8
IOB_0_4	0	76	-	-	-	P9	P7
IOB_0_5	0	75	-	-	-	P8	P6
IOB_0_6	0	74	-	-	-	P7	P5
IOB_0_7	0	73	-	-	-	P6	P4
IOB_0_8 (GOE1)	0	71	P40	P34	D1	P4	P2
IOB_0_9 (GOE0)	0	70	P39	P33	C1	P3	P1
IOB_0_10 (GOE3)	0	69	P38	P32	A3	P2	P81
IOB_0_11 (GOE2)	0	68	P37	P31	A2	P1	P80
IOB_0_12 (GSR)	0	66	P36	P30	B1	P99	P78
IOB_0_13	0	64	-	-	A1	P97	P76
IOB_0_14	0	63	-	-	C3	P94	P75
IOB_0_15	0	62	-	-	-	P92	P74
IOB_1_0	0	0	P1	P39	G1	P14	P12
IOB_1_1	0	1	P2	P40	F3	P15	P13
IOB_1_2	0	2	-	-	-	P16	P14
IOB_1_3	0	3	-	-	-	P17	P15
IOB_1_4	0	4	P3	P41	H1	P18	P16
IOB_1_5	0	5	P4	P42	G3	P19	P17
IOB_1_6 (GCLK0)	0	7	P5	P43	J1	P22	P19
IOB_1_7 (GCLK1)	0	8	P6	P44	K1	P23	P20
IOB_1_8	0	9	-	-	K4	P24	P21
IOB_1_9 (GCLK2)	0	11	P7	P1	K2	P27	P23
IOB_1_10	0	12	-	-	-	P28	P24
IOB_1_11	0	13	P8	P2	K3	P29	P25
IOB_1_12	0	14	P9	P3	H3	P30	P26
IOB_1_13	0	16	-	-	K5	P32	P28
IOB_1_14	0	17	-	-	-	P33	P29
IOB_1_15	0	18	-	-	-	P34	P30
IOB_2_0	0	61	P35	P29	C4	P91	P73
IOB_2_1	0	60	P34	P28	A4	P90	P72
IOB_2_2	0	59	P33	P27	C5	P89	P71
IOB_2_3	0	55	-	-	A7	P81	P67
IOB_2_4	0	54	-	-	C8	P79	P66
IOB_2_5	0	53	P29	P23	A8	P78	P65
IOB_2_6	0	52	-	-	A9	P77	P64
IOB_2_7	0	51	-	-	-	P76	P63
IOB_2_8	0	50	-	-	A5	P74	P62
IOB_2_9	0	49	P28	P22	A10	P72	P61
IOB_2_10	0	48	P27	P21	B10	P71	P60
IOB_2_11	0	47	P26	P20	C10	P70	P59
IOB_2_12	0	45	-	-	D8	P68	P57
IOB_2_13	0	44	P25	P19	E8	P67	P56
IOB_2_14	0	43	P24	P18	D10	P64	P55
IOB_2_15	0	41	-	-	-	P61	P53
IOB_3_0	0	19	P11	P5	K6	P35	P31
IOB_3_1	0	20	P12	P6	H5	P36	P32
IOB_3_2	0	21	-	-	K7	P37	P33
IOB_3_3	0	23	-	-	-	P39	P35
IOB_3_4	0	24	-	-	H7	P40	P36
IOB_3_5	0	25	-	-	-	P41	P37
IOB_3_6	0	26	P14	P8	H8	P42	P38
IOB_3_7	0	27	-	-	-	P43	P39
IOB_3_8	0	31	-	-	-	P49	P43
IOB_3_9	0	32	-	-	K8	P50	P44
IOB_3_10	0	34	P18	P12	H10	P52	P46
IOB_3_11	0	35	-	-	-	P53	P47
IOB_3_12	0	36	P19	P13	G10	P55	P48
IOB_3_13	0	37	P20	P14	-	P56	P49
IOB_3_14	0	39	P22	P16	F10	P58	P51
IOB_3_15	0	40	-	-	E10	P60	P52
TCK	AUX		P17	P11	K10	P48	P42
TMS	AUX		P16	P10	K9	P47	P41
TDI	AUX		P15	P9	J10	P45	P40
TDO	AUX		P30	P24	A6	P83	P68
GND	-		P10 P23 P31	P17 P25 P4	C7 F8 H4	P100 P21 P31 P62 P69 P84	P18 P27 P54 P58 P69 P79
VCCINT	-		P21	P15	G8	P26 P57	P22 P50
VCCIO0	0		P13 P32	P26 P7	C6 H6	P38 P51 P88 P98	P34 P45 P70 P77
VCCAUX	-		P41	P35	D3	P5	P3
NC	-		-	-	-	-	-

Speed data

Timing parameter	xc2c64-5	xc2c64-7
DEL_CLK_Q	400	700
DEL_D_Q_COMB	500	700
DEL_D_Q_LATCH	1700	2500
DEL_IBUF_D	2600	4000
DEL_IBUF_FCLK	1600	2500
DEL_IBUF_FOE	2700	3900
DEL_IBUF_FSR	2400	3500
DEL_IBUF_IMUX	1700	2400
DEL_IBUF_PLAIN.LVCMOS18	0	0
DEL_IBUF_PLAIN.LVCMOS18_ANY	0	0
DEL_IBUF_PLAIN.LVCMOS25	500	1000
DEL_IBUF_PLAIN.LVCMOS33	500	1000
DEL_IBUF_PLAIN.LVTTL	500	1000
DEL_IBUF_SCHMITT.LVCMOS15	4000	6000
DEL_IBUF_SCHMITT.LVCMOS18	3000	4000
DEL_IBUF_SCHMITT.LVCMOS18_ANY	3000	4000
DEL_IBUF_SCHMITT.LVCMOS25	2500	3000
DEL_IBUF_SCHMITT.LVCMOS33	2000	3000
DEL_IBUF_SCHMITT.LVTTL	2000	3000
DEL_IMUX_CT	2000	2500
DEL_IMUX_OR	900	1600
DEL_IMUX_PT	500	800
DEL_MC_FOE	1700	1700
DEL_OBUF_FAST.LVCMOS15	2800	4300
DEL_OBUF_FAST.LVCMOS18	1900	2800
DEL_OBUF_FAST.LVCMOS18_ANY	1900	2800
DEL_OBUF_FAST.LVCMOS25	6700	8800
DEL_OBUF_FAST.LVCMOS33	8900	12800
DEL_OBUF_FAST.LVTTL	8900	12800
DEL_OBUF_OE	5300	6100
DEL_OBUF_SLOW.LVCMOS15	6800	10300
DEL_OBUF_SLOW.LVCMOS18	5400	7800
DEL_OBUF_SLOW.LVCMOS18_ANY	5400	7800
DEL_OBUF_SLOW.LVCMOS25	9200	12800
DEL_OBUF_SLOW.LVCMOS33	11400	16800
DEL_OBUF_SLOW.LVTTL	11400	16800
DEL_SR_Q	1700	2000
DEL_UIM_IMUX	1500	3000
HOLD_CE_CLK	0	0
HOLD_D_CLK_IBUF_FCLK	400	400
HOLD_D_CLK_IBUF_PT	0	0
HOLD_D_CLK_PT_FCLK	400	400
HOLD_D_CLK_PT_PT	0	0
SETUP_CE_CLK	900	1300
SETUP_D_CLK_IBUF_FCLK	1400	1800
SETUP_D_CLK_IBUF_PT	2000	2600
SETUP_D_CLK_PT_FCLK	1400	1800
SETUP_D_CLK_PT_PT	2000	2600
WIDTH_CLK	1500	2500
WIDTH_CLK_PT	5000	7500
WIDTH_SR	5000	7500

IMUX bits

Row	Column
Row	0	2	4	6	8	10	12	14	16	18	20	22	24	26	28	30
0	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
2	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
3	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
4	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
5	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
6	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
7	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
8	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
9	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
10	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
11	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
12	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
13	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
14	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
15	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
16	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
17	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
18	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
19	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
28	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
29	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
30	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
31	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
32	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
33	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
34	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
35	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
36	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
37	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
38	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
39	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
40	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
41	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
42	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
43	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
44	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
45	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
46	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
47	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X

IM[0].MUX	[0, 0]	[0, 2]	[0, 4]	[0, 6]	[0, 8]	[0, 10]	[0, 12]	[0, 14]	[0, 16]	[0, 18]	[0, 20]	[0, 22]	[0, 24]	[0, 26]	[0, 28]	[0, 30]
IOB_0_0	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_11	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_6	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_1	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_12	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_8	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_4	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_0	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_12	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_8	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_4	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_5	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[1].MUX	[1, 0]	[1, 2]	[1, 4]	[1, 6]	[1, 8]	[1, 10]	[1, 12]	[1, 14]	[1, 16]	[1, 18]	[1, 20]	[1, 22]	[1, 24]	[1, 26]	[1, 28]	[1, 30]
IOB_0_1	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_12	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_13	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_3	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_15	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_13	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_14	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_15	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_8	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_2	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_2	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_6	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[2].MUX	[2, 0]	[2, 2]	[2, 4]	[2, 6]	[2, 8]	[2, 10]	[2, 12]	[2, 14]	[2, 16]	[2, 18]	[2, 20]	[2, 22]	[2, 24]	[2, 26]	[2, 28]	[2, 30]
IOB_0_2	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_3	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_7	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_15	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_14	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_11	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_15	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_9	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_11	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_4	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_7	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[3].MUX	[3, 0]	[3, 2]	[3, 4]	[3, 6]	[3, 8]	[3, 10]	[3, 12]	[3, 14]	[3, 16]	[3, 18]	[3, 20]	[3, 22]	[3, 24]	[3, 26]	[3, 28]	[3, 30]
IOB_0_3	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_15	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_5	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_2	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_9	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_10	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_7	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_11	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_4	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_7	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_0	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_8	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[4].MUX	[4, 0]	[4, 2]	[4, 4]	[4, 6]	[4, 8]	[4, 10]	[4, 12]	[4, 14]	[4, 16]	[4, 18]	[4, 20]	[4, 22]	[4, 24]	[4, 26]	[4, 28]	[4, 30]
IOB_0_4	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_1	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_10	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_15	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_13	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_5	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_6	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_3	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_7	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_1_15	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_3	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_9	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[5].MUX	[5, 0]	[5, 2]	[5, 4]	[5, 6]	[5, 8]	[5, 10]	[5, 12]	[5, 14]	[5, 16]	[5, 18]	[5, 20]	[5, 22]	[5, 24]	[5, 26]	[5, 28]	[5, 30]
IOB_0_5	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_12	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_12	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_5	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_10	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_9	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_2	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_5	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_3	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[6].MUX	[6, 0]	[6, 2]	[6, 4]	[6, 6]	[6, 8]	[6, 10]	[6, 12]	[6, 14]	[6, 16]	[6, 18]	[6, 20]	[6, 22]	[6, 24]	[6, 26]	[6, 28]	[6, 30]
IOB_0_6	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_10	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_5	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_7	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_0	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_6	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_5	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_13	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_14	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_1	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[7].MUX	[7, 0]	[7, 2]	[7, 4]	[7, 6]	[7, 8]	[7, 10]	[7, 12]	[7, 14]	[7, 16]	[7, 18]	[7, 20]	[7, 22]	[7, 24]	[7, 26]	[7, 28]	[7, 30]
IOB_0_7	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_0	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_4	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_0	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_2	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_12	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_2	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_1	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_9	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_0	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[8].MUX	[8, 0]	[8, 2]	[8, 4]	[8, 6]	[8, 8]	[8, 10]	[8, 12]	[8, 14]	[8, 16]	[8, 18]	[8, 20]	[8, 22]	[8, 24]	[8, 26]	[8, 28]	[8, 30]
IOB_0_8	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_14	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_11	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_14	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_11	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_4	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_8	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_14	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_13	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_5	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[9].MUX	[9, 0]	[9, 2]	[9, 4]	[9, 6]	[9, 8]	[9, 10]	[9, 12]	[9, 14]	[9, 16]	[9, 18]	[9, 20]	[9, 22]	[9, 24]	[9, 26]	[9, 28]	[9, 30]
IOB_0_9	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_13	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_9	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_6	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_8	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_7	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_0	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_10	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_10	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_9	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_1	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[10].MUX	[10, 0]	[10, 2]	[10, 4]	[10, 6]	[10, 8]	[10, 10]	[10, 12]	[10, 14]	[10, 16]	[10, 18]	[10, 20]	[10, 22]	[10, 24]	[10, 26]	[10, 28]	[10, 30]
IOB_0_1	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_2	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_8	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_4	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_1	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_3	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_3	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_12	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_6	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_6	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[11].MUX	[11, 0]	[11, 2]	[11, 4]	[11, 6]	[11, 8]	[11, 10]	[11, 12]	[11, 14]	[11, 16]	[11, 18]	[11, 20]	[11, 22]	[11, 24]	[11, 26]	[11, 28]	[11, 30]
IOB_0_6	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_1	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_12	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_7	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_2	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_3	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_15	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_11	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_7	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_3	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[12].MUX	[12, 0]	[12, 2]	[12, 4]	[12, 6]	[12, 8]	[12, 10]	[12, 12]	[12, 14]	[12, 16]	[12, 18]	[12, 20]	[12, 22]	[12, 24]	[12, 26]	[12, 28]	[12, 30]
IOB_0_0	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_0	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_8	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_1	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_0	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_4	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_0	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_2	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_9	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_6	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_4	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_9	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[13].MUX	[13, 0]	[13, 2]	[13, 4]	[13, 6]	[13, 8]	[13, 10]	[13, 12]	[13, 14]	[13, 16]	[13, 18]	[13, 20]	[13, 22]	[13, 24]	[13, 26]	[13, 28]	[13, 30]
IOB_0_1	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_10	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_11	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_3	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_12	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_5	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_7	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_12	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_14	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_5	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_2	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[14].MUX	[14, 0]	[14, 2]	[14, 4]	[14, 6]	[14, 8]	[14, 10]	[14, 12]	[14, 14]	[14, 16]	[14, 18]	[14, 20]	[14, 22]	[14, 24]	[14, 26]	[14, 28]	[14, 30]
IOB_0_9	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_12	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_4	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_6	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_14	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_6	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_3	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_3	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_8	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_0	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_1	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_5	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[15].MUX	[15, 0]	[15, 2]	[15, 4]	[15, 6]	[15, 8]	[15, 10]	[15, 12]	[15, 14]	[15, 16]	[15, 18]	[15, 20]	[15, 22]	[15, 24]	[15, 26]	[15, 28]	[15, 30]
IOB_0_8	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_15	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_7	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_14	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_1	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_7	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_5	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_15	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_5	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_4	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_8	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[16].MUX	[16, 0]	[16, 2]	[16, 4]	[16, 6]	[16, 8]	[16, 10]	[16, 12]	[16, 14]	[16, 16]	[16, 18]	[16, 20]	[16, 22]	[16, 24]	[16, 26]	[16, 28]	[16, 30]
IOB_0_3	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_3	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_5	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_2	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_8	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_8	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_8	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_1	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_11	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_1	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_0	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_6	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[17].MUX	[17, 0]	[17, 2]	[17, 4]	[17, 6]	[17, 8]	[17, 10]	[17, 12]	[17, 14]	[17, 16]	[17, 18]	[17, 20]	[17, 22]	[17, 24]	[17, 26]	[17, 28]	[17, 30]
IOB_0_7	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_14	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_10	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_0	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_13	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_9	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_14	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_10	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_13	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_7	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[18].MUX	[18, 0]	[18, 2]	[18, 4]	[18, 6]	[18, 8]	[18, 10]	[18, 12]	[18, 14]	[18, 16]	[18, 18]	[18, 20]	[18, 22]	[18, 24]	[18, 26]	[18, 28]	[18, 30]
IOB_0_4	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_2	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_9	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_15	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_11	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_10	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_4	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_9	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_6	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_9	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_3	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[19].MUX	[19, 0]	[19, 2]	[19, 4]	[19, 6]	[19, 8]	[19, 10]	[19, 12]	[19, 14]	[19, 16]	[19, 18]	[19, 20]	[19, 22]	[19, 24]	[19, 26]	[19, 28]	[19, 30]
IOB_0_3	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_15	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_13	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_4	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_10	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_11	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_2	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_0	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_4	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_2	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[20].MUX	[28, 0]	[28, 2]	[28, 4]	[28, 6]	[28, 8]	[28, 10]	[28, 12]	[28, 14]	[28, 16]	[28, 18]	[28, 20]	[28, 22]	[28, 24]	[28, 26]	[28, 28]	[28, 30]
IOB_0_2	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_11	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_10	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_0	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_15	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_12	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_14	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_12	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_1_15	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[21].MUX	[29, 0]	[29, 2]	[29, 4]	[29, 6]	[29, 8]	[29, 10]	[29, 12]	[29, 14]	[29, 16]	[29, 18]	[29, 20]	[29, 22]	[29, 24]	[29, 26]	[29, 28]	[29, 30]
IOB_0_5	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_13	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_6	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_5	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_9	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_13	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_6	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_13	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_10	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_8	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_7	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[22].MUX	[30, 0]	[30, 2]	[30, 4]	[30, 6]	[30, 8]	[30, 10]	[30, 12]	[30, 14]	[30, 16]	[30, 18]	[30, 20]	[30, 22]	[30, 24]	[30, 26]	[30, 28]	[30, 30]
IOB_0_1	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_12	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_7	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_2	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_13	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_9	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_5	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_1	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_13	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_9	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[23].MUX	[31, 0]	[31, 2]	[31, 4]	[31, 6]	[31, 8]	[31, 10]	[31, 12]	[31, 14]	[31, 16]	[31, 18]	[31, 20]	[31, 22]	[31, 24]	[31, 26]	[31, 28]	[31, 30]
IOB_0_2	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_3	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_9	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_5	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_2	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_3	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_4	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_13	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_7	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_7	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[24].MUX	[32, 0]	[32, 2]	[32, 4]	[32, 6]	[32, 8]	[32, 10]	[32, 12]	[32, 14]	[32, 16]	[32, 18]	[32, 20]	[32, 22]	[32, 24]	[32, 26]	[32, 28]	[32, 30]
IOB_0_9	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_13	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_11	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_4	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_0	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_4	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_14	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_0	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_9	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_3	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[25].MUX	[33, 0]	[33, 2]	[33, 4]	[33, 6]	[33, 8]	[33, 10]	[33, 12]	[33, 14]	[33, 16]	[33, 18]	[33, 20]	[33, 22]	[33, 24]	[33, 26]	[33, 28]	[33, 30]
IOB_0_5	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_0	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_8	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_15	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_15	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_12	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_0	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_9	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_12	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_5	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_12	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[26].MUX	[34, 0]	[34, 2]	[34, 4]	[34, 6]	[34, 8]	[34, 10]	[34, 12]	[34, 14]	[34, 16]	[34, 18]	[34, 20]	[34, 22]	[34, 24]	[34, 26]	[34, 28]	[34, 30]
IOB_0_7	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_0	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_5	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_3	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_10	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_11	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_8	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_12	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_4	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_8	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_7	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[27].MUX	[35, 0]	[35, 2]	[35, 4]	[35, 6]	[35, 8]	[35, 10]	[35, 12]	[35, 14]	[35, 16]	[35, 18]	[35, 20]	[35, 22]	[35, 24]	[35, 26]	[35, 28]	[35, 30]
IOB_0_5	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_2	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_11	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_0	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_14	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_6	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_7	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_10	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_8	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_1_15	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[28].MUX	[36, 0]	[36, 2]	[36, 4]	[36, 6]	[36, 8]	[36, 10]	[36, 12]	[36, 14]	[36, 16]	[36, 18]	[36, 20]	[36, 22]	[36, 24]	[36, 26]	[36, 28]	[36, 30]
IOB_0_0	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_11	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_13	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_6	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_11	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_10	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_2	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_3	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_6	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_4	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_0	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_8	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[29].MUX	[37, 0]	[37, 2]	[37, 4]	[37, 6]	[37, 8]	[37, 10]	[37, 12]	[37, 14]	[37, 16]	[37, 18]	[37, 20]	[37, 22]	[37, 24]	[37, 26]	[37, 28]	[37, 30]
IOB_0_6	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_10	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_6	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_1	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_3_1	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_7	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_6	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_14	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_5	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_2	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_1	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[30].MUX	[38, 0]	[38, 2]	[38, 4]	[38, 6]	[38, 8]	[38, 10]	[38, 12]	[38, 14]	[38, 16]	[38, 18]	[38, 20]	[38, 22]	[38, 24]	[38, 26]	[38, 28]	[38, 30]
IOB_0_4	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_1	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_4	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_1	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_9	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_13	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_3	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_2	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_10	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_1	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_2	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_6	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[31].MUX	[39, 0]	[39, 2]	[39, 4]	[39, 6]	[39, 8]	[39, 10]	[39, 12]	[39, 14]	[39, 16]	[39, 18]	[39, 20]	[39, 22]	[39, 24]	[39, 26]	[39, 28]	[39, 30]
IOB_0_3	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_15	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_12	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_14	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_12	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_5	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_15	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_15	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_14	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_6	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_3	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_9	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[32].MUX	[40, 0]	[40, 2]	[40, 4]	[40, 6]	[40, 8]	[40, 10]	[40, 12]	[40, 14]	[40, 16]	[40, 18]	[40, 20]	[40, 22]	[40, 24]	[40, 26]	[40, 28]	[40, 30]
IOB_0_8	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_14	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_10	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_7	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_8	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_8	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_11	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_11	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_0	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_4	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_5	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[33].MUX	[41, 0]	[41, 2]	[41, 4]	[41, 6]	[41, 8]	[41, 10]	[41, 12]	[41, 14]	[41, 16]	[41, 18]	[41, 20]	[41, 22]	[41, 24]	[41, 26]	[41, 28]	[41, 30]
IOB_0_7	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_2	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_13	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_5	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_8	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_4	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_0	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_12	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_8	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_4	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_0	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_7	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[34].MUX	[42, 0]	[42, 2]	[42, 4]	[42, 6]	[42, 8]	[42, 10]	[42, 12]	[42, 14]	[42, 16]	[42, 18]	[42, 20]	[42, 22]	[42, 24]	[42, 26]	[42, 28]	[42, 30]
IOB_0_6	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_14	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_7	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_6	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_9	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_5	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_7	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_14	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_11	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_9	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_10	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_14	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[35].MUX	[43, 0]	[43, 2]	[43, 4]	[43, 6]	[43, 8]	[43, 10]	[43, 12]	[43, 14]	[43, 16]	[43, 18]	[43, 20]	[43, 22]	[43, 24]	[43, 26]	[43, 28]	[43, 30]
IOB_0_0	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_1	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_9	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_2	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_10	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_12	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_3	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_10	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_7	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_8	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[36].MUX	[44, 0]	[44, 2]	[44, 4]	[44, 6]	[44, 8]	[44, 10]	[44, 12]	[44, 14]	[44, 16]	[44, 18]	[44, 20]	[44, 22]	[44, 24]	[44, 26]	[44, 28]	[44, 30]
IOB_0_2	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_10	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_12	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_4	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_11	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_8	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_8	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_13	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_5	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_6	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_3	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_15	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[37].MUX	[45, 0]	[45, 2]	[45, 4]	[45, 6]	[45, 8]	[45, 10]	[45, 12]	[45, 14]	[45, 16]	[45, 18]	[45, 20]	[45, 22]	[45, 24]	[45, 26]	[45, 28]	[45, 30]
IOB_0_8	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_13	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_4	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_7	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_12	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_10	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_4	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_0_10	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_9	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_1	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_2	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_11	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[38].MUX	[46, 0]	[46, 2]	[46, 4]	[46, 6]	[46, 8]	[46, 10]	[46, 12]	[46, 14]	[46, 16]	[46, 18]	[46, 20]	[46, 22]	[46, 24]	[46, 26]	[46, 28]	[46, 30]
IOB_0_9	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_0_11	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_8	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_14	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_13	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_13	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
MC_0_6	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_0	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_6	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_5	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_2_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_13	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

IM[39].MUX	[47, 0]	[47, 2]	[47, 4]	[47, 6]	[47, 8]	[47, 10]	[47, 12]	[47, 14]	[47, 16]	[47, 18]	[47, 20]	[47, 22]	[47, 24]	[47, 26]	[47, 28]	[47, 30]
IOB_0_4	0	1	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_3	1	0	1	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_1_6	1	1	0	0	1	1	1	1	0	1	1	1	1	1	1	1
IOB_2_3	1	1	1	0	0	1	1	1	0	1	1	1	1	1	1	1
IOB_2_14	1	1	1	0	1	0	1	1	0	1	1	1	1	1	1	1
IOB_3_3	1	1	1	0	1	1	0	1	0	1	1	1	1	1	1	1
IOB_3_15	1	1	1	1	1	1	1	1	0	0	1	1	0	1	1	1
MC_1_2	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1
MC_1_12	1	1	1	1	1	1	1	1	0	1	1	0	0	1	1	1
MC_2_2	1	1	1	1	1	1	1	1	0	1	1	1	0	0	1	1
MC_3_1	1	1	1	1	1	1	1	1	0	1	1	1	0	1	0	1
MC_3_6	1	1	1	1	1	1	1	1	0	1	1	1	0	1	1	0
VCC	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

MC bits

Row	Column
Row	0	1	2	3	4	5	6	7	8
0	X	X	X	X	X	X	X	X	X
1	X	X	X	X	X	X	X	X	X
2	X	X	X	X	X	X	X	X	X

SET_MUX	[0, 1]	[0, 0]
PT	0	0
CT6	0	1
FSR	1	0
GND	1	1

RST_MUX	[0, 3]	[0, 2]
PT	0	0
CT5	0	1
FSR	1	0
GND	1	1

CLK_DDR	[0, 4]
Non-inverted	[0]

CLK_INV	[0, 7]
Non-inverted	[0]

CLK_MUX	[0, 6]	[0, 5]	[0, 8]
FCLK0	0	0	0
FCLK1	0	1	0
FCLK2	1	0	0
PT	1	1	0
CT4	1	1	1

MC_IOB_MUX	[1, 0]
REG	0
XOR	1

IBUF_MODE	[1, 1]
PLAIN	0
SCHMITT	1

REG_D_MUX	[1, 2]
IBUF	0
XOR	1

MC_ZIA_MUX	[1, 4]	[1, 3]
XOR	0	0
REG	0	1
NONE	1	1

IOB_ZIA_MUX	[1, 6]	[1, 5]
IBUF	0	0
REG	0	1
NONE	1	1

REG_MODE	[1, 8]	[1, 7]
DFF	0	0
TFF	0	1
LATCH	1	0
DFFCE	1	1

REG_INIT	[2, 0]
Inverted	~[0]

IOB_SLEW	[2, 1]
FAST	0
SLOW	1

IOB_TERM_ENABLE	[2, 2]
Non-inverted	[0]

OE_MUX	[2, 6]	[2, 5]	[2, 4]	[2, 3]
VCC	0	0	0	0
CT7	0	0	0	1
PT	0	0	1	0
FOE0	0	0	1	1
FOE1	0	1	0	0
FOE2	0	1	0	1
FOE3	0	1	1	0
IS_GND	0	1	1	1
OPEN_DRAIN	1	0	0	0
GND	1	1	1	1

XOR_MUX	[2, 8]	[2, 7]
GND	0	0
PT	0	1
PT_INV	1	0
VCC	1	1

JED mapping

JED offset	Bit
0	CLK_MUX[0]
1	CLK_INV
2	CLK_MUX[1]
3	CLK_MUX[2]
4	CLK_DDR
5	RST_MUX[0]
6	RST_MUX[1]
7	SET_MUX[0]
8	SET_MUX[1]
9	REG_MODE[0]
10	REG_MODE[1]
11	IOB_ZIA_MUX[0]
12	IOB_ZIA_MUX[1]
13	MC_ZIA_MUX[0]
14	MC_ZIA_MUX[1]
15	REG_D_MUX
16	IBUF_MODE
17	XOR_MUX[0]
18	XOR_MUX[1]
19	MC_IOB_MUX
20	OE_MUX[0]
21	OE_MUX[1]
22	OE_MUX[2]
23	OE_MUX[3]
24	IOB_TERM_ENABLE
25	IOB_SLEW
26	REG_INIT

Global bits

Row	Column
Row	0	2	4	6	8	133	134	135	136	137	138	242	243	244	245	246	247	248	249	250	251	252	253	254	255	256	257	258	259	260	261	262	263	264	265	266	267	268	269	270	271	272	273
23	-	-	-	-	-	X	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	X	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
73	-	-	-	-	-	-	-	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
96	X	X	X	X	X	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
97	-	-	-	-	-	-	-	-	-	-	-	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X

FCLK0_ENABLE	[23, 133]
Non-inverted	[0]

FCLK1_ENABLE	[23, 134]
Non-inverted	[0]

FCLK2_ENABLE	[23, 135]
Non-inverted	[0]

TERM_MODE	[23, 136]
KEEPER	0
PULLUP	1

IBUF_VOLT	[23, 137]
HIGH	0
LOW	1

OBUF_VOLT	[23, 138]
HIGH	0
LOW	1

FOE0_MUX	[24, 134]	[24, 133]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

FOE1_MUX	[24, 136]	[24, 135]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

FOE3_MUX	[24, 138]	[24, 137]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

FSR_INV	[73, 135]
Inverted	~[0]

FSR_ENABLE	[73, 136]
Non-inverted	[0]

FOE2_MUX	[73, 138]	[73, 137]
IBUF_INV	0	0
IBUF	0	1
MC	1	0
NONE	1	1

READ_PROT	[96, 0]	[96, 2]	[96, 4]	[96, 6]
Inverted	~[3]	~[2]	~[1]	~[0]

DONE	[96, 8]
Inverted	~[0]

USERCODE	[97, 242]	[97, 243]	[97, 244]	[97, 245]	[97, 246]	[97, 247]	[97, 248]	[97, 249]	[97, 250]	[97, 251]	[97, 252]	[97, 253]	[97, 254]	[97, 255]	[97, 256]	[97, 257]	[97, 258]	[97, 259]	[97, 260]	[97, 261]	[97, 262]	[97, 263]	[97, 264]	[97, 265]	[97, 266]	[97, 267]	[97, 268]	[97, 269]	[97, 270]	[97, 271]	[97, 272]	[97, 273]
Non-inverted	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

JED mapping

JED offset	Bit
0	FCLK0_ENABLE
1	FCLK1_ENABLE
2	FCLK2_ENABLE
3	FSR_INV
4	FSR_ENABLE
5	FOE0_MUX[0]
6	FOE0_MUX[1]
7	FOE1_MUX[0]
8	FOE1_MUX[1]
9	FOE2_MUX[0]
10	FOE2_MUX[1]
11	FOE3_MUX[0]
12	FOE3_MUX[1]
13	TERM_MODE
14	IBUF_VOLT
15	OBUF_VOLT