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Contents:
Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Xilinx XPLA3 CPLDs
Xilinx Coolrunner II CPLDs
Introduction
Device structure
Bitstream structure
Database — devices
JTAG interface
Xilinx FPGAs
Project Combine
Xilinx Coolrunner II CPLDs
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Xilinx Coolrunner II CPLDs
Contents:
Introduction
Devices
Packages
Device pins
Device structure
Overview
AIM and FB inputs
Product terms
Sum term, XOR gate
Register
Macrocell and IOB outputs
Input/output buffer
Global networks
Clock divider
Bank configuration
Misc configuration
Bitstream structure
Database — devices
XC2C32
XC2C32A, XA2C32A
XC2C64
XC2C64A, XA2C64A
XC2C128, XA2C128
XC2C256, XA2C256
XC2C384, XA2C384
XC2C512
JTAG interface
IR
Boundary scan register
ISP instructions
Programming sequence