Project Combine
Contents:
Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Xilinx XPLA3 CPLDs
Xilinx Coolrunner II CPLDs
Introduction
Device structure
Bitstream structure
Database — devices
XC2C32
XC2C32A, XA2C32A
XC2C64
XC2C64A, XA2C64A
XC2C128, XA2C128
XC2C256, XA2C256
XC2C384, XA2C384
XC2C512
JTAG interface
Xilinx FPGAs
Project Combine
Xilinx Coolrunner II CPLDs
Database — devices
View page source
Database — devices
Contents:
XC2C32
I/O pins
Speed data
IMUX bits
MC bits
JED mapping
Global bits
JED mapping
XC2C32A, XA2C32A
I/O pins
Speed data
IMUX bits
MC bits
JED mapping
Global bits
JED mapping
XC2C64
I/O pins
Speed data
IMUX bits
MC bits
JED mapping
Global bits
JED mapping
XC2C64A, XA2C64A
I/O pins
Speed data
IMUX bits
MC bits
JED mapping
Global bits
JED mapping
XC2C128, XA2C128
I/O pins
Speed data
IMUX bits
MC bits
JED mapping — MCs with IOBs
JED mapping — MCs without IOBs
Global bits
JED mapping
XC2C256, XA2C256
I/O pins
Speed data
IMUX bits
MC bits
JED mapping — MCs with IOBs
JED mapping — MCs without IOBs
Global bits
JED mapping
XC2C384, XA2C384
I/O pins
Speed data
IMUX bits
MC bits
JED mapping — MCs with IOBs
JED mapping — MCs without IOBs
Global bits
JED mapping
XC2C512
I/O pins
Speed data
IMUX bits
MC bits
JED mapping — MCs with IOBs
JED mapping — MCs without IOBs
Global bits
JED mapping