Project Combine

Contents:

  • Xilinx XC9500, XC9500XL, XC9500XV CPLDs
  • Xilinx XPLA3 CPLDs
  • Xilinx Coolrunner II CPLDs
  • Xilinx FPGAs
    • XC4000E
    • XC4000EX
    • XC4000XLA
    • XC4000XV
    • Spartan XL
    • XC5200
    • Virtex
      • Configurable Logic Block
      • Block RAM
      • Input/Output
      • Corners
      • Delay Locked Loop
      • PCI Logic
      • Clock interconnect
      • Configuration registers
    • Virtex 2
    • Spartan 3
    • FPGAcore
    • Spartan 6
    • Virtex 4
    • Virtex 5
    • Virtex 6
    • Virtex 7
Project Combine
  • Xilinx FPGAs
  • Virtex
  • View page source

Virtex

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

  • Configurable Logic Block
    • Bitstream
  • Block RAM
    • Bitstream — left side
    • Bitstream — right side
    • Bitstream — middle
    • Bitstream — column bottom
    • Bitstream — column top
  • Input/Output
    • IO.L
    • IO.R
    • IO.B
    • IO.T
    • IOB.L.V
    • IOB.R.V
    • IOB.B.V
    • IOB.T.V
    • IOB.L.VE
    • IOB.R.VE
    • IOB.B.VE
    • IOB.T.VE
    • I/O buffers — Virtex
    • I/O buffers — Virtex E
  • Corners
    • CNR.BL
    • CNR.BR
    • CNR.TL
    • CNR.TR
  • Delay Locked Loop
    • DLL.BOT
    • DLLP.BOT
    • DLLS.BOT
    • DLL.TOP
    • DLLP.TOP
    • DLLS.TOP
  • PCI Logic
    • CLKL
    • CLKR
  • Clock interconnect
    • CLKB
    • CLKB_4DLL
    • CLKB_2DLL
    • CLKT
    • CLKT_4DLL
    • CLKT_2DLL
    • CLKV.CLKV
    • CLKV.GCLKV
    • CLKV_BRAM_BOT
    • CLKV_BRAM_TOP
  • Configuration registers
    • COR
    • CTL
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