FPGAcore

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

• General interconnect
  • Bitstream — interconnect tiles
• Configurable Logic Block
  • Bitstream
  • RESERVED_ANDOR
• Clock interconnect
  • Clock source — spine bottom and top
  • The CLKC clock center tile
  • The GCLKVM secondary clock center tiles
  • The GCLKVC clock spine distribution tiles
  • The GCLKH clock row distribution tiles
• Input / Output
  • I/O interface
  • I/O buffer tiles
• Corners
  • Lower left
  • Upper left
  • Lower right
  • Upper right
• Configuration registers
  • COR.FC
  • CTL.S3