Spartan 6

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

• General interconnect
  • Bitstream — normal tile
  • Bitstream — IOI tile
  • Bitstream — interface tiles
• Configurable Logic Block
  • Bitstream — CLEXL
  • Bitstream — CLEXM
• Block RAM
  • Bitstream
• DSP
  • Bitstream
• Clock interconnect
  • Bitstream — bottom tile
  • Bitstream — top tile
  • Bitstream — left tile
  • Bitstream — right tile
  • Bitstream — HCLK
  • Bitstream — HCLK_CLEXL
  • Bitstream — HCLK_CLEXM
  • Bitstream — HCLK_IOI
  • Bitstream — HCLK_GTP
  • Bitstream — HCLK_ROW
  • Bitstream — CLKC
  • Bitstream — DCM_BUFPLL
  • Bitstream — PLL_BUFPLL_OUT0
  • Bitstream — PLL_BUFPLL_OUT1
  • Bitstream — PLL_BUFPLL_B
  • Bitstream — PLL_BUFPLL_T
  • Bitstream — PCILOGICSE
  • PCI_CE_DELAY
• Input/Output
  • Bitstream — IOI.LR
  • Bitstream — IOI.BT
  • Bitstream — IOB
  • Tables
• Memory Controller Block
  • Bitstream
• PCI Express
  • Bitstream
• Multi-gigabit transceivers
  • Bitstream
• Digital clock manager
  • Bitstream
• Phase-locked loop
  • Bitstream
  • Tables
• Corners
  • Lower left
  • Upper left
  • Lower right
  • Upper right
• Configuration registers
  • COR1
  • COR2
  • CTL
  • CCLK_FREQ
  • HC_OPT
  • POWERDOWN
  • PU_GWE
  • PU_GTS
  • EYE_MASK
  • MODE
  • GENERAL[12]
  • GENERAL[34]
  • GENERAL5
  • TIMER
  • SEU_OPT
  • TESTMODE