Project Combine

Contents:

  • Xilinx XC9500, XC9500XL, XC9500XV CPLDs
  • Xilinx XPLA3 CPLDs
  • Xilinx Coolrunner II CPLDs
  • Xilinx FPGAs
    • XC4000E
    • XC4000EX
    • XC4000XLA
    • XC4000XV
    • Spartan XL
    • XC5200
    • Virtex
    • Virtex 2
    • Spartan 3
    • FPGAcore
    • Spartan 6
    • Virtex 4
      • Device geometry
      • General Interconnect
      • Configurable Logic Block
      • Block RAM
      • DSP
      • Input/Output
      • Configuration Center
      • Clock interconnect
      • Digital Clock Managers
      • Clock Companion Modules
      • Configuration registers
      • System monitor
      • Multi-gigabit transceivers
    • Virtex 5
    • Virtex 6
    • Virtex 7
Project Combine
  • Xilinx FPGAs
  • Virtex 4
  • View page source

Virtex 4

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

  • Device geometry
    • General structure
    • Bitstream geometry
  • General Interconnect
    • Bitstream
    • Bitstream — interface tile
  • Configurable Logic Block
    • Bitstream
  • Block RAM
    • FIFO mode
    • ECC mode
    • Bitstream
  • DSP
    • Bitstream
  • Input/Output
    • I/O banks and special functions
    • Bitstream
    • Tables
  • Configuration Center
    • Bitstream
  • Clock interconnect
    • CLK_HROW
    • HCLK
    • Spine clock terminators
    • Spine muxes — IOB
    • Spine muxes — DCM
    • MGT clock repeater
    • Row clock terminators
    • IO clock nodes
    • HCLK_MGT
    • I/O standard data
  • Digital Clock Managers
    • Bitstream
  • Clock Companion Modules
    • Bitstream
  • Configuration registers
    • COR
    • CTL
  • System monitor
    • Bitstream
  • Multi-gigabit transceivers
    • Bitstream
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