Virtex 2

Todo

io, dcm, corner, ppc, pcilogic, bitstream format, jtag, …

Contents:

• Introduction
  • Device table
• Device geometry
  • General structure
  • Clock rows
  • Clock spine
  • IO banks and IO buffers
  • PCI logic
  • Bitstream geometry
• General interconnect
  • Backbone
  • Input multiplexers
  • Primitive outputs
  • Terminators
  • PowerPC holes
  • Clock spine top and bottom
  • Bitstream — interconnect tiles
  • Bitstream — terminator tiles
  • Bitstream — PowerPC hole tiles
  • Bitstream — interface tiles
• Configurable Logic Block
  • LUTs
  • Wide multiplexers
  • Carry logic
  • Sum of products
  • Output multiplexers
  • Registers
  • Tristate buses and TBUFs
  • Bitstream
• Block RAM — Virtex 2, Spartan 3
  • The BRAM bel
  • The MULT bel — Virtex 2 and Spartan 3
  • The MULT bel — Spartan 3E and Spartan 3A
  • Bitstream
• Clock interconnect
  • Clock source — spine bottom and top
  • The GCLKC clock spine distribution tiles
  • The clock row distribution tiles
  • DCM output bus
• Input / Output
  • I/O interface
  • I/O buffers — Virtex 2
  • I/O buffers — Virtex 2 Pro
• Digital Clock Managers
  • DCM.V2
  • DCM.V2P
  • DESKEW_ADJUST
• Hard PowerPC 405 cores
• Multi-gigabit transceivers — Virtex 2 Pro
  • Bitstream
• Multi-gigabit transceivers — Virtex 2 Pro X
  • Bitstream
  • PMA_SPEED values
• Hard PCI logic
• Corners
  • Lower left
  • Upper left
  • Lower right
  • Upper right
  • I/O data — Virtex 2
  • I/O data — Virtex 2 Pro
• Configuration registers
  • COR
  • CTL