Virtex 7

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

• Device geometry
  • General structure
  • Bitstream geometry
• Interconnect
  • Bitstream
  • Bitstream — INTF
  • Bitstream — INTF.BRAM
  • Bitstream — INTF.DELAY
• Configurable Logic Block
  • Bitstream — CLBLL
  • Bitstream — CLBLM
• Block RAM
  • Bitstream
• DSP
  • Bitstream
• Input/Output
  • I/O banks and special functions
  • Bitstream — IO_HP_PAIR
  • Bitstream — IO_HP_BOT
  • Bitstream — IO_HP_TOP
  • Bitstream — IO_HR_PAIR
  • Bitstream — IO_HR_BOT
  • Bitstream — IO_HR_TOP
  • Bitstream — HCLK_IOI_HP
  • Bitstream — HCLK_IOI_HR
  • Tables — HP IO
  • Tables — HR IO
• Configuration Center
  • Bitstream
  • XADC
• Clock interconnect
  • HCLK
  • CLK_BUFG
  • CLK_HROW
  • CLK_BUFG_REBUF
  • CLK_BALI_REBUF
• Clock management tile
  • CMT
  • CMT_FIFO
  • MMCM Tables
  • PLL Tables
• PCI Express Gen2 cores
  • Bitstream
• PCI Express Gen3 cores
  • Bitstream
• GTP transceivers
  • GTP_COMMON
  • GTP_CHANNEL
  • GTP_COMMON_MID
  • GTP_CHANNEL_MID
• GTX transceivers
  • GTX_COMMON
  • GTX_CHANNEL
• GTH transceivers
  • GTH_COMMON
  • GTH_CHANNEL
• Configuration registers
  • COR
  • COR1
  • CTL
  • CTL1
  • BSPI
  • WBSTAR
  • TIMER
  • TESTMODE
  • TRIM0
  • TRIM1
  • TRIM2