Project Combine

Contents:

  • Xilinx XC9500, XC9500XL, XC9500XV CPLDs
  • Xilinx XPLA3 CPLDs
  • Xilinx Coolrunner II CPLDs
  • Xilinx FPGAs
    • XC4000E
    • XC4000EX
    • XC4000XLA
    • XC4000XV
    • Spartan XL
    • XC5200
    • Virtex
    • Virtex 2
    • Spartan 3
    • FPGAcore
    • Spartan 6
    • Virtex 4
    • Virtex 5
    • Virtex 6
      • Device geometry
      • Interconnect
      • Configurable Logic Block
      • Block RAM
      • DSP
      • Input/Output
      • Configuration Center
      • Clock interconnect
      • Clock management tile
      • Ethernet MACs
      • PCI Express cores
      • GTX transceivers
      • GTH transceivers
      • Configuration registers
    • Virtex 7
Project Combine
  • Xilinx FPGAs
  • Virtex 6
  • View page source

Virtex 6

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

  • Device geometry
    • General structure
    • Bitstream geometry
  • Interconnect
    • Bitstream
    • Bitstream — INTF
    • Bitstream — INTF.DELAY
  • Configurable Logic Block
    • Bitstream — CLBLL
    • Bitstream — CLBLM
  • Block RAM
    • Bitstream
  • DSP
    • Bitstream
  • Input/Output
    • I/O banks and special functions
    • Bitstream — IO
    • Bitstream — HCLK_IOI
    • Tables
  • Configuration Center
    • Bitstream
  • Clock interconnect
    • HCLK
    • CMT_BUFG_BOT
    • CMT_BUFG_TOP
    • PMVIOB
  • Clock management tile
    • CMT
    • Tables
  • Ethernet MACs
    • Bitstream
  • PCI Express cores
    • Bitstream
  • GTX transceivers
    • Bitstream
  • GTH transceivers
    • Bitstream
  • Configuration registers
    • COR
    • COR1
    • CTL
    • CTL1
    • TIMER
    • TESTMODE
    • TRIM
    • UNK1C
Previous Next

© Copyright 2023, Wanda.

Built with Sphinx using a theme provided by Read the Docs.