Spartan 3

Todo

intro document, bitstream format, other tiles, jtag, …

Contents:

• Introduction
  • Device table
• Device geometry
  • General structure
  • Clock rows
  • Primary vertical clock spine
  • Horizontal clock spine
  • Secondary vertical clock spines
  • IO banks and IO buffers
  • Bitstream geometry
• General interconnect
  • Backbone
  • Input multiplexers
  • Primitive outputs
  • Terminators
  • Long line splitters
  • Bitstream — interconnect tiles
  • Bitstream — LLH tiles
  • Bitstream — LLV tiles
  • Bitstream — interface tiles
• Configurable Logic Block
  • LUTs
  • Wide multiplexers
  • Carry logic
  • Output multiplexers — Spartan 3
  • Output multiplexers — Virtex 4
  • Registers
  • Bitstream
  • RESERVED_ANDOR
• Block RAM
  • Bitstream
  • Default option values
• DSP
  • Bitstream
• Clock interconnect
  • Clock source — spine bottom and top
  • Clock source — left and right
  • The CLKC clock center tile
  • The CLKC_50A clock center tile
  • The GCLKVM secondary clock center tiles
  • The GCLKVC clock spine distribution tiles
  • The GCLKH clock row distribution tiles
• Input / Output
  • I/O interface
  • I/O buffers — Spartan 3
  • I/O buffers — Spartan 3E
  • I/O buffers — Spartan 3A
• Digital Clock Managers — Spartan 3
  • DCM.S3
  • DESKEW_ADJUST
• Digital Clock Managers — Spartan 3E, 3A
  • DCM.S3E.BL
  • DCM.S3E.BR
  • DCM.S3E.TL
  • DCM.S3E.TR
  • DCM.S3E.LB
  • DCM.S3E.LT
  • DCM.S3E.RB
  • DCM.S3E.RT
  • DESKEW_ADJUST
• Corners
  • Lower left
  • Upper left
  • Lower right
  • Upper right
  • I/O data — Spartan 3
  • I/O data — Spartan 3E
  • I/O data — Spartan 3A
• Configuration registers — Spartan 3, Spartan 3E
  • COR.S3
  • COR.S3E
  • CTL.S3
• Configuration registers — Spartan 3A and 3A DSP
  • COR1.S3A
  • COR2.S3A
  • CTL.S3A
  • CCLK_FREQ
  • HC_OPT
  • POWERDOWN
  • PU_GWE
  • PU_GTS
  • MODE
  • GENERAL[12]
  • SEU_OPT