Input/Output

I/O banks and special functions

Virtex 6 devices have a very regular I/O bank structure. There are up to four I/O columns in the device:

  • outer left (sometimes present)

  • inner left (always present)

  • inner right (always present)

  • outer right (sometimes present)

These columns consist entirely of IO tiles, with one tile per two interconnect rows. Every tile contains two I/O pads: IOB0 and IOB1. IOB0 is located in the bottom row of the tile, while IOB1 is located in the top row. Every I/O bank consists of exactly one region, or 40 I/O pads. The banks are numbered as follows:

  • the bank in region c + i of outer left column (where c is the region containing the top half of the CFG tile) has number 15 + i

  • the bank in region c + i of inner left column has number 25 + i

  • the bank in region c + i of inner right column has number 35 + i

  • the bank in region c + i of outer right column has number 45 + i

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input and true differential output is supported on all pins of the device.

IOB1 pads in the 8 rows surrounding the HCLK row (that is, rows 17, 19, 21, 23) are considered “clock-capable”. They can drive BUFIODQS buffers via dedicated connections. The ones in rows 19 and 21 can drive BUFR buffers in this and two surrounding regions, and are considered “multi-region clock capable”, while the ones in rows 17 and 23 are considered “single-region clock capable”. While Xilinx documentation also considers corresponding IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

There are 8 IOB1s that are considered “global clock-capable” and can drive BUFGCTRL global buffers via dedicated interconnect. They are:

  • bank 24 rows 37, 39

  • bank 25 rows 1, 3

  • bank 34 rows 37, 39

  • bank 35 rows 1, 3

The IOB0 in rows 10 and 30 of every region is capable of being used as a VREF pad.

Each bank has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

  • bank 24: rows 4-5

  • bank 34: rows 0-1

  • banks 15, 25, 35: rows 6-7

  • all other banks: rows 14-15

In parallel or SPI configuration modes, some I/O pads in banks 24 and 34 are borrowed for configuration use:

  • bank 24 row 6: CSO_B

  • bank 24 row 7: RS[0]

  • bank 24 row 8: RS[1]

  • bank 24 row 9: FWE_B

  • bank 24 row 10: FOE_B/MOSI

  • bank 24 row 11: FCS_B

  • bank 24 row 12: D[0]/FS[0]

  • bank 24 row 13: D[1]/FS[1]

  • bank 24 row 14: D[2]/FS[2]

  • bank 24 row 15: D[3]

  • bank 24 row 24: D[4]

  • bank 24 row 25: D[5]

  • bank 24 row 26: D[6]

  • bank 24 row 27: D[7]

  • bank 24 row 28: D[8]

  • bank 24 row 29: D[9]

  • bank 24 row 30: D[10]

  • bank 24 row 31: D[11]

  • bank 24 row 32: D[12]

  • bank 24 row 33: D[13]

  • bank 24 row 34: D[14]

  • bank 24 row 35: D[15]

  • bank 34 row 2: A[16]

  • bank 34 row 3: A[17]

  • bank 34 row 4: A[18]

  • bank 34 row 5: A[19]

  • bank 34 row 6: A[20]

  • bank 34 row 7: A[21]

  • bank 34 row 8: A[22]

  • bank 34 row 9: A[23]

  • bank 34 row 10: A[24]

  • bank 34 row 11: A[25]

  • bank 34 row 12: D[16]/A[0]

  • bank 34 row 13: D[17]/A[1]

  • bank 34 row 14: D[18]/A[2]

  • bank 34 row 15: D[19]/A[3]

  • bank 34 row 24: D[20]/A[4]

  • bank 34 row 25: D[21]/A[5]

  • bank 34 row 26: D[22]/A[6]

  • bank 34 row 27: D[23]/A[7]

  • bank 34 row 28: D[24]/A[8]

  • bank 34 row 29: D[25]/A[9]

  • bank 34 row 30: D[26]/A[10]

  • bank 34 row 31: D[27]/A[11]

  • bank 34 row 32: D[28]/A[12]

  • bank 34 row 33: D[29]/A[13]

  • bank 34 row 34: D[30]/A[14]

  • bank 34 row 35: D[31]/A[15]

The SYSMON present on the device can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. If the device has a outer left IO column, the IOBs are located in banks 15 and 35; otherwise, they are located in banks 25 and 35. The IOBs are in the following tiles:

  • VP0/VN0: bank 35 rows 34-35

  • VP1/VN1: bank 35 rows 32-33

  • VP2/VN2: bank 35 rows 28-29

  • VP3/VN3: bank 35 rows 26-27

  • VP4/VN4: bank 35 rows 24-25

  • VP5/VN5: bank 35 rows 14-15

  • VP6/VN6: bank 35 rows 12-13

  • VP7/VN7: bank 35 rows 8-9

  • VP8/VN8: bank 15/25 rows 34-35

  • VP9/VN9: bank 15/25 rows 32-33

  • VP10/VN10: bank 15/25 rows 28-29

  • VP11/VN11: bank 15/25 rows 26-27

  • VP12/VN12: bank 15/25 rows 24-25

  • VP13/VN13: bank 15/25 rows 14-15

  • VP14/VN14: bank 15/25 rows 12-13

  • VP15/VN15: bank 15/25 rows 8-9

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

  • CCLK

  • CSI_B

  • DIN

  • DONE

  • DOUT_BUSY

  • HSWAPEN

  • INIT_B

  • M0, M1, M2

  • PROGRAM_B

  • RDWR_B

  • TCK, TDI, TDO, TMS

Bitstream — IO

IO bittile 0
RowColumn
01234567891011121314151617181920212223242526272829303132333435363738394041
0 --------------------------~ILOGIC0:INV.DOLOGIC0:MISR_RESET-----OLOGIC0:OFF_SR_SYNC[1]ILOGIC0:MUX.CLK[0]-OLOGIC0:INIT_FIFO_ADDR[10]---IOB0:IBUF_MODE[0]-
1 ---------------------------------OLOGIC0:INIT_ORANK1[0]ILOGIC0:MUX.CLK[3]-OLOGIC0:INIT_DLY_CNT[8]OLOGIC0:INIT_PIPE_DATA0[5]---IOB0:IBUF_MODE[1]
2 --------------------------------OLOGIC0:INIT_PIPE_DATA0[11]--ILOGIC0:MUX.CLK[7]-OLOGIC0:INIT_FIFO_ADDR[8]--IOB0:IBUF_MODE[3]-
3 ---------------------------OLOGIC0:MISR_ENABLE_FDBK------ILOGIC0:MUX.CLK[8]--OLOGIC0:INIT_PIPE_DATA0[3]---IOB0:VREF_SYSMON
4 --------------------------ILOGIC0:IFF_DELAY_ENABLEOLOGIC0:MISR_ENABLE--------OLOGIC0:INIT_FIFO_RESET[2]---IOB0:IBUF_MODE[4]-
5 ---------------------------~ILOGIC0:INIT_RANK1_PARTIAL[0]----OLOGIC0:INIT_PIPE_DATA0[9]OLOGIC0:INV.D6--OLOGIC0:INIT_FIFO_RESET[9]----IOB0:LVDS[0]
6 --------------------------~ILOGIC0:INIT_RANK1_PARTIAL[1]------OLOGIC0:INIT_ORANK1[1]ILOGIC0:MUX.CLK[1]-OLOGIC0:INTERFACE_TYPE---IOB0:NDRIVE[5]-
7 --------------------------ILOGIC0:IFF_TSBYPASS_ENABLEOLOGIC0:MISR_CLK_SELECT[0]-------ILOGIC0:MUX.CLK[5]OLOGIC0:INIT_FIFO_ADDR[9]----IOB0:PDRIVE[5]
8 --------------------------ILOGIC0:I_TSBYPASS_ENABLEOLOGIC0:MISR_CLK_SELECT[1]----OLOGIC0:INV.D5-ILOGIC0:MUX.CLK[9]ILOGIC0:MUX.CLK[10]OLOGIC0:INIT_FIFO_ADDR[7]OLOGIC0:INIT_PIPE_DATA1[5]IODELAY0:DELAY_TYPE[2]-IOB0:LVDS[1]-
9 --------------------------ILOGIC0:TSBYPASS_MUXILOGIC0:DYN_CLKDIV_INV_EN-----OLOGIC0:INIT_PIPE_DATA1[11]ILOGIC0:MUX.CLK[2]ILOGIC0:MUX.CLK[4]-OLOGIC0:INIT_FIFO_RESET[1]IODELAY0:DELAY_TYPE[3]--IOB0:OUTPUT_MISC[3]
10 ---------------------------ILOGIC0:INTERFACE_TYPE[1]-----OLOGIC0:INIT_ORANK1[2]-ILOGIC0:MUX.CLK[6]-OLOGIC0:INIT_FIFO_RESET[6]IODELAY0:ALT_DELAY_VALUE[4]-IOB0:PSLEW[4]-
11 ---------------------------------OLOGIC0:INV.D4OLOGIC0:MUX.CLK[0]-OLOGIC0:INIT_PIPE_DATA0[4]-IODELAY0:ALT_DELAY_VALUE[3]---
12 --------------------------~ILOGIC0:INIT_BITSLIPCNT[3]---------OLOGIC0:INIT_FIFO_ADDR[2]OLOGIC0:INIT_PIPE_DATA1[3]IODELAY0:ALT_DELAY_VALUE[2]-IOB0:DCI_MODE[1]-
13 --------------------------ILOGIC0:DYN_OCLK_INV_EN[0]~ILOGIC0:INV.OCLK2----OLOGIC0:INIT_LOADCNT[0]OLOGIC0:INIT_PIPE_DATA1[9]OLOGIC0:MUX.CLK[7]OLOGIC0:MUX.CLK[8]-OLOGIC0:INIT_DLY_CNT[5]IODELAY0:ALT_DELAY_VALUE[1]--IOB0:VR
14 ---------------------------ILOGIC0:DYN_OCLK_INV_EN[1]----OLOGIC0:INV.D3OLOGIC0:INIT_PIPE_DATA1[10]OLOGIC0:MUX.CLK[1]OLOGIC0:MUX.CLK[3]-OLOGIC0:INIT_FIFO_ADDR[1]IODELAY0:ALT_DELAY_VALUE[0]-IOB0:DCI_MODE[0]-
15 --------------------------ILOGIC0:INTERFACE_TYPE[0]------OLOGIC0:INIT_PIPE_DATA0[10]--OLOGIC0:INIT_PIPE_DATA1[4]-IODELAY0:DELAY_TYPE[1]---
16 --------------------------ILOGIC0:INTERFACE_TYPE[2]~ILOGIC0:INV.OCLK1-----OLOGIC0:INIT_ORANK1[3]--OLOGIC0:INIT_FIFO_RESET[0]-IODELAY0:IDELAY_VALUE_INIT[4]---
17 --------------------------ILOGIC0:DATA_WIDTH[0]~ILOGIC0:INV.CLK[0]-----OLOGIC0:INIT_PIPE_DATA0[8]OLOGIC0:MUX.CLK[2]--OLOGIC0:INIT_PIPE_DATA0[2]IODELAY0:IDELAY_VALUE_INIT[3]--IOB0:NSLEW[3]
18 ---------------------------ILOGIC0:DATA_WIDTH[1]------OLOGIC0:MUX.CLK[4]-OLOGIC0:INIT_FIFO_ADDR[3]-IODELAY0:IDELAY_VALUE_INIT[2]-IOB0:LVDS[2]-
19 ---------------------------~ILOGIC0:INIT_BITSLIPCNT[2]----OLOGIC0:INIT_LOADCNT[1]OLOGIC0:OFF_SR_SYNC[2]OLOGIC0:MUX.CLK[9]OLOGIC0:MUX.CLK[10]OLOGIC0:INIT_DLY_CNT[4]OLOGIC0:INIT_PIPE_DATA1[2]IODELAY0:IDELAY_VALUE_INIT[1]--IOB0:DCI_MODE[2]
20 --------------------------~ILOGIC0:INIT_BITSLIPCNT[1]-----OLOGIC0:INV.D2OLOGIC0:INIT_PIPE_DATA1[8]---OLOGIC0:INIT_FIFO_ADDR[0]IODELAY0:IDELAY_VALUE_INIT[0]-IOB0:PSLEW[3]-
21 --------------------------ILOGIC0:DATA_WIDTH[2]ILOGIC0:BITSLIP_ENABLE------OLOGIC0:MUX.CLK[5]-OLOGIC0:INIT_FIFO_RESET[3]OLOGIC0:WC_DELAYIODELAY0:CINVCTRL_SEL--IOB0:NDRIVE[4]
22 ---------------------------~ILOGIC0:INV.CLK[1]----OLOGIC0:INIT_ORANK1[4]-OLOGIC0:MUX.CLK[6]-OLOGIC0:INIT_FIFO_RESET[5]~OLOGIC0:INV.CLKPERFIODELAY0:INV.C-IOB0:LVDS[3]-
23 --------------------------ILOGIC0:DATA_WIDTH[3]ILOGIC0:DYN_CLK_INV_EN----OLOGIC0:INIT_PIPE_DATA0[7]OLOGIC0:INIT_LOADCNT[2]OLOGIC0:MUX.CLKDIV[7]OLOGIC0:MUX.CLKDIV[0]OLOGIC0:DDR3_BYPASSOLOGIC0:DDR3_DATA---IOB0:LVDS[4]
24 --------------------------ILOGIC0:INV.CLKDIV~ILOGIC0:INV.CLK[2]----OLOGIC0:INIT_PIPE_DATA1[7]OLOGIC0:INV.D1OLOGIC0:MUX.CLKDIV[1]-----IOB0:OUTPUT_MISC[1]-
25 ---------------------------~ILOGIC0:INIT_BITSLIPCNT[0]----OLOGIC0:OMUX[2]OLOGIC0:INIT_PIPE_DATA1[6]OLOGIC0:MUX.CLKDIV[8]OLOGIC0:MUX.CLKDIV[5]OLOGIC0:INIT_DLY_CNT[0]-~IODELAY0:INV.IDATAIN--IOB0:OUTPUT_MISC[2]
26 --------------------------~ILOGIC0:INIT_RANK1_PARTIAL[2]------OLOGIC0:OMUX[1]--OLOGIC0:INIT_PIPE_DATA0[1]OLOGIC0:INIT_PIPE_DATA1[1]IODELAY0:DELAY_TYPE[0]-~IOB0:PDRIVE[4]-
27 ---------------------------~ILOGIC0:INIT_RANK1_PARTIAL[3]----OLOGIC0:INIT_ORANK1[5]-OLOGIC0:MUX.CLKDIV[2]OLOGIC0:MUX.CLKDIV[3]--~IODELAY0:IDELAY_VALUE_CUR[0]--IOB0:PSLEW[2]
28 --------------------------ILOGIC0:INIT_BITSLIP[0]-----OLOGIC0:INIT_PIPE_DATA0[6]-OLOGIC0:MUX.CLKDIV[6]--OLOGIC0:INIT_FIFO_RESET[10]--IOB0:OUTPUT_ENABLE[0]-
29 ---------------------------~ILOGIC0:INIT_RANK2[0]----OLOGIC0:INIT_LOADCNT[3]---OLOGIC0:INIT_PIPE_DATA0[0]----IOB0:OUTPUT_ENABLE[1]
30 --------------------------~ILOGIC0:INIT_RANK3[0]--------OLOGIC0:MUX.CLKDIV[4]----IOB0:NSLEW[1]-
31 --------------------------ILOGIC0:SERDES_MODEILOGIC0:BITSLIP_SYNC-----OLOGIC0:SERDESILOGIC0:MUX.CLKB[0]--OLOGIC0:INIT_DLY_CNT[2]---IOB0:PSLEW[1]
32 --------------------------ILOGIC0:D_EMU-----OLOGIC0:TFF_SR_SYNC[0]-ILOGIC0:MUX.CLKB[2]--OLOGIC0:SERDES_MODE--IOB0:NSLEW[2]-
33 ---------------------------ILOGIC0:I_DELAY_ENABLE----OLOGIC0:INIT_TRANK1[0]--ILOGIC0:MUX.CLKB[7]-OLOGIC0:INIT_FIFO_RESET[7]---IOB0:LVDS[5]
34 --------------------------ILOGIC0:DATA_RATE-------ILOGIC0:MUX.CLKB[8]--OLOGIC0:INIT_PIPE_DATA1[0]--~IOB0:NDRIVE[3]-
35 ---------------------------~ILOGIC0:INIT_RANK1_PARTIAL[4]-------ILOGIC0:MUX.CLKB[5]--~IODELAY0:IDELAY_VALUE_CUR[1]--IOB0:OUTPUT_MISC[0]
36 --------------------------ILOGIC0:INIT_BITSLIP[1]------~OLOGIC0:OFF_SRVAL[2]------IOB0:OMUX-
37 ---------------------------~ILOGIC0:INIT_RANK2[1]-----OLOGIC0:INIT_TRANK1[1]ILOGIC0:MUX.CLKB[1]---~IODELAY0:INV.DATAIN--IOB0:PULL_DYNAMIC
38 --------------------------~ILOGIC0:INIT_RANK3[1]-----~OLOGIC0:OFF_SRVAL[0]-ILOGIC0:MUX.CLKB[4]-OLOGIC0:OFF_SR_SYNC[3]---IOB0:LVDS[6]-
39 ---------------------------~ILOGIC0:INIT_RANK2[2]----~OLOGIC0:OFF_INIT-ILOGIC0:MUX.CLKB[9]ILOGIC0:MUX.CLKB[10]~OLOGIC0:TFF_INITOLOGIC0:INIT_FIFO_ADDR[6]---IOB0:PSLEW[0]
40 --------------------------~ILOGIC0:IFF4_SRVALILOGIC0:DDR_CLK_EDGE[1]----~OLOGIC0:OFF_SRVAL[1]--ILOGIC0:MUX.CLKB[3]OLOGIC0:ODELAY_USED-----
41 --------------------------~ILOGIC0:IFF3_SRVAL~ILOGIC0:IFF4_INIT------ILOGIC0:MUX.CLKB[6]-OLOGIC0:INIT_FIFO_ADDR[5]-IODELAY0:DELAY_SRC[3]--IOB0:PDRIVE[3]
42 --------------------------~ILOGIC0:INIT_RANK3[2]------OLOGIC0:INIT_TRANK1[2]OLOGIC0:MUX.CLKB[1]-OLOGIC0:INIT_DLY_CNT[9]-IODELAY0:DELAY_SRC[4]-~IOB0:NDRIVE[2]-
43 ---------------------------ILOGIC0:INIT_BITSLIP[2]----OLOGIC0:OFF_SR_SYNC[0]OLOGIC0:SELFHEAL-OLOGIC0:MUX.CLKB[5]-~OLOGIC0:TFF_SRVAL[1]~IODELAY0:IDELAY_VALUE_CUR[2]--IOB0:NSLEW[4]
44 --------------------------~ILOGIC0:INIT_RANK2[3]-----OLOGIC0:CLK_RATIO[2]OLOGIC0:CLK_RATIO[3]-OLOGIC0:MUX.CLKB[7]OLOGIC0:MUX.CLKPERF~OLOGIC0:TFF_SRVAL[2]IODELAY0:DELAY_SRC[2]-IOB0:NSLEW[0]-
45 ---------------------------~ILOGIC0:IFF3_INIT-----OLOGIC0:CLK_RATIO[1]OLOGIC0:MUX.CLKB[8]-OLOGIC0:INIT_FIFO_RESET[12]IODELAY0:HIGH_PERFORMANCE_MODE---~IOB0:PDRIVE[2]
46 --------------------------~ILOGIC0:INIT_RANK3[3]-----OLOGIC0:CLK_RATIO[0]---~OLOGIC0:TFF_SRVAL[0]OLOGIC0:INIT_FIFO_ADDR[4]--IOB0:PULL[0]-
47 ---------------------------~ILOGIC0:IFF2_INIT-------OLOGIC0:MUX.CLKB[0]OLOGIC0:INIT_DLY_CNT[7]----IOB0:PULL[1]
48 --------------------------ILOGIC0:INIT_BITSLIP[3]-----OLOGIC0:INIT_TRANK1[3]~OLOGIC0:INV.T4OLOGIC0:MUX.CLKB[2]OLOGIC0:MUX.CLKB[4]OLOGIC0:TFF_SR_SYNC[1]---IOB0:PULL[2]-
49 ---------------------------ILOGIC0:INIT_BITSLIP[4]----~OLOGIC0:INV.T3~OLOGIC0:INV.T2---OLOGIC0:TRISTATE_WIDTHIODELAY0:DELAY_SRC[0]--~IOB0:NDRIVE[1]
50 --------------------------~ILOGIC0:INIT_RANK2[4]-----~OLOGIC0:INV.T1OLOGIC0:DATA_WIDTH[1]OLOGIC0:MUX.CLKB[9]OLOGIC0:MUX.CLKB[10]OLOGIC0:TFF_SR_USEDOLOGIC0:INIT_FIFO_RESET[4]IODELAY0:DELAY_SRC[1]-IOB0:LVDS[7]-
51 ---------------------------~ILOGIC0:INIT_RANK3[4]----OLOGIC0:DATA_WIDTH[5]OLOGIC0:DATA_WIDTH[3]----~IODELAY0:IDELAY_VALUE_CUR[3]--IOB0:OUTPUT_DELAY
52 --------------------------~ILOGIC0:IFF1_INIT-----OLOGIC0:DATA_WIDTH[2]OLOGIC0:DATA_WIDTH[6]OLOGIC0:MUX.CLKB[3]-OLOGIC0:INIT_ORANK2_PARTIAL[0]-IODELAY0:DELAY_TYPE[4]-~IOB0:PDRIVE[1]-
53 --------------------------ILOGIC0:DDR_CLK_EDGE[0]~ILOGIC0:IFF2_SRVAL----OLOGIC0:DATA_WIDTH[7]OLOGIC0:DATA_WIDTH[0]OLOGIC0:MUX.CLKB[6]OLOGIC0:MUX.CLKDIVB[6]OLOGIC0:INIT_ORANK2_PARTIAL[1]IODELAY0:ENABLE----
54 --------------------------ILOGIC0:IFF_SR_SYNCILOGIC0:SERDES----OLOGIC0:OFF_SR_USEDOLOGIC0:DATA_WIDTH[4]-OLOGIC0:MUX.CLKDIVB[0]-OLOGIC0:INIT_DLY_CNT[6]--~IOB0:DCIUPDATEMODE_ASREQUIRED-
55 --------------------------~ILOGIC0:IFF1_SRVAL~ILOGIC0:IFF_LATCH----OLOGIC0:INV.CLKDIV~OLOGIC0:INV.CLK1OLOGIC0:MUX.CLKDIVB[1]--OLOGIC0:INIT_ORANK2_PARTIAL[2]---IOB0:LVDS[8]
56 --------------------------~ILOGIC0:INIT_RANK3[5]-----~OLOGIC0:INV.CLK2-OLOGIC0:MUX.CLKDIVB[7]OLOGIC0:MUX.CLKDIVB[5]OLOGIC0:INIT_FIFO_RESET[11]OLOGIC0:INIT_ORANK2_PARTIAL[3]--~IOB0:PDRIVE[0]-
57 ---------------------------~ILOGIC0:INIT_RANK2[5]-----OLOGIC0:OMUX[4]----~IODELAY0:IDELAY_VALUE_CUR[4]--IOB0:DCI_MISC[1]
58 --------------------------ILOGIC0:INIT_BITSLIP[5]-----OLOGIC0:OMUX[0]OLOGIC0:OMUX[3]OLOGIC0:MUX.CLKDIVB[2]OLOGIC0:MUX.CLKDIVB[3]----IOB0:DCI_MISC[0]-
59 ---------------------------~ILOGIC0:INIT_CE[0]--------OLOGIC0:TMUX[1]OLOGIC0:INIT_DLY_CNT[1]----
60 --------------------------~ILOGIC0:INIT_CE[1]---------OLOGIC0:TMUX[2]IODELAY0:EXTRA_DELAY----
61 --------------------------ILOGIC0:READBACK_IILOGIC0:IFF_REV_USED------OLOGIC0:MUX.CLKDIVB[8]OLOGIC0:MUX.CLKDIVB[4]OLOGIC0:INIT_FIFO_RESET[8]OLOGIC0:TMUX[3]---~IOB0:NDRIVE[0]
62 --------------------------ILOGIC0:NUM_CEILOGIC0:RANK23_DLY----ILOGIC0:D_EMU_OPTION[2]---OLOGIC0:TMUX[4]---IOB0:DCI_T-
63 --------------------------ILOGIC0:RANK12_DLYILOGIC0:IFF_SR_USED----ILOGIC0:D_EMU_OPTION[0]ILOGIC0:D_EMU_OPTION[1]--OLOGIC0:TMUX[0]OLOGIC0:INIT_DLY_CNT[3]---IOB0:IBUF_MODE[2]
IO bittile 1
RowColumn
01234567891011121314151617181920212223242526272829303132333435363738394041
0 --------------------------ILOGIC1:IFF_SR_USEDILOGIC1:RANK12_DLY----ILOGIC1:D_EMU_OPTION[1]ILOGIC1:D_EMU_OPTION[0]--OLOGIC1:INIT_DLY_CNT[3]OLOGIC1:TMUX[0]--IOB1:IBUF_MODE[2]-
1 --------------------------ILOGIC1:RANK23_DLYILOGIC1:NUM_CE-----ILOGIC1:D_EMU_OPTION[2]---OLOGIC1:TMUX[4]---IOB1:DCI_T
2 --------------------------ILOGIC1:IFF_REV_USEDILOGIC1:READBACK_I------OLOGIC1:MUX.CLKDIVB[4]OLOGIC1:MUX.CLKDIVB[8]OLOGIC1:TMUX[3]OLOGIC1:INIT_FIFO_RESET[8]--~IOB1:NDRIVE[0]-
3 ---------------------------~ILOGIC1:INIT_CE[1]--------IODELAY1:EXTRA_DELAYOLOGIC1:TMUX[2]----
4 --------------------------~ILOGIC1:INIT_CE[0]---------OLOGIC1:INIT_DLY_CNT[1]OLOGIC1:TMUX[1]----
5 ---------------------------ILOGIC1:INIT_BITSLIP[5]----OLOGIC1:OMUX[3]OLOGIC1:OMUX[0]OLOGIC1:MUX.CLKDIVB[3]OLOGIC1:MUX.CLKDIVB[2]-----IOB1:DCI_MISC[0]
6 --------------------------~ILOGIC1:INIT_RANK2[5]-----OLOGIC1:OMUX[4]------~IODELAY1:IDELAY_VALUE_CUR[4]IOB1:DCI_MISC[1]-
7 ---------------------------~ILOGIC1:INIT_RANK3[5]-----~OLOGIC1:INV.CLK2OLOGIC1:MUX.CLKDIVB[5]OLOGIC1:MUX.CLKDIVB[7]OLOGIC1:INIT_ORANK2_PARTIAL[3]OLOGIC1:INIT_FIFO_RESET[11]---~IOB1:PDRIVE[0]
8 --------------------------~ILOGIC1:IFF_LATCH~ILOGIC1:IFF1_SRVAL----~OLOGIC1:INV.CLK1OLOGIC1:INV.CLKDIV-OLOGIC1:MUX.CLKDIVB[1]OLOGIC1:INIT_ORANK2_PARTIAL[2]---IOB1:LVDS[8]-
9 --------------------------ILOGIC1:SERDESILOGIC1:IFF_SR_SYNC----OLOGIC1:DATA_WIDTH[4]OLOGIC1:OFF_SR_USEDOLOGIC1:MUX.CLKDIVB[0]-OLOGIC1:INIT_DLY_CNT[6]----~IOB1:DCIUPDATEMODE_ASREQUIRED
10 --------------------------~ILOGIC1:IFF2_SRVALILOGIC1:DDR_CLK_EDGE[0]----OLOGIC1:DATA_WIDTH[0]OLOGIC1:DATA_WIDTH[7]OLOGIC1:MUX.CLKDIVB[6]OLOGIC1:MUX.CLKB[6]IODELAY1:ENABLEOLOGIC1:INIT_ORANK2_PARTIAL[1]----
11 ---------------------------~ILOGIC1:IFF1_INIT----OLOGIC1:DATA_WIDTH[6]OLOGIC1:DATA_WIDTH[2]-OLOGIC1:MUX.CLKB[3]-OLOGIC1:INIT_ORANK2_PARTIAL[0]-IODELAY1:DELAY_TYPE[3]-~IOB1:PDRIVE[1]
12 --------------------------~ILOGIC1:INIT_RANK3[4]-----OLOGIC1:DATA_WIDTH[3]OLOGIC1:DATA_WIDTH[5]-----~IODELAY1:IDELAY_VALUE_CUR[3]IOB1:OUTPUT_DELAY-
13 ---------------------------~ILOGIC1:INIT_RANK2[4]----OLOGIC1:DATA_WIDTH[1]~OLOGIC1:INV.T1OLOGIC1:MUX.CLKB[10]OLOGIC1:MUX.CLKB[9]OLOGIC1:INIT_FIFO_RESET[4]OLOGIC1:TFF_SR_USED-IODELAY1:DELAY_SRC[1]-IOB1:LVDS[7]
14 --------------------------ILOGIC1:INIT_BITSLIP[4]-----~OLOGIC1:INV.T2~OLOGIC1:INV.T3--OLOGIC1:TRISTATE_WIDTH--IODELAY1:DELAY_SRC[0]~IOB1:NDRIVE[1]-
15 ---------------------------ILOGIC1:INIT_BITSLIP[3]----~OLOGIC1:INV.T4OLOGIC1:INIT_TRANK1[0]OLOGIC1:MUX.CLKB[4]OLOGIC1:MUX.CLKB[2]-OLOGIC1:TFF_SR_SYNC[1]---IOB1:PULL[2]
16 --------------------------~ILOGIC1:IFF2_INIT-------OLOGIC1:MUX.CLKB[0]--OLOGIC1:INIT_DLY_CNT[7]--IOB1:PULL[1]-
17 ---------------------------~ILOGIC1:INIT_RANK3[3]-----OLOGIC1:CLK_RATIO[0]--OLOGIC1:INIT_FIFO_ADDR[4]~OLOGIC1:TFF_SRVAL[2]---IOB1:PULL[0]
18 --------------------------~ILOGIC1:IFF3_INIT-----OLOGIC1:CLK_RATIO[1]--OLOGIC1:MUX.CLKB[8]IODELAY1:HIGH_PERFORMANCE_MODEOLOGIC1:INIT_FIFO_RESET[12]--~IOB1:PDRIVE[2]-
19 ---------------------------~ILOGIC1:INIT_RANK2[3]----OLOGIC1:CLK_RATIO[3]OLOGIC1:CLK_RATIO[2]OLOGIC1:MUX.CLKB[7]-~OLOGIC1:TFF_SRVAL[0]OLOGIC1:MUX.CLKPERF-IODELAY1:DELAY_SRC[2]-IOB1:NSLEW[0]
20 --------------------------ILOGIC1:INIT_BITSLIP[2]-----OLOGIC1:SELFHEALOLOGIC1:OFF_SR_SYNC[2]OLOGIC1:MUX.CLKB[5]-~OLOGIC1:TFF_SRVAL[1]--~IODELAY1:IDELAY_VALUE_CUR[2]IOB1:NSLEW[4]-
21 ---------------------------~ILOGIC1:INIT_RANK3[2]----OLOGIC1:INIT_TRANK1[1]--OLOGIC1:MUX.CLKB[1]-OLOGIC1:INIT_DLY_CNT[9]-IODELAY1:DELAY_SRC[4]-~IOB1:NDRIVE[2]
22 --------------------------~ILOGIC1:IFF4_INIT~ILOGIC1:IFF3_SRVAL-------ILOGIC1:MUX.CLKB[6]-OLOGIC1:INIT_FIFO_ADDR[5]-IODELAY1:DELAY_SRC[3]IOB1:PDRIVE[3]-
23 --------------------------ILOGIC1:DDR_CLK_EDGE[1]~ILOGIC1:IFF4_SRVAL-----~OLOGIC1:OFF_SRVAL[1]ILOGIC1:MUX.CLKB[3]--OLOGIC1:ODELAY_USED----
24 --------------------------~ILOGIC1:INIT_RANK2[2]------~OLOGIC1:OFF_INITILOGIC1:MUX.CLKB[10]ILOGIC1:MUX.CLKB[9]OLOGIC1:INIT_FIFO_ADDR[6]~OLOGIC1:TFF_INIT--IOB1:PSLEW[0]-
25 ---------------------------~ILOGIC1:INIT_RANK3[1]-----~OLOGIC1:OFF_SRVAL[2]-ILOGIC1:MUX.CLKB[4]-OLOGIC1:OFF_SR_SYNC[3]---IOB1:LVDS[6]
26 --------------------------~ILOGIC1:INIT_RANK2[1]-----OLOGIC1:INIT_TRANK1[2]--ILOGIC1:MUX.CLKB[1]---~IODELAY1:INV.DATAINIOB1:PULL_DYNAMIC-
27 ---------------------------ILOGIC1:INIT_BITSLIP[1]----~OLOGIC1:OFF_SRVAL[0]---------
28 --------------------------~ILOGIC1:INIT_RANK1_PARTIAL[4]-------ILOGIC1:MUX.CLKB[5]----~IODELAY1:IDELAY_VALUE_CUR[1]IOB1:OUTPUT_MISC[0]-
29 ---------------------------ILOGIC1:DATA_RATE-------ILOGIC1:MUX.CLKB[8]OLOGIC1:INIT_PIPE_DATA1[0]----~IOB1:NDRIVE[3]
30 --------------------------ILOGIC1:I_DELAY_ENABLE------OLOGIC1:INIT_TRANK1[3]ILOGIC1:MUX.CLKB[7]-OLOGIC1:INIT_FIFO_RESET[7]---IOB1:LVDS[5]-
31 ---------------------------ILOGIC1:D_EMU-----OLOGIC1:TFF_SR_SYNC[0]-ILOGIC1:MUX.CLKB[2]OLOGIC1:SERDES_MODE----IOB1:NSLEW[2]
32 --------------------------ILOGIC1:BITSLIP_SYNCILOGIC1:SERDES_MODE----OLOGIC1:SERDES--ILOGIC1:MUX.CLKB[0]OLOGIC1:INIT_DLY_CNT[2]---IOB1:PSLEW[1]-
33 ---------------------------~ILOGIC1:INIT_RANK3[0]------OLOGIC1:MUX.CLKDIV[4]------IOB1:NSLEW[1]
34 --------------------------~ILOGIC1:INIT_RANK2[0]------OLOGIC1:INIT_LOADCNT[3]---OLOGIC1:INIT_PIPE_DATA0[0]--IOB1:OUTPUT_ENABLE[0]-
35 ---------------------------ILOGIC1:INIT_BITSLIP[0]-----OLOGIC1:INIT_PIPE_DATA0[6]-OLOGIC1:MUX.CLKDIV[6]OLOGIC1:INIT_FIFO_RESET[10]----IOB1:OUTPUT_ENABLE[1]
36 --------------------------~ILOGIC1:INIT_RANK1_PARTIAL[3]------OLOGIC1:INIT_ORANK1[5]OLOGIC1:MUX.CLKDIV[3]OLOGIC1:MUX.CLKDIV[2]---~IODELAY1:IDELAY_VALUE_CUR[0]IOB1:PSLEW[2]-
37 ---------------------------~ILOGIC1:INIT_RANK1_PARTIAL[2]----OLOGIC1:OMUX[1]---OLOGIC1:INIT_PIPE_DATA1[1]OLOGIC1:INIT_PIPE_DATA0[1]-IODELAY1:DELAY_TYPE[0]-~IOB1:PDRIVE[4]
38 --------------------------~ILOGIC1:INIT_BITSLIPCNT[0]-----OLOGIC1:INIT_PIPE_DATA1[6]OLOGIC1:OMUX[2]OLOGIC1:MUX.CLKDIV[5]OLOGIC1:MUX.CLKDIV[8]-OLOGIC1:INIT_DLY_CNT[0]-~IODELAY1:INV.IDATAINIOB1:OUTPUT_MISC[2]-
39 --------------------------~ILOGIC1:INV.CLK[0]ILOGIC1:INV.CLKDIV----OLOGIC1:INV.D1OLOGIC1:INIT_PIPE_DATA1[7]-OLOGIC1:MUX.CLKDIV[1]-----IOB1:OUTPUT_MISC[1]
40 --------------------------ILOGIC1:DYN_CLK_INV_ENILOGIC1:DATA_WIDTH[3]----OLOGIC1:INIT_LOADCNT[2]OLOGIC1:INIT_PIPE_DATA0[7]OLOGIC1:MUX.CLKDIV[0]OLOGIC1:MUX.CLKDIV[7]OLOGIC1:DDR3_DATAOLOGIC1:DDR3_BYPASS--IOB1:LVDS[4]-
41 --------------------------~ILOGIC1:INV.CLK[1]------OLOGIC1:INIT_ORANK1[4]-OLOGIC1:MUX.CLK[6]~OLOGIC1:INV.CLKPERFOLOGIC1:INIT_FIFO_RESET[5]-IODELAY1:INV.C-IOB1:LVDS[3]
42 --------------------------ILOGIC1:BITSLIP_ENABLEILOGIC1:DATA_WIDTH[2]-------OLOGIC1:MUX.CLK[5]OLOGIC1:WC_DELAYOLOGIC1:INIT_FIFO_RESET[3]-IODELAY1:CINVCTRL_SELIOB1:NDRIVE[4]-
43 ---------------------------~ILOGIC1:INIT_BITSLIPCNT[1]----OLOGIC1:INIT_PIPE_DATA1[8]OLOGIC1:INV.D2--OLOGIC1:INIT_FIFO_ADDR[0]--IODELAY1:IDELAY_VALUE_INIT[0]-IOB1:PSLEW[3]
44 --------------------------~ILOGIC1:INIT_BITSLIPCNT[2]-----OLOGIC1:OFF_SR_SYNC[0]OLOGIC1:INIT_LOADCNT[1]OLOGIC1:MUX.CLK[10]OLOGIC1:MUX.CLK[9]OLOGIC1:INIT_PIPE_DATA1[2]OLOGIC1:INIT_DLY_CNT[4]-IODELAY1:IDELAY_VALUE_INIT[1]IOB1:DCI_MODE[2]-
45 --------------------------ILOGIC1:DATA_WIDTH[1]--------OLOGIC1:MUX.CLK[4]-OLOGIC1:INIT_FIFO_ADDR[3]-IODELAY1:IDELAY_VALUE_INIT[2]-IOB1:LVDS[2]
46 --------------------------~ILOGIC1:INV.CLK[2]ILOGIC1:DATA_WIDTH[0]----OLOGIC1:INIT_PIPE_DATA0[8]--OLOGIC1:MUX.CLK[2]OLOGIC1:INIT_PIPE_DATA0[2]--IODELAY1:IDELAY_VALUE_INIT[3]IOB1:NSLEW[3]-
47 --------------------------~ILOGIC1:INV.OCLK1ILOGIC1:INTERFACE_TYPE[2]----OLOGIC1:INIT_ORANK1[3]----OLOGIC1:INIT_FIFO_RESET[0]-IODELAY1:IDELAY_VALUE_INIT[4]--
48 ---------------------------ILOGIC1:INTERFACE_TYPE[0]----OLOGIC1:INIT_PIPE_DATA0[10]----OLOGIC1:INIT_PIPE_DATA1[4]-IODELAY1:DELAY_TYPE[1]--
49 --------------------------ILOGIC1:DYN_OCLK_INV_EN[0]-----OLOGIC1:INIT_PIPE_DATA1[10]OLOGIC1:INV.D3OLOGIC1:MUX.CLK[3]OLOGIC1:MUX.CLK[1]OLOGIC1:INIT_FIFO_ADDR[1]--IODELAY1:ALT_DELAY_VALUE[0]-IOB1:DCI_MODE[0]
50 --------------------------~ILOGIC1:INV.OCLK2ILOGIC1:DYN_OCLK_INV_EN[1]----OLOGIC1:INIT_PIPE_DATA1[9]OLOGIC1:INIT_LOADCNT[0]OLOGIC1:MUX.CLK[8]OLOGIC1:MUX.CLK[7]OLOGIC1:INIT_DLY_CNT[5]--IODELAY1:ALT_DELAY_VALUE[1]IOB1:VR-
51 ---------------------------~ILOGIC1:INIT_BITSLIPCNT[3]--------OLOGIC1:INIT_PIPE_DATA1[3]OLOGIC1:INIT_FIFO_ADDR[2]-IODELAY1:ALT_DELAY_VALUE[2]-IOB1:DCI_MODE[1]
52 --------------------------------OLOGIC1:INV.D4--OLOGIC1:MUX.CLK[0]-OLOGIC1:INIT_PIPE_DATA0[4]-IODELAY1:ALT_DELAY_VALUE[3]--
53 --------------------------ILOGIC1:INTERFACE_TYPE[1]-----OLOGIC1:INIT_ORANK1[2]-ILOGIC1:MUX.CLK[6]-OLOGIC1:INIT_FIFO_RESET[6]--IODELAY1:ALT_DELAY_VALUE[4]-IOB1:PSLEW[4]
54 --------------------------ILOGIC1:DYN_CLKDIV_INV_ENILOGIC1:TSBYPASS_MUX----OLOGIC1:INIT_PIPE_DATA1[11]-ILOGIC1:MUX.CLK[4]ILOGIC1:MUX.CLK[2]OLOGIC1:INIT_FIFO_RESET[1]--IODELAY1:DELAY_TYPE[4]IOB1:OUTPUT_MISC[3]-
55 --------------------------OLOGIC1:MISR_CLK_SELECT[1]ILOGIC1:I_TSBYPASS_ENABLE-----OLOGIC1:INV.D5ILOGIC1:MUX.CLK[10]ILOGIC1:MUX.CLK[9]OLOGIC1:INIT_PIPE_DATA1[5]OLOGIC1:INIT_FIFO_ADDR[7]-IODELAY1:DELAY_TYPE[2]-IOB1:LVDS[1]
56 --------------------------OLOGIC1:MISR_CLK_SELECT[0]ILOGIC1:IFF_TSBYPASS_ENABLE------ILOGIC1:MUX.CLK[5]--OLOGIC1:INIT_FIFO_ADDR[9]--IOB1:PDRIVE[5]-
57 ---------------------------~ILOGIC1:INIT_RANK1_PARTIAL[1]----OLOGIC1:INIT_ORANK1[1]--ILOGIC1:MUX.CLK[1]-OLOGIC1:INTERFACE_TYPE---IOB1:NDRIVE[5]
58 --------------------------~ILOGIC1:INIT_RANK1_PARTIAL[0]-----OLOGIC1:INV.D6OLOGIC1:INIT_PIPE_DATA0[9]---OLOGIC1:INIT_FIFO_RESET[9]--IOB1:LVDS[0]-
59 --------------------------OLOGIC1:MISR_ENABLEILOGIC1:IFF_DELAY_ENABLE---------OLOGIC1:INIT_FIFO_RESET[2]---IOB1:IBUF_MODE[4]
60 --------------------------OLOGIC1:MISR_ENABLE_FDBK--------ILOGIC1:MUX.CLK[8]OLOGIC1:INIT_PIPE_DATA0[3]---IOB1:VREF_SYSMON-
61 ---------------------------------OLOGIC1:INIT_PIPE_DATA0[11]ILOGIC1:MUX.CLK[7]-OLOGIC1:INIT_FIFO_ADDR[8]----IOB1:IBUF_MODE[3]
62 --------------------------------OLOGIC1:INIT_ORANK1[0]--ILOGIC1:MUX.CLK[3]OLOGIC1:INIT_PIPE_DATA0[5]OLOGIC1:INIT_DLY_CNT[8]--IOB1:IBUF_MODE[1]-
63 --------------------------OLOGIC1:MISR_RESET~ILOGIC1:INV.D----OLOGIC1:OFF_SR_SYNC[1]--ILOGIC1:MUX.CLK[0]-OLOGIC1:INIT_FIFO_ADDR[10]---IOB1:IBUF_MODE[0]
ILOGIC0:IFF1_INIT[0, 26, 52]
ILOGIC0:IFF1_SRVAL[0, 26, 55]
ILOGIC0:IFF2_INIT[0, 27, 47]
ILOGIC0:IFF2_SRVAL[0, 27, 53]
ILOGIC0:IFF3_INIT[0, 27, 45]
ILOGIC0:IFF3_SRVAL[0, 26, 41]
ILOGIC0:IFF4_INIT[0, 27, 41]
ILOGIC0:IFF4_SRVAL[0, 26, 40]
ILOGIC0:IFF_LATCH[0, 27, 55]
ILOGIC0:INV.D[0, 26, 0]
ILOGIC0:INV.OCLK1[0, 27, 16]
ILOGIC0:INV.OCLK2[0, 27, 13]
ILOGIC1:IFF1_INIT[1, 27, 11]
ILOGIC1:IFF1_SRVAL[1, 27, 8]
ILOGIC1:IFF2_INIT[1, 26, 16]
ILOGIC1:IFF2_SRVAL[1, 26, 10]
ILOGIC1:IFF3_INIT[1, 26, 18]
ILOGIC1:IFF3_SRVAL[1, 27, 22]
ILOGIC1:IFF4_INIT[1, 26, 22]
ILOGIC1:IFF4_SRVAL[1, 27, 23]
ILOGIC1:IFF_LATCH[1, 26, 8]
ILOGIC1:INV.D[1, 27, 63]
ILOGIC1:INV.OCLK1[1, 26, 47]
ILOGIC1:INV.OCLK2[1, 26, 50]
IOB0:DCIUPDATEMODE_ASREQUIRED[0, 40, 54]
IOB1:DCIUPDATEMODE_ASREQUIRED[1, 41, 9]
IODELAY0:INV.DATAIN[0, 38, 37]
IODELAY0:INV.IDATAIN[0, 38, 25]
IODELAY1:INV.DATAIN[1, 39, 26]
IODELAY1:INV.IDATAIN[1, 39, 38]
OLOGIC0:INV.CLK1[0, 33, 55]
OLOGIC0:INV.CLK2[0, 32, 56]
OLOGIC0:INV.CLKPERF[0, 37, 22]
OLOGIC0:INV.T1[0, 32, 50]
OLOGIC0:INV.T2[0, 33, 49]
OLOGIC0:INV.T3[0, 32, 49]
OLOGIC0:INV.T4[0, 33, 48]
OLOGIC0:OFF_INIT[0, 32, 39]
OLOGIC0:TFF_INIT[0, 36, 39]
OLOGIC1:INV.CLK1[1, 32, 8]
OLOGIC1:INV.CLK2[1, 33, 7]
OLOGIC1:INV.CLKPERF[1, 36, 41]
OLOGIC1:INV.T1[1, 33, 13]
OLOGIC1:INV.T2[1, 32, 14]
OLOGIC1:INV.T3[1, 33, 14]
OLOGIC1:INV.T4[1, 32, 15]
OLOGIC1:OFF_INIT[1, 33, 24]
OLOGIC1:TFF_INIT[1, 37, 24]
Inverted~[0]
ILOGIC0:BITSLIP_ENABLE[0, 27, 21]
ILOGIC0:BITSLIP_SYNC[0, 27, 31]
ILOGIC0:DYN_CLKDIV_INV_EN[0, 27, 9]
ILOGIC0:DYN_CLK_INV_EN[0, 27, 23]
ILOGIC0:D_EMU[0, 26, 32]
ILOGIC0:IFF_DELAY_ENABLE[0, 26, 4]
ILOGIC0:IFF_REV_USED[0, 27, 61]
ILOGIC0:IFF_SR_SYNC[0, 26, 54]
ILOGIC0:IFF_SR_USED[0, 27, 63]
ILOGIC0:IFF_TSBYPASS_ENABLE[0, 26, 7]
ILOGIC0:INV.CLKDIV[0, 26, 24]
ILOGIC0:I_DELAY_ENABLE[0, 27, 33]
ILOGIC0:I_TSBYPASS_ENABLE[0, 26, 8]
ILOGIC0:RANK12_DLY[0, 26, 63]
ILOGIC0:RANK23_DLY[0, 27, 62]
ILOGIC0:READBACK_I[0, 26, 61]
ILOGIC0:SERDES[0, 27, 54]
ILOGIC1:BITSLIP_ENABLE[1, 26, 42]
ILOGIC1:BITSLIP_SYNC[1, 26, 32]
ILOGIC1:DYN_CLKDIV_INV_EN[1, 26, 54]
ILOGIC1:DYN_CLK_INV_EN[1, 26, 40]
ILOGIC1:D_EMU[1, 27, 31]
ILOGIC1:IFF_DELAY_ENABLE[1, 27, 59]
ILOGIC1:IFF_REV_USED[1, 26, 2]
ILOGIC1:IFF_SR_SYNC[1, 27, 9]
ILOGIC1:IFF_SR_USED[1, 26, 0]
ILOGIC1:IFF_TSBYPASS_ENABLE[1, 27, 56]
ILOGIC1:INV.CLKDIV[1, 27, 39]
ILOGIC1:I_DELAY_ENABLE[1, 26, 30]
ILOGIC1:I_TSBYPASS_ENABLE[1, 27, 55]
ILOGIC1:RANK12_DLY[1, 27, 0]
ILOGIC1:RANK23_DLY[1, 26, 1]
ILOGIC1:READBACK_I[1, 27, 2]
ILOGIC1:SERDES[1, 26, 9]
IOB0:DCI_T[0, 40, 62]
IOB0:OUTPUT_DELAY[0, 41, 51]
IOB0:PULL_DYNAMIC[0, 41, 37]
IOB0:VR[0, 41, 13]
IOB0:VREF_SYSMON[0, 41, 3]
IOB1:DCI_T[1, 41, 1]
IOB1:OUTPUT_DELAY[1, 40, 12]
IOB1:PULL_DYNAMIC[1, 40, 26]
IOB1:VR[1, 40, 50]
IOB1:VREF_SYSMON[1, 40, 60]
IODELAY0:CINVCTRL_SEL[0, 38, 21]
IODELAY0:ENABLE[0, 37, 53]
IODELAY0:EXTRA_DELAY[0, 37, 60]
IODELAY0:HIGH_PERFORMANCE_MODE[0, 37, 45]
IODELAY0:INV.C[0, 38, 22]
IODELAY1:CINVCTRL_SEL[1, 39, 42]
IODELAY1:ENABLE[1, 36, 10]
IODELAY1:EXTRA_DELAY[1, 36, 3]
IODELAY1:HIGH_PERFORMANCE_MODE[1, 36, 18]
IODELAY1:INV.C[1, 39, 41]
OLOGIC0:DDR3_BYPASS[0, 36, 23]
OLOGIC0:DDR3_DATA[0, 37, 23]
OLOGIC0:INV.CLKDIV[0, 32, 55]
OLOGIC0:INV.D1[0, 33, 24]
OLOGIC0:INV.D2[0, 32, 20]
OLOGIC0:INV.D3[0, 32, 14]
OLOGIC0:INV.D4[0, 33, 11]
OLOGIC0:INV.D5[0, 32, 8]
OLOGIC0:INV.D6[0, 33, 5]
OLOGIC0:MISR_ENABLE[0, 27, 4]
OLOGIC0:MISR_ENABLE_FDBK[0, 27, 3]
OLOGIC0:MISR_RESET[0, 27, 0]
OLOGIC0:ODELAY_USED[0, 36, 40]
OLOGIC0:OFF_SR_USED[0, 32, 54]
OLOGIC0:SELFHEAL[0, 33, 43]
OLOGIC0:SERDES[0, 33, 31]
OLOGIC0:TFF_SR_USED[0, 36, 50]
OLOGIC0:WC_DELAY[0, 37, 21]
OLOGIC1:DDR3_BYPASS[1, 37, 40]
OLOGIC1:DDR3_DATA[1, 36, 40]
OLOGIC1:INV.CLKDIV[1, 33, 8]
OLOGIC1:INV.D1[1, 32, 39]
OLOGIC1:INV.D2[1, 33, 43]
OLOGIC1:INV.D3[1, 33, 49]
OLOGIC1:INV.D4[1, 32, 52]
OLOGIC1:INV.D5[1, 33, 55]
OLOGIC1:INV.D6[1, 32, 58]
OLOGIC1:MISR_ENABLE[1, 26, 59]
OLOGIC1:MISR_ENABLE_FDBK[1, 26, 60]
OLOGIC1:MISR_RESET[1, 26, 63]
OLOGIC1:ODELAY_USED[1, 37, 23]
OLOGIC1:OFF_SR_USED[1, 33, 9]
OLOGIC1:SELFHEAL[1, 32, 20]
OLOGIC1:SERDES[1, 32, 32]
OLOGIC1:TFF_SR_USED[1, 37, 13]
OLOGIC1:WC_DELAY[1, 36, 42]
Non-inverted[0]
ILOGIC0:TSBYPASS_MUX[0, 26, 9]
ILOGIC1:TSBYPASS_MUX[1, 27, 54]
T0
GND1
ILOGIC0:DYN_OCLK_INV_EN[0, 27, 14][0, 26, 13]
ILOGIC1:DYN_OCLK_INV_EN[1, 27, 50][1, 26, 49]
IOB0:DCI_MISC[0, 41, 57][0, 40, 58]
IOB0:OUTPUT_ENABLE[0, 41, 29][0, 40, 28]
IOB1:DCI_MISC[1, 40, 6][1, 41, 5]
IOB1:OUTPUT_ENABLE[1, 41, 35][1, 40, 34]
OLOGIC0:TFF_SR_SYNC[0, 36, 48][0, 32, 32]
OLOGIC1:TFF_SR_SYNC[1, 37, 15][1, 33, 31]
Non-inverted[1][0]
ILOGIC0:INTERFACE_TYPE[0, 26, 16][0, 27, 10][0, 26, 15]
ILOGIC1:INTERFACE_TYPE[1, 27, 47][1, 26, 53][1, 27, 48]
MEMORY000
NETWORKING001
MEMORY_DDR3011
OVERSAMPLE101
ILOGIC0:DATA_WIDTH[0, 26, 23][0, 26, 21][0, 27, 18][0, 26, 17]
ILOGIC1:DATA_WIDTH[1, 27, 40][1, 27, 42][1, 26, 45][1, 27, 46]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
ILOGIC0:INIT_BITSLIP[0, 26, 58][0, 27, 49][0, 26, 48][0, 27, 43][0, 26, 36][0, 26, 28]
ILOGIC1:INIT_BITSLIP[1, 27, 5][1, 26, 14][1, 27, 15][1, 26, 20][1, 27, 27][1, 27, 35]
OLOGIC0:INIT_ORANK1[0, 32, 27][0, 32, 22][0, 33, 16][0, 33, 10][0, 33, 6][0, 33, 1]
OLOGIC1:INIT_ORANK1[1, 33, 36][1, 33, 41][1, 32, 47][1, 32, 53][1, 32, 57][1, 32, 62]
Non-inverted[5][4][3][2][1][0]
ILOGIC0:INIT_RANK2[0, 27, 57][0, 26, 50][0, 26, 44][0, 27, 39][0, 27, 37][0, 27, 29]
ILOGIC0:INIT_RANK3[0, 26, 56][0, 27, 51][0, 26, 46][0, 26, 42][0, 26, 38][0, 26, 30]
ILOGIC1:INIT_RANK2[1, 26, 6][1, 27, 13][1, 27, 19][1, 26, 24][1, 26, 26][1, 26, 34]
ILOGIC1:INIT_RANK3[1, 27, 7][1, 26, 12][1, 27, 17][1, 27, 21][1, 27, 25][1, 27, 33]
Inverted~[5]~[4]~[3]~[2]~[1]~[0]
ILOGIC0:SERDES_MODE[0, 26, 31]
ILOGIC1:SERDES_MODE[1, 27, 32]
OLOGIC0:SERDES_MODE[0, 37, 32]
OLOGIC1:SERDES_MODE[1, 36, 31]
MASTER0
SLAVE1
ILOGIC0:DATA_RATE[0, 26, 34]
ILOGIC1:DATA_RATE[1, 27, 29]
DDR0
SDR1
ILOGIC0:DDR_CLK_EDGE[0, 27, 40][0, 26, 53]
ILOGIC1:DDR_CLK_EDGE[1, 26, 23][1, 27, 10]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC0:NUM_CE[0, 26, 62]
ILOGIC1:NUM_CE[1, 27, 1]
10
21
ILOGIC0:INIT_RANK1_PARTIAL[0, 27, 35][0, 27, 27][0, 26, 26][0, 26, 6][0, 27, 5]
ILOGIC1:INIT_RANK1_PARTIAL[1, 26, 28][1, 26, 36][1, 27, 37][1, 27, 57][1, 26, 58]
IODELAY0:IDELAY_VALUE_CUR[0, 38, 57][0, 38, 51][0, 38, 43][0, 38, 35][0, 38, 27]
IODELAY1:IDELAY_VALUE_CUR[1, 39, 6][1, 39, 12][1, 39, 20][1, 39, 28][1, 39, 36]
Inverted~[4]~[3]~[2]~[1]~[0]
OLOGIC0:MISR_CLK_SELECT[0, 27, 8][0, 27, 7]
OLOGIC1:MISR_CLK_SELECT[1, 26, 55][1, 26, 56]
NONE00
CLK101
CLK210
ILOGIC0:INV.CLK[0, 27, 24][0, 27, 22][0, 27, 17]
ILOGIC1:INV.CLK[1, 26, 46][1, 26, 41][1, 26, 39]
OLOGIC0:OFF_SRVAL[0, 33, 36][0, 32, 40][0, 32, 38]
OLOGIC0:TFF_SRVAL[0, 37, 44][0, 37, 43][0, 36, 46]
OLOGIC1:OFF_SRVAL[1, 33, 25][1, 33, 23][1, 32, 27]
OLOGIC1:TFF_SRVAL[1, 37, 17][1, 36, 20][1, 36, 19]
Inverted~[2]~[1]~[0]
ILOGIC0:INIT_BITSLIPCNT[0, 26, 12][0, 27, 19][0, 26, 20][0, 27, 25]
ILOGIC1:INIT_BITSLIPCNT[1, 27, 51][1, 26, 44][1, 27, 43][1, 26, 38]
Inverted~[3]~[2]~[1]~[0]
ILOGIC0:INIT_CE[0, 26, 60][0, 27, 59]
ILOGIC1:INIT_CE[1, 27, 3][1, 26, 4]
Inverted~[1]~[0]
IOB0:OUTPUT_MISC[0, 41, 9][0, 41, 25][0, 40, 24][0, 41, 35]
IOB1:OUTPUT_MISC[1, 40, 54][1, 40, 38][1, 41, 39][1, 40, 28]
OLOGIC0:INIT_LOADCNT[0, 32, 29][0, 33, 23][0, 32, 19][0, 32, 13]
OLOGIC0:INIT_ORANK2_PARTIAL[0, 37, 56][0, 37, 55][0, 36, 53][0, 36, 52]
OLOGIC0:INIT_TRANK1[0, 32, 48][0, 33, 42][0, 33, 37][0, 32, 33]
OLOGIC0:OFF_SR_SYNC[0, 36, 38][0, 33, 19][0, 33, 0][0, 32, 43]
OLOGIC1:INIT_LOADCNT[1, 33, 34][1, 32, 40][1, 33, 44][1, 33, 50]
OLOGIC1:INIT_ORANK2_PARTIAL[1, 36, 7][1, 36, 8][1, 37, 10][1, 37, 11]
OLOGIC1:INIT_TRANK1[1, 33, 30][1, 32, 26][1, 32, 21][1, 33, 15]
OLOGIC1:OFF_SR_SYNC[1, 37, 25][1, 33, 20][1, 32, 63][1, 32, 44]
Non-inverted[3][2][1][0]
OLOGIC0:CLK_RATIO[0, 33, 44][0, 32, 44][0, 33, 45][0, 32, 46]
OLOGIC1:CLK_RATIO[1, 32, 19][1, 33, 19][1, 32, 18][1, 33, 17]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC0:OMUX[0, 33, 57][0, 33, 58][0, 32, 25][0, 33, 26][0, 32, 58]
OLOGIC1:OMUX[1, 32, 6][1, 32, 5][1, 33, 38][1, 32, 37][1, 33, 5]
NONE00000
D100001
SERDES_SDR00010
SERDES_DDR00100
FF01010
DDR01100
LATCH10010
ILOGIC0:D_EMU_OPTION[0, 32, 62][0, 33, 63][0, 32, 63]
ILOGIC1:D_EMU_OPTION[1, 33, 1][1, 32, 0][1, 33, 0]
DLY3000
DLY0001
DLY2010
MATCH_DLY0011
MATCH_DLY2100
DLY1110
OLOGIC0:DATA_WIDTH[0, 32, 53][0, 33, 52][0, 32, 51][0, 33, 54][0, 33, 51][0, 32, 52][0, 33, 50][0, 33, 53]
OLOGIC1:DATA_WIDTH[1, 33, 10][1, 32, 11][1, 33, 12][1, 32, 9][1, 32, 12][1, 33, 11][1, 32, 13][1, 32, 10]
NONE00000000
200000001
300000010
400000100
500001000
600010000
700100000
801000000
1010000000
ILOGIC0:MUX.CLK[0, 35, 8][0, 34, 8][0, 34, 3][0, 35, 2][0, 35, 10][0, 35, 7][0, 35, 9][0, 34, 1][0, 34, 9][0, 34, 6][0, 34, 0]
ILOGIC0:MUX.CLKB[0, 35, 39][0, 34, 39][0, 34, 34][0, 35, 33][0, 34, 41][0, 35, 35][0, 34, 38][0, 35, 40][0, 34, 32][0, 34, 37][0, 34, 31]
ILOGIC1:MUX.CLK[1, 34, 55][1, 35, 55][1, 35, 60][1, 34, 61][1, 34, 53][1, 34, 56][1, 34, 54][1, 35, 62][1, 35, 54][1, 35, 57][1, 35, 63]
ILOGIC1:MUX.CLKB[1, 34, 24][1, 35, 24][1, 35, 29][1, 34, 30][1, 35, 22][1, 34, 28][1, 35, 25][1, 34, 23][1, 35, 31][1, 35, 26][1, 35, 32]
OLOGIC0:MUX.CLK[0, 35, 19][0, 34, 19][0, 35, 13][0, 34, 13][0, 34, 22][0, 34, 21][0, 34, 18][0, 35, 14][0, 34, 17][0, 34, 14][0, 34, 11]
OLOGIC0:MUX.CLKB[0, 35, 50][0, 34, 50][0, 34, 45][0, 35, 44][0, 34, 53][0, 35, 43][0, 35, 48][0, 34, 52][0, 34, 48][0, 34, 42][0, 35, 47]
OLOGIC1:MUX.CLK[1, 34, 44][1, 35, 44][1, 34, 50][1, 35, 50][1, 35, 41][1, 35, 42][1, 35, 45][1, 34, 49][1, 35, 46][1, 35, 49][1, 35, 52]
OLOGIC1:MUX.CLKB[1, 34, 13][1, 35, 13][1, 35, 18][1, 34, 19][1, 35, 10][1, 34, 20][1, 34, 15][1, 35, 11][1, 35, 15][1, 35, 21][1, 34, 16]
NONE00000000000
HCLK000010000001
HCLK100010000010
HCLK200010000100
HCLK300010001000
HCLK400010010000
HCLK500010100000
HCLK600011000000
HCLK700100000001
HCLK800100000010
HCLK900100000100
HCLK1000100001000
HCLK1100100010000
RCLK000100100000
RCLK100101000000
RCLK201000000001
RCLK301000000010
RCLK401000000100
RCLK501000001000
IOCLK001000010000
IOCLK101000100000
IOCLK201001000000
IOCLK310000000001
IOCLK410000000010
IOCLK510000000100
IOCLK610000001000
IOCLK710000010000
OLOGIC0:MUX.CLKDIV[0, 34, 25][0, 34, 23][0, 34, 28][0, 35, 25][0, 35, 30][0, 35, 27][0, 34, 27][0, 34, 24][0, 35, 23]
OLOGIC0:MUX.CLKDIVB[0, 34, 61][0, 34, 56][0, 35, 53][0, 35, 56][0, 35, 61][0, 35, 58][0, 34, 58][0, 34, 55][0, 35, 54]
OLOGIC1:MUX.CLKDIV[1, 35, 38][1, 35, 40][1, 35, 35][1, 34, 38][1, 34, 33][1, 34, 36][1, 35, 36][1, 35, 39][1, 34, 40]
OLOGIC1:MUX.CLKDIVB[1, 35, 2][1, 35, 7][1, 34, 10][1, 34, 7][1, 34, 2][1, 34, 5][1, 35, 5][1, 35, 8][1, 34, 9]
NONE000000000
HCLK0000100001
HCLK4000100010
HCLK8000100100
RCLK0000101000
RCLK4000110000
HCLK1001000001
HCLK5001000010
HCLK9001000100
RCLK1001001000
RCLK5001010000
HCLK2010000001
HCLK6010000010
HCLK10010000100
RCLK2010001000
HCLK3100000001
HCLK7100000010
HCLK11100000100
RCLK3100001000
OLOGIC0:INTERFACE_TYPE[0, 36, 6]
OLOGIC1:INTERFACE_TYPE[1, 37, 57]
DEFAULT0
MEMORY_DDR31
OLOGIC0:INIT_FIFO_RESET[0, 36, 45][0, 36, 56][0, 37, 28][0, 36, 5][0, 36, 61][0, 37, 33][0, 37, 10][0, 36, 22][0, 37, 50][0, 36, 21][0, 36, 4][0, 37, 9][0, 36, 16]
OLOGIC1:INIT_FIFO_RESET[1, 37, 18][1, 37, 7][1, 36, 35][1, 37, 58][1, 37, 2][1, 36, 30][1, 36, 53][1, 37, 41][1, 36, 13][1, 37, 42][1, 37, 59][1, 36, 54][1, 37, 47]
Non-inverted[12][11][10][9][8][7][6][5][4][3][2][1][0]
OLOGIC0:INIT_DLY_CNT[0, 36, 42][0, 36, 1][0, 36, 47][0, 37, 54][0, 37, 13][0, 36, 19][0, 37, 63][0, 37, 31][0, 37, 59][0, 36, 25]
OLOGIC1:INIT_DLY_CNT[1, 37, 21][1, 37, 62][1, 37, 16][1, 36, 9][1, 36, 50][1, 37, 44][1, 36, 0][1, 36, 32][1, 36, 4][1, 37, 38]
Non-inverted[9][8][7][6][5][4][3][2][1][0]
OLOGIC0:INIT_PIPE_DATA0[0, 32, 2][0, 33, 15][0, 32, 5][0, 33, 17][0, 32, 23][0, 32, 28][0, 37, 1][0, 36, 11][0, 37, 3][0, 37, 17][0, 36, 26][0, 36, 29]
OLOGIC0:INIT_PIPE_DATA1[0, 33, 9][0, 33, 14][0, 33, 13][0, 33, 20][0, 32, 24][0, 33, 25][0, 37, 8][0, 36, 15][0, 37, 12][0, 37, 19][0, 37, 26][0, 37, 34]
OLOGIC1:INIT_PIPE_DATA0[1, 33, 61][1, 32, 48][1, 33, 58][1, 32, 46][1, 33, 40][1, 33, 35][1, 36, 62][1, 37, 52][1, 36, 60][1, 36, 46][1, 37, 37][1, 37, 34]
OLOGIC1:INIT_PIPE_DATA1[1, 32, 54][1, 32, 49][1, 32, 50][1, 32, 43][1, 33, 39][1, 32, 38][1, 36, 55][1, 37, 48][1, 36, 51][1, 36, 44][1, 36, 37][1, 36, 29]
Non-inverted[11][10][9][8][7][6][5][4][3][2][1][0]
OLOGIC0:MUX.CLKPERF[0, 36, 44]
OLOGIC1:MUX.CLKPERF[1, 37, 19]
OCLK00
OCLK11
OLOGIC0:TMUX[0, 36, 62][0, 37, 61][0, 36, 60][0, 36, 59][0, 36, 63]
OLOGIC1:TMUX[1, 37, 1][1, 36, 2][1, 37, 3][1, 37, 4][1, 37, 0]
NONE00000
T100001
SERDES_SDR00010
SERDES_DDR00100
FF01010
DDR01100
LATCH10010
OLOGIC0:INIT_FIFO_ADDR[0, 36, 0][0, 36, 7][0, 37, 2][0, 36, 8][0, 37, 39][0, 36, 41][0, 37, 46][0, 36, 18][0, 36, 12][0, 37, 14][0, 37, 20]
OLOGIC1:INIT_FIFO_ADDR[1, 37, 63][1, 37, 56][1, 36, 61][1, 37, 55][1, 36, 24][1, 37, 22][1, 36, 17][1, 37, 45][1, 37, 51][1, 36, 49][1, 36, 43]
Non-inverted[10][9][8][7][6][5][4][3][2][1][0]
OLOGIC0:TRISTATE_WIDTH[0, 37, 49]
OLOGIC1:TRISTATE_WIDTH[1, 36, 14]
10
41
IOB0:NSLEW[0, 41, 43][0, 41, 17][0, 40, 32][0, 40, 30][0, 40, 44]
IOB0:PSLEW[0, 40, 10][0, 40, 20][0, 41, 27][0, 41, 31][0, 41, 39]
IOB1:NSLEW[1, 40, 20][1, 40, 46][1, 41, 31][1, 41, 33][1, 41, 19]
IOB1:PSLEW[1, 41, 53][1, 41, 43][1, 40, 36][1, 40, 32][1, 40, 24]
IODELAY0:ALT_DELAY_VALUE[0, 38, 10][0, 38, 11][0, 38, 12][0, 38, 13][0, 38, 14]
IODELAY0:IDELAY_VALUE_INIT[0, 38, 16][0, 38, 17][0, 38, 18][0, 38, 19][0, 38, 20]
IODELAY1:ALT_DELAY_VALUE[1, 39, 53][1, 39, 52][1, 39, 51][1, 39, 50][1, 39, 49]
IODELAY1:IDELAY_VALUE_INIT[1, 39, 47][1, 39, 46][1, 39, 45][1, 39, 44][1, 39, 43]
Non-inverted[4][3][2][1][0]
IODELAY0:DELAY_TYPE[0, 38, 52][0, 38, 9][0, 38, 8][0, 38, 15][0, 38, 26]
IODELAY1:DELAY_TYPE[1, 39, 54][1, 39, 11][1, 39, 55][1, 39, 48][1, 39, 37]
FIXED00000
VARIABLE00001
VAR_LOADABLE00011
VARIABLE_SWAPPED00101
IO_VAR_LOADABLE11111
IODELAY0:DELAY_SRC[0, 38, 42][0, 38, 41][0, 38, 44][0, 38, 50][0, 38, 49]
IODELAY1:DELAY_SRC[1, 39, 21][1, 39, 22][1, 39, 19][1, 39, 13][1, 39, 14]
NONE00000
I00001
O00010
IO00011
DATAIN00100
CLKIN01000
DELAYCHAIN_OSC10000
IOB0:IBUF_MODE[0, 40, 4][0, 40, 2][0, 41, 63][0, 41, 1][0, 40, 0]
IOB1:IBUF_MODE[1, 41, 59][1, 41, 61][1, 40, 0][1, 40, 62][1, 41, 63]
OFF00000
VREF_LP00001
DIFF_LP00010
CMOS1200011
CMOS00111
VREF_HP01001
DIFF_HP10010
IOB0:DCI_MODE[0, 41, 19][0, 40, 12][0, 40, 14]
IOB1:DCI_MODE[1, 40, 44][1, 41, 51][1, 41, 49]
NONE000
OUTPUT001
OUTPUT_HALF010
TERM_VCC011
TERM_SPLIT100
IOB0:OMUX[0, 40, 36]
O0
OTHER_O_INV1
IOB0:PULL[0, 40, 48][0, 41, 47][0, 40, 46]
IOB1:PULL[1, 41, 15][1, 40, 16][1, 41, 17]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:PDRIVE[0, 41, 7][0, 40, 26][0, 41, 41][0, 41, 45][0, 40, 52][0, 40, 56]
IOB1:PDRIVE[1, 40, 56][1, 41, 37][1, 40, 22][1, 40, 18][1, 41, 11][1, 41, 7]
Mixed inversion[5]~[4][3]~[2]~[1]~[0]
IOB0:LVDS[0, 41, 55][0, 40, 50][0, 40, 38][0, 41, 33][0, 41, 23][0, 40, 22][0, 40, 18][0, 40, 8][0, 41, 5]
IOB1:LVDS[1, 40, 8][1, 41, 13][1, 41, 25][1, 40, 30][1, 40, 40][1, 41, 41][1, 41, 45][1, 41, 55][1, 40, 58]
Non-inverted[8][7][6][5][4][3][2][1][0]
IOB0:NDRIVE[0, 40, 6][0, 41, 21][0, 40, 34][0, 40, 42][0, 41, 49][0, 41, 61]
IOB1:NDRIVE[1, 41, 57][1, 40, 42][1, 41, 29][1, 41, 21][1, 40, 14][1, 40, 2]
Mixed inversion[5][4]~[3]~[2]~[1]~[0]

Bitstream — HCLK_IOI

HCLK_IOI bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031323334353637383940414243
0 --------------------------------------------
1 --------------------------------------------
2 --------------------------------------------
3 --------------------------------------------
4 --------------------------------------------
5 --------------------------------------------
6 --------------------------------------------
7 --------------------------------------------
8 --------------------------------------------
9 --------------------------------------------
10 --------------------------------------------
11 --------------------------------------------
12 --------------------------------------------
13 --------------------------------------------
14 -----------------------------HCLK_IOI:BUF.RCLK0--HCLK_IOI:MUX.RCLK0[2]---HCLK_IOI:BUF.PERF2HCLK_IOI:BUF.PERF3--DCI:PREF_TERM_VCC[0]DCI:PREF_OUTPUT[0]LVDS:LVDSBIAS[15]DCI:PMASK_TERM_VCC[0]
15 -----------------------------HCLK_IOI:BUF.RCLK1--HCLK_IOI:MUX.RCLK0[1]----HCLK_IOI:BUF.PERF1--DCI:PREF_TERM_VCC[1]DCI:PREF_OUTPUT[1]LVDS:LVDSBIAS[14]DCI:NMASK_TERM_SPLIT[0]
16 -----------------------------HCLK_IOI:BUF.RCLK2BUFR0:MUX.I[8]BUFR0:MUX.I[0]HCLK_IOI:MUX.RCLK0[3]---HCLK_IOI:DELAY.IOCLK6HCLK_IOI:BUF.IOCLK6--DCI:NREF_OUTPUT[0]DCI:PREF_OUTPUT_HALF[0]LVDS:LVDSBIAS[13]DCI:NMASK_TERM_SPLIT[1]
17 -----------------------------HCLK_IOI:BUF.RCLK3BUFR0:MUX.I[9]BUFR0:MUX.I[1]HCLK_IOI:MUX.RCLK1[2]----BUFIODQS2:ENABLE--DCI:NREF_OUTPUT[1]DCI:PREF_OUTPUT_HALF[1]LVDS:LVDSBIAS[12]DCI:NMASK_TERM_SPLIT[2]
18 -----------------------------HCLK_IOI:BUF.RCLK4BUFR0:MUX.I[10]BUFR0:MUX.I[2]HCLK_IOI:MUX.RCLK1[1]BUFR0:BUFR_DIVIDE[1]--HCLK_IOI:DELAY.IOCLK2BUFIODQS2:DQSMASK_ENABLE--DCI:NREF_OUTPUT_HALF[0]DCI:PREF_OUTPUT_HALF[2]LVDS:LVDSBIAS[11]DCI:NMASK_TERM_SPLIT[3]
19 -----------------------------HCLK_IOI:BUF.RCLK5BUFR0:MUX.I[11]BUFR0:MUX.I[3]HCLK_IOI:MUX.RCLK1[3]BUFR0:BUFR_DIVIDE[2]---BUFIODQS3:DQSMASK_ENABLE--DCI:NREF_OUTPUT_HALF[1]DCI:PREF_TERM_SPLIT[0]LVDS:LVDSBIAS[10]DCI:NMASK_TERM_SPLIT[4]
20 ---------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.RCLK0[0]HCLK_IOI:BUF.HCLK0BUFR0:MUX.I[12]BUFR0:MUX.I[4]HCLK_IOI:MUX.RCLK2[2]BUFR0:BUFR_DIVIDE[3]--HCLK_IOI:DELAY.IOCLK3BUFIODQS2:MUX.I--DCI:NREF_OUTPUT_HALF[2]DCI:PREF_TERM_SPLIT[1]LVDS:LVDSBIAS[9]DCI:NMASK_TERM_SPLIT[5]
21 ---------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.RCLK1[0]HCLK_IOI:BUF.HCLK1BUFR0:MUX.I[13]BUFR0:MUX.I[5]HCLK_IOI:MUX.RCLK2[1]BUFR0:BUFR_DIVIDE[0]---BUFIODQS3:MUX.I---DCI:PREF_TERM_SPLIT[2]LVDS:LVDSBIAS[8]DCI:PMASK_TERM_SPLIT[0]
22 ---------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.RCLK2[0]HCLK_IOI:BUF.HCLK2BUFR0:MUX.I[15]BUFR0:MUX.I[6]HCLK_IOI:MUX.RCLK2[3]BUFR0:ENABLE--HCLK_IOI:DELAY.IOCLK7BUFIODQS3:ENABLEIDELAYCTRL:HIGH_PERFORMANCE_MODEBUFO0:MUX.I[0]--LVDS:LVDSBIAS[7]DCI:PMASK_TERM_SPLIT[1]
23 ---------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.RCLK3[0]HCLK_IOI:BUF.HCLK3BUFR0:MUX.I[14]BUFR0:MUX.I[7]HCLK_IOI:MUX.RCLK3[2]---HCLK_IOI:BUF.PERF0HCLK_IOI:BUF.IOCLK7-BUFO0:MUX.I[2]DCI:NREF_TERM_SPLIT[0]DCI:TEST_ENABLE[1]LVDS:LVDSBIAS[6]DCI:PMASK_TERM_SPLIT[2]
24 ---------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.RCLK4[0]HCLK_IOI:BUF.HCLK4BUFR1:MUX.I[8]BUFR1:MUX.I[0]HCLK_IOI:MUX.RCLK3[1]----HCLK_IOI:BUF.IOCLK4-BUFO0:MUX.I[3]DCI:NREF_TERM_SPLIT[1]INTERNAL_VREF:VREF[2]LVDS:LVDSBIAS[5]DCI:PMASK_TERM_SPLIT[3]
25 ---------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.RCLK5[0]HCLK_IOI:BUF.HCLK5BUFR1:MUX.I[9]BUFR1:MUX.I[1]HCLK_IOI:MUX.RCLK3[3]---HCLK_IOI:DELAY.IOCLK4BUFIODQS0:ENABLE-BUFO1:MUX.I[2]DCI:NREF_TERM_SPLIT[2]-LVDS:LVDSBIAS[4]DCI:PMASK_TERM_SPLIT[4]
26 ---------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:UNUSED.RCLK0HCLK_IOI:BUF.HCLK6BUFR1:MUX.I[10]BUFR1:MUX.I[2]HCLK_IOI:MUX.RCLK4[2]----BUFIODQS0:DQSMASK_ENABLEIDELAYCTRL:MODE[3]BUFO1:MUX.I[0]INTERNAL_VREF:VREF[0]-LVDS:LVDSBIAS[3]DCI:PMASK_TERM_SPLIT[5]
27 ---------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:UNUSED.RCLK1HCLK_IOI:BUF.HCLK7BUFR1:MUX.I[11]BUFR1:MUX.I[3]HCLK_IOI:MUX.RCLK4[1]BUFR1:ENABLE--HCLK_IOI:DELAY.IOCLK0BUFIODQS1:DQSMASK_ENABLE-BUFO1:MUX.I[3]DCI:CASCADE_FROM_ABOVE-LVDS:LVDSBIAS[2]DCI:PMASK_TERM_VCC[1]
28 ---------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:UNUSED.RCLK2HCLK_IOI:BUF.HCLK8BUFR1:MUX.I[12]BUFR1:MUX.I[4]HCLK_IOI:MUX.RCLK4[3]BUFR1:BUFR_DIVIDE[1]---BUFIODQS0:MUX.IIDELAYCTRL:MODE[1]HCLK_IOI:BUF.VOCLK0DCI:CASCADE_FROM_BELOWLVDS:LVDSBIAS[16]LVDS:LVDSBIAS[1]DCI:PMASK_TERM_VCC[2]
29 ---------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:UNUSED.RCLK3HCLK_IOI:BUF.HCLK9BUFR1:MUX.I[13]BUFR1:MUX.I[5]HCLK_IOI:MUX.RCLK5[2]BUFR1:BUFR_DIVIDE[2]--HCLK_IOI:DELAY.IOCLK1BUFIODQS1:MUX.IIDELAYCTRL:MODE[0]HCLK_IOI:BUF.VOCLK1INTERNAL_VREF:VREF[4]INTERNAL_VREF:VREF[3]DCI:DYNAMIC_ENABLEDCI:PMASK_TERM_VCC[3]
30 ---------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:UNUSED.RCLK4HCLK_IOI:BUF.HCLK10BUFR1:MUX.I[15]BUFR1:MUX.I[6]HCLK_IOI:MUX.RCLK5[1]BUFR1:BUFR_DIVIDE[3]---BUFIODQS1:ENABLEIDELAYCTRL:MODE[2]BUFO0:MUX.I[1]INTERNAL_VREF:VREF[5]INTERNAL_VREF:VREF[1]LVDS:LVDSBIAS[0]DCI:PMASK_TERM_VCC[4]
31 ---------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:UNUSED.RCLK5HCLK_IOI:BUF.HCLK11BUFR1:MUX.I[14]BUFR1:MUX.I[7]HCLK_IOI:MUX.RCLK5[3]BUFR1:BUFR_DIVIDE[0]--HCLK_IOI:DELAY.IOCLK5HCLK_IOI:BUF.IOCLK5IDELAYCTRL:RESET_STYLEBUFO1:MUX.I[1]DCI:TEST_ENABLE[0]DCI:QUIETDCI:ENABLEDCI:PMASK_TERM_VCC[5]
IDELAYCTRL:MUX.REFCLK[0, 27, 20][0, 27, 21][0, 27, 22][0, 27, 23][0, 27, 24][0, 27, 25][0, 27, 26][0, 27, 27][0, 27, 28][0, 27, 29][0, 27, 30][0, 27, 31]
HCLK0000000000001
HCLK1000000000010
HCLK2000000000100
HCLK3000000001000
HCLK4000000010000
HCLK5000000100000
HCLK6000001000000
HCLK7000010000000
HCLK8000100000000
HCLK9001000000000
HCLK10010000000000
HCLK11100000000000
HCLK_IOI:MUX.RCLK0[0, 32, 16][0, 32, 14][0, 32, 15][0, 28, 20]
HCLK_IOI:MUX.RCLK1[0, 32, 19][0, 32, 17][0, 32, 18][0, 28, 21]
HCLK_IOI:MUX.RCLK2[0, 32, 22][0, 32, 20][0, 32, 21][0, 28, 22]
HCLK_IOI:MUX.RCLK3[0, 32, 25][0, 32, 23][0, 32, 24][0, 28, 23]
HCLK_IOI:MUX.RCLK4[0, 32, 28][0, 32, 26][0, 32, 27][0, 28, 24]
HCLK_IOI:MUX.RCLK5[0, 32, 31][0, 32, 29][0, 32, 30][0, 28, 25]
NONE0000
VRCLK0_N0001
VRCLK00011
VRCLK1_N0101
VRCLK10111
VRCLK0_S1001
VRCLK1_S1101
BUFIODQS0:DQSMASK_ENABLE[0, 37, 26]
BUFIODQS0:ENABLE[0, 37, 25]
BUFIODQS1:DQSMASK_ENABLE[0, 37, 27]
BUFIODQS1:ENABLE[0, 37, 30]
BUFIODQS2:DQSMASK_ENABLE[0, 37, 18]
BUFIODQS2:ENABLE[0, 37, 17]
BUFIODQS3:DQSMASK_ENABLE[0, 37, 19]
BUFIODQS3:ENABLE[0, 37, 22]
BUFR0:ENABLE[0, 33, 22]
BUFR1:ENABLE[0, 33, 27]
DCI:CASCADE_FROM_ABOVE[0, 40, 27]
DCI:CASCADE_FROM_BELOW[0, 40, 28]
DCI:DYNAMIC_ENABLE[0, 42, 29]
DCI:ENABLE[0, 42, 31]
DCI:QUIET[0, 41, 31]
HCLK_IOI:BUF.HCLK0[0, 29, 20]
HCLK_IOI:BUF.HCLK1[0, 29, 21]
HCLK_IOI:BUF.HCLK10[0, 29, 30]
HCLK_IOI:BUF.HCLK11[0, 29, 31]
HCLK_IOI:BUF.HCLK2[0, 29, 22]
HCLK_IOI:BUF.HCLK3[0, 29, 23]
HCLK_IOI:BUF.HCLK4[0, 29, 24]
HCLK_IOI:BUF.HCLK5[0, 29, 25]
HCLK_IOI:BUF.HCLK6[0, 29, 26]
HCLK_IOI:BUF.HCLK7[0, 29, 27]
HCLK_IOI:BUF.HCLK8[0, 29, 28]
HCLK_IOI:BUF.HCLK9[0, 29, 29]
HCLK_IOI:BUF.IOCLK4[0, 37, 24]
HCLK_IOI:BUF.IOCLK5[0, 37, 31]
HCLK_IOI:BUF.IOCLK6[0, 37, 16]
HCLK_IOI:BUF.IOCLK7[0, 37, 23]
HCLK_IOI:BUF.PERF0[0, 36, 23]
HCLK_IOI:BUF.PERF1[0, 37, 15]
HCLK_IOI:BUF.PERF2[0, 36, 14]
HCLK_IOI:BUF.PERF3[0, 37, 14]
HCLK_IOI:BUF.RCLK0[0, 29, 14]
HCLK_IOI:BUF.RCLK1[0, 29, 15]
HCLK_IOI:BUF.RCLK2[0, 29, 16]
HCLK_IOI:BUF.RCLK3[0, 29, 17]
HCLK_IOI:BUF.RCLK4[0, 29, 18]
HCLK_IOI:BUF.RCLK5[0, 29, 19]
HCLK_IOI:BUF.VOCLK0[0, 39, 28]
HCLK_IOI:BUF.VOCLK1[0, 39, 29]
HCLK_IOI:DELAY.IOCLK0[0, 36, 27]
HCLK_IOI:DELAY.IOCLK1[0, 36, 29]
HCLK_IOI:DELAY.IOCLK2[0, 36, 18]
HCLK_IOI:DELAY.IOCLK3[0, 36, 20]
HCLK_IOI:DELAY.IOCLK4[0, 36, 25]
HCLK_IOI:DELAY.IOCLK5[0, 36, 31]
HCLK_IOI:DELAY.IOCLK6[0, 36, 16]
HCLK_IOI:DELAY.IOCLK7[0, 36, 22]
HCLK_IOI:UNUSED.RCLK0[0, 28, 26]
HCLK_IOI:UNUSED.RCLK1[0, 28, 27]
HCLK_IOI:UNUSED.RCLK2[0, 28, 28]
HCLK_IOI:UNUSED.RCLK3[0, 28, 29]
HCLK_IOI:UNUSED.RCLK4[0, 28, 30]
HCLK_IOI:UNUSED.RCLK5[0, 28, 31]
IDELAYCTRL:HIGH_PERFORMANCE_MODE[0, 38, 22]
Non-inverted[0]
BUFR0:MUX.I[0, 30, 22][0, 30, 23][0, 30, 21][0, 30, 20][0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 31, 23][0, 31, 22][0, 31, 21][0, 31, 20][0, 31, 19][0, 31, 18][0, 31, 17][0, 31, 16]
BUFR1:MUX.I[0, 30, 30][0, 30, 31][0, 30, 29][0, 30, 28][0, 30, 27][0, 30, 26][0, 30, 25][0, 30, 24][0, 31, 31][0, 31, 30][0, 31, 29][0, 31, 28][0, 31, 27][0, 31, 26][0, 31, 25][0, 31, 24]
NONE0000000000000000
BUFIO0_I0000000000000001
BUFIO1_I0000000000000010
BUFIO2_I0000000000000100
BUFIO3_I0000000000001000
MGT00000000000010000
MGT10000000000100000
MGT20000000001000000
MGT30000000010000000
MGT40000000100000000
MGT50000001000000000
MGT60000010000000000
MGT70000100000000000
MGT80001000000000000
MGT90010000000000000
CKINT00100000000000000
CKINT11000000000000000
BUFR0:BUFR_DIVIDE[0, 33, 20][0, 33, 19][0, 33, 18][0, 33, 21]
BUFR1:BUFR_DIVIDE[0, 33, 30][0, 33, 29][0, 33, 28][0, 33, 31]
BYPASS0000
10001
20011
30101
40111
51001
61011
71101
81111
BUFIODQS2:MUX.I[0, 37, 20]
CCIO0
PERF31
BUFIODQS3:MUX.I[0, 37, 21]
CCIO0
PERF21
BUFIODQS0:MUX.I[0, 37, 28]
CCIO0
PERF11
BUFIODQS1:MUX.I[0, 37, 29]
CCIO0
PERF01
IDELAYCTRL:MODE[0, 38, 26][0, 38, 30][0, 38, 28][0, 38, 29]
NONE0000
DEFAULT0011
FULL_00101
FULL_11101
IDELAYCTRL:RESET_STYLE[0, 38, 31]
V50
V41
BUFO0:MUX.I[0, 39, 24][0, 39, 23][0, 39, 30][0, 39, 22]
VOCLK00000
VOCLK0_S0011
VOCLK0_N1100
BUFO1:MUX.I[0, 39, 27][0, 39, 25][0, 39, 31][0, 39, 26]
VOCLK10000
VOCLK1_S0011
VOCLK1_N1100
DCI:NREF_OUTPUT[0, 40, 17][0, 40, 16]
DCI:PREF_OUTPUT[0, 41, 15][0, 41, 14]
DCI:PREF_TERM_VCC[0, 40, 15][0, 40, 14]
DCI:TEST_ENABLE[0, 41, 23][0, 40, 31]
Non-inverted[1][0]
DCI:NREF_OUTPUT_HALF[0, 40, 20][0, 40, 19][0, 40, 18]
DCI:NREF_TERM_SPLIT[0, 40, 25][0, 40, 24][0, 40, 23]
DCI:PREF_OUTPUT_HALF[0, 41, 18][0, 41, 17][0, 41, 16]
DCI:PREF_TERM_SPLIT[0, 41, 21][0, 41, 20][0, 41, 19]
Non-inverted[2][1][0]
INTERNAL_VREF:VREF[0, 40, 30][0, 40, 29][0, 41, 29][0, 41, 24][0, 41, 30][0, 40, 26]
OFF000000
600000011
750000101
900001001
1100010001
1250100001
LVDS:LVDSBIAS[0, 41, 28][0, 42, 14][0, 42, 15][0, 42, 16][0, 42, 17][0, 42, 18][0, 42, 19][0, 42, 20][0, 42, 21][0, 42, 22][0, 42, 23][0, 42, 24][0, 42, 25][0, 42, 26][0, 42, 27][0, 42, 28][0, 42, 30]
Non-inverted[16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
DCI:NMASK_TERM_SPLIT[0, 43, 20][0, 43, 19][0, 43, 18][0, 43, 17][0, 43, 16][0, 43, 15]
DCI:PMASK_TERM_SPLIT[0, 43, 26][0, 43, 25][0, 43, 24][0, 43, 23][0, 43, 22][0, 43, 21]
DCI:PMASK_TERM_VCC[0, 43, 31][0, 43, 30][0, 43, 29][0, 43, 28][0, 43, 27][0, 43, 14]
Non-inverted[5][4][3][2][1][0]

Tables

NameIOSTD:PDRIVEIOSTD:NDRIVE
[5][4][3][2][1][0][5][4][3][2][1][0]
BLVDS_25101100101100
HSTL_I011110001001
HSTL_II111010010001
HSTL_III011110011010
HSTL_III_18010110011010
HSTL_III_DCI011110011010
HSTL_III_DCI_18010110011010
HSTL_II_18101011010001
HSTL_II_DCI111010010001
HSTL_II_DCI_18101011010001
HSTL_II_T_DCI011110001001
HSTL_II_T_DCI_18010110001001
HSTL_I_12111001001100
HSTL_I_18010110001001
HSTL_I_DCI011110001001
HSTL_I_DCI_18010110001001
LVCMOS12.2001111000011
LVCMOS12.4011101000110
LVCMOS12.6101010001001
LVCMOS12.8111001001100
LVCMOS15.12101111001110
LVCMOS15.16111111010011
LVCMOS15.2001000000011
LVCMOS15.4010000000101
LVCMOS15.6011000000111
LVCMOS15.8100000001010
LVCMOS18.12011111001100
LVCMOS18.16100111010000
LVCMOS18.2000101000010
LVCMOS18.4001010000100
LVCMOS18.6001111000110
LVCMOS18.8010101001000
LVCMOS25.12010111001111
LVCMOS25.16011111010001
LVCMOS25.2000100000010
LVCMOS25.24101111011010
LVCMOS25.4001000000100
LVCMOS25.6001100000110
LVCMOS25.8010000001001
LVPECL_25110000111100
OFF000000000000
SSTL15100100001010
SSTL15_DCI100100001010
SSTL15_T_DCI100100001010
SSTL18_I010011001000
SSTL18_II111000010110
SSTL18_II_DCI011010001011
SSTL18_II_T_DCI001111000110
SSTL18_I_DCI001111000110
SSTL2_I001101000111
SSTL2_II100011010100
SSTL2_II_DCI010001001001
SSTL2_II_T_DCI001001000101
SSTL2_I_DCI001001000101
VR000000000000
NameIOSTD:PSLEWIOSTD:NSLEW
[4][3][2][1][0][4][3][2][1][0]
BLVDS_250010111111
HSLVDCI_150111100111
HSLVDCI_180000011111
HSLVDCI_250000011111
HSTL_I0100110111
HSTL_II0001111100
HSTL_III0000010111
HSTL_III_180000011111
HSTL_III_DCI0000011110
HSTL_III_DCI_180000111111
HSTL_II_180001001001
HSTL_II_DCI0111111111
HSTL_II_DCI_180111001111
HSTL_II_T_DCI1010011110
HSTL_II_T_DCI_180011100111
HSTL_I_120011110000
HSTL_I_180011110111
HSTL_I_DCI1010011110
HSTL_I_DCI_180011100111
LVCMOS12.2.FAST1111111000
LVCMOS12.2.SLOW0000100001
LVCMOS12.4.FAST1111111111
LVCMOS12.4.SLOW0000100001
LVCMOS12.6.FAST1111111111
LVCMOS12.6.SLOW0000100100
LVCMOS12.8.FAST1100111111
LVCMOS12.8.SLOW0000100011
LVCMOS15.12.FAST0100011111
LVCMOS15.12.SLOW0000100100
LVCMOS15.16.FAST0011011111
LVCMOS15.16.SLOW0000100111
LVCMOS15.2.FAST1111100001
LVCMOS15.2.SLOW1001000001
LVCMOS15.4.FAST1111111111
LVCMOS15.4.SLOW0000100100
LVCMOS15.6.FAST1111111111
LVCMOS15.6.SLOW0000100100
LVCMOS15.8.FAST0100111111
LVCMOS15.8.SLOW0000100100
LVCMOS18.12.FAST0011011111
LVCMOS18.12.SLOW0000100100
LVCMOS18.16.FAST0011011111
LVCMOS18.16.SLOW0000100111
LVCMOS18.2.FAST1000111111
LVCMOS18.2.SLOW0000100111
LVCMOS18.4.FAST1111111111
LVCMOS18.4.SLOW0000100100
LVCMOS18.6.FAST0011111111
LVCMOS18.6.SLOW0000100101
LVCMOS18.8.FAST0011011111
LVCMOS18.8.SLOW0000100101
LVCMOS25.12.FAST0011011111
LVCMOS25.12.SLOW0000101010
LVCMOS25.16.FAST0000111111
LVCMOS25.16.SLOW0000000101
LVCMOS25.2.FAST1111111111
LVCMOS25.2.SLOW0000011111
LVCMOS25.24.FAST0001011111
LVCMOS25.24.SLOW0000110100
LVCMOS25.4.FAST1111111111
LVCMOS25.4.SLOW0000011111
LVCMOS25.6.FAST0001011111
LVCMOS25.6.SLOW0000101010
LVCMOS25.8.FAST0000111111
LVCMOS25.8.SLOW0000101010
LVDCI_150111100111
LVDCI_180000011111
LVDCI_250000011111
LVDCI_DV2_151111100001
LVDCI_DV2_180000001101
LVDCI_DV2_250000011111
LVPECL_250011011111
OFF0000000000
SSTL150110011110
SSTL15_DCI1010110111
SSTL15_T_DCI1010110111
SSTL18_I0111011111
SSTL18_II0011011111
SSTL18_II_DCI1000011111
SSTL18_II_T_DCI1000000011
SSTL18_I_DCI1000000011
SSTL2_I0001111111
SSTL2_II0001111111
SSTL2_II_DCI0010101010
SSTL2_II_T_DCI0001111111
SSTL2_I_DCI0001111111
VR1111111111
NameIOSTD:OUTPUT_MISC
[3][2][1][0]
BLVDS_250000
HSLVDCI_150000
HSLVDCI_180000
HSLVDCI_250000
HSTL_I0000
HSTL_II0000
HSTL_III0000
HSTL_III_180000
HSTL_III_DCI0000
HSTL_III_DCI_180000
HSTL_II_180000
HSTL_II_DCI0000
HSTL_II_DCI_180000
HSTL_II_T_DCI0000
HSTL_II_T_DCI_180000
HSTL_I_121000
HSTL_I_180000
HSTL_I_DCI0000
HSTL_I_DCI_180000
LVCMOS121000
LVCMOS151000
LVCMOS180000
LVCMOS250000
LVDCI_150000
LVDCI_180000
LVDCI_250000
LVDCI_DV2_150000
LVDCI_DV2_180000
LVDCI_DV2_250000
LVPECL_250000
OFF0000
SSTL150000
SSTL15_DCI0000
SSTL15_T_DCI0000
SSTL18_I0000
SSTL18_II0000
SSTL18_II_DCI0000
SSTL18_II_T_DCI0000
SSTL18_I_DCI0000
SSTL2_I0000
SSTL2_II0000
SSTL2_II_DCI0000
SSTL2_II_T_DCI0000
SSTL2_I_DCI0000
NameIOSTD:LVDS_TIOSTD:LVDS_C
[8][7][6][5][4][3][2][1][0][8][7][6][5][4][3][2][1][0]
OFF000000000000000000
OUTPUT_HT_25101100000011001110
OUTPUT_LVDSEXT_25110100000000011110
OUTPUT_LVDS_25100100000000011110
OUTPUT_RSDS_25100100000000011110
TERM_DYNAMIC_HT_25000000010111001110
TERM_DYNAMIC_LVDSEXT_25000000010100011110
TERM_DYNAMIC_LVDS_25000000010100011110
TERM_DYNAMIC_RSDS_25000000010100011110
TERM_HT_25000000000111001110
TERM_LVDSEXT_25000000000100011110
TERM_LVDS_25000000000100011110
TERM_RSDS_25000000000100011110
NameIOSTD:LVDSBIAS
[16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
HT_2510100010101000010
LVDSEXT_2510100010101000010
LVDS_2510100010101000010
OFF00000000000000000
RSDS_2510100010101000010
NameIOSTD:DCI:PREF_OUTPUTIOSTD:DCI:NREF_OUTPUT
[1][0][1][0]
HSLVDCI_150000
HSLVDCI_180000
HSLVDCI_250000
LVDCI_150000
LVDCI_180000
LVDCI_250000
OFF0000
NameIOSTD:DCI:PREF_OUTPUT_HALFIOSTD:DCI:NREF_OUTPUT_HALF
[2][1][0][2][1][0]
LVDCI_DV2_15011011
LVDCI_DV2_18011011
LVDCI_DV2_25011011
OFF000000
NameIOSTD:DCI:PREF_TERM_VCCIOSTD:DCI:PMASK_TERM_VCC
[1][0][5][4][3][2][1][0]
HSTL_III_DCI10000000
HSTL_III_DCI_1810000000
OFF00000000
NameIOSTD:DCI:PREF_TERM_SPLITIOSTD:DCI:NREF_TERM_SPLITIOSTD:DCI:PMASK_TERM_SPLITIOSTD:DCI:NMASK_TERM_SPLIT
[2][1][0][2][1][0][5][4][3][2][1][0][5][4][3][2][1][0]
HSTL_II_DCI000000010111100010
HSTL_II_DCI_18000000110101100010
HSTL_II_T_DCI000000011110100100
HSTL_II_T_DCI_18000000011010100100
HSTL_I_DCI000000000000000000
HSTL_I_DCI_18000000000000000000
OFF000000000000000000
SSTL15_DCI000000000000000000
SSTL15_T_DCI000000001001010100
SSTL18_II_DCI000000010110110100
SSTL18_II_T_DCI000000111100011000
SSTL18_I_DCI000000000000000000
SSTL2_II_DCI000000100010100100
SSTL2_II_T_DCI000000100100101000
SSTL2_I_DCI000000000000000000
DeviceIODELAY:DEFAULT_IDELAY_VALUE
[4][3][2][1][0]
xc6vcx130t10110
xc6vcx195t11011
xc6vcx240t11011
xc6vcx75t10011
xc6vhx250t10010
xc6vhx255t01100
xc6vhx380t10010
xc6vhx565t11000
xc6vlx130t10110
xc6vlx130tl10110
xc6vlx195t11011
xc6vlx195tl11011
xc6vlx240t11011
xc6vlx240tl11011
xc6vlx365t01100
xc6vlx365tl01100
xc6vlx550t10110
xc6vlx550tl10110
xc6vlx75t10011
xc6vlx75tl10011
xc6vlx76011011
xc6vlx760l11011
xc6vsx315t10010
xc6vsx315tl10010
xc6vsx475t11000
xc6vsx475tl11000
xq6vlx130t10110
xq6vlx130tl10110
xq6vlx240t11011
xq6vlx240tl11011
xq6vlx550t10110
xq6vlx550tl10110
xq6vsx315t10010
xq6vsx315tl10010
xq6vsx475t11000
xq6vsx475tl11000