Input/Output
I/O banks and special functions
Virtex 6 devices have a very regular I/O bank structure. There are up to four I/O columns in the device:
outer left (sometimes present)
inner left (always present)
inner right (always present)
outer right (sometimes present)
These columns consist entirely of IO tiles, with one tile per two interconnect rows. Every tile contains two I/O pads: IOB0 and IOB1. IOB0 is located in the bottom row of the tile, while IOB1 is located in the top row. Every I/O bank consists of exactly one region, or 40 I/O pads. The banks are numbered as follows:
the bank in region
c + iof outer left column (wherecis the region containing the top half of theCFGtile) has number15 + ithe bank in region
c + iof inner left column has number25 + ithe bank in region
c + iof inner right column has number35 + ithe bank in region
c + iof outer right column has number45 + i
All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input and true differential output is supported on all pins of the device.
IOB1 pads in the 8 rows surrounding the HCLK row (that is, rows 17, 19, 21, 23) are considered “clock-capable”. They can drive BUFIODQS buffers via dedicated connections. The ones in rows 19 and 21 can drive BUFR buffers in this and two surrounding regions, and are considered “multi-region clock capable”, while the ones in rows 17 and 23 are considered “single-region clock capable”. While Xilinx documentation also considers corresponding IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.
There are 8 IOB1s that are considered “global clock-capable” and can drive BUFGCTRL global buffers via dedicated interconnect. They are:
bank 24 rows 37, 39
bank 25 rows 1, 3
bank 34 rows 37, 39
bank 35 rows 1, 3
The IOB0 in rows 10 and 30 of every region is capable of being used as a VREF pad.
Each bank has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:
bank 24: rows 4-5
bank 34: rows 0-1
banks 15, 25, 35: rows 6-7
all other banks: rows 14-15
In parallel or SPI configuration modes, some I/O pads in banks 24 and 34 are borrowed for configuration use:
bank 24 row 6:
CSO_Bbank 24 row 7:
RS[0]bank 24 row 8:
RS[1]bank 24 row 9:
FWE_Bbank 24 row 10:
FOE_B/MOSIbank 24 row 11:
FCS_Bbank 24 row 12:
D[0]/FS[0]bank 24 row 13:
D[1]/FS[1]bank 24 row 14:
D[2]/FS[2]bank 24 row 15:
D[3]bank 24 row 24:
D[4]bank 24 row 25:
D[5]bank 24 row 26:
D[6]bank 24 row 27:
D[7]bank 24 row 28:
D[8]bank 24 row 29:
D[9]bank 24 row 30:
D[10]bank 24 row 31:
D[11]bank 24 row 32:
D[12]bank 24 row 33:
D[13]bank 24 row 34:
D[14]bank 24 row 35:
D[15]bank 34 row 2:
A[16]bank 34 row 3:
A[17]bank 34 row 4:
A[18]bank 34 row 5:
A[19]bank 34 row 6:
A[20]bank 34 row 7:
A[21]bank 34 row 8:
A[22]bank 34 row 9:
A[23]bank 34 row 10:
A[24]bank 34 row 11:
A[25]bank 34 row 12:
D[16]/A[0]bank 34 row 13:
D[17]/A[1]bank 34 row 14:
D[18]/A[2]bank 34 row 15:
D[19]/A[3]bank 34 row 24:
D[20]/A[4]bank 34 row 25:
D[21]/A[5]bank 34 row 26:
D[22]/A[6]bank 34 row 27:
D[23]/A[7]bank 34 row 28:
D[24]/A[8]bank 34 row 29:
D[25]/A[9]bank 34 row 30:
D[26]/A[10]bank 34 row 31:
D[27]/A[11]bank 34 row 32:
D[28]/A[12]bank 34 row 33:
D[29]/A[13]bank 34 row 34:
D[30]/A[14]bank 34 row 35:
D[31]/A[15]
The SYSMON present on the device can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. If the device has a outer left IO column, the IOBs are located in banks 15 and 35; otherwise, they are located in banks 25 and 35. The IOBs are in the following tiles:
VP0/VN0: bank 35 rows 34-35VP1/VN1: bank 35 rows 32-33VP2/VN2: bank 35 rows 28-29VP3/VN3: bank 35 rows 26-27VP4/VN4: bank 35 rows 24-25VP5/VN5: bank 35 rows 14-15VP6/VN6: bank 35 rows 12-13VP7/VN7: bank 35 rows 8-9VP8/VN8: bank 15/25 rows 34-35VP9/VN9: bank 15/25 rows 32-33VP10/VN10: bank 15/25 rows 28-29VP11/VN11: bank 15/25 rows 26-27VP12/VN12: bank 15/25 rows 24-25VP13/VN13: bank 15/25 rows 14-15VP14/VN14: bank 15/25 rows 12-13VP15/VN15: bank 15/25 rows 8-9
The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:
CCLKCSI_BDINDONEDOUT_BUSYHSWAPENINIT_BM0,M1,M2PROGRAM_BRDWR_BTCK,TDI,TDO,TMS
Bitstream — IO
| Name | IOSTD:PDRIVE | IOSTD:NDRIVE | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [5] | [4] | [3] | [2] | [1] | [0] | [5] | [4] | [3] | [2] | [1] | [0] | |
| BLVDS_25 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
| HSTL_I | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_II | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| HSTL_III | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| HSTL_III_18 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| HSTL_III_DCI | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| HSTL_III_DCI_18 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| HSTL_II_18 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 |
| HSTL_II_DCI | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| HSTL_II_DCI_18 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 |
| HSTL_II_T_DCI | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_II_T_DCI_18 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_I_12 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| HSTL_I_18 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_I_DCI | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_I_DCI_18 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| LVCMOS12.2 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| LVCMOS12.4 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| LVCMOS12.6 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| LVCMOS12.8 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| LVCMOS15.12 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |
| LVCMOS15.16 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| LVCMOS15.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| LVCMOS15.4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| LVCMOS15.6 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| LVCMOS15.8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| LVCMOS18.12 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| LVCMOS18.16 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| LVCMOS18.2 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| LVCMOS18.4 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS18.6 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| LVCMOS18.8 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| LVCMOS25.12 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
| LVCMOS25.16 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 |
| LVCMOS25.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| LVCMOS25.24 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| LVCMOS25.4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS25.6 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| LVCMOS25.8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| LVPECL_25 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SSTL15 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| SSTL15_DCI | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| SSTL15_T_DCI | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| SSTL18_I | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| SSTL18_II | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| SSTL18_II_DCI | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
| SSTL18_II_T_DCI | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| SSTL18_I_DCI | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| SSTL2_I | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
| SSTL2_II | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| SSTL2_II_DCI | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| SSTL2_II_T_DCI | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| SSTL2_I_DCI | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| VR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | IOSTD:PSLEW | IOSTD:NSLEW | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| [4] | [3] | [2] | [1] | [0] | [4] | [3] | [2] | [1] | [0] | |
| BLVDS_25 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| HSLVDCI_15 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
| HSLVDCI_18 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| HSLVDCI_25 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| HSTL_I | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| HSTL_II | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| HSTL_III | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
| HSTL_III_18 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| HSTL_III_DCI | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| HSTL_III_DCI_18 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| HSTL_II_18 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| HSTL_II_DCI | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| HSTL_II_DCI_18 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
| HSTL_II_T_DCI | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| HSTL_II_T_DCI_18 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
| HSTL_I_12 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| HSTL_I_18 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| HSTL_I_DCI | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| HSTL_I_DCI_18 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
| LVCMOS12.2.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| LVCMOS12.2.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| LVCMOS12.4.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS12.4.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| LVCMOS12.6.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS12.6.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS12.8.FAST | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS12.8.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
| LVCMOS15.12.FAST | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS15.12.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS15.16.FAST | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS15.16.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
| LVCMOS15.2.FAST | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| LVCMOS15.2.SLOW | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| LVCMOS15.4.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS15.4.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS15.6.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS15.6.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS15.8.FAST | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS15.8.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS18.12.FAST | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.12.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS18.16.FAST | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.16.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
| LVCMOS18.2.FAST | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.2.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
| LVCMOS18.4.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.4.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| LVCMOS18.6.FAST | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.6.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| LVCMOS18.8.FAST | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS18.8.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| LVCMOS25.12.FAST | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.12.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| LVCMOS25.16.FAST | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.16.SLOW | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| LVCMOS25.2.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.2.SLOW | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.24.FAST | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.24.SLOW | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| LVCMOS25.4.FAST | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.4.SLOW | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.6.FAST | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.6.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| LVCMOS25.8.FAST | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| LVCMOS25.8.SLOW | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| LVDCI_15 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
| LVDCI_18 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVDCI_25 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVDCI_DV2_15 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| LVDCI_DV2_18 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| LVDCI_DV2_25 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| LVPECL_25 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SSTL15 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| SSTL15_DCI | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| SSTL15_T_DCI | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
| SSTL18_I | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| SSTL18_II | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| SSTL18_II_DCI | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| SSTL18_II_T_DCI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| SSTL18_I_DCI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| SSTL2_I | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| SSTL2_II | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| SSTL2_II_DCI | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| SSTL2_II_T_DCI | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| SSTL2_I_DCI | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| VR | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | IOSTD:OUTPUT_MISC | |||
|---|---|---|---|---|
| [3] | [2] | [1] | [0] | |
| BLVDS_25 | 0 | 0 | 0 | 0 |
| HSLVDCI_15 | 0 | 0 | 0 | 0 |
| HSLVDCI_18 | 0 | 0 | 0 | 0 |
| HSLVDCI_25 | 0 | 0 | 0 | 0 |
| HSTL_I | 0 | 0 | 0 | 0 |
| HSTL_II | 0 | 0 | 0 | 0 |
| HSTL_III | 0 | 0 | 0 | 0 |
| HSTL_III_18 | 0 | 0 | 0 | 0 |
| HSTL_III_DCI | 0 | 0 | 0 | 0 |
| HSTL_III_DCI_18 | 0 | 0 | 0 | 0 |
| HSTL_II_18 | 0 | 0 | 0 | 0 |
| HSTL_II_DCI | 0 | 0 | 0 | 0 |
| HSTL_II_DCI_18 | 0 | 0 | 0 | 0 |
| HSTL_II_T_DCI | 0 | 0 | 0 | 0 |
| HSTL_II_T_DCI_18 | 0 | 0 | 0 | 0 |
| HSTL_I_12 | 1 | 0 | 0 | 0 |
| HSTL_I_18 | 0 | 0 | 0 | 0 |
| HSTL_I_DCI | 0 | 0 | 0 | 0 |
| HSTL_I_DCI_18 | 0 | 0 | 0 | 0 |
| LVCMOS12 | 1 | 0 | 0 | 0 |
| LVCMOS15 | 1 | 0 | 0 | 0 |
| LVCMOS18 | 0 | 0 | 0 | 0 |
| LVCMOS25 | 0 | 0 | 0 | 0 |
| LVDCI_15 | 0 | 0 | 0 | 0 |
| LVDCI_18 | 0 | 0 | 0 | 0 |
| LVDCI_25 | 0 | 0 | 0 | 0 |
| LVDCI_DV2_15 | 0 | 0 | 0 | 0 |
| LVDCI_DV2_18 | 0 | 0 | 0 | 0 |
| LVDCI_DV2_25 | 0 | 0 | 0 | 0 |
| LVPECL_25 | 0 | 0 | 0 | 0 |
| OFF | 0 | 0 | 0 | 0 |
| SSTL15 | 0 | 0 | 0 | 0 |
| SSTL15_DCI | 0 | 0 | 0 | 0 |
| SSTL15_T_DCI | 0 | 0 | 0 | 0 |
| SSTL18_I | 0 | 0 | 0 | 0 |
| SSTL18_II | 0 | 0 | 0 | 0 |
| SSTL18_II_DCI | 0 | 0 | 0 | 0 |
| SSTL18_II_T_DCI | 0 | 0 | 0 | 0 |
| SSTL18_I_DCI | 0 | 0 | 0 | 0 |
| SSTL2_I | 0 | 0 | 0 | 0 |
| SSTL2_II | 0 | 0 | 0 | 0 |
| SSTL2_II_DCI | 0 | 0 | 0 | 0 |
| SSTL2_II_T_DCI | 0 | 0 | 0 | 0 |
| SSTL2_I_DCI | 0 | 0 | 0 | 0 |
| Name | IOSTD:LVDS_T | IOSTD:LVDS_C | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] | |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OUTPUT_HT_25 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |
| OUTPUT_LVDSEXT_25 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| OUTPUT_LVDS_25 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| OUTPUT_RSDS_25 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_DYNAMIC_HT_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |
| TERM_DYNAMIC_LVDSEXT_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_DYNAMIC_LVDS_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_DYNAMIC_RSDS_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_HT_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |
| TERM_LVDSEXT_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_LVDS_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| TERM_RSDS_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| IO bittile 0 | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Row | Column | |||||||||||||||||||||||||||||||||||||||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:IBUF_MODE[0] | - |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:IBUF_MODE[1] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:IBUF_MODE[3] | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:VREF_SYSMON |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:IBUF_MODE[4] | - |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[0] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NDRIVE[5] | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PDRIVE[5] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[1] | - |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[3] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PSLEW[4] | - |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_MODE[1] | - |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:VR |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_MODE[0] | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NSLEW[3] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[2] | - |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_MODE[2] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PSLEW[3] | - |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NDRIVE[4] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[3] | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[4] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[1] | - |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[2] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:PDRIVE[4] | - |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PSLEW[2] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_ENABLE[0] | - |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_ENABLE[1] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NSLEW[1] | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PSLEW[1] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NSLEW[2] | - |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[5] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:NDRIVE[3] | - |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[0] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OMUX | - |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PULL_DYNAMIC |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[6] | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PSLEW[0] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PDRIVE[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:NDRIVE[2] | - |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NSLEW[4] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:NSLEW[0] | - |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:PDRIVE[2] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PULL[0] | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PULL[1] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:PULL[2] | - |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:NDRIVE[1] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[7] | - |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_DELAY |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:PDRIVE[1] | - |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:DCIUPDATEMODE_ASREQUIRED | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:LVDS[8] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:PDRIVE[0] | - |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_MISC[1] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_MISC[0] | - |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:NDRIVE[0] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:DCI_T | - |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:IBUF_MODE[2] |
| IO bittile 1 | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Row | Column | |||||||||||||||||||||||||||||||||||||||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:IBUF_MODE[2] | - |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_T |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:NDRIVE[0] | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_MISC[0] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_MISC[1] | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:PDRIVE[0] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[8] | - |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:DCIUPDATEMODE_ASREQUIRED |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:PDRIVE[1] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_DELAY | - |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[7] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:NDRIVE[1] | - |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PULL[2] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PULL[1] | - |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PULL[0] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:PDRIVE[2] | - |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NSLEW[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NSLEW[4] | - |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:NDRIVE[2] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PDRIVE[3] | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PSLEW[0] | - |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[6] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PULL_DYNAMIC | - |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_MISC[0] | - |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:NDRIVE[3] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[5] | - |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NSLEW[2] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PSLEW[1] | - |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NSLEW[1] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_ENABLE[0] | - |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_ENABLE[1] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PSLEW[2] | - |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB1:PDRIVE[4] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_MISC[2] | - |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_MISC[1] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[4] | - |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NDRIVE[4] | - |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PSLEW[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_MODE[2] | - |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[2] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NSLEW[3] | - |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_MODE[0] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:VR | - |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:DCI_MODE[1] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PSLEW[4] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:OUTPUT_MISC[3] | - |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[1] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:PDRIVE[5] | - |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:NDRIVE[5] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:LVDS[0] | - |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:IBUF_MODE[4] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:VREF_SYSMON | - |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:IBUF_MODE[3] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:IBUF_MODE[1] | - |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB1:IBUF_MODE[0] |
| IOB0:IBUF_MODE | [0, 40, 4] | [0, 40, 2] | [0, 41, 63] | [0, 41, 1] | [0, 40, 0] |
|---|---|---|---|---|---|
| IOB1:IBUF_MODE | [1, 41, 59] | [1, 41, 61] | [1, 40, 0] | [1, 40, 62] | [1, 41, 63] |
| OFF | 0 | 0 | 0 | 0 | 0 |
| VREF_LP | 0 | 0 | 0 | 0 | 1 |
| DIFF_LP | 0 | 0 | 0 | 1 | 0 |
| CMOS12 | 0 | 0 | 0 | 1 | 1 |
| CMOS | 0 | 0 | 1 | 1 | 1 |
| VREF_HP | 0 | 1 | 0 | 0 | 1 |
| DIFF_HP | 1 | 0 | 0 | 1 | 0 |
| IOB0:DCI_MODE | [0, 41, 19] | [0, 40, 12] | [0, 40, 14] |
|---|---|---|---|
| IOB1:DCI_MODE | [1, 40, 44] | [1, 41, 51] | [1, 41, 49] |
| NONE | 0 | 0 | 0 |
| OUTPUT | 0 | 0 | 1 |
| OUTPUT_HALF | 0 | 1 | 0 |
| TERM_VCC | 0 | 1 | 1 |
| TERM_SPLIT | 1 | 0 | 0 |
| IOB0:DCI_MISC | [0, 41, 57] | [0, 40, 58] |
|---|---|---|
| IOB0:OUTPUT_ENABLE | [0, 41, 29] | [0, 40, 28] |
| IOB1:DCI_MISC | [1, 40, 6] | [1, 41, 5] |
| IOB1:OUTPUT_ENABLE | [1, 41, 35] | [1, 40, 34] |
| Non-inverted | [1] | [0] |
| IOB0:OMUX | [0, 40, 36] |
|---|---|
| O | 0 |
| OTHER_O_INV | 1 |
| IOB0:NSLEW | [0, 41, 43] | [0, 41, 17] | [0, 40, 32] | [0, 40, 30] | [0, 40, 44] |
|---|---|---|---|---|---|
| IOB0:PSLEW | [0, 40, 10] | [0, 40, 20] | [0, 41, 27] | [0, 41, 31] | [0, 41, 39] |
| IOB1:NSLEW | [1, 40, 20] | [1, 40, 46] | [1, 41, 31] | [1, 41, 33] | [1, 41, 19] |
| IOB1:PSLEW | [1, 41, 53] | [1, 41, 43] | [1, 40, 36] | [1, 40, 32] | [1, 40, 24] |
| Non-inverted | [4] | [3] | [2] | [1] | [0] |
| IOB0:PULL | [0, 40, 48] | [0, 41, 47] | [0, 40, 46] |
|---|---|---|---|
| IOB1:PULL | [1, 41, 15] | [1, 40, 16] | [1, 41, 17] |
| PULLDOWN | 0 | 0 | 0 |
| NONE | 0 | 0 | 1 |
| PULLUP | 0 | 1 | 1 |
| KEEPER | 1 | 0 | 1 |
| IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 40, 54] |
|---|---|
| IOB1:DCIUPDATEMODE_ASREQUIRED | [1, 41, 9] |
| Inverted | ~[0] |
| IOB0:PDRIVE | [0, 41, 7] | [0, 40, 26] | [0, 41, 41] | [0, 41, 45] | [0, 40, 52] | [0, 40, 56] |
|---|---|---|---|---|---|---|
| IOB1:PDRIVE | [1, 40, 56] | [1, 41, 37] | [1, 40, 22] | [1, 40, 18] | [1, 41, 11] | [1, 41, 7] |
| Mixed inversion | [5] | ~[4] | [3] | ~[2] | ~[1] | ~[0] |
| IOB0:DCI_T | [0, 40, 62] |
|---|---|
| IOB0:OUTPUT_DELAY | [0, 41, 51] |
| IOB0:PULL_DYNAMIC | [0, 41, 37] |
| IOB0:VR | [0, 41, 13] |
| IOB0:VREF_SYSMON | [0, 41, 3] |
| IOB1:DCI_T | [1, 41, 1] |
| IOB1:OUTPUT_DELAY | [1, 40, 12] |
| IOB1:PULL_DYNAMIC | [1, 40, 26] |
| IOB1:VR | [1, 40, 50] |
| IOB1:VREF_SYSMON | [1, 40, 60] |
| Non-inverted | [0] |
| IOB0:LVDS | [0, 41, 55] | [0, 40, 50] | [0, 40, 38] | [0, 41, 33] | [0, 41, 23] | [0, 40, 22] | [0, 40, 18] | [0, 40, 8] | [0, 41, 5] |
|---|---|---|---|---|---|---|---|---|---|
| IOB1:LVDS | [1, 40, 8] | [1, 41, 13] | [1, 41, 25] | [1, 40, 30] | [1, 40, 40] | [1, 41, 41] | [1, 41, 45] | [1, 41, 55] | [1, 40, 58] |
| Non-inverted | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| IOB0:OUTPUT_MISC | [0, 41, 9] | [0, 41, 25] | [0, 40, 24] | [0, 41, 35] |
|---|---|---|---|---|
| IOB1:OUTPUT_MISC | [1, 40, 54] | [1, 40, 38] | [1, 41, 39] | [1, 40, 28] |
| Non-inverted | [3] | [2] | [1] | [0] |
| IOB0:NDRIVE | [0, 40, 6] | [0, 41, 21] | [0, 40, 34] | [0, 40, 42] | [0, 41, 49] | [0, 41, 61] |
|---|---|---|---|---|---|---|
| IOB1:NDRIVE | [1, 41, 57] | [1, 40, 42] | [1, 41, 29] | [1, 41, 21] | [1, 40, 14] | [1, 40, 2] |
| Mixed inversion | [5] | [4] | ~[3] | ~[2] | ~[1] | ~[0] |
Bitstream — HCLK_IOI
| Name | IOSTD:LVDSBIAS | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] | |
| HT_25 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| LVDSEXT_25 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| LVDS_25 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RSDS_25 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| Name | IOSTD:DCI:PREF_OUTPUT | IOSTD:DCI:NREF_OUTPUT | ||
|---|---|---|---|---|
| [1] | [0] | [1] | [0] | |
| HSLVDCI_15 | 0 | 0 | 0 | 0 |
| HSLVDCI_18 | 0 | 0 | 0 | 0 |
| HSLVDCI_25 | 0 | 0 | 0 | 0 |
| LVDCI_15 | 0 | 0 | 0 | 0 |
| LVDCI_18 | 0 | 0 | 0 | 0 |
| LVDCI_25 | 0 | 0 | 0 | 0 |
| OFF | 0 | 0 | 0 | 0 |
| Name | IOSTD:DCI:PREF_OUTPUT_HALF | IOSTD:DCI:NREF_OUTPUT_HALF | ||||
|---|---|---|---|---|---|---|
| [2] | [1] | [0] | [2] | [1] | [0] | |
| LVDCI_DV2_15 | 0 | 1 | 1 | 0 | 1 | 1 |
| LVDCI_DV2_18 | 0 | 1 | 1 | 0 | 1 | 1 |
| LVDCI_DV2_25 | 0 | 1 | 1 | 0 | 1 | 1 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | IOSTD:DCI:PREF_TERM_VCC | IOSTD:DCI:PMASK_TERM_VCC | ||||||
|---|---|---|---|---|---|---|---|---|
| [1] | [0] | [5] | [4] | [3] | [2] | [1] | [0] | |
| HSTL_III_DCI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| HSTL_III_DCI_18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | IOSTD:DCI:PREF_TERM_SPLIT | IOSTD:DCI:NREF_TERM_SPLIT | IOSTD:DCI:PMASK_TERM_SPLIT | IOSTD:DCI:NMASK_TERM_SPLIT | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [2] | [1] | [0] | [2] | [1] | [0] | [5] | [4] | [3] | [2] | [1] | [0] | [5] | [4] | [3] | [2] | [1] | [0] | |
| HSTL_II_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| HSTL_II_DCI_18 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| HSTL_II_T_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| HSTL_II_T_DCI_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| HSTL_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| HSTL_I_DCI_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SSTL15_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SSTL15_T_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| SSTL18_II_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| SSTL18_II_T_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| SSTL18_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SSTL2_II_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| SSTL2_II_T_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| SSTL2_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| HCLK_IOI bittile 0 | ||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Row | Column | |||||||||||||||||||||||||||||||||||||||||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:PREF_TERM_VCC[0] | DCI:PREF_OUTPUT[0] | LVDS:LVDSBIAS[15] | DCI:PMASK_TERM_VCC[0] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:PREF_TERM_VCC[1] | DCI:PREF_OUTPUT[1] | LVDS:LVDSBIAS[14] | DCI:NMASK_TERM_SPLIT[0] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_OUTPUT[0] | DCI:PREF_OUTPUT_HALF[0] | LVDS:LVDSBIAS[13] | DCI:NMASK_TERM_SPLIT[1] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_OUTPUT[1] | DCI:PREF_OUTPUT_HALF[1] | LVDS:LVDSBIAS[12] | DCI:NMASK_TERM_SPLIT[2] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_OUTPUT_HALF[0] | DCI:PREF_OUTPUT_HALF[2] | LVDS:LVDSBIAS[11] | DCI:NMASK_TERM_SPLIT[3] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_OUTPUT_HALF[1] | DCI:PREF_TERM_SPLIT[0] | LVDS:LVDSBIAS[10] | DCI:NMASK_TERM_SPLIT[4] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_OUTPUT_HALF[2] | DCI:PREF_TERM_SPLIT[1] | LVDS:LVDSBIAS[9] | DCI:NMASK_TERM_SPLIT[5] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:PREF_TERM_SPLIT[2] | LVDS:LVDSBIAS[8] | DCI:PMASK_TERM_SPLIT[0] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | LVDS:LVDSBIAS[7] | DCI:PMASK_TERM_SPLIT[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_TERM_SPLIT[0] | DCI:TEST_ENABLE[1] | LVDS:LVDSBIAS[6] | DCI:PMASK_TERM_SPLIT[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_TERM_SPLIT[1] | INTERNAL_VREF:VREF[2] | LVDS:LVDSBIAS[5] | DCI:PMASK_TERM_SPLIT[3] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:NREF_TERM_SPLIT[2] | - | LVDS:LVDSBIAS[4] | DCI:PMASK_TERM_SPLIT[4] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | INTERNAL_VREF:VREF[0] | - | LVDS:LVDSBIAS[3] | DCI:PMASK_TERM_SPLIT[5] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:CASCADE_FROM_ABOVE | - | LVDS:LVDSBIAS[2] | DCI:PMASK_TERM_VCC[1] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:CASCADE_FROM_BELOW | LVDS:LVDSBIAS[16] | LVDS:LVDSBIAS[1] | DCI:PMASK_TERM_VCC[2] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | INTERNAL_VREF:VREF[4] | INTERNAL_VREF:VREF[3] | DCI:DYNAMIC_ENABLE | DCI:PMASK_TERM_VCC[3] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | INTERNAL_VREF:VREF[5] | INTERNAL_VREF:VREF[1] | LVDS:LVDSBIAS[0] | DCI:PMASK_TERM_VCC[4] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DCI:TEST_ENABLE[0] | DCI:QUIET | DCI:ENABLE | DCI:PMASK_TERM_VCC[5] |
| DCI:NREF_OUTPUT | [0, 40, 17] | [0, 40, 16] |
|---|---|---|
| DCI:PREF_OUTPUT | [0, 41, 15] | [0, 41, 14] |
| DCI:PREF_TERM_VCC | [0, 40, 15] | [0, 40, 14] |
| DCI:TEST_ENABLE | [0, 41, 23] | [0, 40, 31] |
| Non-inverted | [1] | [0] |
| DCI:NREF_OUTPUT_HALF | [0, 40, 20] | [0, 40, 19] | [0, 40, 18] |
|---|---|---|---|
| DCI:NREF_TERM_SPLIT | [0, 40, 25] | [0, 40, 24] | [0, 40, 23] |
| DCI:PREF_OUTPUT_HALF | [0, 41, 18] | [0, 41, 17] | [0, 41, 16] |
| DCI:PREF_TERM_SPLIT | [0, 41, 21] | [0, 41, 20] | [0, 41, 19] |
| Non-inverted | [2] | [1] | [0] |
| INTERNAL_VREF:VREF | [0, 40, 30] | [0, 40, 29] | [0, 41, 29] | [0, 41, 24] | [0, 41, 30] | [0, 40, 26] |
|---|---|---|---|---|---|---|
| OFF | 0 | 0 | 0 | 0 | 0 | 0 |
| 600 | 0 | 0 | 0 | 0 | 1 | 1 |
| 750 | 0 | 0 | 0 | 1 | 0 | 1 |
| 900 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1100 | 0 | 1 | 0 | 0 | 0 | 1 |
| 1250 | 1 | 0 | 0 | 0 | 0 | 1 |
| DCI:CASCADE_FROM_ABOVE | [0, 40, 27] |
|---|---|
| DCI:CASCADE_FROM_BELOW | [0, 40, 28] |
| DCI:DYNAMIC_ENABLE | [0, 42, 29] |
| DCI:ENABLE | [0, 42, 31] |
| DCI:QUIET | [0, 41, 31] |
| Non-inverted | [0] |
| LVDS:LVDSBIAS | [0, 41, 28] | [0, 42, 14] | [0, 42, 15] | [0, 42, 16] | [0, 42, 17] | [0, 42, 18] | [0, 42, 19] | [0, 42, 20] | [0, 42, 21] | [0, 42, 22] | [0, 42, 23] | [0, 42, 24] | [0, 42, 25] | [0, 42, 26] | [0, 42, 27] | [0, 42, 28] | [0, 42, 30] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Non-inverted | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| DCI:NMASK_TERM_SPLIT | [0, 43, 20] | [0, 43, 19] | [0, 43, 18] | [0, 43, 17] | [0, 43, 16] | [0, 43, 15] |
|---|---|---|---|---|---|---|
| DCI:PMASK_TERM_SPLIT | [0, 43, 26] | [0, 43, 25] | [0, 43, 24] | [0, 43, 23] | [0, 43, 22] | [0, 43, 21] |
| DCI:PMASK_TERM_VCC | [0, 43, 31] | [0, 43, 30] | [0, 43, 29] | [0, 43, 28] | [0, 43, 27] | [0, 43, 14] |
| Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |