Splitters

LLH.CLB

LLH.CLB bittile 0
RowColumn
0
0 -
1 -
2 -
3 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
4 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
5 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
LLH.CLB bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
7 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
8 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
INT:BIPASS.0.LONG.H0.1.LONG.H0[1, 0, 8]
INT:BIPASS.0.LONG.H1.1.LONG.H1[1, 0, 7]
INT:BIPASS.0.LONG.H2.1.LONG.H2[1, 0, 6]
INT:BIPASS.0.LONG.H3.1.LONG.H3[0, 0, 4]
INT:BIPASS.0.LONG.H4.1.LONG.H4[0, 0, 5]
INT:BIPASS.0.LONG.H5.1.LONG.H5[0, 0, 3]
Inverted~[0]

LLH.CLB.B

LLH.CLB.B bittile 0
RowColumn
0
0 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
1 -
2 -
3 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
4 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
5 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
LLH.CLB.B bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8 -
9 -
10 -
11 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
12 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
INT:BIPASS.0.LONG.H0.1.LONG.H0[1, 0, 11]
INT:BIPASS.0.LONG.H1.1.LONG.H1[1, 0, 12]
INT:BIPASS.0.LONG.H2.1.LONG.H2[0, 0, 0]
INT:BIPASS.0.LONG.H3.1.LONG.H3[0, 0, 4]
INT:BIPASS.0.LONG.H4.1.LONG.H4[0, 0, 5]
INT:BIPASS.0.LONG.H5.1.LONG.H5[0, 0, 3]
Inverted~[0]

LLH.IO.B

LLH.IO.B bittile 0
RowColumn
0
0 ~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
1 ~INT:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2
2 ~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
3 ~INT:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3
4 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
5 ~INT:BIPASS.0.DEC.H2.1.DEC.H2
6 ~INT:BIPASS.0.DEC.H1.1.DEC.H1
7 ~INT:BIPASS.0.DEC.H3.1.DEC.H3
8 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
9 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
10 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
INT:BIPASS.0.DEC.H0.1.DEC.H0[0, 0, 4]
INT:BIPASS.0.DEC.H1.1.DEC.H1[0, 0, 6]
INT:BIPASS.0.DEC.H2.1.DEC.H2[0, 0, 5]
INT:BIPASS.0.DEC.H3.1.DEC.H3[0, 0, 7]
INT:BIPASS.0.LONG.H3.1.LONG.H3[0, 0, 10]
INT:BIPASS.0.LONG.H4.1.LONG.H4[0, 0, 9]
INT:BIPASS.0.LONG.H5.1.LONG.H5[0, 0, 8]
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0[0, 0, 2]
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1[0, 0, 0]
INT:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2[0, 0, 1]
INT:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3[0, 0, 3]
Inverted~[0]

LLH.IO.T

LLH.IO.T bittile 0
RowColumn
0
0 ~INT:BIPASS.0.DEC.H2.1.DEC.H2
1 ~INT:BIPASS.0.DEC.H1.1.DEC.H1
2 ~INT:BIPASS.0.DEC.H3.1.DEC.H3
3 ~INT:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3
4 ~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
5 ~INT:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2
6 ~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
LLH.IO.T bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
7 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
8 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
9 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
INT:BIPASS.0.DEC.H0.1.DEC.H0[1, 0, 9]
INT:BIPASS.0.DEC.H1.1.DEC.H1[0, 0, 1]
INT:BIPASS.0.DEC.H2.1.DEC.H2[0, 0, 0]
INT:BIPASS.0.DEC.H3.1.DEC.H3[0, 0, 2]
INT:BIPASS.0.LONG.H0.1.LONG.H0[1, 0, 8]
INT:BIPASS.0.LONG.H1.1.LONG.H1[1, 0, 7]
INT:BIPASS.0.LONG.H2.1.LONG.H2[1, 0, 6]
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0[0, 0, 4]
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1[0, 0, 6]
INT:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2[0, 0, 5]
INT:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3[0, 0, 3]
Inverted~[0]

LLV.CLB

LLV.CLB bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930
0 ----CLKH:MUX.O1[3]CLKH:MUX.O1[1]CLKH:MUX.O1[0]CLKH:MUX.O1[2]CLKH:MUX.O1[4]CLKH:MUX.O3[4]CLKH:MUX.O3[2]CLKH:MUX.O3[0]-CLKH:MUX.O3[1]CLKH:MUX.O3[3]CLKH:MUX.O0[3]CLKH:MUX.O0[1]CLKH:MUX.O0[0]CLKH:MUX.O0[2]CLKH:MUX.O0[4]~INT:BIPASS.0.LONG.V4.1.LONG.V4~INT:BIPASS.0.LONG.V0.1.LONG.V0~INT:BIPASS.0.LONG.V3.1.LONG.V3CLKH:MUX.O2[3]CLKH:MUX.O2[1]CLKH:MUX.O2[0]CLKH:MUX.O2[2]CLKH:MUX.O2[4]~INT:BIPASS.0.LONG.V2.1.LONG.V2~INT:BIPASS.0.LONG.V1.1.LONG.V1~INT:BIPASS.0.LONG.V5.1.LONG.V5
CLKH:MUX.O1[0, 8, 0][0, 4, 0][0, 7, 0][0, 5, 0][0, 6, 0]
I.LL.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O3[0, 9, 0][0, 14, 0][0, 10, 0][0, 13, 0][0, 11, 0]
I.UR.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O0[0, 19, 0][0, 15, 0][0, 18, 0][0, 16, 0][0, 17, 0]
I.UL.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
INT:BIPASS.0.LONG.V0.1.LONG.V0[0, 21, 0]
INT:BIPASS.0.LONG.V1.1.LONG.V1[0, 29, 0]
INT:BIPASS.0.LONG.V2.1.LONG.V2[0, 28, 0]
INT:BIPASS.0.LONG.V3.1.LONG.V3[0, 22, 0]
INT:BIPASS.0.LONG.V4.1.LONG.V4[0, 20, 0]
INT:BIPASS.0.LONG.V5.1.LONG.V5[0, 30, 0]
Inverted~[0]
CLKH:MUX.O2[0, 27, 0][0, 23, 0][0, 26, 0][0, 24, 0][0, 25, 0]
I.LR.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111

LLV.IO.L

LLV.IO.L bittile 0
RowColumn
012345678910111213141516171819202122232425
0 CLKH:MUX.O2[4]-~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0~INT:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3~INT:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2-CLKH:MUX.O0[3]~INT:BIPASS.0.DEC.V0.1.DEC.V0CLKH:MUX.O0[1]CLKH:MUX.O0[0]CLKH:MUX.O0[2]CLKH:MUX.O0[4]~INT:BIPASS.0.DEC.V1.1.DEC.V1~INT:BIPASS.0.DEC.V2.1.DEC.V2~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1CLKH:MUX.O1[3]CLKH:MUX.O1[1]CLKH:MUX.O1[0]CLKH:MUX.O1[2]CLKH:MUX.O1[4]~INT:BIPASS.0.DEC.V3.1.DEC.V3CLKH:MUX.O3[3]CLKH:MUX.O3[1]CLKH:MUX.O3[0]CLKH:MUX.O3[2]CLKH:MUX.O3[4]
LLV.IO.L bittile 1
RowColumn
012345678910111213141516171819202122232425262728293031323334
0 -------------------------------CLKH:MUX.O2[3]CLKH:MUX.O2[1]CLKH:MUX.O2[0]CLKH:MUX.O2[2]
INT:BIPASS.0.DEC.V0.1.DEC.V0[0, 7, 0]
INT:BIPASS.0.DEC.V1.1.DEC.V1[0, 12, 0]
INT:BIPASS.0.DEC.V2.1.DEC.V2[0, 13, 0]
INT:BIPASS.0.DEC.V3.1.DEC.V3[0, 20, 0]
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0[0, 2, 0]
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1[0, 14, 0]
INT:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2[0, 4, 0]
INT:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3[0, 3, 0]
Inverted~[0]
CLKH:MUX.O0[0, 11, 0][0, 6, 0][0, 10, 0][0, 8, 0][0, 9, 0]
I.UL.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O1[0, 19, 0][0, 15, 0][0, 18, 0][0, 16, 0][0, 17, 0]
I.LL.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O3[0, 25, 0][0, 21, 0][0, 24, 0][0, 22, 0][0, 23, 0]
I.UR.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O2[0, 0, 0][1, 31, 0][1, 34, 0][1, 32, 0][1, 33, 0]
I.LR.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111

LLV.IO.R

LLV.IO.R bittile 0
RowColumn
01234567891011121314151617181920212223242526272829303132333435
0 CLKH:MUX.O3[4]CLKH:MUX.O3[2]CLKH:MUX.O3[0]CLKH:MUX.O3[1]CLKH:MUX.O3[3]~INT:BIPASS.0.DEC.V0.1.DEC.V0CLKH:MUX.O1[4]CLKH:MUX.O1[2]CLKH:MUX.O1[0]CLKH:MUX.O1[1]CLKH:MUX.O1[3]~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1~INT:BIPASS.0.DEC.V1.1.DEC.V1~INT:BIPASS.0.DEC.V2.1.DEC.V2CLKH:MUX.O0[4]CLKH:MUX.O0[2]CLKH:MUX.O0[0]CLKH:MUX.O0[1]~INT:BIPASS.0.DEC.V3.1.DEC.V3CLKH:MUX.O0[3]-~INT:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2~INT:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0~INT:BIPASS.0.LONG.V4.1.LONG.V4~MISC:TLC~INT:BIPASS.0.LONG.V0.1.LONG.V0~INT:BIPASS.0.LONG.V3.1.LONG.V3CLKH:MUX.O2[3]CLKH:MUX.O2[1]CLKH:MUX.O2[0]CLKH:MUX.O2[2]CLKH:MUX.O2[4]~INT:BIPASS.0.LONG.V2.1.LONG.V2~INT:BIPASS.0.LONG.V1.1.LONG.V1~INT:BIPASS.0.LONG.V5.1.LONG.V5
CLKH:MUX.O3[0, 0, 0][0, 4, 0][0, 1, 0][0, 3, 0][0, 2, 0]
I.UR.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
INT:BIPASS.0.DEC.V0.1.DEC.V0[0, 5, 0]
INT:BIPASS.0.DEC.V1.1.DEC.V1[0, 12, 0]
INT:BIPASS.0.DEC.V2.1.DEC.V2[0, 13, 0]
INT:BIPASS.0.DEC.V3.1.DEC.V3[0, 18, 0]
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0[0, 23, 0]
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1[0, 11, 0]
INT:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2[0, 21, 0]
INT:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3[0, 22, 0]
INT:BIPASS.0.LONG.V0.1.LONG.V0[0, 26, 0]
INT:BIPASS.0.LONG.V1.1.LONG.V1[0, 34, 0]
INT:BIPASS.0.LONG.V2.1.LONG.V2[0, 33, 0]
INT:BIPASS.0.LONG.V3.1.LONG.V3[0, 27, 0]
INT:BIPASS.0.LONG.V4.1.LONG.V4[0, 24, 0]
INT:BIPASS.0.LONG.V5.1.LONG.V5[0, 35, 0]
MISC:TLC[0, 25, 0]
Inverted~[0]
CLKH:MUX.O1[0, 6, 0][0, 10, 0][0, 7, 0][0, 9, 0][0, 8, 0]
I.LL.H01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O0[0, 14, 0][0, 19, 0][0, 15, 0][0, 17, 0][0, 16, 0]
I.UL.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111
CLKH:MUX.O2[0, 32, 0][0, 28, 0][0, 31, 0][0, 29, 0][0, 30, 0]
I.LR.V01111
I.LL.V10111
I.UL.H11011
I.LR.H11101
I.UR.V11110
NONE11111