Corners

CNR.BL

CNR.BL bittile 0
RowColumn
01234567891011121314151617181920212223242526
0 ---------------------------
1 ---------------------------
2 -INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[5]MD2:PULL[0]MD2:PULL[1]~BUFG.H:ALT_PAD~BUFG.H:CLK_EN~BUFG.V:ALT_PAD------------------
3 -INT:MUX.IMUX.BUFG.H[4]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[6]INT:MUX.IMUX.BUFG.H[0]INT:MUX.IMUX.IOB1.O1[4]MISC:5V_TOLERANT_IOINT:MUX.IMUX.BUFG.V[4]~BUFG.V:CLK_EN------------------
4 -~PULLUP.DEC.H0:ENABLE~PULLUP.DEC.H1:ENABLE~PULLUP.DEC.H2:ENABLE~PULLUP.DEC.H3:ENABLEINT:MUX.IMUX.IOB1.O1[2]INT:MUX.IMUX.RDBK.TRIG[3]INT:MUX.IMUX.RDBK.TRIG[2]~MISC:TM_BOTINT:MUX.IMUX.BUFG.V[3]INT:MUX.LONG.IO.H2[0]INT:MUX.LONG.IO.H2[1]INT:MUX.IMUX.BUFG.V[1]INT:MUX.LONG.IO.H0[1]~MISC:READ_CAPTUREINT:MUX.LONG.IO.H0[0]~MISC:READ_ABORTINT:MUX.LONG.IO.H3[0]INT:MUX.LONG.IO.H3[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.IO.H1[1]INT:MUX.IMUX.BUFG.V[5]INT:MUX.LONG.IO.H1[0]INT:MUX.IMUX.BUFG.V[0]MD0:PULL[0]MD0:PULL[1]-
5 -INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]INT:MUX.IMUX.IOB1.O1[5]INT:MUX.IMUX.IOB1.O1[3]INT:MUX.IMUX.IOB1.O1[1]INT:MUX.IMUX.IOB1.O1[0]INT:MUX.LONG.IO.V3[3]INT:MUX.LONG.IO.V3[1]INT:MUX.LONG.IO.V3[2]INT:MUX.LONG.IO.V3[0]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V1[4]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.IMUX.RDBK.TRIG[1]INT:MUX.IMUX.RDBK.TRIG[0]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[3]~RDBK:ENABLE--
6 --INT:MUX.IMUX.IOB1.IK[3]INT:MUX.IMUX.IOB1.IK[2]INT:MUX.IMUX.IOB1.IK[0]INT:MUX.LONG.IO.V2[4]INT:MUX.LONG.IO.V3[4]--------------------
7 -INT:MUX.IMUX.IOB1.IK[4]INT:MUX.IMUX.IOB1.IK[1]INT:MUX.IMUX.IOB1.IK[5]------INT:MUX.IO.DBUF.V0[3]INT:MUX.IO.DBUF.V0[2]INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]-------------
8 -~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H1.0.LONG.IO.V0~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H5.0.LONG.IO.V2-~INT:PASS.SINGLE.H0.0.DEC.V3~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2~INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1------------
9 -~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0~INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1~INT:PASS.SINGLE.H4.0.DEC.V1-----------
10 -INT:MUX.LONG.H4[2]INT:MUX.LONG.H4[3]~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA~INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1-INT:MUX.LONG.H5[2]~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0-~INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0-~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1--INT:MUX.LONG.H3[1]------------
11 --INT:MUX.LONG.H4[0]~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.SINT:MUX.LONG.H4[1]~INT:PASS.SINGLE.H2.0.OUT.MD0.I-INT:MUX.LONG.H5[1]-~INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0INT:MUX.LONG.H5[0]INT:MUX.LONG.H5[3]----INT:MUX.IO.DBUF.V1[3]--INT:MUX.LONG.H3[0]----~MD1:ENABLE.O~MD1:ENABLE.T-
12 -~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S~INT:PASS.SINGLE.H6.0.OUT.MD0.I-~INT:PASS.SINGLE.H6.0.LONG.IO.V3~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I----~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S----INT:MUX.IO.DBUF.V1[0]INT:MUX.IO.DBUF.V1[1]INT:MUX.IO.DBUF.V1[2]~INT:PASS.SINGLE.H2.0.LONG.IO.V1-~PULLUP.DEC.V2:ENABLE~PULLUP.DEC.V0:ENABLE~PULLUP.DEC.V1:ENABLE~PULLUP.DEC.V3:ENABLEMD1:PULL[0]MD1:PULL[1]
13 -~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2~INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0-~INT:PASS.SINGLE.H7.0.DEC.V0~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0~INT:PASS.SINGLE.H3.0.DEC.V2---------
14 -~INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S~INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S~INT:BIPASS.IO.DOUBLE.3.W.1.QUAD.H2.0-~INT:BIPASS.QUAD.H0.3.LONG.IO.V3--~INT:BIPASS.IO.DOUBLE.1.W.2.QUAD.H0.0~INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S~INT:BIPASS.QUAD.H2.3.LONG.IO.V1~INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S-INT:MUX.ECLK.V[2]INT:MUX.IMUX.CLB.G2[0]INT:MUX.ECLK.V[6]INT:MUX.IMUX.CLB.F2[1]INT:MUX.IMUX.CLB.C2[3]INT:MUX.IMUX.CLB.C2[4]INT:MUX.IMUX.CLB.C2[1]INT:MUX.ECLK.V[5]INT:MUX.ECLK.V[4]INT:MUX.ECLK.V[3]-INT:MUX.ECLK.V[1]INT:MUX.ECLK.V[0]-
15 --~INT:BIPASS.QUAD.H1.3.LONG.IO.V2~INT:BIPASS.IO.DOUBLE.0.W.1.QUAD.H0.1~INT:BIPASS.IO.DOUBLE.3.W.2.QUAD.H2.1~INT:BIPASS.IO.DOUBLE.2.W.2.QUAD.H1.1~INT:PASS.QUAD.H1.2.0.DEC.V1~INT:BIPASS.IO.DOUBLE.1.W.1.QUAD.H1.2~INT:PASS.QUAD.H0.2.0.DEC.V0~INT:BIPASS.IO.DOUBLE.0.W.2.QUAD.H0.2~INT:PASS.QUAD.H2.2.0.DEC.V2~INT:BIPASS.IO.DOUBLE.2.W.1.QUAD.H2.2--INT:MUX.IMUX.CLB.G2[1]-INT:MUX.IMUX.CLB.F2[0]INT:MUX.IMUX.CLB.C2[0]INT:MUX.IMUX.CLB.C2[2]--------
BUFG.H:ALT_PAD[0, 6, 2]
BUFG.H:CLK_EN[0, 7, 2]
BUFG.V:ALT_PAD[0, 8, 2]
BUFG.V:CLK_EN[0, 8, 3]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0[0, 9, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1[0, 6, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2[0, 3, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0[0, 15, 13]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1[0, 13, 13]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2[0, 11, 13]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0[0, 6, 13]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1[0, 4, 13]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2[0, 2, 13]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0[0, 12, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1[0, 13, 8]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2[0, 11, 8]
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2[0, 4, 9]
INT:BIPASS.IO.DOUBLE.0.W.1.QUAD.H0.1[0, 3, 15]
INT:BIPASS.IO.DOUBLE.0.W.2.QUAD.H0.2[0, 9, 15]
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2[0, 12, 13]
INT:BIPASS.IO.DOUBLE.1.W.1.QUAD.H1.2[0, 7, 15]
INT:BIPASS.IO.DOUBLE.1.W.2.QUAD.H0.0[0, 8, 14]
INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2[0, 12, 8]
INT:BIPASS.IO.DOUBLE.2.W.1.QUAD.H2.2[0, 11, 15]
INT:BIPASS.IO.DOUBLE.2.W.2.QUAD.H1.1[0, 5, 15]
INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2[0, 3, 13]
INT:BIPASS.IO.DOUBLE.3.W.1.QUAD.H2.0[0, 3, 14]
INT:BIPASS.IO.DOUBLE.3.W.2.QUAD.H2.1[0, 4, 15]
INT:BIPASS.QUAD.H0.3.LONG.IO.V3[0, 5, 14]
INT:BIPASS.QUAD.H1.3.LONG.IO.V2[0, 2, 15]
INT:BIPASS.QUAD.H2.3.LONG.IO.V1[0, 10, 14]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0[0, 10, 9]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2[0, 1, 9]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1[0, 7, 9]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0[0, 16, 13]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2[0, 10, 13]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1[0, 14, 13]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0[0, 13, 9]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2[0, 10, 8]
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1[0, 14, 8]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0[0, 7, 13]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2[0, 1, 13]
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1[0, 5, 13]
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S[0, 3, 11]
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I[0, 5, 12]
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA[0, 3, 10]
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S[0, 3, 8]
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1[0, 11, 9]
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0[0, 7, 10]
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1[0, 11, 10]
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0[0, 10, 12]
INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1[0, 14, 9]
INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0[0, 9, 10]
INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1[0, 4, 10]
INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0[0, 9, 11]
INT:PASS.QUAD.H0.2.0.DEC.V0[0, 8, 15]
INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S[0, 1, 14]
INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S[0, 11, 14]
INT:PASS.QUAD.H1.2.0.DEC.V1[0, 6, 15]
INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S[0, 2, 14]
INT:PASS.QUAD.H2.2.0.DEC.V2[0, 10, 15]
INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S[0, 9, 14]
INT:PASS.SINGLE.H0.0.DEC.V3[0, 9, 8]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 2, 8]
INT:PASS.SINGLE.H1.0.LONG.IO.V0[0, 4, 8]
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA[0, 5, 8]
INT:PASS.SINGLE.H2.0.LONG.IO.V1[0, 19, 12]
INT:PASS.SINGLE.H2.0.OUT.MD0.I[0, 5, 11]
INT:PASS.SINGLE.H3.0.DEC.V2[0, 17, 13]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 11, 12]
INT:PASS.SINGLE.H4.0.DEC.V1[0, 15, 9]
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S[0, 1, 8]
INT:PASS.SINGLE.H5.0.LONG.IO.V2[0, 7, 8]
INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA[0, 6, 8]
INT:PASS.SINGLE.H6.0.LONG.IO.V3[0, 4, 12]
INT:PASS.SINGLE.H6.0.OUT.MD0.I[0, 2, 12]
INT:PASS.SINGLE.H7.0.DEC.V0[0, 9, 13]
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S[0, 1, 12]
MD1:ENABLE.O[0, 24, 11]
MD1:ENABLE.T[0, 25, 11]
MISC:READ_ABORT[0, 16, 4]
MISC:READ_CAPTURE[0, 14, 4]
MISC:TM_BOT[0, 8, 4]
PULLUP.DEC.H0:ENABLE[0, 1, 4]
PULLUP.DEC.H1:ENABLE[0, 2, 4]
PULLUP.DEC.H2:ENABLE[0, 3, 4]
PULLUP.DEC.H3:ENABLE[0, 4, 4]
PULLUP.DEC.V0:ENABLE[0, 22, 12]
PULLUP.DEC.V1:ENABLE[0, 23, 12]
PULLUP.DEC.V2:ENABLE[0, 21, 12]
PULLUP.DEC.V3:ENABLE[0, 24, 12]
RDBK:ENABLE[0, 24, 5]
Inverted~[0]
INT:MUX.LONG.H4[0, 2, 10][0, 1, 10][0, 4, 11][0, 2, 11]
0.LONG.IO.V20001
0.DEC.V20010
0.OUT.RDBK.DATA0111
NONE1111
MD0:PULL[0, 25, 4][0, 24, 4]
MD1:PULL[0, 26, 12][0, 25, 12]
MD2:PULL[0, 5, 2][0, 4, 2]
PULLUP01
PULLDOWN10
PULLNONE11
INT:MUX.IMUX.BUFG.H[0, 3, 3][0, 3, 2][0, 1, 3][0, 2, 3][0, 2, 2][0, 1, 2][0, 4, 3]
0.IO.DOUBLE.0.S.00000111
0.IO.DOUBLE.1.S.00001011
0.IO.DOUBLE.2.S.00001101
0.IO.DOUBLE.0.W.10011111
0.IO.DOUBLE.2.W.10100111
0.IO.DOUBLE.3.S.00101011
0.IO.DOUBLE.3.W.10101101
0.IO.DOUBLE.1.W.10111111
0.OUT.IOB.CLKIN.W1101110
NONE1101111
INT:MUX.LONG.IO.V2[0, 5, 6][0, 1, 5][0, 3, 5][0, 2, 5][0, 4, 5]
0.LONG.H400011
0.LONG.IO.H000101
0.LONG.IO.H200110
0.SINGLE.H501111
NONE11111
INT:MUX.IMUX.IOB1.IK[0, 3, 7][0, 1, 7][0, 2, 6][0, 3, 6][0, 2, 7][0, 4, 6]
0.LONG.H3000111
0.LONG.H4001011
0.LONG.H5001101
0.DOUBLE.H0.0011111
1.SINGLE.V2100111
1.SINGLE.V3101011
1.SINGLE.V4101101
1.SINGLE.V5101110
0.DOUBLE.H1.1111111
MISC:5V_TOLERANT_IO[0, 6, 3]
Non-inverted[0]
INT:MUX.IMUX.IOB1.O1[0, 5, 5][0, 5, 3][0, 6, 5][0, 5, 4][0, 7, 5][0, 8, 5]
1.LONG.V0001110
0.SINGLE.H2001111
1.LONG.V1010110
0.SINGLE.H3010111
1.LONG.V2011010
0.SINGLE.H4011011
0.SINGLE.H5011101
1.DOUBLE.V1.0111110
1.DOUBLE.V0.1111111
INT:MUX.LONG.IO.H2[0, 11, 4][0, 10, 4]
0.LONG.IO.V000
0.LONG.IO.V201
NONE11
INT:MUX.LONG.H5[0, 11, 11][0, 6, 10][0, 7, 11][0, 10, 11]
0.LONG.IO.V30001
0.DEC.V30010
0.OUT.RDBK.DATA0111
NONE1111
INT:MUX.LONG.IO.V3[0, 6, 6][0, 9, 5][0, 11, 5][0, 10, 5][0, 12, 5]
0.LONG.H500011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H601111
NONE11111
INT:MUX.IO.DBUF.V0[0, 10, 7][0, 11, 7][0, 13, 7][0, 12, 7]
0.IO.DOUBLE.1.S.00011
0.IO.DOUBLE.2.S.00101
0.IO.DOUBLE.3.S.00110
0.IO.DOUBLE.0.S.01111
INT:MUX.IMUX.CLB.G2[0, 14, 15][0, 14, 14]
1.LONG.V600
1.LONG.V801
1.GCLK710
1.LONG.V911
INT:MUX.LONG.IO.H0[0, 13, 4][0, 15, 4]
0.LONG.IO.V200
0.LONG.IO.V001
NONE11
INT:MUX.IO.DBUF.V1[0, 16, 11][0, 18, 12][0, 17, 12][0, 16, 12]
0.IO.DOUBLE.0.W.20011
0.IO.DOUBLE.1.W.20101
0.IO.DOUBLE.3.W.20110
0.IO.DOUBLE.2.W.21111
INT:MUX.IMUX.CLB.F2[0, 16, 14][0, 16, 15]
1.LONG.V700
1.LONG.V801
1.LONG.V910
1.GCLK711
INT:MUX.LONG.IO.H3[0, 18, 4][0, 17, 4]
0.LONG.IO.V100
0.LONG.IO.V301
NONE11
INT:MUX.LONG.IO.V1[0, 14, 5][0, 13, 5][0, 16, 5][0, 15, 5][0, 17, 5]
0.LONG.H300011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H201111
NONE11111
INT:MUX.IMUX.CLB.C2[0, 18, 14][0, 17, 14][0, 18, 15][0, 19, 14][0, 17, 15]
1.LONG.V101111
1.LONG.V510111
1.LONG.V711011
1.LONG.V811101
1.GCLK611110
NONE11111
INT:MUX.IMUX.RDBK.TRIG[0, 6, 4][0, 7, 4][0, 18, 5][0, 19, 5]
0.SINGLE.H30011
0.SINGLE.H40101
0.SINGLE.H50110
0.SINGLE.H21111
INT:MUX.LONG.H3[0, 14, 10][0, 19, 11]
0.DEC.V100
0.LONG.IO.V101
NONE11
INT:MUX.LONG.IO.V0[0, 23, 5][0, 20, 5][0, 22, 5][0, 21, 5]
0.LONG.IO.H00001
0.LONG.IO.H20010
0.SINGLE.H10111
NONE1111
INT:MUX.LONG.IO.H1[0, 20, 4][0, 22, 4]
0.LONG.IO.V300
0.LONG.IO.V101
NONE11
INT:MUX.IMUX.BUFG.V[0, 21, 4][0, 7, 3][0, 9, 4][0, 19, 4][0, 12, 4][0, 23, 4]
0.IO.OCTAL.S.0000111
0.LONG.IO.H0001011
0.LONG.IO.V0001101
0.IO.OCTAL.S.7011111
0.OUT.IOB.CLKIN.S101110
NONE101111
INT:MUX.ECLK.V[0, 15, 14][0, 20, 14][0, 21, 14][0, 22, 14][0, 13, 14][0, 24, 14][0, 25, 14]
0.LONG.IO.H00011001
0.SINGLE.H20011111
0.LONG.IO.H10101001
0.SINGLE.H30101111
0.LONG.IO.H30110001
0.SINGLE.H40110111
0.OUT.BUFGE.H0111010
0.IO.DOUBLE.3.W.21111001
0.SINGLE.H51111111

CNR.TL

CNR.TL bittile 0
RowColumn
012345678910111213141516171819202122232425
0 --------------------------
1 --------------------------
2 -INT:MUX.IMUX.BSCAN.TDO2[5]INT:MUX.IMUX.BSCAN.TDO2[1]INT:MUX.IMUX.BSCAN.TDO2[2]-----~PULLUP.DEC.V0:ENABLE~PULLUP.DEC.V2:ENABLE~PULLUP.DEC.V1:ENABLE----~PULLUP.DEC.V3:ENABLE~BUFG.V:CLK_EN-INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[5]--
3 -INT:MUX.IMUX.BSCAN.TDO2[0]INT:MUX.IMUX.BSCAN.TDO2[3]INT:MUX.IMUX.BSCAN.TDO2[4]INT:MUX.LONG.IO.H0[0]-INT:MUX.LONG.IO.H2[0]INT:MUX.LONG.IO.H2[1]--INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V2[3]-INT:MUX.LONG.H2[0]INT:MUX.LONG.H2[1]INT:MUX.IMUX.BUFG.V[0]-----
4 -INT:MUX.LONG.IO.H0[1]INT:MUX.IMUX.BSCAN.TDO1[2]INT:MUX.IMUX.BSCAN.TDO1[3]INT:MUX.IMUX.BSCAN.TDO1[0]~PULLUP.DEC.H2:ENABLE~PULLUP.DEC.H3:ENABLEINT:MUX.LONG.IO.V0[2]----INT:MUX.LONG.H0[3]INT:MUX.LONG.H0[2]INT:MUX.LONG.H0[1]INT:MUX.LONG.H0[0]INT:MUX.LONG.H1[2]INT:MUX.LONG.H1[0]INT:MUX.LONG.H1[1]INT:MUX.LONG.H1[3]MISC:OUTPUT-----
5 -INT:MUX.IMUX.BSCAN.TDO1[4]INT:MUX.IMUX.BSCAN.TDO1[5]INT:MUX.IMUX.BSCAN.TDO1[1]INT:MUX.LONG.IO.H3[0]~PULLUP.DEC.H1:ENABLEINT:MUX.LONG.IO.H1[0]~PULLUP.DEC.H0:ENABLEINT:MUX.LONG.IO.V1[3]-INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[0]~MISC:TM_LEFTINT:MUX.LONG.IO.V3[0]INT:MUX.LONG.IO.V3[1]BSCAN:ENABLE-~BUFG.V:ALT_PAD-------
6 -INT:MUX.LONG.IO.H3[1]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[6]INT:MUX.IMUX.BUFG.H[0]INT:MUX.LONG.IO.H1[1]~MISC:TM_TOP------------------
7 -INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[5]-----------------------
8 -INT:MUX.IMUX.BUFG.H[4]MISC:INPUT~MISC:3V~BUFG.H:CLK_EN~BUFG.H:ALT_PAD-------------------BSCAN:CONFIG
INT:MUX.IMUX.BSCAN.TDO2[0, 1, 2][0, 3, 3][0, 2, 3][0, 3, 2][0, 2, 2][0, 1, 3]
0.LONG.H0000111
0.LONG.H1001011
0.LONG.H2001101
1.SINGLE.V2010111
1.SINGLE.V3011011
1.SINGLE.V4011101
1.SINGLE.V5011110
2.DOUBLE.H1.0101111
2.DOUBLE.H0.1111111
MISC:INPUT[0, 2, 8]
MISC:OUTPUT[0, 20, 4]
CMOS0
TTL1
BUFG.H:ALT_PAD[0, 5, 8]
BUFG.H:CLK_EN[0, 4, 8]
BUFG.V:ALT_PAD[0, 18, 5]
BUFG.V:CLK_EN[0, 17, 2]
MISC:3V[0, 3, 8]
MISC:TM_LEFT[0, 13, 5]
MISC:TM_TOP[0, 7, 6]
PULLUP.DEC.H0:ENABLE[0, 7, 5]
PULLUP.DEC.H1:ENABLE[0, 5, 5]
PULLUP.DEC.H2:ENABLE[0, 5, 4]
PULLUP.DEC.H3:ENABLE[0, 6, 4]
PULLUP.DEC.V0:ENABLE[0, 9, 2]
PULLUP.DEC.V1:ENABLE[0, 11, 2]
PULLUP.DEC.V2:ENABLE[0, 10, 2]
PULLUP.DEC.V3:ENABLE[0, 16, 2]
Inverted~[0]
INT:MUX.LONG.IO.H0[0, 1, 4][0, 4, 3]
0.LONG.IO.V200
0.LONG.IO.V001
NONE11
INT:MUX.IMUX.BSCAN.TDO1[0, 2, 5][0, 1, 5][0, 3, 4][0, 2, 4][0, 3, 5][0, 4, 4]
1.LONG.V0000111
1.LONG.V1001011
1.LONG.V2001101
1.DOUBLE.V1.0011111
2.SINGLE.H2100111
2.SINGLE.H3101011
2.SINGLE.H4101101
2.SINGLE.H5101110
1.DOUBLE.V0.1111111
INT:MUX.LONG.IO.H3[0, 1, 6][0, 4, 5]
0.LONG.IO.V100
0.LONG.IO.V301
NONE11
INT:MUX.IMUX.BUFG.H[0, 4, 6][0, 2, 7][0, 1, 8][0, 2, 6][0, 3, 6][0, 1, 7][0, 5, 6]
0.IO.DOUBLE.0.N.10000111
0.IO.DOUBLE.1.N.10001011
0.IO.DOUBLE.2.N.10001101
0.IO.DOUBLE.0.N.20011111
0.IO.DOUBLE.2.N.20100111
0.IO.DOUBLE.3.N.10101011
0.IO.DOUBLE.3.N.20101101
0.IO.DOUBLE.1.N.20111111
0.OUT.IOB.CLKIN.W1101110
NONE1101111
INT:MUX.LONG.IO.H2[0, 7, 3][0, 6, 3]
0.LONG.IO.V000
0.LONG.IO.V201
NONE11
INT:MUX.LONG.IO.H1[0, 6, 6][0, 6, 5]
0.LONG.IO.V300
0.LONG.IO.V101
NONE11
INT:MUX.LONG.IO.V0[0, 10, 3][0, 7, 4][0, 11, 3][0, 12, 3]
0.LONG.H00001
0.LONG.IO.H20010
0.LONG.IO.H00111
NONE1111
INT:MUX.LONG.IO.V1[0, 8, 5][0, 10, 5][0, 11, 5][0, 12, 5]
0.LONG.H10001
0.LONG.IO.H30010
0.LONG.IO.H10111
NONE1111
INT:MUX.LONG.IO.V2[0, 16, 3][0, 13, 3][0, 15, 3][0, 14, 3]
0.LONG.H20001
0.LONG.IO.H00010
0.LONG.IO.H20111
NONE1111
INT:MUX.LONG.IO.V3[0, 15, 5][0, 14, 5]
0.LONG.IO.H100
0.LONG.IO.H301
NONE11
INT:MUX.LONG.H0[0, 12, 4][0, 13, 4][0, 14, 4][0, 15, 4]
0.LONG.IO.V00001
0.DEC.V00010
0.OUT.LR.IOB1.I20111
NONE1111
BSCAN:CONFIG[0, 25, 8]
BSCAN:ENABLE[0, 16, 5]
Non-inverted[0]
INT:MUX.LONG.H1[0, 19, 4][0, 16, 4][0, 18, 4][0, 17, 4]
0.LONG.IO.V10001
0.DEC.V10010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.LONG.H2[0, 19, 3][0, 18, 3]
0.LONG.IO.V200
0.DEC.V201
NONE11
INT:MUX.IMUX.BUFG.V[0, 23, 2][0, 19, 2][0, 22, 2][0, 21, 2][0, 20, 2][0, 20, 3]
0.IO.OCTAL.W.0000111
0.IO.OCTAL.W.7001011
0.LONG.IO.V0001101
0.LONG.IO.H0011111
0.OUT.IOB.CLKIN.N101110
NONE101111

CNR.BR

CNR.BR bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
0 STARTUP:CONFIG_RATE-----------------------------------------~INT:PASS.IO.DOUBLE.2.S.2.0.GCLK6~INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E~INT:BIPASS.IO.DOUBLE.2.S.2.QUAD.V1.2-~INT:PASS.QUAD.V0.3.0.DEC.H2INT:MUX.VCLK[6]--~INT:PASS.IO.DOUBLE.2.S.1.0.LONG.V7-
1 ~STARTUP:CRC-~BUFG.H:CLK_EN-~MISC:TCTEST~STARTUP:ENABLE.GTSDONE:PULL~STARTUP:INV.GTS~STARTUP:ENABLE.GSR~STARTUP:INV.GSRSTARTUP:STARTUP_CLK~STARTUP:SYNC_TO_DONESTARTUP:DONE_ACTIVE[0]~OSC:TM_OSCOSC:OSC_CLK~BUFG.H:ALT_PAD-----INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[6]~INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1INT:MUX.IMUX.BUFG.H[3]~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1~INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1INT:MUX.IO.DBUF.H1[1]INT:MUX.IO.DBUF.H1[0]--~INT:BIPASS.IO.DOUBLE.3.S.1.QUAD.V2.2~INT:BIPASS.IO.DOUBLE.3.S.2.QUAD.V2.1~INT:BIPASS.IO.DOUBLE.2.S.1.QUAD.V1.3~INT:BIPASS.IO.DOUBLE.0.S.1.QUAD.V0.2INT:MUX.VCLK[3]INT:MUX.VCLK[4]INT:MUX.VCLK[2]INT:MUX.VCLK[1]INT:MUX.VCLK[0]
2 --------------------INT:MUX.IMUX.BUFG.H[0]~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1INT:MUX.IMUX.BUFG.H[4]~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1~INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2INT:MUX.IO.DBUF.H1[3]INT:MUX.IO.DBUF.H1[2]-~INT:PASS.IO.DOUBLE.3.S.1.0.GCLK7~INT:PASS.IO.DOUBLE.1.S.2.0.GCLK5~INT:PASS.IO.DOUBLE.0.S.1.0.GCLK4~INT:PASS.QUAD.V1.3.0.DEC.H1~INT:BIPASS.IO.DOUBLE.0.S.2.QUAD.V0.1~INT:BIPASS.IO.DOUBLE.1.S.1.QUAD.V1.1~INT:PASS.IO.DOUBLE.3.S.2.0.LONG.V6INT:MUX.VCLK[5]~INT:PASS.IO.DOUBLE.0.S.2.0.LONG.V9~INT:BIPASS.IO.DOUBLE.1.S.2.QUAD.V0.3
3 ~BUFG.V:ALT_PAD~MISC:FIX_DISCHARGE-----~STARTUP:EXPRESS_MODE--INT:MUX.LONG.IO.H3[1]INT:MUX.LONG.IO.H3[0]STARTUP:DONE_ACTIVE[1]INT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.H1[1]STARTUP:GSR_INACTIVE[1]STARTUP:GSR_INACTIVE[0]STARTUP:OUTPUTS_ACTIVE[0]STARTUP:OUTPUTS_ACTIVE[1]INT:MUX.LONG.IO.H2[1]INT:MUX.LONG.IO.H2[0]INT:MUX.IMUX.BUFG.H[5]INT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1INT:MUX.IMUX.BUFG.H[2]~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2INT:MUX.LONG.IO.H0[4]INT:MUX.LONG.IO.H0[5]INT:MUX.LONG.IO.H1[6]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H1[7]INT:MUX.LONG.IO.H2[6]INT:MUX.LONG.IO.H3[5]INT:MUX.LONG.IO.H2[7]INT:MUX.LONG.IO.H2[4]INT:MUX.LONG.IO.H2[5]~PULLUP.DEC.H0:ENABLE-INT:MUX.ECLK.H[6]INT:MUX.ECLK.H[5]INT:MUX.ECLK.H[4]----~INT:PASS.IO.DOUBLE.1.S.1.0.LONG.V8~INT:BIPASS.QUAD.V0.0.LONG.IO.H0-
4 OSC:ENABLEOSC:MUX.OUT0[3]-OSC:MUX.OUT1[3]INT:MUX.LONG.IO.V3[1]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V3[2]INT:MUX.IO.DBUF.H0[3]INT:MUX.IO.DBUF.H0[1]INT:MUX.IO.DBUF.H0[0]INT:MUX.LONG.IO.V1[4]INT:MUX.IO.DBUF.H0[2]INT:MUX.LONG.IO.V3[0]~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V0.0.DEC.H3INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V3[4]~INT:PASS.SINGLE.V1.0.LONG.IO.H0~INT:PASS.SINGLE.V2.0.LONG.IO.H1INT:MUX.LONG.V0[3]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.V0[2]INT:MUX.LONG.IO.V2[4]INT:MUX.LONG.V0[1]INT:MUX.LONG.V0[0]-INT:MUX.LONG.IO.H3[4]~INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V5.0.LONG.IO.H2~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.EINT:MUX.LONG.V5[2]INT:MUX.LONG.V5[0]INT:MUX.LONG.V5[1]~INT:PASS.SINGLE.V7.0.DEC.H0INT:MUX.LONG.V5[3]~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E~PULLUP.DEC.H1:ENABLE~PULLUP.DEC.H2:ENABLE~PULLUP.DEC.H3:ENABLE-INT:MUX.ECLK.H[2]INT:MUX.ECLK.H[0]INT:MUX.ECLK.H[1]INT:MUX.ECLK.H[3]---~INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E~INT:BIPASS.QUAD.V2.0.LONG.IO.H3~INT:BIPASS.QUAD.V1.0.LONG.IO.H1
5 OSC:MUX.OUT1[2]OSC:MUX.OUT0[2]-INT:MUX.LONG.IO.V3[3]INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[2]~PULLUP.DEC.V0:ENABLE~PULLUP.DEC.V2:ENABLE~INT:PASS.SINGLE.V6.0.LONG.IO.H3~PULLUP.DEC.V1:ENABLE~PULLUP.DEC.V3:ENABLEINT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V2[2]-INT:MUX.LONG.H5[3]INT:MUX.LONG.H5[2]INT:MUX.LONG.H5[0]INT:MUX.LONG.H3[1]INT:MUX.LONG.V4[2]INT:MUX.LONG.V4[1]INT:MUX.LONG.V4[0]INT:MUX.LONG.V4[3]-~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.V2[1]INT:MUX.LONG.V2[3]INT:MUX.IMUX.STARTUP.GTS[0]INT:MUX.IMUX.STARTUP.GTS[5]INT:MUX.IMUX.STARTUP.GTS[4]INT:MUX.IMUX.STARTUP.GTS[3]INT:MUX.IMUX.STARTUP.GTS[2]INT:MUX.IMUX.STARTUP.GTS[1]INT:MUX.LONG.V3[3]INT:MUX.LONG.V3[0]INT:MUX.LONG.V1[1]INT:MUX.LONG.V1[3]INT:MUX.LONG.V1[0]-~INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H1[2]~INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H1[3]~INT:BUF.LONG.V7.0.LONG.IO.H1~INT:BUF.LONG.V6.0.LONG.IO.H0INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H0[2]~INT:PASS.QUAD.V2.3.0.DEC.H0-
6 ------INT:MUX.LONG.H4[2]INT:MUX.LONG.H4[0]~BUFG.V:CLK_ENINT:MUX.LONG.H4[1]INT:MUX.LONG.H4[3]~INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2-INT:MUX.IMUX.BUFG.V[0]INT:MUX.IMUX.BUFG.V[5]INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.H5[1]INT:MUX.LONG.H3[0]-~INT:BUF.LONG.H3.0.SINGLE.V4INT:MUX.LONG.V2[2]-INT:MUX.LONG.V2[0]~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEININT:MUX.IMUX.STARTUP.GSR[4]INT:MUX.IMUX.STARTUP.GSR[5]INT:MUX.IMUX.STARTUP.GSR[1]INT:MUX.IMUX.STARTUP.GSR[2]INT:MUX.IMUX.STARTUP.GSR[0]INT:MUX.IMUX.STARTUP.GSR[3]INT:MUX.LONG.V3[2]INT:MUX.LONG.V3[1]~INT:PASS.SINGLE.V3.0.DEC.H2INT:MUX.LONG.V1[2]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V4.0.DEC.H1~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H3[2]~INT:BUF.LONG.V9.0.LONG.IO.H3INT:MUX.LONG.IO.H3[3]--~INT:BUF.LONG.V8.0.LONG.IO.H2INT:MUX.LONG.IO.H2[3]INT:MUX.LONG.IO.H2[2]--
7 ----------------------------------------------------
8 -----------------------------~INT:PASS.SINGLE.H5.0.LONG.V4~INT:BIPASS.SINGLE.H1.SINGLE.V1.S~INT:BIPASS.SINGLE.H0.SINGLE.V0.S~INT:BIPASS.SINGLE.V1.SINGLE.V1.S-~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2~INT:PASS.SINGLE.H4.0.LONG.V3~INT:BIPASS.SINGLE.H5.SINGLE.V5INT:MUX.IMUX.STARTUP.CLK[3]INT:MUX.IMUX.STARTUP.CLK[2]INT:MUX.IMUX.STARTUP.CLK[1]INT:MUX.IMUX.STARTUP.CLK[0]------~INT:PASS.SINGLE.H4.E.0.LONG.V8~INT:PASS.SINGLE.H7.E.0.LONG.V9--
9 OSC:MUX.OUT1[1]OSC:MUX.OUT0[1]~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1INT:MUX.IMUX.READCLK.I[3]INT:MUX.IMUX.READCLK.I[0]INT:MUX.IMUX.READCLK.I[1]INT:MUX.IMUX.READCLK.I[2]~INT:PASS.SINGLE.H4.0.DEC.V2~INT:PASS.SINGLE.H5.0.LONG.IO.V2~INT:PASS.SINGLE.H0.0.DEC.V0~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0~INT:BUF.LONG.V3.0.SINGLE.H4~INT:PASS.SINGLE.H2.0.LONG.IO.V1~INT:BUF.LONG.V4.0.SINGLE.H5~INT:BUF.LONG.V0.0.SINGLE.H1.E~INT:BUF.LONG.H4.0.SINGLE.V5-------~INT:BIPASS.SINGLE.H0.E.SINGLE.V0~INT:BIPASS.SINGLE.H0.SINGLE.V0~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S~INT:BIPASS.SINGLE.H1.SINGLE.V1~INT:BIPASS.SINGLE.H1.SINGLE.H1.E~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S~INT:PASS.SINGLE.H1.E.0.LONG.V0~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2~INT:BIPASS.SINGLE.H5.SINGLE.H5.E~INT:BIPASS.SINGLE.H5.E.SINGLE.V5~INT:BIPASS.SINGLE.H5.SINGLE.V5.S~INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S~INT:BIPASS.SINGLE.V5.SINGLE.V5.S~INT:PASS.SINGLE.V5.0.LONG.H4----------
10 OSC:MUX.OUT1[0]~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1~INT:PASS.SINGLE.H7.0.DEC.V3~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0~INT:PASS.SINGLE.H6.0.LONG.IO.V3~INT:PASS.SINGLE.H1.0.LONG.IO.V0-~INT:BUF.LONG.H5.0.SINGLE.V6~INT:BUF.LONG.V2.0.SINGLE.H3.E~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S-~INT:PASS.SINGLE.V0.0.GND-~INT:BIPASS.SINGLE.H0.SINGLE.H0.E~INT:BIPASS.SINGLE.V0.SINGLE.V0.S~INT:BIPASS.SINGLE.H1.E.SINGLE.V1-~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2~INT:PASS.SINGLE.H3.E.0.LONG.V2~INT:BIPASS.SINGLE.H4.SINGLE.V4.S~INT:BIPASS.SINGLE.H4.SINGLE.H4.E~INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S~INT:BIPASS.SINGLE.V4.SINGLE.V4.S~INT:BIPASS.SINGLE.H4.SINGLE.V4-----------
11 OSC:MUX.OUT0[0]~INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0INT:MUX.IO.DBUF.V0[3]~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4~INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4-------------------~INT:PASS.SINGLE.V4.0.LONG.H3~INT:BIPASS.SINGLE.V3.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.SINGLE.V3~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0~INT:BIPASS.SINGLE.H3.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.SINGLE.H3.E~INT:BIPASS.SINGLE.H3.E.SINGLE.V3~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S~INT:BIPASS.SINGLE.H6.E.SINGLE.V6~INT:BIPASS.SINGLE.H6.SINGLE.H6.E~INT:BIPASS.SINGLE.H6.SINGLE.V6.S~INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S~INT:BIPASS.SINGLE.V6.SINGLE.V6.S-~INT:PASS.SINGLE.V6.0.LONG.H5~INT:PASS.SINGLE.H3.E.0.LONG.V7~INT:BUF.LONG.V7.0.SINGLE.H3.E~INT:BUF.LONG.V6.0.SINGLE.H0.E~INT:BIPASS.SINGLE.H4.E.QUAD.V2.0~INT:BIPASS.SINGLE.H1.E.QUAD.V0.3~INT:PASS.SINGLE.H0.E.0.LONG.V6~INT:BIPASS.SINGLE.H0.E.QUAD.V0.1~INT:BUF.LONG.V8.0.SINGLE.H4.E~INT:BUF.LONG.V9.0.SINGLE.H7.E-
12 ----------------------------~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2-~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2-~INT:BIPASS.SINGLE.H2.SINGLE.V2~INT:BIPASS.SINGLE.H2.SINGLE.H2.E~INT:BIPASS.SINGLE.H2.SINGLE.V2.S-~INT:BUF.LONG.V5.0.SINGLE.H6~INT:BIPASS.SINGLE.H6.SINGLE.V6~INT:BIPASS.SINGLE.H7.SINGLE.V7.S~INT:BUF.LONG.V1.0.SINGLE.H2.E~INT:BIPASS.SINGLE.H4.E.SINGLE.V4-~INT:BIPASS.SINGLE.H2.E.QUAD.V0.2~INT:BIPASS.SINGLE.H7.E.QUAD.V2.2~INT:BIPASS.DOUBLE.H0.2.QUAD.V0.0~INT:BIPASS.DOUBLE.H1.1.QUAD.V1.3-~INT:BIPASS.SINGLE.H5.E.QUAD.V1.1~INT:BIPASS.SINGLE.H6.E.QUAD.V2.3~INT:BIPASS.QUAD.H1.0.QUAD.H1.4~INT:BIPASS.SINGLE.H3.E.QUAD.V1.0-
13 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0INT:MUX.IO.DBUF.V0[2]INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]~INT:PASS.SINGLE.H3.0.DEC.V1INT:MUX.IO.DBUF.V1[3]~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1INT:MUX.IO.DBUF.V1[1]INT:MUX.IO.DBUF.V1[2]INT:MUX.IO.DBUF.V1[0]~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1~INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0--~INT:PASS.SINGLE.V7.0.GND~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2~INT:BIPASS.SINGLE.V2.SINGLE.V2.S~INT:BIPASS.SINGLE.H2.E.SINGLE.V2~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S-~INT:PASS.SINGLE.H6.0.LONG.V5~INT:BIPASS.SINGLE.H7.SINGLE.V7~INT:BIPASS.SINGLE.V7.SINGLE.V7.S~INT:BIPASS.SINGLE.H7.E.SINGLE.V7~INT:BIPASS.SINGLE.H7.SINGLE.H7.E~INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S~INT:PASS.SINGLE.H2.E.0.LONG.V1~INT:PASS.QUAD.H1.0.0.QBUF.1~INT:PASS.QUAD.V1.4.0.QBUF.1~INT:PASS.QUAD.H1.4.0.QBUF.1INT:MUX.QBUF.1[0]INT:MUX.QBUF.1[1]~INT:BIPASS.QUAD.H1.0.QUAD.V1.0~INT:BIPASS.QUAD.H1.0.QUAD.V1.4~INT:BIPASS.QUAD.V1.0.QUAD.V1.4~INT:BIPASS.QUAD.H1.4.QUAD.V1.0~INT:BIPASS.QUAD.H1.4.QUAD.V1.4
14 --~INT:BIPASS.QUAD.H0.0.LONG.IO.V3-~INT:BIPASS.IO.DOUBLE.1.E.0.QUAD.H0.1~INT:PASS.QUAD.H0.1.0.DEC.V3-INT:MUX.ECLK.V[6]INT:MUX.ECLK.V[2]INT:MUX.ECLK.V[3]INT:MUX.ECLK.V[4]INT:MUX.ECLK.V[5]INT:MUX.ECLK.V[1]INT:MUX.IMUX.CLB.G4[0]INT:MUX.ECLK.V[0]INT:MUX.IMUX.CLB.F4[1]~INT:PASS.QUAD.H2.1.0.DEC.V1~INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.H2.1~INT:BIPASS.IO.DOUBLE.0.E.0.QUAD.H0.3~INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S~INT:BIPASS.QUAD.H2.0.LONG.IO.V1~INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S-INT:MUX.IMUX.CLB.C4[1]INT:MUX.IMUX.CLB.C4[3]INT:MUX.IMUX.CLB.C4[4]--------~INT:BIPASS.DOUBLE.V0.2.QUAD.H0.3~INT:BIPASS.SINGLE.V1.S.QUAD.H0.0~INT:BIPASS.SINGLE.V3.S.QUAD.H1.1~INT:BIPASS.SINGLE.V7.S.QUAD.H2.1~INT:BIPASS.DOUBLE.V1.1.QUAD.H2.0~INT:BIPASS.SINGLE.V5.S.QUAD.H2.3INT:MUX.QBUF.0[0]INT:MUX.QBUF.0[1]~INT:PASS.QUAD.V1.0.0.QBUF.1~INT:PASS.QUAD.V0.4.0.QBUF.0~INT:PASS.QUAD.H0.4.0.QBUF.0~INT:PASS.QUAD.H0.0.0.QBUF.0~INT:PASS.QUAD.V0.0.0.QBUF.0INT:MUX.QBUF.2[0]INT:MUX.QBUF.2[1]~INT:PASS.QUAD.V2.4.0.QBUF.2~INT:PASS.QUAD.H2.4.0.QBUF.2~INT:PASS.QUAD.H2.0.0.QBUF.2
15 --~INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.H2.3-~INT:BIPASS.IO.DOUBLE.2.E.0.QUAD.H1.1~INT:PASS.QUAD.H1.1.0.DEC.V2-------INT:MUX.IMUX.CLB.G4[1]-INT:MUX.IMUX.CLB.F4[0]~INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S~INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S~INT:BIPASS.QUAD.H1.0.LONG.IO.V2~INT:BIPASS.IO.DOUBLE.3.E.0.QUAD.H2.2-~INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.H1.2-~INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.H0.2INT:MUX.IMUX.CLB.C4[0]INT:MUX.IMUX.CLB.C4[2]--------~INT:BIPASS.SINGLE.V0.S.QUAD.H0.2~INT:BIPASS.SINGLE.V2.S.QUAD.H1.2-~INT:BIPASS.SINGLE.V6.S.QUAD.H2.2~INT:BIPASS.SINGLE.V4.S.QUAD.H1.0~INT:BIPASS.QUAD.V0.0.QUAD.V0.4~INT:BIPASS.QUAD.H0.0.QUAD.V0.4~INT:BIPASS.QUAD.H0.4.QUAD.V0.4~INT:BIPASS.QUAD.H0.4.QUAD.V0.0~INT:BIPASS.QUAD.H0.0.QUAD.H0.4~INT:BIPASS.QUAD.H0.0.QUAD.V0.0~INT:BIPASS.QUAD.V2.0.QUAD.V2.4~INT:BIPASS.QUAD.H2.0.QUAD.V2.4~INT:BIPASS.QUAD.H2.4.QUAD.V2.4~INT:BIPASS.QUAD.H2.4.QUAD.V2.0~INT:BIPASS.QUAD.H2.0.QUAD.H2.4~INT:BIPASS.QUAD.H2.0.QUAD.V2.0~INT:PASS.QUAD.V2.0.0.QBUF.2
STARTUP:CONFIG_RATE[0, 0, 0]
FAST0
SLOW1
BUFG.H:ALT_PAD[0, 15, 1]
BUFG.H:CLK_EN[0, 2, 1]
BUFG.V:ALT_PAD[0, 0, 3]
BUFG.V:CLK_EN[0, 8, 6]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2[0, 30, 13]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0[0, 28, 13]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2[0, 29, 13]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0[0, 3, 13]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1[0, 3, 10]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1[0, 1, 13]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0[0, 14, 10]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1[0, 11, 13]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1[0, 16, 13]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0[0, 30, 11]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2[0, 30, 12]
INT:BIPASS.DOUBLE.H0.2.QUAD.V0.0[0, 44, 12]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2[0, 34, 10]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0[0, 33, 10]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2[0, 34, 8]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0[0, 2, 11]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1[0, 4, 10]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1[0, 2, 10]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0[0, 23, 13]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1[0, 20, 13]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1[0, 19, 13]
INT:BIPASS.DOUBLE.H1.1.QUAD.V1.3[0, 45, 12]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0[0, 34, 9]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2[0, 35, 9]
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2[0, 28, 12]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 29, 2]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1[0, 27, 3]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2[0, 31, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 25, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1[0, 25, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2[0, 27, 2]
INT:BIPASS.DOUBLE.V0.2.QUAD.H0.3[0, 34, 14]
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2[0, 35, 8]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1[0, 28, 1]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1[0, 30, 1]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2[0, 33, 2]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1[0, 37, 1]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1[0, 35, 2]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2[0, 37, 2]
INT:BIPASS.DOUBLE.V1.1.QUAD.H2.0[0, 38, 14]
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1[0, 10, 13]
INT:BIPASS.IO.DOUBLE.0.E.0.QUAD.H0.3[0, 18, 14]
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2[0, 24, 3]
INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.H0.2[0, 23, 15]
INT:BIPASS.IO.DOUBLE.0.S.1.QUAD.V0.2[0, 46, 1]
INT:BIPASS.IO.DOUBLE.0.S.2.QUAD.V0.1[0, 46, 2]
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1[0, 2, 13]
INT:BIPASS.IO.DOUBLE.1.E.0.QUAD.H0.1[0, 4, 14]
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2[0, 28, 3]
INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.H1.2[0, 21, 15]
INT:BIPASS.IO.DOUBLE.1.S.1.QUAD.V1.1[0, 47, 2]
INT:BIPASS.IO.DOUBLE.1.S.2.QUAD.V0.3[0, 51, 2]
INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1[0, 1, 11]
INT:BIPASS.IO.DOUBLE.2.E.0.QUAD.H1.1[0, 4, 15]
INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2[0, 31, 1]
INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.H2.3[0, 2, 15]
INT:BIPASS.IO.DOUBLE.2.S.1.QUAD.V1.3[0, 45, 1]
INT:BIPASS.IO.DOUBLE.2.S.2.QUAD.V1.2[0, 44, 0]
INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1[0, 21, 13]
INT:BIPASS.IO.DOUBLE.3.E.0.QUAD.H2.2[0, 19, 15]
INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2[0, 36, 2]
INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.H2.1[0, 17, 14]
INT:BIPASS.IO.DOUBLE.3.S.1.QUAD.V2.2[0, 43, 1]
INT:BIPASS.IO.DOUBLE.3.S.2.QUAD.V2.1[0, 44, 1]
INT:BIPASS.QUAD.H0.0.LONG.IO.V3[0, 2, 14]
INT:BIPASS.QUAD.H0.0.QUAD.H0.4[0, 43, 15]
INT:BIPASS.QUAD.H0.0.QUAD.V0.0[0, 44, 15]
INT:BIPASS.QUAD.H0.0.QUAD.V0.4[0, 40, 15]
INT:BIPASS.QUAD.H0.4.QUAD.V0.0[0, 42, 15]
INT:BIPASS.QUAD.H0.4.QUAD.V0.4[0, 41, 15]
INT:BIPASS.QUAD.H1.0.LONG.IO.V2[0, 18, 15]
INT:BIPASS.QUAD.H1.0.QUAD.H1.4[0, 49, 12]
INT:BIPASS.QUAD.H1.0.QUAD.V1.0[0, 47, 13]
INT:BIPASS.QUAD.H1.0.QUAD.V1.4[0, 48, 13]
INT:BIPASS.QUAD.H1.4.QUAD.V1.0[0, 50, 13]
INT:BIPASS.QUAD.H1.4.QUAD.V1.4[0, 51, 13]
INT:BIPASS.QUAD.H2.0.LONG.IO.V1[0, 20, 14]
INT:BIPASS.QUAD.H2.0.QUAD.H2.4[0, 49, 15]
INT:BIPASS.QUAD.H2.0.QUAD.V2.0[0, 50, 15]
INT:BIPASS.QUAD.H2.0.QUAD.V2.4[0, 46, 15]
INT:BIPASS.QUAD.H2.4.QUAD.V2.0[0, 48, 15]
INT:BIPASS.QUAD.H2.4.QUAD.V2.4[0, 47, 15]
INT:BIPASS.QUAD.V0.0.LONG.IO.H0[0, 50, 3]
INT:BIPASS.QUAD.V0.0.QUAD.V0.4[0, 39, 15]
INT:BIPASS.QUAD.V1.0.LONG.IO.H1[0, 51, 4]
INT:BIPASS.QUAD.V1.0.QUAD.V1.4[0, 49, 13]
INT:BIPASS.QUAD.V2.0.LONG.IO.H3[0, 50, 4]
INT:BIPASS.QUAD.V2.0.QUAD.V2.4[0, 45, 15]
INT:BIPASS.SINGLE.H0.E.QUAD.V0.1[0, 48, 11]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0[0, 27, 9]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S[0, 29, 9]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0[0, 13, 10]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1[0, 17, 13]
INT:BIPASS.SINGLE.H0.SINGLE.H0.E[0, 29, 10]
INT:BIPASS.SINGLE.H0.SINGLE.V0[0, 28, 9]
INT:BIPASS.SINGLE.H0.SINGLE.V0.S[0, 31, 8]
INT:BIPASS.SINGLE.H1.E.QUAD.V0.3[0, 46, 11]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1[0, 31, 10]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S[0, 32, 9]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1[0, 15, 13]
INT:BIPASS.SINGLE.H1.SINGLE.H1.E[0, 31, 9]
INT:BIPASS.SINGLE.H1.SINGLE.V1[0, 30, 9]
INT:BIPASS.SINGLE.H1.SINGLE.V1.S[0, 30, 8]
INT:BIPASS.SINGLE.H2.E.QUAD.V0.2[0, 42, 12]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2[0, 32, 13]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S[0, 33, 13]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0[0, 4, 13]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1[0, 0, 13]
INT:BIPASS.SINGLE.H2.SINGLE.H2.E[0, 33, 12]
INT:BIPASS.SINGLE.H2.SINGLE.V2[0, 32, 12]
INT:BIPASS.SINGLE.H2.SINGLE.V2.S[0, 34, 12]
INT:BIPASS.SINGLE.H3.E.QUAD.V1.0[0, 50, 12]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3[0, 33, 11]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S[0, 34, 11]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1[0, 3, 9]
INT:BIPASS.SINGLE.H3.SINGLE.H3.E[0, 32, 11]
INT:BIPASS.SINGLE.H3.SINGLE.V3[0, 29, 11]
INT:BIPASS.SINGLE.H3.SINGLE.V3.S[0, 31, 11]
INT:BIPASS.SINGLE.H4.E.QUAD.V2.0[0, 45, 11]
INT:BIPASS.SINGLE.H4.E.SINGLE.V4[0, 40, 12]
INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S[0, 38, 10]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0[0, 3, 11]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1[0, 1, 10]
INT:BIPASS.SINGLE.H4.SINGLE.H4.E[0, 37, 10]
INT:BIPASS.SINGLE.H4.SINGLE.V4[0, 40, 10]
INT:BIPASS.SINGLE.H4.SINGLE.V4.S[0, 36, 10]
INT:BIPASS.SINGLE.H5.E.QUAD.V1.1[0, 47, 12]
INT:BIPASS.SINGLE.H5.E.SINGLE.V5[0, 37, 9]
INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S[0, 39, 9]
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1[0, 2, 9]
INT:BIPASS.SINGLE.H5.SINGLE.H5.E[0, 36, 9]
INT:BIPASS.SINGLE.H5.SINGLE.V5[0, 37, 8]
INT:BIPASS.SINGLE.H5.SINGLE.V5.S[0, 38, 9]
INT:BIPASS.SINGLE.H6.E.QUAD.V2.3[0, 48, 12]
INT:BIPASS.SINGLE.H6.E.SINGLE.V6[0, 35, 11]
INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S[0, 38, 11]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0[0, 24, 13]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1[0, 18, 13]
INT:BIPASS.SINGLE.H6.SINGLE.H6.E[0, 36, 11]
INT:BIPASS.SINGLE.H6.SINGLE.V6[0, 37, 12]
INT:BIPASS.SINGLE.H6.SINGLE.V6.S[0, 37, 11]
INT:BIPASS.SINGLE.H7.E.QUAD.V2.2[0, 43, 12]
INT:BIPASS.SINGLE.H7.E.SINGLE.V7[0, 38, 13]
INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S[0, 40, 13]
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1[0, 22, 13]
INT:BIPASS.SINGLE.H7.SINGLE.H7.E[0, 39, 13]
INT:BIPASS.SINGLE.H7.SINGLE.V7[0, 36, 13]
INT:BIPASS.SINGLE.H7.SINGLE.V7.S[0, 38, 12]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1[0, 24, 1]
INT:BIPASS.SINGLE.V0.S.QUAD.H0.2[0, 34, 15]
INT:BIPASS.SINGLE.V0.SINGLE.V0.S[0, 30, 10]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1[0, 24, 2]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2[0, 28, 2]
INT:BIPASS.SINGLE.V1.S.QUAD.H0.0[0, 35, 14]
INT:BIPASS.SINGLE.V1.SINGLE.V1.S[0, 32, 8]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1[0, 30, 2]
INT:BIPASS.SINGLE.V2.S.QUAD.H1.2[0, 35, 15]
INT:BIPASS.SINGLE.V2.SINGLE.V2.S[0, 31, 13]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1[0, 25, 1]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2[0, 32, 2]
INT:BIPASS.SINGLE.V3.S.QUAD.H1.1[0, 36, 14]
INT:BIPASS.SINGLE.V3.SINGLE.V3.S[0, 28, 11]
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1[0, 27, 1]
INT:BIPASS.SINGLE.V4.S.QUAD.H1.0[0, 38, 15]
INT:BIPASS.SINGLE.V4.SINGLE.V4.S[0, 39, 10]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1[0, 29, 1]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2[0, 34, 2]
INT:BIPASS.SINGLE.V5.S.QUAD.H2.3[0, 39, 14]
INT:BIPASS.SINGLE.V5.SINGLE.V5.S[0, 40, 9]
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1[0, 38, 1]
INT:BIPASS.SINGLE.V6.S.QUAD.H2.2[0, 37, 15]
INT:BIPASS.SINGLE.V6.SINGLE.V6.S[0, 39, 11]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1[0, 36, 1]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2[0, 38, 2]
INT:BIPASS.SINGLE.V7.S.QUAD.H2.1[0, 37, 14]
INT:BIPASS.SINGLE.V7.SINGLE.V7.S[0, 37, 13]
INT:BUF.LONG.H3.0.SINGLE.V4[0, 24, 6]
INT:BUF.LONG.H4.0.SINGLE.V5[0, 19, 9]
INT:BUF.LONG.H5.0.SINGLE.V6[0, 18, 10]
INT:BUF.LONG.V0.0.SINGLE.H1.E[0, 18, 9]
INT:BUF.LONG.V1.0.SINGLE.H2.E[0, 39, 12]
INT:BUF.LONG.V2.0.SINGLE.H3.E[0, 19, 10]
INT:BUF.LONG.V3.0.SINGLE.H4[0, 15, 9]
INT:BUF.LONG.V4.0.SINGLE.H5[0, 17, 9]
INT:BUF.LONG.V5.0.SINGLE.H6[0, 36, 12]
INT:BUF.LONG.V6.0.LONG.IO.H0[0, 47, 5]
INT:BUF.LONG.V6.0.SINGLE.H0.E[0, 44, 11]
INT:BUF.LONG.V7.0.LONG.IO.H1[0, 46, 5]
INT:BUF.LONG.V7.0.SINGLE.H3.E[0, 43, 11]
INT:BUF.LONG.V8.0.LONG.IO.H2[0, 47, 6]
INT:BUF.LONG.V8.0.SINGLE.H4.E[0, 49, 11]
INT:BUF.LONG.V9.0.LONG.IO.H3[0, 43, 6]
INT:BUF.LONG.V9.0.SINGLE.H7.E[0, 50, 11]
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4[0, 6, 11]
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S[0, 12, 9]
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S[0, 25, 10]
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3[0, 21, 10]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 13, 4]
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2[0, 13, 6]
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN[0, 30, 4]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 39, 6]
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0[0, 14, 9]
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1[0, 23, 2]
INT:PASS.IO.DOUBLE.0.S.1.0.GCLK4[0, 44, 2]
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1[0, 10, 10]
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0[0, 32, 1]
INT:PASS.IO.DOUBLE.0.S.2.0.LONG.V9[0, 50, 2]
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0[0, 13, 9]
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1[0, 21, 2]
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1[0, 7, 10]
INT:PASS.IO.DOUBLE.1.S.1.0.LONG.V8[0, 49, 3]
INT:PASS.IO.DOUBLE.1.S.2.0.GCLK5[0, 43, 2]
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0[0, 33, 1]
INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0[0, 11, 10]
INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1[0, 22, 2]
INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1[0, 9, 10]
INT:PASS.IO.DOUBLE.2.S.1.0.LONG.V7[0, 50, 0]
INT:PASS.IO.DOUBLE.2.S.2.0.GCLK6[0, 42, 0]
INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0[0, 34, 1]
INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0[0, 12, 10]
INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1[0, 23, 1]
INT:PASS.IO.DOUBLE.3.S.1.0.GCLK7[0, 42, 2]
INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1[0, 8, 10]
INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0[0, 35, 1]
INT:PASS.IO.DOUBLE.3.S.2.0.LONG.V6[0, 48, 2]
INT:PASS.QUAD.H0.0.0.QBUF.0[0, 45, 14]
INT:PASS.QUAD.H0.1.0.DEC.V3[0, 5, 14]
INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S[0, 19, 14]
INT:PASS.QUAD.H0.4.0.QBUF.0[0, 44, 14]
INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S[0, 17, 15]
INT:PASS.QUAD.H1.0.0.QBUF.1[0, 42, 13]
INT:PASS.QUAD.H1.1.0.DEC.V2[0, 5, 15]
INT:PASS.QUAD.H1.4.0.QBUF.1[0, 44, 13]
INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S[0, 21, 14]
INT:PASS.QUAD.H2.0.0.QBUF.2[0, 51, 14]
INT:PASS.QUAD.H2.1.0.DEC.V1[0, 16, 14]
INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S[0, 16, 15]
INT:PASS.QUAD.H2.4.0.QBUF.2[0, 50, 14]
INT:PASS.QUAD.V0.0.0.QBUF.0[0, 46, 14]
INT:PASS.QUAD.V0.3.0.DEC.H2[0, 46, 0]
INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E[0, 44, 5]
INT:PASS.QUAD.V0.4.0.QBUF.0[0, 43, 14]
INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E[0, 43, 0]
INT:PASS.QUAD.V1.0.0.QBUF.1[0, 42, 14]
INT:PASS.QUAD.V1.3.0.DEC.H1[0, 45, 2]
INT:PASS.QUAD.V1.4.0.QBUF.1[0, 43, 13]
INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E[0, 42, 5]
INT:PASS.QUAD.V2.0.0.QBUF.2[0, 51, 15]
INT:PASS.QUAD.V2.3.0.DEC.H0[0, 50, 5]
INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E[0, 49, 4]
INT:PASS.QUAD.V2.4.0.QBUF.2[0, 49, 14]
INT:PASS.SINGLE.H0.0.DEC.V0[0, 10, 9]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 24, 10]
INT:PASS.SINGLE.H0.E.0.LONG.V6[0, 47, 11]
INT:PASS.SINGLE.H1.0.LONG.IO.V0[0, 16, 10]
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3[0, 20, 10]
INT:PASS.SINGLE.H1.E.0.LONG.V0[0, 33, 9]
INT:PASS.SINGLE.H2.0.LONG.IO.V1[0, 16, 9]
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4[0, 5, 11]
INT:PASS.SINGLE.H2.E.0.LONG.V1[0, 41, 13]
INT:PASS.SINGLE.H3.0.DEC.V1[0, 8, 13]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 11, 9]
INT:PASS.SINGLE.H3.E.0.LONG.V2[0, 35, 10]
INT:PASS.SINGLE.H3.E.0.LONG.V7[0, 42, 11]
INT:PASS.SINGLE.H4.0.DEC.V2[0, 8, 9]
INT:PASS.SINGLE.H4.0.LONG.V3[0, 36, 8]
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S[0, 23, 10]
INT:PASS.SINGLE.H4.E.0.LONG.V8[0, 48, 8]
INT:PASS.SINGLE.H5.0.LONG.IO.V2[0, 9, 9]
INT:PASS.SINGLE.H5.0.LONG.V4[0, 29, 8]
INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3[0, 22, 10]
INT:PASS.SINGLE.H6.0.LONG.IO.V3[0, 15, 10]
INT:PASS.SINGLE.H6.0.LONG.V5[0, 35, 13]
INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4[0, 7, 11]
INT:PASS.SINGLE.H7.0.DEC.V3[0, 5, 10]
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S[0, 6, 10]
INT:PASS.SINGLE.H7.E.0.LONG.V9[0, 49, 8]
INT:PASS.SINGLE.V0.0.DEC.H3[0, 14, 4]
INT:PASS.SINGLE.V0.0.GND[0, 27, 10]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 27, 5]
INT:PASS.SINGLE.V1.0.LONG.IO.H0[0, 18, 4]
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN[0, 28, 6]
INT:PASS.SINGLE.V2.0.LONG.IO.H1[0, 19, 4]
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2[0, 12, 6]
INT:PASS.SINGLE.V3.0.DEC.H2[0, 37, 6]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 31, 4]
INT:PASS.SINGLE.V4.0.DEC.H1[0, 40, 6]
INT:PASS.SINGLE.V4.0.LONG.H3[0, 27, 11]
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E[0, 41, 6]
INT:PASS.SINGLE.V5.0.LONG.H4[0, 41, 9]
INT:PASS.SINGLE.V5.0.LONG.IO.H2[0, 29, 4]
INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN[0, 28, 4]
INT:PASS.SINGLE.V6.0.LONG.H5[0, 41, 11]
INT:PASS.SINGLE.V6.0.LONG.IO.H3[0, 10, 5]
INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2[0, 11, 6]
INT:PASS.SINGLE.V7.0.DEC.H0[0, 35, 4]
INT:PASS.SINGLE.V7.0.GND[0, 27, 13]
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E[0, 37, 4]
MISC:FIX_DISCHARGE[0, 1, 3]
MISC:TCTEST[0, 4, 1]
OSC:TM_OSC[0, 13, 1]
PULLUP.DEC.H0:ENABLE[0, 40, 3]
PULLUP.DEC.H1:ENABLE[0, 38, 4]
PULLUP.DEC.H2:ENABLE[0, 39, 4]
PULLUP.DEC.H3:ENABLE[0, 40, 4]
PULLUP.DEC.V0:ENABLE[0, 8, 5]
PULLUP.DEC.V1:ENABLE[0, 11, 5]
PULLUP.DEC.V2:ENABLE[0, 9, 5]
PULLUP.DEC.V3:ENABLE[0, 12, 5]
STARTUP:CRC[0, 0, 1]
STARTUP:ENABLE.GSR[0, 8, 1]
STARTUP:ENABLE.GTS[0, 5, 1]
STARTUP:EXPRESS_MODE[0, 7, 3]
STARTUP:INV.GSR[0, 9, 1]
STARTUP:INV.GTS[0, 7, 1]
STARTUP:SYNC_TO_DONE[0, 11, 1]
Inverted~[0]
OSC:ENABLE[0, 0, 4]
Non-inverted[0]
OSC:MUX.OUT0[0, 1, 4][0, 1, 5][0, 1, 9][0, 0, 11]
OSC:MUX.OUT1[0, 3, 4][0, 0, 5][0, 0, 9][0, 0, 10]
F4900011
F16K0101
F500K0110
F151111
INT:MUX.IMUX.READCLK.I[0, 4, 9][0, 7, 9][0, 6, 9][0, 5, 9]
0.SINGLE.H20011
0.SINGLE.H30101
0.SINGLE.H40110
0.SINGLE.H51111
DONE:PULL[0, 6, 1]
PULLUP0
PULLNONE1
INT:MUX.LONG.IO.V1[0, 10, 4][0, 5, 4][0, 7, 5][0, 5, 5][0, 6, 5]
0.LONG.H300011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H201111
NONE11111
INT:MUX.IO.DBUF.V0[0, 4, 11][0, 5, 13][0, 7, 13][0, 6, 13]
0.IO.DOUBLE.1.S.10011
0.IO.DOUBLE.2.S.10101
0.IO.DOUBLE.3.S.10110
0.IO.DOUBLE.0.S.11111
INT:MUX.LONG.H4[0, 10, 6][0, 6, 6][0, 9, 6][0, 7, 6]
0.LONG.IO.V20001
0.DEC.V10010
0.OUT.STARTUP.Q30111
NONE1111
INT:MUX.IO.DBUF.H0[0, 7, 4][0, 11, 4][0, 8, 4][0, 9, 4]
0.IO.DOUBLE.0.E.10011
0.IO.DOUBLE.2.E.10101
0.IO.DOUBLE.3.E.10110
0.IO.DOUBLE.1.E.11111
STARTUP:STARTUP_CLK[0, 10, 1]
CCLK0
USERCLK1
INT:MUX.LONG.IO.H3[0, 36, 3][0, 27, 4][0, 44, 6][0, 42, 6][0, 10, 3][0, 11, 3]
0.LONG.V5001111
0.SINGLE.V6011111
0.LONG.V9110011
0.GCLK7110111
0.LONG.IO.V1111100
0.LONG.IO.V3111101
NONE111111
STARTUP:DONE_ACTIVE[0, 12, 3][0, 12, 1]
Q200
Q301
Q1Q410
Q011
INT:MUX.LONG.IO.V3[0, 17, 4][0, 3, 5][0, 6, 4][0, 4, 4][0, 12, 4]
0.LONG.H500011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H601111
NONE11111
INT:MUX.LONG.IO.H1[0, 34, 3][0, 31, 3][0, 33, 3][0, 32, 3][0, 45, 5][0, 43, 5][0, 14, 3][0, 13, 3]
0.LONG.V100011111
0.LONG.V300101111
0.SINGLE.V201111111
0.LONG.V711110011
0.GCLK511110111
0.LONG.IO.V311111100
0.LONG.IO.V111111101
NONE11111111
INT:MUX.LONG.IO.V2[0, 23, 4][0, 4, 5][0, 16, 5][0, 14, 5][0, 13, 5]
0.LONG.H400011
0.LONG.IO.H000101
0.LONG.IO.H200110
0.SINGLE.H501111
NONE11111
INT:MUX.IMUX.CLB.G4[0, 13, 15][0, 13, 14]
0.LONG.V901
0.GCLK410
0.LONG.V611
OSC:OSC_CLK[0, 14, 1]
EXTCLK0
CCLK1
INT:MUX.IO.DBUF.V1[0, 9, 13][0, 13, 13][0, 12, 13][0, 14, 13]
0.IO.DOUBLE.0.E.00011
0.IO.DOUBLE.1.E.00101
0.IO.DOUBLE.3.E.00110
0.IO.DOUBLE.2.E.01111
INT:MUX.ECLK.V[0, 7, 14][0, 11, 14][0, 10, 14][0, 9, 14][0, 8, 14][0, 12, 14][0, 14, 14]
0.LONG.IO.H30011001
0.SINGLE.H20011111
0.LONG.IO.H10101001
0.SINGLE.H30101111
0.LONG.IO.H00110001
0.SINGLE.H40110111
0.OUT.BUFGE.H0111010
0.IO.DOUBLE.3.E.11111001
0.SINGLE.H51111111
INT:MUX.IMUX.BUFG.V[0, 16, 6][0, 17, 6][0, 18, 6][0, 20, 6][0, 19, 6][0, 15, 6]
0.IO.OCTAL.E.7000111
0.LONG.IO.H0001011
0.LONG.IO.V0001101
0.IO.OCTAL.E.0011111
0.OUT.IOB.CLKIN.S101110
NONE101111
INT:MUX.IMUX.CLB.F4[0, 15, 14][0, 15, 15]
0.LONG.V701
0.LONG.V910
0.GCLK411
STARTUP:GSR_INACTIVE[0, 15, 3][0, 16, 3]
DONE_IN00
Q301
Q1Q410
Q211
INT:MUX.LONG.IO.V0[0, 21, 4][0, 15, 5][0, 15, 4][0, 16, 4]
0.LONG.IO.H00001
0.LONG.IO.H20010
0.SINGLE.H10111
NONE1111
STARTUP:OUTPUTS_ACTIVE[0, 18, 3][0, 17, 3]
Q300
DONE_IN01
Q210
Q1Q411
INT:MUX.IMUX.BUFG.H[0, 22, 1][0, 21, 3][0, 26, 2][0, 26, 1][0, 26, 3][0, 21, 1][0, 20, 2]
0.IO.DOUBLE.3.E.10001101
0.IO.DOUBLE.0.E.10001111
0.IO.DOUBLE.2.S.10010101
0.IO.DOUBLE.0.S.10010111
0.IO.DOUBLE.3.S.10011001
0.IO.DOUBLE.1.E.10011011
0.IO.DOUBLE.1.S.10111101
0.IO.DOUBLE.2.E.10111111
0.OUT.IOB.CLKIN.E1011110
NONE1011111
INT:MUX.LONG.IO.H2[0, 37, 3][0, 35, 3][0, 39, 3][0, 38, 3][0, 48, 6][0, 49, 6][0, 19, 3][0, 20, 3]
0.LONG.V200011111
0.LONG.V400101111
0.SINGLE.V501111111
0.LONG.V811110011
0.GCLK611110111
0.LONG.IO.V011111100
0.LONG.IO.V211111101
NONE11111111
INT:MUX.LONG.H5[0, 18, 5][0, 19, 5][0, 21, 6][0, 20, 5]
0.LONG.IO.V30001
0.DEC.V00010
0.OUT.STARTUP.Q30111
NONE1111
INT:MUX.LONG.IO.H0[0, 30, 3][0, 29, 3][0, 48, 5][0, 49, 5][0, 23, 3][0, 22, 3]
0.LONG.V0001111
0.SINGLE.V1011111
0.LONG.V6110011
0.GCLK4110111
0.LONG.IO.V2111100
0.LONG.IO.V0111101
NONE111111
INT:MUX.LONG.H3[0, 21, 5][0, 22, 6]
0.LONG.IO.V100
0.DEC.V201
NONE11
INT:MUX.LONG.V4[0, 25, 5][0, 22, 5][0, 23, 5][0, 24, 5]
0.LONG.IO.H20001
0.DEC.H20010
0.OUT.STARTUP.DONEIN0111
NONE1111
INT:MUX.IMUX.CLB.C4[0, 25, 14][0, 24, 14][0, 25, 15][0, 23, 14][0, 24, 15]
0.LONG.V001111
0.LONG.V410111
0.LONG.V611011
0.LONG.V811101
0.GCLK511110
NONE11111
INT:MUX.LONG.V0[0, 20, 4][0, 22, 4][0, 24, 4][0, 25, 4]
0.LONG.IO.H00001
0.DEC.H00010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.LONG.V2[0, 29, 5][0, 25, 6][0, 28, 5][0, 27, 6]
0.LONG.IO.H20001
0.DEC.H20010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.IMUX.STARTUP.GTS[0, 31, 5][0, 32, 5][0, 33, 5][0, 34, 5][0, 35, 5][0, 30, 5]
0.LONG.H3001110
0.SINGLE.V2001111
0.SINGLE.V3010111
0.LONG.H5011010
0.SINGLE.V4011011
0.LONG.H4011100
0.SINGLE.V5011101
0.DOUBLE.H1.0111110
0.DOUBLE.H0.1111111
INT:MUX.LONG.V5[0, 36, 4][0, 32, 4][0, 34, 4][0, 33, 4]
0.LONG.IO.H30001
0.DEC.H30010
0.OUT.STARTUP.DONEIN0111
NONE1111
INT:MUX.IMUX.STARTUP.GSR[0, 30, 6][0, 29, 6][0, 34, 6][0, 32, 6][0, 31, 6][0, 33, 6]
0.SINGLE.H2000111
0.SINGLE.H3001011
0.LONG.V4001110
0.LONG.V5010111
0.DOUBLE.V1.1011011
0.SINGLE.H4011101
0.LONG.V3011110
0.DOUBLE.V0.0101111
0.SINGLE.H5111111
INT:MUX.LONG.V3[0, 36, 5][0, 35, 6][0, 36, 6][0, 37, 5]
0.LONG.IO.H10001
0.DEC.H10010
0.OUT.STARTUP.DONEIN0111
NONE1111
INT:MUX.IO.DBUF.H1[0, 39, 2][0, 40, 2][0, 39, 1][0, 40, 1]
0.IO.DOUBLE.1.S.20011
0.IO.DOUBLE.2.S.20101
0.IO.DOUBLE.3.S.20110
0.IO.DOUBLE.0.S.21111
INT:MUX.LONG.V1[0, 39, 5][0, 38, 6][0, 38, 5][0, 40, 5]
0.LONG.IO.H10001
0.DEC.H10010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.QBUF.0[0, 41, 14][0, 40, 14]
0.QUAD.V0.400
0.QUAD.H0.001
0.QUAD.V0.010
0.QUAD.H0.411
INT:MUX.IMUX.STARTUP.CLK[0, 38, 8][0, 39, 8][0, 40, 8][0, 41, 8]
0.SINGLE.V30011
0.SINGLE.V40101
0.SINGLE.V50110
0.SINGLE.V21111
INT:MUX.ECLK.H[0, 42, 3][0, 43, 3][0, 44, 3][0, 45, 4][0, 42, 4][0, 44, 4][0, 43, 4]
0.LONG.IO.H10011001
0.GCLK50011010
0.SINGLE.V30011111
0.OUT.BUFGE.V0101001
0.GCLK60101010
0.SINGLE.V40101111
0.LONG.IO.H30110001
0.GCLK70110010
0.SINGLE.V50110111
0.LONG.IO.H01111001
0.GCLK41111010
0.SINGLE.V21111111
INT:MUX.QBUF.1[0, 46, 13][0, 45, 13]
0.QUAD.V1.400
0.QUAD.H1.001
0.QUAD.V1.010
0.QUAD.H1.411
INT:MUX.QBUF.2[0, 48, 14][0, 47, 14]
0.QUAD.V2.400
0.QUAD.H2.001
0.QUAD.V2.010
0.QUAD.H2.411
INT:MUX.VCLK[0, 47, 0][0, 49, 2][0, 48, 1][0, 47, 1][0, 49, 1][0, 50, 1][0, 51, 1]
0.LONG.IO.H00011001
0.LONG.IO.H10011010
0.IO.DOUBLE.0.S.20011111
NONE0101001
0.OUT.BT.IOB1.I1.E0101010
0.IO.DOUBLE.1.S.10101111
0.QUAD.V0.00110001
0.LONG.IO.H30110010
0.IO.DOUBLE.2.S.10110111
0.ECLK.H1111001
0.BUFGE.H1111010
0.IO.DOUBLE.3.S.21111111

CNR.TR

CNR.TR bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
0 ----------------------------------------------------
1 ----------------------------------------------------
2 ------INT:MUX.LONG.H1[2]INT:MUX.LONG.H1[0]~BUFG.V:CLK_ENINT:MUX.LONG.H1[1]INT:MUX.LONG.H1[3]~INT:PASS.SINGLE.V6.0.OUT.UPDATE.O~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O~MISC:TM_RIGHTINT:MUX.IMUX.BUFG.V[0]INT:MUX.IMUX.BUFG.V[5]INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.H0[1]INT:MUX.LONG.H2[0]-~INT:BUF.LONG.H2.0.SINGLE.V3INT:MUX.LONG.V2[2]-INT:MUX.LONG.V2[0]~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1INT:MUX.IMUX.TDO.T[5]INT:MUX.IMUX.TDO.T[4]INT:MUX.IMUX.TDO.T[0]INT:MUX.IMUX.TDO.T[3]INT:MUX.IMUX.TDO.T[2]INT:MUX.IMUX.TDO.T[1]INT:MUX.LONG.V3[2]INT:MUX.LONG.V3[1]~INT:PASS.SINGLE.V3.0.DEC.H1INT:MUX.LONG.V1[2]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V4.0.DEC.H2~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H3[2]~INT:BUF.LONG.V9.0.LONG.IO.H3INT:MUX.LONG.IO.H3[3]--~INT:BUF.LONG.V8.0.LONG.IO.H2INT:MUX.LONG.IO.H2[3]INT:MUX.LONG.IO.H2[2]--
3 -----INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[1]~PULLUP.DEC.V0:ENABLE~PULLUP.DEC.V2:ENABLE~INT:PASS.SINGLE.V6.0.LONG.IO.H3~PULLUP.DEC.V1:ENABLE~PULLUP.DEC.V3:ENABLEINT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V2[1]-INT:MUX.LONG.H0[3]INT:MUX.LONG.H0[2]INT:MUX.LONG.H0[0]INT:MUX.LONG.H2[1]INT:MUX.LONG.V4[2]INT:MUX.LONG.V4[1]INT:MUX.LONG.V4[0]INT:MUX.LONG.V4[3]-~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.V2[1]INT:MUX.LONG.V2[3]INT:MUX.IMUX.TDO.O[0]INT:MUX.IMUX.TDO.O[5]INT:MUX.IMUX.TDO.O[4]INT:MUX.IMUX.TDO.O[3]INT:MUX.IMUX.TDO.O[2]INT:MUX.IMUX.TDO.O[1]INT:MUX.LONG.V3[3]INT:MUX.LONG.V3[0]INT:MUX.LONG.V1[1]INT:MUX.LONG.V1[3]INT:MUX.LONG.V1[0]-~INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H1[2]~INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.IO.H1[3]~INT:BUF.LONG.V7.0.LONG.IO.H1~INT:BUF.LONG.V6.0.LONG.IO.H0INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H0[2]~INT:PASS.QUAD.V0.2.0.OUT.TOP.COUT.E~INT:PASS.QUAD.V2.2.0.DEC.H3
4 -------INT:MUX.IO.DBUF.H0[3]INT:MUX.IO.DBUF.H0[1]INT:MUX.IO.DBUF.H0[0]INT:MUX.LONG.IO.V1[3]INT:MUX.IO.DBUF.H0[2]INT:MUX.LONG.IO.V3[0]~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V0.0.DEC.H0INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V3[1]~INT:PASS.SINGLE.V1.0.LONG.IO.H0~INT:PASS.SINGLE.V2.0.LONG.IO.H1INT:MUX.LONG.V0[3]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.V0[2]INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.V0[1]INT:MUX.LONG.V0[0]-INT:MUX.LONG.IO.H3[4]~INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V5.0.LONG.IO.H2~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.EINT:MUX.LONG.V5[2]INT:MUX.LONG.V5[0]INT:MUX.LONG.V5[1]~INT:PASS.SINGLE.V7.0.DEC.H3INT:MUX.LONG.V5[3]~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E~PULLUP.DEC.H2:ENABLE~PULLUP.DEC.H1:ENABLE~PULLUP.DEC.H0:ENABLE-INT:MUX.ECLK.H[2]INT:MUX.ECLK.H[0]INT:MUX.ECLK.H[1]INT:MUX.ECLK.H[3]---~INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E~INT:BIPASS.QUAD.V2.3.LONG.IO.H3~INT:BIPASS.QUAD.V1.3.LONG.IO.H1
5 -------~TDO:ENABLE.T~TDO:ENABLE.O-INT:MUX.LONG.IO.H3[1]INT:MUX.LONG.IO.H3[0]READCLK:READ_CLKINT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.H1[1]~MISC:TACTDO:PULL[0]BSCAN:ENABLETDO:PULL[1]INT:MUX.LONG.IO.H2[1]INT:MUX.LONG.IO.H2[0]INT:MUX.IMUX.BUFG.H[5]INT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1INT:MUX.IMUX.BUFG.H[1]~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2INT:MUX.LONG.IO.H0[4]INT:MUX.LONG.IO.H0[5]INT:MUX.LONG.IO.H1[6]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H1[7]INT:MUX.LONG.IO.H2[6]INT:MUX.LONG.IO.H3[5]INT:MUX.LONG.IO.H2[7]INT:MUX.LONG.IO.H2[4]INT:MUX.LONG.IO.H2[5]~PULLUP.DEC.H3:ENABLE-INT:MUX.ECLK.H[6]INT:MUX.ECLK.H[5]INT:MUX.ECLK.H[4]----~INT:PASS.IO.DOUBLE.1.E.1.0.LONG.V8~INT:BIPASS.QUAD.V0.3.LONG.IO.H0-
6 --------------------INT:MUX.IMUX.BUFG.H[0]~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2INT:MUX.IMUX.BUFG.H[3]~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1~INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0INT:MUX.IO.DBUF.H1[3]INT:MUX.IO.DBUF.H1[2]-~INT:PASS.IO.DOUBLE.3.E.1.0.GCLK7~INT:PASS.IO.DOUBLE.1.N.0.0.GCLK5~INT:PASS.IO.DOUBLE.0.E.1.0.GCLK4~INT:PASS.QUAD.V1.2.0.DEC.H2~INT:BIPASS.IO.DOUBLE.0.N.0.QUAD.V0.1~INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.V1.1~INT:PASS.IO.DOUBLE.3.N.0.0.LONG.V6INT:MUX.VCLK[5]~INT:PASS.IO.DOUBLE.0.N.0.0.LONG.V9~INT:BIPASS.IO.DOUBLE.1.N.0.QUAD.V0.0
7 ---------------------INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[6]~INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2INT:MUX.IMUX.BUFG.H[4]~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1~INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1INT:MUX.IO.DBUF.H1[1]INT:MUX.IO.DBUF.H1[0]--~INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.V2.0~INT:BIPASS.IO.DOUBLE.3.N.0.QUAD.V2.1~INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.V1.0~INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.V0.2INT:MUX.VCLK[3]INT:MUX.VCLK[4]INT:MUX.VCLK[2]INT:MUX.VCLK[1]INT:MUX.VCLK[0]
8 -MISC:ADDRESS_LINES~BUFG.H:CLK_EN~BSCAN:STATUS--------------------------------------~INT:PASS.IO.DOUBLE.2.N.0.0.GCLK6~INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E~INT:BIPASS.IO.DOUBLE.2.N.0.QUAD.V1.2-~INT:PASS.QUAD.V0.2.0.DEC.H1INT:MUX.VCLK[6]-~BUFG.H:ALT_PAD~INT:PASS.IO.DOUBLE.2.E.1.0.LONG.V7~BUFG.V:ALT_PAD
CNR.TR bittile 1
RowColumn
01234567891011121314151617181920212223242526272829303132333435
0 ------------------------------------
1 ------------------------------------
2 ------------------------------------
3 ------------------------------------
4 ------------------------------------
5 ------------------------------------
6 ------------------------------------
7 ------------------------------------
8 ---------------------------~INT:BUF.LONG.H0.0.SINGLE.V1-~INT:PASS.SINGLE.V1.0.LONG.H0-~INT:BUF.LONG.H1.0.SINGLE.V2---~INT:PASS.SINGLE.V2.0.LONG.H1
9 ----------------------------------~INT:PASS.SINGLE.V3.0.LONG.H2-
MISC:ADDRESS_LINES[0, 1, 8]
220
181
BSCAN:STATUS[0, 3, 8]
BUFG.H:ALT_PAD[0, 49, 8]
BUFG.H:CLK_EN[0, 2, 8]
BUFG.V:ALT_PAD[0, 51, 8]
BUFG.V:CLK_EN[0, 8, 2]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 27, 5]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2[0, 29, 6]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0[0, 31, 6]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 25, 5]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2[0, 25, 6]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0[0, 27, 6]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1[0, 30, 7]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2[0, 28, 7]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0[0, 33, 6]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1[0, 35, 6]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2[0, 37, 7]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0[0, 37, 6]
INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.V0.2[0, 46, 7]
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2[0, 24, 5]
INT:BIPASS.IO.DOUBLE.0.N.0.QUAD.V0.1[0, 46, 6]
INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.V1.1[0, 47, 6]
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2[0, 28, 5]
INT:BIPASS.IO.DOUBLE.1.N.0.QUAD.V0.0[0, 51, 6]
INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.V1.0[0, 45, 7]
INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2[0, 31, 7]
INT:BIPASS.IO.DOUBLE.2.N.0.QUAD.V1.2[0, 44, 8]
INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.V2.0[0, 43, 7]
INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2[0, 36, 6]
INT:BIPASS.IO.DOUBLE.3.N.0.QUAD.V2.1[0, 44, 7]
INT:BIPASS.QUAD.V0.3.LONG.IO.H0[0, 50, 5]
INT:BIPASS.QUAD.V1.3.LONG.IO.H1[0, 51, 4]
INT:BIPASS.QUAD.V2.3.LONG.IO.H3[0, 50, 4]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1[0, 24, 7]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2[0, 24, 6]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0[0, 28, 6]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1[0, 30, 6]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2[0, 25, 7]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0[0, 32, 6]
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1[0, 27, 7]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2[0, 29, 7]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0[0, 34, 6]
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1[0, 38, 7]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2[0, 36, 7]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0[0, 38, 6]
INT:BUF.LONG.H0.0.SINGLE.V1[1, 27, 8]
INT:BUF.LONG.H1.0.SINGLE.V2[1, 31, 8]
INT:BUF.LONG.H2.0.SINGLE.V3[0, 24, 2]
INT:BUF.LONG.V6.0.LONG.IO.H0[0, 47, 3]
INT:BUF.LONG.V7.0.LONG.IO.H1[0, 46, 3]
INT:BUF.LONG.V8.0.LONG.IO.H2[0, 47, 2]
INT:BUF.LONG.V9.0.LONG.IO.H3[0, 43, 2]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 13, 4]
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O[0, 13, 2]
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1[0, 30, 4]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 39, 2]
INT:PASS.IO.DOUBLE.0.E.1.0.GCLK4[0, 44, 6]
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1[0, 23, 6]
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0[0, 32, 7]
INT:PASS.IO.DOUBLE.0.N.0.0.LONG.V9[0, 50, 6]
INT:PASS.IO.DOUBLE.1.E.1.0.LONG.V8[0, 49, 5]
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1[0, 21, 6]
INT:PASS.IO.DOUBLE.1.N.0.0.GCLK5[0, 43, 6]
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0[0, 33, 7]
INT:PASS.IO.DOUBLE.2.E.1.0.LONG.V7[0, 50, 8]
INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1[0, 22, 6]
INT:PASS.IO.DOUBLE.2.N.0.0.GCLK6[0, 42, 8]
INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0[0, 34, 7]
INT:PASS.IO.DOUBLE.3.E.1.0.GCLK7[0, 42, 6]
INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1[0, 23, 7]
INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0[0, 35, 7]
INT:PASS.IO.DOUBLE.3.N.0.0.LONG.V6[0, 48, 6]
INT:PASS.QUAD.V0.2.0.DEC.H1[0, 46, 8]
INT:PASS.QUAD.V0.2.0.OUT.TOP.COUT.E[0, 50, 3]
INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E[0, 44, 3]
INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E[0, 43, 8]
INT:PASS.QUAD.V1.2.0.DEC.H2[0, 45, 6]
INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E[0, 42, 3]
INT:PASS.QUAD.V2.2.0.DEC.H3[0, 51, 3]
INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E[0, 49, 4]
INT:PASS.SINGLE.V0.0.DEC.H0[0, 14, 4]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 27, 3]
INT:PASS.SINGLE.V1.0.LONG.H0[1, 29, 8]
INT:PASS.SINGLE.V1.0.LONG.IO.H0[0, 18, 4]
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1[0, 28, 2]
INT:PASS.SINGLE.V2.0.LONG.H1[1, 35, 8]
INT:PASS.SINGLE.V2.0.LONG.IO.H1[0, 19, 4]
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O[0, 12, 2]
INT:PASS.SINGLE.V3.0.DEC.H1[0, 37, 2]
INT:PASS.SINGLE.V3.0.LONG.H2[1, 34, 9]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 31, 4]
INT:PASS.SINGLE.V4.0.DEC.H2[0, 40, 2]
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E[0, 41, 2]
INT:PASS.SINGLE.V5.0.LONG.IO.H2[0, 29, 4]
INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1[0, 28, 4]
INT:PASS.SINGLE.V6.0.LONG.IO.H3[0, 10, 3]
INT:PASS.SINGLE.V6.0.OUT.UPDATE.O[0, 11, 2]
INT:PASS.SINGLE.V7.0.DEC.H3[0, 35, 4]
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E[0, 37, 4]
MISC:TAC[0, 15, 5]
MISC:TM_RIGHT[0, 14, 2]
PULLUP.DEC.H0:ENABLE[0, 40, 4]
PULLUP.DEC.H1:ENABLE[0, 39, 4]
PULLUP.DEC.H2:ENABLE[0, 38, 4]
PULLUP.DEC.H3:ENABLE[0, 40, 5]
PULLUP.DEC.V0:ENABLE[0, 8, 3]
PULLUP.DEC.V1:ENABLE[0, 11, 3]
PULLUP.DEC.V2:ENABLE[0, 9, 3]
PULLUP.DEC.V3:ENABLE[0, 12, 3]
TDO:ENABLE.O[0, 8, 5]
TDO:ENABLE.T[0, 7, 5]
Inverted~[0]
INT:MUX.LONG.IO.V1[0, 10, 4][0, 5, 3][0, 7, 3][0, 6, 3]
0.LONG.H10001
0.LONG.IO.H30010
0.LONG.IO.H10111
NONE1111
INT:MUX.LONG.H1[0, 10, 2][0, 6, 2][0, 9, 2][0, 7, 2]
0.LONG.IO.V10001
0.DEC.V20010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.IO.DBUF.H0[0, 7, 4][0, 11, 4][0, 8, 4][0, 9, 4]
0.IO.DOUBLE.0.E.20011
0.IO.DOUBLE.2.E.20101
0.IO.DOUBLE.3.E.20110
0.IO.DOUBLE.1.E.21111
INT:MUX.LONG.IO.H3[0, 36, 5][0, 27, 4][0, 44, 2][0, 42, 2][0, 10, 5][0, 11, 5]
0.LONG.V5001111
0.SINGLE.V6011111
0.LONG.V9110011
0.GCLK7110111
0.LONG.IO.V1111100
0.LONG.IO.V3111101
NONE111111
INT:MUX.LONG.IO.V3[0, 17, 4][0, 12, 4]
0.LONG.IO.H100
0.LONG.IO.H301
NONE11
READCLK:READ_CLK[0, 12, 5]
RDBK0
CCLK1
INT:MUX.LONG.IO.H1[0, 34, 5][0, 31, 5][0, 33, 5][0, 32, 5][0, 45, 3][0, 43, 3][0, 14, 5][0, 13, 5]
0.LONG.V100011111
0.LONG.V300101111
0.SINGLE.V201111111
0.LONG.V711110011
0.GCLK511110111
0.LONG.IO.V311111100
0.LONG.IO.V111111101
NONE11111111
INT:MUX.LONG.IO.V2[0, 23, 4][0, 13, 3][0, 16, 3][0, 14, 3]
0.LONG.H20001
0.LONG.IO.H00010
0.LONG.IO.H20111
NONE1111
INT:MUX.IMUX.BUFG.V[0, 16, 2][0, 17, 2][0, 18, 2][0, 20, 2][0, 19, 2][0, 15, 2]
0.IO.OCTAL.N.7000111
0.LONG.IO.H0001011
0.LONG.IO.V0001101
0.IO.OCTAL.N.0011111
0.OUT.IOB.CLKIN.N101110
NONE101111
INT:MUX.LONG.IO.V0[0, 21, 4][0, 15, 4][0, 15, 3][0, 16, 4]
0.LONG.H00001
0.LONG.IO.H20010
0.LONG.IO.H00111
NONE1111
TDO:PULL[0, 18, 5][0, 16, 5]
PULLUP01
PULLDOWN10
PULLNONE11
BSCAN:ENABLE[0, 17, 5]
Non-inverted[0]
INT:MUX.LONG.H0[0, 18, 3][0, 19, 3][0, 21, 2][0, 20, 3]
0.LONG.IO.V00001
0.DEC.V30010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.LONG.IO.H2[0, 37, 5][0, 35, 5][0, 39, 5][0, 38, 5][0, 48, 2][0, 49, 2][0, 19, 5][0, 20, 5]
0.LONG.V200011111
0.LONG.V400101111
0.SINGLE.V501111111
0.LONG.V811110011
0.GCLK611110111
0.LONG.IO.V011111100
0.LONG.IO.V211111101
NONE11111111
INT:MUX.IMUX.BUFG.H[0, 22, 7][0, 21, 5][0, 26, 7][0, 26, 6][0, 21, 7][0, 26, 5][0, 20, 6]
0.IO.DOUBLE.2.E.10001011
0.IO.DOUBLE.0.E.10001111
0.IO.DOUBLE.3.E.20010011
0.IO.DOUBLE.0.E.20010111
0.IO.DOUBLE.3.E.10011001
0.IO.DOUBLE.1.E.20011101
0.IO.DOUBLE.1.E.10111011
0.IO.DOUBLE.2.E.20111111
0.OUT.IOB.CLKIN.E1011110
NONE1011111
INT:MUX.LONG.H2[0, 21, 3][0, 22, 2]
0.LONG.IO.V200
0.DEC.V101
NONE11
INT:MUX.LONG.IO.H0[0, 30, 5][0, 29, 5][0, 48, 3][0, 49, 3][0, 23, 5][0, 22, 5]
0.LONG.V0001111
0.SINGLE.V1011111
0.LONG.V6110011
0.GCLK4110111
0.LONG.IO.V2111100
0.LONG.IO.V0111101
NONE111111
INT:MUX.LONG.V4[0, 25, 3][0, 22, 3][0, 23, 3][0, 24, 3]
0.LONG.IO.H20001
0.DEC.H10010
0.OUT.OSC.MUX10111
NONE1111
INT:MUX.LONG.V0[0, 20, 4][0, 22, 4][0, 24, 4][0, 25, 4]
0.LONG.IO.H00001
0.DEC.H30010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.LONG.V2[0, 29, 3][0, 25, 2][0, 28, 3][0, 27, 2]
0.LONG.IO.H20001
0.DEC.H10010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.IMUX.TDO.O[0, 31, 3][0, 32, 3][0, 33, 3][0, 34, 3][0, 35, 3][0, 30, 3]
0.LONG.H0001110
0.SINGLE.V2001111
0.SINGLE.V3010111
0.LONG.H1011010
0.SINGLE.V4011011
0.LONG.H2011100
0.SINGLE.V5011101
1.DOUBLE.H1.1111110
1.DOUBLE.H0.0111111
INT:MUX.IMUX.TDO.T[0, 29, 2][0, 30, 2][0, 32, 2][0, 33, 2][0, 34, 2][0, 31, 2]
1.SINGLE.H3000111
0.LONG.V4001011
1.SINGLE.H2001101
0.DOUBLE.V0.0011111
0.DOUBLE.V1.1100111
0.LONG.V3101011
0.LONG.V5101101
1.SINGLE.H4101110
1.SINGLE.H5111111
INT:MUX.LONG.V5[0, 36, 4][0, 32, 4][0, 34, 4][0, 33, 4]
0.LONG.IO.H30001
0.DEC.H00010
0.OUT.OSC.MUX10111
NONE1111
INT:MUX.LONG.V3[0, 36, 3][0, 35, 2][0, 36, 2][0, 37, 3]
0.LONG.IO.H10001
0.DEC.H20010
0.OUT.OSC.MUX10111
NONE1111
INT:MUX.LONG.V1[0, 39, 3][0, 38, 2][0, 38, 3][0, 40, 3]
0.LONG.IO.H10001
0.DEC.H20010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.IO.DBUF.H1[0, 39, 6][0, 40, 6][0, 39, 7][0, 40, 7]
0.IO.DOUBLE.1.N.00011
0.IO.DOUBLE.2.N.00101
0.IO.DOUBLE.3.N.00110
0.IO.DOUBLE.0.N.01111
INT:MUX.ECLK.H[0, 42, 5][0, 43, 5][0, 44, 5][0, 45, 4][0, 42, 4][0, 44, 4][0, 43, 4]
0.LONG.IO.H10011001
0.GCLK50011010
0.SINGLE.V30011111
0.OUT.BUFGE.V0101001
0.GCLK60101010
0.SINGLE.V40101111
0.LONG.IO.H30110001
0.GCLK70110010
0.SINGLE.V50110111
0.LONG.IO.H01111001
0.GCLK41111010
0.SINGLE.V21111111
INT:MUX.VCLK[0, 47, 8][0, 49, 6][0, 48, 7][0, 47, 7][0, 49, 7][0, 50, 7][0, 51, 7]
0.LONG.IO.H00011001
0.LONG.IO.H10011010
0.IO.DOUBLE.0.N.00011111
NONE0101001
0.OUT.BT.IOB1.I1.E0101010
0.IO.DOUBLE.1.E.10101111
0.OUT.TOP.COUT.E0110001
0.LONG.IO.H30110010
0.IO.DOUBLE.2.E.10110111
0.ECLK.H1111001
0.BUFGE.H1111010
0.IO.DOUBLE.3.N.01111111