Corners

CNR.BL

CNR.BL bittile 0
Row	Column
	0	1	2	3	4	5	6
0	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-
2	-	-	MISC:SCAN_TEST[1]	-	-	-	-
3	-	-	MISC:SCAN_TEST[0]	-	-	-	-
4	MISC:SCAN_TEST[2]	~MISC:READ_ABORT	~MISC:READ_CAPTURE	-	-	-	-
5	-	-	-	-	-	-	-
6	-	RDBK:READ_CLK	-	-	-	-	-
7	-	-	-	-	-	-	-
8	~INT:PASS.LONG.H6.LONG.V6	~INT:PASS.LONG.H7.LONG.V7	-	-	-	-	-
9	-	~INT:PASS.LONG.H5.LONG.V5	-	-	-	-	-
10	~INT:PASS.LONG.H3.LONG.V3	-	-	-	-	-	-
11	~INT:PASS.LONG.H4.LONG.V4	~INT:PASS.LONG.H0.LONG.V0	-	-	-	-	-
12	-	-	-	-	-	-	-
13	-	~INT:PASS.LONG.H1.LONG.V1	-	-	-	-	-
14	~INT:PASS.LONG.H0.OUT.RDBK.RIP	~INT:PASS.LONG.H2.LONG.V2	INT:MUX.IMUX.BUFG[0]	-	-	-	-
15	-	~INT:PASS.LONG.H1.OUT.RDBK.RIP	INT:MUX.IMUX.BUFG[1]	-	-	-	-
16	~INT:PASS.IO.SINGLE.L.N1.OUT.RDBK.RIP	~INT:PASS.IO.SINGLE.L.N0.OUT.RDBK.RIP	INT:MUX.IMUX.BUFG[2]	-	-	-	-
17	-	-	INT:MUX.IMUX.BUFG[3]	-	-	-	-
18	~INT:PASS.LONG.H2.OUT.RDBK.RIP	~INT:PASS.LONG.H3.OUT.RDBK.RIP	INT:MUX.IMUX.BUFG[4]	-	-	-	-
19	-	-	-	-	-	-	-
20	~INT:PASS.IO.SINGLE.L.N3.OUT.RDBK.RIP	~INT:PASS.IO.SINGLE.L.N2.OUT.RDBK.RIP	-	-	-	-	-
21	-	-	-	-	-	-	-
22	~INT:PASS.LONG.H4.OUT.RDBK.DATA	~INT:PASS.LONG.H5.OUT.RDBK.DATA	-	-	-	-	-
23	-	~INT:PASS.IO.SINGLE.L.N4.OUT.RDBK.DATA	INT:MUX.IMUX.RDBK.RCLK[0]	-	-	-	-
24	~INT:PASS.IO.SINGLE.L.N5.OUT.RDBK.DATA	~INT:PASS.LONG.H7.OUT.RDBK.DATA	INT:MUX.IMUX.RDBK.RCLK[2]	-	-	-	-
25	-	-	INT:MUX.IMUX.RDBK.RCLK[1]	-	-	-	-
26	~INT:PASS.LONG.H6.OUT.RDBK.DATA	~INT:PASS.IO.SINGLE.L.N6.OUT.RDBK.DATA	INT:MUX.IMUX.RDBK.TRIG[0]	-	-	INT:MUX.IMUX.BUFG[7]	INT:MUX.IMUX.BUFG[6]
27	~INT:PASS.IO.SINGLE.L.N7.OUT.RDBK.DATA	INT:MUX.IMUX.RDBK.TRIG[1]	INT:MUX.IMUX.RDBK.TRIG[2]	-	-	INT:MUX.IMUX.BUFG[8]	INT:MUX.IMUX.BUFG[5]

INT:PASS.IO.SINGLE.L.N0.OUT.RDBK.RIP	[0, 1, 16]
INT:PASS.IO.SINGLE.L.N1.OUT.RDBK.RIP	[0, 0, 16]
INT:PASS.IO.SINGLE.L.N2.OUT.RDBK.RIP	[0, 1, 20]
INT:PASS.IO.SINGLE.L.N3.OUT.RDBK.RIP	[0, 0, 20]
INT:PASS.IO.SINGLE.L.N4.OUT.RDBK.DATA	[0, 1, 23]
INT:PASS.IO.SINGLE.L.N5.OUT.RDBK.DATA	[0, 0, 24]
INT:PASS.IO.SINGLE.L.N6.OUT.RDBK.DATA	[0, 1, 26]
INT:PASS.IO.SINGLE.L.N7.OUT.RDBK.DATA	[0, 0, 27]
INT:PASS.LONG.H0.LONG.V0	[0, 1, 11]
INT:PASS.LONG.H0.OUT.RDBK.RIP	[0, 0, 14]
INT:PASS.LONG.H1.LONG.V1	[0, 1, 13]
INT:PASS.LONG.H1.OUT.RDBK.RIP	[0, 1, 15]
INT:PASS.LONG.H2.LONG.V2	[0, 1, 14]
INT:PASS.LONG.H2.OUT.RDBK.RIP	[0, 0, 18]
INT:PASS.LONG.H3.LONG.V3	[0, 0, 10]
INT:PASS.LONG.H3.OUT.RDBK.RIP	[0, 1, 18]
INT:PASS.LONG.H4.LONG.V4	[0, 0, 11]
INT:PASS.LONG.H4.OUT.RDBK.DATA	[0, 0, 22]
INT:PASS.LONG.H5.LONG.V5	[0, 1, 9]
INT:PASS.LONG.H5.OUT.RDBK.DATA	[0, 1, 22]
INT:PASS.LONG.H6.LONG.V6	[0, 0, 8]
INT:PASS.LONG.H6.OUT.RDBK.DATA	[0, 0, 26]
INT:PASS.LONG.H7.LONG.V7	[0, 1, 8]
INT:PASS.LONG.H7.OUT.RDBK.DATA	[0, 1, 24]
MISC:READ_ABORT	[0, 1, 4]
MISC:READ_CAPTURE	[0, 2, 4]
Inverted	~[0]

RDBK:READ_CLK	[0, 1, 6]
RDBK	0
CCLK	1

MISC:SCAN_TEST	[0, 0, 4]	[0, 2, 2]	[0, 2, 3]
ENABLE	0	1	1
ENLL	1	0	1
NE7	1	1	0
DISABLE	1	1	1

INT:MUX.IMUX.BUFG	[0, 5, 27]	[0, 5, 26]	[0, 6, 26]	[0, 6, 27]	[0, 2, 18]	[0, 2, 17]	[0, 2, 16]	[0, 2, 15]	[0, 2, 14]
IO.SINGLE.L.N0	0	1	1	1	1	1	1	1	1
IO.SINGLE.L.N1	1	0	1	1	1	1	1	1	1
IO.SINGLE.L.N2	1	1	0	1	1	1	1	1	1
IO.SINGLE.L.N3	1	1	1	0	1	1	1	1	1
LONG.V4	1	1	1	1	0	1	1	1	1
LONG.V5	1	1	1	1	1	0	1	1	1
LONG.V6	1	1	1	1	1	1	0	1	1
LONG.V7	1	1	1	1	1	1	1	0	1
OUT.CLKIOB	1	1	1	1	1	1	1	1	0
GND	1	1	1	1	1	1	1	1	1

INT:MUX.IMUX.RDBK.RCLK	[0, 2, 24]	[0, 2, 25]	[0, 2, 23]
LONG.H1	0	0	0
IO.SINGLE.L.N1	0	0	1
LONG.H0	0	1	0
IO.SINGLE.L.N0	0	1	1
LONG.H3	1	0	0
IO.SINGLE.L.N2	1	0	1
LONG.H2	1	1	0
IO.SINGLE.L.N3	1	1	1

INT:MUX.IMUX.RDBK.TRIG	[0, 2, 27]	[0, 1, 27]	[0, 2, 26]
LONG.H4	0	0	0
IO.SINGLE.L.N4	0	0	1
LONG.H5	0	1	0
IO.SINGLE.L.N5	0	1	1
LONG.H6	1	0	0
IO.SINGLE.L.N6	1	0	1
LONG.H7	1	1	0
GND	1	1	1

CNR.BR

CNR.BR bittile 0
Row	Column
	0	1	2	3	4	5	6
0	STARTUP:CRC	-	-	-	-	-	-
1	STARTUP:CONFIG_RATE[1]	-	-	-	-	-	-
2	STARTUP:CONFIG_RATE[0]	-	-	-	-	-	-
3	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-
11	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-
14	INT:MUX.IMUX.BUFG[5]	INT:MUX.IMUX.BUFG[8]	-	~INT:PASS.LONG.H0.LONG.V0	-	-	-
15	MISC:DONEPIN	INT:MUX.IMUX.BUFG[7]	-	-	-	-	-
16	MISC:PROGPIN	INT:MUX.IMUX.BUFG[6]	-	~INT:PASS.LONG.H1.LONG.V1	-	-	-
17	STARTUP:OUTPUTS_ACTIVE[1]	~STARTUP:SYNC_TO_DONE	-	-	-	-	-
18	STARTUP:GSR_INACTIVE[1]	STARTUP:OUTPUTS_ACTIVE[0]	-	~INT:PASS.LONG.H2.LONG.V2	OSC:OSC2_ATTR[2]	OSC:OSC2_ATTR[1]	OSC:OSC1_ATTR[1]
19	STARTUP:GSR_INACTIVE[0]	INT:MUX.IMUX.BUFG[4]	-	-	OSC:CMUX	OSC:OSC2_ATTR[0]	OSC:OSC1_ATTR[0]
20	~STARTUP:INV.GR	INT:MUX.IMUX.BUFG[3]	-	~INT:PASS.LONG.H3.LONG.V3	-	~INT:PASS.LONG.V0.OUT.STARTUP.DONEIN	~INT:PASS.LONG.V1.OUT.STARTUP.DONEIN
21	INT:MUX.IMUX.STARTUP.GTS[3]	INT:MUX.IMUX.BUFG[2]	-	-	-	~INT:PASS.IO.SINGLE.B.W0.OUT.STARTUP.DONEIN	~INT:PASS.IO.SINGLE.B.W1.OUT.STARTUP.DONEIN
22	~STARTUP:INV.GTS	INT:MUX.IMUX.BUFG[1]	-	~INT:PASS.LONG.H4.LONG.V4	INT:MUX.IMUX.STARTUP.GRST[2]	~INT:PASS.LONG.V2.OUT.STARTUP.Q3	~INT:PASS.LONG.V3.OUT.STARTUP.Q3
23	STARTUP:DONE_ACTIVE[1]	INT:MUX.IMUX.BUFG[0]	-	-	INT:MUX.IMUX.STARTUP.GRST[1]	~INT:PASS.IO.SINGLE.B.W2.OUT.STARTUP.Q3	~INT:PASS.IO.SINGLE.B.W3.OUT.STARTUP.Q3
24	STARTUP:DONE_ACTIVE[0]	-	-	~INT:PASS.LONG.H5.LONG.V5	INT:MUX.IMUX.STARTUP.GRST[0]	~INT:PASS.LONG.V4.OUT.STARTUP.Q2	~INT:PASS.LONG.V5.OUT.STARTUP.Q2
25	INT:MUX.IMUX.STARTUP.GRST[3]	INT:MUX.IMUX.STARTUP.SCLK[0]	-	-	INT:MUX.IMUX.STARTUP.GTS[2]	~INT:PASS.IO.SINGLE.B.W4.OUT.STARTUP.Q2	~INT:PASS.IO.SINGLE.B.W5.OUT.STARTUP.Q2
26	STARTUP:STARTUP_CLK	INT:MUX.IMUX.STARTUP.SCLK[1]	-	~INT:PASS.LONG.H6.LONG.V6	INT:MUX.IMUX.STARTUP.GTS[1]	~INT:PASS.LONG.V6.OUT.STARTUP.Q1Q4	~INT:PASS.LONG.V7.OUT.STARTUP.Q1Q4
27	~MISC:TCTEST	INT:MUX.IMUX.STARTUP.SCLK[2]	-	~INT:PASS.LONG.H7.LONG.V7	INT:MUX.IMUX.STARTUP.GTS[0]	~INT:PASS.IO.SINGLE.B.W6.OUT.STARTUP.Q1Q4	~INT:PASS.IO.SINGLE.B.W7.OUT.STARTUP.Q1Q4

STARTUP:CRC	[0, 0, 0]
Non-inverted	[0]

STARTUP:CONFIG_RATE	[0, 0, 1]	[0, 0, 2]
SLOW	0	0
MED	0	1
FAST	1	0

MISC:DONEPIN	[0, 0, 15]
MISC:PROGPIN	[0, 0, 16]
PULLNONE	0
PULLUP	1

STARTUP:GSR_INACTIVE	[0, 0, 18]	[0, 0, 19]
DONE_IN	0	0
Q1Q4	0	1
Q3	1	0
Q2	1	1

INT:PASS.IO.SINGLE.B.W0.OUT.STARTUP.DONEIN	[0, 5, 21]
INT:PASS.IO.SINGLE.B.W1.OUT.STARTUP.DONEIN	[0, 6, 21]
INT:PASS.IO.SINGLE.B.W2.OUT.STARTUP.Q3	[0, 5, 23]
INT:PASS.IO.SINGLE.B.W3.OUT.STARTUP.Q3	[0, 6, 23]
INT:PASS.IO.SINGLE.B.W4.OUT.STARTUP.Q2	[0, 5, 25]
INT:PASS.IO.SINGLE.B.W5.OUT.STARTUP.Q2	[0, 6, 25]
INT:PASS.IO.SINGLE.B.W6.OUT.STARTUP.Q1Q4	[0, 5, 27]
INT:PASS.IO.SINGLE.B.W7.OUT.STARTUP.Q1Q4	[0, 6, 27]
INT:PASS.LONG.H0.LONG.V0	[0, 3, 14]
INT:PASS.LONG.H1.LONG.V1	[0, 3, 16]
INT:PASS.LONG.H2.LONG.V2	[0, 3, 18]
INT:PASS.LONG.H3.LONG.V3	[0, 3, 20]
INT:PASS.LONG.H4.LONG.V4	[0, 3, 22]
INT:PASS.LONG.H5.LONG.V5	[0, 3, 24]
INT:PASS.LONG.H6.LONG.V6	[0, 3, 26]
INT:PASS.LONG.H7.LONG.V7	[0, 3, 27]
INT:PASS.LONG.V0.OUT.STARTUP.DONEIN	[0, 5, 20]
INT:PASS.LONG.V1.OUT.STARTUP.DONEIN	[0, 6, 20]
INT:PASS.LONG.V2.OUT.STARTUP.Q3	[0, 5, 22]
INT:PASS.LONG.V3.OUT.STARTUP.Q3	[0, 6, 22]
INT:PASS.LONG.V4.OUT.STARTUP.Q2	[0, 5, 24]
INT:PASS.LONG.V5.OUT.STARTUP.Q2	[0, 6, 24]
INT:PASS.LONG.V6.OUT.STARTUP.Q1Q4	[0, 5, 26]
INT:PASS.LONG.V7.OUT.STARTUP.Q1Q4	[0, 6, 26]
MISC:TCTEST	[0, 0, 27]
STARTUP:INV.GR	[0, 0, 20]
STARTUP:INV.GTS	[0, 0, 22]
STARTUP:SYNC_TO_DONE	[0, 1, 17]
Inverted	~[0]

STARTUP:DONE_ACTIVE	[0, 0, 23]	[0, 0, 24]
Q1Q4	0	0
Q2	0	1
Q3	1	0
Q0	1	1

STARTUP:STARTUP_CLK	[0, 0, 26]
USERCLK	0
CCLK	1

STARTUP:OUTPUTS_ACTIVE	[0, 0, 17]	[0, 1, 18]
DONE_IN	0	0
Q3	0	1
Q2	1	0
Q1Q4	1	1

INT:MUX.IMUX.BUFG	[0, 1, 14]	[0, 1, 15]	[0, 1, 16]	[0, 0, 14]	[0, 1, 19]	[0, 1, 20]	[0, 1, 21]	[0, 1, 22]	[0, 1, 23]
IO.SINGLE.B.W0	0	1	1	1	1	1	1	1	1
IO.SINGLE.B.W1	1	0	1	1	1	1	1	1	1
IO.SINGLE.B.W2	1	1	0	1	1	1	1	1	1
IO.SINGLE.B.W3	1	1	1	0	1	1	1	1	1
LONG.H4	1	1	1	1	0	1	1	1	1
LONG.H5	1	1	1	1	1	0	1	1	1
LONG.H6	1	1	1	1	1	1	0	1	1
LONG.H7	1	1	1	1	1	1	1	0	1
OUT.CLKIOB	1	1	1	1	1	1	1	1	0
GND	1	1	1	1	1	1	1	1	1

INT:MUX.IMUX.STARTUP.SCLK	[0, 1, 27]	[0, 1, 26]	[0, 1, 25]
LONG.V0	0	0	0
LONG.V1	0	0	1
LONG.V2	0	1	0
LONG.V3	0	1	1
LONG.V4	1	0	0
LONG.V5	1	0	1
LONG.V6	1	1	0
LONG.V7	1	1	1

OSC:CMUX	[0, 4, 19]
CCLK	0
USERCLK	1

INT:MUX.IMUX.STARTUP.GRST	[0, 0, 25]	[0, 4, 22]	[0, 4, 23]	[0, 4, 24]
IO.SINGLE.B.W4	0	0	0	0
IO.SINGLE.B.W5	0	0	0	1
IO.SINGLE.B.W6	0	0	1	0
IO.SINGLE.B.W7	0	0	1	1
LONG.V4	0	1	0	0
LONG.V5	0	1	0	1
LONG.V6	0	1	1	0
LONG.V7	0	1	1	1
NONE	1	1	1	1

INT:MUX.IMUX.STARTUP.GTS	[0, 0, 21]	[0, 4, 25]	[0, 4, 26]	[0, 4, 27]
LONG.V3	0	0	0	0
IO.SINGLE.B.W3	0	0	0	1
LONG.V1	0	0	1	0
IO.SINGLE.B.W1	0	0	1	1
LONG.V2	0	1	0	0
IO.SINGLE.B.W2	0	1	0	1
LONG.V0	0	1	1	0
IO.SINGLE.B.W0	0	1	1	1
NONE	1	1	1	1

OSC:OSC2_ATTR	[0, 4, 18]	[0, 5, 18]	[0, 5, 19]
128	0	0	0
32	0	0	1
8	0	1	0
2	0	1	1
65536	1	0	0
16384	1	0	1
4096	1	1	0
1024	1	1	1

OSC:OSC1_ATTR	[0, 6, 18]	[0, 6, 19]
256	0	0
64	0	1
16	1	0
4	1	1

CNR.TL

CNR.TL bittile 0
Row	Column
	0	1	2	3	4	5
0	~INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.RESET	~INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.IDLE	~INT:PASS.LONG.V7.OUT.BSCAN.IDLE	~INT:PASS.LONG.H7.LONG.V7	-	INT:MUX.IMUX.BSCAN.TDO1[0]
1	~INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.IDLE	~INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.RESET	~INT:PASS.LONG.V7.OUT.BSCAN.RESET	~INT:PASS.LONG.H6.LONG.V6	-	INT:MUX.IMUX.BSCAN.TDO1[1]
2	~INT:PASS.IO.SINGLE.T.E5.OUT.BSCAN.UPDATE	~INT:PASS.IO.SINGLE.T.E4.OUT.BSCAN.UPDATE	~INT:PASS.LONG.V6.OUT.BSCAN.RESET	-	-	INT:MUX.IMUX.BSCAN.TDO2[0]
3	~INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SHIFT	~INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SEL1	~INT:PASS.LONG.V6.OUT.BSCAN.IDLE	~INT:PASS.LONG.H5.LONG.V5	-	INT:MUX.IMUX.BSCAN.TDO2[1]
4	~INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SEL1	~INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SHIFT	~INT:PASS.LONG.V5.OUT.BSCAN.UPDATE	-	-	INT:MUX.IMUX.BUFG[0]
5	~INT:PASS.LONG.V1.OUT.BSCAN.SEL2	~INT:PASS.LONG.V1.OUT.BSCAN.DRCK	~INT:PASS.LONG.V4.OUT.BSCAN.UPDATE	~INT:PASS.LONG.H4.LONG.V4	-	INT:MUX.IMUX.BUFG[4]
6	~INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.DRCK	~INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.SEL2	~INT:PASS.LONG.V3.OUT.BSCAN.SEL1	-	-	INT:MUX.IMUX.BUFG[3]
7	~INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.SEL2	~INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.DRCK	~INT:PASS.LONG.V3.OUT.BSCAN.SHIFT	~INT:PASS.LONG.H3.LONG.V3	-	INT:MUX.IMUX.BUFG[2]
8	~INT:PASS.LONG.V0.OUT.BSCAN.DRCK	~INT:PASS.LONG.V0.OUT.BSCAN.SEL2	~INT:PASS.LONG.V2.OUT.BSCAN.SHIFT	-	-	INT:MUX.IMUX.BUFG[1]
9	~BSCAN:ENABLE	-	~INT:PASS.LONG.V2.OUT.BSCAN.SEL1	~INT:PASS.LONG.H2.LONG.V2	-	~MISC:BS_RECONFIG
10	-	-	-	-	-	MISC:INPUT
11	-	-	-	~INT:PASS.LONG.H1.LONG.V1	-	INT:MUX.IMUX.BUFG[8]
12	-	-	-	-	-	INT:MUX.IMUX.BUFG[7]
13	-	-	-	~INT:PASS.LONG.H0.LONG.V0	-	INT:MUX.IMUX.BUFG[6]
14	-	-	-	-	-	-
15	-	-	-	~MISC:BS_READBACK	-	INT:MUX.IMUX.BUFG[5]

BSCAN:ENABLE	[0, 0, 9]
INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.DRCK	[0, 1, 7]
INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.SEL2	[0, 0, 7]
INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.DRCK	[0, 0, 6]
INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.SEL2	[0, 1, 6]
INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SEL1	[0, 0, 4]
INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SHIFT	[0, 1, 4]
INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SEL1	[0, 1, 3]
INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SHIFT	[0, 0, 3]
INT:PASS.IO.SINGLE.T.E4.OUT.BSCAN.UPDATE	[0, 1, 2]
INT:PASS.IO.SINGLE.T.E5.OUT.BSCAN.UPDATE	[0, 0, 2]
INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.IDLE	[0, 0, 1]
INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.RESET	[0, 1, 1]
INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.IDLE	[0, 1, 0]
INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.RESET	[0, 0, 0]
INT:PASS.LONG.H0.LONG.V0	[0, 3, 13]
INT:PASS.LONG.H1.LONG.V1	[0, 3, 11]
INT:PASS.LONG.H2.LONG.V2	[0, 3, 9]
INT:PASS.LONG.H3.LONG.V3	[0, 3, 7]
INT:PASS.LONG.H4.LONG.V4	[0, 3, 5]
INT:PASS.LONG.H5.LONG.V5	[0, 3, 3]
INT:PASS.LONG.H6.LONG.V6	[0, 3, 1]
INT:PASS.LONG.H7.LONG.V7	[0, 3, 0]
INT:PASS.LONG.V0.OUT.BSCAN.DRCK	[0, 0, 8]
INT:PASS.LONG.V0.OUT.BSCAN.SEL2	[0, 1, 8]
INT:PASS.LONG.V1.OUT.BSCAN.DRCK	[0, 1, 5]
INT:PASS.LONG.V1.OUT.BSCAN.SEL2	[0, 0, 5]
INT:PASS.LONG.V2.OUT.BSCAN.SEL1	[0, 2, 9]
INT:PASS.LONG.V2.OUT.BSCAN.SHIFT	[0, 2, 8]
INT:PASS.LONG.V3.OUT.BSCAN.SEL1	[0, 2, 6]
INT:PASS.LONG.V3.OUT.BSCAN.SHIFT	[0, 2, 7]
INT:PASS.LONG.V4.OUT.BSCAN.UPDATE	[0, 2, 5]
INT:PASS.LONG.V5.OUT.BSCAN.UPDATE	[0, 2, 4]
INT:PASS.LONG.V6.OUT.BSCAN.IDLE	[0, 2, 3]
INT:PASS.LONG.V6.OUT.BSCAN.RESET	[0, 2, 2]
INT:PASS.LONG.V7.OUT.BSCAN.IDLE	[0, 2, 0]
INT:PASS.LONG.V7.OUT.BSCAN.RESET	[0, 2, 1]
MISC:BS_READBACK	[0, 3, 15]
MISC:BS_RECONFIG	[0, 5, 9]
Inverted	~[0]

INT:MUX.IMUX.BSCAN.TDO1	[0, 5, 1]	[0, 5, 0]
IO.SINGLE.T.E7	0	0
IO.SINGLE.T.E6	0	1
LONG.V7	1	0
LONG.V6	1	1

INT:MUX.IMUX.BSCAN.TDO2	[0, 5, 3]	[0, 5, 2]
IO.SINGLE.T.E5	0	0
IO.SINGLE.T.E4	0	1
LONG.V5	1	0
LONG.V4	1	1

INT:MUX.IMUX.BUFG	[0, 5, 11]	[0, 5, 12]	[0, 5, 13]	[0, 5, 15]	[0, 5, 5]	[0, 5, 6]	[0, 5, 7]	[0, 5, 8]	[0, 5, 4]
IO.SINGLE.T.E0	0	1	1	1	1	1	1	1	1
IO.SINGLE.T.E1	1	0	1	1	1	1	1	1	1
IO.SINGLE.T.E2	1	1	0	1	1	1	1	1	1
IO.SINGLE.T.E3	1	1	1	0	1	1	1	1	1
LONG.H4	1	1	1	1	0	1	1	1	1
LONG.H5	1	1	1	1	1	0	1	1	1
LONG.H6	1	1	1	1	1	1	0	1	1
LONG.H7	1	1	1	1	1	1	1	0	1
OUT.CLKIOB	1	1	1	1	1	1	1	1	0
GND	1	1	1	1	1	1	1	1	1

MISC:INPUT	[0, 5, 10]
CMOS	0
TTL	1

CNR.TR

CNR.TR bittile 0
Row	Column
	0	1	2	3	4	5	6
0	-	~INT:PASS.LONG.H7.LONG.V7	-	INT:MUX.IMUX.BUFG[1]	~INT:PASS.LONG.H7.OUT.OSC.OSC2	~INT:PASS.IO.SINGLE.R.S6.OUT.OSC.OSC2	~INT:PASS.IO.SINGLE.R.S7.OUT.OSC.OSC2
1	-	~INT:PASS.LONG.H6.LONG.V6	-	INT:MUX.IMUX.BUFG[2]	~INT:PASS.LONG.H6.OUT.OSC.OSC2	~INT:PASS.IO.SINGLE.R.S5.OUT.OSC.OSC1	~INT:PASS.IO.SINGLE.R.S4.OUT.OSC.OSC1
2	-	~INT:PASS.LONG.H5.LONG.V5	-	INT:MUX.IMUX.BUFG[3]	~INT:PASS.LONG.H5.OUT.OSC.OSC1	INT:MUX.IMUX.BYPOSC.PUMP[1]	INT:MUX.IMUX.OSC.OCLK[1]
3	-	~INT:PASS.LONG.H4.LONG.V4	-	INT:MUX.IMUX.BUFG[4]	~INT:PASS.LONG.H4.OUT.OSC.OSC1	INT:MUX.IMUX.BYPOSC.PUMP[0]	INT:MUX.IMUX.OSC.OCLK[2]
4	-	~INT:PASS.LONG.H3.LONG.V3	-	INT:MUX.IMUX.BUFG[0]	~INT:PASS.LONG.H3.OUT.BSUPD	INT:MUX.IMUX.BYPOSC.PUMP[3]	INT:MUX.IMUX.OSC.OCLK[3]
5	-	~INT:PASS.LONG.H2.LONG.V2	-	-	~INT:PASS.LONG.H2.OUT.BSUPD	INT:MUX.IMUX.BYPOSC.PUMP[2]	INT:MUX.IMUX.OSC.OCLK[4]
6	-	~INT:PASS.LONG.H1.LONG.V1	-	-	~INT:PASS.IO.SINGLE.R.S3.OUT.BSUPD	-	INT:MUX.IMUX.OSC.OCLK[0]
7	-	~INT:PASS.LONG.H0.LONG.V0	-	-	~INT:PASS.IO.SINGLE.R.S2.OUT.BSUPD	-	-
8	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-
10	~MISC:TAC	INT:MUX.IMUX.BUFG[5]	-	INT:MUX.IMUX.BUFG[8]	-	-	-
11	~MISC:TLC	INT:MUX.IMUX.BUFG[6]	-	INT:MUX.IMUX.BUFG[7]	-	-	-

INT:PASS.IO.SINGLE.R.S2.OUT.BSUPD	[0, 4, 7]
INT:PASS.IO.SINGLE.R.S3.OUT.BSUPD	[0, 4, 6]
INT:PASS.IO.SINGLE.R.S4.OUT.OSC.OSC1	[0, 6, 1]
INT:PASS.IO.SINGLE.R.S5.OUT.OSC.OSC1	[0, 5, 1]
INT:PASS.IO.SINGLE.R.S6.OUT.OSC.OSC2	[0, 5, 0]
INT:PASS.IO.SINGLE.R.S7.OUT.OSC.OSC2	[0, 6, 0]
INT:PASS.LONG.H0.LONG.V0	[0, 1, 7]
INT:PASS.LONG.H1.LONG.V1	[0, 1, 6]
INT:PASS.LONG.H2.LONG.V2	[0, 1, 5]
INT:PASS.LONG.H2.OUT.BSUPD	[0, 4, 5]
INT:PASS.LONG.H3.LONG.V3	[0, 1, 4]
INT:PASS.LONG.H3.OUT.BSUPD	[0, 4, 4]
INT:PASS.LONG.H4.LONG.V4	[0, 1, 3]
INT:PASS.LONG.H4.OUT.OSC.OSC1	[0, 4, 3]
INT:PASS.LONG.H5.LONG.V5	[0, 1, 2]
INT:PASS.LONG.H5.OUT.OSC.OSC1	[0, 4, 2]
INT:PASS.LONG.H6.LONG.V6	[0, 1, 1]
INT:PASS.LONG.H6.OUT.OSC.OSC2	[0, 4, 1]
INT:PASS.LONG.H7.LONG.V7	[0, 1, 0]
INT:PASS.LONG.H7.OUT.OSC.OSC2	[0, 4, 0]
MISC:TAC	[0, 0, 10]
MISC:TLC	[0, 0, 11]
Inverted	~[0]

INT:MUX.IMUX.BUFG	[0, 3, 10]	[0, 3, 11]	[0, 1, 11]	[0, 1, 10]	[0, 3, 3]	[0, 3, 2]	[0, 3, 1]	[0, 3, 0]	[0, 3, 4]
IO.SINGLE.R.S0	0	1	1	1	1	1	1	1	1
IO.SINGLE.R.S1	1	0	1	1	1	1	1	1	1
IO.SINGLE.R.S2	1	1	0	1	1	1	1	1	1
IO.SINGLE.R.S3	1	1	1	0	1	1	1	1	1
LONG.V4	1	1	1	1	0	1	1	1	1
LONG.V5	1	1	1	1	1	0	1	1	1
LONG.V6	1	1	1	1	1	1	0	1	1
LONG.V7	1	1	1	1	1	1	1	0	1
OUT.CLKIOB	1	1	1	1	1	1	1	1	0
GND	1	1	1	1	1	1	1	1	1

INT:MUX.IMUX.BYPOSC.PUMP	[0, 5, 4]	[0, 5, 5]	[0, 5, 2]	[0, 5, 3]
IO.SINGLE.R.S4	0	1	1	1
IO.SINGLE.R.S5	1	0	1	1
LONG.H4	1	1	0	1
LONG.V3	1	1	1	0
NONE	1	1	1	1

INT:MUX.IMUX.OSC.OCLK	[0, 6, 5]	[0, 6, 4]	[0, 6, 3]	[0, 6, 2]	[0, 6, 6]
LONG.H0	0	1	1	1	0
IO.SINGLE.R.S0	0	1	1	1	1
LONG.H1	1	0	1	1	0
IO.SINGLE.R.S1	1	0	1	1	1
LONG.H2	1	1	0	1	0
IO.SINGLE.R.S2	1	1	0	1	1
LONG.H3	1	1	1	0	0
IO.SINGLE.R.S3	1	1	1	0	1
GND	1	1	1	1	1