Input/Output

I/O banks and special functions

Virtex 4 devices have exactly three I/O columns:

the left I/O column, containing only IO tiles; if the device has no transceivers, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column
the center column, part of which contains IO tiles; the IO tiles in this column come in two segments:
- the lower segment, between lower DCMs/CCMs and the configuration center
- the upper segment, between the configuration center and the upper DCMs/CCMs
the right I/O column, containing only IO tiles; if the device has no transceivers, it is the rightmost column of the device; otherwise, it is somewhat to the left of the right GT column

Virtex 4 has the following banks:

bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:
- CCLK
- CS_B
- DONE
- DOUT_BUSY
- D_IN
- HSWAP_EN
- INIT
- M0
- M1
- M2
- PROGRAM_B
- PWRDWN_B
- RDWR_B
- TCK
- TDI
- TDO
- TMS
bank 0 is not associated with any IO tiles
banks 1-4 are central column banks, with no support for true differential output; they are:
- bank 1: right above configuration center; has 8, 24, or 40 I/O tiles
- bank 2: right below configuration center; has 8, 24, or 40 I/O tiles
- bank 3: above bank 1, below top DCMs/CCMs; always has 8 I/O tiles
- bank 4: below bank 2, above bottom DCMs/CCMs; always has 8 I/O tiles
banks 5-16: left and right column banks; the number of present banks in these column varies between devices, but each bank has a constant size of 32 I/O tiles (ie. is two regions high); the HCLK tile in bottom region of the bank contains DCI control circuitry, while the HCLK tile in top region of the bank contains contains LVDS output circuitry
- odd-numbered banks belong to the left column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
  - 4 regions: 7, 5
  - 6 regions: 7, 9, 5
  - 8 regions: 7, 11, 9, 5
  - 10 regions: 7, 11, 13, 9, 5
  - 12 regions: 7, 11, 15, 13, 9, 5
- even-numbered banks belong to the right column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
  - 4 regions: 8, 6
  - 6 regions: 8, 10, 6
  - 8 regions: 8, 12, 10, 6
  - 10 regions: 8, 12, 14, 10, 6
  - 12 regions: 8, 12, 16, 14, 10, 6

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input is supported on all pins of the device. True differential output is supported only in the left and right columns, in all tiles except for rows 7 and 8 of every region (ie. except the “clock-capable” pads).

IOB1 pads next to the HCLK row (that is, in row 7 and 8 of every clock region) are considered “clock-capable”. They can drive BUFIO and BUFR buffers via dedicated connections. While Xilinx documentation also considers IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

The 16 bottommost IOB1 pads and 16 topmost IOB1 pads in the central column are considered “global clock-capable”. They can drive BUFGCTRL buffers and DCM primitives via dedicated connections. Likewise, Xilinx considers IOB0 pads to be clock-capable, but they can only drive clocks as part of differential pair with IOB1.

The IOB0 in rows 4 and 12 of every region is capable of being used as a VREF pad.

Each bank, with some exceptions on the smaller devices, has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

bank 1, if the bank has 8 I/O tiles: DCI is not supported in this bank
bank 1, if the bank has 24 I/O tiles: row 14 of the bank (row 6 of the topmost region of the bank)
bank 1, if the bank has 40 I/O tiles: row 30 of the bank (row 6 of the topmost region of the bank)
bank 2, if the bank has 8 I/O tiles: DCI is not supported in this bank
bank 2, if the bank has 24 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
bank 2, if the bank has 40 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
bank 3: row 6 of the bank (row 6 of the region)
bank 4: row 1 of the bank (row 9 of the region)
banks 5-16: row 9 of the bank (row 9 of the bottom region of the bank)

In parallel configuration modes, some I/O pads in banks 1 and 2 are borrowed for configuration use, as the parallel data pins:

D[i], i % 2 == 0, 0 <= i < 16: IOB0 of row i / 2 of topmost region of bank 2
D[i], i % 2 == 1, 0 <= i < 16: IOB1 of row (i - 1) / 2 of topmost region of bank 2
D[i], i % 2 == 0, 16 <= i < 32: IOB0 of row i / 2 of bottom region of bank 1 (or, row (i - 16) / 2 of the bank)
D[i], i % 2 == 1, 16 <= i < 32: IOB1 of row (i - 1) / 2 of bottom region of bank 1 (or, row (i - 17) / 2 of the bank)

Every SYSMON present on the device can use up to seven IOB pairs from the left I/O column as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. The IOBs are in the following tiles, where r is the bottom row of the SYSMON:

VP1/VN1: left I/O column, row r
VP2/VN2: left I/O column, row r + 1
VP3/VN3: left I/O column, row r + 2
VP4/VN4: left I/O column, row r + 3
VP5/VN5: left I/O column, row r + 5
VP6/VN6: left I/O column, row r + 6
VP7/VN7: left I/O column, row r + 7

Row r + 4 is not used as SYSMON input — the “analog function” of that pin is considered to be VREF instead (they are controlled by the same bit).

Bitstream

Name	IOSTD:PDRIVE					IOSTD:NDRIVE
Name	[4]	[3]	[2]	[1]	[0]	[4]	[3]	[2]	[1]	[0]
BLVDS_25	1	1	1	1	1	1	1	1	0	0
GTL	0	0	0	0	0	1	0	0	1	0
GTLP	0	0	0	0	0	1	0	0	0	0
GTLP_DCI	0	0	0	0	0	1	0	0	0	0
GTL_DCI	0	0	0	0	0	1	0	0	1	0
HSTL_I	0	1	1	0	1	0	0	1	0	1
HSTL_II	1	1	0	1	0	0	1	0	0	1
HSTL_III	0	1	1	0	1	0	1	1	1	1
HSTL_III_18	0	1	1	0	0	1	0	0	0	1
HSTL_III_DCI	0	1	1	0	1	0	1	1	1	1
HSTL_III_DCI_18	0	1	1	0	0	1	0	0	0	1
HSTL_II_18	1	1	0	1	1	0	1	1	0	1
HSTL_II_DCI	1	1	0	1	0	0	1	0	0	1
HSTL_II_DCI_18	1	1	0	1	1	0	1	1	0	1
HSTL_II_T_DCI	0	1	1	0	1	0	0	1	0	1
HSTL_II_T_DCI_18	0	1	1	0	0	0	0	1	1	0
HSTL_IV	0	1	1	0	1	1	1	1	1	0
HSTL_IV_18	0	1	1	0	0	1	1	1	1	1
HSTL_IV_DCI	0	1	1	0	1	1	1	1	1	0
HSTL_IV_DCI_18	0	1	1	0	0	1	1	1	1	1
HSTL_I_12	1	0	1	0	1	0	0	1	0	0
HSTL_I_18	0	1	1	0	0	0	0	1	1	0
HSTL_I_DCI	0	1	1	0	1	0	0	1	0	1
HSTL_I_DCI_18	0	1	1	0	0	0	0	1	1	0
LVCMOS15.12	1	0	0	1	1	0	0	1	1	0
LVCMOS15.16	1	1	0	0	0	0	1	0	0	1
LVCMOS15.2	0	0	0	1	1	0	0	0	0	1
LVCMOS15.4	0	0	1	1	0	0	0	0	1	0
LVCMOS15.6	0	1	0	0	0	0	0	0	1	1
LVCMOS15.8	0	1	1	0	0	0	0	1	0	0
LVCMOS18.12	0	1	1	1	0	0	0	1	1	0
LVCMOS18.16	1	0	1	0	0	0	1	0	0	1
LVCMOS18.2	0	0	0	1	1	0	0	0	0	1
LVCMOS18.4	0	0	1	0	1	0	0	0	1	0
LVCMOS18.6	0	0	1	1	1	0	0	0	1	1
LVCMOS18.8	0	1	0	0	1	0	0	1	0	0
LVCMOS25.12	0	1	0	1	0	0	0	1	1	0
LVCMOS25.16	0	1	1	0	1	0	1	0	0	1
LVCMOS25.2	0	0	0	1	0	0	0	0	0	1
LVCMOS25.24	1	0	1	1	1	0	1	1	1	0
LVCMOS25.4	0	0	1	0	0	0	0	0	1	0
LVCMOS25.6	0	0	1	0	1	0	0	0	1	1
LVCMOS25.8	0	0	1	1	1	0	0	1	0	1
LVCMOS33.12	0	1	0	0	0	0	0	1	1	1
LVCMOS33.16	0	1	0	1	0	0	1	0	0	1
LVCMOS33.2	0	0	0	0	1	0	0	0	0	1
LVCMOS33.24	1	0	0	1	1	0	1	1	1	0
LVCMOS33.4	0	0	0	1	1	0	0	0	1	0
LVCMOS33.6	0	0	1	0	0	0	0	0	1	1
LVCMOS33.8	0	0	1	0	1	0	0	1	0	0
LVPECL_25	1	1	0	0	0	1	1	1	1	0
LVTTL.12	0	1	0	0	0	0	0	1	1	1
LVTTL.16	0	1	0	1	0	0	1	0	0	1
LVTTL.2	0	0	0	0	1	0	0	0	0	1
LVTTL.24	1	0	0	1	1	0	1	1	1	0
LVTTL.4	0	0	0	1	1	0	0	0	1	0
LVTTL.6	0	0	1	0	0	0	0	0	1	1
LVTTL.8	0	0	1	0	1	0	0	1	0	0
OFF	0	0	0	0	0	0	0	0	0	0
PCI33_3	0	1	0	0	1	0	1	1	0	1
PCI66_3	0	1	0	0	1	0	1	1	0	1
PCIX	0	1	1	0	0	0	1	1	0	0
SSTL18_I	0	1	0	0	0	0	0	1	0	0
SSTL18_II	1	1	0	0	1	0	1	0	1	1
SSTL18_II_DCI	0	1	1	0	1	0	0	1	1	0
SSTL18_II_T_DCI	0	0	1	1	1	0	0	0	1	1
SSTL18_I_DCI	0	0	1	1	1	0	0	0	1	1
SSTL2_I	0	0	1	1	0	0	0	1	0	0
SSTL2_II	1	0	0	1	1	0	1	0	1	0
SSTL2_II_DCI	0	1	0	0	0	0	0	1	1	0
SSTL2_II_T_DCI	0	0	1	0	1	0	0	0	1	1
SSTL2_I_DCI	0	0	1	0	1	0	0	0	1	1
VR	0	0	0	0	0	0	0	0	0	0
VREF	0	1	1	0	1	0	0	0	0	0

Name	IOSTD:PSLEW				IOSTD:NSLEW
Name	[3]	[2]	[1]	[0]	[3]	[2]	[1]	[0]
BLVDS_25	0	1	0	0	1	0	1	0
GTL	0	0	0	0	1	0	1	0
GTLP	0	0	0	0	1	1	0	0
GTLP_DCI	0	0	0	0	1	1	1	1
GTL_DCI	0	0	0	0	1	1	1	0
HSLVDCI_15	1	1	1	0	1	0	0	1
HSLVDCI_18	0	0	0	1	1	1	0	0
HSLVDCI_25	0	0	0	0	1	0	0	1
HSLVDCI_33	0	0	0	0	1	1	1	1
HSTL_I	1	1	1	1	1	0	0	1
HSTL_II	1	0	1	1	0	1	0	0
HSTL_III	0	0	1	1	0	1	1	0
HSTL_III_18	1	0	0	0	0	1	1	0
HSTL_III_DCI	0	0	1	1	0	1	1	0
HSTL_III_DCI_18	1	0	0	0	0	1	1	0
HSTL_II_18	0	0	1	1	0	1	1	0
HSTL_II_DCI	0	1	1	1	0	1	1	0
HSTL_II_DCI_18	0	0	1	1	0	1	1	0
HSTL_II_T_DCI	1	1	1	1	1	0	0	1
HSTL_II_T_DCI_18	0	1	1	1	1	0	0	1
HSTL_IV	0	0	1	1	1	0	1	0
HSTL_IV_18	0	0	1	1	1	0	0	0
HSTL_IV_DCI	0	0	1	1	1	0	0	0
HSTL_IV_DCI_18	0	0	1	1	1	0	0	0
HSTL_I_12	0	1	1	1	0	1	0	0
HSTL_I_18	0	1	1	1	1	0	0	1
HSTL_I_DCI	1	1	1	1	1	0	0	1
HSTL_I_DCI_18	0	1	1	1	1	0	0	1
LVCMOS15.12.FAST	0	1	1	1	1	1	1	1
LVCMOS15.12.SLOW	0	0	0	0	0	0	0	1
LVCMOS15.16.FAST	0	1	1	1	1	1	1	1
LVCMOS15.16.SLOW	0	0	0	0	0	0	0	1
LVCMOS15.2.FAST	0	1	1	1	1	1	1	1
LVCMOS15.2.SLOW	0	0	0	0	0	0	0	1
LVCMOS15.4.FAST	0	1	1	1	1	1	1	1
LVCMOS15.4.SLOW	0	0	0	0	0	0	0	1
LVCMOS15.6.FAST	0	1	1	1	1	1	1	1
LVCMOS15.6.SLOW	0	0	0	0	0	0	0	1
LVCMOS15.8.FAST	0	1	1	1	1	1	1	1
LVCMOS15.8.SLOW	0	0	0	0	0	0	0	1
LVCMOS18.12.FAST	0	1	1	1	1	1	1	1
LVCMOS18.12.SLOW	0	0	0	0	0	0	0	1
LVCMOS18.16.FAST	0	1	1	1	1	1	1	1
LVCMOS18.16.SLOW	0	0	0	0	0	0	0	1
LVCMOS18.2.FAST	0	1	1	1	1	1	1	1
LVCMOS18.2.SLOW	0	0	0	0	0	0	0	1
LVCMOS18.4.FAST	0	1	1	1	1	1	1	1
LVCMOS18.4.SLOW	0	0	0	1	0	0	0	1
LVCMOS18.6.FAST	0	1	1	1	1	1	1	1
LVCMOS18.6.SLOW	0	0	0	1	0	0	0	1
LVCMOS18.8.FAST	0	1	1	1	1	1	1	1
LVCMOS18.8.SLOW	0	0	0	0	0	0	1	0
LVCMOS25.12.FAST	0	1	1	1	1	1	1	1
LVCMOS25.12.SLOW	0	0	0	0	0	0	1	0
LVCMOS25.16.FAST	0	1	1	1	1	1	1	1
LVCMOS25.16.SLOW	0	0	0	0	0	0	1	0
LVCMOS25.2.FAST	0	1	1	1	1	1	1	1
LVCMOS25.2.SLOW	0	0	0	0	0	0	0	1
LVCMOS25.24.FAST	0	1	1	1	1	1	1	1
LVCMOS25.24.SLOW	0	0	0	1	0	0	1	1
LVCMOS25.4.FAST	0	1	1	1	1	1	1	1
LVCMOS25.4.SLOW	0	0	0	0	0	0	0	1
LVCMOS25.6.FAST	0	1	1	1	1	1	1	1
LVCMOS25.6.SLOW	0	0	0	0	0	0	0	1
LVCMOS25.8.FAST	0	1	1	1	1	1	1	1
LVCMOS25.8.SLOW	0	0	0	0	0	0	0	1
LVCMOS33.12.FAST	0	1	1	1	1	1	1	1
LVCMOS33.12.SLOW	0	0	0	0	0	0	0	1
LVCMOS33.16.FAST	1	1	1	1	0	1	1	1
LVCMOS33.16.SLOW	0	0	0	0	0	0	1	0
LVCMOS33.2.FAST	0	1	1	1	1	1	1	1
LVCMOS33.2.SLOW	0	0	0	0	0	0	0	1
LVCMOS33.24.FAST	0	1	1	1	1	1	1	1
LVCMOS33.24.SLOW	0	0	0	1	0	0	1	0
LVCMOS33.4.FAST	0	1	1	1	1	1	1	1
LVCMOS33.4.SLOW	0	0	0	0	0	0	0	1
LVCMOS33.6.FAST	0	1	1	1	1	1	1	1
LVCMOS33.6.SLOW	0	0	0	0	0	0	0	1
LVCMOS33.8.FAST	0	1	1	1	1	1	1	1
LVCMOS33.8.SLOW	0	0	0	0	0	0	0	1
LVDCI_15	1	1	1	0	1	0	0	1
LVDCI_18	0	0	0	1	1	1	0	0
LVDCI_25	0	0	0	0	1	0	0	1
LVDCI_33	0	0	0	0	1	1	1	1
LVDCI_DV2_15	0	0	1	1	0	1	1	1
LVDCI_DV2_18	0	0	0	1	0	1	1	1
LVDCI_DV2_25	0	0	0	1	1	1	1	1
LVPECL_25	0	1	1	0	1	0	1	0
LVTTL.12.FAST	0	1	1	1	1	1	1	1
LVTTL.12.SLOW	0	0	0	0	0	0	0	1
LVTTL.16.FAST	1	1	1	1	0	1	1	1
LVTTL.16.SLOW	0	0	0	0	0	0	1	0
LVTTL.2.FAST	0	1	1	1	1	1	1	1
LVTTL.2.SLOW	0	0	0	0	0	0	0	1
LVTTL.24.FAST	0	1	1	1	1	1	1	1
LVTTL.24.SLOW	0	0	0	1	0	0	1	0
LVTTL.4.FAST	0	1	1	1	1	1	1	1
LVTTL.4.SLOW	0	0	0	0	0	0	0	1
LVTTL.6.FAST	0	1	1	1	1	1	1	1
LVTTL.6.SLOW	0	0	0	0	0	0	0	1
LVTTL.8.FAST	0	1	1	1	1	1	1	1
LVTTL.8.SLOW	0	0	0	0	0	0	0	1
OFF	0	0	0	0	0	0	1	0
PCI33_3	0	0	0	1	0	0	1	1
PCI66_3	0	0	0	1	0	0	1	1
PCIX	0	1	1	1	1	0	1	1
SSTL18_I	0	1	0	0	0	1	1	0
SSTL18_II	0	1	0	0	0	1	0	0
SSTL18_II_DCI	0	0	1	1	0	1	0	0
SSTL18_II_T_DCI	0	0	1	1	0	1	0	0
SSTL18_I_DCI	0	0	1	1	0	1	0	0
SSTL2_I	0	0	1	1	0	1	1	1
SSTL2_II	0	0	1	1	1	0	0	0
SSTL2_II_DCI	0	0	1	0	0	1	0	1
SSTL2_II_T_DCI	0	0	1	0	0	1	1	0
SSTL2_I_DCI	0	0	1	0	0	1	1	0
VR	0	1	1	1	0	1	1	1
VREF	0	0	0	0	0	0	0	0

Name	IOSTD:OUTPUT_MISC
Name	[1]	[0]
BLVDS_25	0	0
GTL	0	1
GTLP	1	0
GTLP_DCI	0	0
GTL_DCI	0	1
HSLVDCI_15	0	0
HSLVDCI_18	0	0
HSLVDCI_25	0	0
HSLVDCI_33	0	0
HSTL_I	0	1
HSTL_II	0	0
HSTL_III	0	1
HSTL_III_18	0	0
HSTL_III_DCI	0	1
HSTL_III_DCI_18	0	0
HSTL_II_18	0	1
HSTL_II_DCI	0	0
HSTL_II_DCI_18	0	1
HSTL_II_T_DCI	0	1
HSTL_II_T_DCI_18	0	1
HSTL_IV	0	1
HSTL_IV_18	1	0
HSTL_IV_DCI	0	1
HSTL_IV_DCI_18	1	0
HSTL_I_12	0	0
HSTL_I_18	0	1
HSTL_I_DCI	0	1
HSTL_I_DCI_18	0	1
LVCMOS15	0	0
LVCMOS18	0	0
LVCMOS25	0	0
LVCMOS33	0	0
LVDCI_15	0	0
LVDCI_18	0	0
LVDCI_25	0	0
LVDCI_33	0	0
LVDCI_DV2_15	0	0
LVDCI_DV2_18	0	0
LVDCI_DV2_25	0	0
LVPECL_25	0	0
LVTTL	0	0
OFF	0	0
PCI33_3	1	0
PCI66_3	1	0
PCIX	0	0
SSTL18_I	0	1
SSTL18_II	0	1
SSTL18_II_DCI	0	0
SSTL18_II_T_DCI	0	0
SSTL18_I_DCI	0	0
SSTL2_I	0	1
SSTL2_II	1	0
SSTL2_II_DCI	0	0
SSTL2_II_T_DCI	0	0
SSTL2_I_DCI	0	0

Name	IOSTD:LVDS_T				IOSTD:LVDS_C
Name	[3]	[2]	[1]	[0]	[3]	[2]	[1]	[0]
OFF	0	0	0	0	0	0	0	0
OUTPUT_LDT_25	0	1	1	0	0	1	1	0
OUTPUT_LVDSEXT_25	1	1	1	0	0	0	1	0
OUTPUT_LVDSEXT_25_DCI	1	1	0	0	0	0	0	0
OUTPUT_LVDS_25	0	1	1	0	1	0	1	0
OUTPUT_LVDS_25_DCI	0	1	0	0	0	0	0	0
OUTPUT_RSDS_25	0	1	1	0	1	0	1	0
OUTPUT_ULVDS_25	0	1	1	0	0	1	1	0
TERM_LDT_25	0	0	1	1	0	0	1	0
TERM_LVDSEXT_25	0	0	1	1	1	0	1	0
TERM_LVDS_25	0	0	1	1	1	0	1	0
TERM_RSDS_25	0	0	1	1	1	0	1	0
TERM_ULVDS_25	0	0	1	1	0	0	1	0

IO bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:BITSLIP_ENABLE[0]	-	-	-	-	~OLOGIC0:TFF_INIT[0]	OLOGIC0:OFF_SERDES[0]	IOB0:PSLEW[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:DATA_RATE	-	ILOGIC0:IOBDELAY_VALUE_INIT[5]	-	-	~OLOGIC0:OFF_INIT[0]	~OLOGIC0:INIT_LOADCNT[3]	IOB0:NSLEW[0]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:BITSLIP_SYNC	-	-	-	~OLOGIC0:TFF_INIT[1]	OLOGIC0:DATA_WIDTH[0]	IOB0:IBUF_MODE[2]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC0:OFF_INIT[1]	-	IOB0:IBUF_MODE[1]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:IOBDELAY_VALUE_CUR[5]	-	-	~OLOGIC0:INV.T1	OLOGIC0:OFF_SERDES[1]	IOB0:IBUF_MODE[0]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:IOBDELAY_VALUE_INIT[4]	-	-	OLOGIC0:TFF_SYNC[0]	~OLOGIC0:INIT_LOADCNT[2]	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_BITSLIPCNT[0]	-	~OLOGIC0:INV.CLK1	-	-	~OLOGIC0:INV.T2	OLOGIC0:DATA_WIDTH[7]	IOB0:PSLEW[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:BITSLIP_ENABLE[1]	ILOGIC0:BITSLIP_ENABLE[3]	~OLOGIC0:INV.CLK2	-	-	~OLOGIC0:TFF_INIT[2]	-	~IOB0:NSLEW[1]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK2[5]	ILOGIC0:BITSLIP_ENABLE[4]	~ILOGIC0:IOBDELAY_VALUE_CUR[4]	-	-	~OLOGIC0:INV.T3	OLOGIC0:OFF_SERDES[2]	IOB0:DCI_T
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK2[4]	-	-	-	-	~OLOGIC0:OFF_INIT[2]	OLOGIC0:DATA_WIDTH[2]	IOB0:LVDS[0]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK2[1]	~ILOGIC0:INIT_RANK2[3]	ILOGIC0:IOBDELAY_VALUE_INIT[3]	-	-	OLOGIC0:TMUX[1]	~OLOGIC0:INIT_LOADCNT[1]	-
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK2[0]	-	-	-	-	OLOGIC0:TMUX[2]	OLOGIC0:DATA_WIDTH[1]	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK2[2]	-	~ILOGIC0:IOBDELAY_VALUE_CUR[3]	-	-	OLOGIC0:OFF_SYNC[0]	OLOGIC0:DATA_WIDTH[5]	IOB0:PSLEW[2]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC0:INV.T4	OLOGIC0:DATA_WIDTH[4]	IOB0:NSLEW[2]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC0:OFF_SERDES[3]	~IOB0:DCIUPDATEMODE_ASREQUIRED
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:DATA_WIDTH[2]	ILOGIC0:DATA_WIDTH[0]	ILOGIC0:IOBDELAY_VALUE_INIT[2]	-	-	~OLOGIC0:TFF_INIT[3]	OLOGIC0:DATA_WIDTH[3]	IOB0:PULL[1]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:DATA_WIDTH[3]	ILOGIC0:DATA_WIDTH[1]	-	-	-	~OLOGIC0:INV.D6	-	IOB0:PULL[2]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:INV.SR	-	-	-	~OLOGIC0:INV.D2	OLOGIC0:DATA_WIDTH[6]	IOB0:OUTPUT_ENABLE[1]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:BITSLIP_ENABLE[2]	~ILOGIC0:INIT_BITSLIPCNT[1]	~ILOGIC0:IOBDELAY_VALUE_CUR[2]	-	-	~OLOGIC0:INV.D5	OLOGIC0:OFF_SYNC[2]	IOB0:PSLEW[3]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK3[5]	ILOGIC0:BITSLIP_ENABLE[5]	-	-	-	~OLOGIC0:INV.D4	IOB0:NSLEW[3]	IOB0:OUTPUT_MISC[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK3[4]	ILOGIC0:BITSLIP_ENABLE[6]	ILOGIC0:IOBDELAY_VALUE_INIT[1]	-	-	OLOGIC0:TFF_LATCH	IOB0:OUTPUT_MISC[1]	IOB0:LVDS[2]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK3[0]	~ILOGIC0:INIT_RANK3[3]	-	-	-	~OLOGIC0:INV.D3	IOB0:OUTPUT_ENABLE[0]	IOB0:PULL[0]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK3[1]	ILOGIC0:DDR_CLK_EDGE[1]	ILOGIC0:IOBDELAY_TYPE[0]	-	-	-	IOB0:LVDS[3]	IOB0:LVDS[1]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK3[2]	ILOGIC0:DDR_CLK_EDGE[0]	~ILOGIC0:IOBDELAY_VALUE_CUR[1]	-	-	~OLOGIC0:INV.D1	-	IOB0:DCI_MISC[0]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_BITSLIPCNT[3]	~ILOGIC0:INIT_BITSLIPCNT[2]	ILOGIC0:IOBDELAY_VALUE_INIT[0]	-	-	OLOGIC0:TMUX[0]	~OLOGIC0:INIT_LOADCNT[0]	IOB0:NDRIVE[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:INV.OCLK2	~ILOGIC0:INV.CLK[1]	-	-	-	~OLOGIC0:TFF3_SRVAL	~OLOGIC0:OFF_SRVAL[0]	IOB0:PDRIVE[0]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INV.CLK[0]	ILOGIC0:INV.OCLK1	-	-	-	~OLOGIC0:TFF_INIT[4]	~OLOGIC0:OFF_INIT[3]	~IOB0:NDRIVE[1]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK1_PARTIAL[3]	~ILOGIC0:IFF1_SRVAL	~ILOGIC0:IOBDELAY_VALUE_CUR[0]	-	-	~OLOGIC0:TFF2_SRVAL	OLOGIC0:OMUX[1]	~IOB0:PDRIVE[1]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:IFF2_INIT	~ILOGIC0:IFF4_SRVAL	ILOGIC0:IOBDELAY_TYPE[1]	-	-	~OLOGIC0:TFF1_SRVAL	OLOGIC0:OMUX[2]	~IOB0:NDRIVE[2]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:IFF3_INIT	~ILOGIC0:INIT_RANK1_PARTIAL[1]	-	OLOGIC0:MUX.CLK[8]	-	OLOGIC0:TRISTATE_WIDTH[1]	-	IOB0:PDRIVE[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:SERDES	~ILOGIC0:INIT_RANK1_PARTIAL[0]	ILOGIC0:IFF_ENABLE	ILOGIC0:MUX.CLK[4]	ILOGIC0:MUX.CLK[1]	OLOGIC0:TRISTATE_WIDTH[0]	-	IOB0:NDRIVE[3]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INV.CLK[2]	ILOGIC0:IDELAYMUX[0]	ILOGIC0:MUX.CLK[3]	ILOGIC0:MUX.CLK[2]	OLOGIC0:TFF_SR_USED	OLOGIC0:OMUX[0]	~IOB0:PDRIVE[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:INTERFACE_TYPE	ILOGIC0:SERDES_MODE	ILOGIC1:READBACK_I	OLOGIC0:MUX.CLK[5]	ILOGIC0:MUX.CLK[0]	~OLOGIC0:OFF_INIT_SERDES[0]	OLOGIC0:OFF_LATCH	IOB0:NDRIVE[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INIT_RANK1_PARTIAL[4]	~ILOGIC0:INIT_CE[1]	ILOGIC0:I_TSBYPASS_ENABLE	OLOGIC0:MUX.CLK[6]	ILOGIC0:MUX.CLK[5]	OLOGIC0:TFF_SYNC[1]	~OLOGIC0:OFF_SRVAL[1]	IOB0:PDRIVE[4]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:INV.REV	~ILOGIC0:IFF1_INIT	ILOGIC0:IDELAYMUX[1]	OLOGIC0:MUX.CLK[7]	ILOGIC0:MUX.CLK[6]	OLOGIC0:TFF_REV_USED	~OLOGIC0:OFF_SRVAL[2]	IOB0:DCI_MISC[1]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC0:NUM_CE	~ILOGIC0:IFF4_INIT	ILOGIC0:I_DELAY_DEFAULT	ILOGIC0:MUX.CLK[8]	ILOGIC0:MUX.CLK[7]	OLOGIC0:OFF_SYNC[1]	OLOGIC0:OFF_SR_USED	IOB0:DCI_MODE[0]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:IFF_LATCH	~ILOGIC0:INIT_CE[0]	ILOGIC0:I_DELAY_ENABLE	OLOGIC0:MUX.CLK[3]	OLOGIC0:MUX.CLK[0]	~OLOGIC0:OFF_INIT_SERDES[1]	-	IOB0:DCI_MODE[1]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:IFF_SYNC	~ILOGIC0:INIT_RANK1_PARTIAL[2]	ILOGIC0:TSBYPASS_MUX	OLOGIC0:MUX.CLK[4]	OLOGIC0:MUX.CLK[1]	~OLOGIC0:OFF_INIT_SERDES[2]	-	IOB0:DCI_MODE[2]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INV.CE2	~ILOGIC0:IFF2_SRVAL	ILOGIC0:IFF_DELAY_ENABLE	-	OLOGIC0:MUX.CLK[2]	OLOGIC0:SERDES	OLOGIC0:OFF_SYNC[3]	IOB0:VR
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC0:INV.CE1	~ILOGIC0:IFF3_SRVAL	ILOGIC0:IFF_TSBYPASS_ENABLE	-	-	OLOGIC0:SERDES_MODE	OLOGIC0:OFF_REV_USED	IOB0:VREF_SYSMON
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INV.CE1	~ILOGIC1:IFF3_SRVAL	ILOGIC1:IFF_TSBYPASS_ENABLE	-	-	OLOGIC1:SERDES_MODE	OLOGIC1:OFF_REV_USED	IOB1:VREF_SYSMON
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INV.CE2	~ILOGIC1:IFF2_SRVAL	ILOGIC1:IFF_DELAY_ENABLE	-	OLOGIC1:MUX.CLK[2]	OLOGIC1:SERDES	OLOGIC1:OFF_SYNC[2]	IOB1:VR
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:IFF_SYNC	~ILOGIC1:INIT_RANK1_PARTIAL[2]	ILOGIC1:TSBYPASS_MUX	OLOGIC1:MUX.CLK[4]	OLOGIC1:MUX.CLK[1]	~OLOGIC1:OFF_INIT_SERDES[0]	-	IOB1:DCI_MODE[2]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:IFF_LATCH	~ILOGIC1:INIT_CE[0]	ILOGIC1:I_DELAY_ENABLE	OLOGIC1:MUX.CLK[3]	OLOGIC1:MUX.CLK[0]	~OLOGIC1:OFF_INIT_SERDES[1]	-	IOB1:DCI_MODE[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:NUM_CE	~ILOGIC1:IFF4_INIT	ILOGIC1:I_DELAY_DEFAULT	ILOGIC1:MUX.CLK[8]	ILOGIC1:MUX.CLK[7]	OLOGIC1:OFF_SYNC[0]	OLOGIC1:OFF_SR_USED	IOB1:DCI_MODE[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INV.REV	~ILOGIC1:IFF1_INIT	ILOGIC1:IDELAYMUX[1]	OLOGIC1:MUX.CLK[7]	ILOGIC1:MUX.CLK[6]	OLOGIC1:TFF_REV_USED	~OLOGIC1:OFF_SRVAL[0]	IOB1:DCI_MISC[1]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK1_PARTIAL[4]	~ILOGIC1:INIT_CE[1]	ILOGIC1:I_TSBYPASS_ENABLE	OLOGIC1:MUX.CLK[6]	ILOGIC1:MUX.CLK[5]	OLOGIC1:TFF_SYNC[0]	~OLOGIC1:OFF_SRVAL[1]	IOB1:PDRIVE[4]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INTERFACE_TYPE	ILOGIC1:SERDES_MODE	ILOGIC0:READBACK_I	OLOGIC1:MUX.CLK[5]	ILOGIC1:MUX.CLK[0]	~OLOGIC1:OFF_INIT_SERDES[2]	OLOGIC1:OFF_LATCH	IOB1:NDRIVE[4]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INV.CLK[1]	ILOGIC1:IDELAYMUX[0]	ILOGIC1:MUX.CLK[3]	ILOGIC1:MUX.CLK[2]	OLOGIC1:TFF_SR_USED	OLOGIC1:OMUX[0]	~IOB1:PDRIVE[3]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:SERDES	~ILOGIC1:INIT_RANK1_PARTIAL[0]	ILOGIC1:IFF_ENABLE	ILOGIC1:MUX.CLK[4]	ILOGIC1:MUX.CLK[1]	OLOGIC1:TRISTATE_WIDTH[0]	-	IOB1:NDRIVE[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:IFF3_INIT	~ILOGIC1:INIT_RANK1_PARTIAL[1]	-	OLOGIC1:MUX.CLK[8]	-	OLOGIC1:TRISTATE_WIDTH[1]	-	IOB1:PDRIVE[2]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:IFF2_INIT	~ILOGIC1:IFF4_SRVAL	ILOGIC1:IOBDELAY_TYPE[1]	-	-	~OLOGIC1:TFF1_SRVAL	OLOGIC1:OMUX[2]	~IOB1:NDRIVE[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK1_PARTIAL[3]	~ILOGIC1:IFF1_SRVAL	~ILOGIC1:IOBDELAY_VALUE_CUR[0]	-	-	~OLOGIC1:TFF2_SRVAL	OLOGIC1:OMUX[1]	~IOB1:PDRIVE[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INV.CLK[0]	ILOGIC1:INV.OCLK1	-	-	-	~OLOGIC1:TFF_INIT[0]	~OLOGIC1:OFF_INIT[3]	~IOB1:NDRIVE[1]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INV.OCLK2	~ILOGIC1:INV.CLK[2]	-	-	-	~OLOGIC1:TFF3_SRVAL	~OLOGIC1:OFF_SRVAL[2]	IOB1:PDRIVE[0]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INIT_BITSLIPCNT[3]	ILOGIC1:INIT_BITSLIPCNT[2]	ILOGIC1:IOBDELAY_VALUE_INIT[0]	-	-	OLOGIC1:TMUX[0]	~OLOGIC1:INIT_LOADCNT[0]	IOB1:NDRIVE[0]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK3[2]	ILOGIC1:DDR_CLK_EDGE[0]	~ILOGIC1:IOBDELAY_VALUE_CUR[1]	-	-	~OLOGIC1:INV.D1	-	IOB1:DCI_MISC[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK3[1]	ILOGIC1:DDR_CLK_EDGE[1]	ILOGIC1:IOBDELAY_TYPE[0]	-	-	-	IOB1:LVDS[3]	IOB1:LVDS[1]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK3[0]	~ILOGIC1:INIT_RANK3[3]	-	-	-	~OLOGIC1:INV.D3	IOB1:OUTPUT_ENABLE[0]	IOB1:PULL[0]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK3[4]	ILOGIC1:BITSLIP_ENABLE[3]	ILOGIC1:IOBDELAY_VALUE_INIT[1]	-	-	OLOGIC1:TFF_LATCH	IOB1:OUTPUT_MISC[1]	IOB1:LVDS[2]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK3[5]	ILOGIC1:BITSLIP_ENABLE[4]	-	-	-	~OLOGIC1:INV.D4	IOB1:NSLEW[3]	IOB1:OUTPUT_MISC[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:BITSLIP_ENABLE[0]	ILOGIC1:INIT_BITSLIPCNT[1]	~ILOGIC1:IOBDELAY_VALUE_CUR[2]	-	-	~OLOGIC1:INV.D5	OLOGIC1:OFF_SYNC[3]	IOB1:PSLEW[3]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INV.SR	-	-	-	~OLOGIC1:INV.D2	OLOGIC1:DATA_WIDTH[6]	IOB1:OUTPUT_ENABLE[1]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:DATA_WIDTH[3]	ILOGIC1:DATA_WIDTH[1]	-	-	-	~OLOGIC1:INV.D6	-	IOB1:PULL[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:DATA_WIDTH[2]	ILOGIC1:DATA_WIDTH[0]	ILOGIC1:IOBDELAY_VALUE_INIT[2]	-	-	~OLOGIC1:TFF_INIT[1]	OLOGIC1:DATA_WIDTH[3]	IOB1:PULL[1]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC1:OFF_SERDES[0]	~IOB1:DCIUPDATEMODE_ASREQUIRED
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC1:INV.T4	OLOGIC1:DATA_WIDTH[4]	IOB1:NSLEW[2]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK2[2]	-	~ILOGIC1:IOBDELAY_VALUE_CUR[3]	-	-	OLOGIC1:OFF_SYNC[1]	OLOGIC1:DATA_WIDTH[5]	IOB1:PSLEW[2]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK2[0]	-	-	-	-	OLOGIC1:TMUX[2]	OLOGIC1:DATA_WIDTH[1]	-
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK2[1]	~ILOGIC1:INIT_RANK2[3]	ILOGIC1:IOBDELAY_VALUE_INIT[3]	-	-	OLOGIC1:TMUX[1]	~OLOGIC1:INIT_LOADCNT[1]	-
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK2[4]	-	-	-	-	~OLOGIC1:OFF_INIT[0]	OLOGIC1:DATA_WIDTH[2]	IOB1:LVDS[0]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:INIT_RANK2[5]	ILOGIC1:BITSLIP_ENABLE[5]	~ILOGIC1:IOBDELAY_VALUE_CUR[4]	-	-	~OLOGIC1:INV.T3	OLOGIC1:OFF_SERDES[1]	IOB1:DCI_T
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:BITSLIP_ENABLE[1]	ILOGIC1:BITSLIP_ENABLE[6]	~OLOGIC1:INV.CLK2	-	-	~OLOGIC1:TFF_INIT[2]	-	~IOB1:NSLEW[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:INIT_BITSLIPCNT[0]	-	~OLOGIC1:INV.CLK1	-	-	~OLOGIC1:INV.T2	OLOGIC1:DATA_WIDTH[7]	IOB1:PSLEW[1]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:IOBDELAY_VALUE_INIT[4]	-	-	OLOGIC1:TFF_SYNC[1]	~OLOGIC1:INIT_LOADCNT[2]	-
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC1:IOBDELAY_VALUE_CUR[5]	-	-	~OLOGIC1:INV.T1	OLOGIC1:OFF_SERDES[2]	IOB1:IBUF_MODE[0]
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC1:OFF_INIT[1]	-	IOB1:IBUF_MODE[1]
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:BITSLIP_SYNC	-	-	-	~OLOGIC1:TFF_INIT[3]	OLOGIC1:DATA_WIDTH[0]	IOB1:IBUF_MODE[2]
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:DATA_RATE	-	ILOGIC1:IOBDELAY_VALUE_INIT[5]	-	-	~OLOGIC1:OFF_INIT[2]	~OLOGIC1:INIT_LOADCNT[3]	IOB1:NSLEW[0]
79	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC1:BITSLIP_ENABLE[2]	-	-	-	-	~OLOGIC1:TFF_INIT[4]	OLOGIC1:OFF_SERDES[3]	IOB1:PSLEW[0]

ILOGIC0:BITSLIP_ENABLE	[0, 20, 20]	[0, 20, 19]	[0, 20, 8]	[0, 20, 7]	[0, 19, 18]	[0, 19, 7]	[0, 19, 0]
ILOGIC1:BITSLIP_ENABLE	[0, 20, 72]	[0, 20, 71]	[0, 20, 60]	[0, 20, 59]	[0, 19, 79]	[0, 19, 72]	[0, 19, 61]
Non-inverted	[6]	[5]	[4]	[3]	[2]	[1]	[0]

ILOGIC0:DATA_RATE	[0, 19, 1]
ILOGIC1:DATA_RATE	[0, 19, 78]
DDR	0
SDR	1

ILOGIC0:INIT_BITSLIPCNT	[0, 19, 24]	[0, 20, 24]	[0, 20, 18]	[0, 19, 6]
OLOGIC0:INIT_LOADCNT	[0, 25, 1]	[0, 25, 5]	[0, 25, 10]	[0, 25, 24]
OLOGIC0:OFF_INIT	[0, 25, 26]	[0, 24, 9]	[0, 24, 3]	[0, 24, 1]
OLOGIC1:INIT_LOADCNT	[0, 25, 78]	[0, 25, 74]	[0, 25, 69]	[0, 25, 55]
OLOGIC1:OFF_INIT	[0, 25, 53]	[0, 24, 78]	[0, 24, 76]	[0, 24, 70]
Inverted	~[3]	~[2]	~[1]	~[0]

ILOGIC0:INIT_RANK2	[0, 19, 8]	[0, 19, 9]	[0, 20, 10]	[0, 19, 12]	[0, 19, 10]	[0, 19, 11]
ILOGIC0:INIT_RANK3	[0, 19, 19]	[0, 19, 20]	[0, 20, 21]	[0, 19, 23]	[0, 19, 22]	[0, 19, 21]
ILOGIC0:IOBDELAY_VALUE_CUR	[0, 21, 4]	[0, 21, 8]	[0, 21, 12]	[0, 21, 18]	[0, 21, 23]	[0, 21, 27]
ILOGIC1:INIT_RANK2	[0, 19, 71]	[0, 19, 70]	[0, 20, 69]	[0, 19, 67]	[0, 19, 69]	[0, 19, 68]
ILOGIC1:INIT_RANK3	[0, 19, 60]	[0, 19, 59]	[0, 20, 58]	[0, 19, 56]	[0, 19, 57]	[0, 19, 58]
ILOGIC1:IOBDELAY_VALUE_CUR	[0, 21, 75]	[0, 21, 71]	[0, 21, 67]	[0, 21, 61]	[0, 21, 56]	[0, 21, 52]
Inverted	~[5]	~[4]	~[3]	~[2]	~[1]	~[0]

ILOGIC0:BITSLIP_SYNC	[0, 20, 2]
ILOGIC0:IFF_DELAY_ENABLE	[0, 21, 38]
ILOGIC0:IFF_ENABLE	[0, 21, 30]
ILOGIC0:IFF_TSBYPASS_ENABLE	[0, 21, 39]
ILOGIC0:INV.OCLK1	[0, 20, 26]
ILOGIC0:INV.OCLK2	[0, 19, 25]
ILOGIC0:INV.REV	[0, 19, 34]
ILOGIC0:INV.SR	[0, 20, 17]
ILOGIC0:I_DELAY_DEFAULT	[0, 21, 35]
ILOGIC0:I_DELAY_ENABLE	[0, 21, 36]
ILOGIC0:I_TSBYPASS_ENABLE	[0, 21, 33]
ILOGIC0:READBACK_I	[0, 21, 47]
ILOGIC0:SERDES	[0, 19, 30]
ILOGIC1:BITSLIP_SYNC	[0, 20, 77]
ILOGIC1:IFF_DELAY_ENABLE	[0, 21, 41]
ILOGIC1:IFF_ENABLE	[0, 21, 49]
ILOGIC1:IFF_TSBYPASS_ENABLE	[0, 21, 40]
ILOGIC1:INV.OCLK1	[0, 20, 53]
ILOGIC1:INV.OCLK2	[0, 19, 54]
ILOGIC1:INV.REV	[0, 19, 45]
ILOGIC1:INV.SR	[0, 20, 62]
ILOGIC1:I_DELAY_DEFAULT	[0, 21, 44]
ILOGIC1:I_DELAY_ENABLE	[0, 21, 43]
ILOGIC1:I_TSBYPASS_ENABLE	[0, 21, 46]
ILOGIC1:READBACK_I	[0, 21, 32]
ILOGIC1:SERDES	[0, 19, 49]
IOB0:DCI_T	[0, 26, 8]
IOB0:VR	[0, 26, 38]
IOB0:VREF_SYSMON	[0, 26, 39]
IOB1:DCI_T	[0, 26, 71]
IOB1:VR	[0, 26, 41]
IOB1:VREF_SYSMON	[0, 26, 40]
OLOGIC0:OFF_LATCH	[0, 25, 32]
OLOGIC0:OFF_REV_USED	[0, 25, 39]
OLOGIC0:OFF_SR_USED	[0, 25, 35]
OLOGIC0:SERDES	[0, 24, 38]
OLOGIC0:TFF_LATCH	[0, 24, 20]
OLOGIC0:TFF_REV_USED	[0, 24, 34]
OLOGIC0:TFF_SR_USED	[0, 24, 31]
OLOGIC1:OFF_LATCH	[0, 25, 47]
OLOGIC1:OFF_REV_USED	[0, 25, 40]
OLOGIC1:OFF_SR_USED	[0, 25, 44]
OLOGIC1:SERDES	[0, 24, 41]
OLOGIC1:TFF_LATCH	[0, 24, 59]
OLOGIC1:TFF_REV_USED	[0, 24, 45]
OLOGIC1:TFF_SR_USED	[0, 24, 48]
Non-inverted	[0]

ILOGIC0:INV.CLK	[0, 20, 31]	[0, 20, 25]	[0, 19, 26]
ILOGIC1:INV.CLK	[0, 20, 54]	[0, 20, 48]	[0, 19, 53]
OLOGIC0:OFF_INIT_SERDES	[0, 24, 37]	[0, 24, 36]	[0, 24, 32]
OLOGIC0:OFF_SRVAL	[0, 25, 34]	[0, 25, 33]	[0, 25, 25]
OLOGIC1:OFF_INIT_SERDES	[0, 24, 47]	[0, 24, 43]	[0, 24, 42]
OLOGIC1:OFF_SRVAL	[0, 25, 54]	[0, 25, 46]	[0, 25, 45]
Inverted	~[2]	~[1]	~[0]

ILOGIC0:IFF1_INIT	[0, 20, 34]
ILOGIC0:IFF1_SRVAL	[0, 20, 27]
ILOGIC0:IFF2_INIT	[0, 19, 28]
ILOGIC0:IFF2_SRVAL	[0, 20, 38]
ILOGIC0:IFF3_INIT	[0, 19, 29]
ILOGIC0:IFF3_SRVAL	[0, 20, 39]
ILOGIC0:IFF4_INIT	[0, 20, 35]
ILOGIC0:IFF4_SRVAL	[0, 20, 28]
ILOGIC0:IFF_LATCH	[0, 19, 36]
ILOGIC0:IFF_SYNC	[0, 19, 37]
ILOGIC0:INV.CE1	[0, 19, 39]
ILOGIC0:INV.CE2	[0, 19, 38]
ILOGIC1:IFF1_INIT	[0, 20, 45]
ILOGIC1:IFF1_SRVAL	[0, 20, 52]
ILOGIC1:IFF2_INIT	[0, 19, 51]
ILOGIC1:IFF2_SRVAL	[0, 20, 41]
ILOGIC1:IFF3_INIT	[0, 19, 50]
ILOGIC1:IFF3_SRVAL	[0, 20, 40]
ILOGIC1:IFF4_INIT	[0, 20, 44]
ILOGIC1:IFF4_SRVAL	[0, 20, 51]
ILOGIC1:IFF_LATCH	[0, 19, 43]
ILOGIC1:IFF_SYNC	[0, 19, 42]
ILOGIC1:INV.CE1	[0, 19, 40]
ILOGIC1:INV.CE2	[0, 19, 41]
IOB0:DCIUPDATEMODE_ASREQUIRED	[0, 26, 14]
IOB1:DCIUPDATEMODE_ASREQUIRED	[0, 26, 65]
OLOGIC0:INV.CLK1	[0, 21, 6]
OLOGIC0:INV.CLK2	[0, 21, 7]
OLOGIC0:INV.D1	[0, 24, 23]
OLOGIC0:INV.D2	[0, 24, 17]
OLOGIC0:INV.D3	[0, 24, 21]
OLOGIC0:INV.D4	[0, 24, 19]
OLOGIC0:INV.D5	[0, 24, 18]
OLOGIC0:INV.D6	[0, 24, 16]
OLOGIC0:INV.T1	[0, 24, 4]
OLOGIC0:INV.T2	[0, 24, 6]
OLOGIC0:INV.T3	[0, 24, 8]
OLOGIC0:INV.T4	[0, 24, 13]
OLOGIC0:TFF1_SRVAL	[0, 24, 28]
OLOGIC0:TFF2_SRVAL	[0, 24, 27]
OLOGIC0:TFF3_SRVAL	[0, 24, 25]
OLOGIC1:INV.CLK1	[0, 21, 73]
OLOGIC1:INV.CLK2	[0, 21, 72]
OLOGIC1:INV.D1	[0, 24, 56]
OLOGIC1:INV.D2	[0, 24, 62]
OLOGIC1:INV.D3	[0, 24, 58]
OLOGIC1:INV.D4	[0, 24, 60]
OLOGIC1:INV.D5	[0, 24, 61]
OLOGIC1:INV.D6	[0, 24, 63]
OLOGIC1:INV.T1	[0, 24, 75]
OLOGIC1:INV.T2	[0, 24, 73]
OLOGIC1:INV.T3	[0, 24, 71]
OLOGIC1:INV.T4	[0, 24, 66]
OLOGIC1:TFF1_SRVAL	[0, 24, 51]
OLOGIC1:TFF2_SRVAL	[0, 24, 52]
OLOGIC1:TFF3_SRVAL	[0, 24, 54]
Inverted	~[0]

ILOGIC0:INTERFACE_TYPE	[0, 19, 32]
ILOGIC1:INTERFACE_TYPE	[0, 19, 47]
MEMORY	0
NETWORKING	1

ILOGIC0:NUM_CE	[0, 19, 35]
ILOGIC1:NUM_CE	[0, 19, 44]
1	0
2	1

ILOGIC1:INIT_BITSLIPCNT	[0, 19, 55]	[0, 20, 55]	[0, 20, 61]	[0, 19, 73]
IOB0:LVDS	[0, 25, 22]	[0, 26, 20]	[0, 26, 22]	[0, 26, 9]
IOB0:PSLEW	[0, 26, 18]	[0, 26, 12]	[0, 26, 6]	[0, 26, 0]
IOB1:LVDS	[0, 25, 57]	[0, 26, 59]	[0, 26, 57]	[0, 26, 70]
IOB1:PSLEW	[0, 26, 61]	[0, 26, 67]	[0, 26, 73]	[0, 26, 79]
OLOGIC0:OFF_SERDES	[0, 25, 14]	[0, 25, 8]	[0, 25, 4]	[0, 25, 0]
OLOGIC0:OFF_SYNC	[0, 25, 38]	[0, 25, 18]	[0, 24, 35]	[0, 24, 12]
OLOGIC1:OFF_SERDES	[0, 25, 79]	[0, 25, 75]	[0, 25, 71]	[0, 25, 65]
OLOGIC1:OFF_SYNC	[0, 25, 61]	[0, 25, 41]	[0, 24, 67]	[0, 24, 44]
Non-inverted	[3]	[2]	[1]	[0]

ILOGIC0:DATA_WIDTH	[0, 19, 16]	[0, 19, 15]	[0, 20, 16]	[0, 20, 15]
ILOGIC1:DATA_WIDTH	[0, 19, 63]	[0, 19, 64]	[0, 20, 63]	[0, 20, 64]
NONE	0	0	0	0
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
10	1	0	1	0

ILOGIC0:DDR_CLK_EDGE	[0, 20, 22]	[0, 20, 23]
ILOGIC1:DDR_CLK_EDGE	[0, 20, 57]	[0, 20, 56]
SAME_EDGE_PIPELINED	0	0
OPPOSITE_EDGE	0	1
SAME_EDGE	1	0

ILOGIC0:INIT_RANK1_PARTIAL	[0, 19, 33]	[0, 19, 27]	[0, 20, 37]	[0, 20, 29]	[0, 20, 30]
ILOGIC1:INIT_RANK1_PARTIAL	[0, 19, 46]	[0, 19, 52]	[0, 20, 42]	[0, 20, 50]	[0, 20, 49]
OLOGIC0:TFF_INIT	[0, 24, 26]	[0, 24, 15]	[0, 24, 7]	[0, 24, 2]	[0, 24, 0]
OLOGIC1:TFF_INIT	[0, 24, 79]	[0, 24, 77]	[0, 24, 72]	[0, 24, 64]	[0, 24, 53]
Inverted	~[4]	~[3]	~[2]	~[1]	~[0]

ILOGIC0:SERDES_MODE	[0, 20, 32]
ILOGIC1:SERDES_MODE	[0, 20, 47]
OLOGIC0:SERDES_MODE	[0, 24, 39]
OLOGIC1:SERDES_MODE	[0, 24, 40]
MASTER	0
SLAVE	1

ILOGIC0:INIT_CE	[0, 20, 33]	[0, 20, 36]
ILOGIC1:INIT_CE	[0, 20, 46]	[0, 20, 43]
Inverted	~[1]	~[0]

ILOGIC0:IOBDELAY_TYPE	[0, 21, 28]	[0, 21, 22]
ILOGIC1:IOBDELAY_TYPE	[0, 21, 51]	[0, 21, 57]
DEFAULT	0	0
FIXED	0	1
VARIABLE	1	1

ILOGIC0:IOBDELAY_VALUE_INIT	[0, 21, 1]	[0, 21, 5]	[0, 21, 10]	[0, 21, 15]	[0, 21, 20]	[0, 21, 24]
ILOGIC1:IOBDELAY_VALUE_INIT	[0, 21, 78]	[0, 21, 74]	[0, 21, 69]	[0, 21, 64]	[0, 21, 59]	[0, 21, 55]
Non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

ILOGIC0:IDELAYMUX	[0, 21, 34]	[0, 21, 31]
ILOGIC1:IDELAYMUX	[0, 21, 45]	[0, 21, 48]
NONE	0	0
D	0	1
OFB	1	0

ILOGIC0:TSBYPASS_MUX	[0, 21, 37]
ILOGIC1:TSBYPASS_MUX	[0, 21, 42]
T	0
GND	1

ILOGIC0:MUX.CLK	[0, 22, 35]	[0, 23, 35]	[0, 23, 34]	[0, 23, 33]	[0, 22, 30]	[0, 22, 31]	[0, 23, 31]	[0, 23, 30]	[0, 23, 32]
ILOGIC1:MUX.CLK	[0, 22, 44]	[0, 23, 44]	[0, 23, 45]	[0, 23, 46]	[0, 22, 49]	[0, 22, 48]	[0, 23, 48]	[0, 23, 49]	[0, 23, 47]
OLOGIC0:MUX.CLK	[0, 22, 29]	[0, 22, 34]	[0, 22, 33]	[0, 22, 32]	[0, 22, 37]	[0, 22, 36]	[0, 23, 38]	[0, 23, 37]	[0, 23, 36]
OLOGIC1:MUX.CLK	[0, 22, 50]	[0, 22, 45]	[0, 22, 46]	[0, 22, 47]	[0, 22, 42]	[0, 22, 43]	[0, 23, 41]	[0, 23, 42]	[0, 23, 43]
NONE	0	0	0	0	0	0	0	0	0
CKINT	0	0	0	0	0	0	0	0	1
HCLK0	0	0	0	1	0	0	0	1	0
HCLK4	0	0	0	1	0	0	1	0	0
RCLK0	0	0	0	1	0	1	0	0	0
IOCLK_S0	0	0	0	1	1	0	0	0	0
HCLK1	0	0	1	0	0	0	0	1	0
HCLK5	0	0	1	0	0	0	1	0	0
RCLK1	0	0	1	0	0	1	0	0	0
IOCLK_S1	0	0	1	0	1	0	0	0	0
HCLK2	0	1	0	0	0	0	0	1	0
HCLK6	0	1	0	0	0	0	1	0	0
IOCLK0	0	1	0	0	0	1	0	0	0
IOCLK_N0	0	1	0	0	1	0	0	0	0
HCLK3	1	0	0	0	0	0	0	1	0
HCLK7	1	0	0	0	0	0	1	0	0
IOCLK1	1	0	0	0	0	1	0	0	0
IOCLK_N1	1	0	0	0	1	0	0	0	0

IOB0:DCI_MISC	[0, 26, 34]	[0, 26, 23]
IOB0:OUTPUT_ENABLE	[0, 26, 17]	[0, 25, 21]
IOB0:OUTPUT_MISC	[0, 25, 20]	[0, 26, 19]
IOB1:DCI_MISC	[0, 26, 45]	[0, 26, 56]
IOB1:OUTPUT_ENABLE	[0, 26, 62]	[0, 25, 58]
IOB1:OUTPUT_MISC	[0, 25, 59]	[0, 26, 60]
OLOGIC0:TFF_SYNC	[0, 24, 33]	[0, 24, 5]
OLOGIC1:TFF_SYNC	[0, 24, 74]	[0, 24, 46]
Non-inverted	[1]	[0]

OLOGIC0:TMUX	[0, 24, 11]	[0, 24, 10]	[0, 24, 24]
OLOGIC1:TMUX	[0, 24, 68]	[0, 24, 69]	[0, 24, 55]
NONE	0	0	0
T1	0	0	1
TFF1	0	1	0
TFFDDR	1	1	0

OLOGIC0:TRISTATE_WIDTH	[0, 24, 29]	[0, 24, 30]
OLOGIC1:TRISTATE_WIDTH	[0, 24, 50]	[0, 24, 49]
1	0	0
2	0	1
4	1	1

OLOGIC0:DATA_WIDTH	[0, 25, 6]	[0, 25, 17]	[0, 25, 12]	[0, 25, 13]	[0, 25, 15]	[0, 25, 9]	[0, 25, 11]	[0, 25, 2]
OLOGIC1:DATA_WIDTH	[0, 25, 73]	[0, 25, 62]	[0, 25, 67]	[0, 25, 66]	[0, 25, 64]	[0, 25, 70]	[0, 25, 68]	[0, 25, 77]
NONE	0	0	0	0	0	0	0	0
2	0	0	0	0	0	0	0	1
3	0	0	0	0	0	0	1	0
4	0	0	0	0	0	1	0	0
5	0	0	0	0	1	0	0	0
6	0	0	0	1	0	0	0	0
7	0	0	1	0	0	0	0	0
8	0	1	0	0	0	0	0	0
10	1	0	0	0	0	0	0	0

OLOGIC0:OMUX	[0, 25, 28]	[0, 25, 27]	[0, 25, 31]
OLOGIC1:OMUX	[0, 25, 51]	[0, 25, 52]	[0, 25, 48]
NONE	0	0	0
D1	0	0	1
OFF1	0	1	0
OFFDDR	1	1	0

IOB0:NSLEW	[0, 25, 19]	[0, 26, 13]	[0, 26, 7]	[0, 26, 1]
IOB1:NSLEW	[0, 25, 60]	[0, 26, 66]	[0, 26, 72]	[0, 26, 78]
Mixed inversion	[3]	[2]	~[1]	[0]

IOB0:IBUF_MODE	[0, 26, 2]	[0, 26, 3]	[0, 26, 4]
IOB1:IBUF_MODE	[0, 26, 77]	[0, 26, 76]	[0, 26, 75]
OFF	0	0	0
VREF	0	0	1
DIFF	0	1	0
CMOS	1	1	1

IOB0:PULL	[0, 26, 16]	[0, 26, 15]	[0, 26, 21]
IOB1:PULL	[0, 26, 63]	[0, 26, 64]	[0, 26, 58]
PULLDOWN	0	0	0
NONE	0	0	1
PULLUP	0	1	1
KEEPER	1	0	1

IOB0:NDRIVE	[0, 26, 32]	[0, 26, 30]	[0, 26, 28]	[0, 26, 26]	[0, 26, 24]
IOB1:NDRIVE	[0, 26, 47]	[0, 26, 49]	[0, 26, 51]	[0, 26, 53]	[0, 26, 55]
Mixed inversion	[4]	[3]	~[2]	~[1]	[0]

IOB0:PDRIVE	[0, 26, 33]	[0, 26, 31]	[0, 26, 29]	[0, 26, 27]	[0, 26, 25]
IOB1:PDRIVE	[0, 26, 46]	[0, 26, 48]	[0, 26, 50]	[0, 26, 52]	[0, 26, 54]
Mixed inversion	[4]	~[3]	[2]	~[1]	[0]

IOB0:DCI_MODE	[0, 26, 37]	[0, 26, 36]	[0, 26, 35]
IOB1:DCI_MODE	[0, 26, 42]	[0, 26, 43]	[0, 26, 44]
NONE	0	0	0
OUTPUT	0	0	1
OUTPUT_HALF	0	1	0
TERM_VCC	0	1	1
TERM_SPLIT	1	0	0