Corners

CNR.BL

CNR.BL bittile 0
RowColumn
01234567891011121314151617181920
0 ------------------~MISC:READ_ABORT--
1 ---------------------
2 ---------------------
3 --INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[2]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[5]INT:MUX.IMUX.BUFG.V[0]INT:MUX.IMUX.IOB1.O1[3]INT:MUX.IMUX.IOB1.O1[1]INT:MUX.IMUX.IOB1.O1[0]INT:MUX.IMUX.IOB1.O1[2]INT:MUX.IMUX.IOB1.O1[4]INT:MUX.IMUX.IOB1.IK[0]INT:MUX.IMUX.IOB1.IK[4]INT:MUX.IMUX.IOB1.IK[2]INT:MUX.IMUX.IOB1.IK[1]INT:MUX.IMUX.IOB1.IK[3]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]-
4 --~PULLUP.DEC.H0:ENABLE~PULLUP.DEC.H1:ENABLE-~MISC:TM_BOTINT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.V0[5]INT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.V1[5]INT:MUX.LONG.IO.H1[1]INT:MUX.LONG.IO.H0[1]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V0[1]-----
5 --~PULLUP.DEC.V0:ENABLE--------INT:MUX.LONG.IO.V1[4]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V0[4]INT:MUX.LONG.IO.V0[3]INT:MUX.IMUX.BUFG.H~PULLUP.DEC.V1:ENABLE-~MISC:READ_CAPTUREMD1:PULL[0]MD1:PULL[1]
6 -INT:MUX.LONG.H2[2]-INT:MUX.LONG.H2[1]INT:MUX.LONG.H2[0]INT:MUX.LONG.H2[3]---INT:MUX.LONG.H3[3]INT:MUX.LONG.H3[2]INT:MUX.LONG.H3[1]INT:MUX.LONG.H3[0]INT:MUX.IMUX.RDBK.TRIG[3]INT:MUX.IMUX.RDBK.TRIG[2]INT:MUX.IMUX.RDBK.TRIG[1]INT:MUX.IMUX.RDBK.TRIG[0]~RDBK:ENABLE---
7 ~INT:PASS.SINGLE.H3.0.DEC.V0~INT:PASS.SINGLE.H1.0.DEC.V0~INT:PASS.SINGLE.H0.0.LONG.IO.V0~INT:PASS.SINGLE.H2.0.LONG.IO.V0~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H1.0.LONG.IO.V1~INT:PASS.SINGLE.H3.0.LONG.IO.V1~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.MD0.I~INT:PASS.SINGLE.H2.0.OUT.MD0.I~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H2.0.DEC.V1~INT:PASS.SINGLE.H0.0.DEC.V1--
8 ~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I--~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1-----
9 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2INT:MUX.IO.DBUF.V1[0]INT:MUX.IO.DBUF.V1[1]~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1---~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0-~MD1:ENABLE.T~MD1:ENABLE.O
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0[0, 0, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1[0, 2, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2[0, 1, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0[0, 13, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1[0, 14, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2[0, 12, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0[0, 17, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1[0, 16, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2[0, 15, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0[0, 3, 8]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1[0, 3, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2[0, 4, 9]
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2[0, 4, 8]
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2[0, 12, 8]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0[0, 5, 8]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2[0, 7, 9]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1[0, 8, 9]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0[0, 14, 8]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2[0, 13, 8]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1[0, 15, 8]
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S[0, 11, 7]
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I[0, 0, 8]
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA[0, 14, 7]
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S[0, 8, 7]
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1[0, 7, 8]
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0[0, 10, 8]
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1[0, 6, 8]
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0[0, 11, 8]
INT:PASS.SINGLE.H0.0.DEC.V1[0, 18, 7]
INT:PASS.SINGLE.H0.0.LONG.IO.V0[0, 2, 7]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 4, 7]
INT:PASS.SINGLE.H0.0.OUT.MD0.I[0, 9, 7]
INT:PASS.SINGLE.H1.0.DEC.V0[0, 1, 7]
INT:PASS.SINGLE.H1.0.LONG.IO.V1[0, 6, 7]
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S[0, 13, 7]
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA[0, 15, 7]
INT:PASS.SINGLE.H2.0.DEC.V1[0, 17, 7]
INT:PASS.SINGLE.H2.0.LONG.IO.V0[0, 3, 7]
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S[0, 5, 7]
INT:PASS.SINGLE.H2.0.OUT.MD0.I[0, 10, 7]
INT:PASS.SINGLE.H3.0.DEC.V0[0, 0, 7]
INT:PASS.SINGLE.H3.0.LONG.IO.V1[0, 7, 7]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 12, 7]
INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA[0, 16, 7]
MD1:ENABLE.O[0, 20, 9]
MD1:ENABLE.T[0, 19, 9]
MISC:READ_ABORT[0, 18, 0]
MISC:READ_CAPTURE[0, 18, 5]
MISC:TM_BOT[0, 5, 4]
PULLUP.DEC.H0:ENABLE[0, 2, 4]
PULLUP.DEC.H1:ENABLE[0, 3, 4]
PULLUP.DEC.V0:ENABLE[0, 2, 5]
PULLUP.DEC.V1:ENABLE[0, 16, 5]
RDBK:ENABLE[0, 17, 6]
Inverted~[0]
INT:MUX.LONG.H2[0, 5, 6][0, 1, 6][0, 3, 6][0, 4, 6]
0.LONG.IO.V00001
0.DEC.V00010
0.OUT.RDBK.DATA0111
NONE1111
INT:MUX.IO.DBUF.V1[0, 6, 9][0, 5, 9]
0.IO.DOUBLE.1.W.200
0.IO.DOUBLE.0.W.211
INT:MUX.LONG.IO.H0[0, 11, 4][0, 6, 4]
0.LONG.IO.V100
0.LONG.IO.V001
NONE11
INT:MUX.IMUX.BUFG.V[0, 6, 3][0, 2, 3][0, 4, 3][0, 3, 3][0, 5, 3][0, 7, 3]
0.IO.DOUBLE.0.S.0000111
0.IO.DOUBLE.0.W.1001011
0.IO.DOUBLE.1.W.1001101
0.IO.DOUBLE.1.S.0011111
0.OUT.IOB.CLKIN.S101110
NONE101111
INT:MUX.LONG.IO.H1[0, 10, 4][0, 8, 4]
0.LONG.IO.V000
0.LONG.IO.V101
NONE11
INT:MUX.IO.DBUF.V0[0, 9, 8][0, 8, 8]
0.IO.DOUBLE.0.S.000
0.IO.DOUBLE.1.S.011
INT:MUX.IMUX.IOB1.O1[0, 12, 3][0, 8, 3][0, 11, 3][0, 9, 3][0, 10, 3]
0.SINGLE.H100011
1.LONG.V000101
1.LONG.V100110
0.SINGLE.H001111
0.SINGLE.H210011
0.SINGLE.H310101
1.DOUBLE.V0.110110
1.DOUBLE.V1.011111
INT:MUX.LONG.IO.V1[0, 9, 4][0, 11, 5][0, 12, 5][0, 13, 4][0, 14, 4][0, 12, 4]
0.SINGLE.H3000111
0.LONG.H3001011
0.LONG.IO.H0001101
0.LONG.IO.H1001110
0.SINGLE.H1011111
NONE111111
INT:MUX.LONG.H3[0, 9, 6][0, 10, 6][0, 11, 6][0, 12, 6]
0.LONG.IO.V10001
0.DEC.V10010
0.OUT.RDBK.DATA0111
NONE1111
INT:MUX.IMUX.IOB1.IK[0, 14, 3][0, 17, 3][0, 15, 3][0, 16, 3][0, 13, 3]
1.SINGLE.V300110
0.DOUBLE.H0.000111
1.SINGLE.V201010
0.LONG.H201011
1.SINGLE.V101100
0.LONG.H301101
1.SINGLE.V011110
0.DOUBLE.H1.111111
INT:MUX.IMUX.BUFG.H[0, 15, 5]
0.OUT.IOB.CLKIN.W0
NONE1
INT:MUX.IMUX.RDBK.TRIG[0, 13, 6][0, 14, 6][0, 15, 6][0, 16, 6]
0.SINGLE.H10011
0.SINGLE.H20101
0.SINGLE.H30110
0.SINGLE.H01111
INT:MUX.LONG.IO.V0[0, 7, 4][0, 13, 5][0, 14, 5][0, 18, 3][0, 15, 4][0, 19, 3]
0.SINGLE.H2000111
0.LONG.H2001011
0.LONG.IO.H0001101
0.LONG.IO.H1001110
0.SINGLE.H0011111
NONE111111
MD1:PULL[0, 20, 5][0, 19, 5]
PULLUP01
PULLDOWN10
PULLNONE11

CNR.TL

CNR.TL bittile 0
RowColumn
012345678910111213141516171819
0 --~PULLUP.DEC.V0:ENABLEINT:MUX.LONG.H0[2]INT:MUX.LONG.H0[0]INT:MUX.LONG.H0[1]INT:MUX.LONG.H0[3]---INT:MUX.LONG.H1[2]INT:MUX.LONG.H1[0]INT:MUX.LONG.H1[3]---INT:MUX.IMUX.BUFG.VINT:MUX.LONG.H1[1]~PULLUP.DEC.V1:ENABLEBSCAN:ENABLE
1 --~PULLUP.DEC.H1:ENABLE~PULLUP.DEC.H0:ENABLE~MISC:TM_LEFT~MISC:TM_TOPINT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.H1[1]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.H0[1]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V0[2]----
2 --INT:MUX.IMUX.BUFG.H[4]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[5]INT:MUX.IMUX.BUFG.H[0]INT:MUX.IMUX.BSCAN.TDO1[4]INT:MUX.IMUX.BSCAN.TDO1[1]INT:MUX.IMUX.BSCAN.TDO1[3]INT:MUX.IMUX.BSCAN.TDO1[0]INT:MUX.IMUX.BSCAN.TDO1[2]INT:MUX.IMUX.BSCAN.TDO2[1]INT:MUX.IMUX.BSCAN.TDO2[4]INT:MUX.IMUX.BSCAN.TDO2[2]INT:MUX.IMUX.BSCAN.TDO2[3]INT:MUX.IMUX.BSCAN.TDO2[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[0]
3 --------------------
4 --------------------
5 ------------------MISC:INPUT-
MISC:TM_LEFT[0, 4, 1]
MISC:TM_TOP[0, 5, 1]
PULLUP.DEC.H0:ENABLE[0, 3, 1]
PULLUP.DEC.H1:ENABLE[0, 2, 1]
PULLUP.DEC.V0:ENABLE[0, 2, 0]
PULLUP.DEC.V1:ENABLE[0, 18, 0]
Inverted~[0]
INT:MUX.LONG.H0[0, 6, 0][0, 3, 0][0, 5, 0][0, 4, 0]
0.LONG.IO.V00001
0.DEC.V00010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.LONG.IO.H0[0, 13, 1][0, 6, 1]
0.LONG.IO.V100
0.LONG.IO.V001
NONE11
INT:MUX.IMUX.BUFG.H[0, 6, 2][0, 2, 2][0, 4, 2][0, 3, 2][0, 5, 2][0, 7, 2]
0.IO.DOUBLE.0.W.0000111
0.IO.DOUBLE.0.W.1001011
0.IO.DOUBLE.1.W.1001101
0.IO.DOUBLE.1.W.0011111
0.OUT.IOB.CLKIN.W101110
NONE101111
INT:MUX.LONG.IO.H1[0, 10, 1][0, 8, 1]
0.LONG.IO.V000
0.LONG.IO.V101
NONE11
INT:MUX.LONG.H1[0, 12, 0][0, 10, 0][0, 17, 0][0, 11, 0]
0.LONG.IO.V10001
0.DEC.V10010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.IMUX.BSCAN.TDO1[0, 8, 2][0, 10, 2][0, 12, 2][0, 9, 2][0, 11, 2]
1.LONG.V100011
1.DOUBLE.V0.100111
1.LONG.V001001
2.SINGLE.H101010
2.SINGLE.H301101
2.SINGLE.H201110
2.SINGLE.H011011
1.DOUBLE.V1.011111
INT:MUX.LONG.IO.V1[0, 9, 1][0, 11, 1][0, 12, 1][0, 14, 1]
0.LONG.H10001
0.LONG.IO.H00010
0.LONG.IO.H10111
NONE1111
INT:MUX.IMUX.BUFG.V[0, 16, 0]
0.OUT.IOB.CLKIN.N0
NONE1
INT:MUX.IMUX.BSCAN.TDO2[0, 14, 2][0, 16, 2][0, 15, 2][0, 13, 2][0, 17, 2]
1.SINGLE.V100101
0.LONG.H000111
1.SINGLE.V201001
0.LONG.H101011
1.SINGLE.V301100
2.DOUBLE.H1.001110
1.SINGLE.V011101
2.DOUBLE.H0.111111
MISC:INPUT[0, 18, 5]
CMOS0
TTL1
BSCAN:ENABLE[0, 19, 0]
Non-inverted[0]
INT:MUX.LONG.IO.V0[0, 7, 1][0, 15, 1][0, 18, 2][0, 19, 2]
0.LONG.H00001
0.LONG.IO.H10010
0.LONG.IO.H00111
NONE1111

CNR.BR

CNR.BR bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031
0 STARTUP:CONFIG_RATE--------------------~STARTUP:ENABLE.GTSDONE:PULL~STARTUP:INV.GTS~STARTUP:SYNC_TO_DONESTARTUP:DONE_ACTIVE[0]STARTUP:DONE_ACTIVE[1]STARTUP:GSR_INACTIVE[1]-STARTUP:GSR_INACTIVE[0]STARTUP:OUTPUTS_ACTIVE[0]~STARTUP:INV.GSR
1 ~STARTUP:CRC--------------------INT:MUX.IMUX.BUFG.H[0]~PULLUP.DEC.V1:ENABLESTARTUP:STARTUP_CLK-----STARTUP:OUTPUTS_ACTIVE[1]-~STARTUP:ENABLE.GSR
2 -----INT:MUX.LONG.H3[2]INT:MUX.LONG.H3[0]INT:MUX.LONG.H3[1]INT:MUX.IMUX.STARTUP.GSR[4]INT:MUX.IMUX.STARTUP.GSR[3]INT:MUX.IMUX.STARTUP.GSR[2]INT:MUX.IMUX.STARTUP.GSR[1]INT:MUX.IMUX.STARTUP.GSR[0]INT:MUX.IMUX.READCLK.I[3]INT:MUX.IMUX.READCLK.I[1]INT:MUX.LONG.H2[2]INT:MUX.LONG.H2[1]INT:MUX.IMUX.READCLK.I[2]INT:MUX.IMUX.READCLK.I[0]INT:MUX.LONG.H2[0]INT:MUX.LONG.H2[3]INT:MUX.IMUX.BUFG.H[4]INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.STARTUP.GTS[2]INT:MUX.IMUX.STARTUP.GTS[4]INT:MUX.IMUX.STARTUP.GTS[0]INT:MUX.IMUX.STARTUP.CLK[3]INT:MUX.IMUX.STARTUP.GTS[3]INT:MUX.IMUX.STARTUP.GTS[1]INT:MUX.IMUX.STARTUP.CLK[0]
3 ~MISC:TCTESTINT:MUX.LONG.IO.H0[6]INT:MUX.IMUX.BUFG.VINT:MUX.LONG.H3[3]INT:MUX.LONG.IO.H0[5]INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H0[4]INT:MUX.LONG.IO.H0[2]INT:MUX.LONG.IO.H1[6]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[2]INT:MUX.LONG.IO.H1[3]~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1INT:MUX.IMUX.BUFG.H[5]~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2INT:MUX.IMUX.STARTUP.CLK[1]INT:MUX.IMUX.STARTUP.CLK[2]
4 -----~PULLUP.DEC.H0:ENABLE~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1INT:MUX.IO.DBUF.H1[0]INT:MUX.IO.DBUF.H1[1]~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0INT:MUX.IO.DBUF.H0[0]INT:MUX.IO.DBUF.H0[1]~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1INT:MUX.LONG.V1[0]~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V3.0.LONG.IO.H1~INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V1.0.DEC.H0~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V1.0.LONG.IO.H1~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2~INT:PASS.SINGLE.V2.0.DEC.H1~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2~INT:PASS.SINGLE.V2.0.LONG.IO.H0
5 OSC:MUX.OUT0[3]OSC:MUX.OUT1[3]~PULLUP.DEC.H1:ENABLE~PULLUP.DEC.V0:ENABLEINT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]INT:MUX.LONG.IO.H1[1]-INT:MUX.LONG.IO.H1[0]INT:MUX.LONG.V2[2]INT:MUX.LONG.V2[0]INT:MUX.LONG.V2[3]INT:MUX.LONG.V2[1]INT:MUX.LONG.V1[2]INT:MUX.LONG.V1[1]INT:MUX.LONG.V1[3]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E~INT:BUF.LONG.H2.0.SINGLE.V2~INT:PASS.SINGLE.V3.0.DEC.H0INT:MUX.LONG.V3[2]INT:MUX.LONG.V3[1]INT:MUX.LONG.V3[0]INT:MUX.LONG.V3[3]INT:MUX.LONG.V0[2]INT:MUX.LONG.V0[1]INT:MUX.LONG.V0[0]INT:MUX.LONG.V0[3]~INT:PASS.SINGLE.V0.0.DEC.H1~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2~INT:PASS.SINGLE.V0.0.LONG.IO.H0
6 -OSC:MUX.OUT0[0]OSC:MUX.OUT1[0]OSC:MUX.OUT1[1]INT:MUX.LONG.IO.V0[5]INT:MUX.LONG.IO.V1[5]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[3]~INT:BUF.LONG.V3.0.SINGLE.H3~INT:PASS.SINGLE.H3.0.LONG.IO.V1~INT:PASS.SINGLE.H1.0.LONG.IO.V1~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:BUF.LONG.V2.0.SINGLE.H2~INT:BUF.LONG.V1.0.SINGLE.H1.E~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H3.0.LONG.V3~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2~INT:BUF.LONG.H3.0.SINGLE.V3--~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.SINGLE.H3.E~INT:BIPASS.SINGLE.H3.SINGLE.V3.S~INT:BUF.LONG.V0.0.SINGLE.H0.E--~INT:PASS.SINGLE.H0.E.0.LONG.V0-
7 ~INT:PASS.SINGLE.H0.0.DEC.V0~INT:PASS.SINGLE.H2.0.DEC.V0INT:MUX.LONG.IO.V0[4]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V1[4]~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4~INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H2.0.LONG.IO.V0~INT:PASS.SINGLE.H0.0.LONG.IO.V0~INT:PASS.SINGLE.H1.0.DEC.V1~INT:PASS.SINGLE.H3.0.DEC.V1~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2~INT:PASS.SINGLE.V3.0.LONG.H3~INT:PASS.SINGLE.H2.0.LONG.V2~INT:BIPASS.SINGLE.H3.SINGLE.V3~INT:BIPASS.SINGLE.V3.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.E.SINGLE.V3~INT:PASS.SINGLE.H1.E.0.LONG.V1~INT:PASS.SINGLE.V2.0.LONG.H2-
8 -OSC:MUX.OUT1[2]INT:MUX.LONG.IO.V0[2]--~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.H1.SINGLE.H1.E~INT:BIPASS.SINGLE.H1.SINGLE.V1~INT:BIPASS.SINGLE.H1.SINGLE.V1.S~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S~INT:BIPASS.SINGLE.H1.E.SINGLE.V1~INT:BIPASS.SINGLE.V1.SINGLE.V1.S-~INT:BIPASS.SINGLE.H2.SINGLE.V2.S~INT:BIPASS.SINGLE.H2.SINGLE.V2~INT:BIPASS.SINGLE.H2.SINGLE.H2.E~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S~INT:BIPASS.SINGLE.H2.E.SINGLE.V2~INT:BIPASS.SINGLE.V2.SINGLE.V2.S-
9 OSC:ENABLEOSC:MUX.OUT0[2]OSC:MUX.OUT0[1]~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]-~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0INT:MUX.IO.DBUF.V1[0]INT:MUX.IO.DBUF.V1[1]~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2-~INT:BIPASS.SINGLE.H0.SINGLE.V0.S~INT:BIPASS.SINGLE.H0.SINGLE.V0~INT:BIPASS.SINGLE.H0.SINGLE.H0.E~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S~INT:BIPASS.SINGLE.H0.E.SINGLE.V0~INT:BIPASS.SINGLE.V0.SINGLE.V0.S
STARTUP:CONFIG_RATE[0, 0, 0]
FAST0
SLOW1
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2[0, 20, 9]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0[0, 21, 9]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2[0, 19, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0[0, 8, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1[0, 6, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1[0, 7, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0[0, 16, 8]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1[0, 18, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1[0, 17, 8]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0[0, 23, 9]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2[0, 24, 9]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2[0, 19, 7]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0[0, 20, 7]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2[0, 20, 6]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0[0, 16, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1[0, 17, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1[0, 15, 8]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0[0, 5, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1[0, 4, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1[0, 3, 9]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0[0, 22, 7]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2[0, 23, 7]
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2[0, 22, 9]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 14, 3]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1[0, 7, 4]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2[0, 16, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 25, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1[0, 22, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2[0, 29, 3]
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2[0, 21, 7]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1[0, 24, 3]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1[0, 21, 3]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2[0, 27, 3]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1[0, 9, 4]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1[0, 8, 4]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2[0, 17, 3]
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1[0, 14, 8]
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2[0, 23, 3]
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1[0, 8, 8]
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2[0, 15, 3]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0[0, 30, 9]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S[0, 29, 9]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0[0, 13, 9]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1[0, 13, 8]
INT:BIPASS.SINGLE.H0.SINGLE.H0.E[0, 28, 9]
INT:BIPASS.SINGLE.H0.SINGLE.V0[0, 27, 9]
INT:BIPASS.SINGLE.H0.SINGLE.V0.S[0, 26, 9]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1[0, 22, 8]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S[0, 21, 8]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1[0, 12, 9]
INT:BIPASS.SINGLE.H1.SINGLE.H1.E[0, 18, 8]
INT:BIPASS.SINGLE.H1.SINGLE.V1[0, 19, 8]
INT:BIPASS.SINGLE.H1.SINGLE.V1.S[0, 20, 8]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2[0, 29, 8]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S[0, 28, 8]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0[0, 7, 8]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1[0, 6, 8]
INT:BIPASS.SINGLE.H2.SINGLE.H2.E[0, 27, 8]
INT:BIPASS.SINGLE.H2.SINGLE.V2[0, 26, 8]
INT:BIPASS.SINGLE.H2.SINGLE.V2.S[0, 25, 8]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3[0, 28, 7]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S[0, 24, 6]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1[0, 5, 8]
INT:BIPASS.SINGLE.H3.SINGLE.H3.E[0, 25, 6]
INT:BIPASS.SINGLE.H3.SINGLE.V3[0, 26, 7]
INT:BIPASS.SINGLE.H3.SINGLE.V3.S[0, 26, 6]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1[0, 19, 3]
INT:BIPASS.SINGLE.V0.SINGLE.V0.S[0, 31, 9]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1[0, 26, 3]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2[0, 28, 3]
INT:BIPASS.SINGLE.V1.SINGLE.V1.S[0, 23, 8]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1[0, 6, 4]
INT:BIPASS.SINGLE.V2.SINGLE.V2.S[0, 30, 8]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1[0, 13, 3]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2[0, 18, 3]
INT:BIPASS.SINGLE.V3.SINGLE.V3.S[0, 27, 7]
INT:BUF.LONG.H2.0.SINGLE.V2[0, 18, 5]
INT:BUF.LONG.H3.0.SINGLE.V3[0, 21, 6]
INT:BUF.LONG.V0.0.SINGLE.H0.E[0, 27, 6]
INT:BUF.LONG.V1.0.SINGLE.H1.E[0, 16, 6]
INT:BUF.LONG.V2.0.SINGLE.H2[0, 15, 6]
INT:BUF.LONG.V3.0.SINGLE.H3[0, 10, 6]
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4[0, 18, 7]
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S[0, 9, 7]
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S[0, 12, 7]
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3[0, 17, 6]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 28, 4]
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2[0, 26, 4]
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN[0, 19, 4]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 16, 5]
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0[0, 10, 8]
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1[0, 18, 4]
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1[0, 11, 8]
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0[0, 12, 4]
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0[0, 9, 8]
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1[0, 16, 4]
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1[0, 12, 8]
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0[0, 13, 4]
INT:PASS.SINGLE.H0.0.DEC.V0[0, 0, 7]
INT:PASS.SINGLE.H0.0.LONG.IO.V0[0, 14, 7]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 14, 6]
INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4[0, 11, 7]
INT:PASS.SINGLE.H0.E.0.LONG.V0[0, 30, 6]
INT:PASS.SINGLE.H1.0.DEC.V1[0, 15, 7]
INT:PASS.SINGLE.H1.0.LONG.IO.V1[0, 12, 6]
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S[0, 7, 7]
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3[0, 17, 7]
INT:PASS.SINGLE.H1.E.0.LONG.V1[0, 29, 7]
INT:PASS.SINGLE.H2.0.DEC.V0[0, 1, 7]
INT:PASS.SINGLE.H2.0.LONG.IO.V0[0, 13, 7]
INT:PASS.SINGLE.H2.0.LONG.V2[0, 25, 7]
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S[0, 13, 6]
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4[0, 10, 7]
INT:PASS.SINGLE.H3.0.DEC.V1[0, 16, 7]
INT:PASS.SINGLE.H3.0.LONG.IO.V1[0, 11, 6]
INT:PASS.SINGLE.H3.0.LONG.V3[0, 19, 6]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 8, 7]
INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3[0, 18, 6]
INT:PASS.SINGLE.V0.0.DEC.H1[0, 28, 5]
INT:PASS.SINGLE.V0.0.LONG.IO.H0[0, 31, 5]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 29, 5]
INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2[0, 30, 5]
INT:PASS.SINGLE.V1.0.DEC.H0[0, 22, 4]
INT:PASS.SINGLE.V1.0.LONG.IO.H1[0, 25, 4]
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E[0, 24, 4]
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN[0, 23, 4]
INT:PASS.SINGLE.V2.0.DEC.H1[0, 27, 4]
INT:PASS.SINGLE.V2.0.LONG.H2[0, 30, 7]
INT:PASS.SINGLE.V2.0.LONG.IO.H0[0, 31, 4]
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E[0, 29, 4]
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2[0, 30, 4]
INT:PASS.SINGLE.V3.0.DEC.H0[0, 19, 5]
INT:PASS.SINGLE.V3.0.LONG.H3[0, 24, 7]
INT:PASS.SINGLE.V3.0.LONG.IO.H1[0, 20, 4]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 17, 5]
INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN[0, 21, 4]
MISC:TCTEST[0, 0, 3]
PULLUP.DEC.H0:ENABLE[0, 5, 4]
PULLUP.DEC.H1:ENABLE[0, 2, 5]
PULLUP.DEC.V0:ENABLE[0, 3, 5]
PULLUP.DEC.V1:ENABLE[0, 22, 1]
STARTUP:CRC[0, 0, 1]
STARTUP:ENABLE.GSR[0, 31, 1]
STARTUP:ENABLE.GTS[0, 21, 0]
STARTUP:INV.GSR[0, 31, 0]
STARTUP:INV.GTS[0, 23, 0]
STARTUP:SYNC_TO_DONE[0, 24, 0]
Inverted~[0]
OSC:ENABLE[0, 0, 9]
Non-inverted[0]
OSC:MUX.OUT0[0, 0, 5][0, 1, 9][0, 2, 9][0, 1, 6]
OSC:MUX.OUT1[0, 1, 5][0, 1, 8][0, 3, 6][0, 2, 6]
F500K0011
F16K0101
F4900110
F151111
INT:MUX.IMUX.BUFG.V[0, 2, 3]
0.OUT.IOB.CLKIN.S0
NONE1
INT:MUX.LONG.IO.H0[0, 1, 3][0, 4, 3][0, 6, 3][0, 5, 3][0, 7, 3][0, 5, 5][0, 4, 5]
0.SINGLE.V20001111
0.LONG.V00010111
0.LONG.V20011011
0.SINGLE.V00111111
0.LONG.IO.V01111100
0.LONG.IO.V11111101
NONE1111111
INT:MUX.LONG.IO.V0[0, 4, 6][0, 2, 7][0, 3, 7][0, 2, 8][0, 5, 7][0, 4, 7]
0.SINGLE.H0000111
0.LONG.H2001011
0.LONG.IO.H0001101
0.LONG.IO.H1001110
0.SINGLE.H2011111
NONE111111
INT:MUX.LONG.H3[0, 3, 3][0, 5, 2][0, 7, 2][0, 6, 2]
0.LONG.IO.V10001
0.DEC.V00010
0.OUT.STARTUP.Q30111
NONE1111
INT:MUX.LONG.IO.H1[0, 8, 3][0, 9, 3][0, 10, 3][0, 12, 3][0, 11, 3][0, 6, 5][0, 8, 5]
0.SINGLE.V30001111
0.LONG.V10010111
0.LONG.V30011011
0.SINGLE.V10111111
0.LONG.IO.V11111100
0.LONG.IO.V01111101
NONE1111111
INT:MUX.LONG.IO.V1[0, 5, 6][0, 6, 7][0, 9, 6][0, 7, 6][0, 6, 6][0, 8, 6]
0.SINGLE.H1000111
0.LONG.H3001011
0.LONG.IO.H0001101
0.LONG.IO.H1001110
0.SINGLE.H3011111
NONE111111
INT:MUX.IO.DBUF.V0[0, 10, 9][0, 9, 9]
0.IO.DOUBLE.0.S.100
0.IO.DOUBLE.1.S.111
INT:MUX.IO.DBUF.H1[0, 11, 4][0, 10, 4]
0.IO.DOUBLE.0.S.200
0.IO.DOUBLE.1.S.211
INT:MUX.LONG.V2[0, 11, 5][0, 9, 5][0, 12, 5][0, 10, 5]
0.LONG.IO.H00001
0.DEC.H00010
0.OUT.STARTUP.DONEIN0111
NONE1111
INT:MUX.IMUX.STARTUP.GSR[0, 8, 2][0, 9, 2][0, 10, 2][0, 11, 2][0, 12, 2]
0.SINGLE.H100011
0.SINGLE.H300101
0.DOUBLE.V0.000110
0.SINGLE.H001111
0.LONG.V210011
0.LONG.V310101
0.DOUBLE.V1.110110
0.SINGLE.H211111
INT:MUX.IO.DBUF.H0[0, 15, 4][0, 14, 4]
0.IO.DOUBLE.1.E.100
0.IO.DOUBLE.0.E.111
INT:MUX.IO.DBUF.V1[0, 15, 9][0, 14, 9]
0.IO.DOUBLE.1.E.000
0.IO.DOUBLE.0.E.011
INT:MUX.LONG.V1[0, 15, 5][0, 13, 5][0, 14, 5][0, 17, 4]
0.LONG.IO.H10001
0.DEC.H10010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.IMUX.READCLK.I[0, 13, 2][0, 17, 2][0, 14, 2][0, 18, 2]
0.SINGLE.H10011
0.SINGLE.H20101
0.SINGLE.H30110
0.SINGLE.H01111
INT:MUX.LONG.H2[0, 20, 2][0, 15, 2][0, 16, 2][0, 19, 2]
0.LONG.IO.V00001
0.DEC.V10010
0.OUT.STARTUP.Q30111
NONE1111
INT:MUX.IMUX.BUFG.H[0, 20, 3][0, 21, 2][0, 23, 2][0, 24, 2][0, 22, 2][0, 21, 1]
0.IO.DOUBLE.0.E.1000111
0.IO.DOUBLE.0.S.1001011
0.IO.DOUBLE.1.S.1001101
0.IO.DOUBLE.1.E.1011111
0.OUT.IOB.CLKIN.E101110
NONE101111
DONE:PULL[0, 22, 0]
PULLUP0
PULLNONE1
INT:MUX.LONG.V3[0, 23, 5][0, 20, 5][0, 21, 5][0, 22, 5]
0.LONG.IO.H10001
0.DEC.H10010
0.OUT.STARTUP.DONEIN0111
NONE1111
STARTUP:STARTUP_CLK[0, 23, 1]
CCLK0
USERCLK1
STARTUP:DONE_ACTIVE[0, 26, 0][0, 25, 0]
Q200
Q301
Q1Q410
Q011
INT:MUX.LONG.V0[0, 27, 5][0, 24, 5][0, 25, 5][0, 26, 5]
0.LONG.IO.H00001
0.DEC.H00010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.IMUX.STARTUP.GTS[0, 26, 2][0, 29, 2][0, 25, 2][0, 30, 2][0, 27, 2]
0.LONG.H200011
0.SINGLE.V000111
0.SINGLE.V301001
0.LONG.H301010
0.SINGLE.V201101
0.DOUBLE.H0.101110
0.SINGLE.V111011
0.DOUBLE.H1.011111
STARTUP:GSR_INACTIVE[0, 27, 0][0, 29, 0]
DONE_IN00
Q301
Q1Q410
Q211
STARTUP:OUTPUTS_ACTIVE[0, 29, 1][0, 30, 0]
Q300
DONE_IN01
Q210
Q1Q411
INT:MUX.IMUX.STARTUP.CLK[0, 28, 2][0, 31, 3][0, 30, 3][0, 31, 2]
0.SINGLE.V00011
0.SINGLE.V20101
0.SINGLE.V30110
0.SINGLE.V11111

CNR.TR

CNR.TR bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031
0 READCLK:READ_CLK~MISC:TAC~PULLUP.DEC.H0:ENABLE~PULLUP.DEC.V0:ENABLEINT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]INT:MUX.LONG.IO.H1[1]~MISC:TM_RIGHTINT:MUX.LONG.IO.H1[0]INT:MUX.LONG.V2[2]INT:MUX.LONG.V2[0]INT:MUX.LONG.V2[3]INT:MUX.LONG.V2[1]INT:MUX.LONG.V1[2]INT:MUX.LONG.V1[1]INT:MUX.LONG.V1[3]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E~INT:BUF.LONG.H1.0.SINGLE.V1~INT:PASS.SINGLE.V3.0.DEC.H1INT:MUX.LONG.V3[2]INT:MUX.LONG.V3[1]INT:MUX.LONG.V3[0]INT:MUX.LONG.V3[3]INT:MUX.LONG.V0[2]INT:MUX.LONG.V0[1]INT:MUX.LONG.V0[0]INT:MUX.LONG.V0[3]~INT:PASS.SINGLE.V0.0.DEC.H0~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V0.0.OUT.UPDATE.O~INT:PASS.SINGLE.V0.0.LONG.IO.H0
1 ---TDO:PULL[0]TDO:PULL[1]~PULLUP.DEC.H1:ENABLE~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2INT:MUX.IO.DBUF.H1[0]INT:MUX.IO.DBUF.H1[1]~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0INT:MUX.IO.DBUF.H0[0]INT:MUX.IO.DBUF.H0[1]~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1INT:MUX.LONG.V1[0]~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V3.0.LONG.IO.H1~INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V1.0.DEC.H1~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V1.0.LONG.IO.H1~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O~INT:PASS.SINGLE.V2.0.DEC.H0~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O~INT:PASS.SINGLE.V2.0.LONG.IO.H0
2 ~TDO:ENABLE.TINT:MUX.LONG.IO.H0[6]INT:MUX.IMUX.BUFG.HINT:MUX.LONG.H1[3]INT:MUX.LONG.IO.H0[5]INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H0[4]INT:MUX.LONG.IO.H0[2]INT:MUX.LONG.IO.H1[6]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[2]INT:MUX.LONG.IO.H1[3]~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1~PULLUP.DEC.V1:ENABLE~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0INT:MUX.IMUX.TDO.O[1]INT:MUX.IMUX.TDO.O[3]
3 -----INT:MUX.LONG.H1[2]INT:MUX.LONG.H1[0]INT:MUX.LONG.H1[1]INT:MUX.IMUX.TDO.T[2]INT:MUX.IMUX.TDO.T[4]INT:MUX.IMUX.TDO.T[1]INT:MUX.IMUX.TDO.T[0]INT:MUX.IMUX.TDO.T[3]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.H0[2]INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[0]INT:MUX.LONG.H0[3]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[2]INT:MUX.IMUX.BUFG.V[1]INT:MUX.LONG.H0[1]INT:MUX.IMUX.TDO.O[4]INT:MUX.LONG.H0[0]INT:MUX.IMUX.TDO.O[2]
4 -----------------------------INT:MUX.IMUX.BUFG.V[5]INT:MUX.IMUX.TDO.O[0]-
5 -----------------------------~TDO:ENABLE.OBSCAN:ENABLE-
CNR.TR bittile 1
RowColumn
0123456789101112131415161718192021222324252627282930
0 -------------------------------
1 -------------------------------
2 -------------------------------
3 -------------------------------
4 -------------------------------
5 -------------------------------
6 -------------------------------
7 -------------------------------
8 -------------------------------
9 ---------------------~INT:PASS.SINGLE.V1.0.LONG.H1-------~INT:BUF.LONG.H0.0.SINGLE.V0~INT:PASS.SINGLE.V0.0.LONG.H0
READCLK:READ_CLK[0, 0, 0]
RDBK0
CCLK1
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 7, 1]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2[0, 14, 2]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0[0, 16, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 22, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2[0, 25, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0[0, 29, 2]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1[0, 21, 2]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2[0, 24, 2]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0[0, 27, 2]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1[0, 8, 1]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2[0, 9, 1]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0[0, 17, 2]
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2[0, 23, 2]
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2[0, 15, 2]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1[0, 19, 2]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2[0, 26, 2]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0[0, 28, 2]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1[0, 6, 1]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2[0, 13, 2]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0[0, 18, 2]
INT:BUF.LONG.H0.0.SINGLE.V0[1, 29, 9]
INT:BUF.LONG.H1.0.SINGLE.V1[0, 18, 0]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 28, 1]
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O[0, 26, 1]
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1[0, 19, 1]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 16, 0]
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1[0, 18, 1]
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0[0, 12, 1]
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1[0, 16, 1]
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0[0, 13, 1]
INT:PASS.SINGLE.V0.0.DEC.H0[0, 28, 0]
INT:PASS.SINGLE.V0.0.LONG.H0[1, 30, 9]
INT:PASS.SINGLE.V0.0.LONG.IO.H0[0, 31, 0]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 29, 0]
INT:PASS.SINGLE.V0.0.OUT.UPDATE.O[0, 30, 0]
INT:PASS.SINGLE.V1.0.DEC.H1[0, 22, 1]
INT:PASS.SINGLE.V1.0.LONG.H1[1, 21, 9]
INT:PASS.SINGLE.V1.0.LONG.IO.H1[0, 25, 1]
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E[0, 24, 1]
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1[0, 23, 1]
INT:PASS.SINGLE.V2.0.DEC.H0[0, 27, 1]
INT:PASS.SINGLE.V2.0.LONG.IO.H0[0, 31, 1]
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E[0, 29, 1]
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O[0, 30, 1]
INT:PASS.SINGLE.V3.0.DEC.H1[0, 19, 0]
INT:PASS.SINGLE.V3.0.LONG.IO.H1[0, 20, 1]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 17, 0]
INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1[0, 21, 1]
MISC:TAC[0, 1, 0]
MISC:TM_RIGHT[0, 7, 0]
PULLUP.DEC.H0:ENABLE[0, 2, 0]
PULLUP.DEC.H1:ENABLE[0, 5, 1]
PULLUP.DEC.V0:ENABLE[0, 3, 0]
PULLUP.DEC.V1:ENABLE[0, 20, 2]
TDO:ENABLE.O[0, 29, 5]
TDO:ENABLE.T[0, 0, 2]
Inverted~[0]
INT:MUX.IMUX.BUFG.H[0, 2, 2]
0.OUT.IOB.CLKIN.E0
NONE1
TDO:PULL[0, 4, 1][0, 3, 1]
PULLUP01
PULLDOWN10
PULLNONE11
INT:MUX.LONG.IO.H0[0, 1, 2][0, 4, 2][0, 6, 2][0, 5, 2][0, 7, 2][0, 5, 0][0, 4, 0]
0.SINGLE.V20001111
0.LONG.V00010111
0.LONG.V20011011
0.SINGLE.V00111111
0.LONG.IO.V01111100
0.LONG.IO.V11111101
NONE1111111
INT:MUX.LONG.H1[0, 3, 2][0, 5, 3][0, 7, 3][0, 6, 3]
0.LONG.IO.V10001
0.DEC.V00010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.LONG.IO.H1[0, 8, 2][0, 9, 2][0, 10, 2][0, 12, 2][0, 11, 2][0, 6, 0][0, 8, 0]
0.SINGLE.V30001111
0.LONG.V10010111
0.LONG.V30011011
0.SINGLE.V10111111
0.LONG.IO.V11111100
0.LONG.IO.V01111101
NONE1111111
INT:MUX.LONG.V2[0, 11, 0][0, 9, 0][0, 12, 0][0, 10, 0]
0.LONG.IO.H00001
0.DEC.H10010
0.OUT.OSC.MUX10111
NONE1111
INT:MUX.IO.DBUF.H1[0, 11, 1][0, 10, 1]
0.IO.DOUBLE.0.N.000
0.IO.DOUBLE.1.N.011
INT:MUX.IMUX.TDO.T[0, 9, 3][0, 12, 3][0, 8, 3][0, 10, 3][0, 11, 3]
0.DOUBLE.V0.000011
0.DOUBLE.V1.100111
1.SINGLE.H101001
1.SINGLE.H301010
0.LONG.V201101
0.LONG.V301110
1.SINGLE.H011011
1.SINGLE.H211111
INT:MUX.IO.DBUF.H0[0, 15, 1][0, 14, 1]
0.IO.DOUBLE.1.E.200
0.IO.DOUBLE.0.E.211
INT:MUX.LONG.IO.V1[0, 16, 3][0, 13, 3][0, 15, 3][0, 14, 3]
0.LONG.H10001
0.LONG.IO.H00010
0.LONG.IO.H10111
NONE1111
INT:MUX.LONG.V1[0, 15, 0][0, 13, 0][0, 14, 0][0, 17, 1]
0.LONG.IO.H10001
0.DEC.H00010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.LONG.IO.V0[0, 17, 3][0, 18, 3][0, 20, 3][0, 19, 3]
0.LONG.H00001
0.LONG.IO.H10010
0.LONG.IO.H00111
NONE1111
INT:MUX.LONG.V3[0, 23, 0][0, 20, 0][0, 21, 0][0, 22, 0]
0.LONG.IO.H10001
0.DEC.H00010
0.OUT.OSC.MUX10111
NONE1111
INT:MUX.IMUX.BUFG.V[0, 29, 4][0, 22, 3][0, 25, 3][0, 26, 3][0, 27, 3][0, 23, 3]
0.IO.DOUBLE.0.E.2000111
0.IO.DOUBLE.1.E.1001011
0.IO.DOUBLE.1.E.2001101
0.IO.DOUBLE.0.E.1011111
0.OUT.IOB.CLKIN.N101110
NONE101111
INT:MUX.LONG.V0[0, 27, 0][0, 24, 0][0, 25, 0][0, 26, 0]
0.LONG.IO.H00001
0.DEC.H10010
0.OUT.BT.IOB1.I2.E0111
NONE1111
INT:MUX.LONG.H0[0, 24, 3][0, 21, 3][0, 28, 3][0, 30, 3]
0.LONG.IO.V00001
0.DEC.V10010
0.OUT.LR.IOB1.I20111
NONE1111
INT:MUX.IMUX.TDO.O[0, 29, 3][0, 31, 2][0, 31, 3][0, 30, 2][0, 30, 4]
0.LONG.H000011
0.SINGLE.V000111
0.SINGLE.V301001
0.LONG.H101010
0.SINGLE.V201101
1.DOUBLE.H1.101110
0.SINGLE.V111011
1.DOUBLE.H0.011111
BSCAN:ENABLE[0, 30, 5]
Non-inverted[0]