Splitters

`LLH.CLB`

LLH.CLB bittile 0
Row	Column
Row	0
0	-
1	-
2	-
3	-
4	-
5	-
6	~INT:BIPASS.0.LONG.H2.1.LONG.H2
7	~INT:BIPASS.0.LONG.H3.1.LONG.H3

LLH.CLB bittile 1
Row	Column
Row	0
0	-
1	-
2	-
3	-
4	~INT:BIPASS.0.LONG.H0.1.LONG.H0
5	-
6	-
7	-
8	~INT:BIPASS.0.LONG.H1.1.LONG.H1

INT:BIPASS.0.LONG.H0.1.LONG.H0	[1, 0, 4]
INT:BIPASS.0.LONG.H1.1.LONG.H1	[1, 0, 8]
INT:BIPASS.0.LONG.H2.1.LONG.H2	[0, 0, 6]
INT:BIPASS.0.LONG.H3.1.LONG.H3	[0, 0, 7]
Inverted	~[0]

`LLH.CLB.B`

LLH.CLB.B bittile 0
Row	Column
Row	0
0	-
1	-
2	-
3	-
4	-
5	-
6	~INT:BIPASS.0.LONG.H2.1.LONG.H2
7	~INT:BIPASS.0.LONG.H3.1.LONG.H3

LLH.CLB.B bittile 1
Row	Column
Row	0
0	-
1	-
2	-
3	-
4	-
5	-
6	-
7	-
8	~INT:BIPASS.0.LONG.H1.1.LONG.H1
9	~INT:BIPASS.0.LONG.H0.1.LONG.H0

INT:BIPASS.0.LONG.H0.1.LONG.H0	[1, 0, 9]
INT:BIPASS.0.LONG.H1.1.LONG.H1	[1, 0, 8]
INT:BIPASS.0.LONG.H2.1.LONG.H2	[0, 0, 6]
INT:BIPASS.0.LONG.H3.1.LONG.H3	[0, 0, 7]
Inverted	~[0]

`LLH.IO.B`

LLH.IO.B bittile 0
Row	Column
Row	0
0	-
1	-
2	~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
3	~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
4	~INT:BIPASS.0.DEC.H0.1.DEC.H0
5	~INT:BIPASS.0.DEC.H1.1.DEC.H1
6	~INT:BIPASS.0.LONG.H2.1.LONG.H2
7	~INT:BIPASS.0.LONG.H3.1.LONG.H3

INT:BIPASS.0.DEC.H0.1.DEC.H0	[0, 0, 4]
INT:BIPASS.0.DEC.H1.1.DEC.H1	[0, 0, 5]
INT:BIPASS.0.LONG.H2.1.LONG.H2	[0, 0, 6]
INT:BIPASS.0.LONG.H3.1.LONG.H3	[0, 0, 7]
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0	[0, 0, 3]
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1	[0, 0, 2]
Inverted	~[0]

`LLH.IO.T`

LLH.IO.T bittile 0
Row	Column
Row	0
0	~INT:BIPASS.0.DEC.H0.1.DEC.H0
1	~INT:BIPASS.0.DEC.H1.1.DEC.H1
2	~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
3	~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1

LLH.IO.T bittile 1
Row	Column
Row	0
0	-
1	-
2	-
3	-
4	~INT:BIPASS.0.LONG.H0.1.LONG.H0
5	-
6	-
7	-
8	~INT:BIPASS.0.LONG.H1.1.LONG.H1

INT:BIPASS.0.DEC.H0.1.DEC.H0	[0, 0, 0]
INT:BIPASS.0.DEC.H1.1.DEC.H1	[0, 0, 1]
INT:BIPASS.0.LONG.H0.1.LONG.H0	[1, 0, 4]
INT:BIPASS.0.LONG.H1.1.LONG.H1	[1, 0, 8]
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0	[0, 0, 2]
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1	[0, 0, 3]
Inverted	~[0]

`LLV.CLB`

LLV.CLB bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27
0	-	-	CLKH:MUX.O1[3]	CLKH:MUX.O1[1]	CLKH:MUX.O1[0]	CLKH:MUX.O1[2]	CLKH:MUX.O1[4]	-	CLKH:MUX.O3[3]	CLKH:MUX.O3[1]	CLKH:MUX.O3[0]	CLKH:MUX.O3[2]	CLKH:MUX.O3[4]	CLKH:MUX.O2[3]	CLKH:MUX.O2[1]	CLKH:MUX.O2[0]	CLKH:MUX.O2[2]	CLKH:MUX.O2[4]	CLKH:MUX.O0[4]	CLKH:MUX.O0[2]	CLKH:MUX.O0[0]	CLKH:MUX.O0[1]	CLKH:MUX.O0[3]	-	~INT:BIPASS.0.LONG.V2.1.LONG.V2	~INT:BIPASS.0.LONG.V1.1.LONG.V1	~INT:BIPASS.0.LONG.V0.1.LONG.V0	~INT:BIPASS.0.LONG.V3.1.LONG.V3

CLKH:MUX.O1	[0, 6, 0]	[0, 2, 0]	[0, 5, 0]	[0, 3, 0]	[0, 4, 0]
I.LL.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O3	[0, 12, 0]	[0, 8, 0]	[0, 11, 0]	[0, 9, 0]	[0, 10, 0]
I.UR.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O2	[0, 17, 0]	[0, 13, 0]	[0, 16, 0]	[0, 14, 0]	[0, 15, 0]
I.LR.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O0	[0, 18, 0]	[0, 22, 0]	[0, 19, 0]	[0, 21, 0]	[0, 20, 0]
I.UL.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

INT:BIPASS.0.LONG.V0.1.LONG.V0	[0, 26, 0]
INT:BIPASS.0.LONG.V1.1.LONG.V1	[0, 25, 0]
INT:BIPASS.0.LONG.V2.1.LONG.V2	[0, 24, 0]
INT:BIPASS.0.LONG.V3.1.LONG.V3	[0, 27, 0]
Inverted	~[0]

`LLV.IO.L`

LLV.IO.L bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
0	CLKH:MUX.O2[0]	CLKH:MUX.O2[2]	CLKH:MUX.O2[4]	~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0	CLKH:MUX.O0[3]	CLKH:MUX.O0[1]	CLKH:MUX.O0[0]	CLKH:MUX.O0[2]	CLKH:MUX.O0[4]	~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1	CLKH:MUX.O1[3]	CLKH:MUX.O1[1]	CLKH:MUX.O1[0]	CLKH:MUX.O1[2]	CLKH:MUX.O1[4]	~INT:BIPASS.0.DEC.V1.1.DEC.V1	CLKH:MUX.O3[3]	CLKH:MUX.O3[1]	CLKH:MUX.O3[0]	CLKH:MUX.O3[2]	CLKH:MUX.O3[4]

LLV.IO.L bittile 1
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~INT:BIPASS.0.DEC.V0.1.DEC.V0	CLKH:MUX.O2[3]	CLKH:MUX.O2[1]

CLKH:MUX.O2	[0, 2, 0]	[1, 29, 0]	[0, 1, 0]	[1, 30, 0]	[0, 0, 0]
I.LR.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

INT:BIPASS.0.DEC.V0.1.DEC.V0	[1, 28, 0]
INT:BIPASS.0.DEC.V1.1.DEC.V1	[0, 15, 0]
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0	[0, 3, 0]
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1	[0, 9, 0]
Inverted	~[0]

CLKH:MUX.O0	[0, 8, 0]	[0, 4, 0]	[0, 7, 0]	[0, 5, 0]	[0, 6, 0]
I.UL.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O1	[0, 14, 0]	[0, 10, 0]	[0, 13, 0]	[0, 11, 0]	[0, 12, 0]
I.LL.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O3	[0, 20, 0]	[0, 16, 0]	[0, 19, 0]	[0, 17, 0]	[0, 18, 0]
I.UR.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

`LLV.IO.R`

LLV.IO.R bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28
0	CLKH:MUX.O3[4]	CLKH:MUX.O3[2]	CLKH:MUX.O3[0]	CLKH:MUX.O3[1]	CLKH:MUX.O3[3]	~INT:BIPASS.0.DEC.V0.1.DEC.V0	CLKH:MUX.O1[4]	CLKH:MUX.O1[2]	CLKH:MUX.O1[0]	CLKH:MUX.O1[1]	CLKH:MUX.O1[3]	~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1	CLKH:MUX.O0[4]	CLKH:MUX.O0[2]	CLKH:MUX.O0[0]	CLKH:MUX.O0[1]	CLKH:MUX.O0[3]	~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0	CLKH:MUX.O2[4]	CLKH:MUX.O2[2]	CLKH:MUX.O2[0]	CLKH:MUX.O2[1]	CLKH:MUX.O2[3]	~INT:BIPASS.0.DEC.V1.1.DEC.V1	~INT:BIPASS.0.LONG.V2.1.LONG.V2	~INT:BIPASS.0.LONG.V1.1.LONG.V1	~INT:BIPASS.0.LONG.V0.1.LONG.V0	~INT:BIPASS.0.LONG.V3.1.LONG.V3	~MISC:TLC

CLKH:MUX.O3	[0, 0, 0]	[0, 4, 0]	[0, 1, 0]	[0, 3, 0]	[0, 2, 0]
I.UR.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

INT:BIPASS.0.DEC.V0.1.DEC.V0	[0, 5, 0]
INT:BIPASS.0.DEC.V1.1.DEC.V1	[0, 23, 0]
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0	[0, 17, 0]
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1	[0, 11, 0]
INT:BIPASS.0.LONG.V0.1.LONG.V0	[0, 26, 0]
INT:BIPASS.0.LONG.V1.1.LONG.V1	[0, 25, 0]
INT:BIPASS.0.LONG.V2.1.LONG.V2	[0, 24, 0]
INT:BIPASS.0.LONG.V3.1.LONG.V3	[0, 27, 0]
MISC:TLC	[0, 28, 0]
Inverted	~[0]

CLKH:MUX.O1	[0, 6, 0]	[0, 10, 0]	[0, 7, 0]	[0, 9, 0]	[0, 8, 0]
I.LL.H	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O0	[0, 12, 0]	[0, 16, 0]	[0, 13, 0]	[0, 15, 0]	[0, 14, 0]
I.UL.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1

CLKH:MUX.O2	[0, 18, 0]	[0, 22, 0]	[0, 19, 0]	[0, 21, 0]	[0, 20, 0]
I.LR.V	0	1	1	1	1
I.LL.V	1	0	1	1	1
I.UL.H	1	1	0	1	1
I.LR.H	1	1	1	0	1
I.UR.V	1	1	1	1	0
NONE	1	1	1	1	1