Splitters

LLHC.CLB

LLHC.CLB bittile 0
RowColumn
01
0 ~INT:BUF.1.LONG.H4.0.LONG.H4-
1 ~INT:BUF.0.LONG.H4.1.LONG.H4-
2 ~INT:BUF.1.LONG.H5.0.LONG.H5-
3 ~INT:BUF.0.LONG.H5.1.LONG.H5-
4 --
5 -~TBUF_SPLITTER1:PASS
6 --
7 -~PULLUP.TBUF1.R:ENABLE
8 --
9 --
10 ~TBUF_SPLITTER1:BUF_E~PULLUP.TBUF1.L:ENABLE
11 ~TBUF_SPLITTER1:BUF_W-
LLHC.CLB bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 ~INT:BUF.0.LONG.H1.1.LONG.H1~PULLUP.TBUF0.L:ENABLE
5 ~INT:BUF.1.LONG.H0.0.LONG.H0-
6 ~INT:BUF.0.LONG.H0.1.LONG.H0~TBUF_SPLITTER0:PASS
7 ~INT:BUF.1.LONG.H1.0.LONG.H1-
8 -~TBUF_SPLITTER0:BUF_E
9 ~PULLUP.TBUF0.R:ENABLE~TBUF_SPLITTER0:BUF_W
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 6]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 4]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 1]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 3]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 0, 5]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 0, 7]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 0, 0]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 2]
PULLUP.TBUF0.L:ENABLE[1, 1, 4]
PULLUP.TBUF0.R:ENABLE[1, 0, 9]
PULLUP.TBUF1.L:ENABLE[0, 1, 10]
PULLUP.TBUF1.R:ENABLE[0, 1, 7]
TBUF_SPLITTER0:BUF_E[1, 1, 8]
TBUF_SPLITTER0:BUF_W[1, 1, 9]
TBUF_SPLITTER0:PASS[1, 1, 6]
TBUF_SPLITTER1:BUF_E[0, 0, 10]
TBUF_SPLITTER1:BUF_W[0, 0, 11]
TBUF_SPLITTER1:PASS[0, 1, 5]
Inverted~[0]

LLHC.CLB.B

LLHC.CLB.B bittile 0
RowColumn
01
0 ~INT:BUF.1.LONG.H4.0.LONG.H4-
1 ~INT:BUF.0.LONG.H4.1.LONG.H4-
2 ~INT:BUF.1.LONG.H5.0.LONG.H5-
3 ~INT:BUF.0.LONG.H5.1.LONG.H5-
4 --
5 -~TBUF_SPLITTER1:PASS
6 --
7 -~PULLUP.TBUF1.R:ENABLE
8 --
9 --
10 ~TBUF_SPLITTER1:BUF_E~PULLUP.TBUF1.L:ENABLE
11 ~TBUF_SPLITTER1:BUF_W-
LLHC.CLB.B bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 --
10 --
11 ~TBUF_SPLITTER0:BUF_W~TBUF_SPLITTER0:BUF_E
12 ~PULLUP.TBUF0.R:ENABLE-
13 ~INT:BUF.0.LONG.H1.1.LONG.H1-
14 ~TBUF_SPLITTER0:PASS~INT:BUF.1.LONG.H1.0.LONG.H1
15 ~INT:BUF.0.LONG.H0.1.LONG.H0~INT:BUF.1.LONG.H0.0.LONG.H0
LLHC.CLB.B bittile 2
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8 -
9 -
10 -
11 -
12 ~PULLUP.TBUF0.L:ENABLE
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 15]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 13]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 1]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 3]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 1, 15]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 1, 14]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 0, 0]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 2]
PULLUP.TBUF0.L:ENABLE[2, 0, 12]
PULLUP.TBUF0.R:ENABLE[1, 0, 12]
PULLUP.TBUF1.L:ENABLE[0, 1, 10]
PULLUP.TBUF1.R:ENABLE[0, 1, 7]
TBUF_SPLITTER0:BUF_E[1, 1, 11]
TBUF_SPLITTER0:BUF_W[1, 0, 11]
TBUF_SPLITTER0:PASS[1, 0, 14]
TBUF_SPLITTER1:BUF_E[0, 0, 10]
TBUF_SPLITTER1:BUF_W[0, 0, 11]
TBUF_SPLITTER1:PASS[0, 1, 5]
Inverted~[0]

LLHC.IO.B

LLHC.IO.B bittile 0
RowColumn
01
0 ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3~PULLUP.DEC.L3:ENABLE
1 ~PULLUP.DEC.R3:ENABLE~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3
2 -~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2
3 ~INT:BUF.0.LONG.H5.1.LONG.H5~INT:BUF.1.LONG.H5.0.LONG.H5
4 ~INT:BIPASS.0.DEC.H2.1.DEC.H2~INT:BIPASS.0.DEC.H3.1.DEC.H3
5 ~INT:BUF.0.LONG.H4.1.LONG.H4~INT:BUF.1.LONG.H4.0.LONG.H4
6 -~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
7 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1
8 ~INT:BUF.0.LONG.H3.1.LONG.H3-
9 -~INT:BUF.1.LONG.H3.0.LONG.H3
10 ~INT:BIPASS.0.DEC.H1.1.DEC.H1~PULLUP.DEC.R2:ENABLE
11 --
12 -~PULLUP.DEC.L2:ENABLE
13 -~PULLUP.DEC.R1:ENABLE
LLHC.IO.B bittile 1
RowColumn
0
0 -
1 -
2 ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
3 -
4 ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
5 -
6 -
7 -
8 -
9 -
10 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
11 -
12 -
13 ~PULLUP.DEC.L0:ENABLE
14 ~PULLUP.DEC.R0:ENABLE
15 ~PULLUP.DEC.L1:ENABLE
INT:BIPASS.0.DEC.H0.1.DEC.H0[1, 0, 10]
INT:BIPASS.0.DEC.H1.1.DEC.H1[0, 0, 10]
INT:BIPASS.0.DEC.H2.1.DEC.H2[0, 0, 4]
INT:BIPASS.0.DEC.H3.1.DEC.H3[0, 1, 4]
INT:BUF.0.LONG.H3.1.LONG.H3[0, 0, 8]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 5]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 3]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0[0, 0, 7]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1[1, 0, 4]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2[1, 0, 2]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3[0, 0, 0]
INT:BUF.1.LONG.H3.0.LONG.H3[0, 1, 9]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 1, 5]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 1, 3]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0[0, 1, 6]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1[0, 1, 7]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2[0, 1, 2]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3[0, 1, 1]
PULLUP.DEC.L0:ENABLE[1, 0, 13]
PULLUP.DEC.L1:ENABLE[1, 0, 15]
PULLUP.DEC.L2:ENABLE[0, 1, 12]
PULLUP.DEC.L3:ENABLE[0, 1, 0]
PULLUP.DEC.R0:ENABLE[1, 0, 14]
PULLUP.DEC.R1:ENABLE[0, 1, 13]
PULLUP.DEC.R2:ENABLE[0, 1, 10]
PULLUP.DEC.R3:ENABLE[0, 0, 1]
Inverted~[0]

LLHC.IO.T

LLHC.IO.T bittile 0
RowColumn
01
0 ~PULLUP.DEC.R3:ENABLE~PULLUP.DEC.L3:ENABLE
1 ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
2 ~PULLUP.DEC.L0:ENABLE~PULLUP.DEC.R0:ENABLE
3 ~PULLUP.DEC.R2:ENABLE~PULLUP.DEC.L2:ENABLE
4 ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
5 ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3
6 ~PULLUP.DEC.L1:ENABLE~PULLUP.DEC.R1:ENABLE
LLHC.IO.T bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 ~INT:BUF.0.LONG.H1.1.LONG.H1-
5 ~INT:BUF.1.LONG.H0.0.LONG.H0-
6 ~INT:BUF.0.LONG.H0.1.LONG.H0-
7 ~INT:BUF.1.LONG.H1.0.LONG.H1-
8 -~INT:BUF.1.LONG.H2.0.LONG.H2
9 -~INT:BUF.0.LONG.H2.1.LONG.H2
LLHC.IO.T bittile 2
RowColumn
0
0 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0
1 ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
2 ~INT:BIPASS.0.DEC.H3.1.DEC.H3
3 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
4 -
5 ~INT:BIPASS.0.DEC.H1.1.DEC.H1
6 -
7 ~INT:BIPASS.0.DEC.H2.1.DEC.H2
INT:BIPASS.0.DEC.H0.1.DEC.H0[2, 0, 3]
INT:BIPASS.0.DEC.H1.1.DEC.H1[2, 0, 5]
INT:BIPASS.0.DEC.H2.1.DEC.H2[2, 0, 7]
INT:BIPASS.0.DEC.H3.1.DEC.H3[2, 0, 2]
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 6]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 4]
INT:BUF.0.LONG.H2.1.LONG.H2[1, 1, 9]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0[2, 0, 0]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1[0, 1, 1]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2[0, 1, 4]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3[0, 1, 5]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 0, 5]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 0, 7]
INT:BUF.1.LONG.H2.0.LONG.H2[1, 1, 8]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0[2, 0, 1]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1[0, 0, 1]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2[0, 0, 4]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3[0, 0, 5]
PULLUP.DEC.L0:ENABLE[0, 0, 2]
PULLUP.DEC.L1:ENABLE[0, 0, 6]
PULLUP.DEC.L2:ENABLE[0, 1, 3]
PULLUP.DEC.L3:ENABLE[0, 1, 0]
PULLUP.DEC.R0:ENABLE[0, 1, 2]
PULLUP.DEC.R1:ENABLE[0, 1, 6]
PULLUP.DEC.R2:ENABLE[0, 0, 3]
PULLUP.DEC.R3:ENABLE[0, 0, 0]
Inverted~[0]

LLHQ.CLB

LLHQ.CLB bittile 0
RowColumn
0
0 ~INT:BUF.0.LONG.H5.1.LONG.H5
1 ~INT:BUF.1.LONG.H5.0.LONG.H5
2 ~INT:BUF.1.LONG.H4.0.LONG.H4
3 ~INT:BUF.0.LONG.H4.1.LONG.H4
4 ~PULLUP.TBUF1.R:ENABLE
5 ~PULLUP.TBUF1.L:ENABLE
LLHQ.CLB bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 ~PULLUP.TBUF0.R:ENABLE
7 ~PULLUP.TBUF0.L:ENABLE
8 ~INT:BUF.0.LONG.H1.1.LONG.H1
9 ~INT:BUF.1.LONG.H1.0.LONG.H1
10 ~INT:BUF.0.LONG.H0.1.LONG.H0
11 ~INT:BUF.1.LONG.H0.0.LONG.H0
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 10]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 8]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 3]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 0]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 0, 11]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 0, 9]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 0, 2]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 1]
PULLUP.TBUF0.L:ENABLE[1, 0, 7]
PULLUP.TBUF0.R:ENABLE[1, 0, 6]
PULLUP.TBUF1.L:ENABLE[0, 0, 5]
PULLUP.TBUF1.R:ENABLE[0, 0, 4]
Inverted~[0]

LLHQ.CLB.B

LLHQ.CLB.B bittile 0
RowColumn
0
0 ~INT:BUF.0.LONG.H5.1.LONG.H5
1 ~INT:BUF.1.LONG.H5.0.LONG.H5
2 ~INT:BUF.1.LONG.H4.0.LONG.H4
3 ~INT:BUF.0.LONG.H4.1.LONG.H4
4 ~PULLUP.TBUF1.R:ENABLE
5 ~PULLUP.TBUF1.L:ENABLE
LLHQ.CLB.B bittile 1
RowColumn
LLHQ.CLB.B bittile 2
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8 -
9 -
10 ~INT:BUF.1.LONG.H1.0.LONG.H1
11 ~INT:BUF.0.LONG.H1.1.LONG.H1
12 ~INT:BUF.1.LONG.H0.0.LONG.H0
13 ~INT:BUF.0.LONG.H0.1.LONG.H0
14 ~PULLUP.TBUF0.R:ENABLE
15 ~PULLUP.TBUF0.L:ENABLE
INT:BUF.0.LONG.H0.1.LONG.H0[2, 0, 13]
INT:BUF.0.LONG.H1.1.LONG.H1[2, 0, 11]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 3]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 0]
INT:BUF.1.LONG.H0.0.LONG.H0[2, 0, 12]
INT:BUF.1.LONG.H1.0.LONG.H1[2, 0, 10]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 0, 2]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 1]
PULLUP.TBUF0.L:ENABLE[2, 0, 15]
PULLUP.TBUF0.R:ENABLE[2, 0, 14]
PULLUP.TBUF1.L:ENABLE[0, 0, 5]
PULLUP.TBUF1.R:ENABLE[0, 0, 4]
Inverted~[0]

LLHQ.CLB.T

LLHQ.CLB.T bittile 0
RowColumn
0
0 ~INT:BUF.0.LONG.H5.1.LONG.H5
1 ~INT:BUF.1.LONG.H5.0.LONG.H5
2 ~INT:BUF.1.LONG.H4.0.LONG.H4
3 ~INT:BUF.0.LONG.H4.1.LONG.H4
4 ~PULLUP.TBUF1.L:ENABLE
5 ~PULLUP.TBUF1.R:ENABLE
LLHQ.CLB.T bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 ~PULLUP.TBUF0.R:ENABLE
7 ~PULLUP.TBUF0.L:ENABLE
8 ~INT:BUF.0.LONG.H1.1.LONG.H1
9 ~INT:BUF.1.LONG.H1.0.LONG.H1
10 ~INT:BUF.0.LONG.H0.1.LONG.H0
11 ~INT:BUF.1.LONG.H0.0.LONG.H0
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 10]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 8]
INT:BUF.0.LONG.H4.1.LONG.H4[0, 0, 3]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 0]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 0, 11]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 0, 9]
INT:BUF.1.LONG.H4.0.LONG.H4[0, 0, 2]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 1]
PULLUP.TBUF0.L:ENABLE[1, 0, 7]
PULLUP.TBUF0.R:ENABLE[1, 0, 6]
PULLUP.TBUF1.L:ENABLE[0, 0, 4]
PULLUP.TBUF1.R:ENABLE[0, 0, 5]
Inverted~[0]

LLHQ.IO.B

LLHQ.IO.B bittile 0
RowColumn
0
0 ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3
1 ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3
2 -
3 -
4 ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
5 ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1
6 ~INT:BUF.0.LONG.H5.1.LONG.H5
7 ~INT:BUF.1.LONG.H5.0.LONG.H5
8 -
9 -
10 ~INT:BUF.1.LONG.H3.0.LONG.H3
11 ~INT:BUF.0.LONG.H3.1.LONG.H3
LLHQ.IO.B bittile 1
RowColumn
0
0 ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
1 ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2
2 -
3 -
4 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0
5 ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
6 ~INT:BUF.0.LONG.H4.1.LONG.H4
7 ~INT:BUF.1.LONG.H4.0.LONG.H4
INT:BUF.0.LONG.H3.1.LONG.H3[0, 0, 11]
INT:BUF.0.LONG.H4.1.LONG.H4[1, 0, 6]
INT:BUF.0.LONG.H5.1.LONG.H5[0, 0, 6]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0[1, 0, 4]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1[0, 0, 4]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2[1, 0, 0]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3[0, 0, 0]
INT:BUF.1.LONG.H3.0.LONG.H3[0, 0, 10]
INT:BUF.1.LONG.H4.0.LONG.H4[1, 0, 7]
INT:BUF.1.LONG.H5.0.LONG.H5[0, 0, 7]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0[1, 0, 5]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1[0, 0, 5]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2[1, 0, 1]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3[0, 0, 1]
Inverted~[0]

LLHQ.IO.T

LLHQ.IO.T bittile 0
RowColumn
0
0 ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
1 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0
2 ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1
3 ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
4 ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2
5 ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
6 ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3
7 ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3
LLHQ.IO.T bittile 1
RowColumn
0
0 -
1 -
2 -
3 -
4 -
5 -
6 ~INT:BUF.0.LONG.H2.1.LONG.H2
7 ~INT:BUF.1.LONG.H2.0.LONG.H2
8 ~INT:BUF.0.LONG.H1.1.LONG.H1
9 ~INT:BUF.1.LONG.H1.0.LONG.H1
10 ~INT:BUF.0.LONG.H0.1.LONG.H0
11 ~INT:BUF.1.LONG.H0.0.LONG.H0
INT:BUF.0.LONG.H0.1.LONG.H0[1, 0, 10]
INT:BUF.0.LONG.H1.1.LONG.H1[1, 0, 8]
INT:BUF.0.LONG.H2.1.LONG.H2[1, 0, 6]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0[0, 0, 1]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1[0, 0, 3]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2[0, 0, 5]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3[0, 0, 7]
INT:BUF.1.LONG.H0.0.LONG.H0[1, 0, 11]
INT:BUF.1.LONG.H1.0.LONG.H1[1, 0, 9]
INT:BUF.1.LONG.H2.0.LONG.H2[1, 0, 7]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0[0, 0, 0]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1[0, 0, 2]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2[0, 0, 4]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3[0, 0, 6]
Inverted~[0]

LLVC.CLB

LLVC.CLB bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839404142434445
0 -----INT:MUX.0.VCLK[6]INT:MUX.0.VCLK[5]INT:MUX.0.VCLK[0]INT:MUX.0.VCLK[1]-----INT:MUX.0.VCLK[2]INT:MUX.0.VCLK[4]--INT:MUX.1.VCLK[5]INT:MUX.1.VCLK[6]--INT:MUX.1.VCLK[0]INT:MUX.1.VCLK[4]----INT:MUX.1.VCLK[1]INT:MUX.1.VCLK[2]----INT:MUX.1.VCLK[3]INT:MUX.0.VCLK[3]----------
1 ----------------------~INT:BUF.0.LONG.V2.1.LONG.V2~INT:BUF.1.LONG.V2.0.LONG.V2~INT:BUF.0.LONG.V4.1.LONG.V4~INT:BUF.1.LONG.V0.0.LONG.V0~INT:BUF.0.LONG.V0.1.LONG.V0~INT:BUF.1.LONG.V1.0.LONG.V1~INT:BUF.0.LONG.V1.1.LONG.V1-~INT:BUF.1.LONG.V4.0.LONG.V4-~INT:BUF.1.LONG.V9.0.LONG.V9~INT:BUF.0.LONG.V9.1.LONG.V9~INT:BUF.0.LONG.V8.1.LONG.V8~INT:BUF.1.LONG.V8.0.LONG.V8--~INT:BUF.0.LONG.V7.1.LONG.V7~INT:BUF.1.LONG.V7.0.LONG.V7~INT:BUF.1.LONG.V3.0.LONG.V3~INT:BUF.0.LONG.V3.1.LONG.V3~INT:BUF.1.LONG.V5.0.LONG.V5~INT:BUF.0.LONG.V5.1.LONG.V5~INT:BUF.1.LONG.V6.0.LONG.V6~INT:BUF.0.LONG.V6.1.LONG.V6
INT:MUX.0.VCLK[0, 5, 0][0, 6, 0][0, 15, 0][0, 35, 0][0, 14, 0][0, 8, 0][0, 7, 0]
0.QUAD.V0.40000111
1.LONG.V00001011
1.QUAD.V2.00010101
1.LONG.V60010110
1.SINGLE.V10011001
1.SINGLE.V20011010
1.GCLK50110111
1.SINGLE.V40111011
1.SINGLE.V51001111
1.LONG.V41011101
1.GCLK21011110
1.SINGLE.V01111111
INT:MUX.1.VCLK[0, 19, 0][0, 18, 0][0, 23, 0][0, 34, 0][0, 29, 0][0, 28, 0][0, 22, 0]
0.QUAD.V1.40000111
1.SINGLE.V10001011
1.QUAD.V0.00010101
0.LONG.V80010110
0.LONG.V10011001
1.SINGLE.V40011010
0.LONG.V50101111
1.SINGLE.V60111101
0.GCLK10111110
0.GCLK41010111
1.SINGLE.V51011011
1.SINGLE.V01111111
INT:BUF.0.LONG.V0.1.LONG.V0[0, 26, 1]
INT:BUF.0.LONG.V1.1.LONG.V1[0, 28, 1]
INT:BUF.0.LONG.V2.1.LONG.V2[0, 22, 1]
INT:BUF.0.LONG.V3.1.LONG.V3[0, 41, 1]
INT:BUF.0.LONG.V4.1.LONG.V4[0, 24, 1]
INT:BUF.0.LONG.V5.1.LONG.V5[0, 43, 1]
INT:BUF.0.LONG.V6.1.LONG.V6[0, 45, 1]
INT:BUF.0.LONG.V7.1.LONG.V7[0, 38, 1]
INT:BUF.0.LONG.V8.1.LONG.V8[0, 34, 1]
INT:BUF.0.LONG.V9.1.LONG.V9[0, 33, 1]
INT:BUF.1.LONG.V0.0.LONG.V0[0, 25, 1]
INT:BUF.1.LONG.V1.0.LONG.V1[0, 27, 1]
INT:BUF.1.LONG.V2.0.LONG.V2[0, 23, 1]
INT:BUF.1.LONG.V3.0.LONG.V3[0, 40, 1]
INT:BUF.1.LONG.V4.0.LONG.V4[0, 30, 1]
INT:BUF.1.LONG.V5.0.LONG.V5[0, 42, 1]
INT:BUF.1.LONG.V6.0.LONG.V6[0, 44, 1]
INT:BUF.1.LONG.V7.0.LONG.V7[0, 39, 1]
INT:BUF.1.LONG.V8.0.LONG.V8[0, 35, 1]
INT:BUF.1.LONG.V9.0.LONG.V9[0, 32, 1]
Inverted~[0]

LLVC.IO.L

LLVC.IO.L bittile 0
RowColumn
012345678910111213141516171819202122232425
0 --------------------------
1 ----~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2--~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1~PULLUP.DEC.B0:ENABLE~PULLUP.DEC.T0:ENABLE~INT:BIPASS.0.DEC.V2.1.DEC.V2~INT:BIPASS.0.DEC.V0.1.DEC.V0~PULLUP.DEC.T2:ENABLE~PULLUP.DEC.B2:ENABLE~PULLUP.DEC.B1:ENABLE~PULLUP.DEC.T1:ENABLE~PULLUP.DEC.T3:ENABLE~PULLUP.DEC.B3:ENABLE~INT:BIPASS.0.DEC.V3.1.DEC.V3~INT:BIPASS.0.DEC.V1.1.DEC.V1
INT:BIPASS.0.DEC.V0.1.DEC.V0[0, 17, 1]
INT:BIPASS.0.DEC.V1.1.DEC.V1[0, 25, 1]
INT:BIPASS.0.DEC.V2.1.DEC.V2[0, 16, 1]
INT:BIPASS.0.DEC.V3.1.DEC.V3[0, 24, 1]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 10, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 13, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 6, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 5, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 11, 1]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 12, 1]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 7, 1]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 4, 1]
PULLUP.DEC.B0:ENABLE[0, 14, 1]
PULLUP.DEC.B1:ENABLE[0, 20, 1]
PULLUP.DEC.B2:ENABLE[0, 19, 1]
PULLUP.DEC.B3:ENABLE[0, 23, 1]
PULLUP.DEC.T0:ENABLE[0, 15, 1]
PULLUP.DEC.T1:ENABLE[0, 21, 1]
PULLUP.DEC.T2:ENABLE[0, 18, 1]
PULLUP.DEC.T3:ENABLE[0, 22, 1]
Inverted~[0]

LLVC.IO.R

LLVC.IO.R bittile 0
RowColumn
01234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
0 --~MISC:TLC-~INT:BIPASS.0.DEC.V0.1.DEC.V0~INT:BIPASS.0.DEC.V2.1.DEC.V2-~INT:BIPASS.0.DEC.V1.1.DEC.V1-INT:MUX.0.VCLK[6]INT:MUX.0.VCLK[5]INT:MUX.0.VCLK[0]INT:MUX.0.VCLK[1]------INT:MUX.0.VCLK[2]INT:MUX.0.VCLK[4]--INT:MUX.1.VCLK[5]INT:MUX.1.VCLK[6]--INT:MUX.1.VCLK[0]INT:MUX.1.VCLK[4]----INT:MUX.1.VCLK[1]INT:MUX.1.VCLK[2]----INT:MUX.1.VCLK[3]INT:MUX.0.VCLK[3]----------
1 ----~PULLUP.DEC.B0:ENABLE~PULLUP.DEC.B2:ENABLE~PULLUP.DEC.T2:ENABLE~PULLUP.DEC.T0:ENABLE-~INT:BUF.0.LONG.V5.1.LONG.V5~INT:BUF.1.LONG.V5.0.LONG.V5~PULLUP.DEC.T1:ENABLE~PULLUP.DEC.B1:ENABLE~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1~INT:BUF.1.LONG.V0.0.LONG.V0~INT:BUF.0.LONG.V0.1.LONG.V0~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.1.LONG.V3.0.LONG.V3~INT:BUF.0.LONG.V3.1.LONG.V3--~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2~INT:BUF.1.LONG.V4.0.LONG.V4~INT:BUF.0.LONG.V4.1.LONG.V4~INT:BUF.0.LONG.V2.1.LONG.V2~INT:BUF.1.LONG.V2.0.LONG.V2~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0~PULLUP.DEC.T3:ENABLE~INT:BUF.1.LONG.V1.0.LONG.V1~PULLUP.DEC.B3:ENABLE~INT:BUF.0.LONG.V1.1.LONG.V1~INT:BIPASS.0.DEC.V3.1.DEC.V3-~INT:BUF.1.LONG.V9.0.LONG.V9~INT:BUF.0.LONG.V9.1.LONG.V9~INT:BUF.0.LONG.V8.1.LONG.V8~INT:BUF.1.LONG.V8.0.LONG.V8--~INT:BUF.0.LONG.V7.1.LONG.V7~INT:BUF.1.LONG.V7.0.LONG.V7----~INT:BUF.1.LONG.V6.0.LONG.V6~INT:BUF.0.LONG.V6.1.LONG.V6
INT:BIPASS.0.DEC.V0.1.DEC.V0[0, 4, 0]
INT:BIPASS.0.DEC.V1.1.DEC.V1[0, 7, 0]
INT:BIPASS.0.DEC.V2.1.DEC.V2[0, 5, 0]
INT:BIPASS.0.DEC.V3.1.DEC.V3[0, 35, 1]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 30, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 13, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 23, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 18, 1]
INT:BUF.0.LONG.V0.1.LONG.V0[0, 16, 1]
INT:BUF.0.LONG.V1.1.LONG.V1[0, 34, 1]
INT:BUF.0.LONG.V2.1.LONG.V2[0, 27, 1]
INT:BUF.0.LONG.V3.1.LONG.V3[0, 20, 1]
INT:BUF.0.LONG.V4.1.LONG.V4[0, 26, 1]
INT:BUF.0.LONG.V5.1.LONG.V5[0, 9, 1]
INT:BUF.0.LONG.V6.1.LONG.V6[0, 50, 1]
INT:BUF.0.LONG.V7.1.LONG.V7[0, 43, 1]
INT:BUF.0.LONG.V8.1.LONG.V8[0, 39, 1]
INT:BUF.0.LONG.V9.1.LONG.V9[0, 38, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 29, 1]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 14, 1]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 24, 1]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 17, 1]
INT:BUF.1.LONG.V0.0.LONG.V0[0, 15, 1]
INT:BUF.1.LONG.V1.0.LONG.V1[0, 32, 1]
INT:BUF.1.LONG.V2.0.LONG.V2[0, 28, 1]
INT:BUF.1.LONG.V3.0.LONG.V3[0, 19, 1]
INT:BUF.1.LONG.V4.0.LONG.V4[0, 25, 1]
INT:BUF.1.LONG.V5.0.LONG.V5[0, 10, 1]
INT:BUF.1.LONG.V6.0.LONG.V6[0, 49, 1]
INT:BUF.1.LONG.V7.0.LONG.V7[0, 44, 1]
INT:BUF.1.LONG.V8.0.LONG.V8[0, 40, 1]
INT:BUF.1.LONG.V9.0.LONG.V9[0, 37, 1]
MISC:TLC[0, 2, 0]
PULLUP.DEC.B0:ENABLE[0, 4, 1]
PULLUP.DEC.B1:ENABLE[0, 12, 1]
PULLUP.DEC.B2:ENABLE[0, 5, 1]
PULLUP.DEC.B3:ENABLE[0, 33, 1]
PULLUP.DEC.T0:ENABLE[0, 7, 1]
PULLUP.DEC.T1:ENABLE[0, 11, 1]
PULLUP.DEC.T2:ENABLE[0, 6, 1]
PULLUP.DEC.T3:ENABLE[0, 31, 1]
Inverted~[0]
INT:MUX.0.VCLK[0, 9, 0][0, 10, 0][0, 20, 0][0, 40, 0][0, 19, 0][0, 12, 0][0, 11, 0]
0.QUAD.V0.40000111
1.LONG.V00001011
1.QUAD.V2.00010101
1.LONG.V60010110
1.SINGLE.V10011001
1.SINGLE.V20011010
1.GCLK50110111
1.SINGLE.V40111011
1.SINGLE.V51001111
1.LONG.V41011101
1.GCLK21011110
1.SINGLE.V01111111
INT:MUX.1.VCLK[0, 24, 0][0, 23, 0][0, 28, 0][0, 39, 0][0, 34, 0][0, 33, 0][0, 27, 0]
0.QUAD.V1.40000111
1.SINGLE.V10001011
1.QUAD.V0.00010101
0.LONG.V80010110
0.LONG.V10011001
1.SINGLE.V40011010
0.LONG.V50101111
1.SINGLE.V60111101
0.GCLK10111110
0.GCLK41010111
1.SINGLE.V51011011
1.SINGLE.V01111111

LLVQ.CLB

LLVQ.CLB bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031323334353637383940414243444546
0 INT:MUX.0.GCLK1[1]-INT:MUX.0.GCLK1[2]INT:MUX.0.GCLK1[4]~INT:BUF.1.LONG.V0.0.LONG.V0INT:MUX.0.GCLK3[1]-INT:MUX.0.GCLK3[2]INT:MUX.0.GCLK3[4]~INT:BUF.1.LONG.V3.0.LONG.V3INT:MUX.0.GCLK2[1]-INT:MUX.0.GCLK2[2]INT:MUX.0.GCLK2[5]~INT:PASS.1.SINGLE.V2.0.VCLK~INT:BUF.1.LONG.V5.0.LONG.V5INT:MUX.0.GCLK7[1]~INT:PASS.1.SINGLE.V0.0.VCLKINT:MUX.0.GCLK7[2]INT:MUX.0.GCLK7[5]~INT:BUF.1.LONG.V1.0.LONG.V1INT:MUX.0.GCLK6[1]~INT:PASS.1.QUAD.V2.0.0.VCLKINT:MUX.0.GCLK6[2]INT:MUX.0.GCLK6[4]~INT:BUF.1.LONG.V4.0.LONG.V4INT:MUX.0.GCLK0[1]~INT:PASS.1.SINGLE.V3.1.VCLK~INT:PASS.1.SINGLE.V5.1.VCLKINT:MUX.0.GCLK0[2]INT:MUX.0.GCLK0[4]~INT:BUF.1.LONG.V2.0.LONG.V2~INT:PASS.1.SINGLE.V7.1.VCLKINT:MUX.0.GCLK5[1]INT:MUX.0.GCLK5[2]INT:MUX.0.GCLK5[4]INT:MUX.0.LONG.V9[1]~INT:PASS.1.SINGLE.V6.0.VCLK~INT:PASS.1.SINGLE.V4.0.VCLKINT:MUX.0.GCLK4[1]INT:MUX.0.GCLK4[2]INT:MUX.0.GCLK4[5]~INT:PASS.0.QUAD.V2.4.1.VCLK~INT:PASS.0.QUAD.V1.4.0.VCLK~INT:BUF.1.LONG.V8.0.LONG.V8INT:MUX.1.LONG.V7[1]~INT:BUF.1.LONG.V6.0.LONG.V6
1 INT:MUX.0.GCLK1[0]INT:MUX.0.GCLK1[6]INT:MUX.0.GCLK1[3]INT:MUX.0.GCLK1[5]~INT:BUF.0.LONG.V0.1.LONG.V0INT:MUX.0.GCLK3[0]INT:MUX.0.GCLK3[6]INT:MUX.0.GCLK3[3]INT:MUX.0.GCLK3[5]~INT:BUF.0.LONG.V3.1.LONG.V3INT:MUX.0.GCLK2[0]INT:MUX.0.GCLK2[6]INT:MUX.0.GCLK2[4]INT:MUX.0.GCLK2[3]-~INT:BUF.0.LONG.V5.1.LONG.V5INT:MUX.0.GCLK7[0]INT:MUX.0.GCLK7[6]INT:MUX.0.GCLK7[4]INT:MUX.0.GCLK7[3]~INT:BUF.0.LONG.V1.1.LONG.V1INT:MUX.0.GCLK6[0]INT:MUX.0.GCLK6[6]INT:MUX.0.GCLK6[3]INT:MUX.0.GCLK6[5]~INT:BUF.0.LONG.V4.1.LONG.V4~INT:PASS.1.SINGLE.V1.1.VCLKINT:MUX.0.GCLK0[0]INT:MUX.0.GCLK0[6]INT:MUX.0.GCLK0[3]INT:MUX.0.GCLK0[5]~INT:BUF.0.LONG.V2.1.LONG.V2INT:MUX.0.GCLK5[0]INT:MUX.0.GCLK5[6]INT:MUX.0.GCLK5[3]INT:MUX.0.GCLK5[5]INT:MUX.0.LONG.V9[0]~INT:BUF.1.LONG.V9.0.LONG.V9INT:MUX.0.GCLK4[0]INT:MUX.0.GCLK4[6]INT:MUX.0.GCLK4[4]INT:MUX.0.GCLK4[3]~INT:BUF.0.LONG.V8.1.LONG.V8INT:MUX.1.LONG.V7[0]~INT:PASS.1.QUAD.V0.0.1.VCLK~INT:BUF.0.LONG.V7.1.LONG.V7~INT:BUF.0.LONG.V6.1.LONG.V6
INT:MUX.0.GCLK1[0, 1, 1][0, 3, 1][0, 3, 0][0, 2, 1][0, 2, 0][0, 0, 0][0, 0, 1]
0.QUAD.V0.40011111
0.VCLK0101111
1.SINGLE.V10110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:BUF.0.LONG.V0.1.LONG.V0[0, 4, 1]
INT:BUF.0.LONG.V1.1.LONG.V1[0, 20, 1]
INT:BUF.0.LONG.V2.1.LONG.V2[0, 31, 1]
INT:BUF.0.LONG.V3.1.LONG.V3[0, 9, 1]
INT:BUF.0.LONG.V4.1.LONG.V4[0, 25, 1]
INT:BUF.0.LONG.V5.1.LONG.V5[0, 15, 1]
INT:BUF.0.LONG.V6.1.LONG.V6[0, 46, 1]
INT:BUF.0.LONG.V7.1.LONG.V7[0, 45, 1]
INT:BUF.0.LONG.V8.1.LONG.V8[0, 42, 1]
INT:BUF.1.LONG.V0.0.LONG.V0[0, 4, 0]
INT:BUF.1.LONG.V1.0.LONG.V1[0, 20, 0]
INT:BUF.1.LONG.V2.0.LONG.V2[0, 31, 0]
INT:BUF.1.LONG.V3.0.LONG.V3[0, 9, 0]
INT:BUF.1.LONG.V4.0.LONG.V4[0, 25, 0]
INT:BUF.1.LONG.V5.0.LONG.V5[0, 15, 0]
INT:BUF.1.LONG.V6.0.LONG.V6[0, 46, 0]
INT:BUF.1.LONG.V8.0.LONG.V8[0, 44, 0]
INT:BUF.1.LONG.V9.0.LONG.V9[0, 37, 1]
INT:PASS.0.QUAD.V1.4.0.VCLK[0, 43, 0]
INT:PASS.0.QUAD.V2.4.1.VCLK[0, 42, 0]
INT:PASS.1.QUAD.V0.0.1.VCLK[0, 44, 1]
INT:PASS.1.QUAD.V2.0.0.VCLK[0, 22, 0]
INT:PASS.1.SINGLE.V0.0.VCLK[0, 17, 0]
INT:PASS.1.SINGLE.V1.1.VCLK[0, 26, 1]
INT:PASS.1.SINGLE.V2.0.VCLK[0, 14, 0]
INT:PASS.1.SINGLE.V3.1.VCLK[0, 27, 0]
INT:PASS.1.SINGLE.V4.0.VCLK[0, 38, 0]
INT:PASS.1.SINGLE.V5.1.VCLK[0, 28, 0]
INT:PASS.1.SINGLE.V6.0.VCLK[0, 37, 0]
INT:PASS.1.SINGLE.V7.1.VCLK[0, 32, 0]
Inverted~[0]
INT:MUX.0.GCLK3[0, 6, 1][0, 8, 1][0, 8, 0][0, 7, 1][0, 7, 0][0, 5, 0][0, 5, 1]
0.QUAD.V1.40011111
0.VCLK0101111
1.SINGLE.V30110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK2[0, 11, 1][0, 13, 0][0, 12, 1][0, 13, 1][0, 12, 0][0, 10, 0][0, 10, 1]
0.VCLK0011111
1.SINGLE.V20101111
1.QUAD.V0.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK7[0, 17, 1][0, 19, 0][0, 18, 1][0, 19, 1][0, 18, 0][0, 16, 0][0, 16, 1]
0.VCLK0011111
1.SINGLE.V70101111
1.QUAD.V2.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK6[0, 22, 1][0, 24, 1][0, 24, 0][0, 23, 1][0, 23, 0][0, 21, 0][0, 21, 1]
0.QUAD.V2.40011111
0.VCLK0101111
1.SINGLE.V60110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK0[0, 28, 1][0, 30, 1][0, 30, 0][0, 29, 1][0, 29, 0][0, 26, 0][0, 27, 1]
0.QUAD.V0.30011111
0.VCLK0101111
1.SINGLE.V00110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK5[0, 33, 1][0, 35, 1][0, 35, 0][0, 34, 1][0, 34, 0][0, 33, 0][0, 32, 1]
0.QUAD.V2.30011111
0.VCLK0101111
1.SINGLE.V50110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.LONG.V9[0, 36, 0][0, 36, 1]
1.LONG.V900
1.VCLK01
NONE11
INT:MUX.0.GCLK4[0, 39, 1][0, 41, 0][0, 40, 1][0, 41, 1][0, 40, 0][0, 39, 0][0, 38, 1]
0.VCLK0011111
1.SINGLE.V40101111
1.QUAD.V1.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.1.LONG.V7[0, 45, 0][0, 43, 1]
0.LONG.V700
0.VCLK01
NONE11

LLVQ.IO.L.B

LLVQ.IO.L.B bittile 0
RowColumn
01234567891011121314151617181920212223242526
0 -----~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2-~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1-~INT:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.VINT:MUX.0.GCLK2[1]INT:MUX.0.GCLK2[2]INT:MUX.0.GCLK2[3]~INT:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.VINT:MUX.0.GCLK0[1]INT:MUX.0.GCLK0[2]INT:MUX.0.GCLK0[3]~INT:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.VINT:MUX.0.GCLK3[1]INT:MUX.0.GCLK3[3]INT:MUX.0.GCLK3[2]~INT:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.VINT:MUX.0.GCLK1[1]INT:MUX.0.GCLK1[2]INT:MUX.0.GCLK1[3]
1 -----~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1-INT:MUX.0.GCLK2[0]INT:MUX.0.GCLK2[6]INT:MUX.0.GCLK2[5]INT:MUX.0.GCLK2[4]INT:MUX.0.GCLK0[0]INT:MUX.0.GCLK0[6]INT:MUX.0.GCLK0[4]INT:MUX.0.GCLK0[5]INT:MUX.0.GCLK3[0]INT:MUX.0.GCLK3[6]INT:MUX.0.GCLK3[5]INT:MUX.0.GCLK3[4]INT:MUX.0.GCLK1[0]INT:MUX.0.GCLK1[6]INT:MUX.0.GCLK1[4]INT:MUX.0.GCLK1[5]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 7, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 9, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 5, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 8, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 7, 0]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 9, 0]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 5, 0]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 8, 0]
INT:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V[0, 15, 0]
INT:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V[0, 11, 0]
INT:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V[0, 19, 0]
INT:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V[0, 6, 1]
INT:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V[0, 23, 0]
Inverted~[0]
INT:MUX.0.GCLK2[0, 12, 1][0, 13, 1][0, 14, 1][0, 14, 0][0, 13, 0][0, 12, 0][0, 11, 1]
0.IO.DOUBLE.1.W.10011111
0.IO.DOUBLE.3.W.10101111
0.ECLK.V0110111
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK0[0, 16, 1][0, 18, 1][0, 17, 1][0, 18, 0][0, 17, 0][0, 16, 0][0, 15, 1]
0.IO.DOUBLE.0.W.10011111
0.IO.DOUBLE.2.W.10101111
0.BUFGE.V10110111
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK3[0, 20, 1][0, 21, 1][0, 22, 1][0, 21, 0][0, 22, 0][0, 20, 0][0, 19, 1]
0.IO.DOUBLE.1.W.20011111
0.IO.DOUBLE.3.W.20101111
0.BUFGE.V00110111
0.BUFGE.V10111011
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H01110101
1.BUFGLS.H11110110
1.BUFGLS.H21111001
1.BUFGLS.H31111010
NONE1111111
INT:MUX.0.GCLK1[0, 24, 1][0, 26, 1][0, 25, 1][0, 26, 0][0, 25, 0][0, 24, 0][0, 23, 1]
0.IO.DOUBLE.0.W.20011111
0.IO.DOUBLE.2.W.20101111
0.ECLK.V0110111
0.BUFGE.V00111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111

LLVQ.IO.L.T

LLVQ.IO.L.T bittile 0
RowColumn
01234567891011121314151617181920212223242526
0 -----~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2-~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1-~INT:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.VINT:MUX.0.GCLK2[1]INT:MUX.0.GCLK2[2]INT:MUX.0.GCLK2[3]~INT:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.VINT:MUX.0.GCLK0[1]INT:MUX.0.GCLK0[2]INT:MUX.0.GCLK0[3]~INT:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.VINT:MUX.0.GCLK3[1]INT:MUX.0.GCLK3[2]INT:MUX.0.GCLK3[3]~INT:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.VINT:MUX.0.GCLK1[1]INT:MUX.0.GCLK1[3]INT:MUX.0.GCLK1[2]
1 -----~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1-INT:MUX.0.GCLK2[0]INT:MUX.0.GCLK2[6]INT:MUX.0.GCLK2[5]INT:MUX.0.GCLK2[4]INT:MUX.0.GCLK0[0]INT:MUX.0.GCLK0[6]INT:MUX.0.GCLK0[4]INT:MUX.0.GCLK0[5]INT:MUX.0.GCLK3[0]INT:MUX.0.GCLK3[6]INT:MUX.0.GCLK3[5]INT:MUX.0.GCLK3[4]INT:MUX.0.GCLK1[0]INT:MUX.0.GCLK1[6]INT:MUX.0.GCLK1[4]INT:MUX.0.GCLK1[5]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 7, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 9, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 5, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 8, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 7, 0]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 9, 0]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 5, 0]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 8, 0]
INT:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V[0, 15, 0]
INT:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V[0, 11, 0]
INT:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V[0, 19, 0]
INT:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V[0, 6, 1]
INT:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V[0, 23, 0]
Inverted~[0]
INT:MUX.0.GCLK2[0, 12, 1][0, 13, 1][0, 14, 1][0, 14, 0][0, 13, 0][0, 12, 0][0, 11, 1]
0.IO.DOUBLE.1.W.10011111
0.IO.DOUBLE.3.W.10101111
1.ECLK.V0110111
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK0[0, 16, 1][0, 18, 1][0, 17, 1][0, 18, 0][0, 17, 0][0, 16, 0][0, 15, 1]
0.IO.DOUBLE.0.W.10011111
0.IO.DOUBLE.2.W.10101111
0.BUFGE.V00110111
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK3[0, 20, 1][0, 21, 1][0, 22, 1][0, 22, 0][0, 21, 0][0, 20, 0][0, 19, 1]
0.IO.DOUBLE.1.W.20011111
0.IO.DOUBLE.3.W.20101111
0.BUFGE.V00110111
0.BUFGE.V10111011
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK1[0, 24, 1][0, 26, 1][0, 25, 1][0, 25, 0][0, 26, 0][0, 24, 0][0, 23, 1]
0.IO.DOUBLE.0.W.20011111
0.IO.DOUBLE.2.W.20101111
0.BUFGE.V10110111
1.ECLK.V0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H01110101
1.BUFGLS.H11110110
1.BUFGLS.H21111001
1.BUFGLS.H31111010
NONE1111111

LLVQ.IO.R.B

LLVQ.IO.R.B bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
0 INT:MUX.0.GCLK3[1]~INT:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.VINT:MUX.0.GCLK3[3]INT:MUX.0.GCLK3[2]INT:MUX.0.GCLK1[1]~INT:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.VINT:MUX.0.GCLK1[2]INT:MUX.0.GCLK1[3]INT:MUX.0.GCLK0[1]~INT:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.VINT:MUX.0.GCLK0[2]INT:MUX.0.GCLK0[3]INT:MUX.0.GCLK2[1]-INT:MUX.0.GCLK2[2]INT:MUX.0.GCLK2[3]~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:PASS.1.SINGLE.V1.1.VCLKINT:MUX.0.LONG.V9[1]~INT:BUF.1.LONG.V8.0.LONG.V8~INT:PASS.1.SINGLE.V0.0.VCLKINT:MUX.1.LONG.V7[1]~INT:BUF.1.LONG.V6.0.LONG.V6~INT:BUF.1.LONG.V1.0.LONG.V1~INT:PASS.1.SINGLE.V2.0.VCLK~INT:BUF.1.LONG.V4.0.LONG.V4~INT:PASS.1.QUAD.V0.0.1.VCLK~INT:BUF.1.LONG.V0.0.LONG.V0~INT:PASS.0.QUAD.V2.4.1.VCLK~INT:BUF.1.LONG.V2.0.LONG.V2~INT:BUF.1.LONG.V3.0.LONG.V3~INT:BUF.1.LONG.V5.0.LONG.V5~INT:PASS.1.SINGLE.V7.1.VCLKINT:MUX.0.GCLK7[1]INT:MUX.0.GCLK7[2]INT:MUX.0.GCLK7[5]INT:MUX.0.GCLK6[1]~INT:PASS.1.SINGLE.V6.0.VCLKINT:MUX.0.GCLK6[2]INT:MUX.0.GCLK6[4]INT:MUX.0.GCLK5[1]~INT:PASS.1.SINGLE.V5.1.VCLKINT:MUX.0.GCLK5[2]INT:MUX.0.GCLK5[4]~INT:PASS.1.SINGLE.V4.0.VCLKINT:MUX.0.GCLK4[1]INT:MUX.0.GCLK4[2]INT:MUX.0.GCLK4[5]
1 INT:MUX.0.GCLK3[0]INT:MUX.0.GCLK3[6]INT:MUX.0.GCLK3[5]INT:MUX.0.GCLK3[4]INT:MUX.0.GCLK1[0]INT:MUX.0.GCLK1[6]INT:MUX.0.GCLK1[4]INT:MUX.0.GCLK1[5]INT:MUX.0.GCLK0[0]INT:MUX.0.GCLK0[6]INT:MUX.0.GCLK0[4]INT:MUX.0.GCLK0[5]INT:MUX.0.GCLK2[0]INT:MUX.0.GCLK2[6]INT:MUX.0.GCLK2[5]INT:MUX.0.GCLK2[4]~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0INT:MUX.0.LONG.V9[0]~INT:BUF.1.LONG.V9.0.LONG.V9~INT:BUF.0.LONG.V8.1.LONG.V8INT:MUX.1.LONG.V7[0]~INT:BUF.0.LONG.V7.1.LONG.V7~INT:BUF.0.LONG.V6.1.LONG.V6~INT:BUF.0.LONG.V1.1.LONG.V1~INT:PASS.1.SINGLE.V3.1.VCLK~INT:BUF.0.LONG.V4.1.LONG.V4~INT:PASS.0.QUAD.V1.4.0.VCLK~INT:BUF.0.LONG.V0.1.LONG.V0~INT:PASS.1.QUAD.V2.0.0.VCLK~INT:BUF.0.LONG.V2.1.LONG.V2~INT:BUF.0.LONG.V3.1.LONG.V3~INT:BUF.0.LONG.V5.1.LONG.V5INT:MUX.0.GCLK7[0]INT:MUX.0.GCLK7[6]INT:MUX.0.GCLK7[4]INT:MUX.0.GCLK7[3]INT:MUX.0.GCLK6[0]INT:MUX.0.GCLK6[6]INT:MUX.0.GCLK6[3]INT:MUX.0.GCLK6[5]INT:MUX.0.GCLK5[0]INT:MUX.0.GCLK5[6]INT:MUX.0.GCLK5[3]INT:MUX.0.GCLK5[5]INT:MUX.0.GCLK4[0]INT:MUX.0.GCLK4[6]INT:MUX.0.GCLK4[4]INT:MUX.0.GCLK4[3]
INT:MUX.0.GCLK3[0, 1, 1][0, 2, 1][0, 3, 1][0, 2, 0][0, 3, 0][0, 0, 0][0, 0, 1]
0.IO.DOUBLE.1.E.00011111
0.IO.DOUBLE.3.E.00101111
0.BUFGE.V00110111
0.BUFGE.V10111011
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H01110101
1.BUFGLS.H11110110
1.BUFGLS.H21111001
1.BUFGLS.H31111010
NONE1111111
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 20, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 16, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 18, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 17, 1]
INT:BUF.0.LONG.V0.1.LONG.V0[0, 31, 1]
INT:BUF.0.LONG.V1.1.LONG.V1[0, 27, 1]
INT:BUF.0.LONG.V2.1.LONG.V2[0, 33, 1]
INT:BUF.0.LONG.V3.1.LONG.V3[0, 34, 1]
INT:BUF.0.LONG.V4.1.LONG.V4[0, 29, 1]
INT:BUF.0.LONG.V5.1.LONG.V5[0, 35, 1]
INT:BUF.0.LONG.V6.1.LONG.V6[0, 26, 1]
INT:BUF.0.LONG.V7.1.LONG.V7[0, 25, 1]
INT:BUF.0.LONG.V8.1.LONG.V8[0, 23, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 20, 0]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 16, 0]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 18, 0]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 17, 0]
INT:BUF.1.LONG.V0.0.LONG.V0[0, 31, 0]
INT:BUF.1.LONG.V1.0.LONG.V1[0, 27, 0]
INT:BUF.1.LONG.V2.0.LONG.V2[0, 33, 0]
INT:BUF.1.LONG.V3.0.LONG.V3[0, 34, 0]
INT:BUF.1.LONG.V4.0.LONG.V4[0, 29, 0]
INT:BUF.1.LONG.V5.0.LONG.V5[0, 35, 0]
INT:BUF.1.LONG.V6.0.LONG.V6[0, 26, 0]
INT:BUF.1.LONG.V8.0.LONG.V8[0, 23, 0]
INT:BUF.1.LONG.V9.0.LONG.V9[0, 22, 1]
INT:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V[0, 19, 0]
INT:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V[0, 9, 0]
INT:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V[0, 5, 0]
INT:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V[0, 1, 0]
INT:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V[0, 19, 1]
INT:PASS.0.QUAD.V1.4.0.VCLK[0, 30, 1]
INT:PASS.0.QUAD.V2.4.1.VCLK[0, 32, 0]
INT:PASS.1.QUAD.V0.0.1.VCLK[0, 30, 0]
INT:PASS.1.QUAD.V2.0.0.VCLK[0, 32, 1]
INT:PASS.1.SINGLE.V0.0.VCLK[0, 24, 0]
INT:PASS.1.SINGLE.V1.1.VCLK[0, 21, 0]
INT:PASS.1.SINGLE.V2.0.VCLK[0, 28, 0]
INT:PASS.1.SINGLE.V3.1.VCLK[0, 28, 1]
INT:PASS.1.SINGLE.V4.0.VCLK[0, 48, 0]
INT:PASS.1.SINGLE.V5.1.VCLK[0, 45, 0]
INT:PASS.1.SINGLE.V6.0.VCLK[0, 41, 0]
INT:PASS.1.SINGLE.V7.1.VCLK[0, 36, 0]
Inverted~[0]
INT:MUX.0.GCLK1[0, 5, 1][0, 7, 1][0, 6, 1][0, 7, 0][0, 6, 0][0, 4, 0][0, 4, 1]
0.IO.DOUBLE.0.E.00011111
0.IO.DOUBLE.2.E.00101111
0.ECLK.V0110111
0.BUFGE.V00111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK0[0, 9, 1][0, 11, 1][0, 10, 1][0, 11, 0][0, 10, 0][0, 8, 0][0, 8, 1]
0.IO.DOUBLE.0.E.10011111
0.IO.DOUBLE.2.E.10101111
0.BUFGE.V10110111
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK2[0, 13, 1][0, 14, 1][0, 15, 1][0, 15, 0][0, 14, 0][0, 12, 0][0, 12, 1]
0.IO.DOUBLE.1.E.10011111
0.IO.DOUBLE.3.E.10101111
0.ECLK.V0110111
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.LONG.V9[0, 22, 0][0, 21, 1]
1.LONG.V900
1.VCLK01
NONE11
INT:MUX.1.LONG.V7[0, 25, 0][0, 24, 1]
0.LONG.V700
0.VCLK01
NONE11
INT:MUX.0.GCLK7[0, 37, 1][0, 39, 0][0, 38, 1][0, 39, 1][0, 38, 0][0, 37, 0][0, 36, 1]
0.VCLK0011111
1.SINGLE.V70101111
1.QUAD.V2.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK6[0, 41, 1][0, 43, 1][0, 43, 0][0, 42, 1][0, 42, 0][0, 40, 0][0, 40, 1]
0.QUAD.V2.40011111
0.VCLK0101111
1.SINGLE.V60110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK5[0, 45, 1][0, 47, 1][0, 47, 0][0, 46, 1][0, 46, 0][0, 44, 0][0, 44, 1]
0.QUAD.V2.30011111
0.VCLK0101111
1.SINGLE.V50110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK4[0, 49, 1][0, 51, 0][0, 50, 1][0, 51, 1][0, 50, 0][0, 49, 0][0, 48, 1]
0.VCLK0011111
1.SINGLE.V40101111
1.QUAD.V1.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111

LLVQ.IO.R.T

LLVQ.IO.R.T bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
0 INT:MUX.0.GCLK3[1]~INT:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.VINT:MUX.0.GCLK3[2]INT:MUX.0.GCLK3[3]INT:MUX.0.GCLK1[1]~INT:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.VINT:MUX.0.GCLK1[3]INT:MUX.0.GCLK1[2]INT:MUX.0.GCLK0[1]~INT:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.VINT:MUX.0.GCLK0[2]INT:MUX.0.GCLK0[3]INT:MUX.0.GCLK2[1]-INT:MUX.0.GCLK2[2]INT:MUX.0.GCLK2[3]~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0~INT:PASS.1.SINGLE.V1.1.VCLKINT:MUX.0.LONG.V9[1]~INT:BUF.1.LONG.V8.0.LONG.V8~INT:PASS.1.SINGLE.V0.0.VCLKINT:MUX.1.LONG.V7[1]~INT:BUF.1.LONG.V6.0.LONG.V6~INT:BUF.1.LONG.V1.0.LONG.V1~INT:PASS.1.SINGLE.V2.0.VCLK~INT:BUF.1.LONG.V4.0.LONG.V4~INT:PASS.1.QUAD.V0.0.1.VCLK~INT:BUF.1.LONG.V0.0.LONG.V0~INT:PASS.0.QUAD.V2.4.1.VCLK~INT:BUF.1.LONG.V2.0.LONG.V2~INT:BUF.1.LONG.V3.0.LONG.V3~INT:BUF.1.LONG.V5.0.LONG.V5~INT:PASS.1.SINGLE.V7.1.VCLKINT:MUX.0.GCLK7[1]INT:MUX.0.GCLK7[2]INT:MUX.0.GCLK7[5]INT:MUX.0.GCLK6[1]~INT:PASS.1.SINGLE.V6.0.VCLKINT:MUX.0.GCLK6[2]INT:MUX.0.GCLK6[4]INT:MUX.0.GCLK5[1]~INT:PASS.1.SINGLE.V5.1.VCLKINT:MUX.0.GCLK5[2]INT:MUX.0.GCLK5[4]~INT:PASS.1.SINGLE.V4.0.VCLKINT:MUX.0.GCLK4[1]INT:MUX.0.GCLK4[2]INT:MUX.0.GCLK4[5]
1 INT:MUX.0.GCLK3[0]INT:MUX.0.GCLK3[6]INT:MUX.0.GCLK3[5]INT:MUX.0.GCLK3[4]INT:MUX.0.GCLK1[0]INT:MUX.0.GCLK1[6]INT:MUX.0.GCLK1[4]INT:MUX.0.GCLK1[5]INT:MUX.0.GCLK0[0]INT:MUX.0.GCLK0[6]INT:MUX.0.GCLK0[4]INT:MUX.0.GCLK0[5]INT:MUX.0.GCLK2[0]INT:MUX.0.GCLK2[6]INT:MUX.0.GCLK2[5]INT:MUX.0.GCLK2[4]~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2~INT:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0INT:MUX.0.LONG.V9[0]~INT:BUF.1.LONG.V9.0.LONG.V9~INT:BUF.0.LONG.V8.1.LONG.V8INT:MUX.1.LONG.V7[0]~INT:BUF.0.LONG.V7.1.LONG.V7~INT:BUF.0.LONG.V6.1.LONG.V6~INT:BUF.0.LONG.V1.1.LONG.V1~INT:PASS.1.SINGLE.V3.1.VCLK~INT:BUF.0.LONG.V4.1.LONG.V4~INT:PASS.0.QUAD.V1.4.0.VCLK~INT:BUF.0.LONG.V0.1.LONG.V0~INT:PASS.1.QUAD.V2.0.0.VCLK~INT:BUF.0.LONG.V2.1.LONG.V2~INT:BUF.0.LONG.V3.1.LONG.V3~INT:BUF.0.LONG.V5.1.LONG.V5INT:MUX.0.GCLK7[0]INT:MUX.0.GCLK7[6]INT:MUX.0.GCLK7[4]INT:MUX.0.GCLK7[3]INT:MUX.0.GCLK6[0]INT:MUX.0.GCLK6[6]INT:MUX.0.GCLK6[3]INT:MUX.0.GCLK6[5]INT:MUX.0.GCLK5[0]INT:MUX.0.GCLK5[6]INT:MUX.0.GCLK5[3]INT:MUX.0.GCLK5[5]INT:MUX.0.GCLK4[0]INT:MUX.0.GCLK4[6]INT:MUX.0.GCLK4[4]INT:MUX.0.GCLK4[3]
INT:MUX.0.GCLK3[0, 1, 1][0, 2, 1][0, 3, 1][0, 3, 0][0, 2, 0][0, 0, 0][0, 0, 1]
0.IO.DOUBLE.1.E.00011111
0.IO.DOUBLE.3.E.00101111
0.BUFGE.V00110111
0.BUFGE.V10111011
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0[0, 20, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1[0, 16, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2[0, 18, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3[0, 17, 1]
INT:BUF.0.LONG.V0.1.LONG.V0[0, 31, 1]
INT:BUF.0.LONG.V1.1.LONG.V1[0, 27, 1]
INT:BUF.0.LONG.V2.1.LONG.V2[0, 33, 1]
INT:BUF.0.LONG.V3.1.LONG.V3[0, 34, 1]
INT:BUF.0.LONG.V4.1.LONG.V4[0, 29, 1]
INT:BUF.0.LONG.V5.1.LONG.V5[0, 35, 1]
INT:BUF.0.LONG.V6.1.LONG.V6[0, 26, 1]
INT:BUF.0.LONG.V7.1.LONG.V7[0, 25, 1]
INT:BUF.0.LONG.V8.1.LONG.V8[0, 23, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0[0, 20, 0]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1[0, 16, 0]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2[0, 18, 0]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3[0, 17, 0]
INT:BUF.1.LONG.V0.0.LONG.V0[0, 31, 0]
INT:BUF.1.LONG.V1.0.LONG.V1[0, 27, 0]
INT:BUF.1.LONG.V2.0.LONG.V2[0, 33, 0]
INT:BUF.1.LONG.V3.0.LONG.V3[0, 34, 0]
INT:BUF.1.LONG.V4.0.LONG.V4[0, 29, 0]
INT:BUF.1.LONG.V5.0.LONG.V5[0, 35, 0]
INT:BUF.1.LONG.V6.0.LONG.V6[0, 26, 0]
INT:BUF.1.LONG.V8.0.LONG.V8[0, 23, 0]
INT:BUF.1.LONG.V9.0.LONG.V9[0, 22, 1]
INT:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V[0, 19, 0]
INT:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V[0, 9, 0]
INT:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V[0, 5, 0]
INT:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V[0, 1, 0]
INT:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V[0, 19, 1]
INT:PASS.0.QUAD.V1.4.0.VCLK[0, 30, 1]
INT:PASS.0.QUAD.V2.4.1.VCLK[0, 32, 0]
INT:PASS.1.QUAD.V0.0.1.VCLK[0, 30, 0]
INT:PASS.1.QUAD.V2.0.0.VCLK[0, 32, 1]
INT:PASS.1.SINGLE.V0.0.VCLK[0, 24, 0]
INT:PASS.1.SINGLE.V1.1.VCLK[0, 21, 0]
INT:PASS.1.SINGLE.V2.0.VCLK[0, 28, 0]
INT:PASS.1.SINGLE.V3.1.VCLK[0, 28, 1]
INT:PASS.1.SINGLE.V4.0.VCLK[0, 48, 0]
INT:PASS.1.SINGLE.V5.1.VCLK[0, 45, 0]
INT:PASS.1.SINGLE.V6.0.VCLK[0, 41, 0]
INT:PASS.1.SINGLE.V7.1.VCLK[0, 36, 0]
Inverted~[0]
INT:MUX.0.GCLK1[0, 5, 1][0, 7, 1][0, 6, 1][0, 6, 0][0, 7, 0][0, 4, 0][0, 4, 1]
0.IO.DOUBLE.0.E.00011111
0.IO.DOUBLE.2.E.00101111
0.BUFGE.V10110111
1.ECLK.V0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H01110101
1.BUFGLS.H11110110
1.BUFGLS.H21111001
1.BUFGLS.H31111010
NONE1111111
INT:MUX.0.GCLK0[0, 9, 1][0, 11, 1][0, 10, 1][0, 11, 0][0, 10, 0][0, 8, 0][0, 8, 1]
0.IO.DOUBLE.0.E.10011111
0.IO.DOUBLE.2.E.10101111
0.BUFGE.V00110111
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.GCLK2[0, 13, 1][0, 14, 1][0, 15, 1][0, 15, 0][0, 14, 0][0, 12, 0][0, 12, 1]
0.IO.DOUBLE.1.E.10011111
0.IO.DOUBLE.3.E.10101111
1.ECLK.V0110111
1.BUFGLS.H61011101
1.BUFGLS.H71011110
1.BUFGLS.H41101101
1.BUFGLS.H51101110
1.BUFGLS.H21110101
1.BUFGLS.H31110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
1.OUT.BUFF1111111
INT:MUX.0.LONG.V9[0, 22, 0][0, 21, 1]
1.LONG.V900
1.VCLK01
NONE11
INT:MUX.1.LONG.V7[0, 25, 0][0, 24, 1]
0.LONG.V700
0.VCLK01
NONE11
INT:MUX.0.GCLK7[0, 37, 1][0, 39, 0][0, 38, 1][0, 39, 1][0, 38, 0][0, 37, 0][0, 36, 1]
0.VCLK0011111
1.SINGLE.V70101111
1.QUAD.V2.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK6[0, 41, 1][0, 43, 1][0, 43, 0][0, 42, 1][0, 42, 0][0, 40, 0][0, 40, 1]
0.QUAD.V2.40011111
0.VCLK0101111
1.SINGLE.V60110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK5[0, 45, 1][0, 47, 1][0, 47, 0][0, 46, 1][0, 46, 0][0, 44, 0][0, 44, 1]
0.QUAD.V2.30011111
0.VCLK0101111
1.SINGLE.V50110111
1.VCLK0111011
1.BUFGLS.H41011101
1.BUFGLS.H51011110
1.BUFGLS.H21101101
1.BUFGLS.H31101110
1.BUFGLS.H61110101
1.BUFGLS.H71110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111
INT:MUX.0.GCLK4[0, 49, 1][0, 51, 0][0, 50, 1][0, 51, 1][0, 50, 0][0, 49, 0][0, 48, 1]
0.VCLK0011111
1.SINGLE.V40101111
1.QUAD.V1.00110111
1.VCLK0111011
1.BUFGLS.H21011101
1.BUFGLS.H31011110
1.BUFGLS.H61101101
1.BUFGLS.H71101110
1.BUFGLS.H41110101
1.BUFGLS.H51110110
1.BUFGLS.H01111001
1.BUFGLS.H11111010
NONE1111111