Clock interconnect
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Clock source — spine bottom and top
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Bitstream — bottom tiles
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CLKB.FC
| CLKB.FC bittile 0 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | INT:MUX.OMUX10.N[0] |
| 1 | - |
| 2 | - |
| 3 | - |
| 4 | - |
| 5 | INT:MUX.CLK.IMUX.CLK0[0] |
| 6 | INT:MUX.CLK.IMUX.CLK0[1] |
| 7 | - |
| 8 | INT:MUX.CLK.IMUX.CLK0[2] |
| 9 | INT:MUX.CLK.IMUX.CLK0[3] |
| 10 | BUFG0:MUX.CLK[0] |
| 11 | - |
| 12 | - |
| 13 | BUFG0:MUX.CLK[1] |
| 14 | BUFG1:MUX.CLK[0] |
| 15 | - |
| 16 | - |
| 17 | BUFG1:MUX.CLK[1] |
| 18 | - |
| 19 | INT:MUX.CLK.IMUX.CLK1[2] |
| 20 | INT:MUX.CLK.IMUX.CLK1[3] |
| 21 | - |
| 22 | INT:MUX.CLK.IMUX.CLK1[0] |
| 23 | INT:MUX.CLK.IMUX.CLK1[1] |
| 24 | - |
| 25 | - |
| 26 | - |
| 27 | - |
| 28 | BUFG2:MUX.CLK[0] |
| 29 | - |
| 30 | - |
| 31 | BUFG2:MUX.CLK[1] |
| 32 | - |
| 33 | INT:MUX.CLK.IMUX.CLK2[2] |
| 34 | INT:MUX.CLK.IMUX.CLK2[3] |
| 35 | - |
| 36 | INT:MUX.CLK.IMUX.CLK2[0] |
| 37 | INT:MUX.CLK.IMUX.CLK2[1] |
| 38 | - |
| 39 | - |
| 40 | - |
| 41 | - |
| 42 | INT:MUX.OMUX12.N[0] |
| 43 | INT:MUX.OMUX15.N[0] |
| 44 | INT:MUX.OMUX12.N[2] |
| 45 | INT:MUX.OMUX12.N[1] |
| 46 | INT:MUX.OMUX15.N[1] |
| 47 | INT:MUX.OMUX15.N[2] |
| 48 | BUFG3:MUX.CLK[0] |
| 49 | - |
| 50 | - |
| 51 | BUFG3:MUX.CLK[1] |
| 52 | - |
| 53 | INT:MUX.CLK.IMUX.CLK3[2] |
| 54 | INT:MUX.CLK.IMUX.CLK3[3] |
| 55 | - |
| 56 | INT:MUX.CLK.IMUX.CLK3[0] |
| 57 | INT:MUX.CLK.IMUX.CLK3[1] |
| CLKB.FC bittile 1 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | - |
| 1 | - |
| 2 | - |
| 3 | - |
| 4 | - |
| 5 | - |
| 6 | - |
| 7 | INT:MUX.OMUX11.N[1] |
| 8 | INT:MUX.OMUX10.N[2] |
| 9 | INT:MUX.OMUX10.N[1] |
| 10 | INT:MUX.OMUX11.N[0] |
| 11 | INT:MUX.OMUX11.N[2] |
| INT:MUX.OMUX10.N | [1, 0, 8] | [1, 0, 9] | [0, 0, 0] |
|---|---|---|---|
| INT:MUX.OMUX11.N | [1, 0, 11] | [1, 0, 7] | [1, 0, 10] |
| INT:MUX.OMUX12.N | [0, 0, 44] | [0, 0, 45] | [0, 0, 42] |
| INT:MUX.OMUX15.N | [0, 0, 47] | [0, 0, 46] | [0, 0, 43] |
| NONE | 0 | 0 | 0 |
| CLK.OUT.2 | 0 | 0 | 1 |
| CLK.OUT.3 | 0 | 1 | 0 |
| CLK.OUT.0 | 1 | 0 | 1 |
| CLK.OUT.1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK0 | [0, 0, 9] | [0, 0, 8] | [0, 0, 6] | [0, 0, 5] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W0.2 | 0 | 0 | 0 | 1 |
| DBL.W1.2 | 0 | 0 | 1 | 0 |
| DBL.W0.1 | 0 | 1 | 0 | 1 |
| DBL.W1.1 | 0 | 1 | 1 | 0 |
| DBL.E0.1 | 1 | 0 | 0 | 1 |
| DBL.E1.1 | 1 | 0 | 1 | 0 |
| DBL.E0.0 | 1 | 1 | 0 | 1 |
| DBL.E1.0 | 1 | 1 | 1 | 0 |
| BUFG0:MUX.CLK | [0, 0, 13] | [0, 0, 10] |
|---|---|---|
| BUFG1:MUX.CLK | [0, 0, 17] | [0, 0, 14] |
| BUFG2:MUX.CLK | [0, 0, 31] | [0, 0, 28] |
| BUFG3:MUX.CLK | [0, 0, 51] | [0, 0, 48] |
| INT | 0 | 1 |
| CKI | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK1 | [0, 0, 20] | [0, 0, 19] | [0, 0, 23] | [0, 0, 22] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W2.2 | 0 | 0 | 0 | 1 |
| DBL.W3.2 | 0 | 0 | 1 | 0 |
| DBL.W2.1 | 0 | 1 | 0 | 1 |
| DBL.W3.1 | 0 | 1 | 1 | 0 |
| DBL.E2.1 | 1 | 0 | 0 | 1 |
| DBL.E3.1 | 1 | 0 | 1 | 0 |
| DBL.E2.0 | 1 | 1 | 0 | 1 |
| DBL.E3.0 | 1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK2 | [0, 0, 34] | [0, 0, 33] | [0, 0, 37] | [0, 0, 36] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W4.2 | 0 | 0 | 0 | 1 |
| DBL.W5.2 | 0 | 0 | 1 | 0 |
| DBL.W4.1 | 0 | 1 | 0 | 1 |
| DBL.W5.1 | 0 | 1 | 1 | 0 |
| DBL.E4.1 | 1 | 0 | 0 | 1 |
| DBL.E5.1 | 1 | 0 | 1 | 0 |
| DBL.E4.0 | 1 | 1 | 0 | 1 |
| DBL.E5.0 | 1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK3 | [0, 0, 54] | [0, 0, 53] | [0, 0, 57] | [0, 0, 56] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W6.2 | 0 | 0 | 0 | 1 |
| DBL.W7.2 | 0 | 0 | 1 | 0 |
| DBL.W6.1 | 0 | 1 | 0 | 1 |
| DBL.W7.1 | 0 | 1 | 1 | 0 |
| DBL.E6.1 | 1 | 0 | 0 | 1 |
| DBL.E7.1 | 1 | 0 | 1 | 0 |
| DBL.E6.0 | 1 | 1 | 0 | 1 |
| DBL.E7.0 | 1 | 1 | 1 | 0 |
Bitstream — top tiles
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CLKT.FC
| CLKT.FC bittile 0 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | - |
| 1 | - |
| 2 | - |
| 3 | - |
| 4 | - |
| 5 | - |
| 6 | INT:MUX.CLK.IMUX.CLK0[0] |
| 7 | INT:MUX.CLK.IMUX.CLK0[1] |
| 8 | - |
| 9 | INT:MUX.CLK.IMUX.CLK0[3] |
| 10 | INT:MUX.CLK.IMUX.CLK0[2] |
| 11 | - |
| 12 | BUFG0:MUX.CLK[1] |
| 13 | - |
| 14 | - |
| 15 | BUFG0:MUX.CLK[0] |
| 16 | INT:MUX.OMUX5.S[2] |
| 17 | INT:MUX.OMUX5.S[1] |
| 18 | INT:MUX.OMUX4.S[1] |
| 19 | INT:MUX.OMUX4.S[2] |
| 20 | INT:MUX.OMUX5.S[0] |
| 21 | INT:MUX.OMUX4.S[0] |
| 22 | - |
| 23 | - |
| 24 | - |
| 25 | - |
| 26 | INT:MUX.CLK.IMUX.CLK1[0] |
| 27 | INT:MUX.CLK.IMUX.CLK1[1] |
| 28 | - |
| 29 | INT:MUX.CLK.IMUX.CLK1[3] |
| 30 | INT:MUX.CLK.IMUX.CLK1[2] |
| 31 | - |
| 32 | BUFG1:MUX.CLK[1] |
| 33 | - |
| 34 | - |
| 35 | BUFG1:MUX.CLK[0] |
| 36 | - |
| 37 | - |
| 38 | - |
| 39 | - |
| 40 | INT:MUX.CLK.IMUX.CLK2[0] |
| 41 | INT:MUX.CLK.IMUX.CLK2[1] |
| 42 | - |
| 43 | INT:MUX.CLK.IMUX.CLK2[3] |
| 44 | INT:MUX.CLK.IMUX.CLK2[2] |
| 45 | - |
| 46 | BUFG2:MUX.CLK[1] |
| 47 | - |
| 48 | - |
| 49 | BUFG2:MUX.CLK[0] |
| 50 | BUFG3:MUX.CLK[1] |
| 51 | - |
| 52 | - |
| 53 | BUFG3:MUX.CLK[0] |
| 54 | INT:MUX.CLK.IMUX.CLK3[3] |
| 55 | INT:MUX.CLK.IMUX.CLK3[2] |
| 56 | - |
| 57 | INT:MUX.CLK.IMUX.CLK3[0] |
| 58 | INT:MUX.CLK.IMUX.CLK3[1] |
| 59 | - |
| 60 | - |
| 61 | - |
| 62 | - |
| 63 | INT:MUX.OMUX0.S[0] |
| CLKT.FC bittile 1 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | INT:MUX.OMUX3.S[2] |
| 1 | INT:MUX.OMUX3.S[0] |
| 2 | INT:MUX.OMUX0.S[1] |
| 3 | INT:MUX.OMUX0.S[2] |
| 4 | INT:MUX.OMUX3.S[1] |
| INT:MUX.CLK.IMUX.CLK0 | [0, 0, 9] | [0, 0, 10] | [0, 0, 7] | [0, 0, 6] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W0.2 | 0 | 0 | 0 | 1 |
| DBL.W1.2 | 0 | 0 | 1 | 0 |
| DBL.W0.1 | 0 | 1 | 0 | 1 |
| DBL.W1.1 | 0 | 1 | 1 | 0 |
| DBL.E0.1 | 1 | 0 | 0 | 1 |
| DBL.E1.1 | 1 | 0 | 1 | 0 |
| DBL.E0.0 | 1 | 1 | 0 | 1 |
| DBL.E1.0 | 1 | 1 | 1 | 0 |
| BUFG0:MUX.CLK | [0, 0, 12] | [0, 0, 15] |
|---|---|---|
| BUFG1:MUX.CLK | [0, 0, 32] | [0, 0, 35] |
| BUFG2:MUX.CLK | [0, 0, 46] | [0, 0, 49] |
| BUFG3:MUX.CLK | [0, 0, 50] | [0, 0, 53] |
| INT | 0 | 1 |
| CKI | 1 | 0 |
| INT:MUX.OMUX0.S | [1, 0, 3] | [1, 0, 2] | [0, 0, 63] |
|---|---|---|---|
| INT:MUX.OMUX3.S | [1, 0, 0] | [1, 0, 4] | [1, 0, 1] |
| INT:MUX.OMUX4.S | [0, 0, 19] | [0, 0, 18] | [0, 0, 21] |
| INT:MUX.OMUX5.S | [0, 0, 16] | [0, 0, 17] | [0, 0, 20] |
| NONE | 0 | 0 | 0 |
| CLK.OUT.2 | 0 | 0 | 1 |
| CLK.OUT.3 | 0 | 1 | 0 |
| CLK.OUT.0 | 1 | 0 | 1 |
| CLK.OUT.1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK1 | [0, 0, 29] | [0, 0, 30] | [0, 0, 27] | [0, 0, 26] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W2.2 | 0 | 0 | 0 | 1 |
| DBL.W3.2 | 0 | 0 | 1 | 0 |
| DBL.W2.1 | 0 | 1 | 0 | 1 |
| DBL.W3.1 | 0 | 1 | 1 | 0 |
| DBL.E2.1 | 1 | 0 | 0 | 1 |
| DBL.E3.1 | 1 | 0 | 1 | 0 |
| DBL.E2.0 | 1 | 1 | 0 | 1 |
| DBL.E3.0 | 1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK2 | [0, 0, 43] | [0, 0, 44] | [0, 0, 41] | [0, 0, 40] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W4.2 | 0 | 0 | 0 | 1 |
| DBL.W5.2 | 0 | 0 | 1 | 0 |
| DBL.W4.1 | 0 | 1 | 0 | 1 |
| DBL.W5.1 | 0 | 1 | 1 | 0 |
| DBL.E4.1 | 1 | 0 | 0 | 1 |
| DBL.E5.1 | 1 | 0 | 1 | 0 |
| DBL.E4.0 | 1 | 1 | 0 | 1 |
| DBL.E5.0 | 1 | 1 | 1 | 0 |
| INT:MUX.CLK.IMUX.CLK3 | [0, 0, 54] | [0, 0, 55] | [0, 0, 58] | [0, 0, 57] |
|---|---|---|---|---|
| PULLUP | 0 | 0 | 0 | 0 |
| DBL.W6.2 | 0 | 0 | 0 | 1 |
| DBL.W7.2 | 0 | 0 | 1 | 0 |
| DBL.W6.1 | 0 | 1 | 0 | 1 |
| DBL.W7.1 | 0 | 1 | 1 | 0 |
| DBL.E6.1 | 1 | 0 | 0 | 1 |
| DBL.E7.1 | 1 | 0 | 1 | 0 |
| DBL.E6.0 | 1 | 1 | 0 | 1 |
| DBL.E7.0 | 1 | 1 | 1 | 0 |
The CLKC clock center tile
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The GCLKVM secondary clock center tiles
The GCLKVM tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.
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GCLKVM.S3
| GCLKVM.S3 bittile 0 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | - |
| 1 | - |
| 2 | - |
| 3 | - |
| 4 | - |
| 5 | - |
| 6 | - |
| 7 | - |
| 8 | - |
| 9 | - |
| 10 | - |
| 11 | - |
| 12 | - |
| 13 | - |
| 14 | - |
| 15 | - |
| 16 | - |
| 17 | - |
| 18 | - |
| 19 | - |
| 20 | - |
| 21 | - |
| 22 | - |
| 23 | - |
| 24 | - |
| 25 | - |
| 26 | - |
| 27 | - |
| 28 | - |
| 29 | - |
| 30 | GCLKVM:BUF.OUT_B3 |
| 31 | GCLKVM:BUF.OUT_B4 |
| 32 | GCLKVM:BUF.OUT_B5 |
| 33 | GCLKVM:BUF.OUT_B6 |
| 34 | GCLKVM:BUF.OUT_B2 |
| 35 | GCLKVM:BUF.OUT_B7 |
| 36 | GCLKVM:BUF.OUT_B1 |
| 37 | - |
| 38 | GCLKVM:BUF.OUT_B0 |
| GCLKVM.S3 bittile 1 | |
|---|---|
| Row | Column |
| 0 | |
| 0 | - |
| 1 | - |
| 2 | - |
| 3 | - |
| 4 | - |
| 5 | - |
| 6 | - |
| 7 | - |
| 8 | - |
| 9 | - |
| 10 | - |
| 11 | - |
| 12 | - |
| 13 | - |
| 14 | - |
| 15 | - |
| 16 | - |
| 17 | - |
| 18 | - |
| 19 | - |
| 20 | - |
| 21 | - |
| 22 | - |
| 23 | - |
| 24 | - |
| 25 | GCLKVM:BUF.OUT_T0 |
| 26 | - |
| 27 | GCLKVM:BUF.OUT_T1 |
| 28 | GCLKVM:BUF.OUT_T7 |
| 29 | GCLKVM:BUF.OUT_T2 |
| 30 | GCLKVM:BUF.OUT_T6 |
| 31 | GCLKVM:BUF.OUT_T5 |
| 32 | GCLKVM:BUF.OUT_T4 |
| 33 | GCLKVM:BUF.OUT_T3 |
| GCLKVM:BUF.OUT_B0 | [0, 0, 38] |
|---|---|
| GCLKVM:BUF.OUT_B1 | [0, 0, 36] |
| GCLKVM:BUF.OUT_B2 | [0, 0, 34] |
| GCLKVM:BUF.OUT_B3 | [0, 0, 30] |
| GCLKVM:BUF.OUT_B4 | [0, 0, 31] |
| GCLKVM:BUF.OUT_B5 | [0, 0, 32] |
| GCLKVM:BUF.OUT_B6 | [0, 0, 33] |
| GCLKVM:BUF.OUT_B7 | [0, 0, 35] |
| GCLKVM:BUF.OUT_T0 | [1, 0, 25] |
| GCLKVM:BUF.OUT_T1 | [1, 0, 27] |
| GCLKVM:BUF.OUT_T2 | [1, 0, 29] |
| GCLKVM:BUF.OUT_T3 | [1, 0, 33] |
| GCLKVM:BUF.OUT_T4 | [1, 0, 32] |
| GCLKVM:BUF.OUT_T5 | [1, 0, 31] |
| GCLKVM:BUF.OUT_T6 | [1, 0, 30] |
| GCLKVM:BUF.OUT_T7 | [1, 0, 28] |
| Non-inverted | [0] |
The GCLKVC clock spine distribution tiles
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The GCLKH clock row distribution tiles
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GCLKH
| GCLKH:BUF.OUT_B0 | [0, 15, 0] |
|---|---|
| GCLKH:BUF.OUT_B1 | [0, 13, 0] |
| GCLKH:BUF.OUT_B2 | [0, 11, 0] |
| GCLKH:BUF.OUT_B3 | [0, 9, 0] |
| GCLKH:BUF.OUT_B4 | [0, 7, 0] |
| GCLKH:BUF.OUT_B5 | [0, 5, 0] |
| GCLKH:BUF.OUT_B6 | [0, 3, 0] |
| GCLKH:BUF.OUT_B7 | [0, 1, 0] |
| GCLKH:BUF.OUT_T0 | [0, 16, 0] |
| GCLKH:BUF.OUT_T1 | [0, 14, 0] |
| GCLKH:BUF.OUT_T2 | [0, 12, 0] |
| GCLKH:BUF.OUT_T3 | [0, 10, 0] |
| GCLKH:BUF.OUT_T4 | [0, 8, 0] |
| GCLKH:BUF.OUT_T5 | [0, 6, 0] |
| GCLKH:BUF.OUT_T6 | [0, 4, 0] |
| GCLKH:BUF.OUT_T7 | [0, 2, 0] |
| Non-inverted | [0] |