Input / Output

Todo

document

I/O interface

Todo

document

IOI.FC

IOI.FC bittile 0
Row	Column
	0	1	2	3
0	IBUF0:DELAY_ENABLE[0]	OBUF0:INV.O	IBUF0:DELAY_ENABLE[10]	IBUF0:READBACK_I
1	IBUF0:DELAY_ENABLE[1]	IBUF0:DELAY_ENABLE[8]	IBUF0:DELAY_ENABLE[11]	IBUF0:IFF_DELAY_ENABLE
2	IBUF0:DELAY_ENABLE[2]	IBUF0:DELAY_ENABLE[9]	-	IBUF0:ENABLE_O2IQPATH
3	IBUF0:DELAY_ENABLE[3]	~OBUF0:FF_SRVAL	~IBUF0:FF_SRVAL	-
4	IBUF0:DELAY_ENABLE[4]	-	-	IBUF0:ENABLE_O2I_O2IQ_PATH
5	IBUF0:DELAY_ENABLE[5]	-	IBUF0:DELAY_ENABLE[12]	IBUF0:DELAY_ENABLE[13]
6	IBUF0:DELAY_ENABLE[6]	-	~IBUF0:FF_INIT	IBUF0:ENABLE_O2IPATH
7	-	~OBUF0:FF_INIT	-	~IBUF0:INV.REV
8	IBUF0:DELAY_ENABLE[7]	-	IBUF0:FF_LATCH	IBUF0:I_DELAY_ENABLE
9	-	OBUF0:FF_REV_ENABLE	-	~OBUF0:INV.REV
10	-	OBUF0:FF_SR_ENABLE	IBUF0:FF_REV_ENABLE	-
11	-	OBUF0:FF_SYNC	IBUF0:FF_SR_ENABLE	~IBUF0:INV.CLK
12	-	OBUF0:OMUX[0]	-	~IBUF0:INV.CE
13	-	-	-	-
14	-	OBUF0:FF_LATCH	-	~OBUF0:INV.CLK
15	-	OBUF0:OMUX[1]	IBUF0:FF_SYNC	~IBUF0:INV.SR
16	-	-	IBUF1:FF_SYNC	~IBUF1:INV.SR
17	-	-	-	-
18	-	OBUF1:FF_LATCH	-	~OBUF1:INV.CLK
19	-	-	~IBUF1:FF_SRVAL	~IBUF1:INV.CE
20	-	OBUF1:FF_SYNC	IBUF1:FF_SR_ENABLE	-
21	-	OBUF1:FF_SR_ENABLE	IBUF1:FF_REV_ENABLE	~IBUF1:INV.CLK
22	-	OBUF1:FF_REV_ENABLE	~IBUF1:FF_INIT	~OBUF1:INV.REV
23	IBUF1:DELAY_ENABLE[0]	OBUF1:OMUX[0]	IBUF1:FF_LATCH	IBUF1:I_DELAY_ENABLE
24	-	~OBUF1:FF_INIT	-	~IBUF1:INV.REV
25	IBUF1:DELAY_ENABLE[1]	OBUF1:OMUX[1]	-	IBUF1:ENABLE_O2IPATH
26	IBUF1:DELAY_ENABLE[2]	OBUF1:INV.O	IBUF1:DELAY_ENABLE[10]	IBUF1:DELAY_ENABLE[13]
27	IBUF1:DELAY_ENABLE[3]	~OBUF1:FF_SRVAL	-	IBUF1:ENABLE_O2I_O2IQ_PATH
28	IBUF1:DELAY_ENABLE[4]	-	-	-
29	IBUF1:DELAY_ENABLE[5]	IBUF1:DELAY_ENABLE[8]	-	IBUF1:ENABLE_O2IQPATH
30	IBUF1:DELAY_ENABLE[6]	IBUF1:DELAY_ENABLE[9]	IBUF1:DELAY_ENABLE[11]	IBUF1:IFF_DELAY_ENABLE
31	IBUF1:DELAY_ENABLE[7]	-	IBUF1:DELAY_ENABLE[12]	IBUF1:READBACK_I
32	IBUF2:DELAY_ENABLE[0]	OBUF2:INV.O	IBUF2:DELAY_ENABLE[10]	IBUF2:READBACK_I
33	IBUF2:DELAY_ENABLE[1]	IBUF2:DELAY_ENABLE[8]	IBUF2:DELAY_ENABLE[11]	IBUF2:IFF_DELAY_ENABLE
34	IBUF2:DELAY_ENABLE[2]	IBUF2:DELAY_ENABLE[9]	-	IBUF2:ENABLE_O2IQPATH
35	IBUF2:DELAY_ENABLE[3]	~OBUF2:FF_SRVAL	~IBUF2:FF_SRVAL	-
36	IBUF2:DELAY_ENABLE[4]	-	-	IBUF2:ENABLE_O2I_O2IQ_PATH
37	IBUF2:DELAY_ENABLE[5]	-	IBUF2:DELAY_ENABLE[12]	IBUF2:DELAY_ENABLE[13]
38	IBUF2:DELAY_ENABLE[6]	-	~IBUF2:FF_INIT	IBUF2:ENABLE_O2IPATH
39	-	~OBUF2:FF_INIT	-	~IBUF2:INV.REV
40	IBUF2:DELAY_ENABLE[7]	-	IBUF2:FF_LATCH	IBUF2:I_DELAY_ENABLE
41	-	OBUF2:FF_REV_ENABLE	-	~OBUF2:INV.REV
42	-	OBUF2:FF_SR_ENABLE	IBUF2:FF_REV_ENABLE	-
43	-	OBUF2:FF_SYNC	IBUF2:FF_SR_ENABLE	~IBUF2:INV.CLK
44	-	OBUF2:OMUX[0]	-	~IBUF2:INV.CE
45	-	-	-	-
46	-	OBUF2:FF_LATCH	-	~OBUF2:INV.CLK
47	-	OBUF2:OMUX[1]	IBUF2:FF_SYNC	~IBUF2:INV.SR
48	-	-	IBUF3:FF_SYNC	~IBUF3:INV.SR
49	-	-	-	-
50	-	OBUF3:FF_LATCH	-	~OBUF3:INV.CLK
51	-	-	~IBUF3:FF_SRVAL	~IBUF3:INV.CE
52	-	OBUF3:FF_SYNC	IBUF3:FF_SR_ENABLE	-
53	-	OBUF3:FF_SR_ENABLE	IBUF3:FF_REV_ENABLE	~IBUF3:INV.CLK
54	-	OBUF3:FF_REV_ENABLE	~IBUF3:FF_INIT	~OBUF3:INV.REV
55	IBUF3:DELAY_ENABLE[0]	OBUF3:OMUX[0]	IBUF3:FF_LATCH	IBUF3:I_DELAY_ENABLE
56	-	~OBUF3:FF_INIT	-	~IBUF3:INV.REV
57	IBUF3:DELAY_ENABLE[1]	OBUF3:OMUX[1]	-	IBUF3:ENABLE_O2IPATH
58	IBUF3:DELAY_ENABLE[2]	OBUF3:INV.O	IBUF3:DELAY_ENABLE[10]	IBUF3:DELAY_ENABLE[13]
59	IBUF3:DELAY_ENABLE[3]	~OBUF3:FF_SRVAL	-	IBUF3:ENABLE_O2I_O2IQ_PATH
60	IBUF3:DELAY_ENABLE[4]	-	-	-
61	IBUF3:DELAY_ENABLE[5]	IBUF3:DELAY_ENABLE[8]	-	IBUF3:ENABLE_O2IQPATH
62	IBUF3:DELAY_ENABLE[6]	IBUF3:DELAY_ENABLE[9]	IBUF3:DELAY_ENABLE[11]	IBUF3:IFF_DELAY_ENABLE
63	IBUF3:DELAY_ENABLE[7]	-	IBUF3:DELAY_ENABLE[12]	IBUF3:READBACK_I

IBUF0:DELAY_ENABLE	[0, 3, 5]	[0, 2, 5]	[0, 2, 1]	[0, 2, 0]	[0, 1, 2]	[0, 1, 1]	[0, 0, 8]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
IBUF1:DELAY_ENABLE	[0, 3, 26]	[0, 2, 31]	[0, 2, 30]	[0, 2, 26]	[0, 1, 30]	[0, 1, 29]	[0, 0, 31]	[0, 0, 30]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]	[0, 0, 26]	[0, 0, 25]	[0, 0, 23]
IBUF2:DELAY_ENABLE	[0, 3, 37]	[0, 2, 37]	[0, 2, 33]	[0, 2, 32]	[0, 1, 34]	[0, 1, 33]	[0, 0, 40]	[0, 0, 38]	[0, 0, 37]	[0, 0, 36]	[0, 0, 35]	[0, 0, 34]	[0, 0, 33]	[0, 0, 32]
IBUF3:DELAY_ENABLE	[0, 3, 58]	[0, 2, 63]	[0, 2, 62]	[0, 2, 58]	[0, 1, 62]	[0, 1, 61]	[0, 0, 63]	[0, 0, 62]	[0, 0, 61]	[0, 0, 60]	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]	[0, 0, 55]
Non-inverted	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

IBUF0:ENABLE_O2IPATH	[0, 3, 6]
IBUF0:ENABLE_O2IQPATH	[0, 3, 2]
IBUF0:ENABLE_O2I_O2IQ_PATH	[0, 3, 4]
IBUF0:FF_LATCH	[0, 2, 8]
IBUF0:FF_REV_ENABLE	[0, 2, 10]
IBUF0:FF_SR_ENABLE	[0, 2, 11]
IBUF0:FF_SYNC	[0, 2, 15]
IBUF0:IFF_DELAY_ENABLE	[0, 3, 1]
IBUF0:I_DELAY_ENABLE	[0, 3, 8]
IBUF0:READBACK_I	[0, 3, 0]
IBUF1:ENABLE_O2IPATH	[0, 3, 25]
IBUF1:ENABLE_O2IQPATH	[0, 3, 29]
IBUF1:ENABLE_O2I_O2IQ_PATH	[0, 3, 27]
IBUF1:FF_LATCH	[0, 2, 23]
IBUF1:FF_REV_ENABLE	[0, 2, 21]
IBUF1:FF_SR_ENABLE	[0, 2, 20]
IBUF1:FF_SYNC	[0, 2, 16]
IBUF1:IFF_DELAY_ENABLE	[0, 3, 30]
IBUF1:I_DELAY_ENABLE	[0, 3, 23]
IBUF1:READBACK_I	[0, 3, 31]
IBUF2:ENABLE_O2IPATH	[0, 3, 38]
IBUF2:ENABLE_O2IQPATH	[0, 3, 34]
IBUF2:ENABLE_O2I_O2IQ_PATH	[0, 3, 36]
IBUF2:FF_LATCH	[0, 2, 40]
IBUF2:FF_REV_ENABLE	[0, 2, 42]
IBUF2:FF_SR_ENABLE	[0, 2, 43]
IBUF2:FF_SYNC	[0, 2, 47]
IBUF2:IFF_DELAY_ENABLE	[0, 3, 33]
IBUF2:I_DELAY_ENABLE	[0, 3, 40]
IBUF2:READBACK_I	[0, 3, 32]
IBUF3:ENABLE_O2IPATH	[0, 3, 57]
IBUF3:ENABLE_O2IQPATH	[0, 3, 61]
IBUF3:ENABLE_O2I_O2IQ_PATH	[0, 3, 59]
IBUF3:FF_LATCH	[0, 2, 55]
IBUF3:FF_REV_ENABLE	[0, 2, 53]
IBUF3:FF_SR_ENABLE	[0, 2, 52]
IBUF3:FF_SYNC	[0, 2, 48]
IBUF3:IFF_DELAY_ENABLE	[0, 3, 62]
IBUF3:I_DELAY_ENABLE	[0, 3, 55]
IBUF3:READBACK_I	[0, 3, 63]
OBUF0:FF_LATCH	[0, 1, 14]
OBUF0:FF_REV_ENABLE	[0, 1, 9]
OBUF0:FF_SR_ENABLE	[0, 1, 10]
OBUF0:FF_SYNC	[0, 1, 11]
OBUF0:INV.O	[0, 1, 0]
OBUF1:FF_LATCH	[0, 1, 18]
OBUF1:FF_REV_ENABLE	[0, 1, 22]
OBUF1:FF_SR_ENABLE	[0, 1, 21]
OBUF1:FF_SYNC	[0, 1, 20]
OBUF1:INV.O	[0, 1, 26]
OBUF2:FF_LATCH	[0, 1, 46]
OBUF2:FF_REV_ENABLE	[0, 1, 41]
OBUF2:FF_SR_ENABLE	[0, 1, 42]
OBUF2:FF_SYNC	[0, 1, 43]
OBUF2:INV.O	[0, 1, 32]
OBUF3:FF_LATCH	[0, 1, 50]
OBUF3:FF_REV_ENABLE	[0, 1, 54]
OBUF3:FF_SR_ENABLE	[0, 1, 53]
OBUF3:FF_SYNC	[0, 1, 52]
OBUF3:INV.O	[0, 1, 58]
Non-inverted	[0]

IBUF0:FF_INIT	[0, 2, 6]
IBUF0:FF_SRVAL	[0, 2, 3]
IBUF0:INV.CE	[0, 3, 12]
IBUF0:INV.CLK	[0, 3, 11]
IBUF0:INV.REV	[0, 3, 7]
IBUF0:INV.SR	[0, 3, 15]
IBUF1:FF_INIT	[0, 2, 22]
IBUF1:FF_SRVAL	[0, 2, 19]
IBUF1:INV.CE	[0, 3, 19]
IBUF1:INV.CLK	[0, 3, 21]
IBUF1:INV.REV	[0, 3, 24]
IBUF1:INV.SR	[0, 3, 16]
IBUF2:FF_INIT	[0, 2, 38]
IBUF2:FF_SRVAL	[0, 2, 35]
IBUF2:INV.CE	[0, 3, 44]
IBUF2:INV.CLK	[0, 3, 43]
IBUF2:INV.REV	[0, 3, 39]
IBUF2:INV.SR	[0, 3, 47]
IBUF3:FF_INIT	[0, 2, 54]
IBUF3:FF_SRVAL	[0, 2, 51]
IBUF3:INV.CE	[0, 3, 51]
IBUF3:INV.CLK	[0, 3, 53]
IBUF3:INV.REV	[0, 3, 56]
IBUF3:INV.SR	[0, 3, 48]
OBUF0:FF_INIT	[0, 1, 7]
OBUF0:FF_SRVAL	[0, 1, 3]
OBUF0:INV.CLK	[0, 3, 14]
OBUF0:INV.REV	[0, 3, 9]
OBUF1:FF_INIT	[0, 1, 24]
OBUF1:FF_SRVAL	[0, 1, 27]
OBUF1:INV.CLK	[0, 3, 18]
OBUF1:INV.REV	[0, 3, 22]
OBUF2:FF_INIT	[0, 1, 39]
OBUF2:FF_SRVAL	[0, 1, 35]
OBUF2:INV.CLK	[0, 3, 46]
OBUF2:INV.REV	[0, 3, 41]
OBUF3:FF_INIT	[0, 1, 56]
OBUF3:FF_SRVAL	[0, 1, 59]
OBUF3:INV.CLK	[0, 3, 50]
OBUF3:INV.REV	[0, 3, 54]
Inverted	~[0]

OBUF0:OMUX	[0, 1, 15]	[0, 1, 12]
OBUF1:OMUX	[0, 1, 25]	[0, 1, 23]
OBUF2:OMUX	[0, 1, 47]	[0, 1, 44]
OBUF3:OMUX	[0, 1, 57]	[0, 1, 55]
NONE	0	0
O	0	1
OFF	1	0

I/O buffer tiles

Todo

document

IOBS.FC.T

IOBS.FC.T bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14
0	-	-	-	-	OBUF0:ENABLE[0]	OBUF1:ENABLE[0]	-	-	-	-	-	-	OBUF2:ENABLE[0]	OBUF3:ENABLE[0]	-
1	-	-	-	OBUF0:ENABLE_MISR	OBUF0:ENABLE[1]	OBUF1:ENABLE[1]	OBUF1:ENABLE_MISR	-	-	-	-	OBUF2:ENABLE_MISR	OBUF2:ENABLE[1]	OBUF3:ENABLE[1]	OBUF3:ENABLE_MISR
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	IBUF0:ENABLE	IBUF0:ENABLE_O2IPADPATH	IBUF1:ENABLE_O2IPADPATH	IBUF1:ENABLE	-	-	-	-	IBUF2:ENABLE	IBUF2:ENABLE_O2IPADPATH	IBUF3:ENABLE_O2IPADPATH	IBUF3:ENABLE

IBUF0:ENABLE	[0, 3, 4]
IBUF0:ENABLE_O2IPADPATH	[0, 4, 4]
IBUF1:ENABLE	[0, 6, 4]
IBUF1:ENABLE_O2IPADPATH	[0, 5, 4]
IBUF2:ENABLE	[0, 11, 4]
IBUF2:ENABLE_O2IPADPATH	[0, 12, 4]
IBUF3:ENABLE	[0, 14, 4]
IBUF3:ENABLE_O2IPADPATH	[0, 13, 4]
OBUF0:ENABLE_MISR	[0, 3, 1]
OBUF1:ENABLE_MISR	[0, 6, 1]
OBUF2:ENABLE_MISR	[0, 11, 1]
OBUF3:ENABLE_MISR	[0, 14, 1]
Non-inverted	[0]

OBUF0:ENABLE	[0, 4, 1]	[0, 4, 0]
OBUF1:ENABLE	[0, 5, 1]	[0, 5, 0]
OBUF2:ENABLE	[0, 12, 1]	[0, 12, 0]
OBUF3:ENABLE	[0, 13, 1]	[0, 13, 0]
Non-inverted	[1]	[0]

IOBS.FC.R

IOBS.FC.R bittile 0
Row	Column
	0
0	-
1	-
2	-
3	-
4	-
5	-
6	-
7	-
8	-
9	-
10	OBUF0:ENABLE_MISR
11	-
12	-
13	IBUF0:ENABLE
14	OBUF0:ENABLE[0]
15	OBUF0:ENABLE[1]
16	-
17	-
18	IBUF0:ENABLE_O2IPADPATH
19	IBUF1:ENABLE_O2IPADPATH
20	-
21	-
22	OBUF1:ENABLE[0]
23	OBUF1:ENABLE[1]
24	IBUF1:ENABLE
25	-
26	-
27	OBUF1:ENABLE_MISR
28	-
29	-
30	-
31	-
32	-
33	-
34	-
35	-
36	-
37	-
38	-
39	-
40	OBUF2:ENABLE_MISR
41	-
42	-
43	IBUF2:ENABLE
44	OBUF2:ENABLE[0]
45	OBUF2:ENABLE[1]
46	-
47	-
48	IBUF2:ENABLE_O2IPADPATH
49	IBUF3:ENABLE_O2IPADPATH
50	-
51	-
52	OBUF3:ENABLE[0]
53	OBUF3:ENABLE[1]
54	IBUF3:ENABLE
55	-
56	-
57	OBUF3:ENABLE_MISR

IBUF0:ENABLE	[0, 0, 13]
IBUF0:ENABLE_O2IPADPATH	[0, 0, 18]
IBUF1:ENABLE	[0, 0, 24]
IBUF1:ENABLE_O2IPADPATH	[0, 0, 19]
IBUF2:ENABLE	[0, 0, 43]
IBUF2:ENABLE_O2IPADPATH	[0, 0, 48]
IBUF3:ENABLE	[0, 0, 54]
IBUF3:ENABLE_O2IPADPATH	[0, 0, 49]
OBUF0:ENABLE_MISR	[0, 0, 10]
OBUF1:ENABLE_MISR	[0, 0, 27]
OBUF2:ENABLE_MISR	[0, 0, 40]
OBUF3:ENABLE_MISR	[0, 0, 57]
Non-inverted	[0]

OBUF0:ENABLE	[0, 0, 15]	[0, 0, 14]
OBUF1:ENABLE	[0, 0, 23]	[0, 0, 22]
OBUF2:ENABLE	[0, 0, 45]	[0, 0, 44]
OBUF3:ENABLE	[0, 0, 53]	[0, 0, 52]
Non-inverted	[1]	[0]

IOBS.FC.B

IOBS.FC.B bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14
0	-	-	-	-	OBUF3:ENABLE[0]	OBUF2:ENABLE[0]	-	-	-	-	-	-	OBUF1:ENABLE[0]	OBUF0:ENABLE[0]	-
1	-	-	-	OBUF3:ENABLE_MISR	OBUF3:ENABLE[1]	OBUF2:ENABLE[1]	OBUF2:ENABLE_MISR	-	-	-	-	OBUF1:ENABLE_MISR	OBUF1:ENABLE[1]	OBUF0:ENABLE[1]	OBUF0:ENABLE_MISR
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	IBUF3:ENABLE	IBUF3:ENABLE_O2IPADPATH	IBUF2:ENABLE_O2IPADPATH	IBUF2:ENABLE	-	-	-	-	IBUF1:ENABLE	IBUF1:ENABLE_O2IPADPATH	IBUF0:ENABLE_O2IPADPATH	IBUF0:ENABLE

IBUF0:ENABLE	[0, 14, 4]
IBUF0:ENABLE_O2IPADPATH	[0, 13, 4]
IBUF1:ENABLE	[0, 11, 4]
IBUF1:ENABLE_O2IPADPATH	[0, 12, 4]
IBUF2:ENABLE	[0, 6, 4]
IBUF2:ENABLE_O2IPADPATH	[0, 5, 4]
IBUF3:ENABLE	[0, 3, 4]
IBUF3:ENABLE_O2IPADPATH	[0, 4, 4]
OBUF0:ENABLE_MISR	[0, 14, 1]
OBUF1:ENABLE_MISR	[0, 11, 1]
OBUF2:ENABLE_MISR	[0, 6, 1]
OBUF3:ENABLE_MISR	[0, 3, 1]
Non-inverted	[0]

OBUF0:ENABLE	[0, 13, 1]	[0, 13, 0]
OBUF1:ENABLE	[0, 12, 1]	[0, 12, 0]
OBUF2:ENABLE	[0, 5, 1]	[0, 5, 0]
OBUF3:ENABLE	[0, 4, 1]	[0, 4, 0]
Non-inverted	[1]	[0]

IOBS.FC.L

IOBS.FC.L bittile 0
Row	Column
	0
0	-
1	-
2	-
3	-
4	-
5	-
6	-
7	-
8	-
9	-
10	OBUF0:ENABLE_MISR
11	-
12	-
13	IBUF0:ENABLE
14	OBUF0:ENABLE[0]
15	OBUF0:ENABLE[1]
16	-
17	-
18	IBUF0:ENABLE_O2IPADPATH
19	IBUF1:ENABLE_O2IPADPATH
20	-
21	-
22	OBUF1:ENABLE[0]
23	OBUF1:ENABLE[1]
24	IBUF1:ENABLE
25	-
26	-
27	OBUF1:ENABLE_MISR
28	-
29	-
30	-
31	-
32	-
33	-
34	-
35	-
36	-
37	-
38	-
39	-
40	OBUF2:ENABLE_MISR
41	-
42	-
43	IBUF2:ENABLE
44	OBUF2:ENABLE[0]
45	OBUF2:ENABLE[1]
46	-
47	-
48	IBUF2:ENABLE_O2IPADPATH
49	IBUF3:ENABLE_O2IPADPATH
50	-
51	-
52	OBUF3:ENABLE[0]
53	OBUF3:ENABLE[1]
54	IBUF3:ENABLE
55	-
56	-
57	OBUF3:ENABLE_MISR

IBUF0:ENABLE	[0, 0, 13]
IBUF0:ENABLE_O2IPADPATH	[0, 0, 18]
IBUF1:ENABLE	[0, 0, 24]
IBUF1:ENABLE_O2IPADPATH	[0, 0, 19]
IBUF2:ENABLE	[0, 0, 43]
IBUF2:ENABLE_O2IPADPATH	[0, 0, 48]
IBUF3:ENABLE	[0, 0, 54]
IBUF3:ENABLE_O2IPADPATH	[0, 0, 49]
OBUF0:ENABLE_MISR	[0, 0, 10]
OBUF1:ENABLE_MISR	[0, 0, 27]
OBUF2:ENABLE_MISR	[0, 0, 40]
OBUF3:ENABLE_MISR	[0, 0, 57]
Non-inverted	[0]

OBUF0:ENABLE	[0, 0, 15]	[0, 0, 14]
OBUF1:ENABLE	[0, 0, 23]	[0, 0, 22]
OBUF2:ENABLE	[0, 0, 45]	[0, 0, 44]
OBUF3:ENABLE	[0, 0, 53]	[0, 0, 52]
Non-inverted	[1]	[0]