Corners

CNR.BL

CNR.BL bittile 0
RowColumn
012345678910111213141516171819202122232425
0 --------------------------
1 --------------------------
2 INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[5]MD2:PULL[0]MD2:PULL[1]~BUFGLS.H:ALT_PAD~BUFGLS.H:CLK_EN~BUFGLS.V:ALT_PAD------------------
3 INT:MUX.IMUX.BUFG.H[4]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[6]INT:MUX.IMUX.BUFG.H[0]--INT:MUX.IMUX.BUFG.V[4]~BUFGLS.V:CLK_EN------------------
4 -----INT:MUX.IMUX.RDBK.TRIG[3]INT:MUX.IMUX.RDBK.TRIG[2]~MISC:TM_BOTINT:MUX.IMUX.BUFG.V[3]INT:MUX.LONG.IO.H2[0]INT:MUX.LONG.IO.H2[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.IO.H0[1]~MISC:READ_CAPTUREINT:MUX.LONG.IO.H0[0]~MISC:READ_ABORTINT:MUX.LONG.IO.H3[0]INT:MUX.LONG.IO.H3[1]INT:MUX.IMUX.BUFG.V[1]INT:MUX.LONG.IO.H1[1]INT:MUX.IMUX.BUFG.V[6]INT:MUX.LONG.IO.H1[0]INT:MUX.IMUX.BUFG.V[0]MD0:PULL[0]MD0:PULL[1]-
5 INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]----INT:MUX.LONG.IO.V3[3]INT:MUX.LONG.IO.V3[1]INT:MUX.LONG.IO.V3[2]INT:MUX.LONG.IO.V3[0]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V1[4]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.IMUX.RDBK.TRIG[1]INT:MUX.IMUX.RDBK.TRIG[0]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[3]~RDBK:ENABLEINT:MUX.IMUX.BUFG.V[5]-
6 --------------------------
7 ~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H1.0.LONG.IO.V0~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA~INT:PASS.SINGLE.H5.0.LONG.IO.V2--~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2~INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1INT:MUX.LONG.IO.V2[4]INT:MUX.LONG.IO.V3[4]INT:MUX.IO.DBUF.V0[3]INT:MUX.IO.DBUF.V0[2]INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]MD2:5V_TOLERANT_IOMD0:5V_TOLERANT_IOMD1:5V_TOLERANT_IO---
8 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1-~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0~INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1------------
9 INT:MUX.LONG.H4[0]INT:MUX.LONG.H4[2]~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA~INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1-INT:MUX.LONG.H5[0]~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0-~INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0-~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1--~INT:BUF.LONG.H3.0.LONG.IO.V1------------
10 --~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.SINT:MUX.LONG.H4[1]--INT:MUX.LONG.H5[1]-~INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0-INT:MUX.LONG.H5[2]----INT:MUX.IO.DBUF.V1[3]----------
11 ~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S--~INT:PASS.SINGLE.H6.0.LONG.IO.V3-----~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S----INT:MUX.IO.DBUF.V1[0]INT:MUX.IO.DBUF.V1[1]INT:MUX.IO.DBUF.V1[2]~INT:PASS.SINGLE.H2.0.LONG.IO.V1-----MD1:PULL[0]MD1:PULL[1]
12 ~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2~INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0--~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0----------
BUFGLS.H:ALT_PAD[0, 5, 2]
BUFGLS.H:CLK_EN[0, 6, 2]
BUFGLS.V:ALT_PAD[0, 7, 2]
BUFGLS.V:CLK_EN[0, 7, 3]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0[0, 8, 8]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1[0, 5, 8]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2[0, 2, 8]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0[0, 14, 12]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1[0, 12, 12]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2[0, 10, 12]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0[0, 5, 12]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1[0, 3, 12]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2[0, 1, 12]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0[0, 11, 8]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1[0, 12, 7]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2[0, 10, 7]
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2[0, 3, 8]
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2[0, 11, 12]
INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2[0, 11, 7]
INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2[0, 2, 12]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0[0, 9, 8]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2[0, 0, 8]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1[0, 6, 8]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0[0, 15, 12]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2[0, 9, 12]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1[0, 13, 12]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0[0, 12, 8]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2[0, 9, 7]
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1[0, 13, 7]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0[0, 6, 12]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2[0, 0, 12]
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1[0, 4, 12]
INT:BUF.LONG.H3.0.LONG.IO.V1[0, 13, 9]
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S[0, 2, 10]
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA[0, 2, 9]
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S[0, 2, 7]
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1[0, 10, 8]
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0[0, 6, 9]
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1[0, 10, 9]
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0[0, 9, 11]
INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1[0, 13, 8]
INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0[0, 8, 9]
INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1[0, 3, 9]
INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0[0, 8, 10]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 1, 7]
INT:PASS.SINGLE.H1.0.LONG.IO.V0[0, 3, 7]
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA[0, 4, 7]
INT:PASS.SINGLE.H2.0.LONG.IO.V1[0, 18, 11]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 10, 11]
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S[0, 0, 7]
INT:PASS.SINGLE.H5.0.LONG.IO.V2[0, 6, 7]
INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA[0, 5, 7]
INT:PASS.SINGLE.H6.0.LONG.IO.V3[0, 3, 11]
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S[0, 0, 11]
MISC:READ_ABORT[0, 15, 4]
MISC:READ_CAPTURE[0, 13, 4]
MISC:TM_BOT[0, 7, 4]
RDBK:ENABLE[0, 23, 5]
Inverted~[0]
INT:MUX.LONG.H4[0, 1, 9][0, 3, 10][0, 0, 9]
0.LONG.IO.V2000
0.OUT.RDBK.DATA011
NONE111
MD2:PULL[0, 4, 2][0, 3, 2]
PULLDOWN00
PULLNONE01
PULLUP11
INT:MUX.IMUX.BUFG.H[0, 2, 3][0, 2, 2][0, 0, 3][0, 1, 3][0, 1, 2][0, 0, 2][0, 3, 3]
0.IO.DOUBLE.0.S.00000111
0.IO.DOUBLE.1.S.00001011
0.IO.DOUBLE.2.S.00001101
0.IO.DOUBLE.0.W.10011111
0.IO.DOUBLE.2.W.10100111
0.IO.DOUBLE.3.S.00101011
0.IO.DOUBLE.3.W.10101101
0.IO.DOUBLE.1.W.10111111
0.OUT.IOB.CLKIN.W1101110
NONE1101111
INT:MUX.LONG.IO.V2[0, 14, 7][0, 0, 5][0, 2, 5][0, 1, 5][0, 3, 5]
0.LONG.H400011
0.LONG.IO.H000101
0.LONG.IO.H200110
0.SINGLE.H501111
NONE11111
INT:MUX.LONG.H5[0, 10, 10][0, 6, 10][0, 5, 9]
0.LONG.IO.V3000
0.OUT.RDBK.DATA011
NONE111
INT:MUX.LONG.IO.H2[0, 10, 4][0, 9, 4]
0.LONG.IO.V000
0.LONG.IO.V201
NONE11
INT:MUX.LONG.IO.V3[0, 15, 7][0, 8, 5][0, 10, 5][0, 9, 5][0, 11, 5]
0.LONG.H500011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H601111
NONE11111
INT:MUX.LONG.IO.H0[0, 12, 4][0, 14, 4]
0.LONG.IO.V200
0.LONG.IO.V001
NONE11
INT:MUX.IO.DBUF.V1[0, 15, 10][0, 17, 11][0, 16, 11][0, 15, 11]
0.IO.DOUBLE.0.W.20011
0.IO.DOUBLE.1.W.20101
0.IO.DOUBLE.3.W.20110
0.IO.DOUBLE.2.W.21111
INT:MUX.LONG.IO.H3[0, 17, 4][0, 16, 4]
0.LONG.IO.V100
0.LONG.IO.V301
NONE11
INT:MUX.LONG.IO.V1[0, 13, 5][0, 12, 5][0, 15, 5][0, 14, 5][0, 16, 5]
0.LONG.H300011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H201111
NONE11111
INT:MUX.IMUX.RDBK.TRIG[0, 5, 4][0, 6, 4][0, 17, 5][0, 18, 5]
0.SINGLE.H30011
0.SINGLE.H40101
0.SINGLE.H50110
0.SINGLE.H21111
INT:MUX.IO.DBUF.V0[0, 16, 7][0, 17, 7][0, 19, 7][0, 18, 7]
0.IO.DOUBLE.1.S.00011
0.IO.DOUBLE.2.S.00101
0.IO.DOUBLE.3.S.00110
0.IO.DOUBLE.0.S.01111
INT:MUX.LONG.IO.V0[0, 22, 5][0, 19, 5][0, 21, 5][0, 20, 5]
0.LONG.IO.H00001
0.LONG.IO.H20010
0.SINGLE.H10111
NONE1111
MD0:5V_TOLERANT_IO[0, 21, 7]
MD1:5V_TOLERANT_IO[0, 22, 7]
MD2:5V_TOLERANT_IO[0, 20, 7]
Non-inverted[0]
INT:MUX.LONG.IO.H1[0, 19, 4][0, 21, 4]
0.LONG.IO.V300
0.LONG.IO.V101
NONE11
INT:MUX.IMUX.BUFG.V[0, 20, 4][0, 24, 5][0, 6, 3][0, 8, 4][0, 11, 4][0, 18, 4][0, 22, 4]
0.IO.DOUBLE.0.W.10000111
0.IO.DOUBLE.1.S.00001011
0.IO.DOUBLE.1.W.10001101
0.IO.DOUBLE.0.S.00011111
0.IO.DOUBLE.2.W.10100111
0.IO.DOUBLE.3.S.00101011
0.IO.DOUBLE.3.W.10101101
0.IO.DOUBLE.2.S.00111111
0.OUT.IOB.CLKIN.S1101110
NONE1101111
MD0:PULL[0, 24, 4][0, 23, 4]
MD1:PULL[0, 25, 11][0, 24, 11]
PULLUP01
PULLDOWN10
PULLNONE11

CNR.TL

CNR.TL bittile 0
RowColumn
0123456789101112131415161718192021222324
0 INT:MUX.IMUX.BSCAN.TDO2[5]INT:MUX.IMUX.BSCAN.TDO2[1]INT:MUX.IMUX.BSCAN.TDO2[2]-------------~BUFGLS.V:CLK_EN-INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[2]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[6]--
1 INT:MUX.IMUX.BSCAN.TDO2[0]INT:MUX.IMUX.BSCAN.TDO2[3]INT:MUX.IMUX.BSCAN.TDO2[4]INT:MUX.LONG.IO.H0[0]-INT:MUX.LONG.IO.H2[0]INT:MUX.LONG.IO.H2[1]--INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V2[3]INT:MUX.IMUX.BUFG.V[5]INT:MUX.LONG.H2[0]INT:MUX.LONG.H2[1]INT:MUX.IMUX.BUFG.V[0]-----
2 INT:MUX.LONG.IO.H0[1]INT:MUX.IMUX.BSCAN.TDO1[2]INT:MUX.IMUX.BSCAN.TDO1[3]INT:MUX.IMUX.BSCAN.TDO1[0]--INT:MUX.LONG.IO.V0[2]----INT:MUX.LONG.H0[2]INT:MUX.LONG.H0[0]INT:MUX.LONG.H0[1]-INT:MUX.LONG.H1[0]-INT:MUX.LONG.H1[1]INT:MUX.LONG.H1[2]MISC:OUTPUT-----
3 INT:MUX.IMUX.BSCAN.TDO1[4]INT:MUX.IMUX.BSCAN.TDO1[5]INT:MUX.IMUX.BSCAN.TDO1[1]INT:MUX.LONG.IO.H3[0]-INT:MUX.LONG.IO.H1[0]-INT:MUX.LONG.IO.V1[3]-INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[0]~MISC:TM_LEFTINT:MUX.LONG.IO.V3[0]INT:MUX.LONG.IO.V3[1]BSCAN:ENABLE-~BUFGLS.V:ALT_PAD-------
4 INT:MUX.LONG.IO.H3[1]INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[6]INT:MUX.IMUX.BUFG.H[0]INT:MUX.LONG.IO.H1[1]~MISC:TM_TOP------------------
5 INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[5]-----------------------
6 INT:MUX.IMUX.BUFG.H[4]MISC:INPUT~MISC:3V~BUFGLS.H:CLK_EN~BUFGLS.H:ALT_PAD-------------------BSCAN:CONFIG
INT:MUX.IMUX.BSCAN.TDO2[0, 0, 0][0, 2, 1][0, 1, 1][0, 2, 0][0, 1, 0][0, 0, 1]
0.LONG.H0000111
0.LONG.H1001011
0.LONG.H2001101
1.SINGLE.V2010111
1.SINGLE.V3011011
1.SINGLE.V4011101
1.SINGLE.V5011110
2.DOUBLE.H1.0101111
2.DOUBLE.H0.1111111
MISC:INPUT[0, 1, 6]
MISC:OUTPUT[0, 19, 2]
CMOS0
TTL1
BUFGLS.H:ALT_PAD[0, 4, 6]
BUFGLS.H:CLK_EN[0, 3, 6]
BUFGLS.V:ALT_PAD[0, 17, 3]
BUFGLS.V:CLK_EN[0, 16, 0]
MISC:3V[0, 2, 6]
MISC:TM_LEFT[0, 12, 3]
MISC:TM_TOP[0, 6, 4]
Inverted~[0]
INT:MUX.LONG.IO.H0[0, 0, 2][0, 3, 1]
0.LONG.IO.V200
0.LONG.IO.V001
NONE11
INT:MUX.IMUX.BSCAN.TDO1[0, 1, 3][0, 0, 3][0, 2, 2][0, 1, 2][0, 2, 3][0, 3, 2]
1.LONG.V0000111
1.LONG.V1001011
1.LONG.V2001101
1.DOUBLE.V1.0011111
2.SINGLE.H2100111
2.SINGLE.H3101011
2.SINGLE.H4101101
2.SINGLE.H5101110
1.DOUBLE.V0.1111111
INT:MUX.LONG.IO.H3[0, 0, 4][0, 3, 3]
0.LONG.IO.V100
0.LONG.IO.V301
NONE11
INT:MUX.IMUX.BUFG.H[0, 3, 4][0, 1, 5][0, 0, 6][0, 1, 4][0, 2, 4][0, 0, 5][0, 4, 4]
0.IO.DOUBLE.0.N.10000111
0.IO.DOUBLE.1.N.10001011
0.IO.DOUBLE.2.N.10001101
0.IO.DOUBLE.0.N.20011111
0.IO.DOUBLE.2.N.20100111
0.IO.DOUBLE.3.N.10101011
0.IO.DOUBLE.3.N.20101101
0.IO.DOUBLE.1.N.20111111
0.OUT.IOB.CLKIN.W1101110
NONE1101111
INT:MUX.LONG.IO.H2[0, 6, 1][0, 5, 1]
0.LONG.IO.V000
0.LONG.IO.V201
NONE11
INT:MUX.LONG.IO.H1[0, 5, 4][0, 5, 3]
0.LONG.IO.V300
0.LONG.IO.V101
NONE11
INT:MUX.LONG.IO.V0[0, 9, 1][0, 6, 2][0, 10, 1][0, 11, 1]
0.LONG.H00001
0.LONG.IO.H20010
0.LONG.IO.H00111
NONE1111
INT:MUX.LONG.IO.V1[0, 7, 3][0, 9, 3][0, 10, 3][0, 11, 3]
0.LONG.H10001
0.LONG.IO.H30010
0.LONG.IO.H10111
NONE1111
INT:MUX.LONG.H0[0, 11, 2][0, 13, 2][0, 12, 2]
0.LONG.IO.V0000
0.OUT.LR.IOB1.I2011
NONE111
INT:MUX.LONG.IO.V2[0, 15, 1][0, 12, 1][0, 14, 1][0, 13, 1]
0.LONG.H20001
0.LONG.IO.H00010
0.LONG.IO.H20111
NONE1111
INT:MUX.LONG.IO.V3[0, 14, 3][0, 13, 3]
0.LONG.IO.H100
0.LONG.IO.H301
NONE11
INT:MUX.LONG.H1[0, 18, 2][0, 17, 2][0, 15, 2]
0.LONG.IO.V1000
0.OUT.LR.IOB1.I2011
NONE111
BSCAN:CONFIG[0, 24, 6]
BSCAN:ENABLE[0, 15, 3]
Non-inverted[0]
INT:MUX.LONG.H2[0, 18, 1][0, 17, 1]
0.LONG.IO.V200
NONE11
INT:MUX.IMUX.BUFG.V[0, 22, 0][0, 16, 1][0, 18, 0][0, 19, 0][0, 20, 0][0, 21, 0][0, 19, 1]
0.IO.DOUBLE.0.N.20000111
0.IO.DOUBLE.1.N.10001011
0.IO.DOUBLE.1.N.20001101
0.IO.DOUBLE.0.N.10011111
0.IO.DOUBLE.2.N.20100111
0.IO.DOUBLE.3.N.10101011
0.IO.DOUBLE.3.N.20101101
0.IO.DOUBLE.2.N.10111111
0.OUT.IOB.CLKIN.N1101110
NONE1101111

CNR.BR

CNR.BR bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031323334353637383940
0 STARTUP:CONFIG_RATE----------------------------------------
1 ~STARTUP:CRC-~BUFGLS.H:CLK_ENDONE:5V_TOLERANT_IO~MISC:TCTEST~STARTUP:ENABLE.GTSDONE:PULL~STARTUP:INV.GTS~STARTUP:ENABLE.GSR~STARTUP:INV.GSRSTARTUP:STARTUP_CLK~STARTUP:SYNC_TO_DONESTARTUP:DONE_ACTIVE[0]~OSC:TM_OSCOSC:OSC_CLK~BUFGLS.H:ALT_PAD---INT:MUX.IMUX.BUFG.H[3]INT:MUX.IMUX.BUFG.H[4]INT:MUX.IMUX.BUFG.H[1]INT:MUX.IMUX.BUFG.H[2]~INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1~INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1INT:MUX.IO.DBUF.H1[1]INT:MUX.IO.DBUF.H1[0]-
2 -------------------INT:MUX.IMUX.BUFG.H[6]INT:MUX.IMUX.BUFG.H[0]~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1~INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2INT:MUX.IO.DBUF.H1[3]INT:MUX.IO.DBUF.H1[2]-
3 -------~STARTUP:EXPRESS_MODE--INT:MUX.LONG.IO.H3[1]INT:MUX.LONG.IO.H3[0]STARTUP:DONE_ACTIVE[1]INT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.H1[1]STARTUP:GSR_INACTIVE[1]STARTUP:GSR_INACTIVE[0]STARTUP:OUTPUTS_ACTIVE[0]STARTUP:OUTPUTS_ACTIVE[1]INT:MUX.LONG.IO.H2[1]INT:MUX.LONG.IO.H2[0]INT:MUX.IMUX.BUFG.H[5]INT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2INT:MUX.LONG.IO.H0[2]INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[2]INT:MUX.LONG.IO.H1[3]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H2[4]INT:MUX.LONG.IO.H3[3]INT:MUX.LONG.IO.H2[5]INT:MUX.LONG.IO.H2[2]INT:MUX.LONG.IO.H2[3]INT:MUX.IMUX.STARTUP.CLK[0]-
4 OSC:ENABLEOSC:MUX.OUT0[3]-OSC:MUX.OUT1[3]INT:MUX.LONG.IO.V3[1]INT:MUX.LONG.IO.V1[3]INT:MUX.LONG.IO.V3[2]INT:MUX.IO.DBUF.H0[3]INT:MUX.IO.DBUF.H0[1]INT:MUX.IO.DBUF.H0[0]INT:MUX.LONG.IO.V1[4]INT:MUX.IO.DBUF.H0[2]INT:MUX.LONG.IO.V3[0]~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E-INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V3[4]~INT:PASS.SINGLE.V1.0.LONG.IO.H0~INT:PASS.SINGLE.V2.0.LONG.IO.H1INT:MUX.LONG.V0[2]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.V0[0]INT:MUX.LONG.IO.V2[4]INT:MUX.LONG.V0[1]-INT:MUX.LONG.IO.H3[2]~INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V5.0.LONG.IO.H2~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.EINT:MUX.LONG.V5[0]-INT:MUX.LONG.V5[1]-INT:MUX.LONG.V5[2]~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.EINT:MUX.IMUX.STARTUP.CLK[3]INT:MUX.IMUX.STARTUP.CLK[2]INT:MUX.IMUX.STARTUP.CLK[1]-
5 OSC:MUX.OUT1[2]OSC:MUX.OUT0[2]-INT:MUX.LONG.IO.V3[3]INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.IO.V1[1]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[2]--~INT:PASS.SINGLE.V6.0.LONG.IO.H3--INT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V2[1]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V2[2]INT:MUX.IMUX.BUFG.V[6]INT:MUX.LONG.H5[2]INT:MUX.LONG.H5[0]-INT:MUX.LONG.H3[0]INT:MUX.LONG.V4[0]INT:MUX.LONG.V4[1]-INT:MUX.LONG.V4[2]~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.V2[1]INT:MUX.LONG.V2[2]INT:MUX.IMUX.STARTUP.GTS[0]INT:MUX.IMUX.STARTUP.GTS[5]INT:MUX.IMUX.STARTUP.GTS[4]INT:MUX.IMUX.STARTUP.GTS[3]INT:MUX.IMUX.STARTUP.GTS[2]INT:MUX.IMUX.STARTUP.GTS[1]INT:MUX.LONG.V3[2]-INT:MUX.LONG.V1[0]INT:MUX.LONG.V1[2]--
6 ------INT:MUX.LONG.H4[0]-INT:MUX.LONG.H4[1]INT:MUX.LONG.H4[2]~BUFGLS.V:CLK_EN~INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2INT:MUX.IMUX.BUFG.V[0]~BUFGLS.V:ALT_PADINT:MUX.IMUX.BUFG.V[5]INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.H5[1]INT:MUX.LONG.H3[1]-~INT:BUF.LONG.H3.0.SINGLE.V4INT:MUX.LONG.V2[0]-~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEININT:MUX.IMUX.STARTUP.GSR[4]INT:MUX.IMUX.STARTUP.GSR[5]INT:MUX.IMUX.STARTUP.GSR[1]INT:MUX.IMUX.STARTUP.GSR[2]INT:MUX.IMUX.STARTUP.GSR[0]INT:MUX.IMUX.STARTUP.GSR[3]INT:MUX.LONG.V3[0]INT:MUX.LONG.V3[1]-INT:MUX.LONG.V1[1]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E-~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E
7 -----------------------------------------
8 OSC:MUX.OUT1[1]OSC:MUX.OUT0[1]~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1INT:MUX.IMUX.READCLK.I[3]INT:MUX.IMUX.READCLK.I[0]INT:MUX.IMUX.READCLK.I[1]INT:MUX.IMUX.READCLK.I[2]-~INT:PASS.SINGLE.H5.0.LONG.IO.V2-~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0-~INT:PASS.SINGLE.H2.0.LONG.IO.V1----~INT:BIPASS.SINGLE.V0.SINGLE.V0.S~INT:BIPASS.SINGLE.H0.SINGLE.V0.S~INT:BIPASS.SINGLE.H0.SINGLE.H0.E~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S~INT:BIPASS.SINGLE.H0.E.SINGLE.V0~INT:BIPASS.SINGLE.H0.SINGLE.V0~INT:PASS.SINGLE.V0.0.GND~INT:BIPASS.SINGLE.H1.SINGLE.V1.S~INT:BIPASS.SINGLE.H1.SINGLE.V1~INT:BIPASS.SINGLE.H1.SINGLE.H1.E~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2~INT:BIPASS.SINGLE.H5.SINGLE.V5~INT:BIPASS.SINGLE.H5.SINGLE.H5.E~INT:BIPASS.SINGLE.H5.E.SINGLE.V5~INT:BIPASS.SINGLE.H5.SINGLE.V5.S~INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S~INT:BIPASS.SINGLE.V5.SINGLE.V5.S
9 OSC:MUX.OUT1[0]~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1-~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1~INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0~INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0~INT:PASS.SINGLE.H6.0.LONG.IO.V3~INT:PASS.SINGLE.H1.0.LONG.IO.V0~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3~INT:PASS.SINGLE.H1.E.0.LONG.V0~INT:BUF.LONG.V0.0.SINGLE.H1.E~INT:BUF.LONG.H4.0.SINGLE.V5~INT:PASS.SINGLE.V5.0.LONG.H4~INT:PASS.SINGLE.H5.0.LONG.V4~INT:BIPASS.SINGLE.V1.SINGLE.V1.S~INT:BIPASS.SINGLE.H1.E.SINGLE.V1~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S~INT:BUF.LONG.V4.0.SINGLE.H5~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2~INT:BUF.LONG.V2.0.SINGLE.H3.E~INT:BIPASS.SINGLE.H4.SINGLE.V4.S~INT:BIPASS.SINGLE.H4.SINGLE.H4.E~INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S~INT:BIPASS.SINGLE.V4.SINGLE.V4.S~INT:BIPASS.SINGLE.H4.SINGLE.V4~INT:BUF.LONG.H5.0.SINGLE.V6
10 OSC:MUX.OUT0[0]~INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0INT:MUX.IO.DBUF.V0[3]~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4~INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4PROG:5V_TOLERANT_IO-----------------~INT:PASS.SINGLE.V4.0.LONG.H3~INT:BIPASS.SINGLE.V3.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.SINGLE.V3~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0~INT:BIPASS.SINGLE.H3.SINGLE.V3.S~INT:BIPASS.SINGLE.H3.SINGLE.H3.E~INT:BIPASS.SINGLE.H3.E.SINGLE.V3~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S~INT:BIPASS.SINGLE.H6.E.SINGLE.V6~INT:BIPASS.SINGLE.H6.SINGLE.H6.E~INT:BIPASS.SINGLE.H6.SINGLE.V6.S~INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S~INT:BIPASS.SINGLE.V6.SINGLE.V6.S~INT:PASS.SINGLE.H3.E.0.LONG.V2~INT:PASS.SINGLE.V6.0.LONG.H5
11 ------------------------~INT:BUF.LONG.V3.0.SINGLE.H4~INT:PASS.SINGLE.H4.0.LONG.V3-~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2-~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2-~INT:BIPASS.SINGLE.H2.SINGLE.V2~INT:BIPASS.SINGLE.H2.SINGLE.H2.E~INT:BIPASS.SINGLE.H2.SINGLE.V2.S-~INT:BUF.LONG.V5.0.SINGLE.H6~INT:BIPASS.SINGLE.H6.SINGLE.V6~INT:BIPASS.SINGLE.H7.SINGLE.V7.S~INT:BUF.LONG.V1.0.SINGLE.H2.E~INT:BIPASS.SINGLE.H4.E.SINGLE.V4-
12 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0INT:MUX.IO.DBUF.V0[2]INT:MUX.IO.DBUF.V0[0]INT:MUX.IO.DBUF.V0[1]-INT:MUX.IO.DBUF.V1[3]~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1INT:MUX.IO.DBUF.V1[1]INT:MUX.IO.DBUF.V1[2]INT:MUX.IO.DBUF.V1[0]~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1~INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0-~INT:PASS.SINGLE.V7.0.GND~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2~INT:BIPASS.SINGLE.V2.SINGLE.V2.S~INT:BIPASS.SINGLE.H2.E.SINGLE.V2~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S-~INT:PASS.SINGLE.H6.0.LONG.V5~INT:BIPASS.SINGLE.H7.SINGLE.V7~INT:BIPASS.SINGLE.V7.SINGLE.V7.S~INT:BIPASS.SINGLE.H7.E.SINGLE.V7~INT:BIPASS.SINGLE.H7.SINGLE.H7.E~INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S~INT:PASS.SINGLE.H2.E.0.LONG.V1
STARTUP:CONFIG_RATE[0, 0, 0]
FAST0
SLOW1
BUFGLS.H:ALT_PAD[0, 15, 1]
BUFGLS.H:CLK_EN[0, 2, 1]
BUFGLS.V:ALT_PAD[0, 15, 6]
BUFGLS.V:CLK_EN[0, 10, 6]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2[0, 29, 12]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0[0, 27, 12]
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2[0, 28, 12]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0[0, 3, 12]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1[0, 3, 9]
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1[0, 1, 12]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0[0, 14, 9]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1[0, 11, 12]
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1[0, 16, 12]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0[0, 29, 10]
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2[0, 29, 11]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2[0, 33, 9]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0[0, 32, 9]
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2[0, 31, 8]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0[0, 2, 10]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1[0, 4, 9]
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1[0, 2, 9]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0[0, 23, 12]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1[0, 20, 12]
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1[0, 19, 12]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0[0, 33, 8]
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2[0, 34, 8]
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2[0, 27, 11]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 28, 2]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1[0, 26, 3]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2[0, 30, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 25, 2]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1[0, 25, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2[0, 26, 2]
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2[0, 32, 8]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1[0, 27, 1]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1[0, 29, 1]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2[0, 32, 2]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1[0, 36, 1]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1[0, 34, 2]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2[0, 36, 2]
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1[0, 10, 12]
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2[0, 24, 3]
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1[0, 2, 12]
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2[0, 27, 3]
INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1[0, 1, 10]
INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2[0, 30, 1]
INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1[0, 22, 12]
INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2[0, 35, 2]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0[0, 25, 8]
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S[0, 24, 8]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0[0, 13, 9]
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1[0, 17, 12]
INT:BIPASS.SINGLE.H0.SINGLE.H0.E[0, 23, 8]
INT:BIPASS.SINGLE.H0.SINGLE.V0[0, 26, 8]
INT:BIPASS.SINGLE.H0.SINGLE.V0.S[0, 22, 8]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1[0, 29, 9]
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S[0, 30, 9]
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1[0, 15, 12]
INT:BIPASS.SINGLE.H1.SINGLE.H1.E[0, 30, 8]
INT:BIPASS.SINGLE.H1.SINGLE.V1[0, 29, 8]
INT:BIPASS.SINGLE.H1.SINGLE.V1.S[0, 28, 8]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2[0, 31, 12]
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S[0, 32, 12]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0[0, 4, 12]
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1[0, 0, 12]
INT:BIPASS.SINGLE.H2.SINGLE.H2.E[0, 32, 11]
INT:BIPASS.SINGLE.H2.SINGLE.V2[0, 31, 11]
INT:BIPASS.SINGLE.H2.SINGLE.V2.S[0, 33, 11]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3[0, 32, 10]
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S[0, 33, 10]
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1[0, 3, 8]
INT:BIPASS.SINGLE.H3.SINGLE.H3.E[0, 31, 10]
INT:BIPASS.SINGLE.H3.SINGLE.V3[0, 28, 10]
INT:BIPASS.SINGLE.H3.SINGLE.V3.S[0, 30, 10]
INT:BIPASS.SINGLE.H4.E.SINGLE.V4[0, 39, 11]
INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S[0, 37, 9]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0[0, 3, 10]
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1[0, 1, 9]
INT:BIPASS.SINGLE.H4.SINGLE.H4.E[0, 36, 9]
INT:BIPASS.SINGLE.H4.SINGLE.V4[0, 39, 9]
INT:BIPASS.SINGLE.H4.SINGLE.V4.S[0, 35, 9]
INT:BIPASS.SINGLE.H5.E.SINGLE.V5[0, 37, 8]
INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S[0, 39, 8]
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1[0, 2, 8]
INT:BIPASS.SINGLE.H5.SINGLE.H5.E[0, 36, 8]
INT:BIPASS.SINGLE.H5.SINGLE.V5[0, 35, 8]
INT:BIPASS.SINGLE.H5.SINGLE.V5.S[0, 38, 8]
INT:BIPASS.SINGLE.H6.E.SINGLE.V6[0, 34, 10]
INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S[0, 37, 10]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0[0, 24, 12]
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1[0, 18, 12]
INT:BIPASS.SINGLE.H6.SINGLE.H6.E[0, 35, 10]
INT:BIPASS.SINGLE.H6.SINGLE.V6[0, 36, 11]
INT:BIPASS.SINGLE.H6.SINGLE.V6.S[0, 36, 10]
INT:BIPASS.SINGLE.H7.E.SINGLE.V7[0, 37, 12]
INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S[0, 39, 12]
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1[0, 21, 12]
INT:BIPASS.SINGLE.H7.SINGLE.H7.E[0, 38, 12]
INT:BIPASS.SINGLE.H7.SINGLE.V7[0, 35, 12]
INT:BIPASS.SINGLE.H7.SINGLE.V7.S[0, 37, 11]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1[0, 24, 1]
INT:BIPASS.SINGLE.V0.SINGLE.V0.S[0, 21, 8]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1[0, 24, 2]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2[0, 27, 2]
INT:BIPASS.SINGLE.V1.SINGLE.V1.S[0, 28, 9]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1[0, 29, 2]
INT:BIPASS.SINGLE.V2.SINGLE.V2.S[0, 30, 12]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1[0, 25, 1]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2[0, 31, 2]
INT:BIPASS.SINGLE.V3.SINGLE.V3.S[0, 27, 10]
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1[0, 26, 1]
INT:BIPASS.SINGLE.V4.SINGLE.V4.S[0, 38, 9]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1[0, 28, 1]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2[0, 33, 2]
INT:BIPASS.SINGLE.V5.SINGLE.V5.S[0, 40, 8]
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1[0, 37, 1]
INT:BIPASS.SINGLE.V6.SINGLE.V6.S[0, 38, 10]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1[0, 35, 1]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2[0, 37, 2]
INT:BIPASS.SINGLE.V7.SINGLE.V7.S[0, 36, 12]
INT:BUF.LONG.H3.0.SINGLE.V4[0, 24, 6]
INT:BUF.LONG.H4.0.SINGLE.V5[0, 25, 9]
INT:BUF.LONG.H5.0.SINGLE.V6[0, 40, 9]
INT:BUF.LONG.V0.0.SINGLE.H1.E[0, 24, 9]
INT:BUF.LONG.V1.0.SINGLE.H2.E[0, 38, 11]
INT:BUF.LONG.V2.0.SINGLE.H3.E[0, 34, 9]
INT:BUF.LONG.V3.0.SINGLE.H4[0, 24, 11]
INT:BUF.LONG.V4.0.SINGLE.H5[0, 31, 9]
INT:BUF.LONG.V5.0.SINGLE.H6[0, 35, 11]
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4[0, 6, 10]
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S[0, 12, 8]
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S[0, 19, 9]
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3[0, 21, 9]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 13, 4]
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2[0, 13, 6]
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN[0, 29, 4]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 38, 6]
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0[0, 14, 8]
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1[0, 23, 2]
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1[0, 10, 9]
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0[0, 31, 1]
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0[0, 13, 8]
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1[0, 21, 2]
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1[0, 7, 9]
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0[0, 32, 1]
INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0[0, 11, 9]
INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1[0, 22, 2]
INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1[0, 9, 9]
INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0[0, 33, 1]
INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0[0, 12, 9]
INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1[0, 23, 1]
INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1[0, 8, 9]
INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0[0, 34, 1]
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S[0, 18, 9]
INT:PASS.SINGLE.H1.0.LONG.IO.V0[0, 16, 9]
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3[0, 20, 9]
INT:PASS.SINGLE.H1.E.0.LONG.V0[0, 23, 9]
INT:PASS.SINGLE.H2.0.LONG.IO.V1[0, 16, 8]
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4[0, 5, 10]
INT:PASS.SINGLE.H2.E.0.LONG.V1[0, 40, 12]
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S[0, 11, 8]
INT:PASS.SINGLE.H3.E.0.LONG.V2[0, 39, 10]
INT:PASS.SINGLE.H4.0.LONG.V3[0, 25, 11]
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S[0, 17, 9]
INT:PASS.SINGLE.H5.0.LONG.IO.V2[0, 9, 8]
INT:PASS.SINGLE.H5.0.LONG.V4[0, 27, 9]
INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3[0, 22, 9]
INT:PASS.SINGLE.H6.0.LONG.IO.V3[0, 15, 9]
INT:PASS.SINGLE.H6.0.LONG.V5[0, 34, 12]
INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4[0, 7, 10]
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S[0, 6, 9]
INT:PASS.SINGLE.V0.0.GND[0, 27, 8]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 26, 5]
INT:PASS.SINGLE.V1.0.LONG.IO.H0[0, 18, 4]
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN[0, 27, 6]
INT:PASS.SINGLE.V2.0.LONG.IO.H1[0, 19, 4]
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2[0, 12, 6]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 30, 4]
INT:PASS.SINGLE.V4.0.LONG.H3[0, 26, 10]
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E[0, 40, 6]
INT:PASS.SINGLE.V5.0.LONG.H4[0, 26, 9]
INT:PASS.SINGLE.V5.0.LONG.IO.H2[0, 28, 4]
INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN[0, 27, 4]
INT:PASS.SINGLE.V6.0.LONG.H5[0, 40, 10]
INT:PASS.SINGLE.V6.0.LONG.IO.H3[0, 10, 5]
INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2[0, 11, 6]
INT:PASS.SINGLE.V7.0.GND[0, 26, 12]
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E[0, 36, 4]
MISC:TCTEST[0, 4, 1]
OSC:TM_OSC[0, 13, 1]
STARTUP:CRC[0, 0, 1]
STARTUP:ENABLE.GSR[0, 8, 1]
STARTUP:ENABLE.GTS[0, 5, 1]
STARTUP:EXPRESS_MODE[0, 7, 3]
STARTUP:INV.GSR[0, 9, 1]
STARTUP:INV.GTS[0, 7, 1]
STARTUP:SYNC_TO_DONE[0, 11, 1]
Inverted~[0]
DONE:5V_TOLERANT_IO[0, 3, 1]
OSC:ENABLE[0, 0, 4]
PROG:5V_TOLERANT_IO[0, 8, 10]
Non-inverted[0]
OSC:MUX.OUT0[0, 1, 4][0, 1, 5][0, 1, 8][0, 0, 10]
OSC:MUX.OUT1[0, 3, 4][0, 0, 5][0, 0, 8][0, 0, 9]
F4900011
F16K0101
F500K0110
F151111
INT:MUX.IMUX.READCLK.I[0, 4, 8][0, 7, 8][0, 6, 8][0, 5, 8]
0.SINGLE.H20011
0.SINGLE.H30101
0.SINGLE.H40110
0.SINGLE.H51111
DONE:PULL[0, 6, 1]
PULLUP0
PULLNONE1
INT:MUX.LONG.IO.V1[0, 10, 4][0, 5, 4][0, 7, 5][0, 5, 5][0, 6, 5]
0.LONG.H300011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H201111
NONE11111
INT:MUX.LONG.H4[0, 9, 6][0, 8, 6][0, 6, 6]
0.LONG.IO.V2000
0.OUT.STARTUP.Q3011
NONE111
INT:MUX.IO.DBUF.V0[0, 4, 10][0, 5, 12][0, 7, 12][0, 6, 12]
0.IO.DOUBLE.1.S.10011
0.IO.DOUBLE.2.S.10101
0.IO.DOUBLE.3.S.10110
0.IO.DOUBLE.0.S.11111
INT:MUX.IO.DBUF.H0[0, 7, 4][0, 11, 4][0, 8, 4][0, 9, 4]
0.IO.DOUBLE.0.E.10011
0.IO.DOUBLE.2.E.10101
0.IO.DOUBLE.3.E.10110
0.IO.DOUBLE.1.E.11111
STARTUP:STARTUP_CLK[0, 10, 1]
CCLK0
USERCLK1
INT:MUX.LONG.IO.H3[0, 35, 3][0, 26, 4][0, 10, 3][0, 11, 3]
0.LONG.V50011
0.SINGLE.V60111
0.LONG.IO.V11100
0.LONG.IO.V31101
NONE1111
STARTUP:DONE_ACTIVE[0, 12, 3][0, 12, 1]
Q200
Q301
Q1Q410
Q011
INT:MUX.LONG.IO.V3[0, 17, 4][0, 3, 5][0, 6, 4][0, 4, 4][0, 12, 4]
0.LONG.H500011
0.LONG.IO.H100101
0.LONG.IO.H300110
0.SINGLE.H601111
NONE11111
INT:MUX.LONG.IO.H1[0, 33, 3][0, 30, 3][0, 32, 3][0, 31, 3][0, 14, 3][0, 13, 3]
0.LONG.V1000111
0.LONG.V3001011
0.SINGLE.V2011111
0.LONG.IO.V3111100
0.LONG.IO.V1111101
NONE111111
INT:MUX.LONG.IO.V2[0, 23, 4][0, 4, 5][0, 16, 5][0, 14, 5][0, 13, 5]
0.LONG.H400011
0.LONG.IO.H000101
0.LONG.IO.H200110
0.SINGLE.H501111
NONE11111
OSC:OSC_CLK[0, 14, 1]
EXTCLK0
CCLK1
INT:MUX.IMUX.BUFG.V[0, 17, 5][0, 16, 6][0, 17, 6][0, 18, 6][0, 20, 6][0, 19, 6][0, 14, 6]
0.IO.DOUBLE.0.E.10000111
0.IO.DOUBLE.1.E.10001011
0.IO.DOUBLE.1.S.10001101
0.IO.DOUBLE.0.S.10011111
0.IO.DOUBLE.2.E.10100111
0.IO.DOUBLE.3.E.10101011
0.IO.DOUBLE.3.S.10101101
0.IO.DOUBLE.2.S.10111111
0.OUT.IOB.CLKIN.S1101110
NONE1101111
INT:MUX.IO.DBUF.V1[0, 9, 12][0, 13, 12][0, 12, 12][0, 14, 12]
0.IO.DOUBLE.0.E.00011
0.IO.DOUBLE.1.E.00101
0.IO.DOUBLE.3.E.00110
0.IO.DOUBLE.2.E.01111
STARTUP:GSR_INACTIVE[0, 15, 3][0, 16, 3]
DONE_IN00
Q301
Q1Q410
Q211
INT:MUX.LONG.IO.V0[0, 21, 4][0, 15, 5][0, 15, 4][0, 16, 4]
0.LONG.IO.H00001
0.LONG.IO.H20010
0.SINGLE.H10111
NONE1111
STARTUP:OUTPUTS_ACTIVE[0, 18, 3][0, 17, 3]
Q300
DONE_IN01
Q210
Q1Q411
INT:MUX.LONG.H5[0, 18, 5][0, 21, 6][0, 19, 5]
0.LONG.IO.V3000
0.OUT.STARTUP.Q3011
NONE111
INT:MUX.IMUX.BUFG.H[0, 19, 2][0, 21, 3][0, 20, 1][0, 19, 1][0, 22, 1][0, 21, 1][0, 20, 2]
0.IO.DOUBLE.3.E.10001101
0.IO.DOUBLE.0.E.10001111
0.IO.DOUBLE.2.S.10010101
0.IO.DOUBLE.0.S.10010111
0.IO.DOUBLE.3.S.10011001
0.IO.DOUBLE.1.E.10011011
0.IO.DOUBLE.1.S.10111101
0.IO.DOUBLE.2.E.10111111
0.OUT.IOB.CLKIN.E1011110
NONE1011111
INT:MUX.LONG.IO.H2[0, 36, 3][0, 34, 3][0, 38, 3][0, 37, 3][0, 19, 3][0, 20, 3]
0.LONG.V2000111
0.LONG.V4001011
0.SINGLE.V5011111
0.LONG.IO.V0111100
0.LONG.IO.V2111101
NONE111111
INT:MUX.LONG.H3[0, 22, 6][0, 21, 5]
0.LONG.IO.V100
NONE11
INT:MUX.LONG.IO.H0[0, 29, 3][0, 28, 3][0, 23, 3][0, 22, 3]
0.LONG.V00011
0.SINGLE.V10111
0.LONG.IO.V21100
0.LONG.IO.V01101
NONE1111
INT:MUX.LONG.V0[0, 20, 4][0, 24, 4][0, 22, 4]
0.LONG.IO.H0000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.LONG.V4[0, 25, 5][0, 23, 5][0, 22, 5]
0.LONG.IO.H2000
0.OUT.STARTUP.DONEIN011
NONE111
INT:MUX.LONG.V2[0, 28, 5][0, 27, 5][0, 25, 6]
0.LONG.IO.H2000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.IMUX.STARTUP.GTS[0, 30, 5][0, 31, 5][0, 32, 5][0, 33, 5][0, 34, 5][0, 29, 5]
0.LONG.H3001110
0.SINGLE.V2001111
0.SINGLE.V3010111
0.LONG.H5011010
0.SINGLE.V4011011
0.LONG.H4011100
0.SINGLE.V5011101
0.DOUBLE.H1.0111110
0.DOUBLE.H0.1111111
INT:MUX.LONG.V5[0, 35, 4][0, 33, 4][0, 31, 4]
0.LONG.IO.H3000
0.OUT.STARTUP.DONEIN011
NONE111
INT:MUX.IMUX.STARTUP.GSR[0, 29, 6][0, 28, 6][0, 33, 6][0, 31, 6][0, 30, 6][0, 32, 6]
0.SINGLE.H2000111
0.SINGLE.H3001011
0.LONG.V4001110
0.LONG.V5010111
0.DOUBLE.V1.1011011
0.SINGLE.H4011101
0.LONG.V3011110
0.DOUBLE.V0.0101111
0.SINGLE.H5111111
INT:MUX.LONG.V3[0, 35, 5][0, 35, 6][0, 34, 6]
0.LONG.IO.H1000
0.OUT.STARTUP.DONEIN011
NONE111
INT:MUX.LONG.V1[0, 38, 5][0, 37, 6][0, 37, 5]
0.LONG.IO.H1000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.IO.DBUF.H1[0, 38, 2][0, 39, 2][0, 38, 1][0, 39, 1]
0.IO.DOUBLE.1.S.20011
0.IO.DOUBLE.2.S.20101
0.IO.DOUBLE.3.S.20110
0.IO.DOUBLE.0.S.21111
INT:MUX.IMUX.STARTUP.CLK[0, 37, 4][0, 38, 4][0, 39, 4][0, 39, 3]
0.SINGLE.V30011
0.SINGLE.V40101
0.SINGLE.V50110
0.SINGLE.V21111

CNR.TR

CNR.TR bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031323334353637383940
0 ------INT:MUX.LONG.H1[0]-~BUFGLS.V:CLK_ENINT:MUX.LONG.H1[1]INT:MUX.LONG.H1[2]-TDO:5V_TOLERANT_IOCCLK:5V_TOLERANT_IO~MISC:TM_RIGHTINT:MUX.IMUX.BUFG.V[0]INT:MUX.IMUX.BUFG.V[6]INT:MUX.IMUX.BUFG.V[4]INT:MUX.IMUX.BUFG.V[3]INT:MUX.IMUX.BUFG.V[1]INT:MUX.IMUX.BUFG.V[2]INT:MUX.LONG.H0[1]INT:MUX.LONG.H2[1]-~INT:BUF.LONG.H2.0.SINGLE.V3INT:MUX.LONG.V2[0]-~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1INT:MUX.IMUX.TDO.T[5]INT:MUX.IMUX.TDO.T[4]INT:MUX.IMUX.TDO.T[0]INT:MUX.IMUX.TDO.T[3]INT:MUX.IMUX.TDO.T[2]INT:MUX.IMUX.TDO.T[1]INT:MUX.LONG.V3[0]INT:MUX.LONG.V3[1]-INT:MUX.LONG.V1[0]~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E-~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E
1 -----INT:MUX.LONG.IO.V1[2]INT:MUX.LONG.IO.V1[0]INT:MUX.LONG.IO.V1[1]~BUFGLS.V:ALT_PAD~BUFGLS.H:ALT_PAD~INT:PASS.SINGLE.V6.0.LONG.IO.H3INT:MUX.LONG.V4[2]INT:MUX.IMUX.BUFG.V[5]INT:MUX.LONG.IO.V2[2]INT:MUX.LONG.IO.V2[0]INT:MUX.LONG.IO.V0[1]INT:MUX.LONG.IO.V2[1]-INT:MUX.LONG.H0[2]INT:MUX.LONG.H0[0]-INT:MUX.LONG.H2[0]INT:MUX.LONG.V4[0]INT:MUX.LONG.V4[1]--~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.EINT:MUX.LONG.V2[1]INT:MUX.LONG.V2[2]INT:MUX.IMUX.TDO.O[0]INT:MUX.IMUX.TDO.O[5]INT:MUX.IMUX.TDO.O[4]INT:MUX.IMUX.TDO.O[3]INT:MUX.IMUX.TDO.O[2]INT:MUX.IMUX.TDO.O[1]INT:MUX.LONG.V3[2]-INT:MUX.LONG.V1[1]INT:MUX.LONG.V1[2]--
2 -------INT:MUX.IO.DBUF.H0[3]INT:MUX.IO.DBUF.H0[1]INT:MUX.IO.DBUF.H0[0]INT:MUX.LONG.IO.V1[3]INT:MUX.IO.DBUF.H0[2]INT:MUX.LONG.IO.V3[0]~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.EINT:MUX.IMUX.BUFG.H[4]INT:MUX.LONG.IO.V0[2]INT:MUX.LONG.IO.V0[0]INT:MUX.LONG.IO.V3[1]~INT:PASS.SINGLE.V1.0.LONG.IO.H0~INT:PASS.SINGLE.V2.0.LONG.IO.H1INT:MUX.LONG.V0[2]INT:MUX.LONG.IO.V0[3]INT:MUX.LONG.V0[0]INT:MUX.LONG.IO.V2[3]INT:MUX.LONG.V0[1]-INT:MUX.LONG.IO.H3[2]~INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V5.0.LONG.IO.H2~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.EINT:MUX.LONG.V5[0]-INT:MUX.LONG.V5[1]INT:MUX.IMUX.BUFG.H[3]INT:MUX.LONG.V5[2]~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.EINT:MUX.IMUX.BUFG.H[1]~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O-
3 -------~TDO:ENABLE.T~TDO:ENABLE.O-INT:MUX.LONG.IO.H3[1]INT:MUX.LONG.IO.H3[0]READCLK:READ_CLKINT:MUX.LONG.IO.H1[0]INT:MUX.LONG.IO.H1[1]~MISC:TACTDO:PULL[0]BSCAN:ENABLETDO:PULL[1]INT:MUX.LONG.IO.H2[1]INT:MUX.LONG.IO.H2[0]INT:MUX.IMUX.BUFG.H[5]INT:MUX.LONG.IO.H0[0]INT:MUX.LONG.IO.H0[1]~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2INT:MUX.LONG.IO.H0[2]INT:MUX.LONG.IO.H0[3]INT:MUX.LONG.IO.H1[4]INT:MUX.LONG.IO.H1[2]INT:MUX.LONG.IO.H1[3]INT:MUX.LONG.IO.H1[5]INT:MUX.LONG.IO.H2[4]INT:MUX.LONG.IO.H3[3]INT:MUX.LONG.IO.H2[5]INT:MUX.LONG.IO.H2[2]INT:MUX.LONG.IO.H2[3]~INT:PASS.SINGLE.V6.0.OUT.UPDATE.O-
4 --------------------INT:MUX.IMUX.BUFG.H[0]~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1~INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0INT:MUX.IO.DBUF.H1[3]INT:MUX.IO.DBUF.H1[2]-
5 ---------------------INT:MUX.IMUX.BUFG.H[2]INT:MUX.IMUX.BUFG.H[6]~INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1~INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0~INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1INT:MUX.IO.DBUF.H1[1]INT:MUX.IO.DBUF.H1[0]-
6 -MISC:ADDRESS_LINES~BUFGLS.H:CLK_EN~BSCAN:STATUS-------------------------------------
CNR.TR bittile 1
RowColumn
012345678910111213141516171819202122232425262728293031323334
0 -----------------------------------
1 -----------------------------------
2 -----------------------------------
3 -----------------------------------
4 -----------------------------------
5 -----------------------------------
6 -----------------------------------
7 -----------------------------------
8 --------------------------~INT:BUF.LONG.H0.0.SINGLE.V1-~INT:PASS.SINGLE.V1.0.LONG.H0-~INT:BUF.LONG.H1.0.SINGLE.V2---~INT:PASS.SINGLE.V2.0.LONG.H1
9 ---------------------------------~INT:PASS.SINGLE.V3.0.LONG.H2-
CNR.TR bittile 2
RowColumn
012345
0 -----~INT:BUF.LONG.V0.0.OUT.TOP.COUT.E
MISC:ADDRESS_LINES[0, 1, 6]
220
181
BSCAN:STATUS[0, 3, 6]
BUFGLS.H:ALT_PAD[0, 9, 1]
BUFGLS.H:CLK_EN[0, 2, 6]
BUFGLS.V:ALT_PAD[0, 8, 1]
BUFGLS.V:CLK_EN[0, 8, 0]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1[0, 26, 3]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2[0, 28, 4]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0[0, 30, 4]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1[0, 25, 3]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2[0, 25, 4]
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0[0, 26, 4]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1[0, 29, 5]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2[0, 27, 5]
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0[0, 32, 4]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1[0, 34, 4]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2[0, 36, 5]
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0[0, 36, 4]
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2[0, 24, 3]
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2[0, 27, 3]
INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2[0, 30, 5]
INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2[0, 35, 4]
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1[0, 24, 5]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2[0, 24, 4]
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0[0, 27, 4]
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1[0, 29, 4]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2[0, 25, 5]
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0[0, 31, 4]
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1[0, 26, 5]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2[0, 28, 5]
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0[0, 33, 4]
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1[0, 37, 5]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2[0, 35, 5]
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0[0, 37, 4]
INT:BUF.LONG.H0.0.SINGLE.V1[1, 26, 8]
INT:BUF.LONG.H1.0.SINGLE.V2[1, 30, 8]
INT:BUF.LONG.H2.0.SINGLE.V3[0, 24, 0]
INT:BUF.LONG.V0.0.OUT.TOP.COUT.E[2, 5, 0]
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E[0, 13, 2]
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O[0, 38, 2]
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1[0, 29, 2]
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E[0, 38, 0]
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1[0, 23, 4]
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0[0, 31, 5]
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1[0, 21, 4]
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0[0, 32, 5]
INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1[0, 22, 4]
INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0[0, 33, 5]
INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1[0, 23, 5]
INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0[0, 34, 5]
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E[0, 26, 1]
INT:PASS.SINGLE.V1.0.LONG.H0[1, 28, 8]
INT:PASS.SINGLE.V1.0.LONG.IO.H0[0, 18, 2]
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1[0, 27, 0]
INT:PASS.SINGLE.V2.0.LONG.H1[1, 34, 8]
INT:PASS.SINGLE.V2.0.LONG.IO.H1[0, 19, 2]
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O[0, 39, 2]
INT:PASS.SINGLE.V3.0.LONG.H2[1, 33, 9]
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E[0, 30, 2]
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E[0, 40, 0]
INT:PASS.SINGLE.V5.0.LONG.IO.H2[0, 28, 2]
INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1[0, 27, 2]
INT:PASS.SINGLE.V6.0.LONG.IO.H3[0, 10, 1]
INT:PASS.SINGLE.V6.0.OUT.UPDATE.O[0, 39, 3]
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E[0, 36, 2]
MISC:TAC[0, 15, 3]
MISC:TM_RIGHT[0, 14, 0]
TDO:ENABLE.O[0, 8, 3]
TDO:ENABLE.T[0, 7, 3]
Inverted~[0]
INT:MUX.LONG.H1[0, 10, 0][0, 9, 0][0, 6, 0]
0.LONG.IO.V1000
0.OUT.LR.IOB1.I2011
NONE111
INT:MUX.LONG.IO.V1[0, 10, 2][0, 5, 1][0, 7, 1][0, 6, 1]
0.LONG.H10001
0.LONG.IO.H30010
0.LONG.IO.H10111
NONE1111
INT:MUX.IO.DBUF.H0[0, 7, 2][0, 11, 2][0, 8, 2][0, 9, 2]
0.IO.DOUBLE.0.E.20011
0.IO.DOUBLE.2.E.20101
0.IO.DOUBLE.3.E.20110
0.IO.DOUBLE.1.E.21111
INT:MUX.LONG.IO.H3[0, 35, 3][0, 26, 2][0, 10, 3][0, 11, 3]
0.LONG.V50011
0.SINGLE.V60111
0.LONG.IO.V11100
0.LONG.IO.V31101
NONE1111
BSCAN:ENABLE[0, 17, 3]
CCLK:5V_TOLERANT_IO[0, 13, 0]
TDO:5V_TOLERANT_IO[0, 12, 0]
Non-inverted[0]
INT:MUX.LONG.IO.V3[0, 17, 2][0, 12, 2]
0.LONG.IO.H100
0.LONG.IO.H301
NONE11
READCLK:READ_CLK[0, 12, 3]
RDBK0
CCLK1
INT:MUX.LONG.IO.H1[0, 33, 3][0, 30, 3][0, 32, 3][0, 31, 3][0, 14, 3][0, 13, 3]
0.LONG.V1000111
0.LONG.V3001011
0.SINGLE.V2011111
0.LONG.IO.V3111100
0.LONG.IO.V1111101
NONE111111
INT:MUX.LONG.IO.V2[0, 23, 2][0, 13, 1][0, 16, 1][0, 14, 1]
0.LONG.H20001
0.LONG.IO.H00010
0.LONG.IO.H20111
NONE1111
INT:MUX.IMUX.BUFG.V[0, 16, 0][0, 12, 1][0, 17, 0][0, 18, 0][0, 20, 0][0, 19, 0][0, 15, 0]
0.IO.DOUBLE.0.E.10000111
0.IO.DOUBLE.1.E.10001011
0.IO.DOUBLE.1.E.20001101
0.IO.DOUBLE.0.E.20011111
0.IO.DOUBLE.2.E.10100111
0.IO.DOUBLE.3.E.10101011
0.IO.DOUBLE.3.E.20101101
0.IO.DOUBLE.2.E.20111111
0.OUT.IOB.CLKIN.N1101110
NONE1101111
INT:MUX.LONG.IO.V0[0, 21, 2][0, 15, 2][0, 15, 1][0, 16, 2]
0.LONG.H00001
0.LONG.IO.H20010
0.LONG.IO.H00111
NONE1111
TDO:PULL[0, 18, 3][0, 16, 3]
PULLUP01
PULLDOWN10
PULLNONE11
INT:MUX.LONG.H0[0, 18, 1][0, 21, 0][0, 19, 1]
0.LONG.IO.V0000
0.OUT.LR.IOB1.I2011
NONE111
INT:MUX.LONG.IO.H2[0, 36, 3][0, 34, 3][0, 38, 3][0, 37, 3][0, 19, 3][0, 20, 3]
0.LONG.V2000111
0.LONG.V4001011
0.SINGLE.V5011111
0.LONG.IO.V0111100
0.LONG.IO.V2111101
NONE111111
INT:MUX.IMUX.BUFG.H[0, 22, 5][0, 21, 3][0, 14, 2][0, 34, 2][0, 21, 5][0, 37, 2][0, 20, 4]
0.IO.DOUBLE.2.E.10001011
0.IO.DOUBLE.0.E.10001111
0.IO.DOUBLE.3.E.20010011
0.IO.DOUBLE.0.E.20010111
0.IO.DOUBLE.3.E.10011001
0.IO.DOUBLE.1.E.20011101
0.IO.DOUBLE.1.E.10111011
0.IO.DOUBLE.2.E.20111111
0.OUT.IOB.CLKIN.E1011110
NONE1011111
INT:MUX.LONG.H2[0, 22, 0][0, 21, 1]
0.LONG.IO.V200
NONE11
INT:MUX.LONG.V4[0, 11, 1][0, 23, 1][0, 22, 1]
0.LONG.IO.H2000
0.OUT.OSC.MUX1011
NONE111
INT:MUX.LONG.V0[0, 20, 2][0, 24, 2][0, 22, 2]
0.LONG.IO.H0000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.LONG.IO.H0[0, 29, 3][0, 28, 3][0, 23, 3][0, 22, 3]
0.LONG.V00011
0.SINGLE.V10111
0.LONG.IO.V21100
0.LONG.IO.V01101
NONE1111
INT:MUX.LONG.V2[0, 28, 1][0, 27, 1][0, 25, 0]
0.LONG.IO.H2000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.IMUX.TDO.O[0, 30, 1][0, 31, 1][0, 32, 1][0, 33, 1][0, 34, 1][0, 29, 1]
0.LONG.H0001110
0.SINGLE.V2001111
0.SINGLE.V3010111
0.LONG.H1011010
0.SINGLE.V4011011
0.LONG.H2011100
0.SINGLE.V5011101
1.DOUBLE.H1.1111110
1.DOUBLE.H0.0111111
INT:MUX.IMUX.TDO.T[0, 28, 0][0, 29, 0][0, 31, 0][0, 32, 0][0, 33, 0][0, 30, 0]
1.SINGLE.H3000111
0.LONG.V4001011
1.SINGLE.H2001101
0.DOUBLE.V0.0011111
0.DOUBLE.V1.1100111
0.LONG.V3101011
0.LONG.V5101101
1.SINGLE.H4101110
1.SINGLE.H5111111
INT:MUX.LONG.V5[0, 35, 2][0, 33, 2][0, 31, 2]
0.LONG.IO.H3000
0.OUT.OSC.MUX1011
NONE111
INT:MUX.LONG.V3[0, 35, 1][0, 35, 0][0, 34, 0]
0.LONG.IO.H1000
0.OUT.OSC.MUX1011
NONE111
INT:MUX.LONG.V1[0, 38, 1][0, 37, 1][0, 37, 0]
0.LONG.IO.H1000
0.OUT.BT.IOB1.I2.E011
NONE111
INT:MUX.IO.DBUF.H1[0, 38, 4][0, 39, 4][0, 38, 5][0, 39, 5]
0.IO.DOUBLE.1.N.00011
0.IO.DOUBLE.2.N.00101
0.IO.DOUBLE.3.N.00110
0.IO.DOUBLE.0.N.01111