Splitters

`LLH.CLB`

LLH.CLB bittile 0
Row	Column
Row	0	1
0	~INT:BUF.1.LONG.H5.0.LONG.H5	~INT:BUF.1.LONG.H4.0.LONG.H4
1	~INT:BUF.0.LONG.H5.1.LONG.H5	~INT:BUF.0.LONG.H4.1.LONG.H4
2	-	-
3	-	~TBUF_SPLITTER1:PASS
4	-	-
5	-	-
6	-	-
7	-	-
8	~TBUF_SPLITTER1:BUF_E	-
9	~TBUF_SPLITTER1:BUF_W	-

LLH.CLB bittile 1
Row	Column
Row	0	1
0	-	-
1	-	-
2	~INT:BUF.0.LONG.H1.1.LONG.H1	-
3	~INT:BUF.1.LONG.H0.0.LONG.H0	-
4	~INT:BUF.0.LONG.H0.1.LONG.H0	~TBUF_SPLITTER0:PASS
5	~INT:BUF.1.LONG.H1.0.LONG.H1	-
6	-	~TBUF_SPLITTER0:BUF_E
7	-	~TBUF_SPLITTER0:BUF_W

INT:BUF.0.LONG.H0.1.LONG.H0	[1, 0, 4]
INT:BUF.0.LONG.H1.1.LONG.H1	[1, 0, 2]
INT:BUF.0.LONG.H4.1.LONG.H4	[0, 1, 1]
INT:BUF.0.LONG.H5.1.LONG.H5	[0, 0, 1]
INT:BUF.1.LONG.H0.0.LONG.H0	[1, 0, 3]
INT:BUF.1.LONG.H1.0.LONG.H1	[1, 0, 5]
INT:BUF.1.LONG.H4.0.LONG.H4	[0, 1, 0]
INT:BUF.1.LONG.H5.0.LONG.H5	[0, 0, 0]
TBUF_SPLITTER0:BUF_E	[1, 1, 6]
TBUF_SPLITTER0:BUF_W	[1, 1, 7]
TBUF_SPLITTER0:PASS	[1, 1, 4]
TBUF_SPLITTER1:BUF_E	[0, 0, 8]
TBUF_SPLITTER1:BUF_W	[0, 0, 9]
TBUF_SPLITTER1:PASS	[0, 1, 3]
Inverted	~[0]

`LLH.CLB.B`

LLH.CLB.B bittile 0
Row	Column
Row	0	1
0	~INT:BUF.1.LONG.H5.0.LONG.H5	~INT:BUF.1.LONG.H4.0.LONG.H4
1	~INT:BUF.0.LONG.H5.1.LONG.H5	~INT:BUF.0.LONG.H4.1.LONG.H4
2	-	-
3	-	~TBUF_SPLITTER1:PASS
4	-	-
5	-	-
6	-	-
7	-	-
8	~TBUF_SPLITTER1:BUF_E	-
9	~TBUF_SPLITTER1:BUF_W	-

LLH.CLB.B bittile 1
Row	Column
Row	0	1
0	-	~TBUF_SPLITTER0:BUF_E
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	~TBUF_SPLITTER0:BUF_W	~TBUF_SPLITTER0:PASS
9	-	-
10	-	-
11	~INT:BUF.1.LONG.H1.0.LONG.H1	~INT:BUF.0.LONG.H1.1.LONG.H1
12	~INT:BUF.1.LONG.H0.0.LONG.H0	~INT:BUF.0.LONG.H0.1.LONG.H0

INT:BUF.0.LONG.H0.1.LONG.H0	[1, 1, 12]
INT:BUF.0.LONG.H1.1.LONG.H1	[1, 1, 11]
INT:BUF.0.LONG.H4.1.LONG.H4	[0, 1, 1]
INT:BUF.0.LONG.H5.1.LONG.H5	[0, 0, 1]
INT:BUF.1.LONG.H0.0.LONG.H0	[1, 0, 12]
INT:BUF.1.LONG.H1.0.LONG.H1	[1, 0, 11]
INT:BUF.1.LONG.H4.0.LONG.H4	[0, 1, 0]
INT:BUF.1.LONG.H5.0.LONG.H5	[0, 0, 0]
TBUF_SPLITTER0:BUF_E	[1, 1, 0]
TBUF_SPLITTER0:BUF_W	[1, 0, 8]
TBUF_SPLITTER0:PASS	[1, 1, 8]
TBUF_SPLITTER1:BUF_E	[0, 0, 8]
TBUF_SPLITTER1:BUF_W	[0, 0, 9]
TBUF_SPLITTER1:PASS	[0, 1, 3]
Inverted	~[0]

`LLH.IO.B`

LLH.IO.B bittile 0
Row	Column
Row	0	1
0	-	-
1	-	-
2	~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3	~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3
3	~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2	~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
4	~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1	~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
5	~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0	~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0
6	~INT:BUF.1.LONG.H5.0.LONG.H5	~INT:BUF.0.LONG.H5.1.LONG.H5
7	~INT:BUF.1.LONG.H4.0.LONG.H4	~INT:BUF.0.LONG.H4.1.LONG.H4
8	-	-
9	-	-
10	~INT:BUF.1.LONG.H3.0.LONG.H3	~INT:BUF.0.LONG.H3.1.LONG.H3

INT:BUF.0.LONG.H3.1.LONG.H3	[0, 1, 10]
INT:BUF.0.LONG.H4.1.LONG.H4	[0, 1, 7]
INT:BUF.0.LONG.H5.1.LONG.H5	[0, 1, 6]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0	[0, 1, 5]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1	[0, 1, 4]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2	[0, 1, 3]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3	[0, 1, 2]
INT:BUF.1.LONG.H3.0.LONG.H3	[0, 0, 10]
INT:BUF.1.LONG.H4.0.LONG.H4	[0, 0, 7]
INT:BUF.1.LONG.H5.0.LONG.H5	[0, 0, 6]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0	[0, 0, 5]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1	[0, 0, 4]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2	[0, 0, 3]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3	[0, 0, 2]
Inverted	~[0]

`LLH.IO.T`

LLH.IO.T bittile 0
Row	Column
Row	0	1
0	~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0	~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
1	~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1	~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1
2	-	-
3	-	-
4	~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2	~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2
5	~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3	~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3

LLH.IO.T bittile 1
Row	Column
Row	0	1
0	-	-
1	-	-
2	~INT:BUF.0.LONG.H1.1.LONG.H1	-
3	~INT:BUF.1.LONG.H0.0.LONG.H0	-
4	~INT:BUF.0.LONG.H0.1.LONG.H0	-
5	~INT:BUF.1.LONG.H1.0.LONG.H1	-
6	-	~INT:BUF.1.LONG.H2.0.LONG.H2
7	-	~INT:BUF.0.LONG.H2.1.LONG.H2

INT:BUF.0.LONG.H0.1.LONG.H0	[1, 0, 4]
INT:BUF.0.LONG.H1.1.LONG.H1	[1, 0, 2]
INT:BUF.0.LONG.H2.1.LONG.H2	[1, 1, 7]
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0	[0, 0, 0]
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1	[0, 1, 1]
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2	[0, 1, 4]
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3	[0, 1, 5]
INT:BUF.1.LONG.H0.0.LONG.H0	[1, 0, 3]
INT:BUF.1.LONG.H1.0.LONG.H1	[1, 0, 5]
INT:BUF.1.LONG.H2.0.LONG.H2	[1, 1, 6]
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0	[0, 1, 0]
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1	[0, 0, 1]
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2	[0, 0, 4]
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3	[0, 0, 5]
Inverted	~[0]

`LLV.CLB`

LLV.CLB bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34	35
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKH:ENABLE.I.LR.H	CLKH:ENABLE.I.UL.V	CLKH:ENABLE.I.LL.H	CLKH:ENABLE.I.UR.H	CLKH:ENABLE.I.LR.V	CLKH:ENABLE.I.LL.V	CLKH:ENABLE.I.UL.H	CLKH:ENABLE.I.UR.V	-	-	-
1	CLKH:MUX.O1[3]	CLKH:MUX.O1[5]	CLKH:MUX.O1[1]	CLKH:MUX.O1[4]	CLKH:MUX.O1[2]	CLKH:MUX.O1[0]	CLKH:MUX.O3[3]	CLKH:MUX.O3[5]	CLKH:MUX.O3[1]	CLKH:MUX.O3[4]	CLKH:MUX.O3[2]	CLKH:MUX.O3[0]	CLKH:MUX.O2[3]	CLKH:MUX.O2[5]	CLKH:MUX.O2[1]	CLKH:MUX.O2[4]	CLKH:MUX.O2[2]	CLKH:MUX.O2[0]	CLKH:MUX.O0[3]	CLKH:MUX.O0[5]	CLKH:MUX.O0[1]	CLKH:MUX.O0[4]	CLKH:MUX.O0[2]	CLKH:MUX.O0[0]	~INT:BUF.0.LONG.V4.1.LONG.V4	~INT:BUF.1.LONG.V4.0.LONG.V4	~INT:BUF.0.LONG.V0.1.LONG.V0	~INT:BUF.1.LONG.V0.0.LONG.V0	~INT:BUF.0.LONG.V3.1.LONG.V3	~INT:BUF.1.LONG.V3.0.LONG.V3	~INT:BUF.0.LONG.V5.1.LONG.V5	~INT:BUF.1.LONG.V5.0.LONG.V5	~INT:BUF.0.LONG.V2.1.LONG.V2	~INT:BUF.1.LONG.V2.0.LONG.V2	~INT:BUF.0.LONG.V1.1.LONG.V1	~INT:BUF.1.LONG.V1.0.LONG.V1

CLKH:MUX.O0	[0, 19, 1]	[0, 21, 1]	[0, 18, 1]	[0, 22, 1]	[0, 20, 1]	[0, 23, 1]
CLKH:MUX.O1	[0, 1, 1]	[0, 3, 1]	[0, 0, 1]	[0, 4, 1]	[0, 2, 1]	[0, 5, 1]
CLKH:MUX.O2	[0, 13, 1]	[0, 15, 1]	[0, 12, 1]	[0, 16, 1]	[0, 14, 1]	[0, 17, 1]
CLKH:MUX.O3	[0, 7, 1]	[0, 9, 1]	[0, 6, 1]	[0, 10, 1]	[0, 8, 1]	[0, 11, 1]
I.LL.H	0	0	1	1	1	1
I.UL.V	0	1	1	0	1	1
I.UR.H	0	1	1	1	0	1
I.LR.V	0	1	1	1	1	0
I.LR.H	1	0	0	1	1	1
I.LL.V	1	1	0	0	1	1
I.UL.H	1	1	0	1	0	1
I.UR.V	1	1	0	1	1	0
NONE	1	1	1	1	1	1

INT:BUF.0.LONG.V0.1.LONG.V0	[0, 26, 1]
INT:BUF.0.LONG.V1.1.LONG.V1	[0, 34, 1]
INT:BUF.0.LONG.V2.1.LONG.V2	[0, 32, 1]
INT:BUF.0.LONG.V3.1.LONG.V3	[0, 28, 1]
INT:BUF.0.LONG.V4.1.LONG.V4	[0, 24, 1]
INT:BUF.0.LONG.V5.1.LONG.V5	[0, 30, 1]
INT:BUF.1.LONG.V0.0.LONG.V0	[0, 27, 1]
INT:BUF.1.LONG.V1.0.LONG.V1	[0, 35, 1]
INT:BUF.1.LONG.V2.0.LONG.V2	[0, 33, 1]
INT:BUF.1.LONG.V3.0.LONG.V3	[0, 29, 1]
INT:BUF.1.LONG.V4.0.LONG.V4	[0, 25, 1]
INT:BUF.1.LONG.V5.0.LONG.V5	[0, 31, 1]
Inverted	~[0]

CLKH:ENABLE.I.LL.H	[0, 27, 0]
CLKH:ENABLE.I.LL.V	[0, 30, 0]
CLKH:ENABLE.I.LR.H	[0, 25, 0]
CLKH:ENABLE.I.LR.V	[0, 29, 0]
CLKH:ENABLE.I.UL.H	[0, 31, 0]
CLKH:ENABLE.I.UL.V	[0, 26, 0]
CLKH:ENABLE.I.UR.H	[0, 28, 0]
CLKH:ENABLE.I.UR.V	[0, 32, 0]
Non-inverted	[0]

`LLV.IO.L`

LLV.IO.L bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23
0	-	-	-	-	-	-	-	-	CLKH:MUX.O2[4]	CLKH:MUX.O2[1]	CLKH:ENABLE.I.UL.H	CLKH:ENABLE.I.UR.V	CLKH:MUX.O0[4]	CLKH:MUX.O0[1]	CLKH:ENABLE.I.LL.V	CLKH:ENABLE.I.LR.H	CLKH:MUX.O1[4]	CLKH:MUX.O1[1]	CLKH:ENABLE.I.UL.V	CLKH:ENABLE.I.LL.H	CLKH:MUX.O3[4]	CLKH:MUX.O3[1]	CLKH:ENABLE.I.UR.H	CLKH:ENABLE.I.LR.V
1	~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2	~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1	CLKH:MUX.O2[3]	CLKH:MUX.O2[5]	CLKH:MUX.O2[2]	CLKH:MUX.O2[0]	CLKH:MUX.O0[3]	CLKH:MUX.O0[5]	CLKH:MUX.O0[2]	CLKH:MUX.O0[0]	CLKH:MUX.O1[3]	CLKH:MUX.O1[5]	CLKH:MUX.O1[2]	CLKH:MUX.O1[0]	CLKH:MUX.O3[3]	CLKH:MUX.O3[5]	CLKH:MUX.O3[2]	CLKH:MUX.O3[0]

INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0	[0, 2, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1	[0, 6, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2	[0, 0, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3	[0, 4, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0	[0, 3, 1]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1	[0, 7, 1]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2	[0, 1, 1]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3	[0, 5, 1]
Inverted	~[0]

CLKH:ENABLE.I.LL.H	[0, 19, 0]
CLKH:ENABLE.I.LL.V	[0, 14, 0]
CLKH:ENABLE.I.LR.H	[0, 15, 0]
CLKH:ENABLE.I.LR.V	[0, 23, 0]
CLKH:ENABLE.I.UL.H	[0, 10, 0]
CLKH:ENABLE.I.UL.V	[0, 18, 0]
CLKH:ENABLE.I.UR.H	[0, 22, 0]
CLKH:ENABLE.I.UR.V	[0, 11, 0]
Non-inverted	[0]

CLKH:MUX.O0	[0, 13, 1]	[0, 12, 0]	[0, 12, 1]	[0, 14, 1]	[0, 13, 0]	[0, 15, 1]
CLKH:MUX.O1	[0, 17, 1]	[0, 16, 0]	[0, 16, 1]	[0, 18, 1]	[0, 17, 0]	[0, 19, 1]
CLKH:MUX.O2	[0, 9, 1]	[0, 8, 0]	[0, 8, 1]	[0, 10, 1]	[0, 9, 0]	[0, 11, 1]
CLKH:MUX.O3	[0, 21, 1]	[0, 20, 0]	[0, 20, 1]	[0, 22, 1]	[0, 21, 0]	[0, 23, 1]
I.LL.H	0	0	1	1	1	1
I.UL.V	0	1	1	0	1	1
I.UR.H	0	1	1	1	0	1
I.LR.V	0	1	1	1	1	0
I.LR.H	1	0	0	1	1	1
I.LL.V	1	1	0	0	1	1
I.UL.H	1	1	0	1	0	1
I.UR.V	1	1	0	1	1	0
NONE	1	1	1	1	1	1

`LLV.IO.R`

LLV.IO.R bittile 0
Row	Column
Row	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40
0	-	-	-	-	-	CLKH:MUX.O1[4]	CLKH:MUX.O1[1]	CLKH:ENABLE.I.UR.V	CLKH:ENABLE.I.UL.H	CLKH:MUX.O3[4]	CLKH:MUX.O3[1]	CLKH:ENABLE.I.LL.V	CLKH:ENABLE.I.LR.H	CLKH:MUX.O0[4]	CLKH:MUX.O0[1]	CLKH:ENABLE.I.UL.V	CLKH:ENABLE.I.LL.H	CLKH:MUX.O2[4]	CLKH:MUX.O2[1]	CLKH:ENABLE.I.UR.H	CLKH:ENABLE.I.LR.V	~MISC:TLC	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	CLKH:MUX.O1[3]	CLKH:MUX.O1[5]	CLKH:MUX.O1[2]	CLKH:MUX.O1[0]	CLKH:MUX.O3[3]	CLKH:MUX.O3[5]	CLKH:MUX.O3[2]	CLKH:MUX.O3[0]	CLKH:MUX.O0[3]	CLKH:MUX.O0[5]	CLKH:MUX.O0[2]	CLKH:MUX.O0[0]	CLKH:MUX.O2[3]	CLKH:MUX.O2[5]	CLKH:MUX.O2[2]	CLKH:MUX.O2[0]	~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1	~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2	~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~INT:BUF.0.LONG.V4.1.LONG.V4	~INT:BUF.1.LONG.V4.0.LONG.V4	~INT:BUF.0.LONG.V0.1.LONG.V0	~INT:BUF.1.LONG.V0.0.LONG.V0	~INT:BUF.0.LONG.V3.1.LONG.V3	~INT:BUF.1.LONG.V3.0.LONG.V3	~INT:BUF.0.LONG.V5.1.LONG.V5	~INT:BUF.1.LONG.V5.0.LONG.V5	~INT:BUF.0.LONG.V2.1.LONG.V2	~INT:BUF.1.LONG.V2.0.LONG.V2	~INT:BUF.0.LONG.V1.1.LONG.V1	~INT:BUF.1.LONG.V1.0.LONG.V1

CLKH:ENABLE.I.LL.H	[0, 16, 0]
CLKH:ENABLE.I.LL.V	[0, 11, 0]
CLKH:ENABLE.I.LR.H	[0, 12, 0]
CLKH:ENABLE.I.LR.V	[0, 20, 0]
CLKH:ENABLE.I.UL.H	[0, 8, 0]
CLKH:ENABLE.I.UL.V	[0, 15, 0]
CLKH:ENABLE.I.UR.H	[0, 19, 0]
CLKH:ENABLE.I.UR.V	[0, 7, 0]
Non-inverted	[0]

CLKH:MUX.O0	[0, 14, 1]	[0, 13, 0]	[0, 13, 1]	[0, 15, 1]	[0, 14, 0]	[0, 16, 1]
CLKH:MUX.O1	[0, 6, 1]	[0, 5, 0]	[0, 5, 1]	[0, 7, 1]	[0, 6, 0]	[0, 8, 1]
CLKH:MUX.O2	[0, 18, 1]	[0, 17, 0]	[0, 17, 1]	[0, 19, 1]	[0, 18, 0]	[0, 20, 1]
CLKH:MUX.O3	[0, 10, 1]	[0, 9, 0]	[0, 9, 1]	[0, 11, 1]	[0, 10, 0]	[0, 12, 1]
I.LL.H	0	0	1	1	1	1
I.UL.V	0	1	1	0	1	1
I.UR.H	0	1	1	1	0	1
I.LR.V	0	1	1	1	1	0
I.LR.H	1	0	0	1	1	1
I.LL.V	1	1	0	0	1	1
I.UL.H	1	1	0	1	0	1
I.UR.V	1	1	0	1	1	0
NONE	1	1	1	1	1	1

INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0	[0, 25, 1]
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1	[0, 21, 1]
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2	[0, 27, 1]
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3	[0, 23, 1]
INT:BUF.0.LONG.V0.1.LONG.V0	[0, 31, 1]
INT:BUF.0.LONG.V1.1.LONG.V1	[0, 39, 1]
INT:BUF.0.LONG.V2.1.LONG.V2	[0, 37, 1]
INT:BUF.0.LONG.V3.1.LONG.V3	[0, 33, 1]
INT:BUF.0.LONG.V4.1.LONG.V4	[0, 29, 1]
INT:BUF.0.LONG.V5.1.LONG.V5	[0, 35, 1]
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0	[0, 26, 1]
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1	[0, 22, 1]
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2	[0, 28, 1]
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3	[0, 24, 1]
INT:BUF.1.LONG.V0.0.LONG.V0	[0, 32, 1]
INT:BUF.1.LONG.V1.0.LONG.V1	[0, 40, 1]
INT:BUF.1.LONG.V2.0.LONG.V2	[0, 38, 1]
INT:BUF.1.LONG.V3.0.LONG.V3	[0, 34, 1]
INT:BUF.1.LONG.V4.0.LONG.V4	[0, 30, 1]
INT:BUF.1.LONG.V5.0.LONG.V5	[0, 36, 1]
MISC:TLC	[0, 21, 0]
Inverted	~[0]