Configuration registers — Spartan 3A and 3A DSP

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COR1.S3A

This is the Spartan 3A version of COR1.

REG.COR1.S3A bittile 0
Row	Column
	0
0	STARTUP:STARTUPCLK[0]
1	STARTUP:STARTUPCLK[1]
2	STARTUP:DRIVE_DONE
3	STARTUP:DONE_PIPE
4	~STARTUP:CRC
5	STARTUP:VRDSEL[0]
6	STARTUP:VRDSEL[1]
7	STARTUP:VRDSEL[2]
8	MISC:SEND_VGG[0]
9	MISC:SEND_VGG[1]
10	MISC:SEND_VGG[2]
11	MISC:SEND_VGG[3]
12	~MISC:VGG_SENDMAX
13	~MISC:VGG_ENABLE_OFFCHIP
14	-
15	STARTUP:DRIVE_AWAKE

STARTUP:STARTUPCLK	[0, 0, 1]	[0, 0, 0]
CCLK	0	0
USERCLK	0	1
JTAGCLK	1	0

STARTUP:DONE_PIPE	[0, 0, 3]
STARTUP:DRIVE_AWAKE	[0, 0, 15]
STARTUP:DRIVE_DONE	[0, 0, 2]
Non-inverted	[0]

MISC:VGG_ENABLE_OFFCHIP	[0, 0, 13]
MISC:VGG_SENDMAX	[0, 0, 12]
STARTUP:CRC	[0, 0, 4]
Inverted	~[0]

STARTUP:VRDSEL	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]
Non-inverted	[2]	[1]	[0]

MISC:SEND_VGG	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]
Non-inverted	[3]	[2]	[1]	[0]

COR2.S3A

This is the Spartan 3A version of COR2.

REG.COR2.S3A bittile 0
Row	Column
	0
0	STARTUP:GWE_CYCLE[0]
1	STARTUP:GWE_CYCLE[1]
2	STARTUP:GWE_CYCLE[2]
3	STARTUP:GTS_CYCLE[0]
4	STARTUP:GTS_CYCLE[1]
5	STARTUP:GTS_CYCLE[2]
6	STARTUP:LCK_CYCLE[0]
7	STARTUP:LCK_CYCLE[1]
8	STARTUP:LCK_CYCLE[2]
9	STARTUP:DONE_CYCLE[0]
10	STARTUP:DONE_CYCLE[1]
11	STARTUP:DONE_CYCLE[2]
12	CAPTURE:ONESHOT
13	STARTUP:BPI_DIV8
14	ICAP:BYPASS
15	STARTUP:RESET_ON_ERR

STARTUP:GTS_CYCLE	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
STARTUP:GWE_CYCLE	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
KEEP	0	0	0
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0
DONE	1	1	1

STARTUP:LCK_CYCLE	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0
NOWAIT	1	1	1

STARTUP:DONE_CYCLE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0

CAPTURE:ONESHOT	[0, 0, 12]
ICAP:BYPASS	[0, 0, 14]
STARTUP:BPI_DIV8	[0, 0, 13]
STARTUP:RESET_ON_ERR	[0, 0, 15]
Non-inverted	[0]

CTL.S3A

This is the Spartan 3A version of CTL.

REG.CTL.S3A bittile 0
Row	Column
	0
0	MISC:GTS_USR_B
1	MISC:VGG_TEST
2	ICAP:ENABLE
3	MISC:PERSIST
4	MISC:SECURITY[0]
5	MISC:SECURITY[1]
6	-
7	MISC:MULTIBOOT_ENABLE

ICAP:ENABLE	[0, 0, 2]
MISC:GTS_USR_B	[0, 0, 0]
MISC:MULTIBOOT_ENABLE	[0, 0, 7]
MISC:PERSIST	[0, 0, 3]
MISC:VGG_TEST	[0, 0, 1]
Non-inverted	[0]

MISC:SECURITY	[0, 0, 5]	[0, 0, 4]
NONE	0	0
LEVEL1	0	1
LEVEL2	1	0
LEVEL3	1	1

CCLK_FREQ

REG.CCLK_FREQ bittile 0
Row	Column
	0
0	STARTUP:CONFIG_RATE[0]
1	STARTUP:CONFIG_RATE[1]
2	STARTUP:CONFIG_RATE[2]
3	STARTUP:CONFIG_RATE[3]
4	STARTUP:CONFIG_RATE[4]
5	STARTUP:CONFIG_RATE[5]
6	STARTUP:CONFIG_RATE[6]
7	STARTUP:CONFIG_RATE[7]
8	STARTUP:CONFIG_RATE[8]
9	STARTUP:CONFIG_RATE[9]
10	STARTUP:CCLK_DLY[0]
11	STARTUP:CCLK_DLY[1]
12	STARTUP:CCLK_SEP[0]
13	STARTUP:CCLK_SEP[1]
14	STARTUP:CLK_SWITCH_OPT[0]
15	STARTUP:CLK_SWITCH_OPT[1]

STARTUP:CONFIG_RATE	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
100	0	0	0	0	0	0	0	0	1	1
50	0	0	0	0	0	0	0	1	1	1
44	0	0	0	0	0	0	1	0	0	0
33	0	0	0	0	0	0	1	0	1	1
27	0	0	0	0	0	0	1	1	1	0
25	0	0	0	0	0	0	1	1	1	1
22	0	0	0	0	0	1	0	0	0	1
17	0	0	0	0	0	1	0	1	1	1
13	0	0	0	0	0	1	1	1	1	0
12	0	0	0	0	1	0	0	0	0	0
10	0	0	0	0	1	0	0	1	1	1
8	0	0	0	0	1	1	0	0	0	1
7	0	0	0	0	1	1	1	0	0	0
6	0	0	0	1	0	0	0	0	1	0
3	0	0	1	0	0	0	0	1	0	0
1	0	1	1	0	0	0	1	1	1	1

STARTUP:CCLK_DLY	[0, 0, 11]	[0, 0, 10]
STARTUP:CCLK_SEP	[0, 0, 13]	[0, 0, 12]
STARTUP:CLK_SWITCH_OPT	[0, 0, 15]	[0, 0, 14]
Non-inverted	[1]	[0]

HC_OPT

REG.HC_OPT bittile 0
Row	Column
	0
0	MISC:HC_CYCLE[0]
1	MISC:HC_CYCLE[1]
2	MISC:HC_CYCLE[2]
3	MISC:HC_CYCLE[3]
4	MISC:TWO_ROUND
5	MISC:BRAM_SKIP

MISC:HC_CYCLE	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[3]	[2]	[1]	[0]

MISC:BRAM_SKIP	[0, 0, 5]
MISC:TWO_ROUND	[0, 0, 4]
Non-inverted	[0]

POWERDOWN

REG.POWERDOWN bittile 0
Row	Column
	0
0	MISC:SW_CLK
1	~MISC:EN_PORB
2	MISC:EN_SUSPEND
3	-
4	MISC:EN_SW_GSR
5	~MISC:SUSPEND_FILTER
6	MISC:WAKE_DELAY1[0]
7	MISC:WAKE_DELAY1[1]
8	MISC:WAKE_DELAY1[2]
9	MISC:WAKE_DELAY2[0]
10	MISC:WAKE_DELAY2[1]
11	MISC:WAKE_DELAY2[2]
12	MISC:WAKE_DELAY2[3]
13	MISC:WAKE_DELAY2[4]

MISC:SW_CLK	[0, 0, 0]
INTERNALCLK	0
STARTUPCLK	1

MISC:EN_PORB	[0, 0, 1]
MISC:SUSPEND_FILTER	[0, 0, 5]
Inverted	~[0]

MISC:EN_SUSPEND	[0, 0, 2]
MISC:EN_SW_GSR	[0, 0, 4]
Non-inverted	[0]

MISC:WAKE_DELAY1	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
Non-inverted	[2]	[1]	[0]

MISC:WAKE_DELAY2	[0, 0, 13]	[0, 0, 12]	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
Non-inverted	[4]	[3]	[2]	[1]	[0]

PU_GWE

REG.PU_GWE bittile 0
Row	Column
	0
0	MISC:SW_GWE_CYCLE[0]
1	MISC:SW_GWE_CYCLE[1]
2	MISC:SW_GWE_CYCLE[2]
3	MISC:SW_GWE_CYCLE[3]
4	MISC:SW_GWE_CYCLE[4]
5	MISC:SW_GWE_CYCLE[5]
6	MISC:SW_GWE_CYCLE[6]
7	MISC:SW_GWE_CYCLE[7]
8	MISC:SW_GWE_CYCLE[8]
9	MISC:SW_GWE_CYCLE[9]

MISC:SW_GWE_CYCLE	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

PU_GTS

REG.PU_GTS bittile 0
Row	Column
	0
0	MISC:SW_GTS_CYCLE[0]
1	MISC:SW_GTS_CYCLE[1]
2	MISC:SW_GTS_CYCLE[2]
3	MISC:SW_GTS_CYCLE[3]
4	MISC:SW_GTS_CYCLE[4]
5	MISC:SW_GTS_CYCLE[5]
6	MISC:SW_GTS_CYCLE[6]
7	MISC:SW_GTS_CYCLE[7]
8	MISC:SW_GTS_CYCLE[8]
9	MISC:SW_GTS_CYCLE[9]

MISC:SW_GTS_CYCLE	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MODE

REG.MODE bittile 0
Row	Column
	0
0	MISC:BOOTVSEL[0]
1	MISC:BOOTVSEL[1]
2	MISC:BOOTVSEL[2]
3	MISC:NEXT_CONFIG_BOOT_MODE[0]
4	MISC:NEXT_CONFIG_BOOT_MODE[1]
5	MISC:NEXT_CONFIG_BOOT_MODE[2]
6	MISC:NEXT_CONFIG_NEW_MODE
7	MISC:TESTMODE_EN

MISC:BOOTVSEL	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
MISC:NEXT_CONFIG_BOOT_MODE	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
Non-inverted	[2]	[1]	[0]

MISC:NEXT_CONFIG_NEW_MODE	[0, 0, 6]
MISC:TESTMODE_EN	[0, 0, 7]
Non-inverted	[0]

GENERAL[12]

REG.GENERAL bittile 0
Row	Column
	0
0	MISC:NEXT_CONFIG_ADDR[0]
1	MISC:NEXT_CONFIG_ADDR[1]
2	MISC:NEXT_CONFIG_ADDR[2]
3	MISC:NEXT_CONFIG_ADDR[3]
4	MISC:NEXT_CONFIG_ADDR[4]
5	MISC:NEXT_CONFIG_ADDR[5]
6	MISC:NEXT_CONFIG_ADDR[6]
7	MISC:NEXT_CONFIG_ADDR[7]
8	MISC:NEXT_CONFIG_ADDR[8]
9	MISC:NEXT_CONFIG_ADDR[9]
10	MISC:NEXT_CONFIG_ADDR[10]
11	MISC:NEXT_CONFIG_ADDR[11]
12	MISC:NEXT_CONFIG_ADDR[12]
13	MISC:NEXT_CONFIG_ADDR[13]
14	MISC:NEXT_CONFIG_ADDR[14]
15	MISC:NEXT_CONFIG_ADDR[15]

REG.GENERAL bittile 1
Row	Column
	0
0	MISC:NEXT_CONFIG_ADDR[16]
1	MISC:NEXT_CONFIG_ADDR[17]
2	MISC:NEXT_CONFIG_ADDR[18]
3	MISC:NEXT_CONFIG_ADDR[19]
4	MISC:NEXT_CONFIG_ADDR[20]
5	MISC:NEXT_CONFIG_ADDR[21]
6	MISC:NEXT_CONFIG_ADDR[22]
7	MISC:NEXT_CONFIG_ADDR[23]
8	MISC:NEXT_CONFIG_ADDR[24]
9	MISC:NEXT_CONFIG_ADDR[25]
10	MISC:NEXT_CONFIG_ADDR[26]
11	MISC:NEXT_CONFIG_ADDR[27]
12	MISC:NEXT_CONFIG_ADDR[28]
13	MISC:NEXT_CONFIG_ADDR[29]
14	MISC:NEXT_CONFIG_ADDR[30]
15	MISC:NEXT_CONFIG_ADDR[31]

MISC:NEXT_CONFIG_ADDR	[1, 0, 15]	[1, 0, 14]	[1, 0, 13]	[1, 0, 12]	[1, 0, 11]	[1, 0, 10]	[1, 0, 9]	[1, 0, 8]	[1, 0, 7]	[1, 0, 6]	[1, 0, 5]	[1, 0, 4]	[1, 0, 3]	[1, 0, 2]	[1, 0, 1]	[1, 0, 0]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

SEU_OPT

REG.SEU_OPT bittile 0
Row	Column
	0
0	MISC:POST_CRC_EN
1	MISC:GLUTMASK
2	-
3	MISC:POST_CRC_KEEP
4	MISC:POST_CRC_FREQ[0]
5	MISC:POST_CRC_FREQ[1]
6	MISC:POST_CRC_FREQ[2]
7	MISC:POST_CRC_FREQ[3]
8	MISC:POST_CRC_FREQ[4]
9	MISC:POST_CRC_FREQ[5]
10	MISC:POST_CRC_FREQ[6]
11	MISC:POST_CRC_FREQ[7]
12	MISC:POST_CRC_FREQ[8]
13	MISC:POST_CRC_FREQ[9]

MISC:GLUTMASK	[0, 0, 1]
MISC:POST_CRC_EN	[0, 0, 0]
MISC:POST_CRC_KEEP	[0, 0, 3]
Non-inverted	[0]

MISC:POST_CRC_FREQ	[0, 0, 13]	[0, 0, 12]	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]
100	0	0	0	0	0	0	0	0	1	1
50	0	0	0	0	0	0	0	1	1	1
44	0	0	0	0	0	0	1	0	0	0
33	0	0	0	0	0	0	1	0	1	1
27	0	0	0	0	0	0	1	1	1	0
25	0	0	0	0	0	0	1	1	1	1
22	0	0	0	0	0	1	0	0	0	1
17	0	0	0	0	0	1	0	1	1	1
13	0	0	0	0	0	1	1	1	1	0
12	0	0	0	0	1	0	0	0	0	0
10	0	0	0	0	1	0	0	1	1	1
8	0	0	0	0	1	1	0	0	0	1
7	0	0	0	0	1	1	1	0	0	0
6	0	0	0	1	0	0	0	0	1	0
3	0	0	1	0	0	0	0	1	0	0
1	0	1	1	0	0	0	1	1	1	1