Clock management tile

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CMT

CMT bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[1]	DCM0:DRP40[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[2]	DCM0:DRP40[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[5]	DCM0:DRP40[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[6]	DCM0:DRP40[7]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[9]	DCM0:DRP40[8]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[10]	DCM0:DRP40[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[13]	DCM0:DRP40[12]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP40[14]	DCM0:DRP40[15]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_OSCILLATOR_MODE DCM0:DRP41[1]	DCM0:DRP41[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_FREQUENCY_MODE DCM0:DRP41[2]	DCM0:DFS_CFG_BYPASS DCM0:DRP41[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_SYNTH_FAST_SYNCH[1] DCM0:DRP41[5]	DCM0:DFS_SYNTH_FAST_SYNCH[0] DCM0:DRP41[4]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_AVE_FREQ_GAIN[0] DCM0:DRP41[6]	DCM0:DFS_AVE_FREQ_GAIN[1] DCM0:DRP41[7]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_EARLY_LOCK DCM0:DRP41[9]	DCM0:DFS_AVE_FREQ_GAIN[2] DCM0:DRP41[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP41[10]	DCM0:DRP41[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP41[13]	DCM0:DRP41[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_HARDSYNC_B[0] DCM0:DRP41[14]	DCM0:DFS_HARDSYNC_B[1] DCM0:DRP41[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP42[1]	DCM0:DRP42[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP42[2]	DCM0:DFS_JF_LOWER_LIMIT[0] DCM0:DRP42[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_JF_LOWER_LIMIT[2] DCM0:DRP42[5]	DCM0:DFS_JF_LOWER_LIMIT[1] DCM0:DRP42[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_JF_LOWER_LIMIT[3] DCM0:DRP42[6]	DCM0:DFS_OSC_ON_FX DCM0:DRP42[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_HF_TRIM_CAL[0] DCM0:DRP42[9]	DCM0:DFS_REF_ON_FX DCM0:DRP42[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_HF_TRIM_CAL[1] DCM0:DRP42[10]	DCM0:DFS_HF_TRIM_CAL[2] DCM0:DRP42[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DFS_PWRD_REPLY_TIMES_OUT_B DCM0:DRP42[13]	DCM0:DRP42[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DFS_PWRD_CLKIN_STOP_STICKY_B DCM0:DRP42[14]	~DCM0:DFS_PWRD_CLKIN_STOP_B DCM0:DRP42[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_CLKIN_IODLY_MUXOUT_SEL DCM0:DRP43[1]	DCM0:DCM_CLKFB_IODLY_MUXOUT_SEL DCM0:DRP43[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP43[2]	DCM0:DESKEW_ADJUST[0] DCM0:DRP43[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DESKEW_ADJUST[2] DCM0:DRP43[5]	DCM0:DESKEW_ADJUST[1] DCM0:DRP43[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DESKEW_ADJUST[3] DCM0:DRP43[6]	DCM0:DESKEW_ADJUST[4] DCM0:DRP43[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_PLL_RST_DCM DCM0:DRP43[9]	DCM0:DRP43[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COM_PWC_REF_TAP[0] DCM0:DRP43[10]	DCM0:DCM_COM_PWC_REF_TAP[1] DCM0:DRP43[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COM_PWC_FB_TAP[0] DCM0:DRP43[13]	DCM0:DCM_COM_PWC_REF_TAP[2] DCM0:DRP43[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COM_PWC_FB_TAP[1] DCM0:DRP43[14]	DCM0:DCM_COM_PWC_FB_TAP[2] DCM0:DRP43[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COM_PWC_FB_EN DCM0:DRP44[1]	DCM0:DCM_COM_PWC_REF_EN DCM0:DRP44[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_EXT_FB_EN DCM0:DRP44[2]	DCM0:DCM_USE_REG_READY DCM0:DRP44[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_SYNTH_CLOCK_SPEED[1] DCM0:DRP44[5]	DCM0:DLL_SYNTH_CLOCK_SPEED[0] DCM0:DRP44[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_SYNTH_CLOCK_SPEED[0] DCM0:DRP44[6]	DCM0:DFS_SYNTH_CLOCK_SPEED[1] DCM0:DRP44[7]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_WAIT_PLL DCM0:DRP44[9]	DCM0:DFS_SYNTH_CLOCK_SPEED[2] DCM0:DRP44[8]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKIN_DIVIDE_BY_2 DCM0:DRP44[10]	DCM0:DCM_CLKIN_IODLY_MUXINSEL DCM0:DRP44[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_SYNC_TO_DLL DCM0:DRP44[13]	DCM0:DCM_CLKFB_IODLY_MUXINSEL DCM0:DRP44[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_EN DCM0:DRP44[14]	DCM0:DFS_FAST_UPDATE DCM0:DRP44[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[1] DCM0:DRP45[1]	DCM0:DFS_TAPTRIM[0] DCM0:DRP45[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[2] DCM0:DRP45[2]	DCM0:DFS_TAPTRIM[3] DCM0:DRP45[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[5] DCM0:DRP45[5]	DCM0:DFS_TAPTRIM[4] DCM0:DRP45[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[6] DCM0:DRP45[6]	DCM0:DFS_TAPTRIM[7] DCM0:DRP45[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[9] DCM0:DRP45[9]	DCM0:DFS_TAPTRIM[8] DCM0:DRP45[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TAPTRIM[10] DCM0:DRP45[10]	DCM0:DRP45[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP45[13]	DCM0:DRP45[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP45[14]	DCM0:DRP45[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TWEAK[1] DCM0:DRP46[1]	DCM0:DFS_TWEAK[0] DCM0:DRP46[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TWEAK[2] DCM0:DRP46[2]	DCM0:DFS_TWEAK[3] DCM0:DRP46[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TWEAK[5] DCM0:DRP46[5]	DCM0:DFS_TWEAK[4] DCM0:DRP46[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_TWEAK[6] DCM0:DRP46[6]	DCM0:DFS_TWEAK[7] DCM0:DRP46[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP46[9]	DCM0:DRP46[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP46[10]	DCM0:DRP46[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP46[13]	DCM0:DRP46[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP46[14]	DCM0:DRP46[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP47[1] DCM0:ENABLE.CLKFX180	DCM0:DRP47[0] DCM0:ENABLE.CLKFX
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP47[2] DCM0:ENABLE.CONCUR	DCM0:DFS_OUTPUT_PSDLY_ON_CONCUR DCM0:DRP47[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_UNUSED_TAPS_POWERDOWN[0] DCM0:DRP47[5]	~DCM0:DFS_EN_RELRST_B DCM0:DRP47[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_MPW_LOW DCM0:DRP47[6]	DCM0:DFS_MPW_HIGH DCM0:DRP47[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_CUSTOM_FAST_SYNC[0] DCM0:DRP47[9]	DCM0:DCM_CLKDV_CLKFX_ALIGNMENT DCM0:DRP47[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_CUSTOM_FAST_SYNC[1] DCM0:DRP47[10]	DCM0:DFS_CUSTOM_FAST_SYNC[2] DCM0:DRP47[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[0] DCM0:DRP47[13]	DCM0:DFS_CUSTOM_FAST_SYNC[3] DCM0:DRP47[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[1] DCM0:DRP47[14]	DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[2] DCM0:DRP47[15]

CMT bittile 1
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[1] DCM0:MUX.CLKIN[1]	DCM0:DRP48[0] DCM0:MUX.CLKIN[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[2] DCM0:MUX.CLKIN[2]	DCM0:DRP48[3] DCM0:MUX.CLKIN[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[5] DCM0:MUX.CLKFB[0]	DCM0:DRP48[4] DCM0:MUX.CLKIN[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[6] DCM0:MUX.CLKFB[1]	DCM0:DRP48[7] DCM0:MUX.CLKFB[2]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[9] DCM0:MUX.CLKFB[4]	DCM0:DRP48[8] DCM0:MUX.CLKFB[3]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[10] DCM0:MUX.CLK_TO_PLL[0]	DCM0:DRP48[11] DCM0:MUX.CLK_TO_PLL[1]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[13] DCM0:MUX.CLK_TO_PLL[3]	DCM0:DRP48[12] DCM0:MUX.CLK_TO_PLL[2]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP48[14] DCM0:INV.SKEWCLKIN1	DCM0:DRP48[15] DCM0:INV.SKEWCLKIN2
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[1] DCM0:MUX.SKEWCLKIN2[1]	DCM0:DRP49[0] DCM0:MUX.SKEWCLKIN2[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[2] DCM0:MUX.SKEWCLKIN2[2]	DCM0:DRP49[3] DCM0:MUX.SKEWCLKIN2[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[5] DCM0:INV.SKEWRST	DCM0:DRP49[4] DCM0:INV.SKEWIN
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKIN_CLKFB_ENABLE DCM0:DRP49[6]	DCM0:DRP49[7]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[9]	DCM0:DRP49[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[10]	DCM0:DRP49[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[13]	DCM0:DRP49[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP49[14]	DCM0:DCM_REG_PWRD_CFG DCM0:DRP49[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[1]	DCM0:DRP4A[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[2]	DCM0:DRP4A[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[5]	DCM0:DRP4A[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[6]	DCM0:DRP4A[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[9]	DCM0:DRP4A[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[10]	DCM0:DRP4A[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[13]	DCM0:DRP4A[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4A[14]	DCM0:DRP4A[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PHASE_SHIFT_CALIBRATION[1] DCM0:DRP4B[1]	DCM0:DLL_PHASE_SHIFT_CALIBRATION[0] DCM0:DRP4B[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[2] DCM0:PS_CENTERED	DCM0:DRP4B[3] DCM0:PS_DIRECT
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[5] DCM0:INV.RST	DCM0:DLL_PHASE_SHIFT_LOCK_BY1 DCM0:DRP4B[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[6] DCM0:INV.PSINCDEC	DCM0:DRP4B[7] DCM0:INV.PSEN
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[9]	DCM0:DRP4B[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[10]	DCM0:DRP4B[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[13]	DCM0:DRP4B[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4B[14]	DCM0:DRP4B[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_SCANMODE DCM0:DRP4C[1]	DCM0:DCM_UNUSED_TAPS_POWERDOWN[2] DCM0:DRP4C[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_TAPINIT_CTL[0] DCM0:DRP4C[2]	DCM0:DLL_TAPINIT_CTL[1] DCM0:DRP4C[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4C[5]	DCM0:DLL_TAPINIT_CTL[2] DCM0:DRP4C[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DLL_PWRD_ON_SCANMODE_B DCM0:DRP4C[6]	DCM0:DLL_ZD1_PHASE_SEL_INIT[0] DCM0:DRP4C[7]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PERIOD_LOCK_BY1 DCM0:DRP4C[9]	DCM0:DLL_ZD1_PHASE_SEL_INIT[1] DCM0:DRP4C[8]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_LOCK_BY1 DCM0:DRP4C[10]	DCM0:DLL_ZD2_JF_OVERFLOW_HOLD DCM0:DRP4C[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_JF_OVERFLOW_HOLD DCM0:DRP4C[13]	DCM0:DCM_UNUSED_TAPS_POWERDOWN[3] DCM0:DRP4C[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_UNUSED_TAPS_POWERDOWN[1] DCM0:DRP4C[14]	DCM0:DRP4C[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_TAP_INIT[1] DCM0:DRP4D[1]	DCM0:DLL_ZD2_TAP_INIT[0] DCM0:DRP4D[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_TAP_INIT[2] DCM0:DRP4D[2]	DCM0:DLL_ZD2_TAP_INIT[3] DCM0:DRP4D[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_TAP_INIT[5] DCM0:DRP4D[5]	DCM0:DLL_ZD2_TAP_INIT[4] DCM0:DRP4D[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_TAP_INIT[6] DCM0:DRP4D[6]	DCM0:DRP4D[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_TAP_INIT[1] DCM0:DRP4D[9]	DCM0:DLL_ZD1_TAP_INIT[0] DCM0:DRP4D[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_TAP_INIT[2] DCM0:DRP4D[10]	DCM0:DLL_ZD1_TAP_INIT[3] DCM0:DRP4D[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_TAP_INIT[5] DCM0:DRP4D[13]	DCM0:DLL_ZD1_TAP_INIT[4] DCM0:DRP4D[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_TAP_INIT[6] DCM0:DRP4D[14]	DCM0:DLL_ZD1_TAP_INIT[7] DCM0:DRP4D[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MINTAP[1] DCM0:DRP4E[1]	DCM0:DLL_DESKEW_MINTAP[0] DCM0:DRP4E[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MINTAP[2] DCM0:DRP4E[2]	DCM0:DLL_DESKEW_MINTAP[3] DCM0:DRP4E[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MINTAP[5] DCM0:DRP4E[5]	DCM0:DLL_DESKEW_MINTAP[4] DCM0:DRP4E[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MINTAP[6] DCM0:DRP4E[6]	DCM0:DLL_DESKEW_MINTAP[7] DCM0:DRP4E[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MAXTAP[1] DCM0:DRP4E[9]	DCM0:DLL_DESKEW_MAXTAP[0] DCM0:DRP4E[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MAXTAP[2] DCM0:DRP4E[10]	DCM0:DLL_DESKEW_MAXTAP[3] DCM0:DRP4E[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MAXTAP[5] DCM0:DRP4E[13]	DCM0:DLL_DESKEW_MAXTAP[4] DCM0:DRP4E[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DESKEW_MAXTAP[6] DCM0:DRP4E[14]	DCM0:DLL_DESKEW_MAXTAP[7] DCM0:DRP4E[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[1] DCM0:FACTORY_JF[1]	DCM0:DRP4F[0] DCM0:FACTORY_JF[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[2] DCM0:FACTORY_JF[2]	DCM0:DRP4F[3] DCM0:FACTORY_JF[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[5] DCM0:FACTORY_JF[5]	DCM0:DRP4F[4] DCM0:FACTORY_JF[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[6] DCM0:FACTORY_JF[6]	DCM0:DRP4F[7] DCM0:FACTORY_JF[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[9] DCM0:FACTORY_JF[9]	DCM0:DRP4F[8] DCM0:FACTORY_JF[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[10] DCM0:FACTORY_JF[10]	DCM0:DRP4F[11] DCM0:FACTORY_JF[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[13] DCM0:FACTORY_JF[13]	DCM0:DRP4F[12] DCM0:FACTORY_JF[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP4F[14] DCM0:FACTORY_JF[14]	DCM0:DRP4F[15] DCM0:FACTORY_JF[15]

CMT bittile 2
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_DIVIDE[1] DCM0:DRP50[1]	DCM0:CLKFX_DIVIDE[0] DCM0:DRP50[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_DIVIDE[2] DCM0:DRP50[2]	DCM0:CLKFX_DIVIDE[3] DCM0:DRP50[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_DIVIDE[5] DCM0:DRP50[5]	DCM0:CLKFX_DIVIDE[4] DCM0:DRP50[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_DIVIDE[6] DCM0:DRP50[6]	DCM0:CLKFX_DIVIDE[7] DCM0:DRP50[7]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_MULTIPLY[1] DCM0:DRP50[9]	DCM0:CLKFX_MULTIPLY[0] DCM0:DRP50[8]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_MULTIPLY[2] DCM0:DRP50[10]	DCM0:CLKFX_MULTIPLY[3] DCM0:DRP50[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_MULTIPLY[5] DCM0:DRP50[13]	DCM0:CLKFX_MULTIPLY[4] DCM0:DRP50[12]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKFX_MULTIPLY[6] DCM0:DRP50[14]	DCM0:CLKFX_MULTIPLY[7] DCM0:DRP50[15]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DLL_CLKIN_STOPPED_PWRD_EN_B DCM0:DRP51[1]	~DCM0:DLL_CLKFB_STOPPED_PWRD_EN_B DCM0:DRP51[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_FREQUENCY_MODE[0] DCM0:DRP51[2]	DCM0:DLL_FREQUENCY_MODE[1] DCM0:DRP51[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_EN DCM0:DRP51[5]	DCM0:DRP51[4] DCM0:PS_MODE
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_EN DCM0:DRP51[6]	DCM0:DRP51[7] DCM0:PS_ENABLE
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_SETTLE_TIME[1] DCM0:DRP51[9]	DCM0:DLL_SETTLE_TIME[0] DCM0:DRP51[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_SETTLE_TIME[2] DCM0:DRP51[10]	DCM0:DLL_SETTLE_TIME[3] DCM0:DRP51[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_SETTLE_TIME[5] DCM0:DRP51[13]	DCM0:DLL_SETTLE_TIME[4] DCM0:DRP51[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_SETTLE_TIME[6] DCM0:DRP51[14]	DCM0:DLL_SETTLE_TIME[7] DCM0:DRP51[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_LIVE_TIME[1] DCM0:DRP52[1]	DCM0:DLL_LIVE_TIME[0] DCM0:DRP52[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_LIVE_TIME[2] DCM0:DRP52[2]	DCM0:DLL_LIVE_TIME[3] DCM0:DRP52[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_LIVE_TIME[5] DCM0:DRP52[5]	DCM0:DLL_LIVE_TIME[4] DCM0:DRP52[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_LIVE_TIME[6] DCM0:DRP52[6]	DCM0:DLL_LIVE_TIME[7] DCM0:DRP52[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DEAD_TIME[1] DCM0:DRP52[9]	DCM0:DLL_DEAD_TIME[0] DCM0:DRP52[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DEAD_TIME[2] DCM0:DRP52[10]	DCM0:DLL_DEAD_TIME[3] DCM0:DRP52[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DEAD_TIME[5] DCM0:DRP52[13]	DCM0:DLL_DEAD_TIME[4] DCM0:DRP52[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_DEAD_TIME[6] DCM0:DRP52[14]	DCM0:DLL_DEAD_TIME[7] DCM0:DRP52[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_MAX[1] DCM0:DRP53[1]	DCM0:CLKDV_COUNT_MAX[0] DCM0:DRP53[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_MAX[2] DCM0:DRP53[2]	DCM0:CLKDV_COUNT_MAX[3] DCM0:DRP53[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_FALL[1] DCM0:DRP53[5]	DCM0:CLKDV_COUNT_FALL[0] DCM0:DRP53[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_FALL[2] DCM0:DRP53[6]	DCM0:CLKDV_COUNT_FALL[3] DCM0:DRP53[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_FALL_2[1] DCM0:DRP53[9]	DCM0:CLKDV_COUNT_FALL_2[0] DCM0:DRP53[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_COUNT_FALL_2[2] DCM0:DRP53[10]	DCM0:CLKDV_COUNT_FALL_2[3] DCM0:DRP53[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_PHASE_RISE[1] DCM0:DRP53[13]	DCM0:CLKDV_PHASE_RISE[0] DCM0:DRP53[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:CLKDV_PHASE_FALL[0] DCM0:DRP53[14]	DCM0:CLKDV_PHASE_FALL[1] DCM0:DRP53[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_FDBKLOST_EN DCM0:DRP54[1]	DCM0:CLKDV_MODE DCM0:DRP54[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_CLKLOST_EN DCM0:DRP54[2]	~DCM0:DCM_LOCK_HIGH_B DCM0:DRP54[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP54[5] DCM0:ENABLE.CLK90	DCM0:DRP54[4] DCM0:ENABLE.CLK0
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP54[6] DCM0:ENABLE.CLK180	DCM0:DRP54[7] DCM0:ENABLE.CLK270
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP54[9] DCM0:ENABLE.CLK2X180	DCM0:DRP54[8] DCM0:ENABLE.CLK2X
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP54[10] DCM0:ENABLE.CLKDV	DCM0:DCM_TRIM_CAL[0] DCM0:DRP54[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_TRIM_CAL[2] DCM0:DRP54[13]	DCM0:DCM_TRIM_CAL[1] DCM0:DRP54[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_TEST_MUX_SEL[0] DCM0:DRP54[14]	DCM0:DLL_TEST_MUX_SEL[1] DCM0:DRP54[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[1] DCM0:PHASE_SHIFT[1]	DCM0:DRP55[0] DCM0:PHASE_SHIFT[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[2] DCM0:PHASE_SHIFT[2]	DCM0:DRP55[3] DCM0:PHASE_SHIFT[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[5] DCM0:PHASE_SHIFT[5]	DCM0:DRP55[4] DCM0:PHASE_SHIFT[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[6] DCM0:PHASE_SHIFT[6]	DCM0:DRP55[7] DCM0:PHASE_SHIFT[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[9] DCM0:PHASE_SHIFT[9]	DCM0:DRP55[8] DCM0:PHASE_SHIFT[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[10] DCM0:PHASE_SHIFT_NEGATIVE	DCM0:DRP55[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[13]	DCM0:DRP55[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP55[14]	DCM0:DRP55[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PHASE_SHIFT_LFC[1] DCM0:DRP56[1]	DCM0:DLL_PHASE_SHIFT_LFC[0] DCM0:DRP56[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PHASE_SHIFT_LFC[2] DCM0:DRP56[2]	DCM0:DLL_PHASE_SHIFT_LFC[3] DCM0:DRP56[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PHASE_SHIFT_LFC[5] DCM0:DRP56[5]	DCM0:DLL_PHASE_SHIFT_LFC[4] DCM0:DRP56[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_PHASE_SHIFT_LFC[6] DCM0:DRP56[6]	DCM0:DLL_PHASE_SHIFT_LFC[7] DCM0:DRP56[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_PWC_TAP[0] DCM0:DRP56[9]	DCM0:DLL_PHASE_SHIFT_LFC[8] DCM0:DRP56[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_PWC_TAP[1] DCM0:DRP56[10]	DCM0:DLL_ZD2_PWC_TAP[2] DCM0:DRP56[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_PWC_TAP[1] DCM0:DRP56[13]	DCM0:DLL_ZD1_PWC_TAP[0] DCM0:DRP56[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_PWC_TAP[2] DCM0:DRP56[14]	DCM0:DCM_VREG_ENABLE DCM0:DRP56[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD1_PWC_EN DCM0:DRP57[1]	DCM0:DCM_VSPLY_VALID_ACC[0] DCM0:DRP57[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DRP57[2] DCM0:STARTUP_WAIT	DCM0:DCM_VBG_SEL[0] DCM0:DRP57[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ETPP_HOLD DCM0:DRP57[5]	DCM0:DCM_VBG_SEL[1] DCM0:DRP57[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DLL_PWRD_STICKY_B DCM0:DRP57[6]	DCM0:DCM_VBG_SEL[2] DCM0:DRP57[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DLL_ZD2_PWC_EN DCM0:DRP57[9]	DCM0:DCM_VBG_SEL[3] DCM0:DRP57[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM0:DCM_POWERDOWN_COMMON_EN_B DCM0:DRP57[10]	DCM0:DCM_VBG_PD[0] DCM0:DRP57[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COMMON_MSB_SEL[0] DCM0:DRP57[13]	DCM0:DCM_VBG_PD[1] DCM0:DRP57[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM0:DCM_COMMON_MSB_SEL[1] DCM0:DRP57[14]	DCM0:DCM_VSPLY_VALID_ACC[1] DCM0:DRP57[15]

CMT bittile 3
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[1] PLL:PLL_LF_PEN[0]	PLL:DRP00[0] PLL:PLL_MAN_LF_EN
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[2] PLL:PLL_LF_PEN[1]	PLL:DRP00[3] PLL:PLL_LF_NEN[0]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[5] PLL:PLL_VLFHIGH_DIS	PLL:DRP00[4] PLL:PLL_LF_NEN[1]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[6] PLL:PLL_RES[0]	PLL:DRP00[7] PLL:PLL_RES[1]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[9] PLL:PLL_RES[3]	PLL:DRP00[8] PLL:PLL_RES[2]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[10] PLL:PLL_MISC[0]	PLL:DRP00[11] PLL:PLL_MISC[1]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[13] PLL:PLL_MISC[3]	PLL:DRP00[12] PLL:PLL_MISC[2]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP00[14] PLL:PLL_CP_BIAS_TRIP_SHIFT	PLL:DRP00[15] PLL:PLL_SEL_SLIPD
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[1] PLL:PLL_CP[1]	PLL:DRP01[0] PLL:PLL_CP[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[2] PLL:PLL_CP[2]	PLL:DRP01[3] PLL:PLL_CP[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[5] PLL:PLL_CP_RES[1]	PLL:DRP01[4] PLL:PLL_CP_RES[0]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[6] PLL:PLL_LFHF[0]	PLL:DRP01[7] PLL:PLL_LFHF[1]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[9] PLL:PLL_PFD_DLY[1]	PLL:DRP01[8] PLL:PLL_PFD_DLY[0]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[10] PLL:PLL_PFD_CNTRL[0]	PLL:DRP01[11] PLL:PLL_PFD_CNTRL[1]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[13] PLL:PLL_PFD_CNTRL[3]	PLL:DRP01[12] PLL:PLL_PFD_CNTRL[2]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP01[14]	PLL:DRP01[15] PLL:PLL_PWRD_CFG
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[1] PLL:PLL_LOCK_CNT[1]	PLL:DRP02[0] PLL:PLL_LOCK_CNT[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[2] PLL:PLL_LOCK_CNT[2]	PLL:DRP02[3] PLL:PLL_LOCK_CNT[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[5] PLL:PLL_LOCK_CNT[5]	PLL:DRP02[4] PLL:PLL_LOCK_CNT[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[6] PLL:PLL_LOCK_REF_P1[0]	PLL:DRP02[7] PLL:PLL_LOCK_REF_P1[1]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[9] PLL:PLL_LOCK_REF_P1[3]	PLL:DRP02[8] PLL:PLL_LOCK_REF_P1[2]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[10] PLL:PLL_LOCK_REF_P1[4]	PLL:DRP02[11] PLL:PLL_LOCK_REF_P2[0]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[13] PLL:PLL_LOCK_REF_P2[2]	PLL:DRP02[12] PLL:PLL_LOCK_REF_P2[1]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP02[14] PLL:PLL_LOCK_REF_P2[3]	PLL:DRP02[15] PLL:PLL_LOCK_REF_P2[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[1] PLL:PLL_LOCK_FB_P1[1]	PLL:DRP03[0] PLL:PLL_LOCK_FB_P1[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[2] PLL:PLL_LOCK_FB_P1[2]	PLL:DRP03[3] PLL:PLL_LOCK_FB_P1[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[5] PLL:PLL_LOCK_FB_P2[0]	PLL:DRP03[4] PLL:PLL_LOCK_FB_P1[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[6] PLL:PLL_LOCK_FB_P2[1]	PLL:DRP03[7] PLL:PLL_LOCK_FB_P2[2]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[9] PLL:PLL_LOCK_FB_P2[4]	PLL:DRP03[8] PLL:PLL_LOCK_FB_P2[3]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[10] PLL:PLL_INC_SLOCK	PLL:DRP03[11] PLL:PLL_INC_FLOCK
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[13] PLL:PLL_UNLOCK_CNT[1]	PLL:DRP03[12] PLL:PLL_UNLOCK_CNT[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP03[14] PLL:PLL_UNLOCK_CNT[2]	PLL:DRP03[15] PLL:PLL_UNLOCK_CNT[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[1] PLL:PLL_UNLOCK_CNT_RST_FAST	PLL:DRP04[0] PLL:PLL_LOCK_CNT_RST_FAST
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[2] PLL:PLL_FLOCK[0]	PLL:DRP04[3] PLL:PLL_FLOCK[1]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[5] PLL:PLL_FLOCK[3]	PLL:DRP04[4] PLL:PLL_FLOCK[2]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[6] PLL:PLL_FLOCK[4]	PLL:DRP04[7] PLL:PLL_FLOCK[5]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[9] PLL:PLL_INTFB[1]	PLL:DRP04[8] PLL:PLL_INTFB[0]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[10] PLL:PLL_EN_TCLK0	PLL:DRP04[11] PLL:PLL_EN_TCLK1
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[13] PLL:PLL_EN_TCLK3	PLL:DRP04[12] PLL:PLL_EN_TCLK2
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP04[14] PLL:PLL_EN_TCLK4	PLL:DRP04[15] ~PLL:PLL_TCK4_SEL
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[1] PLL:PLL_EN_CNTRL[1]	PLL:DRP05[0] PLL:PLL_EN_CNTRL[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[2] PLL:PLL_EN_CNTRL[2]	PLL:DRP05[3] PLL:PLL_EN_CNTRL[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[5] PLL:PLL_EN_CNTRL[5]	PLL:DRP05[4] PLL:PLL_EN_CNTRL[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[6] PLL:PLL_EN_CNTRL[6]	PLL:DRP05[7] PLL:PLL_EN_CNTRL[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[9] PLL:PLL_EN_CNTRL[9]	PLL:DRP05[8] PLL:PLL_EN_CNTRL[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[10] PLL:PLL_EN_CNTRL[10]	PLL:DRP05[11] PLL:PLL_EN_CNTRL[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[13] PLL:PLL_EN_CNTRL[13]	PLL:DRP05[12] PLL:PLL_EN_CNTRL[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP05[14] PLL:PLL_EN_CNTRL[14]	PLL:DRP05[15] PLL:PLL_EN_CNTRL[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[1] PLL:PLL_DIVCLK_LT[1]	PLL:DRP06[0] PLL:PLL_DIVCLK_LT[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[2] PLL:PLL_DIVCLK_LT[2]	PLL:DRP06[3] PLL:PLL_DIVCLK_LT[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[5] PLL:PLL_DIVCLK_LT[5]	PLL:DRP06[4] PLL:PLL_DIVCLK_LT[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[6] PLL:PLL_DIVCLK_HT[0]	PLL:DRP06[7] PLL:PLL_DIVCLK_HT[1]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[9] PLL:PLL_DIVCLK_HT[3]	PLL:DRP06[8] PLL:PLL_DIVCLK_HT[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[10] PLL:PLL_DIVCLK_HT[4]	PLL:DRP06[11] PLL:PLL_DIVCLK_HT[5]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[13] PLL:PLL_DIVCLK_EDGE	PLL:DRP06[12] PLL:PLL_DIVCLK_NOCOUNT
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP06[14]	PLL:DRP06[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[1] PLL:PLL_IN_DLY_SET[1]	PLL:DRP07[0] PLL:PLL_IN_DLY_SET[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[2] PLL:PLL_IN_DLY_SET[2]	PLL:DRP07[3] PLL:PLL_IN_DLY_SET[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[5] PLL:PLL_IN_DLY_SET[5]	PLL:DRP07[4] PLL:PLL_IN_DLY_SET[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[6] PLL:PLL_IN_DLY_SET[6]	PLL:DRP07[7] PLL:PLL_IN_DLY_SET[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[9] PLL:PLL_EN_DLY	PLL:DRP07[8] PLL:PLL_IN_DLY_SET[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[10] PLL:PLL_IN_DLY_MX_SEL[0]	PLL:DRP07[11] PLL:PLL_IN_DLY_MX_SEL[1]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[13] PLL:PLL_IN_DLY_MX_SEL[3]	PLL:DRP07[12] PLL:PLL_IN_DLY_MX_SEL[2]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP07[14] PLL:PLL_IN_DLY_MX_SEL[4]	PLL:DRP07[15]

CMT bittile 4
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[1] PLL:PLL_EN_CNTRL[17]	PLL:DRP08[0] PLL:PLL_EN_CNTRL[16]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[2] PLL:PLL_EN_CNTRL[18]	PLL:DRP08[3] PLL:PLL_EN_CNTRL[19]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[5] PLL:PLL_EN_CNTRL[21]	PLL:DRP08[4] PLL:PLL_EN_CNTRL[20]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[6] PLL:PLL_EN_CNTRL[22]	PLL:DRP08[7] PLL:PLL_EN_CNTRL[23]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[9] PLL:PLL_EN_CNTRL[25]	PLL:DRP08[8] PLL:PLL_EN_CNTRL[24]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[10] PLL:PLL_EN_CNTRL[26]	PLL:DRP08[11] PLL:PLL_EN_CNTRL[27]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[13] PLL:PLL_EN_CNTRL[29]	PLL:DRP08[12] PLL:PLL_EN_CNTRL[28]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP08[14] PLL:PLL_EN_CNTRL[30]	PLL:DRP08[15] PLL:PLL_EN_CNTRL[31]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[1] PLL:PLL_CLKFBOUT2_LT[1]	PLL:DRP09[0] PLL:PLL_CLKFBOUT2_LT[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[2] PLL:PLL_CLKFBOUT2_LT[2]	PLL:DRP09[3] PLL:PLL_CLKFBOUT2_LT[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[5] PLL:PLL_CLKFBOUT2_LT[5]	PLL:DRP09[4] PLL:PLL_CLKFBOUT2_LT[4]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[6] PLL:PLL_CLKFBOUT2_HT[0]	PLL:DRP09[7] PLL:PLL_CLKFBOUT2_HT[1]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[9] PLL:PLL_CLKFBOUT2_HT[3]	PLL:DRP09[8] PLL:PLL_CLKFBOUT2_HT[2]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[10] PLL:PLL_CLKFBOUT2_HT[4]	PLL:DRP09[11] PLL:PLL_CLKFBOUT2_HT[5]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[13]	PLL:DRP09[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP09[14]	PLL:DRP09[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[1] PLL:PLL_CLKFBOUT2_DT[1]	PLL:DRP0A[0] PLL:PLL_CLKFBOUT2_DT[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[2] PLL:PLL_CLKFBOUT2_DT[2]	PLL:DRP0A[3] PLL:PLL_CLKFBOUT2_DT[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[5] PLL:PLL_CLKFBOUT2_DT[5]	PLL:DRP0A[4] PLL:PLL_CLKFBOUT2_DT[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[6] PLL:PLL_CLKFBOUT2_NOCOUNT	PLL:DRP0A[7] PLL:PLL_CLKFBOUT2_EDGE
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[9]	PLL:DRP0A[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[10] PLL:PLL_DIVCLK_DT[0]	PLL:DRP0A[11] PLL:PLL_DIVCLK_DT[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[13] PLL:PLL_DIVCLK_DT[3]	PLL:DRP0A[12] PLL:PLL_DIVCLK_DT[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0A[14] PLL:PLL_DIVCLK_DT[4]	PLL:DRP0A[15] PLL:PLL_DIVCLK_DT[5]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[1] PLL:PLL_EN_CNTRL[33]	PLL:DRP0B[0] PLL:PLL_EN_CNTRL[32]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[2] PLL:PLL_EN_CNTRL[34]	PLL:DRP0B[3] PLL:PLL_EN_CNTRL[35]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[5] PLL:PLL_EN_CNTRL[37]	PLL:DRP0B[4] PLL:PLL_EN_CNTRL[36]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[6] PLL:PLL_EN_CNTRL[38]	PLL:DRP0B[7] PLL:PLL_EN_CNTRL[39]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[9] PLL:PLL_EN_CNTRL[41]	PLL:DRP0B[8] PLL:PLL_EN_CNTRL[40]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[10] PLL:PLL_EN_CNTRL[42]	PLL:DRP0B[11] PLL:PLL_EN_CNTRL[43]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[13] PLL:PLL_EN_CNTRL[45]	PLL:DRP0B[12] PLL:PLL_EN_CNTRL[44]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0B[14] PLL:PLL_EN_CNTRL[46]	PLL:DRP0B[15] PLL:PLL_EN_CNTRL[47]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[1] PLL:PLL_CLKFBOUT_LT[1]	PLL:DRP0C[0] PLL:PLL_CLKFBOUT_LT[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[2] PLL:PLL_CLKFBOUT_LT[2]	PLL:DRP0C[3] PLL:PLL_CLKFBOUT_LT[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[5] PLL:PLL_CLKFBOUT_LT[5]	PLL:DRP0C[4] PLL:PLL_CLKFBOUT_LT[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[6] PLL:PLL_CLKFBOUT_HT[0]	PLL:DRP0C[7] PLL:PLL_CLKFBOUT_HT[1]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[9] PLL:PLL_CLKFBOUT_HT[3]	PLL:DRP0C[8] PLL:PLL_CLKFBOUT_HT[2]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[10] PLL:PLL_CLKFBOUT_HT[4]	PLL:DRP0C[11] PLL:PLL_CLKFBOUT_HT[5]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[13] PLL:PLL_CLKFBOUT_PM[0]	PLL:DRP0C[12] PLL:PLL_CLKFBOUT_EN
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0C[14] PLL:PLL_CLKFBOUT_PM[1]	PLL:DRP0C[15] PLL:PLL_CLKFBOUT_PM[2]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[1] PLL:PLL_CLKFBOUT_DT[1]	PLL:DRP0D[0] PLL:PLL_CLKFBOUT_DT[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[2] PLL:PLL_CLKFBOUT_DT[2]	PLL:DRP0D[3] PLL:PLL_CLKFBOUT_DT[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[5] PLL:PLL_CLKFBOUT_DT[5]	PLL:DRP0D[4] PLL:PLL_CLKFBOUT_DT[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[6] PLL:PLL_CLKFBOUT_NOCOUNT	PLL:DRP0D[7] PLL:PLL_CLKFBOUT_EDGE
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[9] PLL:PLL_CLKFBMX[1]	PLL:DRP0D[8] PLL:PLL_CLKFBMX[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0D[10] PLL:PLL_NBTI_EN	PLL:CLKFBOUT_DESKEW_ADJUST[0] PLL:DRP0D[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKFBOUT_DESKEW_ADJUST[2] PLL:DRP0D[13]	PLL:CLKFBOUT_DESKEW_ADJUST[1] PLL:DRP0D[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKFBOUT_DESKEW_ADJUST[3] PLL:DRP0D[14]	PLL:CLKFBOUT_DESKEW_ADJUST[4] PLL:DRP0D[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[1] PLL:PLL_CLKOUT5_LT[1]	PLL:DRP0E[0] PLL:PLL_CLKOUT5_LT[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[2] PLL:PLL_CLKOUT5_LT[2]	PLL:DRP0E[3] PLL:PLL_CLKOUT5_LT[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[5] PLL:PLL_CLKOUT5_LT[5]	PLL:DRP0E[4] PLL:PLL_CLKOUT5_LT[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[6] PLL:PLL_CLKOUT5_HT[0]	PLL:DRP0E[7] PLL:PLL_CLKOUT5_HT[1]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[9] PLL:PLL_CLKOUT5_HT[3]	PLL:DRP0E[8] PLL:PLL_CLKOUT5_HT[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[10] PLL:PLL_CLKOUT5_HT[4]	PLL:DRP0E[11] PLL:PLL_CLKOUT5_HT[5]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[13] PLL:PLL_CLKOUT5_PM[0]	PLL:DRP0E[12] PLL:PLL_CLKOUT5_EN
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0E[14] PLL:PLL_CLKOUT5_PM[1]	PLL:DRP0E[15] PLL:PLL_CLKOUT5_PM[2]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[1] PLL:PLL_CLKOUT5_DT[1]	PLL:DRP0F[0] PLL:PLL_CLKOUT5_DT[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[2] PLL:PLL_CLKOUT5_DT[2]	PLL:DRP0F[3] PLL:PLL_CLKOUT5_DT[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[5] PLL:PLL_CLKOUT5_DT[5]	PLL:DRP0F[4] PLL:PLL_CLKOUT5_DT[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[6] PLL:PLL_CLKOUT5_NOCOUNT	PLL:DRP0F[7] PLL:PLL_CLKOUT5_EDGE
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[9] PLL:PLL_CLK5MX[1]	PLL:DRP0F[8] PLL:PLL_CLK5MX[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP0F[10]	PLL:CLKOUT5_DESKEW_ADJUST[0] PLL:DRP0F[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT5_DESKEW_ADJUST[2] PLL:DRP0F[13]	PLL:CLKOUT5_DESKEW_ADJUST[1] PLL:DRP0F[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT5_DESKEW_ADJUST[3] PLL:DRP0F[14]	PLL:CLKOUT5_DESKEW_ADJUST[4] PLL:DRP0F[15]

CMT bittile 5
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[1] PLL:PLL_EN_CNTRL[49]	PLL:DRP10[0] PLL:PLL_EN_CNTRL[48]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[2] PLL:PLL_EN_CNTRL[50]	PLL:DRP10[3] PLL:PLL_EN_CNTRL[51]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[5] PLL:PLL_EN_CNTRL[53]	PLL:DRP10[4] PLL:PLL_EN_CNTRL[52]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[6] PLL:PLL_EN_CNTRL[54]	PLL:DRP10[7] PLL:PLL_EN_CNTRL[55]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[9] PLL:PLL_EN_CNTRL[57]	PLL:DRP10[8] PLL:PLL_EN_CNTRL[56]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[10] PLL:PLL_EN_CNTRL[58]	PLL:DRP10[11] PLL:PLL_EN_CNTRL[59]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[13] PLL:PLL_EN_CNTRL[61]	PLL:DRP10[12] PLL:PLL_EN_CNTRL[60]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP10[14] PLL:PLL_EN_CNTRL[62]	PLL:DRP10[15] PLL:PLL_EN_CNTRL[63]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[1] PLL:PLL_EN_CNTRL[65]	PLL:DRP11[0] PLL:PLL_EN_CNTRL[64]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[2] PLL:PLL_EN_CNTRL[66]	PLL:DRP11[3] PLL:PLL_EN_CNTRL[67]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[5] PLL:PLL_EN_CNTRL[69]	PLL:DRP11[4] PLL:PLL_EN_CNTRL[68]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[6] PLL:PLL_EN_CNTRL[70]	PLL:DRP11[7] PLL:PLL_EN_CNTRL[71]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[9] PLL:PLL_EN_CNTRL[73]	PLL:DRP11[8] PLL:PLL_EN_CNTRL[72]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[10] PLL:PLL_EN_CNTRL[74]	PLL:DRP11[11] PLL:PLL_EN_CNTRL[75]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[13] PLL:PLL_EN_CNTRL[77]	PLL:DRP11[12] PLL:PLL_EN_CNTRL[76]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP11[14] PLL:PLL_PMCD_MODE	PLL:DRP11[15] PLL:PLL_EN
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[1] PLL:PLL_CLKOUT4_LT[1]	PLL:DRP12[0] PLL:PLL_CLKOUT4_LT[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[2] PLL:PLL_CLKOUT4_LT[2]	PLL:DRP12[3] PLL:PLL_CLKOUT4_LT[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[5] PLL:PLL_CLKOUT4_LT[5]	PLL:DRP12[4] PLL:PLL_CLKOUT4_LT[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[6] PLL:PLL_CLKOUT4_HT[0]	PLL:DRP12[7] PLL:PLL_CLKOUT4_HT[1]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[9] PLL:PLL_CLKOUT4_HT[3]	PLL:DRP12[8] PLL:PLL_CLKOUT4_HT[2]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[10] PLL:PLL_CLKOUT4_HT[4]	PLL:DRP12[11] PLL:PLL_CLKOUT4_HT[5]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[13] PLL:PLL_CLKOUT4_PM[0]	PLL:DRP12[12] PLL:PLL_CLKOUT4_EN
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP12[14] PLL:PLL_CLKOUT4_PM[1]	PLL:DRP12[15] PLL:PLL_CLKOUT4_PM[2]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[1] PLL:PLL_CLKOUT4_DT[1]	PLL:DRP13[0] PLL:PLL_CLKOUT4_DT[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[2] PLL:PLL_CLKOUT4_DT[2]	PLL:DRP13[3] PLL:PLL_CLKOUT4_DT[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[5] PLL:PLL_CLKOUT4_DT[5]	PLL:DRP13[4] PLL:PLL_CLKOUT4_DT[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[6] PLL:PLL_CLKOUT4_NOCOUNT	PLL:DRP13[7] PLL:PLL_CLKOUT4_EDGE
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[9] PLL:PLL_CLK4MX[1]	PLL:DRP13[8] PLL:PLL_CLK4MX[0]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP13[10]	PLL:CLKOUT4_DESKEW_ADJUST[0] PLL:DRP13[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT4_DESKEW_ADJUST[2] PLL:DRP13[13]	PLL:CLKOUT4_DESKEW_ADJUST[1] PLL:DRP13[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT4_DESKEW_ADJUST[3] PLL:DRP13[14]	PLL:CLKOUT4_DESKEW_ADJUST[4] PLL:DRP13[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[1] PLL:PLL_CLKOUT3_LT[1]	PLL:DRP14[0] PLL:PLL_CLKOUT3_LT[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[2] PLL:PLL_CLKOUT3_LT[2]	PLL:DRP14[3] PLL:PLL_CLKOUT3_LT[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[5] PLL:PLL_CLKOUT3_LT[5]	PLL:DRP14[4] PLL:PLL_CLKOUT3_LT[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[6] PLL:PLL_CLKOUT3_HT[0]	PLL:DRP14[7] PLL:PLL_CLKOUT3_HT[1]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[9] PLL:PLL_CLKOUT3_HT[3]	PLL:DRP14[8] PLL:PLL_CLKOUT3_HT[2]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[10] PLL:PLL_CLKOUT3_HT[4]	PLL:DRP14[11] PLL:PLL_CLKOUT3_HT[5]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[13] PLL:PLL_CLKOUT3_PM[0]	PLL:DRP14[12] PLL:PLL_CLKOUT3_EN
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP14[14] PLL:PLL_CLKOUT3_PM[1]	PLL:DRP14[15] PLL:PLL_CLKOUT3_PM[2]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[1] PLL:PLL_CLKOUT3_DT[1]	PLL:DRP15[0] PLL:PLL_CLKOUT3_DT[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[2] PLL:PLL_CLKOUT3_DT[2]	PLL:DRP15[3] PLL:PLL_CLKOUT3_DT[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[5] PLL:PLL_CLKOUT3_DT[5]	PLL:DRP15[4] PLL:PLL_CLKOUT3_DT[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[6] PLL:PLL_CLKOUT3_NOCOUNT	PLL:DRP15[7] PLL:PLL_CLKOUT3_EDGE
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[9] PLL:PLL_CLK3MX[1]	PLL:DRP15[8] PLL:PLL_CLK3MX[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP15[10]	PLL:CLKOUT3_DESKEW_ADJUST[0] PLL:DRP15[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT3_DESKEW_ADJUST[2] PLL:DRP15[13]	PLL:CLKOUT3_DESKEW_ADJUST[1] PLL:DRP15[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT3_DESKEW_ADJUST[3] PLL:DRP15[14]	PLL:CLKOUT3_DESKEW_ADJUST[4] PLL:DRP15[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[1] PLL:PLL_CLKOUT2_LT[1]	PLL:DRP16[0] PLL:PLL_CLKOUT2_LT[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[2] PLL:PLL_CLKOUT2_LT[2]	PLL:DRP16[3] PLL:PLL_CLKOUT2_LT[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[5] PLL:PLL_CLKOUT2_LT[5]	PLL:DRP16[4] PLL:PLL_CLKOUT2_LT[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[6] PLL:PLL_CLKOUT2_HT[0]	PLL:DRP16[7] PLL:PLL_CLKOUT2_HT[1]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[9] PLL:PLL_CLKOUT2_HT[3]	PLL:DRP16[8] PLL:PLL_CLKOUT2_HT[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[10] PLL:PLL_CLKOUT2_HT[4]	PLL:DRP16[11] PLL:PLL_CLKOUT2_HT[5]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[13] PLL:PLL_CLKOUT2_PM[0]	PLL:DRP16[12] PLL:PLL_CLKOUT2_EN
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP16[14] PLL:PLL_CLKOUT2_PM[1]	PLL:DRP16[15] PLL:PLL_CLKOUT2_PM[2]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[1] PLL:PLL_CLKOUT2_DT[1]	PLL:DRP17[0] PLL:PLL_CLKOUT2_DT[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[2] PLL:PLL_CLKOUT2_DT[2]	PLL:DRP17[3] PLL:PLL_CLKOUT2_DT[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[5] PLL:PLL_CLKOUT2_DT[5]	PLL:DRP17[4] PLL:PLL_CLKOUT2_DT[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[6] PLL:PLL_CLKOUT2_NOCOUNT	PLL:DRP17[7] PLL:PLL_CLKOUT2_EDGE
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[9] PLL:PLL_CLK2MX[1]	PLL:DRP17[8] PLL:PLL_CLK2MX[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP17[10]	PLL:CLKOUT2_DESKEW_ADJUST[0] PLL:DRP17[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT2_DESKEW_ADJUST[2] PLL:DRP17[13]	PLL:CLKOUT2_DESKEW_ADJUST[1] PLL:DRP17[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT2_DESKEW_ADJUST[3] PLL:DRP17[14]	PLL:CLKOUT2_DESKEW_ADJUST[4] PLL:DRP17[15]

CMT bittile 6
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[1] PLL:PLL_EN_VCO_DIV1	PLL:DRP18[0] PLL:PLL_DIRECT_PATH_CNTRL
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[2] PLL:PLL_EN_VCO_DIV6	PLL:DRP18[3] PLL:PLL_EN_VCO0
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[5] PLL:PLL_EN_VCO2	PLL:DRP18[4] PLL:PLL_EN_VCO1
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[6] PLL:PLL_EN_VCO3	PLL:DRP18[7] PLL:PLL_EN_VCO4
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[9] PLL:PLL_EN_VCO6	PLL:DRP18[8] PLL:PLL_EN_VCO5
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[10] PLL:PLL_EN_VCO7	PLL:DRP18[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[13] PLL:PLL_CLKBURST_CNT[0]	PLL:DRP18[12] PLL:PLL_CLKBURST_ENABLE
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP18[14] PLL:PLL_CLKBURST_CNT[1]	PLL:DRP18[15] PLL:PLL_CLKBURST_CNT[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[1] PLL:PLL_CLKOUT1_LT[1]	PLL:DRP19[0] PLL:PLL_CLKOUT1_LT[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[2] PLL:PLL_CLKOUT1_LT[2]	PLL:DRP19[3] PLL:PLL_CLKOUT1_LT[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[5] PLL:PLL_CLKOUT1_LT[5]	PLL:DRP19[4] PLL:PLL_CLKOUT1_LT[4]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[6] PLL:PLL_CLKOUT1_HT[0]	PLL:DRP19[7] PLL:PLL_CLKOUT1_HT[1]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[9] PLL:PLL_CLKOUT1_HT[3]	PLL:DRP19[8] PLL:PLL_CLKOUT1_HT[2]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[10] PLL:PLL_CLKOUT1_HT[4]	PLL:DRP19[11] PLL:PLL_CLKOUT1_HT[5]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[13] PLL:PLL_CLKOUT1_PM[0]	PLL:DRP19[12] PLL:PLL_CLKOUT1_EN
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP19[14] PLL:PLL_CLKOUT1_PM[1]	PLL:DRP19[15] PLL:PLL_CLKOUT1_PM[2]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[1] PLL:PLL_CLKOUT1_DT[1]	PLL:DRP1A[0] PLL:PLL_CLKOUT1_DT[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[2] PLL:PLL_CLKOUT1_DT[2]	PLL:DRP1A[3] PLL:PLL_CLKOUT1_DT[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[5] PLL:PLL_CLKOUT1_DT[5]	PLL:DRP1A[4] PLL:PLL_CLKOUT1_DT[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[6] PLL:PLL_CLKOUT1_NOCOUNT	PLL:DRP1A[7] PLL:PLL_CLKOUT1_EDGE
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[9] PLL:PLL_CLK1MX[1]	PLL:DRP1A[8] PLL:PLL_CLK1MX[0]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1A[10]	PLL:CLKOUT1_DESKEW_ADJUST[0] PLL:DRP1A[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT1_DESKEW_ADJUST[2] PLL:DRP1A[13]	PLL:CLKOUT1_DESKEW_ADJUST[1] PLL:DRP1A[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT1_DESKEW_ADJUST[3] PLL:DRP1A[14]	PLL:CLKOUT1_DESKEW_ADJUST[4] PLL:DRP1A[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[1] PLL:PLL_CLKOUT0_LT[1]	PLL:DRP1B[0] PLL:PLL_CLKOUT0_LT[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[2] PLL:PLL_CLKOUT0_LT[2]	PLL:DRP1B[3] PLL:PLL_CLKOUT0_LT[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[5] PLL:PLL_CLKOUT0_LT[5]	PLL:DRP1B[4] PLL:PLL_CLKOUT0_LT[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[6] PLL:PLL_CLKOUT0_HT[0]	PLL:DRP1B[7] PLL:PLL_CLKOUT0_HT[1]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[9] PLL:PLL_CLKOUT0_HT[3]	PLL:DRP1B[8] PLL:PLL_CLKOUT0_HT[2]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[10] PLL:PLL_CLKOUT0_HT[4]	PLL:DRP1B[11] PLL:PLL_CLKOUT0_HT[5]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[13] PLL:PLL_CLKOUT0_PM[0]	PLL:DRP1B[12] PLL:PLL_CLKOUT0_EN
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1B[14] PLL:PLL_CLKOUT0_PM[1]	PLL:DRP1B[15] PLL:PLL_CLKOUT0_PM[2]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[1] PLL:PLL_CLKOUT0_DT[1]	PLL:DRP1C[0] PLL:PLL_CLKOUT0_DT[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[2] PLL:PLL_CLKOUT0_DT[2]	PLL:DRP1C[3] PLL:PLL_CLKOUT0_DT[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[5] PLL:PLL_CLKOUT0_DT[5]	PLL:DRP1C[4] PLL:PLL_CLKOUT0_DT[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[6] PLL:PLL_CLKOUT0_NOCOUNT	PLL:DRP1C[7] PLL:PLL_CLKOUT0_EDGE
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[9] PLL:PLL_CLK0MX[1]	PLL:DRP1C[8] PLL:PLL_CLK0MX[0]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1C[10]	PLL:CLKOUT0_DESKEW_ADJUST[0] PLL:DRP1C[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT0_DESKEW_ADJUST[2] PLL:DRP1C[13]	PLL:CLKOUT0_DESKEW_ADJUST[1] PLL:DRP1C[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:CLKOUT0_DESKEW_ADJUST[3] PLL:DRP1C[14]	PLL:CLKOUT0_DESKEW_ADJUST[4] PLL:DRP1C[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[1] PLL:INV.MANPDLF	PLL:DRP1D[0] PLL:INV.RST
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[2] PLL:INV.MANPULF	PLL:DRP1D[3] PLL:INV.REL
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[5] PLL:INV.ENOUTSYNC	PLL:DRP1D[4] PLL:INV.CLKBRST
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[6] ~PLL:PLL_CLKCNTRL	PLL:CLKINSEL_MODE PLL:DRP1D[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CMT:MUX.OUT10[0] PLL:DRP1D[9]	PLL:DRP1D[8] ~PLL:INV.CLKINSEL
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CMT:MUX.OUT10[1] PLL:DRP1D[10]	CMT:MUX.OUT10[2] PLL:DRP1D[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[13] PLL:INV.SKEWCLKIN2	PLL:DRP1D[12] PLL:INV.SKEWCLKIN1
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1D[14] PLL:INV.SKEWSTB	PLL:DRP1D[15] PLL:INV.SKEWRST
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[1] PLL:MUX.CLKIN[1]	PLL:DRP1E[0] PLL:MUX.CLKIN[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[2] PLL:MUX.CLKIN[2]	PLL:DRP1E[3] PLL:MUX.CLKIN[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[5] PLL:MUX.CLKFBIN[0]	PLL:CLKINSEL_STATIC PLL:DRP1E[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[6] PLL:MUX.CLKFBIN[1]	PLL:DRP1E[7] PLL:MUX.CLKFBIN[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[9] PLL:MUX.CLKFBIN[4]	PLL:DRP1E[8] PLL:MUX.CLKFBIN[3]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[10] PLL:MUX.CLK_TO_DCM0[2]	PLL:DRP1E[11] PLL:MUX.CLK_TO_DCM0[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[13] PLL:MUX.CLK_TO_DCM1[2]	PLL:DRP1E[12] PLL:MUX.CLK_TO_DCM0[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1E[14] PLL:MUX.CLK_TO_DCM1[0]	PLL:DRP1E[15] PLL:MUX.CLK_TO_DCM1[1]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[1] PLL:PLL_DVDD_VBG_SEL[1]	PLL:DRP1F[0] PLL:PLL_DVDD_VBG_SEL[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[2] PLL:PLL_DVDD_VBG_SEL[2]	PLL:DRP1F[3] PLL:PLL_DVDD_VBG_SEL[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[5] PLL:PLL_DVDD_VBG_PD[1]	PLL:DRP1F[4] PLL:PLL_DVDD_VBG_PD[0]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[6] PLL:PLL_DVDD_COMP_SET[0]	PLL:DRP1F[7] PLL:PLL_DVDD_COMP_SET[1]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[9] PLL:PLL_AVDD_VBG_SEL[1]	PLL:DRP1F[8] PLL:PLL_AVDD_VBG_SEL[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[10] PLL:PLL_AVDD_VBG_SEL[2]	PLL:DRP1F[11] PLL:PLL_AVDD_VBG_SEL[3]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[13] PLL:PLL_AVDD_VBG_PD[1]	PLL:DRP1F[12] PLL:PLL_AVDD_VBG_PD[0]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PLL:DRP1F[14] PLL:PLL_AVDD_COMP_SET[0]	PLL:DRP1F[15] PLL:PLL_AVDD_COMP_SET[1]

CMT bittile 7
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[1]	DCM1:DRP40[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[2]	DCM1:DRP40[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[5]	DCM1:DRP40[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[6]	DCM1:DRP40[7]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[9]	DCM1:DRP40[8]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[10]	DCM1:DRP40[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[13]	DCM1:DRP40[12]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP40[14]	DCM1:DRP40[15]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_OSCILLATOR_MODE DCM1:DRP41[1]	DCM1:DRP41[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_FREQUENCY_MODE DCM1:DRP41[2]	DCM1:DFS_CFG_BYPASS DCM1:DRP41[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_SYNTH_FAST_SYNCH[1] DCM1:DRP41[5]	DCM1:DFS_SYNTH_FAST_SYNCH[0] DCM1:DRP41[4]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_AVE_FREQ_GAIN[0] DCM1:DRP41[6]	DCM1:DFS_AVE_FREQ_GAIN[1] DCM1:DRP41[7]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_EARLY_LOCK DCM1:DRP41[9]	DCM1:DFS_AVE_FREQ_GAIN[2] DCM1:DRP41[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP41[10]	DCM1:DRP41[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP41[13]	DCM1:DRP41[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_HARDSYNC_B[0] DCM1:DRP41[14]	DCM1:DFS_HARDSYNC_B[1] DCM1:DRP41[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP42[1]	DCM1:DRP42[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP42[2]	DCM1:DFS_JF_LOWER_LIMIT[0] DCM1:DRP42[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_JF_LOWER_LIMIT[2] DCM1:DRP42[5]	DCM1:DFS_JF_LOWER_LIMIT[1] DCM1:DRP42[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_JF_LOWER_LIMIT[3] DCM1:DRP42[6]	DCM1:DFS_OSC_ON_FX DCM1:DRP42[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_HF_TRIM_CAL[0] DCM1:DRP42[9]	DCM1:DFS_REF_ON_FX DCM1:DRP42[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_HF_TRIM_CAL[1] DCM1:DRP42[10]	DCM1:DFS_HF_TRIM_CAL[2] DCM1:DRP42[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DFS_PWRD_REPLY_TIMES_OUT_B DCM1:DRP42[13]	DCM1:DRP42[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DFS_PWRD_CLKIN_STOP_STICKY_B DCM1:DRP42[14]	~DCM1:DFS_PWRD_CLKIN_STOP_B DCM1:DRP42[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_CLKIN_IODLY_MUXOUT_SEL DCM1:DRP43[1]	DCM1:DCM_CLKFB_IODLY_MUXOUT_SEL DCM1:DRP43[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP43[2]	DCM1:DESKEW_ADJUST[0] DCM1:DRP43[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DESKEW_ADJUST[2] DCM1:DRP43[5]	DCM1:DESKEW_ADJUST[1] DCM1:DRP43[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DESKEW_ADJUST[3] DCM1:DRP43[6]	DCM1:DESKEW_ADJUST[4] DCM1:DRP43[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_PLL_RST_DCM DCM1:DRP43[9]	DCM1:DRP43[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COM_PWC_REF_TAP[0] DCM1:DRP43[10]	DCM1:DCM_COM_PWC_REF_TAP[1] DCM1:DRP43[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COM_PWC_FB_TAP[0] DCM1:DRP43[13]	DCM1:DCM_COM_PWC_REF_TAP[2] DCM1:DRP43[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COM_PWC_FB_TAP[1] DCM1:DRP43[14]	DCM1:DCM_COM_PWC_FB_TAP[2] DCM1:DRP43[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COM_PWC_FB_EN DCM1:DRP44[1]	DCM1:DCM_COM_PWC_REF_EN DCM1:DRP44[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_EXT_FB_EN DCM1:DRP44[2]	DCM1:DCM_USE_REG_READY DCM1:DRP44[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_SYNTH_CLOCK_SPEED[1] DCM1:DRP44[5]	DCM1:DLL_SYNTH_CLOCK_SPEED[0] DCM1:DRP44[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_SYNTH_CLOCK_SPEED[0] DCM1:DRP44[6]	DCM1:DFS_SYNTH_CLOCK_SPEED[1] DCM1:DRP44[7]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_WAIT_PLL DCM1:DRP44[9]	DCM1:DFS_SYNTH_CLOCK_SPEED[2] DCM1:DRP44[8]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKIN_DIVIDE_BY_2 DCM1:DRP44[10]	DCM1:DCM_CLKIN_IODLY_MUXINSEL DCM1:DRP44[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_SYNC_TO_DLL DCM1:DRP44[13]	DCM1:DCM_CLKFB_IODLY_MUXINSEL DCM1:DRP44[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_EN DCM1:DRP44[14]	DCM1:DFS_FAST_UPDATE DCM1:DRP44[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[1] DCM1:DRP45[1]	DCM1:DFS_TAPTRIM[0] DCM1:DRP45[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[2] DCM1:DRP45[2]	DCM1:DFS_TAPTRIM[3] DCM1:DRP45[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[5] DCM1:DRP45[5]	DCM1:DFS_TAPTRIM[4] DCM1:DRP45[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[6] DCM1:DRP45[6]	DCM1:DFS_TAPTRIM[7] DCM1:DRP45[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[9] DCM1:DRP45[9]	DCM1:DFS_TAPTRIM[8] DCM1:DRP45[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TAPTRIM[10] DCM1:DRP45[10]	DCM1:DRP45[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP45[13]	DCM1:DRP45[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP45[14]	DCM1:DRP45[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TWEAK[1] DCM1:DRP46[1]	DCM1:DFS_TWEAK[0] DCM1:DRP46[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TWEAK[2] DCM1:DRP46[2]	DCM1:DFS_TWEAK[3] DCM1:DRP46[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TWEAK[5] DCM1:DRP46[5]	DCM1:DFS_TWEAK[4] DCM1:DRP46[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_TWEAK[6] DCM1:DRP46[6]	DCM1:DFS_TWEAK[7] DCM1:DRP46[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP46[9]	DCM1:DRP46[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP46[10]	DCM1:DRP46[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP46[13]	DCM1:DRP46[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP46[14]	DCM1:DRP46[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP47[1] DCM1:ENABLE.CLKFX180	DCM1:DRP47[0] DCM1:ENABLE.CLKFX
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP47[2] DCM1:ENABLE.CONCUR	DCM1:DFS_OUTPUT_PSDLY_ON_CONCUR DCM1:DRP47[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_UNUSED_TAPS_POWERDOWN[0] DCM1:DRP47[5]	~DCM1:DFS_EN_RELRST_B DCM1:DRP47[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_MPW_LOW DCM1:DRP47[6]	DCM1:DFS_MPW_HIGH DCM1:DRP47[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_CUSTOM_FAST_SYNC[0] DCM1:DRP47[9]	DCM1:DCM_CLKDV_CLKFX_ALIGNMENT DCM1:DRP47[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_CUSTOM_FAST_SYNC[1] DCM1:DRP47[10]	DCM1:DFS_CUSTOM_FAST_SYNC[2] DCM1:DRP47[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[0] DCM1:DRP47[13]	DCM1:DFS_CUSTOM_FAST_SYNC[3] DCM1:DRP47[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[1] DCM1:DRP47[14]	DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[2] DCM1:DRP47[15]

CMT bittile 8
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[1] DCM1:MUX.CLKIN[1]	DCM1:DRP48[0] DCM1:MUX.CLKIN[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[2] DCM1:MUX.CLKIN[2]	DCM1:DRP48[3] DCM1:MUX.CLKIN[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[5] DCM1:MUX.CLKFB[0]	DCM1:DRP48[4] DCM1:MUX.CLKIN[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[6] DCM1:MUX.CLKFB[1]	DCM1:DRP48[7] DCM1:MUX.CLKFB[2]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[9] DCM1:MUX.CLKFB[4]	DCM1:DRP48[8] DCM1:MUX.CLKFB[3]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[10] DCM1:MUX.CLK_TO_PLL[0]	DCM1:DRP48[11] DCM1:MUX.CLK_TO_PLL[1]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[13] DCM1:MUX.CLK_TO_PLL[3]	DCM1:DRP48[12] DCM1:MUX.CLK_TO_PLL[2]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP48[14] DCM1:INV.SKEWCLKIN1	DCM1:DRP48[15] DCM1:INV.SKEWCLKIN2
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[1] DCM1:MUX.SKEWCLKIN2[1]	DCM1:DRP49[0] DCM1:MUX.SKEWCLKIN2[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[2] DCM1:MUX.SKEWCLKIN2[2]	DCM1:DRP49[3] DCM1:MUX.SKEWCLKIN2[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[5] DCM1:INV.SKEWRST	DCM1:DRP49[4] DCM1:INV.SKEWIN
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKIN_CLKFB_ENABLE DCM1:DRP49[6]	DCM1:DRP49[7]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[9]	DCM1:DRP49[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[10]	DCM1:DRP49[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[13]	DCM1:DRP49[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP49[14]	DCM1:DCM_REG_PWRD_CFG DCM1:DRP49[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[1]	DCM1:DRP4A[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[2]	DCM1:DRP4A[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[5]	DCM1:DRP4A[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[6]	DCM1:DRP4A[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[9]	DCM1:DRP4A[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[10]	DCM1:DRP4A[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[13]	DCM1:DRP4A[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4A[14]	DCM1:DRP4A[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PHASE_SHIFT_CALIBRATION[1] DCM1:DRP4B[1]	DCM1:DLL_PHASE_SHIFT_CALIBRATION[0] DCM1:DRP4B[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[2] DCM1:PS_CENTERED	DCM1:DRP4B[3] DCM1:PS_DIRECT
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[5] DCM1:INV.RST	DCM1:DLL_PHASE_SHIFT_LOCK_BY1 DCM1:DRP4B[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[6] DCM1:INV.PSINCDEC	DCM1:DRP4B[7] DCM1:INV.PSEN
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[9]	DCM1:DRP4B[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[10]	DCM1:DRP4B[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[13]	DCM1:DRP4B[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4B[14]	DCM1:DRP4B[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_SCANMODE DCM1:DRP4C[1]	DCM1:DCM_UNUSED_TAPS_POWERDOWN[2] DCM1:DRP4C[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_TAPINIT_CTL[0] DCM1:DRP4C[2]	DCM1:DLL_TAPINIT_CTL[1] DCM1:DRP4C[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4C[5]	DCM1:DLL_TAPINIT_CTL[2] DCM1:DRP4C[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DLL_PWRD_ON_SCANMODE_B DCM1:DRP4C[6]	DCM1:DLL_ZD1_PHASE_SEL_INIT[0] DCM1:DRP4C[7]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PERIOD_LOCK_BY1 DCM1:DRP4C[9]	DCM1:DLL_ZD1_PHASE_SEL_INIT[1] DCM1:DRP4C[8]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_LOCK_BY1 DCM1:DRP4C[10]	DCM1:DLL_ZD2_JF_OVERFLOW_HOLD DCM1:DRP4C[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_JF_OVERFLOW_HOLD DCM1:DRP4C[13]	DCM1:DCM_UNUSED_TAPS_POWERDOWN[3] DCM1:DRP4C[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_UNUSED_TAPS_POWERDOWN[1] DCM1:DRP4C[14]	DCM1:DRP4C[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_TAP_INIT[1] DCM1:DRP4D[1]	DCM1:DLL_ZD2_TAP_INIT[0] DCM1:DRP4D[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_TAP_INIT[2] DCM1:DRP4D[2]	DCM1:DLL_ZD2_TAP_INIT[3] DCM1:DRP4D[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_TAP_INIT[5] DCM1:DRP4D[5]	DCM1:DLL_ZD2_TAP_INIT[4] DCM1:DRP4D[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_TAP_INIT[6] DCM1:DRP4D[6]	DCM1:DRP4D[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_TAP_INIT[1] DCM1:DRP4D[9]	DCM1:DLL_ZD1_TAP_INIT[0] DCM1:DRP4D[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_TAP_INIT[2] DCM1:DRP4D[10]	DCM1:DLL_ZD1_TAP_INIT[3] DCM1:DRP4D[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_TAP_INIT[5] DCM1:DRP4D[13]	DCM1:DLL_ZD1_TAP_INIT[4] DCM1:DRP4D[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_TAP_INIT[6] DCM1:DRP4D[14]	DCM1:DLL_ZD1_TAP_INIT[7] DCM1:DRP4D[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MINTAP[1] DCM1:DRP4E[1]	DCM1:DLL_DESKEW_MINTAP[0] DCM1:DRP4E[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MINTAP[2] DCM1:DRP4E[2]	DCM1:DLL_DESKEW_MINTAP[3] DCM1:DRP4E[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MINTAP[5] DCM1:DRP4E[5]	DCM1:DLL_DESKEW_MINTAP[4] DCM1:DRP4E[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MINTAP[6] DCM1:DRP4E[6]	DCM1:DLL_DESKEW_MINTAP[7] DCM1:DRP4E[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MAXTAP[1] DCM1:DRP4E[9]	DCM1:DLL_DESKEW_MAXTAP[0] DCM1:DRP4E[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MAXTAP[2] DCM1:DRP4E[10]	DCM1:DLL_DESKEW_MAXTAP[3] DCM1:DRP4E[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MAXTAP[5] DCM1:DRP4E[13]	DCM1:DLL_DESKEW_MAXTAP[4] DCM1:DRP4E[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DESKEW_MAXTAP[6] DCM1:DRP4E[14]	DCM1:DLL_DESKEW_MAXTAP[7] DCM1:DRP4E[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[1] DCM1:FACTORY_JF[1]	DCM1:DRP4F[0] DCM1:FACTORY_JF[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[2] DCM1:FACTORY_JF[2]	DCM1:DRP4F[3] DCM1:FACTORY_JF[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[5] DCM1:FACTORY_JF[5]	DCM1:DRP4F[4] DCM1:FACTORY_JF[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[6] DCM1:FACTORY_JF[6]	DCM1:DRP4F[7] DCM1:FACTORY_JF[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[9] DCM1:FACTORY_JF[9]	DCM1:DRP4F[8] DCM1:FACTORY_JF[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[10] DCM1:FACTORY_JF[10]	DCM1:DRP4F[11] DCM1:FACTORY_JF[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[13] DCM1:FACTORY_JF[13]	DCM1:DRP4F[12] DCM1:FACTORY_JF[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP4F[14] DCM1:FACTORY_JF[14]	DCM1:DRP4F[15] DCM1:FACTORY_JF[15]

CMT bittile 9
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_DIVIDE[1] DCM1:DRP50[1]	DCM1:CLKFX_DIVIDE[0] DCM1:DRP50[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_DIVIDE[2] DCM1:DRP50[2]	DCM1:CLKFX_DIVIDE[3] DCM1:DRP50[3]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_DIVIDE[5] DCM1:DRP50[5]	DCM1:CLKFX_DIVIDE[4] DCM1:DRP50[4]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_DIVIDE[6] DCM1:DRP50[6]	DCM1:CLKFX_DIVIDE[7] DCM1:DRP50[7]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_MULTIPLY[1] DCM1:DRP50[9]	DCM1:CLKFX_MULTIPLY[0] DCM1:DRP50[8]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_MULTIPLY[2] DCM1:DRP50[10]	DCM1:CLKFX_MULTIPLY[3] DCM1:DRP50[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_MULTIPLY[5] DCM1:DRP50[13]	DCM1:CLKFX_MULTIPLY[4] DCM1:DRP50[12]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKFX_MULTIPLY[6] DCM1:DRP50[14]	DCM1:CLKFX_MULTIPLY[7] DCM1:DRP50[15]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DLL_CLKIN_STOPPED_PWRD_EN_B DCM1:DRP51[1]	~DCM1:DLL_CLKFB_STOPPED_PWRD_EN_B DCM1:DRP51[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_FREQUENCY_MODE[0] DCM1:DRP51[2]	DCM1:DLL_FREQUENCY_MODE[1] DCM1:DRP51[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_EN DCM1:DRP51[5]	DCM1:DRP51[4] DCM1:PS_MODE
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_EN DCM1:DRP51[6]	DCM1:DRP51[7] DCM1:PS_ENABLE
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_SETTLE_TIME[1] DCM1:DRP51[9]	DCM1:DLL_SETTLE_TIME[0] DCM1:DRP51[8]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_SETTLE_TIME[2] DCM1:DRP51[10]	DCM1:DLL_SETTLE_TIME[3] DCM1:DRP51[11]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_SETTLE_TIME[5] DCM1:DRP51[13]	DCM1:DLL_SETTLE_TIME[4] DCM1:DRP51[12]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_SETTLE_TIME[6] DCM1:DRP51[14]	DCM1:DLL_SETTLE_TIME[7] DCM1:DRP51[15]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_LIVE_TIME[1] DCM1:DRP52[1]	DCM1:DLL_LIVE_TIME[0] DCM1:DRP52[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_LIVE_TIME[2] DCM1:DRP52[2]	DCM1:DLL_LIVE_TIME[3] DCM1:DRP52[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_LIVE_TIME[5] DCM1:DRP52[5]	DCM1:DLL_LIVE_TIME[4] DCM1:DRP52[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_LIVE_TIME[6] DCM1:DRP52[6]	DCM1:DLL_LIVE_TIME[7] DCM1:DRP52[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DEAD_TIME[1] DCM1:DRP52[9]	DCM1:DLL_DEAD_TIME[0] DCM1:DRP52[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DEAD_TIME[2] DCM1:DRP52[10]	DCM1:DLL_DEAD_TIME[3] DCM1:DRP52[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DEAD_TIME[5] DCM1:DRP52[13]	DCM1:DLL_DEAD_TIME[4] DCM1:DRP52[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_DEAD_TIME[6] DCM1:DRP52[14]	DCM1:DLL_DEAD_TIME[7] DCM1:DRP52[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_MAX[1] DCM1:DRP53[1]	DCM1:CLKDV_COUNT_MAX[0] DCM1:DRP53[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_MAX[2] DCM1:DRP53[2]	DCM1:CLKDV_COUNT_MAX[3] DCM1:DRP53[3]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_FALL[1] DCM1:DRP53[5]	DCM1:CLKDV_COUNT_FALL[0] DCM1:DRP53[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_FALL[2] DCM1:DRP53[6]	DCM1:CLKDV_COUNT_FALL[3] DCM1:DRP53[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_FALL_2[1] DCM1:DRP53[9]	DCM1:CLKDV_COUNT_FALL_2[0] DCM1:DRP53[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_COUNT_FALL_2[2] DCM1:DRP53[10]	DCM1:CLKDV_COUNT_FALL_2[3] DCM1:DRP53[11]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_PHASE_RISE[1] DCM1:DRP53[13]	DCM1:CLKDV_PHASE_RISE[0] DCM1:DRP53[12]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:CLKDV_PHASE_FALL[0] DCM1:DRP53[14]	DCM1:CLKDV_PHASE_FALL[1] DCM1:DRP53[15]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_FDBKLOST_EN DCM1:DRP54[1]	DCM1:CLKDV_MODE DCM1:DRP54[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_CLKLOST_EN DCM1:DRP54[2]	~DCM1:DCM_LOCK_HIGH_B DCM1:DRP54[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP54[5] DCM1:ENABLE.CLK90	DCM1:DRP54[4] DCM1:ENABLE.CLK0
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP54[6] DCM1:ENABLE.CLK180	DCM1:DRP54[7] DCM1:ENABLE.CLK270
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP54[9] DCM1:ENABLE.CLK2X180	DCM1:DRP54[8] DCM1:ENABLE.CLK2X
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP54[10] DCM1:ENABLE.CLKDV	DCM1:DCM_TRIM_CAL[0] DCM1:DRP54[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_TRIM_CAL[2] DCM1:DRP54[13]	DCM1:DCM_TRIM_CAL[1] DCM1:DRP54[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_TEST_MUX_SEL[0] DCM1:DRP54[14]	DCM1:DLL_TEST_MUX_SEL[1] DCM1:DRP54[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[1] DCM1:PHASE_SHIFT[1]	DCM1:DRP55[0] DCM1:PHASE_SHIFT[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[2] DCM1:PHASE_SHIFT[2]	DCM1:DRP55[3] DCM1:PHASE_SHIFT[3]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[5] DCM1:PHASE_SHIFT[5]	DCM1:DRP55[4] DCM1:PHASE_SHIFT[4]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[6] DCM1:PHASE_SHIFT[6]	DCM1:DRP55[7] DCM1:PHASE_SHIFT[7]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[9] DCM1:PHASE_SHIFT[9]	DCM1:DRP55[8] DCM1:PHASE_SHIFT[8]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[10] DCM1:PHASE_SHIFT_NEGATIVE	DCM1:DRP55[11]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[13]	DCM1:DRP55[12]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP55[14]	DCM1:DRP55[15]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PHASE_SHIFT_LFC[1] DCM1:DRP56[1]	DCM1:DLL_PHASE_SHIFT_LFC[0] DCM1:DRP56[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PHASE_SHIFT_LFC[2] DCM1:DRP56[2]	DCM1:DLL_PHASE_SHIFT_LFC[3] DCM1:DRP56[3]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PHASE_SHIFT_LFC[5] DCM1:DRP56[5]	DCM1:DLL_PHASE_SHIFT_LFC[4] DCM1:DRP56[4]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_PHASE_SHIFT_LFC[6] DCM1:DRP56[6]	DCM1:DLL_PHASE_SHIFT_LFC[7] DCM1:DRP56[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_PWC_TAP[0] DCM1:DRP56[9]	DCM1:DLL_PHASE_SHIFT_LFC[8] DCM1:DRP56[8]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_PWC_TAP[1] DCM1:DRP56[10]	DCM1:DLL_ZD2_PWC_TAP[2] DCM1:DRP56[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_PWC_TAP[1] DCM1:DRP56[13]	DCM1:DLL_ZD1_PWC_TAP[0] DCM1:DRP56[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_PWC_TAP[2] DCM1:DRP56[14]	DCM1:DCM_VREG_ENABLE DCM1:DRP56[15]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD1_PWC_EN DCM1:DRP57[1]	DCM1:DCM_VSPLY_VALID_ACC[0] DCM1:DRP57[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DRP57[2] DCM1:STARTUP_WAIT	DCM1:DCM_VBG_SEL[0] DCM1:DRP57[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ETPP_HOLD DCM1:DRP57[5]	DCM1:DCM_VBG_SEL[1] DCM1:DRP57[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DLL_PWRD_STICKY_B DCM1:DRP57[6]	DCM1:DCM_VBG_SEL[2] DCM1:DRP57[7]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DLL_ZD2_PWC_EN DCM1:DRP57[9]	DCM1:DCM_VBG_SEL[3] DCM1:DRP57[8]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~DCM1:DCM_POWERDOWN_COMMON_EN_B DCM1:DRP57[10]	DCM1:DCM_VBG_PD[0] DCM1:DRP57[11]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COMMON_MSB_SEL[0] DCM1:DRP57[13]	DCM1:DCM_VBG_PD[1] DCM1:DRP57[12]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	DCM1:DCM_COMMON_MSB_SEL[1] DCM1:DRP57[14]	DCM1:DCM_VSPLY_VALID_ACC[1] DCM1:DRP57[15]

DCM0:DFS_OSCILLATOR_MODE	[0, 28, 8]
DCM1:DFS_OSCILLATOR_MODE	[7, 28, 8]
PHASE_FREQ_LOCK	0
AVE_FREQ_LOCK	1

DCM0:DFS_FREQUENCY_MODE	[0, 28, 9]
DCM1:DFS_FREQUENCY_MODE	[7, 28, 9]
LOW	0
HIGH	1

DCM0:DFS_AVE_FREQ_GAIN	[0, 29, 12]	[0, 29, 11]	[0, 28, 11]
DCM1:DFS_AVE_FREQ_GAIN	[7, 29, 12]	[7, 29, 11]	[7, 28, 11]
0.125	0	0	1
0.25	0	1	0
0.5	0	1	1
1.0	1	0	0
2.0	1	0	1
4.0	1	1	0
8.0	1	1	1

DCM0:CLKIN_CLKFB_ENABLE	[1, 28, 11]
DCM0:CLKIN_DIVIDE_BY_2	[0, 28, 37]
DCM0:DCM_CLKDV_CLKFX_ALIGNMENT	[0, 29, 60]
DCM0:DCM_CLKLOST_EN	[2, 28, 33]
DCM0:DCM_COM_PWC_FB_EN	[0, 28, 32]
DCM0:DCM_COM_PWC_REF_EN	[0, 29, 32]
DCM0:DCM_EXT_FB_EN	[0, 28, 33]
DCM0:DCM_PLL_RST_DCM	[0, 28, 28]
DCM0:DCM_REG_PWRD_CFG	[1, 29, 15]
DCM0:DCM_SCANMODE	[1, 28, 32]
DCM0:DCM_USE_REG_READY	[0, 29, 33]
DCM0:DCM_VREG_ENABLE	[2, 29, 55]
DCM0:DCM_WAIT_PLL	[0, 28, 36]
DCM0:DFS_CFG_BYPASS	[0, 29, 9]
DCM0:DFS_EARLY_LOCK	[0, 28, 12]
DCM0:DFS_EN	[0, 28, 39]
DCM0:DFS_FAST_UPDATE	[0, 29, 39]
DCM0:DFS_MPW_HIGH	[0, 29, 59]
DCM0:DFS_MPW_LOW	[0, 28, 59]
DCM0:DFS_OSC_ON_FX	[0, 29, 19]
DCM0:DFS_OUTPUT_PSDLY_ON_CONCUR	[0, 29, 57]
DCM0:DFS_REF_ON_FX	[0, 29, 20]
DCM0:DFS_SYNC_TO_DLL	[0, 28, 38]
DCM0:DLL_DESKEW_LOCK_BY1	[1, 28, 37]
DCM0:DLL_ETPP_HOLD	[2, 28, 58]
DCM0:DLL_FDBKLOST_EN	[2, 28, 32]
DCM0:DLL_PERIOD_LOCK_BY1	[1, 28, 36]
DCM0:DLL_PHASE_SHIFT_LOCK_BY1	[1, 29, 26]
DCM0:DLL_ZD1_EN	[2, 28, 11]
DCM0:DLL_ZD1_JF_OVERFLOW_HOLD	[1, 28, 38]
DCM0:DLL_ZD1_PWC_EN	[2, 28, 56]
DCM0:DLL_ZD2_EN	[2, 28, 10]
DCM0:DLL_ZD2_JF_OVERFLOW_HOLD	[1, 29, 37]
DCM0:DLL_ZD2_PWC_EN	[2, 28, 60]
DCM0:ENABLE.CLK0	[2, 29, 34]
DCM0:ENABLE.CLK180	[2, 28, 35]
DCM0:ENABLE.CLK270	[2, 29, 35]
DCM0:ENABLE.CLK2X	[2, 29, 36]
DCM0:ENABLE.CLK2X180	[2, 28, 36]
DCM0:ENABLE.CLK90	[2, 28, 34]
DCM0:ENABLE.CLKDV	[2, 28, 37]
DCM0:ENABLE.CLKFX	[0, 29, 56]
DCM0:ENABLE.CLKFX180	[0, 28, 56]
DCM0:ENABLE.CONCUR	[0, 28, 57]
DCM0:INV.PSEN	[1, 29, 27]
DCM0:INV.PSINCDEC	[1, 28, 27]
DCM0:INV.RST	[1, 28, 26]
DCM0:INV.SKEWCLKIN1	[1, 28, 7]
DCM0:INV.SKEWCLKIN2	[1, 29, 7]
DCM0:INV.SKEWIN	[1, 29, 10]
DCM0:INV.SKEWRST	[1, 28, 10]
DCM0:PHASE_SHIFT_NEGATIVE	[2, 28, 45]
DCM0:PS_CENTERED	[1, 28, 25]
DCM0:PS_DIRECT	[1, 29, 25]
DCM0:PS_ENABLE	[2, 29, 11]
DCM0:STARTUP_WAIT	[2, 28, 57]
DCM1:CLKIN_CLKFB_ENABLE	[8, 28, 11]
DCM1:CLKIN_DIVIDE_BY_2	[7, 28, 37]
DCM1:DCM_CLKDV_CLKFX_ALIGNMENT	[7, 29, 60]
DCM1:DCM_CLKLOST_EN	[9, 28, 33]
DCM1:DCM_COM_PWC_FB_EN	[7, 28, 32]
DCM1:DCM_COM_PWC_REF_EN	[7, 29, 32]
DCM1:DCM_EXT_FB_EN	[7, 28, 33]
DCM1:DCM_PLL_RST_DCM	[7, 28, 28]
DCM1:DCM_REG_PWRD_CFG	[8, 29, 15]
DCM1:DCM_SCANMODE	[8, 28, 32]
DCM1:DCM_USE_REG_READY	[7, 29, 33]
DCM1:DCM_VREG_ENABLE	[9, 29, 55]
DCM1:DCM_WAIT_PLL	[7, 28, 36]
DCM1:DFS_CFG_BYPASS	[7, 29, 9]
DCM1:DFS_EARLY_LOCK	[7, 28, 12]
DCM1:DFS_EN	[7, 28, 39]
DCM1:DFS_FAST_UPDATE	[7, 29, 39]
DCM1:DFS_MPW_HIGH	[7, 29, 59]
DCM1:DFS_MPW_LOW	[7, 28, 59]
DCM1:DFS_OSC_ON_FX	[7, 29, 19]
DCM1:DFS_OUTPUT_PSDLY_ON_CONCUR	[7, 29, 57]
DCM1:DFS_REF_ON_FX	[7, 29, 20]
DCM1:DFS_SYNC_TO_DLL	[7, 28, 38]
DCM1:DLL_DESKEW_LOCK_BY1	[8, 28, 37]
DCM1:DLL_ETPP_HOLD	[9, 28, 58]
DCM1:DLL_FDBKLOST_EN	[9, 28, 32]
DCM1:DLL_PERIOD_LOCK_BY1	[8, 28, 36]
DCM1:DLL_PHASE_SHIFT_LOCK_BY1	[8, 29, 26]
DCM1:DLL_ZD1_EN	[9, 28, 11]
DCM1:DLL_ZD1_JF_OVERFLOW_HOLD	[8, 28, 38]
DCM1:DLL_ZD1_PWC_EN	[9, 28, 56]
DCM1:DLL_ZD2_EN	[9, 28, 10]
DCM1:DLL_ZD2_JF_OVERFLOW_HOLD	[8, 29, 37]
DCM1:DLL_ZD2_PWC_EN	[9, 28, 60]
DCM1:ENABLE.CLK0	[9, 29, 34]
DCM1:ENABLE.CLK180	[9, 28, 35]
DCM1:ENABLE.CLK270	[9, 29, 35]
DCM1:ENABLE.CLK2X	[9, 29, 36]
DCM1:ENABLE.CLK2X180	[9, 28, 36]
DCM1:ENABLE.CLK90	[9, 28, 34]
DCM1:ENABLE.CLKDV	[9, 28, 37]
DCM1:ENABLE.CLKFX	[7, 29, 56]
DCM1:ENABLE.CLKFX180	[7, 28, 56]
DCM1:ENABLE.CONCUR	[7, 28, 57]
DCM1:INV.PSEN	[8, 29, 27]
DCM1:INV.PSINCDEC	[8, 28, 27]
DCM1:INV.RST	[8, 28, 26]
DCM1:INV.SKEWCLKIN1	[8, 28, 7]
DCM1:INV.SKEWCLKIN2	[8, 29, 7]
DCM1:INV.SKEWIN	[8, 29, 10]
DCM1:INV.SKEWRST	[8, 28, 10]
DCM1:PHASE_SHIFT_NEGATIVE	[9, 28, 45]
DCM1:PS_CENTERED	[8, 28, 25]
DCM1:PS_DIRECT	[8, 29, 25]
DCM1:PS_ENABLE	[9, 29, 11]
DCM1:STARTUP_WAIT	[9, 28, 57]
PLL:CLKINSEL_STATIC	[6, 29, 50]
PLL:INV.CLKBRST	[6, 29, 42]
PLL:INV.ENOUTSYNC	[6, 28, 42]
PLL:INV.MANPDLF	[6, 28, 40]
PLL:INV.MANPULF	[6, 28, 41]
PLL:INV.REL	[6, 29, 41]
PLL:INV.RST	[6, 29, 40]
PLL:INV.SKEWCLKIN1	[6, 29, 46]
PLL:INV.SKEWCLKIN2	[6, 28, 46]
PLL:INV.SKEWRST	[6, 29, 47]
PLL:INV.SKEWSTB	[6, 28, 47]
PLL:PLL_CLKBURST_ENABLE	[6, 29, 6]
PLL:PLL_CLKFBOUT2_EDGE	[4, 29, 19]
PLL:PLL_CLKFBOUT2_NOCOUNT	[4, 28, 19]
PLL:PLL_CLKFBOUT_EDGE	[4, 29, 43]
PLL:PLL_CLKFBOUT_EN	[4, 29, 38]
PLL:PLL_CLKFBOUT_NOCOUNT	[4, 28, 43]
PLL:PLL_CLKOUT0_EDGE	[6, 29, 35]
PLL:PLL_CLKOUT0_EN	[6, 29, 30]
PLL:PLL_CLKOUT0_NOCOUNT	[6, 28, 35]
PLL:PLL_CLKOUT1_EDGE	[6, 29, 19]
PLL:PLL_CLKOUT1_EN	[6, 29, 14]
PLL:PLL_CLKOUT1_NOCOUNT	[6, 28, 19]
PLL:PLL_CLKOUT2_EDGE	[5, 29, 59]
PLL:PLL_CLKOUT2_EN	[5, 29, 54]
PLL:PLL_CLKOUT2_NOCOUNT	[5, 28, 59]
PLL:PLL_CLKOUT3_EDGE	[5, 29, 43]
PLL:PLL_CLKOUT3_EN	[5, 29, 38]
PLL:PLL_CLKOUT3_NOCOUNT	[5, 28, 43]
PLL:PLL_CLKOUT4_EDGE	[5, 29, 27]
PLL:PLL_CLKOUT4_EN	[5, 29, 22]
PLL:PLL_CLKOUT4_NOCOUNT	[5, 28, 27]
PLL:PLL_CLKOUT5_EDGE	[4, 29, 59]
PLL:PLL_CLKOUT5_EN	[4, 29, 54]
PLL:PLL_CLKOUT5_NOCOUNT	[4, 28, 59]
PLL:PLL_CP_BIAS_TRIP_SHIFT	[3, 28, 7]
PLL:PLL_DIRECT_PATH_CNTRL	[6, 29, 0]
PLL:PLL_DIVCLK_EDGE	[3, 28, 54]
PLL:PLL_DIVCLK_NOCOUNT	[3, 29, 54]
PLL:PLL_EN	[5, 29, 15]
PLL:PLL_EN_DLY	[3, 28, 60]
PLL:PLL_EN_TCLK0	[3, 28, 37]
PLL:PLL_EN_TCLK1	[3, 29, 37]
PLL:PLL_EN_TCLK2	[3, 29, 38]
PLL:PLL_EN_TCLK3	[3, 28, 38]
PLL:PLL_EN_TCLK4	[3, 28, 39]
PLL:PLL_EN_VCO0	[6, 29, 1]
PLL:PLL_EN_VCO1	[6, 29, 2]
PLL:PLL_EN_VCO2	[6, 28, 2]
PLL:PLL_EN_VCO3	[6, 28, 3]
PLL:PLL_EN_VCO4	[6, 29, 3]
PLL:PLL_EN_VCO5	[6, 29, 4]
PLL:PLL_EN_VCO6	[6, 28, 4]
PLL:PLL_EN_VCO7	[6, 28, 5]
PLL:PLL_EN_VCO_DIV1	[6, 28, 0]
PLL:PLL_EN_VCO_DIV6	[6, 28, 1]
PLL:PLL_INC_FLOCK	[3, 29, 29]
PLL:PLL_INC_SLOCK	[3, 28, 29]
PLL:PLL_LOCK_CNT_RST_FAST	[3, 29, 32]
PLL:PLL_MAN_LF_EN	[3, 29, 0]
PLL:PLL_NBTI_EN	[4, 28, 45]
PLL:PLL_PMCD_MODE	[5, 28, 15]
PLL:PLL_PWRD_CFG	[3, 29, 15]
PLL:PLL_SEL_SLIPD	[3, 29, 7]
PLL:PLL_UNLOCK_CNT_RST_FAST	[3, 28, 32]
PLL:PLL_VLFHIGH_DIS	[3, 28, 2]
Non-inverted	[0]

DCM0:CLKDV_PHASE_FALL	[2, 29, 31]	[2, 28, 31]
DCM0:CLKDV_PHASE_RISE	[2, 28, 30]	[2, 29, 30]
DCM0:DCM_COMMON_MSB_SEL	[2, 28, 63]	[2, 28, 62]
DCM0:DCM_VBG_PD	[2, 29, 62]	[2, 29, 61]
DCM0:DCM_VSPLY_VALID_ACC	[2, 29, 63]	[2, 29, 56]
DCM0:DFS_HARDSYNC_B	[0, 29, 15]	[0, 28, 15]
DCM0:DFS_SYNTH_FAST_SYNCH	[0, 28, 10]	[0, 29, 10]
DCM0:DLL_TEST_MUX_SEL	[2, 29, 39]	[2, 28, 39]
DCM0:DLL_ZD1_PHASE_SEL_INIT	[1, 29, 36]	[1, 29, 35]
DCM1:CLKDV_PHASE_FALL	[9, 29, 31]	[9, 28, 31]
DCM1:CLKDV_PHASE_RISE	[9, 28, 30]	[9, 29, 30]
DCM1:DCM_COMMON_MSB_SEL	[9, 28, 63]	[9, 28, 62]
DCM1:DCM_VBG_PD	[9, 29, 62]	[9, 29, 61]
DCM1:DCM_VSPLY_VALID_ACC	[9, 29, 63]	[9, 29, 56]
DCM1:DFS_HARDSYNC_B	[7, 29, 15]	[7, 28, 15]
DCM1:DFS_SYNTH_FAST_SYNCH	[7, 28, 10]	[7, 29, 10]
DCM1:DLL_TEST_MUX_SEL	[9, 29, 39]	[9, 28, 39]
DCM1:DLL_ZD1_PHASE_SEL_INIT	[8, 29, 36]	[8, 29, 35]
PLL:PLL_AVDD_COMP_SET	[6, 29, 63]	[6, 28, 63]
PLL:PLL_AVDD_VBG_PD	[6, 28, 62]	[6, 29, 62]
PLL:PLL_CLK0MX	[6, 28, 36]	[6, 29, 36]
PLL:PLL_CLK1MX	[6, 28, 20]	[6, 29, 20]
PLL:PLL_CLK2MX	[5, 28, 60]	[5, 29, 60]
PLL:PLL_CLK3MX	[5, 28, 44]	[5, 29, 44]
PLL:PLL_CLK4MX	[5, 28, 28]	[5, 29, 28]
PLL:PLL_CLK5MX	[4, 28, 60]	[4, 29, 60]
PLL:PLL_CLKFBMX	[4, 28, 44]	[4, 29, 44]
PLL:PLL_CP_RES	[3, 28, 10]	[3, 29, 10]
PLL:PLL_DVDD_COMP_SET	[6, 29, 59]	[6, 28, 59]
PLL:PLL_DVDD_VBG_PD	[6, 28, 58]	[6, 29, 58]
PLL:PLL_INTFB	[3, 28, 36]	[3, 29, 36]
PLL:PLL_LFHF	[3, 29, 11]	[3, 28, 11]
PLL:PLL_LF_NEN	[3, 29, 2]	[3, 29, 1]
PLL:PLL_LF_PEN	[3, 28, 1]	[3, 28, 0]
PLL:PLL_PFD_DLY	[3, 28, 12]	[3, 29, 12]
Non-inverted	[1]	[0]

DCM0:DCM_COM_PWC_FB_TAP	[0, 29, 31]	[0, 28, 31]	[0, 28, 30]
DCM0:DCM_COM_PWC_REF_TAP	[0, 29, 30]	[0, 29, 29]	[0, 28, 29]
DCM0:DCM_TRIM_CAL	[2, 28, 38]	[2, 29, 38]	[2, 29, 37]
DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL	[0, 29, 63]	[0, 28, 63]	[0, 28, 62]
DCM0:DFS_HF_TRIM_CAL	[0, 29, 21]	[0, 28, 21]	[0, 28, 20]
DCM0:DFS_SYNTH_CLOCK_SPEED	[0, 29, 36]	[0, 29, 35]	[0, 28, 35]
DCM0:DLL_TAPINIT_CTL	[1, 29, 34]	[1, 29, 33]	[1, 28, 33]
DCM0:DLL_ZD1_PWC_TAP	[2, 28, 55]	[2, 28, 54]	[2, 29, 54]
DCM0:DLL_ZD2_PWC_TAP	[2, 29, 53]	[2, 28, 53]	[2, 28, 52]
DCM1:DCM_COM_PWC_FB_TAP	[7, 29, 31]	[7, 28, 31]	[7, 28, 30]
DCM1:DCM_COM_PWC_REF_TAP	[7, 29, 30]	[7, 29, 29]	[7, 28, 29]
DCM1:DCM_TRIM_CAL	[9, 28, 38]	[9, 29, 38]	[9, 29, 37]
DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL	[7, 29, 63]	[7, 28, 63]	[7, 28, 62]
DCM1:DFS_HF_TRIM_CAL	[7, 29, 21]	[7, 28, 21]	[7, 28, 20]
DCM1:DFS_SYNTH_CLOCK_SPEED	[7, 29, 36]	[7, 29, 35]	[7, 28, 35]
DCM1:DLL_TAPINIT_CTL	[8, 29, 34]	[8, 29, 33]	[8, 28, 33]
DCM1:DLL_ZD1_PWC_TAP	[9, 28, 55]	[9, 28, 54]	[9, 29, 54]
DCM1:DLL_ZD2_PWC_TAP	[9, 29, 53]	[9, 28, 53]	[9, 28, 52]
PLL:PLL_CLKBURST_CNT	[6, 29, 7]	[6, 28, 7]	[6, 28, 6]
PLL:PLL_CLKFBOUT_PM	[4, 29, 39]	[4, 28, 39]	[4, 28, 38]
PLL:PLL_CLKOUT0_PM	[6, 29, 31]	[6, 28, 31]	[6, 28, 30]
PLL:PLL_CLKOUT1_PM	[6, 29, 15]	[6, 28, 15]	[6, 28, 14]
PLL:PLL_CLKOUT2_PM	[5, 29, 55]	[5, 28, 55]	[5, 28, 54]
PLL:PLL_CLKOUT3_PM	[5, 29, 39]	[5, 28, 39]	[5, 28, 38]
PLL:PLL_CLKOUT4_PM	[5, 29, 23]	[5, 28, 23]	[5, 28, 22]
PLL:PLL_CLKOUT5_PM	[4, 29, 55]	[4, 28, 55]	[4, 28, 54]
Non-inverted	[2]	[1]	[0]

DCM0:DCM_LOCK_HIGH_B	[2, 29, 33]
DCM0:DCM_POWERDOWN_COMMON_EN_B	[2, 28, 61]
DCM0:DFS_EN_RELRST_B	[0, 29, 58]
DCM0:DFS_PWRD_CLKIN_STOP_B	[0, 29, 23]
DCM0:DFS_PWRD_CLKIN_STOP_STICKY_B	[0, 28, 23]
DCM0:DFS_PWRD_REPLY_TIMES_OUT_B	[0, 28, 22]
DCM0:DLL_CLKFB_STOPPED_PWRD_EN_B	[2, 29, 8]
DCM0:DLL_CLKIN_STOPPED_PWRD_EN_B	[2, 28, 8]
DCM0:DLL_PWRD_ON_SCANMODE_B	[1, 28, 35]
DCM0:DLL_PWRD_STICKY_B	[2, 28, 59]
DCM1:DCM_LOCK_HIGH_B	[9, 29, 33]
DCM1:DCM_POWERDOWN_COMMON_EN_B	[9, 28, 61]
DCM1:DFS_EN_RELRST_B	[7, 29, 58]
DCM1:DFS_PWRD_CLKIN_STOP_B	[7, 29, 23]
DCM1:DFS_PWRD_CLKIN_STOP_STICKY_B	[7, 28, 23]
DCM1:DFS_PWRD_REPLY_TIMES_OUT_B	[7, 28, 22]
DCM1:DLL_CLKFB_STOPPED_PWRD_EN_B	[9, 29, 8]
DCM1:DLL_CLKIN_STOPPED_PWRD_EN_B	[9, 28, 8]
DCM1:DLL_PWRD_ON_SCANMODE_B	[8, 28, 35]
DCM1:DLL_PWRD_STICKY_B	[9, 28, 59]
PLL:INV.CLKINSEL	[6, 29, 44]
PLL:PLL_CLKCNTRL	[6, 28, 43]
PLL:PLL_TCK4_SEL	[3, 29, 39]
Inverted	~[0]

DCM0:DCM_CLKFB_IODLY_MUXINSEL	[0, 29, 38]
DCM0:DCM_CLKFB_IODLY_MUXOUT_SEL	[0, 29, 24]
DCM0:DCM_CLKIN_IODLY_MUXINSEL	[0, 29, 37]
DCM0:DCM_CLKIN_IODLY_MUXOUT_SEL	[0, 28, 24]
DCM1:DCM_CLKFB_IODLY_MUXINSEL	[7, 29, 38]
DCM1:DCM_CLKFB_IODLY_MUXOUT_SEL	[7, 29, 24]
DCM1:DCM_CLKIN_IODLY_MUXINSEL	[7, 29, 37]
DCM1:DCM_CLKIN_IODLY_MUXOUT_SEL	[7, 28, 24]
PASS	0
DELAY_LINE	1

DCM0:CLKDV_COUNT_FALL	[2, 29, 27]	[2, 28, 27]	[2, 28, 26]	[2, 29, 26]
DCM0:CLKDV_COUNT_FALL_2	[2, 29, 29]	[2, 28, 29]	[2, 28, 28]	[2, 29, 28]
DCM0:CLKDV_COUNT_MAX	[2, 29, 25]	[2, 28, 25]	[2, 28, 24]	[2, 29, 24]
DCM0:DCM_UNUSED_TAPS_POWERDOWN	[1, 29, 38]	[1, 29, 32]	[1, 28, 39]	[0, 28, 58]
DCM0:DCM_VBG_SEL	[2, 29, 60]	[2, 29, 59]	[2, 29, 58]	[2, 29, 57]
DCM0:DFS_CUSTOM_FAST_SYNC	[0, 29, 62]	[0, 29, 61]	[0, 28, 61]	[0, 28, 60]
DCM0:DFS_JF_LOWER_LIMIT	[0, 28, 19]	[0, 28, 18]	[0, 29, 18]	[0, 29, 17]
DCM1:CLKDV_COUNT_FALL	[9, 29, 27]	[9, 28, 27]	[9, 28, 26]	[9, 29, 26]
DCM1:CLKDV_COUNT_FALL_2	[9, 29, 29]	[9, 28, 29]	[9, 28, 28]	[9, 29, 28]
DCM1:CLKDV_COUNT_MAX	[9, 29, 25]	[9, 28, 25]	[9, 28, 24]	[9, 29, 24]
DCM1:DCM_UNUSED_TAPS_POWERDOWN	[8, 29, 38]	[8, 29, 32]	[8, 28, 39]	[7, 28, 58]
DCM1:DCM_VBG_SEL	[9, 29, 60]	[9, 29, 59]	[9, 29, 58]	[9, 29, 57]
DCM1:DFS_CUSTOM_FAST_SYNC	[7, 29, 62]	[7, 29, 61]	[7, 28, 61]	[7, 28, 60]
DCM1:DFS_JF_LOWER_LIMIT	[7, 28, 19]	[7, 28, 18]	[7, 29, 18]	[7, 29, 17]
PLL:PLL_AVDD_VBG_SEL	[6, 29, 61]	[6, 28, 61]	[6, 28, 60]	[6, 29, 60]
PLL:PLL_CP	[3, 29, 9]	[3, 28, 9]	[3, 28, 8]	[3, 29, 8]
PLL:PLL_DVDD_VBG_SEL	[6, 29, 57]	[6, 28, 57]	[6, 28, 56]	[6, 29, 56]
PLL:PLL_MISC	[3, 28, 6]	[3, 29, 6]	[3, 29, 5]	[3, 28, 5]
PLL:PLL_PFD_CNTRL	[3, 28, 14]	[3, 29, 14]	[3, 29, 13]	[3, 28, 13]
PLL:PLL_RES	[3, 28, 4]	[3, 29, 4]	[3, 29, 3]	[3, 28, 3]
PLL:PLL_UNLOCK_CNT	[3, 29, 31]	[3, 28, 31]	[3, 28, 30]	[3, 29, 30]
Non-inverted	[3]	[2]	[1]	[0]

DCM0:DRP40	[0, 29, 7]	[0, 28, 7]	[0, 28, 6]	[0, 29, 6]	[0, 29, 5]	[0, 28, 5]	[0, 28, 4]	[0, 29, 4]	[0, 29, 3]	[0, 28, 3]	[0, 28, 2]	[0, 29, 2]	[0, 29, 1]	[0, 28, 1]	[0, 28, 0]	[0, 29, 0]
DCM0:DRP41	[0, 29, 15]	[0, 28, 15]	[0, 28, 14]	[0, 29, 14]	[0, 29, 13]	[0, 28, 13]	[0, 28, 12]	[0, 29, 12]	[0, 29, 11]	[0, 28, 11]	[0, 28, 10]	[0, 29, 10]	[0, 29, 9]	[0, 28, 9]	[0, 28, 8]	[0, 29, 8]
DCM0:DRP42	[0, 29, 23]	[0, 28, 23]	[0, 28, 22]	[0, 29, 22]	[0, 29, 21]	[0, 28, 21]	[0, 28, 20]	[0, 29, 20]	[0, 29, 19]	[0, 28, 19]	[0, 28, 18]	[0, 29, 18]	[0, 29, 17]	[0, 28, 17]	[0, 28, 16]	[0, 29, 16]
DCM0:DRP43	[0, 29, 31]	[0, 28, 31]	[0, 28, 30]	[0, 29, 30]	[0, 29, 29]	[0, 28, 29]	[0, 28, 28]	[0, 29, 28]	[0, 29, 27]	[0, 28, 27]	[0, 28, 26]	[0, 29, 26]	[0, 29, 25]	[0, 28, 25]	[0, 28, 24]	[0, 29, 24]
DCM0:DRP44	[0, 29, 39]	[0, 28, 39]	[0, 28, 38]	[0, 29, 38]	[0, 29, 37]	[0, 28, 37]	[0, 28, 36]	[0, 29, 36]	[0, 29, 35]	[0, 28, 35]	[0, 28, 34]	[0, 29, 34]	[0, 29, 33]	[0, 28, 33]	[0, 28, 32]	[0, 29, 32]
DCM0:DRP45	[0, 29, 47]	[0, 28, 47]	[0, 28, 46]	[0, 29, 46]	[0, 29, 45]	[0, 28, 45]	[0, 28, 44]	[0, 29, 44]	[0, 29, 43]	[0, 28, 43]	[0, 28, 42]	[0, 29, 42]	[0, 29, 41]	[0, 28, 41]	[0, 28, 40]	[0, 29, 40]
DCM0:DRP46	[0, 29, 55]	[0, 28, 55]	[0, 28, 54]	[0, 29, 54]	[0, 29, 53]	[0, 28, 53]	[0, 28, 52]	[0, 29, 52]	[0, 29, 51]	[0, 28, 51]	[0, 28, 50]	[0, 29, 50]	[0, 29, 49]	[0, 28, 49]	[0, 28, 48]	[0, 29, 48]
DCM0:DRP47	[0, 29, 63]	[0, 28, 63]	[0, 28, 62]	[0, 29, 62]	[0, 29, 61]	[0, 28, 61]	[0, 28, 60]	[0, 29, 60]	[0, 29, 59]	[0, 28, 59]	[0, 28, 58]	[0, 29, 58]	[0, 29, 57]	[0, 28, 57]	[0, 28, 56]	[0, 29, 56]
DCM0:DRP48	[1, 29, 7]	[1, 28, 7]	[1, 28, 6]	[1, 29, 6]	[1, 29, 5]	[1, 28, 5]	[1, 28, 4]	[1, 29, 4]	[1, 29, 3]	[1, 28, 3]	[1, 28, 2]	[1, 29, 2]	[1, 29, 1]	[1, 28, 1]	[1, 28, 0]	[1, 29, 0]
DCM0:DRP49	[1, 29, 15]	[1, 28, 15]	[1, 28, 14]	[1, 29, 14]	[1, 29, 13]	[1, 28, 13]	[1, 28, 12]	[1, 29, 12]	[1, 29, 11]	[1, 28, 11]	[1, 28, 10]	[1, 29, 10]	[1, 29, 9]	[1, 28, 9]	[1, 28, 8]	[1, 29, 8]
DCM0:DRP4A	[1, 29, 23]	[1, 28, 23]	[1, 28, 22]	[1, 29, 22]	[1, 29, 21]	[1, 28, 21]	[1, 28, 20]	[1, 29, 20]	[1, 29, 19]	[1, 28, 19]	[1, 28, 18]	[1, 29, 18]	[1, 29, 17]	[1, 28, 17]	[1, 28, 16]	[1, 29, 16]
DCM0:DRP4B	[1, 29, 31]	[1, 28, 31]	[1, 28, 30]	[1, 29, 30]	[1, 29, 29]	[1, 28, 29]	[1, 28, 28]	[1, 29, 28]	[1, 29, 27]	[1, 28, 27]	[1, 28, 26]	[1, 29, 26]	[1, 29, 25]	[1, 28, 25]	[1, 28, 24]	[1, 29, 24]
DCM0:DRP4C	[1, 29, 39]	[1, 28, 39]	[1, 28, 38]	[1, 29, 38]	[1, 29, 37]	[1, 28, 37]	[1, 28, 36]	[1, 29, 36]	[1, 29, 35]	[1, 28, 35]	[1, 28, 34]	[1, 29, 34]	[1, 29, 33]	[1, 28, 33]	[1, 28, 32]	[1, 29, 32]
DCM0:DRP4D	[1, 29, 47]	[1, 28, 47]	[1, 28, 46]	[1, 29, 46]	[1, 29, 45]	[1, 28, 45]	[1, 28, 44]	[1, 29, 44]	[1, 29, 43]	[1, 28, 43]	[1, 28, 42]	[1, 29, 42]	[1, 29, 41]	[1, 28, 41]	[1, 28, 40]	[1, 29, 40]
DCM0:DRP4E	[1, 29, 55]	[1, 28, 55]	[1, 28, 54]	[1, 29, 54]	[1, 29, 53]	[1, 28, 53]	[1, 28, 52]	[1, 29, 52]	[1, 29, 51]	[1, 28, 51]	[1, 28, 50]	[1, 29, 50]	[1, 29, 49]	[1, 28, 49]	[1, 28, 48]	[1, 29, 48]
DCM0:DRP4F	[1, 29, 63]	[1, 28, 63]	[1, 28, 62]	[1, 29, 62]	[1, 29, 61]	[1, 28, 61]	[1, 28, 60]	[1, 29, 60]	[1, 29, 59]	[1, 28, 59]	[1, 28, 58]	[1, 29, 58]	[1, 29, 57]	[1, 28, 57]	[1, 28, 56]	[1, 29, 56]
DCM0:DRP50	[2, 29, 7]	[2, 28, 7]	[2, 28, 6]	[2, 29, 6]	[2, 29, 5]	[2, 28, 5]	[2, 28, 4]	[2, 29, 4]	[2, 29, 3]	[2, 28, 3]	[2, 28, 2]	[2, 29, 2]	[2, 29, 1]	[2, 28, 1]	[2, 28, 0]	[2, 29, 0]
DCM0:DRP51	[2, 29, 15]	[2, 28, 15]	[2, 28, 14]	[2, 29, 14]	[2, 29, 13]	[2, 28, 13]	[2, 28, 12]	[2, 29, 12]	[2, 29, 11]	[2, 28, 11]	[2, 28, 10]	[2, 29, 10]	[2, 29, 9]	[2, 28, 9]	[2, 28, 8]	[2, 29, 8]
DCM0:DRP52	[2, 29, 23]	[2, 28, 23]	[2, 28, 22]	[2, 29, 22]	[2, 29, 21]	[2, 28, 21]	[2, 28, 20]	[2, 29, 20]	[2, 29, 19]	[2, 28, 19]	[2, 28, 18]	[2, 29, 18]	[2, 29, 17]	[2, 28, 17]	[2, 28, 16]	[2, 29, 16]
DCM0:DRP53	[2, 29, 31]	[2, 28, 31]	[2, 28, 30]	[2, 29, 30]	[2, 29, 29]	[2, 28, 29]	[2, 28, 28]	[2, 29, 28]	[2, 29, 27]	[2, 28, 27]	[2, 28, 26]	[2, 29, 26]	[2, 29, 25]	[2, 28, 25]	[2, 28, 24]	[2, 29, 24]
DCM0:DRP54	[2, 29, 39]	[2, 28, 39]	[2, 28, 38]	[2, 29, 38]	[2, 29, 37]	[2, 28, 37]	[2, 28, 36]	[2, 29, 36]	[2, 29, 35]	[2, 28, 35]	[2, 28, 34]	[2, 29, 34]	[2, 29, 33]	[2, 28, 33]	[2, 28, 32]	[2, 29, 32]
DCM0:DRP55	[2, 29, 47]	[2, 28, 47]	[2, 28, 46]	[2, 29, 46]	[2, 29, 45]	[2, 28, 45]	[2, 28, 44]	[2, 29, 44]	[2, 29, 43]	[2, 28, 43]	[2, 28, 42]	[2, 29, 42]	[2, 29, 41]	[2, 28, 41]	[2, 28, 40]	[2, 29, 40]
DCM0:DRP56	[2, 29, 55]	[2, 28, 55]	[2, 28, 54]	[2, 29, 54]	[2, 29, 53]	[2, 28, 53]	[2, 28, 52]	[2, 29, 52]	[2, 29, 51]	[2, 28, 51]	[2, 28, 50]	[2, 29, 50]	[2, 29, 49]	[2, 28, 49]	[2, 28, 48]	[2, 29, 48]
DCM0:DRP57	[2, 29, 63]	[2, 28, 63]	[2, 28, 62]	[2, 29, 62]	[2, 29, 61]	[2, 28, 61]	[2, 28, 60]	[2, 29, 60]	[2, 29, 59]	[2, 28, 59]	[2, 28, 58]	[2, 29, 58]	[2, 29, 57]	[2, 28, 57]	[2, 28, 56]	[2, 29, 56]
DCM0:FACTORY_JF	[1, 29, 63]	[1, 28, 63]	[1, 28, 62]	[1, 29, 62]	[1, 29, 61]	[1, 28, 61]	[1, 28, 60]	[1, 29, 60]	[1, 29, 59]	[1, 28, 59]	[1, 28, 58]	[1, 29, 58]	[1, 29, 57]	[1, 28, 57]	[1, 28, 56]	[1, 29, 56]
DCM1:DRP40	[7, 29, 7]	[7, 28, 7]	[7, 28, 6]	[7, 29, 6]	[7, 29, 5]	[7, 28, 5]	[7, 28, 4]	[7, 29, 4]	[7, 29, 3]	[7, 28, 3]	[7, 28, 2]	[7, 29, 2]	[7, 29, 1]	[7, 28, 1]	[7, 28, 0]	[7, 29, 0]
DCM1:DRP41	[7, 29, 15]	[7, 28, 15]	[7, 28, 14]	[7, 29, 14]	[7, 29, 13]	[7, 28, 13]	[7, 28, 12]	[7, 29, 12]	[7, 29, 11]	[7, 28, 11]	[7, 28, 10]	[7, 29, 10]	[7, 29, 9]	[7, 28, 9]	[7, 28, 8]	[7, 29, 8]
DCM1:DRP42	[7, 29, 23]	[7, 28, 23]	[7, 28, 22]	[7, 29, 22]	[7, 29, 21]	[7, 28, 21]	[7, 28, 20]	[7, 29, 20]	[7, 29, 19]	[7, 28, 19]	[7, 28, 18]	[7, 29, 18]	[7, 29, 17]	[7, 28, 17]	[7, 28, 16]	[7, 29, 16]
DCM1:DRP43	[7, 29, 31]	[7, 28, 31]	[7, 28, 30]	[7, 29, 30]	[7, 29, 29]	[7, 28, 29]	[7, 28, 28]	[7, 29, 28]	[7, 29, 27]	[7, 28, 27]	[7, 28, 26]	[7, 29, 26]	[7, 29, 25]	[7, 28, 25]	[7, 28, 24]	[7, 29, 24]
DCM1:DRP44	[7, 29, 39]	[7, 28, 39]	[7, 28, 38]	[7, 29, 38]	[7, 29, 37]	[7, 28, 37]	[7, 28, 36]	[7, 29, 36]	[7, 29, 35]	[7, 28, 35]	[7, 28, 34]	[7, 29, 34]	[7, 29, 33]	[7, 28, 33]	[7, 28, 32]	[7, 29, 32]
DCM1:DRP45	[7, 29, 47]	[7, 28, 47]	[7, 28, 46]	[7, 29, 46]	[7, 29, 45]	[7, 28, 45]	[7, 28, 44]	[7, 29, 44]	[7, 29, 43]	[7, 28, 43]	[7, 28, 42]	[7, 29, 42]	[7, 29, 41]	[7, 28, 41]	[7, 28, 40]	[7, 29, 40]
DCM1:DRP46	[7, 29, 55]	[7, 28, 55]	[7, 28, 54]	[7, 29, 54]	[7, 29, 53]	[7, 28, 53]	[7, 28, 52]	[7, 29, 52]	[7, 29, 51]	[7, 28, 51]	[7, 28, 50]	[7, 29, 50]	[7, 29, 49]	[7, 28, 49]	[7, 28, 48]	[7, 29, 48]
DCM1:DRP47	[7, 29, 63]	[7, 28, 63]	[7, 28, 62]	[7, 29, 62]	[7, 29, 61]	[7, 28, 61]	[7, 28, 60]	[7, 29, 60]	[7, 29, 59]	[7, 28, 59]	[7, 28, 58]	[7, 29, 58]	[7, 29, 57]	[7, 28, 57]	[7, 28, 56]	[7, 29, 56]
DCM1:DRP48	[8, 29, 7]	[8, 28, 7]	[8, 28, 6]	[8, 29, 6]	[8, 29, 5]	[8, 28, 5]	[8, 28, 4]	[8, 29, 4]	[8, 29, 3]	[8, 28, 3]	[8, 28, 2]	[8, 29, 2]	[8, 29, 1]	[8, 28, 1]	[8, 28, 0]	[8, 29, 0]
DCM1:DRP49	[8, 29, 15]	[8, 28, 15]	[8, 28, 14]	[8, 29, 14]	[8, 29, 13]	[8, 28, 13]	[8, 28, 12]	[8, 29, 12]	[8, 29, 11]	[8, 28, 11]	[8, 28, 10]	[8, 29, 10]	[8, 29, 9]	[8, 28, 9]	[8, 28, 8]	[8, 29, 8]
DCM1:DRP4A	[8, 29, 23]	[8, 28, 23]	[8, 28, 22]	[8, 29, 22]	[8, 29, 21]	[8, 28, 21]	[8, 28, 20]	[8, 29, 20]	[8, 29, 19]	[8, 28, 19]	[8, 28, 18]	[8, 29, 18]	[8, 29, 17]	[8, 28, 17]	[8, 28, 16]	[8, 29, 16]
DCM1:DRP4B	[8, 29, 31]	[8, 28, 31]	[8, 28, 30]	[8, 29, 30]	[8, 29, 29]	[8, 28, 29]	[8, 28, 28]	[8, 29, 28]	[8, 29, 27]	[8, 28, 27]	[8, 28, 26]	[8, 29, 26]	[8, 29, 25]	[8, 28, 25]	[8, 28, 24]	[8, 29, 24]
DCM1:DRP4C	[8, 29, 39]	[8, 28, 39]	[8, 28, 38]	[8, 29, 38]	[8, 29, 37]	[8, 28, 37]	[8, 28, 36]	[8, 29, 36]	[8, 29, 35]	[8, 28, 35]	[8, 28, 34]	[8, 29, 34]	[8, 29, 33]	[8, 28, 33]	[8, 28, 32]	[8, 29, 32]
DCM1:DRP4D	[8, 29, 47]	[8, 28, 47]	[8, 28, 46]	[8, 29, 46]	[8, 29, 45]	[8, 28, 45]	[8, 28, 44]	[8, 29, 44]	[8, 29, 43]	[8, 28, 43]	[8, 28, 42]	[8, 29, 42]	[8, 29, 41]	[8, 28, 41]	[8, 28, 40]	[8, 29, 40]
DCM1:DRP4E	[8, 29, 55]	[8, 28, 55]	[8, 28, 54]	[8, 29, 54]	[8, 29, 53]	[8, 28, 53]	[8, 28, 52]	[8, 29, 52]	[8, 29, 51]	[8, 28, 51]	[8, 28, 50]	[8, 29, 50]	[8, 29, 49]	[8, 28, 49]	[8, 28, 48]	[8, 29, 48]
DCM1:DRP4F	[8, 29, 63]	[8, 28, 63]	[8, 28, 62]	[8, 29, 62]	[8, 29, 61]	[8, 28, 61]	[8, 28, 60]	[8, 29, 60]	[8, 29, 59]	[8, 28, 59]	[8, 28, 58]	[8, 29, 58]	[8, 29, 57]	[8, 28, 57]	[8, 28, 56]	[8, 29, 56]
DCM1:DRP50	[9, 29, 7]	[9, 28, 7]	[9, 28, 6]	[9, 29, 6]	[9, 29, 5]	[9, 28, 5]	[9, 28, 4]	[9, 29, 4]	[9, 29, 3]	[9, 28, 3]	[9, 28, 2]	[9, 29, 2]	[9, 29, 1]	[9, 28, 1]	[9, 28, 0]	[9, 29, 0]
DCM1:DRP51	[9, 29, 15]	[9, 28, 15]	[9, 28, 14]	[9, 29, 14]	[9, 29, 13]	[9, 28, 13]	[9, 28, 12]	[9, 29, 12]	[9, 29, 11]	[9, 28, 11]	[9, 28, 10]	[9, 29, 10]	[9, 29, 9]	[9, 28, 9]	[9, 28, 8]	[9, 29, 8]
DCM1:DRP52	[9, 29, 23]	[9, 28, 23]	[9, 28, 22]	[9, 29, 22]	[9, 29, 21]	[9, 28, 21]	[9, 28, 20]	[9, 29, 20]	[9, 29, 19]	[9, 28, 19]	[9, 28, 18]	[9, 29, 18]	[9, 29, 17]	[9, 28, 17]	[9, 28, 16]	[9, 29, 16]
DCM1:DRP53	[9, 29, 31]	[9, 28, 31]	[9, 28, 30]	[9, 29, 30]	[9, 29, 29]	[9, 28, 29]	[9, 28, 28]	[9, 29, 28]	[9, 29, 27]	[9, 28, 27]	[9, 28, 26]	[9, 29, 26]	[9, 29, 25]	[9, 28, 25]	[9, 28, 24]	[9, 29, 24]
DCM1:DRP54	[9, 29, 39]	[9, 28, 39]	[9, 28, 38]	[9, 29, 38]	[9, 29, 37]	[9, 28, 37]	[9, 28, 36]	[9, 29, 36]	[9, 29, 35]	[9, 28, 35]	[9, 28, 34]	[9, 29, 34]	[9, 29, 33]	[9, 28, 33]	[9, 28, 32]	[9, 29, 32]
DCM1:DRP55	[9, 29, 47]	[9, 28, 47]	[9, 28, 46]	[9, 29, 46]	[9, 29, 45]	[9, 28, 45]	[9, 28, 44]	[9, 29, 44]	[9, 29, 43]	[9, 28, 43]	[9, 28, 42]	[9, 29, 42]	[9, 29, 41]	[9, 28, 41]	[9, 28, 40]	[9, 29, 40]
DCM1:DRP56	[9, 29, 55]	[9, 28, 55]	[9, 28, 54]	[9, 29, 54]	[9, 29, 53]	[9, 28, 53]	[9, 28, 52]	[9, 29, 52]	[9, 29, 51]	[9, 28, 51]	[9, 28, 50]	[9, 29, 50]	[9, 29, 49]	[9, 28, 49]	[9, 28, 48]	[9, 29, 48]
DCM1:DRP57	[9, 29, 63]	[9, 28, 63]	[9, 28, 62]	[9, 29, 62]	[9, 29, 61]	[9, 28, 61]	[9, 28, 60]	[9, 29, 60]	[9, 29, 59]	[9, 28, 59]	[9, 28, 58]	[9, 29, 58]	[9, 29, 57]	[9, 28, 57]	[9, 28, 56]	[9, 29, 56]
DCM1:FACTORY_JF	[8, 29, 63]	[8, 28, 63]	[8, 28, 62]	[8, 29, 62]	[8, 29, 61]	[8, 28, 61]	[8, 28, 60]	[8, 29, 60]	[8, 29, 59]	[8, 28, 59]	[8, 28, 58]	[8, 29, 58]	[8, 29, 57]	[8, 28, 57]	[8, 28, 56]	[8, 29, 56]
PLL:DRP00	[3, 29, 7]	[3, 28, 7]	[3, 28, 6]	[3, 29, 6]	[3, 29, 5]	[3, 28, 5]	[3, 28, 4]	[3, 29, 4]	[3, 29, 3]	[3, 28, 3]	[3, 28, 2]	[3, 29, 2]	[3, 29, 1]	[3, 28, 1]	[3, 28, 0]	[3, 29, 0]
PLL:DRP01	[3, 29, 15]	[3, 28, 15]	[3, 28, 14]	[3, 29, 14]	[3, 29, 13]	[3, 28, 13]	[3, 28, 12]	[3, 29, 12]	[3, 29, 11]	[3, 28, 11]	[3, 28, 10]	[3, 29, 10]	[3, 29, 9]	[3, 28, 9]	[3, 28, 8]	[3, 29, 8]
PLL:DRP02	[3, 29, 23]	[3, 28, 23]	[3, 28, 22]	[3, 29, 22]	[3, 29, 21]	[3, 28, 21]	[3, 28, 20]	[3, 29, 20]	[3, 29, 19]	[3, 28, 19]	[3, 28, 18]	[3, 29, 18]	[3, 29, 17]	[3, 28, 17]	[3, 28, 16]	[3, 29, 16]
PLL:DRP03	[3, 29, 31]	[3, 28, 31]	[3, 28, 30]	[3, 29, 30]	[3, 29, 29]	[3, 28, 29]	[3, 28, 28]	[3, 29, 28]	[3, 29, 27]	[3, 28, 27]	[3, 28, 26]	[3, 29, 26]	[3, 29, 25]	[3, 28, 25]	[3, 28, 24]	[3, 29, 24]
PLL:DRP04	[3, 29, 39]	[3, 28, 39]	[3, 28, 38]	[3, 29, 38]	[3, 29, 37]	[3, 28, 37]	[3, 28, 36]	[3, 29, 36]	[3, 29, 35]	[3, 28, 35]	[3, 28, 34]	[3, 29, 34]	[3, 29, 33]	[3, 28, 33]	[3, 28, 32]	[3, 29, 32]
PLL:DRP05	[3, 29, 47]	[3, 28, 47]	[3, 28, 46]	[3, 29, 46]	[3, 29, 45]	[3, 28, 45]	[3, 28, 44]	[3, 29, 44]	[3, 29, 43]	[3, 28, 43]	[3, 28, 42]	[3, 29, 42]	[3, 29, 41]	[3, 28, 41]	[3, 28, 40]	[3, 29, 40]
PLL:DRP06	[3, 29, 55]	[3, 28, 55]	[3, 28, 54]	[3, 29, 54]	[3, 29, 53]	[3, 28, 53]	[3, 28, 52]	[3, 29, 52]	[3, 29, 51]	[3, 28, 51]	[3, 28, 50]	[3, 29, 50]	[3, 29, 49]	[3, 28, 49]	[3, 28, 48]	[3, 29, 48]
PLL:DRP07	[3, 29, 63]	[3, 28, 63]	[3, 28, 62]	[3, 29, 62]	[3, 29, 61]	[3, 28, 61]	[3, 28, 60]	[3, 29, 60]	[3, 29, 59]	[3, 28, 59]	[3, 28, 58]	[3, 29, 58]	[3, 29, 57]	[3, 28, 57]	[3, 28, 56]	[3, 29, 56]
PLL:DRP08	[4, 29, 7]	[4, 28, 7]	[4, 28, 6]	[4, 29, 6]	[4, 29, 5]	[4, 28, 5]	[4, 28, 4]	[4, 29, 4]	[4, 29, 3]	[4, 28, 3]	[4, 28, 2]	[4, 29, 2]	[4, 29, 1]	[4, 28, 1]	[4, 28, 0]	[4, 29, 0]
PLL:DRP09	[4, 29, 15]	[4, 28, 15]	[4, 28, 14]	[4, 29, 14]	[4, 29, 13]	[4, 28, 13]	[4, 28, 12]	[4, 29, 12]	[4, 29, 11]	[4, 28, 11]	[4, 28, 10]	[4, 29, 10]	[4, 29, 9]	[4, 28, 9]	[4, 28, 8]	[4, 29, 8]
PLL:DRP0A	[4, 29, 23]	[4, 28, 23]	[4, 28, 22]	[4, 29, 22]	[4, 29, 21]	[4, 28, 21]	[4, 28, 20]	[4, 29, 20]	[4, 29, 19]	[4, 28, 19]	[4, 28, 18]	[4, 29, 18]	[4, 29, 17]	[4, 28, 17]	[4, 28, 16]	[4, 29, 16]
PLL:DRP0B	[4, 29, 31]	[4, 28, 31]	[4, 28, 30]	[4, 29, 30]	[4, 29, 29]	[4, 28, 29]	[4, 28, 28]	[4, 29, 28]	[4, 29, 27]	[4, 28, 27]	[4, 28, 26]	[4, 29, 26]	[4, 29, 25]	[4, 28, 25]	[4, 28, 24]	[4, 29, 24]
PLL:DRP0C	[4, 29, 39]	[4, 28, 39]	[4, 28, 38]	[4, 29, 38]	[4, 29, 37]	[4, 28, 37]	[4, 28, 36]	[4, 29, 36]	[4, 29, 35]	[4, 28, 35]	[4, 28, 34]	[4, 29, 34]	[4, 29, 33]	[4, 28, 33]	[4, 28, 32]	[4, 29, 32]
PLL:DRP0D	[4, 29, 47]	[4, 28, 47]	[4, 28, 46]	[4, 29, 46]	[4, 29, 45]	[4, 28, 45]	[4, 28, 44]	[4, 29, 44]	[4, 29, 43]	[4, 28, 43]	[4, 28, 42]	[4, 29, 42]	[4, 29, 41]	[4, 28, 41]	[4, 28, 40]	[4, 29, 40]
PLL:DRP0E	[4, 29, 55]	[4, 28, 55]	[4, 28, 54]	[4, 29, 54]	[4, 29, 53]	[4, 28, 53]	[4, 28, 52]	[4, 29, 52]	[4, 29, 51]	[4, 28, 51]	[4, 28, 50]	[4, 29, 50]	[4, 29, 49]	[4, 28, 49]	[4, 28, 48]	[4, 29, 48]
PLL:DRP0F	[4, 29, 63]	[4, 28, 63]	[4, 28, 62]	[4, 29, 62]	[4, 29, 61]	[4, 28, 61]	[4, 28, 60]	[4, 29, 60]	[4, 29, 59]	[4, 28, 59]	[4, 28, 58]	[4, 29, 58]	[4, 29, 57]	[4, 28, 57]	[4, 28, 56]	[4, 29, 56]
PLL:DRP10	[5, 29, 7]	[5, 28, 7]	[5, 28, 6]	[5, 29, 6]	[5, 29, 5]	[5, 28, 5]	[5, 28, 4]	[5, 29, 4]	[5, 29, 3]	[5, 28, 3]	[5, 28, 2]	[5, 29, 2]	[5, 29, 1]	[5, 28, 1]	[5, 28, 0]	[5, 29, 0]
PLL:DRP11	[5, 29, 15]	[5, 28, 15]	[5, 28, 14]	[5, 29, 14]	[5, 29, 13]	[5, 28, 13]	[5, 28, 12]	[5, 29, 12]	[5, 29, 11]	[5, 28, 11]	[5, 28, 10]	[5, 29, 10]	[5, 29, 9]	[5, 28, 9]	[5, 28, 8]	[5, 29, 8]
PLL:DRP12	[5, 29, 23]	[5, 28, 23]	[5, 28, 22]	[5, 29, 22]	[5, 29, 21]	[5, 28, 21]	[5, 28, 20]	[5, 29, 20]	[5, 29, 19]	[5, 28, 19]	[5, 28, 18]	[5, 29, 18]	[5, 29, 17]	[5, 28, 17]	[5, 28, 16]	[5, 29, 16]
PLL:DRP13	[5, 29, 31]	[5, 28, 31]	[5, 28, 30]	[5, 29, 30]	[5, 29, 29]	[5, 28, 29]	[5, 28, 28]	[5, 29, 28]	[5, 29, 27]	[5, 28, 27]	[5, 28, 26]	[5, 29, 26]	[5, 29, 25]	[5, 28, 25]	[5, 28, 24]	[5, 29, 24]
PLL:DRP14	[5, 29, 39]	[5, 28, 39]	[5, 28, 38]	[5, 29, 38]	[5, 29, 37]	[5, 28, 37]	[5, 28, 36]	[5, 29, 36]	[5, 29, 35]	[5, 28, 35]	[5, 28, 34]	[5, 29, 34]	[5, 29, 33]	[5, 28, 33]	[5, 28, 32]	[5, 29, 32]
PLL:DRP15	[5, 29, 47]	[5, 28, 47]	[5, 28, 46]	[5, 29, 46]	[5, 29, 45]	[5, 28, 45]	[5, 28, 44]	[5, 29, 44]	[5, 29, 43]	[5, 28, 43]	[5, 28, 42]	[5, 29, 42]	[5, 29, 41]	[5, 28, 41]	[5, 28, 40]	[5, 29, 40]
PLL:DRP16	[5, 29, 55]	[5, 28, 55]	[5, 28, 54]	[5, 29, 54]	[5, 29, 53]	[5, 28, 53]	[5, 28, 52]	[5, 29, 52]	[5, 29, 51]	[5, 28, 51]	[5, 28, 50]	[5, 29, 50]	[5, 29, 49]	[5, 28, 49]	[5, 28, 48]	[5, 29, 48]
PLL:DRP17	[5, 29, 63]	[5, 28, 63]	[5, 28, 62]	[5, 29, 62]	[5, 29, 61]	[5, 28, 61]	[5, 28, 60]	[5, 29, 60]	[5, 29, 59]	[5, 28, 59]	[5, 28, 58]	[5, 29, 58]	[5, 29, 57]	[5, 28, 57]	[5, 28, 56]	[5, 29, 56]
PLL:DRP18	[6, 29, 7]	[6, 28, 7]	[6, 28, 6]	[6, 29, 6]	[6, 29, 5]	[6, 28, 5]	[6, 28, 4]	[6, 29, 4]	[6, 29, 3]	[6, 28, 3]	[6, 28, 2]	[6, 29, 2]	[6, 29, 1]	[6, 28, 1]	[6, 28, 0]	[6, 29, 0]
PLL:DRP19	[6, 29, 15]	[6, 28, 15]	[6, 28, 14]	[6, 29, 14]	[6, 29, 13]	[6, 28, 13]	[6, 28, 12]	[6, 29, 12]	[6, 29, 11]	[6, 28, 11]	[6, 28, 10]	[6, 29, 10]	[6, 29, 9]	[6, 28, 9]	[6, 28, 8]	[6, 29, 8]
PLL:DRP1A	[6, 29, 23]	[6, 28, 23]	[6, 28, 22]	[6, 29, 22]	[6, 29, 21]	[6, 28, 21]	[6, 28, 20]	[6, 29, 20]	[6, 29, 19]	[6, 28, 19]	[6, 28, 18]	[6, 29, 18]	[6, 29, 17]	[6, 28, 17]	[6, 28, 16]	[6, 29, 16]
PLL:DRP1B	[6, 29, 31]	[6, 28, 31]	[6, 28, 30]	[6, 29, 30]	[6, 29, 29]	[6, 28, 29]	[6, 28, 28]	[6, 29, 28]	[6, 29, 27]	[6, 28, 27]	[6, 28, 26]	[6, 29, 26]	[6, 29, 25]	[6, 28, 25]	[6, 28, 24]	[6, 29, 24]
PLL:DRP1C	[6, 29, 39]	[6, 28, 39]	[6, 28, 38]	[6, 29, 38]	[6, 29, 37]	[6, 28, 37]	[6, 28, 36]	[6, 29, 36]	[6, 29, 35]	[6, 28, 35]	[6, 28, 34]	[6, 29, 34]	[6, 29, 33]	[6, 28, 33]	[6, 28, 32]	[6, 29, 32]
PLL:DRP1D	[6, 29, 47]	[6, 28, 47]	[6, 28, 46]	[6, 29, 46]	[6, 29, 45]	[6, 28, 45]	[6, 28, 44]	[6, 29, 44]	[6, 29, 43]	[6, 28, 43]	[6, 28, 42]	[6, 29, 42]	[6, 29, 41]	[6, 28, 41]	[6, 28, 40]	[6, 29, 40]
PLL:DRP1E	[6, 29, 55]	[6, 28, 55]	[6, 28, 54]	[6, 29, 54]	[6, 29, 53]	[6, 28, 53]	[6, 28, 52]	[6, 29, 52]	[6, 29, 51]	[6, 28, 51]	[6, 28, 50]	[6, 29, 50]	[6, 29, 49]	[6, 28, 49]	[6, 28, 48]	[6, 29, 48]
PLL:DRP1F	[6, 29, 63]	[6, 28, 63]	[6, 28, 62]	[6, 29, 62]	[6, 29, 61]	[6, 28, 61]	[6, 28, 60]	[6, 29, 60]	[6, 29, 59]	[6, 28, 59]	[6, 28, 58]	[6, 29, 58]	[6, 29, 57]	[6, 28, 57]	[6, 28, 56]	[6, 29, 56]
Non-inverted	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCM0:DESKEW_ADJUST	[0, 29, 27]	[0, 28, 27]	[0, 28, 26]	[0, 29, 26]	[0, 29, 25]
DCM1:DESKEW_ADJUST	[7, 29, 27]	[7, 28, 27]	[7, 28, 26]	[7, 29, 26]	[7, 29, 25]
PLL:CLKFBOUT_DESKEW_ADJUST	[4, 29, 47]	[4, 28, 47]	[4, 28, 46]	[4, 29, 46]	[4, 29, 45]
PLL:CLKOUT0_DESKEW_ADJUST	[6, 29, 39]	[6, 28, 39]	[6, 28, 38]	[6, 29, 38]	[6, 29, 37]
PLL:CLKOUT1_DESKEW_ADJUST	[6, 29, 23]	[6, 28, 23]	[6, 28, 22]	[6, 29, 22]	[6, 29, 21]
PLL:CLKOUT2_DESKEW_ADJUST	[5, 29, 63]	[5, 28, 63]	[5, 28, 62]	[5, 29, 62]	[5, 29, 61]
PLL:CLKOUT3_DESKEW_ADJUST	[5, 29, 47]	[5, 28, 47]	[5, 28, 46]	[5, 29, 46]	[5, 29, 45]
PLL:CLKOUT4_DESKEW_ADJUST	[5, 29, 31]	[5, 28, 31]	[5, 28, 30]	[5, 29, 30]	[5, 29, 29]
PLL:CLKOUT5_DESKEW_ADJUST	[4, 29, 63]	[4, 28, 63]	[4, 28, 62]	[4, 29, 62]	[4, 29, 61]
PLL:PLL_IN_DLY_MX_SEL	[3, 28, 63]	[3, 28, 62]	[3, 29, 62]	[3, 29, 61]	[3, 28, 61]
PLL:PLL_LOCK_FB_P1	[3, 29, 26]	[3, 29, 25]	[3, 28, 25]	[3, 28, 24]	[3, 29, 24]
PLL:PLL_LOCK_FB_P2	[3, 28, 28]	[3, 29, 28]	[3, 29, 27]	[3, 28, 27]	[3, 28, 26]
PLL:PLL_LOCK_REF_P1	[3, 28, 21]	[3, 28, 20]	[3, 29, 20]	[3, 29, 19]	[3, 28, 19]
PLL:PLL_LOCK_REF_P2	[3, 29, 23]	[3, 28, 23]	[3, 28, 22]	[3, 29, 22]	[3, 29, 21]
Non-inverted	[4]	[3]	[2]	[1]	[0]

DCM0:DLL_SYNTH_CLOCK_SPEED	[0, 28, 34]	[0, 29, 34]
DCM1:DLL_SYNTH_CLOCK_SPEED	[7, 28, 34]	[7, 29, 34]
NORMAL	0	0
HALF	0	1
QUARTER	1	0
VDD	1	1

DCM0:DFS_TAPTRIM	[0, 28, 45]	[0, 28, 44]	[0, 29, 44]	[0, 29, 43]	[0, 28, 43]	[0, 28, 42]	[0, 29, 42]	[0, 29, 41]	[0, 28, 41]	[0, 28, 40]	[0, 29, 40]
DCM1:DFS_TAPTRIM	[7, 28, 45]	[7, 28, 44]	[7, 29, 44]	[7, 29, 43]	[7, 28, 43]	[7, 28, 42]	[7, 29, 42]	[7, 29, 41]	[7, 28, 41]	[7, 28, 40]	[7, 29, 40]
Non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCM0:CLKFX_DIVIDE	[2, 29, 3]	[2, 28, 3]	[2, 28, 2]	[2, 29, 2]	[2, 29, 1]	[2, 28, 1]	[2, 28, 0]	[2, 29, 0]
DCM0:CLKFX_MULTIPLY	[2, 29, 7]	[2, 28, 7]	[2, 28, 6]	[2, 29, 6]	[2, 29, 5]	[2, 28, 5]	[2, 28, 4]	[2, 29, 4]
DCM0:DFS_TWEAK	[0, 29, 51]	[0, 28, 51]	[0, 28, 50]	[0, 29, 50]	[0, 29, 49]	[0, 28, 49]	[0, 28, 48]	[0, 29, 48]
DCM0:DLL_DEAD_TIME	[2, 29, 23]	[2, 28, 23]	[2, 28, 22]	[2, 29, 22]	[2, 29, 21]	[2, 28, 21]	[2, 28, 20]	[2, 29, 20]
DCM0:DLL_DESKEW_MAXTAP	[1, 29, 55]	[1, 28, 55]	[1, 28, 54]	[1, 29, 54]	[1, 29, 53]	[1, 28, 53]	[1, 28, 52]	[1, 29, 52]
DCM0:DLL_DESKEW_MINTAP	[1, 29, 51]	[1, 28, 51]	[1, 28, 50]	[1, 29, 50]	[1, 29, 49]	[1, 28, 49]	[1, 28, 48]	[1, 29, 48]
DCM0:DLL_LIVE_TIME	[2, 29, 19]	[2, 28, 19]	[2, 28, 18]	[2, 29, 18]	[2, 29, 17]	[2, 28, 17]	[2, 28, 16]	[2, 29, 16]
DCM0:DLL_SETTLE_TIME	[2, 29, 15]	[2, 28, 15]	[2, 28, 14]	[2, 29, 14]	[2, 29, 13]	[2, 28, 13]	[2, 28, 12]	[2, 29, 12]
DCM0:DLL_ZD1_TAP_INIT	[1, 29, 47]	[1, 28, 47]	[1, 28, 46]	[1, 29, 46]	[1, 29, 45]	[1, 28, 45]	[1, 28, 44]	[1, 29, 44]
DCM1:CLKFX_DIVIDE	[9, 29, 3]	[9, 28, 3]	[9, 28, 2]	[9, 29, 2]	[9, 29, 1]	[9, 28, 1]	[9, 28, 0]	[9, 29, 0]
DCM1:CLKFX_MULTIPLY	[9, 29, 7]	[9, 28, 7]	[9, 28, 6]	[9, 29, 6]	[9, 29, 5]	[9, 28, 5]	[9, 28, 4]	[9, 29, 4]
DCM1:DFS_TWEAK	[7, 29, 51]	[7, 28, 51]	[7, 28, 50]	[7, 29, 50]	[7, 29, 49]	[7, 28, 49]	[7, 28, 48]	[7, 29, 48]
DCM1:DLL_DEAD_TIME	[9, 29, 23]	[9, 28, 23]	[9, 28, 22]	[9, 29, 22]	[9, 29, 21]	[9, 28, 21]	[9, 28, 20]	[9, 29, 20]
DCM1:DLL_DESKEW_MAXTAP	[8, 29, 55]	[8, 28, 55]	[8, 28, 54]	[8, 29, 54]	[8, 29, 53]	[8, 28, 53]	[8, 28, 52]	[8, 29, 52]
DCM1:DLL_DESKEW_MINTAP	[8, 29, 51]	[8, 28, 51]	[8, 28, 50]	[8, 29, 50]	[8, 29, 49]	[8, 28, 49]	[8, 28, 48]	[8, 29, 48]
DCM1:DLL_LIVE_TIME	[9, 29, 19]	[9, 28, 19]	[9, 28, 18]	[9, 29, 18]	[9, 29, 17]	[9, 28, 17]	[9, 28, 16]	[9, 29, 16]
DCM1:DLL_SETTLE_TIME	[9, 29, 15]	[9, 28, 15]	[9, 28, 14]	[9, 29, 14]	[9, 29, 13]	[9, 28, 13]	[9, 28, 12]	[9, 29, 12]
DCM1:DLL_ZD1_TAP_INIT	[8, 29, 47]	[8, 28, 47]	[8, 28, 46]	[8, 29, 46]	[8, 29, 45]	[8, 28, 45]	[8, 28, 44]	[8, 29, 44]
Non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCM0:MUX.CLKFB	[1, 28, 4]	[1, 29, 4]	[1, 29, 3]	[1, 28, 3]	[1, 28, 2]
DCM0:MUX.CLKIN	[1, 29, 2]	[1, 29, 1]	[1, 28, 1]	[1, 28, 0]	[1, 29, 0]
DCM1:MUX.CLKFB	[8, 28, 4]	[8, 29, 4]	[8, 29, 3]	[8, 28, 3]	[8, 28, 2]
DCM1:MUX.CLKIN	[8, 29, 2]	[8, 29, 1]	[8, 28, 1]	[8, 28, 0]	[8, 29, 0]
GIOB0	0	0	0	0	0
GIOB1	0	0	0	0	1
GIOB2	0	0	0	1	0
GIOB3	0	0	0	1	1
GIOB4	0	0	1	0	0
GIOB5	0	0	1	0	1
GIOB6	0	1	0	0	0
GIOB7	0	1	0	0	1
GIOB8	0	1	0	1	0
GIOB9	0	1	0	1	1
HCLK0	0	1	1	0	0
HCLK1	0	1	1	0	1
HCLK2	1	0	0	0	0
HCLK3	1	0	0	0	1
HCLK4	1	0	0	1	0
HCLK5	1	0	0	1	1
HCLK6	1	0	1	0	0
HCLK7	1	0	1	0	1
HCLK8	1	1	0	0	0
HCLK9	1	1	0	0	1
CKINT0	1	1	0	1	0
CKINT1	1	1	0	1	1
CKINT2	1	1	1	0	0
CLK_FROM_PLL	1	1	1	0	1

DCM0:MUX.CLK_TO_PLL	[1, 28, 6]	[1, 29, 6]	[1, 29, 5]	[1, 28, 5]
DCM0:MUX.SKEWCLKIN2	[1, 29, 9]	[1, 28, 9]	[1, 28, 8]	[1, 29, 8]
DCM1:MUX.CLK_TO_PLL	[8, 28, 6]	[8, 29, 6]	[8, 29, 5]	[8, 28, 5]
DCM1:MUX.SKEWCLKIN2	[8, 29, 9]	[8, 28, 9]	[8, 28, 8]	[8, 29, 8]
CLK0	0	0	0	0
CLK90	0	0	0	1
CLK180	0	0	1	0
CLK270	0	0	1	1
CLK2X	0	1	0	0
CLK2X180	0	1	0	1
CLKDV	0	1	1	0
CLKFX	0	1	1	1
CLKFX180	1	0	0	0
CONCUR	1	0	0	1

DCM0:DLL_PHASE_SHIFT_CALIBRATION	[1, 28, 24]	[1, 29, 24]
DCM1:DLL_PHASE_SHIFT_CALIBRATION	[8, 28, 24]	[8, 29, 24]
AUTO_DPS	0	0
CONFIG	0	1
MASK	1	0
AUTO_ZD2	1	1

DCM0:DLL_ZD2_TAP_INIT	[1, 28, 43]	[1, 28, 42]	[1, 29, 42]	[1, 29, 41]	[1, 28, 41]	[1, 28, 40]	[1, 29, 40]
DCM1:DLL_ZD2_TAP_INIT	[8, 28, 43]	[8, 28, 42]	[8, 29, 42]	[8, 29, 41]	[8, 28, 41]	[8, 28, 40]	[8, 29, 40]
Non-inverted	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCM0:DLL_FREQUENCY_MODE	[2, 29, 9]	[2, 28, 9]
DCM1:DLL_FREQUENCY_MODE	[9, 29, 9]	[9, 28, 9]
LOW	0	0
HIGH	1	1

DCM0:PS_MODE	[2, 29, 10]
DCM1:PS_MODE	[9, 29, 10]
CLKFB	0
CLKIN	1

DCM0:CLKDV_MODE	[2, 29, 32]
DCM1:CLKDV_MODE	[9, 29, 32]
HALF	0
INT	1

DCM0:PHASE_SHIFT	[2, 28, 44]	[2, 29, 44]	[2, 29, 43]	[2, 28, 43]	[2, 28, 42]	[2, 29, 42]	[2, 29, 41]	[2, 28, 41]	[2, 28, 40]	[2, 29, 40]
DCM1:PHASE_SHIFT	[9, 28, 44]	[9, 29, 44]	[9, 29, 43]	[9, 28, 43]	[9, 28, 42]	[9, 29, 42]	[9, 29, 41]	[9, 28, 41]	[9, 28, 40]	[9, 29, 40]
Non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCM0:DLL_PHASE_SHIFT_LFC	[2, 29, 52]	[2, 29, 51]	[2, 28, 51]	[2, 28, 50]	[2, 29, 50]	[2, 29, 49]	[2, 28, 49]	[2, 28, 48]	[2, 29, 48]
DCM1:DLL_PHASE_SHIFT_LFC	[9, 29, 52]	[9, 29, 51]	[9, 28, 51]	[9, 28, 50]	[9, 29, 50]	[9, 29, 49]	[9, 28, 49]	[9, 28, 48]	[9, 29, 48]
PLL:PLL_IN_DLY_SET	[3, 29, 60]	[3, 29, 59]	[3, 28, 59]	[3, 28, 58]	[3, 29, 58]	[3, 29, 57]	[3, 28, 57]	[3, 28, 56]	[3, 29, 56]
Non-inverted	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

PLL:PLL_CLKFBOUT2_DT	[4, 28, 18]	[4, 29, 18]	[4, 29, 17]	[4, 28, 17]	[4, 28, 16]	[4, 29, 16]
PLL:PLL_CLKFBOUT2_HT	[4, 29, 13]	[4, 28, 13]	[4, 28, 12]	[4, 29, 12]	[4, 29, 11]	[4, 28, 11]
PLL:PLL_CLKFBOUT2_LT	[4, 28, 10]	[4, 29, 10]	[4, 29, 9]	[4, 28, 9]	[4, 28, 8]	[4, 29, 8]
PLL:PLL_CLKFBOUT_DT	[4, 28, 42]	[4, 29, 42]	[4, 29, 41]	[4, 28, 41]	[4, 28, 40]	[4, 29, 40]
PLL:PLL_CLKFBOUT_HT	[4, 29, 37]	[4, 28, 37]	[4, 28, 36]	[4, 29, 36]	[4, 29, 35]	[4, 28, 35]
PLL:PLL_CLKFBOUT_LT	[4, 28, 34]	[4, 29, 34]	[4, 29, 33]	[4, 28, 33]	[4, 28, 32]	[4, 29, 32]
PLL:PLL_CLKOUT0_DT	[6, 28, 34]	[6, 29, 34]	[6, 29, 33]	[6, 28, 33]	[6, 28, 32]	[6, 29, 32]
PLL:PLL_CLKOUT0_HT	[6, 29, 29]	[6, 28, 29]	[6, 28, 28]	[6, 29, 28]	[6, 29, 27]	[6, 28, 27]
PLL:PLL_CLKOUT0_LT	[6, 28, 26]	[6, 29, 26]	[6, 29, 25]	[6, 28, 25]	[6, 28, 24]	[6, 29, 24]
PLL:PLL_CLKOUT1_DT	[6, 28, 18]	[6, 29, 18]	[6, 29, 17]	[6, 28, 17]	[6, 28, 16]	[6, 29, 16]
PLL:PLL_CLKOUT1_HT	[6, 29, 13]	[6, 28, 13]	[6, 28, 12]	[6, 29, 12]	[6, 29, 11]	[6, 28, 11]
PLL:PLL_CLKOUT1_LT	[6, 28, 10]	[6, 29, 10]	[6, 29, 9]	[6, 28, 9]	[6, 28, 8]	[6, 29, 8]
PLL:PLL_CLKOUT2_DT	[5, 28, 58]	[5, 29, 58]	[5, 29, 57]	[5, 28, 57]	[5, 28, 56]	[5, 29, 56]
PLL:PLL_CLKOUT2_HT	[5, 29, 53]	[5, 28, 53]	[5, 28, 52]	[5, 29, 52]	[5, 29, 51]	[5, 28, 51]
PLL:PLL_CLKOUT2_LT	[5, 28, 50]	[5, 29, 50]	[5, 29, 49]	[5, 28, 49]	[5, 28, 48]	[5, 29, 48]
PLL:PLL_CLKOUT3_DT	[5, 28, 42]	[5, 29, 42]	[5, 29, 41]	[5, 28, 41]	[5, 28, 40]	[5, 29, 40]
PLL:PLL_CLKOUT3_HT	[5, 29, 37]	[5, 28, 37]	[5, 28, 36]	[5, 29, 36]	[5, 29, 35]	[5, 28, 35]
PLL:PLL_CLKOUT3_LT	[5, 28, 34]	[5, 29, 34]	[5, 29, 33]	[5, 28, 33]	[5, 28, 32]	[5, 29, 32]
PLL:PLL_CLKOUT4_DT	[5, 28, 26]	[5, 29, 26]	[5, 29, 25]	[5, 28, 25]	[5, 28, 24]	[5, 29, 24]
PLL:PLL_CLKOUT4_HT	[5, 29, 21]	[5, 28, 21]	[5, 28, 20]	[5, 29, 20]	[5, 29, 19]	[5, 28, 19]
PLL:PLL_CLKOUT4_LT	[5, 28, 18]	[5, 29, 18]	[5, 29, 17]	[5, 28, 17]	[5, 28, 16]	[5, 29, 16]
PLL:PLL_CLKOUT5_DT	[4, 28, 58]	[4, 29, 58]	[4, 29, 57]	[4, 28, 57]	[4, 28, 56]	[4, 29, 56]
PLL:PLL_CLKOUT5_HT	[4, 29, 53]	[4, 28, 53]	[4, 28, 52]	[4, 29, 52]	[4, 29, 51]	[4, 28, 51]
PLL:PLL_CLKOUT5_LT	[4, 28, 50]	[4, 29, 50]	[4, 29, 49]	[4, 28, 49]	[4, 28, 48]	[4, 29, 48]
PLL:PLL_DIVCLK_DT	[4, 29, 23]	[4, 28, 23]	[4, 28, 22]	[4, 29, 22]	[4, 29, 21]	[4, 28, 21]
PLL:PLL_DIVCLK_HT	[3, 29, 53]	[3, 28, 53]	[3, 28, 52]	[3, 29, 52]	[3, 29, 51]	[3, 28, 51]
PLL:PLL_DIVCLK_LT	[3, 28, 50]	[3, 29, 50]	[3, 29, 49]	[3, 28, 49]	[3, 28, 48]	[3, 29, 48]
PLL:PLL_FLOCK	[3, 29, 35]	[3, 28, 35]	[3, 28, 34]	[3, 29, 34]	[3, 29, 33]	[3, 28, 33]
PLL:PLL_LOCK_CNT	[3, 28, 18]	[3, 29, 18]	[3, 29, 17]	[3, 28, 17]	[3, 28, 16]	[3, 29, 16]
Non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

PLL:PLL_EN_CNTRL	[5, 28, 14]	[5, 29, 14]	[5, 29, 13]	[5, 28, 13]	[5, 28, 12]	[5, 29, 12]	[5, 29, 11]	[5, 28, 11]	[5, 28, 10]	[5, 29, 10]	[5, 29, 9]	[5, 28, 9]	[5, 28, 8]	[5, 29, 8]	[5, 29, 7]	[5, 28, 7]	[5, 28, 6]	[5, 29, 6]	[5, 29, 5]	[5, 28, 5]	[5, 28, 4]	[5, 29, 4]	[5, 29, 3]	[5, 28, 3]	[5, 28, 2]	[5, 29, 2]	[5, 29, 1]	[5, 28, 1]	[5, 28, 0]	[5, 29, 0]	[4, 29, 31]	[4, 28, 31]	[4, 28, 30]	[4, 29, 30]	[4, 29, 29]	[4, 28, 29]	[4, 28, 28]	[4, 29, 28]	[4, 29, 27]	[4, 28, 27]	[4, 28, 26]	[4, 29, 26]	[4, 29, 25]	[4, 28, 25]	[4, 28, 24]	[4, 29, 24]	[4, 29, 7]	[4, 28, 7]	[4, 28, 6]	[4, 29, 6]	[4, 29, 5]	[4, 28, 5]	[4, 28, 4]	[4, 29, 4]	[4, 29, 3]	[4, 28, 3]	[4, 28, 2]	[4, 29, 2]	[4, 29, 1]	[4, 28, 1]	[4, 28, 0]	[4, 29, 0]	[3, 29, 47]	[3, 28, 47]	[3, 28, 46]	[3, 29, 46]	[3, 29, 45]	[3, 28, 45]	[3, 28, 44]	[3, 29, 44]	[3, 29, 43]	[3, 28, 43]	[3, 28, 42]	[3, 29, 42]	[3, 29, 41]	[3, 28, 41]	[3, 28, 40]	[3, 29, 40]
Non-inverted	[77]	[76]	[75]	[74]	[73]	[72]	[71]	[70]	[69]	[68]	[67]	[66]	[65]	[64]	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

CMT:MUX.OUT10	[6, 29, 45]	[6, 28, 45]	[6, 28, 44]
DCM1_CLKIN	0	0	0
DCM0_CLKIN	0	0	1
DCM1_CLKFB	0	1	0
DCM0_CLKFB	0	1	1
PLL_CLKIN	1	0	0
PLL_CLKINFB	1	0	1
NONE	1	1	1

PLL:MUX.CLKFBIN	[6, 28, 52]	[6, 29, 52]	[6, 29, 51]	[6, 28, 51]	[6, 28, 50]
GIOB0	0	0	0	0	0
GIOB1	0	0	0	0	1
GIOB2	0	0	0	1	0
HCLK0	0	0	0	1	1
HCLK1	0	0	1	0	0
HCLK2	0	0	1	0	1
GIOB3	0	1	0	0	0
GIOB4	0	1	0	0	1
HCLK3	0	1	0	1	0
HCLK4	0	1	0	1	1
GIOB5	1	0	0	0	0
GIOB6	1	0	0	0	1
GIOB7	1	0	0	1	0
HCLK5	1	0	0	1	1
HCLK6	1	0	1	0	0
HCLK7	1	0	1	0	1
GIOB8	1	1	0	0	0
GIOB9	1	1	0	0	1
HCLK8	1	1	0	1	0
HCLK9	1	1	0	1	1
CLKFBDCM	1	1	1	0	0
CLKFBOUT	1	1	1	0	1
CKINT1	1	1	1	1	0

PLL:MUX.CLK_TO_DCM1	[6, 28, 54]	[6, 29, 55]	[6, 28, 55]
CLKOUTDCM0	0	0	0
CLKOUTDCM2	0	0	1
CLKOUTDCM4	0	1	0
NONE	0	1	1
CLKOUTDCM1	1	0	0
CLKOUTDCM3	1	0	1
CLKOUTDCM5	1	1	0
CLKFBDCM	1	1	1

PLL:CLKINSEL_MODE	[6, 29, 43]
STATIC	0
DYNAMIC	1

PLL:MUX.CLKIN	[6, 29, 49]	[6, 28, 49]	[6, 28, 48]	[6, 29, 48]
GIOB0_GIOB5	0	0	0	0
GIOB1_GIOB6	0	0	0	1
GIOB2_GIOB7	0	0	1	0
HCLK0_HCLK5	0	0	1	1
HCLK1_HCLK6	0	1	0	0
HCLK2_HCLK7	0	1	0	1
GIOB3_GIOB8	1	0	0	0
GIOB4_GIOB9	1	0	0	1
HCLK3_HCLK8	1	0	1	0
HCLK4_HCLK9	1	0	1	1
NONE_CLKFBDCM	1	1	0	0
CLK_FROM_DCM0_NONE	1	1	0	1
CLK_FROM_DCM1_NONE	1	1	1	0
CKINT0_NONE	1	1	1	1

PLL:MUX.CLK_TO_DCM0	[6, 28, 53]	[6, 29, 54]	[6, 29, 53]
CLKOUTDCM0	0	0	0
CLKOUTDCM2	0	0	1
CLKOUTDCM4	0	1	0
NONE	0	1	1
CLKOUTDCM1	1	0	0
CLKOUTDCM3	1	0	1
CLKOUTDCM5	1	1	0

Tables

Name	PLL:PLL_CP	PLL:PLL_RES	PLL:PLL_LFHF
HIGH:1	2	11	3
HIGH:10	14	14	3
HIGH:11	15	14	3
HIGH:12	15	14	3
HIGH:13	15	1	3
HIGH:14	15	1	3
HIGH:15	15	1	3
HIGH:16	14	6	3
HIGH:17	14	6	3
HIGH:18	15	6	3
HIGH:19	14	10	3
HIGH:2	5	15	3
HIGH:20	14	10	3
HIGH:21	15	10	3
HIGH:22	15	10	3
HIGH:23	15	10	3
HIGH:24	15	10	3
HIGH:25	15	10	3
HIGH:26	15	10	3
HIGH:27	13	12	3
HIGH:28	13	12	3
HIGH:29	13	12	3
HIGH:3	12	15	3
HIGH:30	14	12	3
HIGH:31	13	12	3
HIGH:32	12	2	3
HIGH:33	15	10	3
HIGH:34	7	2	3
HIGH:35	7	2	3
HIGH:36	7	2	3
HIGH:37	6	2	3
HIGH:38	6	2	3
HIGH:39	6	2	3
HIGH:4	15	15	3
HIGH:40	6	2	3
HIGH:41	6	2	3
HIGH:42	4	4	3
HIGH:43	4	4	3
HIGH:44	4	4	3
HIGH:45	3	8	3
HIGH:46	3	8	3
HIGH:47	3	4	3
HIGH:48	3	4	3
HIGH:49	3	4	3
HIGH:5	15	7	3
HIGH:50	3	4	3
HIGH:51	3	4	3
HIGH:52	3	4	3
HIGH:53	3	4	3
HIGH:54	3	4	3
HIGH:55	3	4	3
HIGH:56	3	4	3
HIGH:57	2	8	3
HIGH:58	2	8	3
HIGH:59	2	8	3
HIGH:6	15	13	3
HIGH:60	2	8	3
HIGH:61	2	8	3
HIGH:62	2	8	3
HIGH:63	2	8	3
HIGH:64	2	8	3
HIGH:7	15	3	3
HIGH:8	15	5	3
HIGH:9	15	9	3
LOW:1	1	13	3
LOW:10	1	4	3
LOW:11	1	4	3
LOW:12	1	4	3
LOW:13	1	4	3
LOW:14	1	4	3
LOW:15	1	4	3
LOW:16	1	4	3
LOW:17	1	4	3
LOW:18	1	4	3
LOW:19	1	8	3
LOW:2	1	14	3
LOW:20	1	8	3
LOW:21	1	8	3
LOW:22	1	8	3
LOW:23	1	8	3
LOW:24	1	8	3
LOW:25	1	8	3
LOW:26	1	8	3
LOW:27	1	8	3
LOW:28	1	8	3
LOW:29	1	8	3
LOW:3	1	6	3
LOW:30	1	8	3
LOW:31	2	4	3
LOW:32	2	4	3
LOW:33	2	4	3
LOW:34	2	4	3
LOW:35	2	4	3
LOW:36	2	4	3
LOW:37	2	4	3
LOW:38	2	8	3
LOW:39	2	8	3
LOW:4	1	10	3
LOW:40	2	8	3
LOW:41	2	8	3
LOW:42	2	8	3
LOW:43	2	8	3
LOW:44	2	8	3
LOW:45	2	8	3
LOW:46	2	8	3
LOW:47	2	8	3
LOW:48	2	8	3
LOW:49	2	8	3
LOW:5	1	12	3
LOW:50	2	8	3
LOW:51	2	8	3
LOW:52	2	8	3
LOW:53	2	8	3
LOW:54	2	8	3
LOW:55	2	8	3
LOW:56	2	8	3
LOW:57	2	8	3
LOW:58	2	8	3
LOW:59	2	8	3
LOW:6	1	12	3
LOW:60	2	8	3
LOW:61	2	8	3
LOW:62	2	8	3
LOW:63	2	8	3
LOW:64	2	8	3
LOW:7	1	12	3
LOW:8	1	2	3
LOW:9	1	2	3

Device	PLL:PLL_IN_DLY_SET
	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
xc5vfx100t	0	0	0	0	1	1	1	0	1
xc5vfx130t	0	0	0	0	1	1	1	1	0
xc5vfx200t	0	0	0	0	1	1	1	1	1
xc5vfx30t	0	0	0	0	1	1	1	0	1
xc5vfx70t	0	0	0	0	1	1	1	0	1
xc5vlx110	0	0	0	0	1	1	1	0	1
xc5vlx110t	0	0	0	0	1	1	1	0	1
xc5vlx155	0	0	0	0	1	1	1	0	1
xc5vlx155t	0	0	0	0	1	1	1	0	1
xc5vlx20t	0	0	0	0	1	1	0	1	0
xc5vlx220	0	0	0	0	1	1	1	1	1
xc5vlx220t	0	0	0	0	1	1	1	1	1
xc5vlx30	0	0	0	0	1	1	1	0	0
xc5vlx30t	0	0	0	0	1	1	1	0	0
xc5vlx330	0	0	0	0	1	1	1	1	1
xc5vlx330t	0	0	0	0	1	1	1	1	1
xc5vlx50	0	0	0	0	1	1	1	0	0
xc5vlx50t	0	0	0	0	1	1	1	0	0
xc5vlx85	0	0	0	0	1	1	1	0	1
xc5vlx85t	0	0	0	0	1	1	1	0	1
xc5vsx240t	0	0	0	0	1	1	1	1	1
xc5vsx35t	0	0	0	0	1	1	1	0	1
xc5vsx50t	0	0	0	0	1	1	1	0	1
xc5vsx95t	0	0	0	0	1	1	1	1	1
xc5vtx150t	0	0	0	0	1	1	1	0	1
xc5vtx240t	0	0	0	0	1	1	1	1	0
xq5vfx100t	0	0	0	0	1	1	1	0	1
xq5vfx130t	0	0	0	0	1	1	1	1	0
xq5vfx200t	0	0	0	0	1	1	1	1	1
xq5vfx70t	0	0	0	0	1	1	1	0	1
xq5vlx110	0	0	0	0	1	1	1	0	1
xq5vlx110t	0	0	0	0	1	1	1	0	1
xq5vlx155t	0	0	0	0	1	1	1	0	1
xq5vlx220t	0	0	0	0	1	1	1	1	1
xq5vlx30t	0	0	0	0	1	1	1	0	0
xq5vlx330t	0	0	0	0	1	1	1	1	1
xq5vlx85	0	0	0	0	1	1	1	0	1
xq5vsx240t	0	0	0	0	1	1	1	1	1
xq5vsx50t	0	0	0	0	1	1	1	0	1
xq5vsx95t	0	0	0	0	1	1	1	1	1