Input/Output

I/O banks and special functions

Virtex 5 devices have up to three I/O columns:

  • the left I/O column, containing only IO tiles; if the device has no transceivers on the left side, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column; it is always present

  • the center column, part of which contains IO tiles; the IO tiles in this column come in up to four segments:

    • the lower segment (variable size, not present on all devices), between the bottom edge of the device and the lower CMTs

    • the lower middle segment (always 20 tiles high), between lower CMTs and the configuration center

    • the upper middle segment (always 20 tiles high), between the configuration center and the upper CMTs

    • the upper segment (variable size, not present on all devices), between the device and the upper CMTs and the top edge of the device

  • the right I/O column, containing only IO tiles; it is present on all devices except for xc5vlx20t; if present, it is somewhat to the left of the device’s right edge

Virtex 5 has the following banks:

  • bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:

    • CCLK

    • CS_B

    • DONE

    • D_OUT_BUSY

    • D_IN

    • HSWAPEN

    • INIT

    • M0

    • M1

    • M2

    • PROGRAM_B

    • RDWR_B

    • TCK

    • TDI

    • TDO

    • TMS

    bank 0 is not associated with any IO tiles

  • banks 1-4: middle segments of the center column; each of them consists of 10 IO tiles; they contain global clock inputs and shared configuration pins

    • bank 1: immediately above configuration center

    • bank 2: immediately below configuration center

    • bank 3: above bank 1, below upper CMTs (not present on xc5vlx20t)

    • bank 4: below bank 2, above lower CMTs

  • banks 5-10: lower and upper segments of the center column; each of them consists of 20 IO tiles

    • banks 5, 7, 9 are the upper segment, with bank 5 being immediately above upper CMTs; bank number increases upwards

    • banks 6, 8, 10 are the lower segment, with bank 6 being immediately below lower CMTs; bank number increases downwards

  • banks 11 and up: left and right column; each of them consists of 20 IO tiles

    • banks 11, 15, 19, 23, …: left column, above the configuration center; bank number increases upwards, starting from bank 11 immediately above the configuration center row

    • banks 12, 16, 20, 24, …: right column, above the configuration center; bank number increases upwards, starting from bank 12 immediately above the configuration center row

    • banks 13, 17, 21, 25, …: left column, below the configuration center; bank number increases downwards, starting from bank 13 immediately below the configuration center row

    • banks 14, 18, 22, 26, …: right column, below the configuration center; bank number increases downwards, starting from bank 14 immediately below the configuration center row

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input and true differential output is supported on all pins of the device.

IOB1 pads in the 4 rows surronding the HCLK row (that is, in rows 8-11 of every clock region) are considered “clock-capable”. They can drive BUFIO and BUFR buffers via dedicated connections. While Xilinx documentation also considers IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

The IOB1 pads in banks 3 and 4 are considered “global clock-capable”. They can drive BUFGCTRL buffers and CMT primitives via dedicated connections. Likewise, Xilinx considers IOB0 pads to be clock-capable, but they can only drive clocks as part of differential pair with IOB1.

The IOB0 in rows 5 and 15 of every region is capable of being used as a VREF pad.

Each bank except for banks 1 and 2 has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

  • bank 1 and 2: VRP/VRN are not present in this bank (DCI can still be used by cascade from banks 3 and 4)

  • bank 3: row 7 of the bank (or row 7 of the region)

  • bank 4: row 2 of the bank (or row 12 of the region)

  • banks 5 and up: row 7 of the bank (or row 7 of the region)

In parallel configuration modes, some I/O pads in banks 1-4 are borrowed for configuration use, as the parallel data pins:

  • bank 4 row 6 IOB0: D[8]

  • bank 4 row 6 IOB1: D[9]

  • bank 4 row 7 IOB0: D[10]

  • bank 4 row 7 IOB1: D[11]

  • bank 4 row 8 IOB0: D[12]

  • bank 4 row 8 IOB1: D[13]

  • bank 4 row 9 IOB0: D[14]

  • bank 4 row 9 IOB1: D[15]

  • bank 2 row 0 IOB0: D[0]/FS[0]

  • bank 2 row 0 IOB1: D[1]/FS[1]

  • bank 2 row 1 IOB0: D[2]/FS[2]

  • bank 2 row 1 IOB1: D[3]

  • bank 2 row 2 IOB0: D[4]

  • bank 2 row 2 IOB1: D[5]

  • bank 2 row 3 IOB0: D[6]

  • bank 2 row 3 IOB1: D[7]

  • bank 2 row 4 IOB0: CSO_B

  • bank 2 row 4 IOB1: FWE_B

  • bank 2 row 5 IOB0: FOE_B/MOSI

  • bank 2 row 5 IOB1: FCS_B

  • bank 2 row 6 IOB0: A[20]

  • bank 2 row 6 IOB1: A[21]

  • bank 2 row 7 IOB0: A[22]

  • bank 2 row 7 IOB1: A[23]

  • bank 2 row 8 IOB0: A[24]

  • bank 2 row 8 IOB1: A[25]

  • bank 2 row 9 IOB0: RS[0]

  • bank 2 row 9 IOB1: RS[1]

  • bank 1 row 0 IOB0: D[16]/A[0]

  • bank 1 row 0 IOB1: D[17]/A[1]

  • bank 1 row 1 IOB0: D[18]/A[2]

  • bank 1 row 1 IOB1: D[19]/A[3]

  • bank 1 row 2 IOB0: D[20]/A[4]

  • bank 1 row 2 IOB1: D[21]/A[5]

  • bank 1 row 3 IOB0: D[22]/A[6]

  • bank 1 row 3 IOB1: D[23]/A[7]

  • bank 1 row 4 IOB0: D[24]/A[8]

  • bank 1 row 4 IOB1: D[25]/A[9]

  • bank 1 row 5 IOB0: D[26]/A[10]

  • bank 1 row 5 IOB1: D[27]/A[11]

  • bank 1 row 6 IOB0: D[28]/A[12]

  • bank 1 row 6 IOB1: D[29]/A[13]

  • bank 1 row 7 IOB0: D[30]/A[14]

  • bank 1 row 7 IOB1: D[31]/A[15]

  • bank 1 row 8 IOB0: A[16]

  • bank 1 row 8 IOB1: A[17]

  • bank 1 row 9 IOB0: A[18]

  • bank 1 row 9 IOB1: A[19]

The SYSMON present on the device can use up to 16 IOB pairs from the left I/O column as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. The IOBs are in the following tiles, where r is the configuration center row:

  • VP0/VN0: left I/O column, row r - 10

  • VP1/VN1: left I/O column, row r - 9

  • VP2/VN2: left I/O column, row r - 8

  • VP3/VN3: left I/O column, row r - 7

  • VP4/VN4: left I/O column, row r - 6

  • VP5/VN5: left I/O column, row r - 4

  • VP6/VN6: left I/O column, row r - 3

  • VP7/VN7: left I/O column, row r - 2

  • VP8/VN8: left I/O column, row r - 1

  • VP9/VN9: left I/O column, row r

  • VP10/VN10: left I/O column, row r + 1

  • VP11/VN11: left I/O column, row r + 2

  • VP12/VN12: left I/O column, row r + 3

  • VP13/VN13: left I/O column, row r + 4

  • VP14/VN14: left I/O column, row r + 8

  • VP15/VN15: left I/O column, row r + 9

Bitstream

IO bittile 0
RowColumn
012345678910111213141516171819202122232425262728293031323334353637
0 ----------------------------~ILOGIC0:INIT_RANK3[0]-IODELAY0:DELAY_SRC[0]IODELAY0:DELAY_SRC[3]-OLOGIC0:OFF_SR_SYNC[1]~OLOGIC0:INV.T3~OLOGIC0:INV.T4-IOB0:PDRIVE[1]
1 ----------------------------~ILOGIC0:INIT_RANK1_PARTIAL[0]~ILOGIC0:INIT_RANK3[1]IODELAY0:DELAY_SRC[1]IOI_CLK:MUX.ICLK0[4]OLOGIC0:TFF_SR_SYNC[0]--~OLOGIC0:TFF_INIT[2]--
2 ----------------------------~ILOGIC0:INIT_BITSLIPCNT[2]-IOI_CLK:MUX.ICLK0[3]IODELAY0:DELAYCHAIN_OSC~OLOGIC0:INV.T1-OLOGIC0:OFF_SERDES[0]--~IOB0:NDRIVE[1]
3 -----------------------------~ILOGIC0:INIT_RANK2[0]IOI_CLK:MUX.ICLK0[2]IODELAY0:DELAY_SRC[2]IODELAY0:IDELAY_VALUE_INIT[5]~OLOGIC0:INV.T2--IOB0:VRIOB0:OUTPUT_MISC[5]
4 ----------------------------~ILOGIC0:INIT_BITSLIPCNT[1]-IOI_CLK:MUX.ICLK0[0]IOI_CLK:MUX.ICLK0[1]---~OLOGIC0:TFF_INIT[3]IOB0:OUTPUT_MISC[4]-
5 ----------------------------~ILOGIC0:INIT_RANK2[1]~ILOGIC0:INIT_RANK1_PARTIAL[1]ILOGIC0:DATA_WIDTH[0]ILOGIC0:DATA_WIDTH[3]IODELAY0:IDELAY_VALUE_INIT[1]IODELAY0:IDELAY_TYPE[1]OLOGIC0:SERDES_MODEOLOGIC0:OMUX[1]IOB0:LVDS[8]~IOB0:DCIUPDATEMODE_ASREQUIRED
6 ----------------------------ILOGIC0:INV.CLKDIV-IOI_CLK:MUX.ICLK0[5]ILOGIC0:DATA_RATE-IODELAY0:IDELAY_VALUE_INIT[3]OLOGIC0:OMUX[2]OLOGIC0:OFF_SERDES[2]IOB0:NDRIVE[3]-
7 -----------------------------~ILOGIC0:INIT_RANK3[2]OLOGIC0:MUX.CLK[0]ILOGIC0:DATA_WIDTH[1]IODELAY0:ODELAY_VALUE[0]IODELAY0:IDELAY_TYPE[0]~OLOGIC0:TFF_INIT[0]-IOB0:OUTPUT_DELAYIOB0:DCI_MODE[0]
8 ----------------------------~ILOGIC0:INIT_RANK1_PARTIAL[2]~ILOGIC0:INIT_BITSLIPCNT[0]~IODELAY0:INV.DATAINILOGIC0:DATA_WIDTH[2]~IODELAY0:ENABLE[0]~OLOGIC0:OFF_INIT_SERDES[1]~OLOGIC0:TFF_INIT[1]-IOB0:DCI_MODE[1]IOB0:DCI_MODE[2]
9 ------------------------------OLOGIC0:MUX.CLK[6]OLOGIC0:MUX.CLK[7]-~IODELAY0:LEGIDELAY---~IOB0:PDRIVE[3]
10 ----------------------------~ILOGIC0:INIT_RANK2[3]-OLOGIC0:MUX.CLK[5]OLOGIC0:MUX.CLK[1]IODELAY0:IDELAY_VALUE_INIT[2]-~OLOGIC0:TFF23_SRVAL[0]~OLOGIC0:TFF23_SRVAL[1]~IOB0:NDRIVE[0]IOB0:PDRIVE[4]
11 ----------------------------~ILOGIC0:INIT_RANK2[2]~ILOGIC0:INIT_RANK1_PARTIAL[3]OLOGIC0:MUX.CLK[4]IOI_CLK:MUX.ICLK0[7]-~OLOGIC0:OFF_INIT_SERDES[2]OLOGIC0:OFF_SERDES[1]OLOGIC0:TMUX[0]IOB0:NDRIVE[4]IOB0:LVDS[0]
12 ----------------------------~ILOGIC0:INIT_CE[1]ILOGIC0:BITSLIP_ENABLE[2]ILOGIC0:INV.OCLK1OLOGIC0:MUX.CLK[3]~IODELAY0:IDELAY_VALUE_CUR[5]-OLOGIC0:OFF_SR_SYNC[2]~OLOGIC0:TFF1_SRVALIOB0:DCI_T-
13 ----------------------------~ILOGIC0:INIT_CE[0]ILOGIC0:READBACK_IOLOGIC0:MUX.CLK[2]OLOGIC0:MUX.CLKDIV[6]~OLOGIC0:OFF_INIT_SERDES[0]IODELAY0:ODELAY_VALUE[5]OLOGIC0:INV.CLKDIVOLOGIC0:OFF_SERDES[3]IOB0:LVDS[1]IOB0:PDRIVE[2]
14 ----------------------------~ILOGIC0:INIT_RANK3[3]~ILOGIC0:INIT_RANK1_PARTIAL[4]ILOGIC0:INV.OCLK2IOI_CLK:MUX.ICLK0[8]IODELAY0:HIGH_PERFORMANCE_MODE---~IOB0:PDRIVE[0]~IOB0:NDRIVE[2]
15 ----------------------------OLOGIC0:MISR_RESETILOGIC0:BITSLIP_ENABLE[3]OLOGIC0:MUX.CLK[8]ILOGIC0:SERDES_MODE~OLOGIC0:OFF_INIT[0]IODELAY0:ODELAY_VALUE[1]OLOGIC0:TFF_REV_USEDOLOGIC0:TFF_SR_USEDIOB0:PULL[1]IOB0:LVDS[2]
16 ----------------------------OLOGIC0:MISR_ENABLEOLOGIC0:MISR_CLK_SELECT[1]ILOGIC0:TSBYPASS_MUXILOGIC0:BITSLIP_ENABLE[6]~IODELAY0:IDELAY_VALUE_CUR[4]~IODELAY0:ENABLE[3]OLOGIC0:TMUX[3]~OLOGIC0:TFF_INIT[4]IOB0:PULL[0]IOB0:DCI_MISC[0]
17 ----------------------------OLOGIC0:MISR_CLK_SELECT[0]~ILOGIC0:INIT_RANK2[4]ILOGIC0:IFF_TSBYPASS_ENABLEILOGIC0:IFF_DELAY_ENABLEIODELAY0:IDELAY_VALUE_INIT[4]IODELAY0:ODELAY_VALUE[4]OLOGIC0:TMUX[2]OLOGIC0:TMUX[1]IOB0:LVDS[3]IOB0:PSLEW[0]
18 ----------------------------ILOGIC0:BITSLIP_ENABLE[0]OLOGIC0:MISR_ENABLE_FDBKOLOGIC0:MUX.CLKDIV[7]IOI_CLK:MUX.ICLK0[6]~IODELAY0:ENABLE[1]~OLOGIC0:OFF_INIT[1]-OLOGIC0:TMUX[4]IOB0:LVDS[4]IOB0:IBUF_MODE[0]
19 ----------------------------~ILOGIC0:INIT_RANK2[5]ILOGIC0:BITSLIP_SYNCOLOGIC0:MUX.CLKDIV[0]OLOGIC0:MUX.CLKDIV[1]~IODELAY0:IDELAY_VALUE_CUR[3]-OLOGIC0:TFF_SR_SYNC[1]OLOGIC0:TRISTATE_WIDTHIOB0:OUTPUT_ENABLE[0]IOB0:PULL[2]
20 ----------------------------ILOGIC0:MUX.CLKB~ILOGIC0:IFF2_INITOLOGIC0:MUX.CLKDIV[2]~ILOGIC0:IFF_LATCH~IODELAY0:ENABLE[2]~OLOGIC0:OFF_INIT[2]OLOGIC0:INV.D4OLOGIC0:SERDESIOB0:OUTPUT_MISC[3]IOB0:NSLEW[5]
21 ----------------------------ILOGIC0:MUX.CLK~ILOGIC0:INIT_RANK3[4]OLOGIC0:MUX.CLKDIV[3]OLOGIC0:MUX.CLKDIV[4]IODELAY0:IDELAY_VALUE_INIT[0]IODELAY0:ODELAY_VALUE[3]--IOB0:LVDS[5]IOB0:LVDS[6]
22 ----------------------------ILOGIC0:BITSLIP_ENABLE[1]~ILOGIC0:IFF2_SRVALILOGIC0:NUM_CE-~IODELAY0:IDELAY_VALUE_CUR[2]IODELAY0:ODELAY_VALUE[2]-~OLOGIC0:OFF_INIT[3]IOB0:OUTPUT_ENABLE[1]IOB0:LVDS[7]
23 ----------------------------ILOGIC0:SERDES-OLOGIC0:MUX.CLKDIV[5]~IOB0:INV.IOLOGIC0:INV.D2~OLOGIC0:INIT_LOADCNT[2]OLOGIC0:INV.D5OLOGIC0:INV.D3IOB0:PSLEW[1]IOB0:PSLEW[2]
24 ----------------------------~ILOGIC0:IFF1_SRVAL--ILOGIC0:IFF_SR_SYNCOLOGIC0:INV.D1--~OLOGIC0:INIT_LOADCNT[0]IOB0:OUTPUT_MISC[0]IOB0:OUTPUT_MISC[1]
25 ------------------------------ILOGIC0:IFF_REV_USEDILOGIC0:INTERFACE_TYPE---OLOGIC0:INV.D6IOB0:IBUF_MODE[1]IOB0:OUTPUT_MISC[2]
26 ----------------------------~ILOGIC0:IFF1_INITILOGIC0:BITSLIP_ENABLE[4]-ILOGIC0:IFF_SR_USEDOLOGIC0:OFF_SR_SYNC[0]OLOGIC0:DATA_WIDTH[0]OLOGIC0:OFF_REV_USEDOLOGIC0:OFF_SR_SYNC[3]IOB0:NSLEW[4]IOB0:DCI_MISC[1]
27 ----------------------------~ILOGIC0:IFF3_INIT---OLOGIC0:DATA_WIDTH[2]OLOGIC0:DATA_WIDTH[1]OLOGIC0:OFF_SR_USED~OLOGIC0:INIT_LOADCNT[1]IOB0:NSLEW[1]IOB0:PSLEW[5]
28 ----------------------------~ILOGIC0:INIT_RANK3[5]~ILOGIC0:IFF3_SRVAL-~IOI_CLK:INV.ICLK0[2]OLOGIC0:DATA_WIDTH[3]~IODELAY0:IDELAY_VALUE_CUR[0]OLOGIC0:DATA_WIDTH[5]OLOGIC0:DATA_WIDTH[4]-IOB0:NSLEW[3]
29 ----------------------------~ILOGIC0:IFF4_SRVAL~ILOGIC0:INIT_BITSLIPCNT[3]~IOI_CLK:INV.ICLK0[0]-OLOGIC0:DATA_WIDTH[6]~OLOGIC0:INIT_LOADCNT[3]OLOGIC0:OMUX[3]OLOGIC0:OMUX[4]IOB0:IBUF_MODE[2]IOB0:PSLEW[4]
30 ----------------------------ILOGIC0:DDR_CLK_EDGE[1]ILOGIC0:BITSLIP_ENABLE[5]~IOI_CLK:INV.ICLK0[1]-OLOGIC0:DATA_WIDTH[7]~OLOGIC0:INV.CLK2~OLOGIC0:OFF_SRVAL[0]OLOGIC0:OMUX[0]IOB0:VREF_SYSMONIOB0:PSLEW[3]
31 ----------------------------~ILOGIC0:IFF4_INITILOGIC0:DDR_CLK_EDGE[0]ILOGIC0:I_DELAY_ENABLEILOGIC0:I_TSBYPASS_ENABLE~IODELAY0:IDELAY_VALUE_CUR[1]~OLOGIC0:INV.CLK1~OLOGIC0:OFF_SRVAL[1]~OLOGIC0:OFF_SRVAL[2]IOB0:NSLEW[0]IOB0:NSLEW[2]
32 ----------------------------~ILOGIC1:IFF4_INITILOGIC1:DDR_CLK_EDGE[0]ILOGIC1:I_DELAY_ENABLEILOGIC1:I_TSBYPASS_ENABLE~IODELAY1:IDELAY_VALUE_CUR[1]~OLOGIC1:INV.CLK1~OLOGIC1:OFF_SRVAL[0]~OLOGIC1:OFF_SRVAL[2]IOB1:NSLEW[0]IOB1:NSLEW[2]
33 ----------------------------ILOGIC1:DDR_CLK_EDGE[1]ILOGIC1:BITSLIP_ENABLE[2]~IOI_CLK:INV.ICLK1[0]-OLOGIC1:DATA_WIDTH[7]~OLOGIC1:INV.CLK2~OLOGIC1:OFF_SRVAL[1]OLOGIC1:OMUX[0]IOB1:VREF_SYSMONIOB1:PSLEW[3]
34 ----------------------------~ILOGIC1:IFF4_SRVAL~ILOGIC1:INIT_BITSLIPCNT[3]~IOI_CLK:INV.ICLK1[1]-OLOGIC1:DATA_WIDTH[6]~OLOGIC1:INIT_LOADCNT[3]OLOGIC1:OMUX[3]OLOGIC1:OMUX[4]IOB1:IBUF_MODE[2]IOB1:PSLEW[4]
35 ----------------------------~ILOGIC1:INIT_RANK3[5]~ILOGIC1:IFF3_SRVAL-~IOI_CLK:INV.ICLK1[2]OLOGIC1:DATA_WIDTH[3]~IODELAY1:IDELAY_VALUE_CUR[0]OLOGIC1:DATA_WIDTH[5]OLOGIC1:DATA_WIDTH[4]-IOB1:NSLEW[3]
36 ----------------------------~ILOGIC1:IFF3_INIT---OLOGIC1:DATA_WIDTH[2]OLOGIC1:DATA_WIDTH[1]OLOGIC1:OFF_SR_USED~OLOGIC1:INIT_LOADCNT[1]IOB1:NSLEW[1]IOB1:PSLEW[5]
37 ----------------------------~ILOGIC1:IFF1_INITILOGIC1:BITSLIP_ENABLE[3]-ILOGIC1:IFF_SR_USEDOLOGIC1:OFF_SR_SYNC[0]OLOGIC1:DATA_WIDTH[0]OLOGIC1:OFF_REV_USEDOLOGIC1:OFF_SR_SYNC[3]IOB1:NSLEW[4]IOB1:DCI_MISC[1]
38 ------------------------------ILOGIC1:IFF_REV_USEDILOGIC1:INTERFACE_TYPE---OLOGIC1:INV.D6IOB1:IBUF_MODE[1]IOB1:OUTPUT_MISC[2]
39 ----------------------------~ILOGIC1:IFF1_SRVAL--ILOGIC1:IFF_SR_SYNCOLOGIC1:INV.D1--~OLOGIC1:INIT_LOADCNT[0]IOB1:OUTPUT_MISC[0]IOB1:OUTPUT_MISC[1]
40 ----------------------------ILOGIC1:SERDES-OLOGIC1:MUX.CLKDIV[5]~IOB1:INV.IOLOGIC1:INV.D2~OLOGIC1:INIT_LOADCNT[2]OLOGIC1:INV.D5OLOGIC1:INV.D3IOB1:PSLEW[1]IOB1:PSLEW[2]
41 ----------------------------ILOGIC1:BITSLIP_ENABLE[0]~ILOGIC1:IFF2_SRVALILOGIC1:NUM_CE-~IODELAY1:IDELAY_VALUE_CUR[2]IODELAY1:ODELAY_VALUE[2]-~OLOGIC1:OFF_INIT[3]IOB1:OUTPUT_ENABLE[0]IOB1:LVDS[7]
42 ----------------------------ILOGIC1:MUX.CLK~ILOGIC1:INIT_RANK3[4]OLOGIC1:MUX.CLKDIV[3]OLOGIC1:MUX.CLKDIV[4]IODELAY1:IDELAY_VALUE_INIT[0]IODELAY1:ODELAY_VALUE[3]--IOB1:LVDS[5]IOB1:LVDS[6]
43 ----------------------------ILOGIC1:MUX.CLKB~ILOGIC1:IFF2_INITOLOGIC1:MUX.CLKDIV[2]~ILOGIC1:IFF_LATCH~IODELAY1:ENABLE[0]~OLOGIC1:OFF_INIT[1]OLOGIC1:INV.D4OLOGIC1:SERDESIOB1:OUTPUT_MISC[3]IOB1:NSLEW[5]
44 ----------------------------~ILOGIC1:INIT_RANK2[5]ILOGIC1:BITSLIP_SYNCOLOGIC1:MUX.CLKDIV[0]OLOGIC1:MUX.CLKDIV[1]~IODELAY1:IDELAY_VALUE_CUR[3]-OLOGIC1:TFF_SR_SYNC[1]OLOGIC1:TRISTATE_WIDTHIOB1:OUTPUT_ENABLE[1]IOB1:PULL[2]
45 ----------------------------ILOGIC1:BITSLIP_ENABLE[1]OLOGIC1:MISR_ENABLE_FDBKOLOGIC1:MUX.CLKDIV[7]IOI_CLK:MUX.ICLK1[6]~IODELAY1:ENABLE[1]~OLOGIC1:OFF_INIT[2]-OLOGIC1:TMUX[4]IOB1:LVDS[4]IOB1:IBUF_MODE[0]
46 ----------------------------OLOGIC1:MISR_CLK_SELECT[0]~ILOGIC1:INIT_RANK2[4]ILOGIC1:IFF_TSBYPASS_ENABLEILOGIC1:IFF_DELAY_ENABLEIODELAY1:IDELAY_VALUE_INIT[4]IODELAY1:ODELAY_VALUE[4]OLOGIC1:TMUX[2]OLOGIC1:TMUX[1]IOB1:LVDS[3]IOB1:PSLEW[0]
47 ----------------------------OLOGIC1:MISR_ENABLEOLOGIC1:MISR_CLK_SELECT[1]ILOGIC1:TSBYPASS_MUXILOGIC1:BITSLIP_ENABLE[6]~IODELAY1:IDELAY_VALUE_CUR[4]~IODELAY1:ENABLE[3]OLOGIC1:TMUX[3]~OLOGIC1:TFF_INIT[2]IOB1:PULL[0]IOB1:DCI_MISC[0]
48 ----------------------------OLOGIC1:MISR_RESETILOGIC1:BITSLIP_ENABLE[4]OLOGIC1:MUX.CLK[8]ILOGIC1:SERDES_MODE~OLOGIC1:OFF_INIT[0]IODELAY1:ODELAY_VALUE[1]OLOGIC1:TFF_REV_USEDOLOGIC1:TFF_SR_USEDIOB1:PULL[1]IOB1:LVDS[2]
49 ----------------------------~ILOGIC1:INIT_RANK3[3]~ILOGIC1:INIT_RANK1_PARTIAL[4]ILOGIC1:INV.OCLK2IOI_CLK:MUX.ICLK1[8]IODELAY1:HIGH_PERFORMANCE_MODE---~IOB1:PDRIVE[0]~IOB1:NDRIVE[2]
50 ----------------------------~ILOGIC1:INIT_CE[0]ILOGIC1:READBACK_IOLOGIC1:MUX.CLK[2]OLOGIC1:MUX.CLKDIV[6]~OLOGIC1:OFF_INIT_SERDES[0]IODELAY1:ODELAY_VALUE[5]OLOGIC1:INV.CLKDIVOLOGIC1:OFF_SERDES[2]IOB1:LVDS[1]IOB1:PDRIVE[2]
51 ----------------------------~ILOGIC1:INIT_CE[1]ILOGIC1:BITSLIP_ENABLE[5]ILOGIC1:INV.OCLK1OLOGIC1:MUX.CLK[3]~IODELAY1:IDELAY_VALUE_CUR[5]-OLOGIC1:OFF_SR_SYNC[2]~OLOGIC1:TFF1_SRVALIOB1:DCI_T-
52 ----------------------------~ILOGIC1:INIT_RANK2[2]~ILOGIC1:INIT_RANK1_PARTIAL[3]OLOGIC1:MUX.CLK[4]IOI_CLK:MUX.ICLK1[7]-~OLOGIC1:OFF_INIT_SERDES[1]OLOGIC1:OFF_SERDES[0]OLOGIC1:TMUX[0]IOB1:NDRIVE[4]IOB1:LVDS[0]
53 ----------------------------~ILOGIC1:INIT_RANK2[3]-OLOGIC1:MUX.CLK[5]OLOGIC1:MUX.CLK[1]IODELAY1:IDELAY_VALUE_INIT[2]-~OLOGIC1:TFF23_SRVAL[0]~OLOGIC1:TFF23_SRVAL[1]~IOB1:NDRIVE[0]IOB1:PDRIVE[4]
54 ------------------------------OLOGIC1:MUX.CLK[6]OLOGIC1:MUX.CLK[7]-~IODELAY1:LEGIDELAY---~IOB1:PDRIVE[3]
55 ----------------------------~ILOGIC1:INIT_RANK1_PARTIAL[2]~ILOGIC1:INIT_BITSLIPCNT[0]~IODELAY1:INV.DATAINILOGIC1:DATA_WIDTH[2]~IODELAY1:ENABLE[2]~OLOGIC1:OFF_INIT_SERDES[2]~OLOGIC1:TFF_INIT[0]-IOB1:DCI_MODE[1]IOB1:DCI_MODE[2]
56 -----------------------------~ILOGIC1:INIT_RANK3[2]OLOGIC1:MUX.CLK[0]ILOGIC1:DATA_WIDTH[1]IODELAY1:ODELAY_VALUE[0]IODELAY1:IDELAY_TYPE[0]~OLOGIC1:TFF_INIT[1]-IOB1:OUTPUT_DELAYIOB1:DCI_MODE[0]
57 ----------------------------ILOGIC1:INV.CLKDIV-IOI_CLK:MUX.ICLK1[5]ILOGIC1:DATA_RATE-IODELAY1:IDELAY_VALUE_INIT[3]OLOGIC1:OMUX[2]OLOGIC1:OFF_SERDES[3]IOB1:NDRIVE[3]-
58 ----------------------------~ILOGIC1:INIT_RANK2[1]~ILOGIC1:INIT_RANK1_PARTIAL[1]ILOGIC1:DATA_WIDTH[0]ILOGIC1:DATA_WIDTH[3]IODELAY1:IDELAY_VALUE_INIT[1]IODELAY1:IDELAY_TYPE[1]OLOGIC1:SERDES_MODEOLOGIC1:OMUX[1]IOB1:LVDS[8]~IOB1:DCIUPDATEMODE_ASREQUIRED
59 ----------------------------~ILOGIC1:INIT_BITSLIPCNT[1]-IOI_CLK:MUX.ICLK1[0]IOI_CLK:MUX.ICLK1[1]---~OLOGIC1:TFF_INIT[3]IOB1:OUTPUT_MISC[4]-
60 -----------------------------~ILOGIC1:INIT_RANK2[0]IOI_CLK:MUX.ICLK1[2]IODELAY1:DELAY_SRC[2]IODELAY1:IDELAY_VALUE_INIT[5]~OLOGIC1:INV.T2--IOB1:VRIOB1:OUTPUT_MISC[5]
61 ----------------------------~ILOGIC1:INIT_BITSLIPCNT[2]-IOI_CLK:MUX.ICLK1[3]IODELAY1:DELAYCHAIN_OSC~OLOGIC1:INV.T1-OLOGIC1:OFF_SERDES[1]--~IOB1:NDRIVE[1]
62 ----------------------------~ILOGIC1:INIT_RANK1_PARTIAL[0]~ILOGIC1:INIT_RANK3[1]IODELAY1:DELAY_SRC[1]IOI_CLK:MUX.ICLK1[4]OLOGIC1:TFF_SR_SYNC[0]--~OLOGIC1:TFF_INIT[4]--
63 ----------------------------~ILOGIC1:INIT_RANK3[0]-IODELAY1:DELAY_SRC[0]IODELAY1:DELAY_SRC[3]-OLOGIC1:OFF_SR_SYNC[1]~OLOGIC1:INV.T3~OLOGIC1:INV.T4-IOB1:PDRIVE[1]
ILOGIC0:INIT_RANK2[0, 28, 19][0, 29, 17][0, 28, 10][0, 28, 11][0, 28, 5][0, 29, 3]
ILOGIC0:INIT_RANK3[0, 28, 28][0, 29, 21][0, 28, 14][0, 29, 7][0, 29, 1][0, 28, 0]
ILOGIC1:INIT_RANK2[0, 28, 44][0, 29, 46][0, 28, 53][0, 28, 52][0, 28, 58][0, 29, 60]
ILOGIC1:INIT_RANK3[0, 28, 35][0, 29, 42][0, 28, 49][0, 29, 56][0, 29, 62][0, 28, 63]
IODELAY0:IDELAY_VALUE_CUR[0, 32, 12][0, 32, 16][0, 32, 19][0, 32, 22][0, 32, 31][0, 33, 28]
IODELAY1:IDELAY_VALUE_CUR[0, 32, 51][0, 32, 47][0, 32, 44][0, 32, 41][0, 32, 32][0, 33, 35]
Inverted~[5]~[4]~[3]~[2]~[1]~[0]
ILOGIC0:INIT_RANK1_PARTIAL[0, 29, 14][0, 29, 11][0, 28, 8][0, 29, 5][0, 28, 1]
ILOGIC1:INIT_RANK1_PARTIAL[0, 29, 49][0, 29, 52][0, 28, 55][0, 29, 58][0, 28, 62]
OLOGIC0:TFF_INIT[0, 35, 16][0, 35, 4][0, 35, 1][0, 34, 8][0, 34, 7]
OLOGIC1:TFF_INIT[0, 35, 62][0, 35, 59][0, 35, 47][0, 34, 56][0, 34, 55]
Inverted~[4]~[3]~[2]~[1]~[0]
ILOGIC0:BITSLIP_SYNC[0, 29, 19]
ILOGIC0:IFF_DELAY_ENABLE[0, 31, 17]
ILOGIC0:IFF_REV_USED[0, 30, 25]
ILOGIC0:IFF_SR_SYNC[0, 31, 24]
ILOGIC0:IFF_SR_USED[0, 31, 26]
ILOGIC0:IFF_TSBYPASS_ENABLE[0, 30, 17]
ILOGIC0:INV.CLKDIV[0, 28, 6]
ILOGIC0:INV.OCLK1[0, 30, 12]
ILOGIC0:INV.OCLK2[0, 30, 14]
ILOGIC0:I_DELAY_ENABLE[0, 30, 31]
ILOGIC0:I_TSBYPASS_ENABLE[0, 31, 31]
ILOGIC0:READBACK_I[0, 29, 13]
ILOGIC0:SERDES[0, 28, 23]
ILOGIC1:BITSLIP_SYNC[0, 29, 44]
ILOGIC1:IFF_DELAY_ENABLE[0, 31, 46]
ILOGIC1:IFF_REV_USED[0, 30, 38]
ILOGIC1:IFF_SR_SYNC[0, 31, 39]
ILOGIC1:IFF_SR_USED[0, 31, 37]
ILOGIC1:IFF_TSBYPASS_ENABLE[0, 30, 46]
ILOGIC1:INV.CLKDIV[0, 28, 57]
ILOGIC1:INV.OCLK1[0, 30, 51]
ILOGIC1:INV.OCLK2[0, 30, 49]
ILOGIC1:I_DELAY_ENABLE[0, 30, 32]
ILOGIC1:I_TSBYPASS_ENABLE[0, 31, 32]
ILOGIC1:READBACK_I[0, 29, 50]
ILOGIC1:SERDES[0, 28, 40]
IOB0:DCI_T[0, 36, 12]
IOB0:OUTPUT_DELAY[0, 36, 7]
IOB0:VR[0, 36, 3]
IOB0:VREF_SYSMON[0, 36, 30]
IOB1:DCI_T[0, 36, 51]
IOB1:OUTPUT_DELAY[0, 36, 56]
IOB1:VR[0, 36, 60]
IOB1:VREF_SYSMON[0, 36, 33]
IODELAY0:DELAYCHAIN_OSC[0, 31, 2]
IODELAY0:HIGH_PERFORMANCE_MODE[0, 32, 14]
IODELAY1:DELAYCHAIN_OSC[0, 31, 61]
IODELAY1:HIGH_PERFORMANCE_MODE[0, 32, 49]
OLOGIC0:INV.CLKDIV[0, 34, 13]
OLOGIC0:INV.D1[0, 32, 24]
OLOGIC0:INV.D2[0, 32, 23]
OLOGIC0:INV.D3[0, 35, 23]
OLOGIC0:INV.D4[0, 34, 20]
OLOGIC0:INV.D5[0, 34, 23]
OLOGIC0:INV.D6[0, 35, 25]
OLOGIC0:MISR_ENABLE[0, 28, 16]
OLOGIC0:MISR_ENABLE_FDBK[0, 29, 18]
OLOGIC0:MISR_RESET[0, 28, 15]
OLOGIC0:OFF_REV_USED[0, 34, 26]
OLOGIC0:OFF_SR_USED[0, 34, 27]
OLOGIC0:SERDES[0, 35, 20]
OLOGIC0:TFF_REV_USED[0, 34, 15]
OLOGIC0:TFF_SR_USED[0, 35, 15]
OLOGIC1:INV.CLKDIV[0, 34, 50]
OLOGIC1:INV.D1[0, 32, 39]
OLOGIC1:INV.D2[0, 32, 40]
OLOGIC1:INV.D3[0, 35, 40]
OLOGIC1:INV.D4[0, 34, 43]
OLOGIC1:INV.D5[0, 34, 40]
OLOGIC1:INV.D6[0, 35, 38]
OLOGIC1:MISR_ENABLE[0, 28, 47]
OLOGIC1:MISR_ENABLE_FDBK[0, 29, 45]
OLOGIC1:MISR_RESET[0, 28, 48]
OLOGIC1:OFF_REV_USED[0, 34, 37]
OLOGIC1:OFF_SR_USED[0, 34, 36]
OLOGIC1:SERDES[0, 35, 43]
OLOGIC1:TFF_REV_USED[0, 34, 48]
OLOGIC1:TFF_SR_USED[0, 35, 48]
Non-inverted[0]
ILOGIC0:INIT_CE[0, 28, 12][0, 28, 13]
ILOGIC1:INIT_CE[0, 28, 51][0, 28, 50]
OLOGIC0:TFF23_SRVAL[0, 35, 10][0, 34, 10]
OLOGIC1:TFF23_SRVAL[0, 35, 53][0, 34, 53]
Inverted~[1]~[0]
OLOGIC0:MISR_CLK_SELECT[0, 29, 16][0, 28, 17]
OLOGIC1:MISR_CLK_SELECT[0, 29, 47][0, 28, 46]
NONE00
CLK101
CLK210
ILOGIC0:BITSLIP_ENABLE[0, 31, 16][0, 29, 30][0, 29, 26][0, 29, 15][0, 29, 12][0, 28, 22][0, 28, 18]
ILOGIC1:BITSLIP_ENABLE[0, 31, 47][0, 29, 51][0, 29, 48][0, 29, 37][0, 29, 33][0, 28, 45][0, 28, 41]
Non-inverted[6][5][4][3][2][1][0]
ILOGIC0:MUX.CLK[0, 28, 21]
ILOGIC0:MUX.CLKB[0, 28, 20]
ICLK00
ICLK11
ILOGIC0:IFF1_INIT[0, 28, 26]
ILOGIC0:IFF1_SRVAL[0, 28, 24]
ILOGIC0:IFF2_INIT[0, 29, 20]
ILOGIC0:IFF2_SRVAL[0, 29, 22]
ILOGIC0:IFF3_INIT[0, 28, 27]
ILOGIC0:IFF3_SRVAL[0, 29, 28]
ILOGIC0:IFF4_INIT[0, 28, 31]
ILOGIC0:IFF4_SRVAL[0, 28, 29]
ILOGIC0:IFF_LATCH[0, 31, 20]
ILOGIC1:IFF1_INIT[0, 28, 37]
ILOGIC1:IFF1_SRVAL[0, 28, 39]
ILOGIC1:IFF2_INIT[0, 29, 43]
ILOGIC1:IFF2_SRVAL[0, 29, 41]
ILOGIC1:IFF3_INIT[0, 28, 36]
ILOGIC1:IFF3_SRVAL[0, 29, 35]
ILOGIC1:IFF4_INIT[0, 28, 32]
ILOGIC1:IFF4_SRVAL[0, 28, 34]
ILOGIC1:IFF_LATCH[0, 31, 43]
IOB0:DCIUPDATEMODE_ASREQUIRED[0, 37, 5]
IOB0:INV.I[0, 31, 23]
IOB1:DCIUPDATEMODE_ASREQUIRED[0, 37, 58]
IOB1:INV.I[0, 31, 40]
IODELAY0:INV.DATAIN[0, 30, 8]
IODELAY0:LEGIDELAY[0, 33, 9]
IODELAY1:INV.DATAIN[0, 30, 55]
IODELAY1:LEGIDELAY[0, 33, 54]
OLOGIC0:INV.CLK1[0, 33, 31]
OLOGIC0:INV.CLK2[0, 33, 30]
OLOGIC0:INV.T1[0, 32, 2]
OLOGIC0:INV.T2[0, 33, 3]
OLOGIC0:INV.T3[0, 34, 0]
OLOGIC0:INV.T4[0, 35, 0]
OLOGIC0:TFF1_SRVAL[0, 35, 12]
OLOGIC1:INV.CLK1[0, 33, 32]
OLOGIC1:INV.CLK2[0, 33, 33]
OLOGIC1:INV.T1[0, 32, 61]
OLOGIC1:INV.T2[0, 33, 60]
OLOGIC1:INV.T3[0, 34, 63]
OLOGIC1:INV.T4[0, 35, 63]
OLOGIC1:TFF1_SRVAL[0, 35, 51]
Inverted~[0]
ILOGIC1:MUX.CLK[0, 28, 42]
ILOGIC1:MUX.CLKB[0, 28, 43]
ICLK10
ICLK01
ILOGIC0:INIT_BITSLIPCNT[0, 29, 29][0, 28, 2][0, 28, 4][0, 29, 8]
ILOGIC1:INIT_BITSLIPCNT[0, 29, 34][0, 28, 61][0, 28, 59][0, 29, 55]
IODELAY0:ENABLE[0, 33, 16][0, 32, 20][0, 32, 18][0, 32, 8]
IODELAY1:ENABLE[0, 33, 47][0, 32, 55][0, 32, 45][0, 32, 43]
OLOGIC0:INIT_LOADCNT[0, 33, 29][0, 33, 23][0, 35, 27][0, 35, 24]
OLOGIC0:OFF_INIT[0, 35, 22][0, 33, 20][0, 33, 18][0, 32, 15]
OLOGIC1:INIT_LOADCNT[0, 33, 34][0, 33, 40][0, 35, 36][0, 35, 39]
OLOGIC1:OFF_INIT[0, 35, 41][0, 33, 45][0, 33, 43][0, 32, 48]
Inverted~[3]~[2]~[1]~[0]
ILOGIC0:DDR_CLK_EDGE[0, 28, 30][0, 29, 31]
ILOGIC1:DDR_CLK_EDGE[0, 28, 33][0, 29, 32]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
IODELAY0:DELAY_SRC[0, 31, 0][0, 31, 3][0, 30, 1][0, 30, 0]
IODELAY1:DELAY_SRC[0, 31, 63][0, 31, 60][0, 30, 62][0, 30, 63]
NONE0000
I0001
IO0011
O0110
DATAIN1000
IOI_CLK:MUX.ICLK0[0, 31, 14][0, 31, 11][0, 31, 18][0, 30, 6][0, 31, 1][0, 30, 2][0, 30, 3][0, 31, 4][0, 30, 4]
NONE000000000
HCLK0000100001
HCLK4000100010
HCLK8000100100
RCLK2000101000
IOCLK2000110000
HCLK1001000001
HCLK5001000010
HCLK9001000100
RCLK3001001000
IOCLK3001010000
HCLK2010000001
HCLK6010000010
RCLK0010000100
IOCLK0010001000
CKINT0010010000
HCLK3100000001
HCLK7100000010
RCLK1100000100
IOCLK1100001000
CKINT1100010000
ILOGIC0:DATA_WIDTH[0, 31, 5][0, 31, 8][0, 31, 7][0, 30, 5]
ILOGIC1:DATA_WIDTH[0, 31, 58][0, 31, 55][0, 31, 56][0, 30, 58]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
OLOGIC0:MUX.CLK[0, 30, 15][0, 31, 9][0, 30, 9][0, 30, 10][0, 30, 11][0, 31, 12][0, 30, 13][0, 31, 10][0, 30, 7]
OLOGIC1:MUX.CLK[0, 30, 48][0, 31, 54][0, 30, 54][0, 30, 53][0, 30, 52][0, 31, 51][0, 30, 50][0, 31, 53][0, 30, 56]
NONE000000000
HCLK0000100001
HCLK4000100010
HCLK8000100100
RCLK2000101000
IOCLK2000110000
HCLK1001000001
HCLK5001000010
HCLK9001000100
RCLK3001001000
IOCLK3001010000
HCLK2010000001
HCLK6010000010
RCLK0010000100
IOCLK0010001000
CKINT010010000
HCLK3100000001
HCLK7100000010
RCLK1100000100
IOCLK1100001000
ILOGIC0:TSBYPASS_MUX[0, 30, 16]
ILOGIC1:TSBYPASS_MUX[0, 30, 47]
T0
GND1
OLOGIC0:MUX.CLKDIV[0, 30, 18][0, 31, 13][0, 30, 23][0, 31, 21][0, 30, 21][0, 30, 20][0, 31, 19][0, 30, 19]
OLOGIC1:MUX.CLKDIV[0, 30, 45][0, 31, 50][0, 30, 40][0, 31, 42][0, 30, 42][0, 30, 43][0, 31, 44][0, 30, 44]
NONE00000000
HCLK000010001
HCLK400010010
HCLK800010100
RCLK200011000
HCLK100100001
HCLK500100010
HCLK900100100
RCLK300101000
HCLK201000001
HCLK601000010
RCLK001000100
CKINT01001000
HCLK310000001
HCLK710000010
RCLK110000100
ILOGIC0:NUM_CE[0, 30, 22]
ILOGIC1:NUM_CE[0, 30, 41]
10
21
IOI_CLK:INV.ICLK0[0, 31, 28][0, 30, 30][0, 30, 29]
IOI_CLK:INV.ICLK1[0, 31, 35][0, 30, 34][0, 30, 33]
OLOGIC0:OFF_INIT_SERDES[0, 33, 11][0, 33, 8][0, 32, 13]
OLOGIC0:OFF_SRVAL[0, 35, 31][0, 34, 31][0, 34, 30]
OLOGIC1:OFF_INIT_SERDES[0, 33, 55][0, 33, 52][0, 32, 50]
OLOGIC1:OFF_SRVAL[0, 35, 32][0, 34, 33][0, 34, 32]
Inverted~[2]~[1]~[0]
IOI_CLK:MUX.ICLK1[0, 31, 49][0, 31, 52][0, 31, 45][0, 30, 57][0, 31, 62][0, 30, 61][0, 30, 60][0, 31, 59][0, 30, 59]
NONE000000000
HCLK0000100001
HCLK4000100010
HCLK8000100100
RCLK2000101000
IOCLK2000110000
HCLK1001000001
HCLK5001000010
HCLK9001000100
RCLK3001001000
IOCLK3001010000
HCLK2010000001
HCLK6010000010
RCLK0010000100
IOCLK0010001000
CKINT1010010000
HCLK3100000001
HCLK7100000010
RCLK1100000100
IOCLK1100001000
CKINT0100010000
ILOGIC0:DATA_RATE[0, 31, 6]
ILOGIC1:DATA_RATE[0, 31, 57]
DDR0
SDR1
ILOGIC0:SERDES_MODE[0, 31, 15]
ILOGIC1:SERDES_MODE[0, 31, 48]
OLOGIC0:SERDES_MODE[0, 34, 5]
OLOGIC1:SERDES_MODE[0, 34, 58]
MASTER0
SLAVE1
ILOGIC0:INTERFACE_TYPE[0, 31, 25]
ILOGIC1:INTERFACE_TYPE[0, 31, 38]
MEMORY0
NETWORKING1
IOB0:DCI_MISC[0, 37, 26][0, 37, 16]
IOB0:OUTPUT_ENABLE[0, 36, 22][0, 36, 19]
IOB1:DCI_MISC[0, 37, 37][0, 37, 47]
IOB1:OUTPUT_ENABLE[0, 36, 44][0, 36, 41]
OLOGIC0:TFF_SR_SYNC[0, 34, 19][0, 32, 1]
OLOGIC1:TFF_SR_SYNC[0, 34, 44][0, 32, 62]
Non-inverted[1][0]
IOB0:NSLEW[0, 37, 20][0, 36, 26][0, 37, 28][0, 37, 31][0, 36, 27][0, 36, 31]
IOB0:OUTPUT_MISC[0, 37, 3][0, 36, 4][0, 36, 20][0, 37, 25][0, 37, 24][0, 36, 24]
IOB0:PSLEW[0, 37, 27][0, 37, 29][0, 37, 30][0, 37, 23][0, 36, 23][0, 37, 17]
IOB1:NSLEW[0, 37, 43][0, 36, 37][0, 37, 35][0, 37, 32][0, 36, 36][0, 36, 32]
IOB1:OUTPUT_MISC[0, 37, 60][0, 36, 59][0, 36, 43][0, 37, 38][0, 37, 39][0, 36, 39]
IOB1:PSLEW[0, 37, 36][0, 37, 34][0, 37, 33][0, 37, 40][0, 36, 40][0, 37, 46]
IODELAY0:IDELAY_VALUE_INIT[0, 32, 3][0, 32, 17][0, 33, 6][0, 32, 10][0, 32, 5][0, 32, 21]
IODELAY0:ODELAY_VALUE[0, 33, 13][0, 33, 17][0, 33, 21][0, 33, 22][0, 33, 15][0, 32, 7]
IODELAY1:IDELAY_VALUE_INIT[0, 32, 60][0, 32, 46][0, 33, 57][0, 32, 53][0, 32, 58][0, 32, 42]
IODELAY1:ODELAY_VALUE[0, 33, 50][0, 33, 46][0, 33, 42][0, 33, 41][0, 33, 48][0, 32, 56]
Non-inverted[5][4][3][2][1][0]
OLOGIC0:OFF_SERDES[0, 35, 13][0, 35, 6][0, 34, 11][0, 34, 2]
OLOGIC0:OFF_SR_SYNC[0, 35, 26][0, 34, 12][0, 33, 0][0, 32, 26]
OLOGIC1:OFF_SERDES[0, 35, 57][0, 35, 50][0, 34, 61][0, 34, 52]
OLOGIC1:OFF_SR_SYNC[0, 35, 37][0, 34, 51][0, 33, 63][0, 32, 37]
Non-inverted[3][2][1][0]
IODELAY0:IDELAY_TYPE[0, 33, 5][0, 33, 7]
IODELAY1:IDELAY_TYPE[0, 33, 58][0, 33, 56]
FIXED00
VARIABLE01
DEFAULT10
OLOGIC0:DATA_WIDTH[0, 32, 30][0, 32, 29][0, 34, 28][0, 35, 28][0, 32, 28][0, 32, 27][0, 33, 27][0, 33, 26]
OLOGIC1:DATA_WIDTH[0, 32, 33][0, 32, 34][0, 34, 35][0, 35, 35][0, 32, 35][0, 32, 36][0, 33, 36][0, 33, 37]
200000001
300000010
400000100
500001000
600010000
700100000
801000000
1010000000
OLOGIC0:TMUX[0, 35, 18][0, 34, 16][0, 34, 17][0, 35, 17][0, 35, 11]
OLOGIC1:TMUX[0, 35, 45][0, 34, 47][0, 34, 46][0, 35, 46][0, 35, 52]
NONE00000
T100001
DDR00100
SERDES_DDR00110
FF01010
LATCH11000
OLOGIC0:TRISTATE_WIDTH[0, 35, 19]
OLOGIC1:TRISTATE_WIDTH[0, 35, 44]
10
41
OLOGIC0:OMUX[0, 35, 29][0, 34, 29][0, 34, 6][0, 35, 5][0, 35, 30]
OLOGIC1:OMUX[0, 35, 34][0, 34, 34][0, 34, 57][0, 35, 58][0, 35, 33]
NONE00000
D100001
SERDES_SDR00010
SERDES_DDR00100
FF01010
DDR01100
LATCH10010
IOB0:NDRIVE[0, 36, 11][0, 36, 6][0, 37, 14][0, 37, 2][0, 36, 10]
IOB1:NDRIVE[0, 36, 52][0, 36, 57][0, 37, 49][0, 37, 61][0, 36, 53]
Mixed inversion[4][3]~[2]~[1]~[0]
IOB0:PDRIVE[0, 37, 10][0, 37, 9][0, 37, 13][0, 37, 0][0, 36, 14]
IOB1:PDRIVE[0, 37, 53][0, 37, 54][0, 37, 50][0, 37, 63][0, 36, 49]
Mixed inversion[4]~[3][2][1]~[0]
IOB0:PULL[0, 37, 19][0, 36, 15][0, 36, 16]
IOB1:PULL[0, 37, 44][0, 36, 48][0, 36, 47]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DCI_MODE[0, 37, 8][0, 36, 8][0, 37, 7]
IOB1:DCI_MODE[0, 37, 55][0, 36, 55][0, 37, 56]
NONE000
OUTPUT001
OUTPUT_HALF010
TERM_VCC011
TERM_SPLIT100
IOB0:LVDS[0, 36, 5][0, 37, 22][0, 37, 21][0, 36, 21][0, 36, 18][0, 36, 17][0, 37, 15][0, 36, 13][0, 37, 11]
IOB1:LVDS[0, 36, 58][0, 37, 41][0, 37, 42][0, 36, 42][0, 36, 45][0, 36, 46][0, 37, 48][0, 36, 50][0, 37, 52]
Non-inverted[8][7][6][5][4][3][2][1][0]
IOB0:IBUF_MODE[0, 36, 29][0, 36, 25][0, 37, 18]
IOB1:IBUF_MODE[0, 36, 34][0, 36, 38][0, 37, 45]
OFF000
VREF001
DIFF010
CMOS111

Tables

NameIOSTD:PDRIVEIOSTD:NDRIVE
[4][3][2][1][0][4][3][2][1][0]
BLVDS_251111110111
GTL0000010011
GTLP0000010000
GTLP_DCI0000010000
GTL_DCI0000010011
HSTL_I0110100101
HSTL_II1101001010
HSTL_III0110101111
HSTL_III_180111010010
HSTL_III_DCI0110101111
HSTL_III_DCI_180111010010
HSTL_II_181101101101
HSTL_II_DCI1101001010
HSTL_II_DCI_181101101101
HSTL_II_T_DCI0110100101
HSTL_II_T_DCI_180111000111
HSTL_IV0110111110
HSTL_IV_180111011111
HSTL_IV_DCI0110111110
HSTL_IV_DCI_180111011111
HSTL_I_121101000110
HSTL_I_180111000111
HSTL_I_DCI0110100101
HSTL_I_DCI_180111000111
LVCMOS12.20011100010
LVCMOS12.40111000100
LVCMOS12.61001100101
LVCMOS12.81101001001
LVCMOS15.121011001000
LVCMOS15.161110001010
LVCMOS15.20011000010
LVCMOS15.40100000011
LVCMOS15.60100100100
LVCMOS15.80110100101
LVCMOS18.120110100110
LVCMOS18.161001101001
LVCMOS18.20001100001
LVCMOS18.40010100010
LVCMOS18.60011100011
LVCMOS18.80100000100
LVCMOS25.120100100111
LVCMOS25.160111001010
LVCMOS25.20001100010
LVCMOS25.241010101111
LVCMOS25.40010100011
LVCMOS25.60011000100
LVCMOS25.80011100101
LVCMOS33.120100001000
LVCMOS33.160101001010
LVCMOS33.20001000010
LVCMOS33.241000110000
LVCMOS33.40001100011
LVCMOS33.60010000100
LVCMOS33.80011000101
LVPECL_251100011110
LVTTL.120100001000
LVTTL.160101001010
LVTTL.20001000010
LVTTL.241000110000
LVTTL.40001100011
LVTTL.60010000100
LVTTL.80011000101
OFF0000000000
PCI33_30101001101
PCI66_30101001101
PCIX0110001100
SSTL18_I0100000100
SSTL18_II1100001100
SSTL18_II_DCI0111000110
SSTL18_II_T_DCI0011100011
SSTL18_I_DCI0011100011
SSTL2_I0011000100
SSTL2_II1001101101
SSTL2_II_DCI0100000110
SSTL2_II_T_DCI0010100011
SSTL2_I_DCI0010100011
VR0000000000
NameIOSTD:PSLEWIOSTD:NSLEW
[5][4][3][2][1][0][5][4][3][2][1][0]
BLVDS_25111111101111
GTL000000010101
GTLP000000010101
GTLP_DCI000000111111
GTL_DCI000000111111
HSLVDCI_15111111000010
HSLVDCI_18111111000000
HSLVDCI_25111111001111
HSLVDCI_33111111111111
HSTL_I111111001101
HSTL_II111111001010
HSTL_III111111010000
HSTL_III_18111111010000
HSTL_III_DCI000110110001
HSTL_III_DCI_18000100011001
HSTL_II_18111111010010
HSTL_II_DCI101110001001
HSTL_II_DCI_18101110101101
HSTL_II_T_DCI011111001010
HSTL_II_T_DCI_18011111101110
HSTL_IV111111010010
HSTL_IV_18111111011000
HSTL_IV_DCI000000111101
HSTL_IV_DCI_18001111111111
HSTL_I_12111111001010
HSTL_I_18111111001111
HSTL_I_DCI011111001010
HSTL_I_DCI_18011111101110
LVCMOS12.2.FAST111111000111
LVCMOS12.2.SLOW000101000000
LVCMOS12.4.FAST111111000111
LVCMOS12.4.SLOW000101000000
LVCMOS12.6.FAST111111000111
LVCMOS12.6.SLOW000101000000
LVCMOS12.8.FAST111111000111
LVCMOS12.8.SLOW000101000000
LVCMOS15.12.FAST111111000111
LVCMOS15.12.SLOW000101000000
LVCMOS15.16.FAST111111001010
LVCMOS15.16.SLOW000101000000
LVCMOS15.2.FAST111111000111
LVCMOS15.2.SLOW000101000000
LVCMOS15.4.FAST111111000111
LVCMOS15.4.SLOW000101000000
LVCMOS15.6.FAST111111000111
LVCMOS15.6.SLOW000101000000
LVCMOS15.8.FAST111111000111
LVCMOS15.8.SLOW000101000000
LVCMOS18.12.FAST111111010011
LVCMOS18.12.SLOW000001000001
LVCMOS18.16.FAST111111001111
LVCMOS18.16.SLOW000001000000
LVCMOS18.2.FAST011111111111
LVCMOS18.2.SLOW000001000011
LVCMOS18.4.FAST111111111000
LVCMOS18.4.SLOW000001000101
LVCMOS18.6.FAST111111001111
LVCMOS18.6.SLOW000001000001
LVCMOS18.8.FAST111111001111
LVCMOS18.8.SLOW000001000001
LVCMOS25.12.FAST111111100000
LVCMOS25.12.SLOW000000000000
LVCMOS25.16.FAST111111100000
LVCMOS25.16.SLOW000001000010
LVCMOS25.2.FAST011111001111
LVCMOS25.2.SLOW000000001010
LVCMOS25.24.FAST111111100000
LVCMOS25.24.SLOW000001000000
LVCMOS25.4.FAST111111101000
LVCMOS25.4.SLOW000001000011
LVCMOS25.6.FAST111111100000
LVCMOS25.6.SLOW000001000010
LVCMOS25.8.FAST111111010001
LVCMOS25.8.SLOW000001000010
LVCMOS33.12.FAST111111111111
LVCMOS33.12.SLOW000001000011
LVCMOS33.16.FAST111111111111
LVCMOS33.16.SLOW000001000011
LVCMOS33.2.FAST111111111111
LVCMOS33.2.SLOW000001000100
LVCMOS33.24.FAST111111111111
LVCMOS33.24.SLOW000001000001
LVCMOS33.4.FAST111111111111
LVCMOS33.4.SLOW000001000101
LVCMOS33.6.FAST111111100000
LVCMOS33.6.SLOW000001000010
LVCMOS33.8.FAST011111111111
LVCMOS33.8.SLOW000001000100
LVDCI_15111111000010
LVDCI_18111111000000
LVDCI_25111111001111
LVDCI_33111111111111
LVDCI_DV2_15111111000011
LVDCI_DV2_18111111000111
LVDCI_DV2_25111111011101
LVPECL_25111111001111
LVTTL.12.FAST111111111111
LVTTL.12.SLOW000001000011
LVTTL.16.FAST111111111111
LVTTL.16.SLOW000001000011
LVTTL.2.FAST111111111111
LVTTL.2.SLOW000001000100
LVTTL.24.FAST111111111111
LVTTL.24.SLOW000001000001
LVTTL.4.FAST111111111111
LVTTL.4.SLOW000001000101
LVTTL.6.FAST111111100000
LVTTL.6.SLOW000001000010
LVTTL.8.FAST011111111111
LVTTL.8.SLOW000001000100
OFF000000000000
PCI33_3000000000000
PCI66_3000000000000
PCIX001111100000
SSTL18_I111111010011
SSTL18_II111111001111
SSTL18_II_DCI111111111111
SSTL18_II_T_DCI001111110000
SSTL18_I_DCI001111110000
SSTL2_I111111010011
SSTL2_II111111001111
SSTL2_II_DCI111011001101
SSTL2_II_T_DCI111111010101
SSTL2_I_DCI111111010101
VR111111111111
NameIOSTD:OUTPUT_MISC
[5][4][3][2][1][0]
BLVDS_25011000
GTL000000
GTLP000000
GTLP_DCI100000
GTL_DCI100001
HSLVDCI_15100000
HSLVDCI_18100000
HSLVDCI_25000000
HSLVDCI_33000000
HSTL_I110000
HSTL_II110000
HSTL_III110000
HSTL_III_18100000
HSTL_III_DCI100000
HSTL_III_DCI_18100000
HSTL_II_18100000
HSTL_II_DCI100000
HSTL_II_DCI_18100000
HSTL_II_T_DCI100000
HSTL_II_T_DCI_18100000
HSTL_IV100000
HSTL_IV_18100000
HSTL_IV_DCI100000
HSTL_IV_DCI_18100010
HSTL_I_12111000
HSTL_I_18100000
HSTL_I_DCI100000
HSTL_I_DCI_18100000
LVCMOS12111000
LVCMOS15111000
LVCMOS18100000
LVCMOS25000000
LVCMOS33000000
LVDCI_15100000
LVDCI_18100000
LVDCI_25000000
LVDCI_33000000
LVDCI_DV2_15100000
LVDCI_DV2_18100000
LVDCI_DV2_25000000
LVPECL_25011000
LVTTL000000
OFF000000
PCI33_3000000
PCI66_3000000
PCIX000000
SSTL18_I100000
SSTL18_II100000
SSTL18_II_DCI100000
SSTL18_II_T_DCI100000
SSTL18_I_DCI100000
SSTL2_I000000
SSTL2_II000000
SSTL2_II_DCI000000
SSTL2_II_T_DCI000000
SSTL2_I_DCI000000
NameIOSTD:LVDS_TIOSTD:LVDS_C
[8][7][6][5][4][3][2][1][0][8][7][6][5][4][3][2][1][0]
OFF000000000000000000
OUTPUT_HT_25101000000001100011
OUTPUT_LVDSEXT_25110000000001000101
OUTPUT_LVDS_25100000000001100011
OUTPUT_RSDS_25100000000001100011
TERM_HT_25000000000101100011
TERM_LVDSEXT_25000000000101100011
TERM_LVDS_25000000000101100011
TERM_RSDS_25000000000101100011
DeviceIODELAY:DEFAULT_IDELAY_VALUE
[5][4][3][2][1][0]
xc5vfx100t110010
xc5vfx130t110111
xc5vfx200t111000
xc5vfx30t100111
xc5vfx70t101100
xc5vlx110101100
xc5vlx110t101100
xc5vlx155110010
xc5vlx155t110010
xc5vlx20t100111
xc5vlx220111000
xc5vlx220t111000
xc5vlx30100111
xc5vlx30t100111
xc5vlx330111000
xc5vlx330t111000
xc5vlx50100111
xc5vlx50t100111
xc5vlx85101100
xc5vlx85t101100
xc5vsx240t111000
xc5vsx35t100111
xc5vsx50t101011
xc5vsx95t110010
xc5vtx150t110111
xc5vtx240t111000
xq5vfx100t110010
xq5vfx130t110111
xq5vfx200t111000
xq5vfx70t101100
xq5vlx110101100
xq5vlx110t101100
xq5vlx155t110010
xq5vlx220t111000
xq5vlx30t100111
xq5vlx330t111000
xq5vlx85101100
xq5vsx240t111000
xq5vsx50t101011
xq5vsx95t110010