Clock management tile

Todo

describe this madness

CMT

CMT bittile 0
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP7F[15]MMCM:DRP7F[14]
1 ----------------------------MMCM:DRP7F[13]MMCM:DRP7F[12]
2 ----------------------------MMCM:DRP7F[11]MMCM:DRP7F[10]
3 ----------------------------MMCM:DRP7F[9]MMCM:DRP7F[8]
4 ----------------------------MMCM:DRP7F[7]MMCM:DRP7F[6]
5 ----------------------------MMCM:DRP7F[5]MMCM:DRP7F[4]
6 ----------------------------MMCM:DRP7F[3]MMCM:DRP7F[2]
7 ----------------------------MMCM:DRP7F[1]MMCM:DRP7F[0]
8 ----------------------------MMCM:DRP7E[15]MMCM:DRP7E[14]
9 ----------------------------MMCM:DRP7E[13]MMCM:DRP7E[12]
10 ----------------------------MMCM:DRP7E[11]MMCM:DRP7E[10]
11 ----------------------------MMCM:DRP7E[9]MMCM:DRP7E[8]
12 ----------------------------MMCM:DRP7E[7]MMCM:DRP7E[6]
13 ----------------------------MMCM:DRP7E[5]MMCM:DRP7E[4]
14 ----------------------------MMCM:DRP7E[3]MMCM:DRP7E[2]
15 ----------------------------MMCM:DRP7E[1]MMCM:DRP7E[0]
16 ----------------------------MMCM:CONTROL_7[15]
MMCM:DRP7D[15]		MMCM:CONTROL_7[14]
MMCM:DRP7D[14]
17 ----------------------------MMCM:CONTROL_7[13]
MMCM:DRP7D[13]		MMCM:CONTROL_7[12]
MMCM:DRP7D[12]
18 ----------------------------MMCM:CONTROL_7[11]
MMCM:DRP7D[11]		MMCM:CONTROL_7[10]
MMCM:DRP7D[10]
19 ----------------------------MMCM:CONTROL_7[9]
MMCM:DRP7D[9]		MMCM:CONTROL_7[8]
MMCM:DRP7D[8]
20 ----------------------------MMCM:CONTROL_7[7]
MMCM:DRP7D[7]		MMCM:CONTROL_7[6]
MMCM:DRP7D[6]
21 ----------------------------MMCM:CONTROL_7[5]
MMCM:DRP7D[5]		MMCM:CONTROL_7[4]
MMCM:DRP7D[4]
22 ----------------------------MMCM:CONTROL_7[3]
MMCM:DRP7D[3]		MMCM:CONTROL_7[2]
MMCM:DRP7D[2]
23 ----------------------------MMCM:CONTROL_7[1]
MMCM:DRP7D[1]		MMCM:CONTROL_7[0]
MMCM:DRP7D[0]
24 ----------------------------MMCM:CONTROL_6[15]
MMCM:DRP7C[15]		MMCM:CONTROL_6[14]
MMCM:DRP7C[14]
25 ----------------------------MMCM:CONTROL_6[13]
MMCM:DRP7C[13]		MMCM:CONTROL_6[12]
MMCM:DRP7C[12]
26 ----------------------------MMCM:CONTROL_6[11]
MMCM:DRP7C[11]		MMCM:CONTROL_6[10]
MMCM:DRP7C[10]
27 ----------------------------MMCM:CONTROL_6[9]
MMCM:DRP7C[9]		MMCM:CONTROL_6[8]
MMCM:DRP7C[8]
28 ----------------------------MMCM:CONTROL_6[7]
MMCM:DRP7C[7]		MMCM:CONTROL_6[6]
MMCM:DRP7C[6]
29 ----------------------------MMCM:CONTROL_6[5]
MMCM:DRP7C[5]		MMCM:CONTROL_6[4]
MMCM:DRP7C[4]
30 ----------------------------MMCM:CONTROL_6[3]
MMCM:DRP7C[3]		MMCM:CONTROL_6[2]
MMCM:DRP7C[2]
31 ----------------------------MMCM:CONTROL_6[1]
MMCM:DRP7C[1]		MMCM:CONTROL_6[0]
MMCM:DRP7C[0]
32 ----------------------------MMCM:CONTROL_5[15]
MMCM:DRP7B[15]		MMCM:CONTROL_5[14]
MMCM:DRP7B[14]
33 ----------------------------MMCM:CONTROL_5[13]
MMCM:DRP7B[13]		MMCM:CONTROL_5[12]
MMCM:DRP7B[12]
34 ----------------------------MMCM:CONTROL_5[11]
MMCM:DRP7B[11]		MMCM:CONTROL_5[10]
MMCM:DRP7B[10]
35 ----------------------------MMCM:CONTROL_5[9]
MMCM:DRP7B[9]		MMCM:CONTROL_5[8]
MMCM:DRP7B[8]
36 ----------------------------MMCM:CONTROL_5[7]
MMCM:DRP7B[7]		MMCM:CONTROL_5[6]
MMCM:DRP7B[6]
37 ----------------------------MMCM:CONTROL_5[5]
MMCM:DRP7B[5]		MMCM:CONTROL_5[4]
MMCM:DRP7B[4]
38 ----------------------------MMCM:CONTROL_5[3]
MMCM:DRP7B[3]		MMCM:CONTROL_5[2]
MMCM:DRP7B[2]
39 ----------------------------MMCM:CONTROL_5[1]
MMCM:DRP7B[1]		MMCM:CONTROL_5[0]
MMCM:DRP7B[0]
40 ----------------------------MMCM:CONTROL_4[15]
MMCM:DRP7A[15]		MMCM:CONTROL_4[14]
MMCM:DRP7A[14]
41 ----------------------------MMCM:CONTROL_4[13]
MMCM:DRP7A[13]		MMCM:CONTROL_4[12]
MMCM:DRP7A[12]
42 ----------------------------MMCM:CONTROL_4[11]
MMCM:DRP7A[11]		MMCM:CONTROL_4[10]
MMCM:DRP7A[10]
43 ----------------------------MMCM:CONTROL_4[9]
MMCM:DRP7A[9]		MMCM:CONTROL_4[8]
MMCM:DRP7A[8]
44 ----------------------------MMCM:CONTROL_4[7]
MMCM:DRP7A[7]		MMCM:CONTROL_4[6]
MMCM:DRP7A[6]
45 ----------------------------MMCM:CONTROL_4[5]
MMCM:DRP7A[5]		MMCM:CONTROL_4[4]
MMCM:DRP7A[4]
46 ----------------------------MMCM:CONTROL_4[3]
MMCM:DRP7A[3]		MMCM:CONTROL_4[2]
MMCM:DRP7A[2]
47 ----------------------------MMCM:CONTROL_4[1]
MMCM:DRP7A[1]		MMCM:CONTROL_4[0]
MMCM:DRP7A[0]
48 ----------------------------MMCM:CONTROL_3[15]
MMCM:DRP79[15]		MMCM:CONTROL_3[14]
MMCM:DRP79[14]
49 ----------------------------MMCM:CONTROL_3[13]
MMCM:DRP79[13]		MMCM:CONTROL_3[12]
MMCM:DRP79[12]
50 ----------------------------MMCM:CONTROL_3[11]
MMCM:DRP79[11]		MMCM:CONTROL_3[10]
MMCM:DRP79[10]
51 ----------------------------MMCM:CONTROL_3[9]
MMCM:DRP79[9]		MMCM:CONTROL_3[8]
MMCM:DRP79[8]
52 ----------------------------MMCM:CONTROL_3[7]
MMCM:DRP79[7]		MMCM:CONTROL_3[6]
MMCM:DRP79[6]
53 ----------------------------MMCM:CONTROL_3[5]
MMCM:DRP79[5]		MMCM:CONTROL_3[4]
MMCM:DRP79[4]
54 ----------------------------MMCM:CONTROL_3[3]
MMCM:DRP79[3]		MMCM:CONTROL_3[2]
MMCM:DRP79[2]
55 ----------------------------MMCM:CONTROL_3[1]
MMCM:DRP79[1]		MMCM:CONTROL_3[0]
MMCM:DRP79[0]
56 ----------------------------MMCM:CONTROL_2[15]
MMCM:DRP78[15]		MMCM:CONTROL_2[14]
MMCM:DRP78[14]
57 ----------------------------MMCM:CONTROL_2[13]
MMCM:DRP78[13]		MMCM:CONTROL_2[12]
MMCM:DRP78[12]
58 ----------------------------MMCM:CONTROL_2[11]
MMCM:DRP78[11]		MMCM:CONTROL_2[10]
MMCM:DRP78[10]
59 ----------------------------MMCM:CONTROL_2[9]
MMCM:DRP78[9]		MMCM:CONTROL_2[8]
MMCM:DRP78[8]
60 ----------------------------MMCM:CONTROL_2[7]
MMCM:DRP78[7]		MMCM:CONTROL_2[6]
MMCM:DRP78[6]
61 ----------------------------MMCM:CONTROL_2[5]
MMCM:DRP78[5]		MMCM:CONTROL_2[4]
MMCM:DRP78[4]
62 ----------------------------MMCM:CONTROL_2[3]
MMCM:DRP78[3]		MMCM:CONTROL_2[2]
MMCM:DRP78[2]
63 ----------------------------MMCM:CONTROL_2[1]
MMCM:DRP78[1]		MMCM:CONTROL_2[0]
MMCM:DRP78[0]
CMT bittile 1
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:CONTROL_1[15]
MMCM:DRP77[15]		MMCM:CONTROL_1[14]
MMCM:DRP77[14]
1 ----------------------------MMCM:CONTROL_1[13]
MMCM:DRP77[13]		MMCM:CONTROL_1[12]
MMCM:DRP77[12]
2 ----------------------------MMCM:CONTROL_1[11]
MMCM:DRP77[11]		MMCM:CONTROL_1[10]
MMCM:DRP77[10]
3 ----------------------------MMCM:CONTROL_1[9]
MMCM:DRP77[9]		MMCM:CONTROL_1[8]
MMCM:DRP77[8]
4 ----------------------------MMCM:CONTROL_1[7]
MMCM:DRP77[7]		MMCM:CONTROL_1[6]
MMCM:DRP77[6]
5 ----------------------------MMCM:CONTROL_1[5]
MMCM:DRP77[5]		MMCM:CONTROL_1[4]
MMCM:DRP77[4]
6 ----------------------------MMCM:CONTROL_1[3]
MMCM:DRP77[3]		MMCM:CONTROL_1[2]
MMCM:DRP77[2]
7 ----------------------------MMCM:CONTROL_1[1]
MMCM:DRP77[1]		MMCM:CONTROL_1[0]
MMCM:DRP77[0]
8 ----------------------------MMCM:CONTROL_0[15]
MMCM:DRP76[15]		MMCM:CONTROL_0[14]
MMCM:DRP76[14]
9 ----------------------------MMCM:CONTROL_0[13]
MMCM:DRP76[13]		MMCM:CONTROL_0[12]
MMCM:DRP76[12]
10 ----------------------------MMCM:CONTROL_0[11]
MMCM:DRP76[11]		MMCM:CONTROL_0[10]
MMCM:DRP76[10]
11 ----------------------------MMCM:CONTROL_0[9]
MMCM:DRP76[9]		MMCM:CONTROL_0[8]
MMCM:DRP76[8]
12 ----------------------------MMCM:CONTROL_0[7]
MMCM:DRP76[7]		MMCM:CONTROL_0[6]
MMCM:DRP76[6]
13 ----------------------------MMCM:CONTROL_0[5]
MMCM:DRP76[5]		MMCM:CONTROL_0[4]
MMCM:DRP76[4]
14 ----------------------------MMCM:CONTROL_0[3]
MMCM:DRP76[3]		MMCM:CONTROL_0[2]
MMCM:DRP76[2]
15 ----------------------------MMCM:CONTROL_0[1]
MMCM:DRP76[1]		MMCM:CONTROL_0[0]
MMCM:DRP76[0]
16 ----------------------------MMCM:DRP75[15]MMCM:DRP75[14]
17 ----------------------------MMCM:DRP75[13]MMCM:DRP75[12]
18 ----------------------------MMCM:DRP75[11]MMCM:DRP75[10]
19 ----------------------------MMCM:DRP75[9]MMCM:DRP75[8]
20 ----------------------------MMCM:DRP75[7]MMCM:DRP75[6]
21 ----------------------------MMCM:DRP75[5]MMCM:DRP75[4]
22 ----------------------------MMCM:DRP75[3]MMCM:DRP75[2]
23 ----------------------------MMCM:DRP75[1]MMCM:DRP75[0]
24 ----------------------------MMCM:DRP74[15]MMCM:DRP74[14]
25 ----------------------------MMCM:DRP74[13]MMCM:DRP74[12]
26 ----------------------------MMCM:DRP74[11]MMCM:DRP74[10]
MMCM:FINE_PS_FRAC[5]
27 ----------------------------MMCM:DRP74[9]
MMCM:FINE_PS_FRAC[4]		MMCM:DRP74[8]
MMCM:FINE_PS_FRAC[3]
28 ----------------------------MMCM:DRP74[7]
MMCM:FINE_PS_FRAC[2]		MMCM:DRP74[6]
MMCM:FINE_PS_FRAC[1]
29 ----------------------------MMCM:DRP74[5]
MMCM:FINE_PS_FRAC[0]		MMCM:DRP74[4]
30 ----------------------------MMCM:DRP74[3]
MMCM:GTS_WAIT		MMCM:DRP74[2]
MMCM:STARTUP_WAIT
31 ----------------------------MMCM:DRP74[1]
MMCM:SS_EN		MMCM:DRP74[0]
MMCM:MMCM_EN
32 ----------------------------MMCM:DRP73[15]MMCM:DRP73[14]
33 ----------------------------MMCM:DRP73[13]MMCM:DRP73[12]
34 ----------------------------MMCM:DRP73[11]MMCM:DRP73[10]
35 ----------------------------MMCM:DRP73[9]MMCM:DRP73[8]
36 ----------------------------MMCM:DRP73[7]MMCM:DRP73[6]
37 ----------------------------MMCM:DRP73[5]MMCM:DRP73[4]
38 ----------------------------MMCM:DRP73[3]MMCM:DRP73[2]
39 ----------------------------MMCM:DRP73[1]MMCM:DRP73[0]
40 ----------------------------MMCM:DRP72[15]MMCM:DRP72[14]
41 ----------------------------MMCM:DRP72[13]MMCM:DRP72[12]
42 ----------------------------MMCM:DRP72[11]MMCM:DRP72[10]
43 ----------------------------MMCM:DRP72[9]MMCM:DRP72[8]
44 ----------------------------MMCM:DRP72[7]MMCM:DRP72[6]
45 ----------------------------MMCM:DRP72[5]MMCM:DRP72[4]
MMCM:INV.CLKINSEL
46 ----------------------------MMCM:DRP72[3]
MMCM:INV.PSEN		MMCM:DRP72[2]
MMCM:INV.PSINCDEC
47 ----------------------------MMCM:DRP72[1]
MMCM:INV.PWRDWN		MMCM:DRP72[0]
MMCM:INV.RST
48 ----------------------------MMCM:DRP71[15]MMCM:DRP71[14]
49 ----------------------------MMCM:DRP71[13]MMCM:DRP71[12]
50 ----------------------------MMCM:DRP71[11]MMCM:DRP71[10]
51 ----------------------------MMCM:DRP71[9]MMCM:DRP71[8]
52 ----------------------------MMCM:DRP71[7]MMCM:DRP71[6]
53 ----------------------------MMCM:DRP71[5]MMCM:DRP71[4]
54 ----------------------------MMCM:DRP71[3]MMCM:DRP71[2]
55 ----------------------------MMCM:DRP71[1]MMCM:DRP71[0]
56 ----------------------------MMCM:DRP70[15]MMCM:DRP70[14]
57 ----------------------------MMCM:DRP70[13]MMCM:DRP70[12]
58 ----------------------------MMCM:DRP70[11]MMCM:DRP70[10]
59 ----------------------------MMCM:DRP70[9]MMCM:DRP70[8]
60 ----------------------------MMCM:DRP70[7]MMCM:DRP70[6]
61 ----------------------------MMCM:DRP70[5]MMCM:DRP70[4]
62 ----------------------------MMCM:DRP70[3]MMCM:DRP70[2]
63 ----------------------------MMCM:DRP70[1]MMCM:DRP70[0]
CMT bittile 2
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP6F[15]MMCM:DRP6F[14]
1 ----------------------------MMCM:DRP6F[13]MMCM:DRP6F[12]
2 ----------------------------MMCM:DRP6F[11]MMCM:DRP6F[10]
3 ----------------------------MMCM:DRP6F[9]MMCM:DRP6F[8]
4 ----------------------------MMCM:DRP6F[7]MMCM:DRP6F[6]
5 ----------------------------MMCM:DRP6F[5]MMCM:DRP6F[4]
6 ----------------------------MMCM:DRP6F[3]MMCM:DRP6F[2]
7 ----------------------------MMCM:DRP6F[1]MMCM:DRP6F[0]
8 ----------------------------MMCM:DRP6E[15]MMCM:DRP6E[14]
9 ----------------------------MMCM:DRP6E[13]MMCM:DRP6E[12]
10 ----------------------------MMCM:DRP6E[11]MMCM:DRP6E[10]
11 ----------------------------MMCM:DRP6E[9]MMCM:DRP6E[8]
12 ----------------------------MMCM:DRP6E[7]MMCM:DRP6E[6]
13 ----------------------------MMCM:DRP6E[5]MMCM:DRP6E[4]
14 ----------------------------MMCM:DRP6E[3]MMCM:DRP6E[2]
15 ----------------------------MMCM:DRP6E[1]MMCM:DRP6E[0]
16 ----------------------------MMCM:DRP6D[15]MMCM:DRP6D[14]
17 ----------------------------MMCM:DRP6D[13]MMCM:DRP6D[12]
18 ----------------------------MMCM:DRP6D[11]MMCM:DRP6D[10]
19 ----------------------------MMCM:DRP6D[9]MMCM:DRP6D[8]
20 ----------------------------MMCM:DRP6D[7]MMCM:DRP6D[6]
21 ----------------------------MMCM:DRP6D[5]MMCM:DRP6D[4]
22 ----------------------------MMCM:DRP6D[3]MMCM:DRP6D[2]
23 ----------------------------MMCM:DRP6D[1]MMCM:DRP6D[0]
24 ----------------------------MMCM:DRP6C[15]MMCM:DRP6C[14]
25 ----------------------------MMCM:DRP6C[13]MMCM:DRP6C[12]
26 ----------------------------MMCM:DRP6C[11]MMCM:DRP6C[10]
27 ----------------------------MMCM:DRP6C[9]MMCM:DRP6C[8]
28 ----------------------------MMCM:DRP6C[7]MMCM:DRP6C[6]
29 ----------------------------MMCM:DRP6C[5]MMCM:DRP6C[4]
30 ----------------------------MMCM:DRP6C[3]MMCM:DRP6C[2]
31 ----------------------------MMCM:DRP6C[1]MMCM:DRP6C[0]
32 ----------------------------MMCM:DRP6B[15]MMCM:DRP6B[14]
33 ----------------------------MMCM:DRP6B[13]MMCM:DRP6B[12]
34 ----------------------------MMCM:DRP6B[11]MMCM:DRP6B[10]
35 ----------------------------MMCM:DRP6B[9]MMCM:DRP6B[8]
36 ----------------------------MMCM:DRP6B[7]MMCM:DRP6B[6]
37 ----------------------------MMCM:DRP6B[5]MMCM:DRP6B[4]
38 ----------------------------MMCM:DRP6B[3]MMCM:DRP6B[2]
39 ----------------------------MMCM:DRP6B[1]MMCM:DRP6B[0]
40 ----------------------------MMCM:DRP6A[15]MMCM:DRP6A[14]
41 ----------------------------MMCM:DRP6A[13]MMCM:DRP6A[12]
42 ----------------------------MMCM:DRP6A[11]MMCM:DRP6A[10]
43 ----------------------------MMCM:DRP6A[9]MMCM:DRP6A[8]
44 ----------------------------MMCM:DRP6A[7]MMCM:DRP6A[6]
45 ----------------------------MMCM:DRP6A[5]MMCM:DRP6A[4]
46 ----------------------------MMCM:DRP6A[3]MMCM:DRP6A[2]
47 ----------------------------MMCM:DRP6A[1]MMCM:DRP6A[0]
48 ----------------------------MMCM:DRP69[15]MMCM:DRP69[14]
49 ----------------------------MMCM:DRP69[13]MMCM:DRP69[12]
50 ----------------------------MMCM:DRP69[11]MMCM:DRP69[10]
51 ----------------------------MMCM:DRP69[9]MMCM:DRP69[8]
52 ----------------------------MMCM:DRP69[7]MMCM:DRP69[6]
53 ----------------------------MMCM:DRP69[5]MMCM:DRP69[4]
54 ----------------------------MMCM:DRP69[3]MMCM:DRP69[2]
55 ----------------------------MMCM:DRP69[1]MMCM:DRP69[0]
56 ----------------------------MMCM:DRP68[15]MMCM:DRP68[14]
57 ----------------------------MMCM:DRP68[13]MMCM:DRP68[12]
58 ----------------------------MMCM:DRP68[11]MMCM:DRP68[10]
59 ----------------------------MMCM:DRP68[9]MMCM:DRP68[8]
60 ----------------------------MMCM:DRP68[7]MMCM:DRP68[6]
61 ----------------------------MMCM:DRP68[5]MMCM:DRP68[4]
62 ----------------------------MMCM:DRP68[3]MMCM:DRP68[2]
63 ----------------------------MMCM:DRP68[1]MMCM:DRP68[0]
CMT bittile 3
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP67[15]MMCM:DRP67[14]
1 ----------------------------MMCM:DRP67[13]MMCM:DRP67[12]
2 ----------------------------MMCM:DRP67[11]MMCM:DRP67[10]
3 ----------------------------MMCM:DRP67[9]MMCM:DRP67[8]
4 ----------------------------MMCM:DRP67[7]MMCM:DRP67[6]
5 ----------------------------MMCM:DRP67[5]MMCM:DRP67[4]
6 ----------------------------MMCM:DRP67[3]MMCM:DRP67[2]
7 ----------------------------MMCM:DRP67[1]MMCM:DRP67[0]
8 ----------------------------MMCM:DRP66[15]MMCM:DRP66[14]
9 ----------------------------MMCM:DRP66[13]MMCM:DRP66[12]
10 ----------------------------MMCM:DRP66[11]MMCM:DRP66[10]
11 ----------------------------MMCM:DRP66[9]MMCM:DRP66[8]
12 ----------------------------MMCM:DRP66[7]MMCM:DRP66[6]
13 ----------------------------MMCM:DRP66[5]MMCM:DRP66[4]
14 ----------------------------MMCM:DRP66[3]MMCM:DRP66[2]
15 ----------------------------MMCM:DRP66[1]MMCM:DRP66[0]
16 ----------------------------MMCM:DRP65[15]MMCM:DRP65[14]
17 ----------------------------MMCM:DRP65[13]MMCM:DRP65[12]
18 ----------------------------MMCM:DRP65[11]MMCM:DRP65[10]
19 ----------------------------MMCM:DRP65[9]MMCM:DRP65[8]
20 ----------------------------MMCM:DRP65[7]MMCM:DRP65[6]
21 ----------------------------MMCM:DRP65[5]MMCM:DRP65[4]
22 ----------------------------MMCM:DRP65[3]MMCM:DRP65[2]
23 ----------------------------MMCM:DRP65[1]MMCM:DRP65[0]
24 ----------------------------MMCM:DRP64[15]MMCM:DRP64[14]
25 ----------------------------MMCM:DRP64[13]MMCM:DRP64[12]
26 ----------------------------MMCM:DRP64[11]MMCM:DRP64[10]
27 ----------------------------MMCM:DRP64[9]MMCM:DRP64[8]
28 ----------------------------MMCM:DRP64[7]MMCM:DRP64[6]
29 ----------------------------MMCM:DRP64[5]MMCM:DRP64[4]
30 ----------------------------MMCM:DRP64[3]MMCM:DRP64[2]
31 ----------------------------MMCM:DRP64[1]MMCM:DRP64[0]
32 ----------------------------MMCM:DRP63[15]MMCM:DRP63[14]
33 ----------------------------MMCM:DRP63[13]MMCM:DRP63[12]
34 ----------------------------MMCM:DRP63[11]MMCM:DRP63[10]
35 ----------------------------MMCM:DRP63[9]MMCM:DRP63[8]
36 ----------------------------MMCM:DRP63[7]MMCM:DRP63[6]
37 ----------------------------MMCM:DRP63[5]MMCM:DRP63[4]
38 ----------------------------MMCM:DRP63[3]MMCM:DRP63[2]
39 ----------------------------MMCM:DRP63[1]MMCM:DRP63[0]
40 ----------------------------MMCM:DRP62[15]MMCM:DRP62[14]
41 ----------------------------MMCM:DRP62[13]MMCM:DRP62[12]
42 ----------------------------MMCM:DRP62[11]MMCM:DRP62[10]
43 ----------------------------MMCM:DRP62[9]MMCM:DRP62[8]
44 ----------------------------MMCM:DRP62[7]MMCM:DRP62[6]
45 ----------------------------MMCM:DRP62[5]MMCM:DRP62[4]
46 ----------------------------MMCM:DRP62[3]MMCM:DRP62[2]
47 ----------------------------MMCM:DRP62[1]MMCM:DRP62[0]
48 ----------------------------MMCM:DRP61[15]MMCM:DRP61[14]
49 ----------------------------MMCM:DRP61[13]MMCM:DRP61[12]
50 ----------------------------MMCM:DRP61[11]MMCM:DRP61[10]
51 ----------------------------MMCM:DRP61[9]MMCM:DRP61[8]
52 ----------------------------MMCM:DRP61[7]MMCM:DRP61[6]
53 ----------------------------MMCM:DRP61[5]MMCM:DRP61[4]
54 ----------------------------MMCM:DRP61[3]MMCM:DRP61[2]
55 ----------------------------MMCM:DRP61[1]MMCM:DRP61[0]
56 ----------------------------MMCM:DRP60[15]MMCM:DRP60[14]
57 ----------------------------MMCM:DRP60[13]MMCM:DRP60[12]
58 ----------------------------MMCM:DRP60[11]MMCM:DRP60[10]
59 ----------------------------MMCM:DRP60[9]MMCM:DRP60[8]
60 ----------------------------MMCM:DRP60[7]MMCM:DRP60[6]
61 ----------------------------MMCM:DRP60[5]MMCM:DRP60[4]
62 ----------------------------MMCM:DRP60[3]MMCM:DRP60[2]
63 ----------------------------MMCM:DRP60[1]MMCM:DRP60[0]
CMT bittile 4
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP5F[15]MMCM:DRP5F[14]
1 ----------------------------MMCM:DRP5F[13]MMCM:DRP5F[12]
2 ----------------------------MMCM:DRP5F[11]MMCM:DRP5F[10]
3 ----------------------------MMCM:DRP5F[9]MMCM:DRP5F[8]
4 ----------------------------MMCM:DRP5F[7]MMCM:DRP5F[6]
5 ----------------------------MMCM:DRP5F[5]MMCM:DRP5F[4]
6 ----------------------------MMCM:DRP5F[3]MMCM:DRP5F[2]
7 ----------------------------MMCM:DRP5F[1]MMCM:DRP5F[0]
8 ----------------------------MMCM:DRP5E[15]MMCM:DRP5E[14]
9 ----------------------------MMCM:DRP5E[13]MMCM:DRP5E[12]
10 ----------------------------MMCM:DRP5E[11]MMCM:DRP5E[10]
11 ----------------------------MMCM:DRP5E[9]MMCM:DRP5E[8]
12 ----------------------------MMCM:DRP5E[7]MMCM:DRP5E[6]
13 ----------------------------MMCM:DRP5E[5]MMCM:DRP5E[4]
14 ----------------------------MMCM:DRP5E[3]MMCM:DRP5E[2]
15 ----------------------------MMCM:DRP5E[1]MMCM:DRP5E[0]
16 ----------------------------MMCM:DRP5D[15]MMCM:DRP5D[14]
17 ----------------------------MMCM:DRP5D[13]MMCM:DRP5D[12]
18 ----------------------------MMCM:DRP5D[11]MMCM:DRP5D[10]
19 ----------------------------MMCM:DRP5D[9]MMCM:DRP5D[8]
20 ----------------------------MMCM:DRP5D[7]MMCM:DRP5D[6]
21 ----------------------------MMCM:DRP5D[5]MMCM:DRP5D[4]
22 ----------------------------MMCM:DRP5D[3]MMCM:DRP5D[2]
23 ----------------------------MMCM:DRP5D[1]MMCM:DRP5D[0]
24 ----------------------------MMCM:DRP5C[15]MMCM:DRP5C[14]
25 ----------------------------MMCM:DRP5C[13]MMCM:DRP5C[12]
26 ----------------------------MMCM:DRP5C[11]MMCM:DRP5C[10]
27 ----------------------------MMCM:DRP5C[9]MMCM:DRP5C[8]
28 ----------------------------MMCM:DRP5C[7]MMCM:DRP5C[6]
29 ----------------------------MMCM:DRP5C[5]MMCM:DRP5C[4]
30 ----------------------------MMCM:DRP5C[3]MMCM:DRP5C[2]
31 ----------------------------MMCM:DRP5C[1]MMCM:DRP5C[0]
32 ----------------------------MMCM:DRP5B[15]MMCM:DRP5B[14]
33 ----------------------------MMCM:DRP5B[13]MMCM:DRP5B[12]
34 ----------------------------MMCM:DRP5B[11]MMCM:DRP5B[10]
35 ----------------------------MMCM:DRP5B[9]MMCM:DRP5B[8]
36 ----------------------------MMCM:DRP5B[7]MMCM:DRP5B[6]
37 ----------------------------MMCM:DRP5B[5]MMCM:DRP5B[4]
38 ----------------------------MMCM:DRP5B[3]MMCM:DRP5B[2]
39 ----------------------------MMCM:DRP5B[1]MMCM:DRP5B[0]
40 ----------------------------MMCM:DRP5A[15]MMCM:DRP5A[14]
41 ----------------------------MMCM:DRP5A[13]MMCM:DRP5A[12]
42 ----------------------------MMCM:DRP5A[11]MMCM:DRP5A[10]
43 ----------------------------MMCM:DRP5A[9]MMCM:DRP5A[8]
44 ----------------------------MMCM:DRP5A[7]MMCM:DRP5A[6]
45 ----------------------------MMCM:DRP5A[5]MMCM:DRP5A[4]
46 ----------------------------MMCM:DRP5A[3]MMCM:DRP5A[2]
47 ----------------------------MMCM:DRP5A[1]MMCM:DRP5A[0]
48 ----------------------------MMCM:DRP59[15]MMCM:DRP59[14]
49 ----------------------------MMCM:DRP59[13]MMCM:DRP59[12]
50 ----------------------------MMCM:DRP59[11]MMCM:DRP59[10]
51 ----------------------------MMCM:DRP59[9]MMCM:DRP59[8]
52 ----------------------------MMCM:DRP59[7]MMCM:DRP59[6]
53 ----------------------------MMCM:DRP59[5]MMCM:DRP59[4]
54 ----------------------------MMCM:DRP59[3]MMCM:DRP59[2]
55 ----------------------------MMCM:DRP59[1]MMCM:DRP59[0]
56 ----------------------------MMCM:DRP58[15]MMCM:DRP58[14]
57 ----------------------------MMCM:DRP58[13]MMCM:DRP58[12]
58 ----------------------------MMCM:DRP58[11]MMCM:DRP58[10]
59 ----------------------------MMCM:DRP58[9]MMCM:DRP58[8]
60 ----------------------------MMCM:DRP58[7]MMCM:DRP58[6]
61 ----------------------------MMCM:DRP58[5]MMCM:DRP58[4]
62 ----------------------------MMCM:DRP58[3]MMCM:DRP58[2]
63 ----------------------------MMCM:DRP58[1]MMCM:DRP58[0]
CMT bittile 5
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP57[15]MMCM:DRP57[14]
1 ----------------------------MMCM:DRP57[13]MMCM:DRP57[12]
2 ----------------------------MMCM:DRP57[11]MMCM:DRP57[10]
3 ----------------------------MMCM:DRP57[9]MMCM:DRP57[8]
4 ----------------------------MMCM:DRP57[7]MMCM:DRP57[6]
5 ----------------------------MMCM:DRP57[5]MMCM:DRP57[4]
6 ----------------------------MMCM:DRP57[3]MMCM:DRP57[2]
7 ----------------------------MMCM:DRP57[1]MMCM:DRP57[0]
8 ----------------------------MMCM:DRP56[15]MMCM:DRP56[14]
9 ----------------------------MMCM:DRP56[13]MMCM:DRP56[12]
10 ----------------------------MMCM:DRP56[11]MMCM:DRP56[10]
11 ----------------------------MMCM:DRP56[9]MMCM:DRP56[8]
12 ----------------------------MMCM:DRP56[7]MMCM:DRP56[6]
13 ----------------------------MMCM:DRP56[5]MMCM:DRP56[4]
14 ----------------------------MMCM:DRP56[3]MMCM:DRP56[2]
15 ----------------------------MMCM:DRP56[1]MMCM:DRP56[0]
16 ----------------------------MMCM:DRP55[15]MMCM:DRP55[14]
17 ----------------------------MMCM:DRP55[13]MMCM:DRP55[12]
18 ----------------------------MMCM:DRP55[11]MMCM:DRP55[10]
19 ----------------------------MMCM:DRP55[9]MMCM:DRP55[8]
20 ----------------------------MMCM:DRP55[7]MMCM:DRP55[6]
21 ----------------------------MMCM:DRP55[5]MMCM:DRP55[4]
22 ----------------------------MMCM:DRP55[3]MMCM:DRP55[2]
23 ----------------------------MMCM:DRP55[1]MMCM:DRP55[0]
24 ----------------------------MMCM:DRP54[15]MMCM:DRP54[14]
25 ----------------------------MMCM:DRP54[13]MMCM:DRP54[12]
26 ----------------------------MMCM:DRP54[11]MMCM:DRP54[10]
27 ----------------------------MMCM:DRP54[9]MMCM:DRP54[8]
28 ----------------------------MMCM:DRP54[7]MMCM:DRP54[6]
29 ----------------------------MMCM:DRP54[5]MMCM:DRP54[4]
30 ----------------------------MMCM:DRP54[3]MMCM:DRP54[2]
31 ----------------------------MMCM:DRP54[1]MMCM:DRP54[0]
32 ----------------------------MMCM:DRP53[15]MMCM:DRP53[14]
33 ----------------------------MMCM:DRP53[13]MMCM:DRP53[12]
34 ----------------------------MMCM:DRP53[11]MMCM:DRP53[10]
35 ----------------------------MMCM:DRP53[9]MMCM:DRP53[8]
36 ----------------------------MMCM:DRP53[7]MMCM:DRP53[6]
37 ----------------------------MMCM:DRP53[5]MMCM:DRP53[4]
38 ----------------------------MMCM:DRP53[3]MMCM:DRP53[2]
39 ----------------------------MMCM:DRP53[1]MMCM:DRP53[0]
40 ----------------------------MMCM:DRP52[15]MMCM:DRP52[14]
41 ----------------------------MMCM:DRP52[13]MMCM:DRP52[12]
42 ----------------------------MMCM:DRP52[11]MMCM:DRP52[10]
43 ----------------------------MMCM:DRP52[9]MMCM:DRP52[8]
44 ----------------------------MMCM:DRP52[7]MMCM:DRP52[6]
45 ----------------------------MMCM:DRP52[5]MMCM:DRP52[4]
46 ----------------------------MMCM:DRP52[3]MMCM:DRP52[2]
47 ----------------------------MMCM:DRP52[1]MMCM:DRP52[0]
48 ----------------------------MMCM:DRP51[15]MMCM:DRP51[14]
49 ----------------------------MMCM:DRP51[13]MMCM:DRP51[12]
50 ----------------------------MMCM:DRP51[11]MMCM:DRP51[10]
51 ----------------------------MMCM:DRP51[9]MMCM:DRP51[8]
52 ----------------------------MMCM:DRP51[7]MMCM:DRP51[6]
53 ----------------------------MMCM:DRP51[5]MMCM:DRP51[4]
54 ----------------------------MMCM:DRP51[3]MMCM:DRP51[2]
55 ----------------------------MMCM:DRP51[1]MMCM:DRP51[0]
56 ----------------------------MMCM:DRP50[15]MMCM:DRP50[14]
57 ----------------------------MMCM:DRP50[13]MMCM:DRP50[12]
58 ----------------------------MMCM:DRP50[11]MMCM:DRP50[10]
59 ----------------------------MMCM:DRP50[9]MMCM:DRP50[8]
60 ----------------------------MMCM:DRP50[7]MMCM:DRP50[6]
61 ----------------------------MMCM:DRP50[5]MMCM:DRP50[4]
62 ----------------------------MMCM:DRP50[3]MMCM:DRP50[2]
63 ----------------------------MMCM:DRP50[1]MMCM:DRP50[0]
CMT bittile 6
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP4F[15]
MMCM:RES[3]		MMCM:DRP4F[14]
1 ----------------------------MMCM:DRP4F[13]MMCM:DRP4F[12]
MMCM:RES[2]
2 ----------------------------MMCM:DRP4F[11]
MMCM:RES[1]		MMCM:DRP4F[10]
3 ----------------------------MMCM:DRP4F[9]MMCM:DRP4F[8]
MMCM:RES[0]
4 ----------------------------MMCM:DRP4F[7]
MMCM:LFHF[1]		MMCM:DRP4F[6]
5 ----------------------------MMCM:DRP4F[5]MMCM:DRP4F[4]
MMCM:LFHF[0]
6 ----------------------------MMCM:DRP4F[3]MMCM:DRP4F[2]
7 ----------------------------MMCM:DRP4F[1]MMCM:DRP4F[0]
8 ----------------------------MMCM:CP[3]
MMCM:DRP4E[15]		MMCM:DRP4E[14]
9 ----------------------------MMCM:DRP4E[13]MMCM:CP[2]
MMCM:DRP4E[12]
10 ----------------------------MMCM:CP[1]
MMCM:DRP4E[11]		MMCM:DRP4E[10]
11 ----------------------------MMCM:DRP4E[9]MMCM:CP[0]
MMCM:DRP4E[8]
12 ----------------------------MMCM:CP_BIAS_TRIP_SET
MMCM:DRP4E[7]		MMCM:DRP4E[6]
13 ----------------------------MMCM:DRP4E[5]MMCM:CP_RES[1]
MMCM:DRP4E[4]
14 ----------------------------MMCM:CP_RES[0]
MMCM:DRP4E[3]		MMCM:DRP4E[2]
15 ----------------------------MMCM:DRP4E[1]MMCM:DRP4E[0]
16 ----------------------------MMCM:DRP4D[15]MMCM:DRP4D[14]
17 ----------------------------MMCM:DRP4D[13]MMCM:DRP4D[12]
18 ----------------------------MMCM:DRP4D[11]MMCM:DRP4D[10]
19 ----------------------------MMCM:DRP4D[9]MMCM:DRP4D[8]
20 ----------------------------MMCM:DRP4D[7]MMCM:DRP4D[6]
21 ----------------------------MMCM:DRP4D[5]MMCM:DRP4D[4]
22 ----------------------------MMCM:DRP4D[3]MMCM:DRP4D[2]
23 ----------------------------MMCM:DRP4D[1]MMCM:DRP4D[0]
24 ----------------------------MMCM:DRP4C[15]MMCM:DRP4C[14]
25 ----------------------------MMCM:DRP4C[13]MMCM:DRP4C[12]
MMCM:HVLF_CNT_TEST_EN
26 ----------------------------MMCM:DRP4C[11]
MMCM:HVLF_CNT_TEST[5]		MMCM:DRP4C[10]
27 ----------------------------MMCM:DRP4C[9]MMCM:DRP4C[8]
MMCM:HVLF_CNT_TEST[4]
28 ----------------------------MMCM:DRP4C[7]
MMCM:HVLF_CNT_TEST[3]		MMCM:DRP4C[6]
29 ----------------------------MMCM:DRP4C[5]MMCM:DRP4C[4]
MMCM:HVLF_CNT_TEST[2]
30 ----------------------------MMCM:DRP4C[3]
MMCM:HVLF_CNT_TEST[1]		MMCM:DRP4C[2]
31 ----------------------------MMCM:DRP4C[1]MMCM:DRP4C[0]
MMCM:HVLF_CNT_TEST[0]
32 ----------------------------MMCM:DRP4B[15]MMCM:DRP4B[14]
33 ----------------------------MMCM:DRP4B[13]MMCM:DRP4B[12]
34 ----------------------------MMCM:DRP4B[11]MMCM:DRP4B[10]
35 ----------------------------MMCM:DRP4B[9]MMCM:DRP4B[8]
36 ----------------------------MMCM:DRP4B[7]MMCM:DRP4B[6]
37 ----------------------------MMCM:DRP4B[5]MMCM:DRP4B[4]
38 ----------------------------MMCM:DRP4B[3]MMCM:DRP4B[2]
39 ----------------------------MMCM:DRP4B[1]MMCM:DRP4B[0]
40 ----------------------------MMCM:DRP4A[15]MMCM:DRP4A[14]
41 ----------------------------MMCM:DRP4A[13]MMCM:DRP4A[12]
42 ----------------------------MMCM:DRP4A[11]MMCM:DRP4A[10]
43 ----------------------------MMCM:AVDD_COMP_SET[2]
MMCM:DRP4A[9]		MMCM:AVDD_COMP_SET[1]
MMCM:DRP4A[8]
44 ----------------------------MMCM:AVDD_COMP_SET[0]
MMCM:DRP4A[7]		MMCM:AVDD_VBG_PD[2]
MMCM:DRP4A[6]
45 ----------------------------MMCM:AVDD_VBG_PD[1]
MMCM:DRP4A[5]		MMCM:AVDD_VBG_PD[0]
MMCM:DRP4A[4]
46 ----------------------------MMCM:AVDD_VBG_SEL[3]
MMCM:DRP4A[3]		MMCM:AVDD_VBG_SEL[2]
MMCM:DRP4A[2]
47 ----------------------------MMCM:AVDD_VBG_SEL[1]
MMCM:DRP4A[1]		MMCM:AVDD_VBG_SEL[0]
MMCM:DRP4A[0]
48 ----------------------------MMCM:DRP49[15]
MMCM:SUP_SEL_AREG		MMCM:DRP49[14]
MMCM:EN_CURR_SINK[1]
49 ----------------------------MMCM:DRP49[13]
MMCM:EN_CURR_SINK[0]		MMCM:DRP49[12]
MMCM:MVDD_SEL[1]
50 ----------------------------MMCM:DRP49[11]
MMCM:MVDD_SEL[0]		MMCM:DRP49[10]
MMCM:SEL_HV_NMOS
51 ----------------------------MMCM:DRP49[9]MMCM:DRP49[8]
52 ----------------------------MMCM:DRP49[7]MMCM:DRP49[6]
53 ----------------------------MMCM:DRP49[5]MMCM:DRP49[4]
54 ----------------------------MMCM:DRP49[3]MMCM:DRP49[2]
55 ----------------------------MMCM:DRP49[1]MMCM:DRP49[0]
56 ----------------------------MMCM:DRP48[15]MMCM:DRP48[14]
57 ----------------------------MMCM:DRP48[13]MMCM:DRP48[12]
58 ----------------------------MMCM:DRP48[11]MMCM:DRP48[10]
59 ----------------------------MMCM:DRP48[9]MMCM:DRP48[8]
60 ----------------------------MMCM:DRP48[7]MMCM:DRP48[6]
61 ----------------------------MMCM:DRP48[5]MMCM:DRP48[4]
62 ----------------------------MMCM:DRP48[3]MMCM:DRP48[2]
63 ----------------------------MMCM:DRP48[1]MMCM:DRP48[0]
CMT bittile 7
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP47[15]MMCM:DRP47[14]
1 ----------------------------MMCM:DRP47[13]MMCM:DRP47[12]
2 ----------------------------MMCM:DRP47[11]MMCM:DRP47[10]
3 ----------------------------MMCM:DRP47[9]MMCM:DRP47[8]
4 ----------------------------MMCM:DRP47[7]MMCM:DRP47[6]
5 ----------------------------MMCM:DRP47[5]MMCM:DRP47[4]
6 ----------------------------MMCM:DRP47[3]MMCM:DRP47[2]
7 ----------------------------MMCM:DRP47[1]MMCM:DRP47[0]
8 ----------------------------MMCM:DRP46[15]MMCM:DRP46[14]
9 ----------------------------MMCM:DRP46[13]MMCM:DRP46[12]
10 ----------------------------MMCM:DRP46[11]MMCM:DRP46[10]
11 ----------------------------MMCM:DRP46[9]MMCM:DRP46[8]
12 ----------------------------MMCM:DRP46[7]MMCM:DRP46[6]
13 ----------------------------MMCM:DRP46[5]MMCM:DRP46[4]
14 ----------------------------MMCM:DRP46[3]MMCM:DRP46[2]
15 ----------------------------MMCM:DRP46[1]MMCM:DRP46[0]
MMCM:VLF_HIGH_PWDN_B
16 ----------------------------MMCM:DRP45[15]MMCM:DRP45[14]
17 ----------------------------MMCM:DRP45[13]MMCM:DRP45[12]
MMCM:VREF_START[1]
18 ----------------------------MMCM:DRP45[11]
MMCM:VREF_START[0]		MMCM:DRP45[10]
19 ----------------------------MMCM:DRP45[9]MMCM:DRP45[8]
20 ----------------------------MMCM:DRP45[7]MMCM:DRP45[6]
21 ----------------------------MMCM:DRP45[5]MMCM:DRP45[4]
22 ----------------------------MMCM:DRP45[3]MMCM:DRP45[2]
23 ----------------------------MMCM:DRP45[1]MMCM:DRP45[0]
24 ----------------------------MMCM:DRP44[15]MMCM:DRP44[14]
25 ----------------------------MMCM:DRP44[13]MMCM:DRP44[12]
26 ----------------------------MMCM:DRP44[11]MMCM:DRP44[10]
27 ----------------------------MMCM:DRP44[9]MMCM:DRP44[8]
MMCM:SPARE_ANALOG[4]
28 ----------------------------MMCM:DRP44[7]
MMCM:SPARE_ANALOG[3]		MMCM:DRP44[6]
29 ----------------------------MMCM:DRP44[5]MMCM:DRP44[4]
MMCM:SPARE_ANALOG[2]
30 ----------------------------MMCM:DRP44[3]
MMCM:SPARE_ANALOG[1]		MMCM:DRP44[2]
31 ----------------------------MMCM:DRP44[1]MMCM:DRP44[0]
MMCM:SPARE_ANALOG[0]
32 ----------------------------MMCM:DRP43[15]MMCM:DRP43[14]
33 ----------------------------MMCM:DRP43[13]MMCM:DRP43[12]
34 ----------------------------MMCM:DRP43[11]MMCM:DRP43[10]
35 ----------------------------MMCM:DRP43[9]MMCM:DRP43[8]
36 ----------------------------MMCM:DRP43[7]MMCM:DRP43[6]
37 ----------------------------MMCM:DRP43[5]MMCM:DRP43[4]
38 ----------------------------MMCM:DRP43[3]MMCM:DRP43[2]
39 ----------------------------MMCM:DRP43[1]MMCM:DRP43[0]
MMCM:LF_LOW_SEL
40 ----------------------------MMCM:DRP42[15]
MMCM:LF_NEN[1]		MMCM:DRP42[14]
41 ----------------------------MMCM:DRP42[13]MMCM:DRP42[12]
MMCM:LF_NEN[0]
42 ----------------------------MMCM:DRP42[11]
MMCM:LF_PEN[1]		MMCM:DRP42[10]
43 ----------------------------MMCM:DRP42[9]MMCM:DRP42[8]
MMCM:LF_PEN[0]
44 ----------------------------MMCM:DRP42[7]
MMCM:VLF_HIGH_DIS_B		MMCM:DRP42[6]
45 ----------------------------MMCM:DRP42[5]MMCM:DRP42[4]
MMCM:MAN_LF[2]
46 ----------------------------MMCM:DRP42[3]
MMCM:MAN_LF[1]		MMCM:DRP42[2]
47 ----------------------------MMCM:DRP42[1]MMCM:DRP42[0]
MMCM:MAN_LF[0]
48 ----------------------------MMCM:DRP41[15]MMCM:DRP41[14]
49 ----------------------------MMCM:DRP41[13]MMCM:DRP41[12]
50 ----------------------------MMCM:DRP41[11]MMCM:DRP41[10]
51 ----------------------------MMCM:DRP41[9]MMCM:DRP41[8]
52 ----------------------------MMCM:DRP41[7]MMCM:DRP41[6]
53 ----------------------------MMCM:DRP41[5]MMCM:DRP41[4]
54 ----------------------------MMCM:DRP41[3]MMCM:DRP41[2]
55 ----------------------------MMCM:DRP41[1]MMCM:DRP41[0]
56 ----------------------------MMCM:DRP40[15]MMCM:DRP40[14]
57 ----------------------------MMCM:DRP40[13]MMCM:DRP40[12]
58 ----------------------------MMCM:DRP40[11]MMCM:DRP40[10]
59 ----------------------------MMCM:DRP40[9]MMCM:DRP40[8]
60 ----------------------------MMCM:DRP40[7]MMCM:DRP40[6]
61 ----------------------------MMCM:DRP40[5]MMCM:DRP40[4]
62 ----------------------------MMCM:DRP40[3]MMCM:DRP40[2]
63 ----------------------------MMCM:DRP40[1]MMCM:DRP40[0]
CMT bittile 8
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP3F[15]MMCM:DRP3F[14]
1 ----------------------------MMCM:DRP3F[13]MMCM:DRP3F[12]
2 ----------------------------MMCM:DRP3F[11]MMCM:DRP3F[10]
3 ----------------------------MMCM:DRP3F[9]MMCM:DRP3F[8]
4 ----------------------------MMCM:DRP3F[7]MMCM:DRP3F[6]
5 ----------------------------MMCM:DRP3F[5]MMCM:DRP3F[4]
6 ----------------------------MMCM:DRP3F[3]MMCM:DRP3F[2]
7 ----------------------------MMCM:DRP3F[1]MMCM:DRP3F[0]
8 ----------------------------MMCM:DRP3E[15]MMCM:DRP3E[14]
9 ----------------------------MMCM:DRP3E[13]MMCM:DRP3E[12]
10 ----------------------------MMCM:DRP3E[11]MMCM:DRP3E[10]
11 ----------------------------MMCM:DRP3E[9]MMCM:DRP3E[8]
12 ----------------------------MMCM:DRP3E[7]MMCM:DRP3E[6]
13 ----------------------------MMCM:DRP3E[5]MMCM:DRP3E[4]
14 ----------------------------MMCM:DRP3E[3]MMCM:DRP3E[2]
15 ----------------------------MMCM:DRP3E[1]MMCM:DRP3E[0]
16 ----------------------------MMCM:DRP3D[15]MMCM:DRP3D[14]
17 ----------------------------MMCM:DRP3D[13]MMCM:DRP3D[12]
18 ----------------------------MMCM:DRP3D[11]MMCM:DRP3D[10]
19 ----------------------------MMCM:DRP3D[9]MMCM:DRP3D[8]
20 ----------------------------MMCM:DRP3D[7]MMCM:DRP3D[6]
21 ----------------------------MMCM:DRP3D[5]MMCM:DRP3D[4]
22 ----------------------------MMCM:DRP3D[3]MMCM:DRP3D[2]
23 ----------------------------MMCM:DRP3D[1]MMCM:DRP3D[0]
24 ----------------------------MMCM:DRP3C[15]MMCM:DRP3C[14]
25 ----------------------------MMCM:DRP3C[13]MMCM:DRP3C[12]
26 ----------------------------MMCM:DRP3C[11]MMCM:DRP3C[10]
27 ----------------------------MMCM:DRP3C[9]MMCM:DRP3C[8]
28 ----------------------------MMCM:DRP3C[7]MMCM:DRP3C[6]
29 ----------------------------MMCM:DRP3C[5]MMCM:DRP3C[4]
30 ----------------------------MMCM:DRP3C[3]MMCM:DRP3C[2]
31 ----------------------------MMCM:DRP3C[1]MMCM:DRP3C[0]
32 ----------------------------MMCM:DRP3B[15]MMCM:DRP3B[14]
33 ----------------------------MMCM:DRP3B[13]MMCM:DRP3B[12]
34 ----------------------------MMCM:DRP3B[11]MMCM:DRP3B[10]
35 ----------------------------MMCM:DRP3B[9]MMCM:DRP3B[8]
36 ----------------------------MMCM:DRP3B[7]MMCM:DRP3B[6]
37 ----------------------------MMCM:DRP3B[5]MMCM:DRP3B[4]
38 ----------------------------MMCM:DRP3B[3]MMCM:DRP3B[2]
39 ----------------------------MMCM:DRP3B[1]MMCM:DRP3B[0]
40 ----------------------------MMCM:DRP3A[15]MMCM:DRP3A[14]
41 ----------------------------MMCM:DRP3A[13]MMCM:DRP3A[12]
42 ----------------------------MMCM:DRP3A[11]MMCM:DRP3A[10]
43 ----------------------------MMCM:DRP3A[9]MMCM:DRP3A[8]
44 ----------------------------MMCM:DRP3A[7]MMCM:DRP3A[6]
45 ----------------------------MMCM:DRP3A[5]MMCM:DRP3A[4]
46 ----------------------------MMCM:DRP3A[3]MMCM:DRP3A[2]
47 ----------------------------MMCM:DRP3A[1]MMCM:DRP3A[0]
48 ----------------------------MMCM:DRP39[15]MMCM:DRP39[14]
49 ----------------------------MMCM:DRP39[13]MMCM:DRP39[12]
50 ----------------------------MMCM:DRP39[11]MMCM:DRP39[10]
51 ----------------------------MMCM:DRP39[9]MMCM:DRP39[8]
52 ----------------------------MMCM:DRP39[7]MMCM:DRP39[6]
53 ----------------------------MMCM:DRP39[5]MMCM:DRP39[4]
54 ----------------------------MMCM:DRP39[3]MMCM:DRP39[2]
55 ----------------------------MMCM:DRP39[1]MMCM:DRP39[0]
56 ----------------------------MMCM:DRP38[15]MMCM:DRP38[14]
57 ----------------------------MMCM:DRP38[13]MMCM:DRP38[12]
58 ----------------------------MMCM:DRP38[11]MMCM:DRP38[10]
59 ----------------------------MMCM:DRP38[9]MMCM:DRP38[8]
60 ----------------------------MMCM:DRP38[7]MMCM:DRP38[6]
61 ----------------------------MMCM:DRP38[5]MMCM:DRP38[4]
62 ----------------------------MMCM:DRP38[3]MMCM:DRP38[2]
63 ----------------------------MMCM:DRP38[1]MMCM:DRP38[0]
CMT bittile 9
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP37[15]MMCM:DRP37[14]
1 ----------------------------MMCM:DRP37[13]MMCM:DRP37[12]
2 ----------------------------MMCM:DRP37[11]MMCM:DRP37[10]
3 ----------------------------MMCM:DRP37[9]MMCM:DRP37[8]
4 ----------------------------MMCM:DRP37[7]MMCM:DRP37[6]
5 ----------------------------MMCM:DRP37[5]MMCM:DRP37[4]
6 ----------------------------MMCM:DRP37[3]MMCM:DRP37[2]
7 ----------------------------MMCM:DRP37[1]MMCM:DRP37[0]
8 ----------------------------MMCM:DRP36[15]MMCM:DRP36[14]
9 ----------------------------MMCM:DRP36[13]MMCM:DRP36[12]
10 ----------------------------MMCM:DRP36[11]MMCM:DRP36[10]
11 ----------------------------MMCM:DRP36[9]MMCM:DRP36[8]
12 ----------------------------MMCM:DRP36[7]MMCM:DRP36[6]
13 ----------------------------MMCM:DRP36[5]MMCM:DRP36[4]
14 ----------------------------MMCM:DRP36[3]MMCM:DRP36[2]
15 ----------------------------MMCM:DRP36[1]MMCM:DRP36[0]
16 ----------------------------MMCM:DRP35[15]MMCM:DRP35[14]
17 ----------------------------MMCM:DRP35[13]MMCM:DRP35[12]
18 ----------------------------MMCM:DRP35[11]MMCM:DRP35[10]
19 ----------------------------MMCM:DRP35[9]MMCM:DRP35[8]
20 ----------------------------MMCM:DRP35[7]MMCM:DRP35[6]
21 ----------------------------MMCM:DRP35[5]MMCM:DRP35[4]
22 ----------------------------MMCM:DRP35[3]MMCM:DRP35[2]
23 ----------------------------MMCM:DRP35[1]MMCM:DRP35[0]
24 ----------------------------MMCM:DRP34[15]MMCM:DRP34[14]
25 ----------------------------MMCM:DRP34[13]MMCM:DRP34[12]
26 ----------------------------MMCM:DRP34[11]MMCM:DRP34[10]
27 ----------------------------MMCM:DRP34[9]MMCM:DRP34[8]
28 ----------------------------MMCM:DRP34[7]MMCM:DRP34[6]
29 ----------------------------MMCM:DRP34[5]MMCM:DRP34[4]
30 ----------------------------MMCM:DRP34[3]MMCM:DRP34[2]
31 ----------------------------MMCM:DRP34[1]MMCM:DRP34[0]
32 ----------------------------MMCM:DRP33[15]MMCM:DRP33[14]
33 ----------------------------MMCM:DRP33[13]MMCM:DRP33[12]
34 ----------------------------MMCM:DRP33[11]MMCM:DRP33[10]
35 ----------------------------MMCM:DRP33[9]MMCM:DRP33[8]
36 ----------------------------MMCM:DRP33[7]MMCM:DRP33[6]
37 ----------------------------MMCM:DRP33[5]MMCM:DRP33[4]
38 ----------------------------MMCM:DRP33[3]MMCM:DRP33[2]
39 ----------------------------MMCM:DRP33[1]MMCM:DRP33[0]
40 ----------------------------MMCM:DRP32[15]MMCM:DRP32[14]
41 ----------------------------MMCM:DRP32[13]MMCM:DRP32[12]
42 ----------------------------MMCM:DRP32[11]MMCM:DRP32[10]
43 ----------------------------MMCM:DRP32[9]MMCM:DRP32[8]
44 ----------------------------MMCM:DRP32[7]MMCM:DRP32[6]
45 ----------------------------MMCM:DRP32[5]MMCM:DRP32[4]
46 ----------------------------MMCM:DRP32[3]MMCM:DRP32[2]
47 ----------------------------MMCM:DRP32[1]MMCM:DRP32[0]
48 ----------------------------MMCM:DRP31[15]MMCM:DRP31[14]
49 ----------------------------MMCM:DRP31[13]MMCM:DRP31[12]
50 ----------------------------MMCM:DRP31[11]MMCM:DRP31[10]
51 ----------------------------MMCM:DRP31[9]MMCM:DRP31[8]
52 ----------------------------MMCM:DRP31[7]MMCM:DRP31[6]
53 ----------------------------MMCM:DRP31[5]MMCM:DRP31[4]
54 ----------------------------MMCM:DRP31[3]MMCM:DRP31[2]
55 ----------------------------MMCM:DRP31[1]MMCM:DRP31[0]
56 ----------------------------MMCM:DRP30[15]MMCM:DRP30[14]
57 ----------------------------MMCM:DRP30[13]MMCM:DRP30[12]
58 ----------------------------MMCM:DRP30[11]MMCM:DRP30[10]
59 ----------------------------MMCM:DRP30[9]MMCM:DRP30[8]
60 ----------------------------MMCM:DRP30[7]MMCM:DRP30[6]
61 ----------------------------MMCM:DRP30[5]MMCM:DRP30[4]
62 ----------------------------MMCM:DRP30[3]MMCM:DRP30[2]
63 ----------------------------MMCM:DRP30[1]MMCM:DRP30[0]
CMT bittile 10
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP2F[15]MMCM:DRP2F[14]
1 ----------------------------MMCM:DRP2F[13]MMCM:DRP2F[12]
2 ----------------------------MMCM:DRP2F[11]MMCM:DRP2F[10]
3 ----------------------------MMCM:DRP2F[9]MMCM:DRP2F[8]
4 ----------------------------MMCM:DRP2F[7]MMCM:DRP2F[6]
5 ----------------------------MMCM:DRP2F[5]MMCM:DRP2F[4]
6 ----------------------------MMCM:DRP2F[3]MMCM:DRP2F[2]
7 ----------------------------MMCM:DRP2F[1]MMCM:DRP2F[0]
8 ----------------------------MMCM:DRP2E[15]MMCM:DRP2E[14]
9 ----------------------------MMCM:DRP2E[13]MMCM:DRP2E[12]
10 ----------------------------MMCM:DRP2E[11]MMCM:DRP2E[10]
11 ----------------------------MMCM:DRP2E[9]MMCM:DRP2E[8]
12 ----------------------------MMCM:DRP2E[7]MMCM:DRP2E[6]
13 ----------------------------MMCM:DRP2E[5]MMCM:DRP2E[4]
14 ----------------------------MMCM:DRP2E[3]MMCM:DRP2E[2]
15 ----------------------------MMCM:DRP2E[1]MMCM:DRP2E[0]
16 ----------------------------MMCM:DRP2D[15]MMCM:DRP2D[14]
17 ----------------------------MMCM:DRP2D[13]MMCM:DRP2D[12]
18 ----------------------------MMCM:DRP2D[11]MMCM:DRP2D[10]
19 ----------------------------MMCM:DRP2D[9]MMCM:DRP2D[8]
20 ----------------------------MMCM:DRP2D[7]MMCM:DRP2D[6]
21 ----------------------------MMCM:DRP2D[5]MMCM:DRP2D[4]
22 ----------------------------MMCM:DRP2D[3]MMCM:DRP2D[2]
23 ----------------------------MMCM:DRP2D[1]MMCM:DRP2D[0]
24 ----------------------------MMCM:DRP2C[15]MMCM:DRP2C[14]
25 ----------------------------MMCM:DRP2C[13]MMCM:DRP2C[12]
26 ----------------------------MMCM:DRP2C[11]MMCM:DRP2C[10]
27 ----------------------------MMCM:DRP2C[9]MMCM:DRP2C[8]
28 ----------------------------MMCM:DRP2C[7]MMCM:DRP2C[6]
29 ----------------------------MMCM:DRP2C[5]MMCM:DRP2C[4]
30 ----------------------------MMCM:DRP2C[3]MMCM:DRP2C[2]
31 ----------------------------MMCM:DRP2C[1]MMCM:DRP2C[0]
32 ----------------------------MMCM:DRP2B[15]MMCM:DRP2B[14]
33 ----------------------------MMCM:DRP2B[13]MMCM:DRP2B[12]
34 ----------------------------MMCM:DRP2B[11]MMCM:DRP2B[10]
35 ----------------------------MMCM:DRP2B[9]MMCM:DRP2B[8]
36 ----------------------------MMCM:DRP2B[7]MMCM:DRP2B[6]
37 ----------------------------MMCM:DRP2B[5]MMCM:DRP2B[4]
38 ----------------------------MMCM:DRP2B[3]MMCM:DRP2B[2]
39 ----------------------------MMCM:DRP2B[1]MMCM:DRP2B[0]
40 ----------------------------MMCM:DRP2A[15]MMCM:DRP2A[14]
41 ----------------------------MMCM:DRP2A[13]MMCM:DRP2A[12]
42 ----------------------------MMCM:DRP2A[11]MMCM:DRP2A[10]
43 ----------------------------MMCM:DRP2A[9]MMCM:DRP2A[8]
44 ----------------------------MMCM:DRP2A[7]MMCM:DRP2A[6]
45 ----------------------------MMCM:DRP2A[5]MMCM:DRP2A[4]
46 ----------------------------MMCM:DRP2A[3]MMCM:DRP2A[2]
47 ----------------------------MMCM:DRP2A[1]MMCM:DRP2A[0]
48 ----------------------------MMCM:DRP29[15]MMCM:DRP29[14]
49 ----------------------------MMCM:DRP29[13]MMCM:DRP29[12]
50 ----------------------------MMCM:DRP29[11]MMCM:DRP29[10]
51 ----------------------------MMCM:DRP29[9]MMCM:DRP29[8]
52 ----------------------------MMCM:DRP29[7]MMCM:DRP29[6]
53 ----------------------------MMCM:DRP29[5]MMCM:DRP29[4]
54 ----------------------------MMCM:DRP29[3]MMCM:DRP29[2]
55 ----------------------------MMCM:DRP29[1]MMCM:DRP29[0]
56 ----------------------------MMCM:DRP28[15]
MMCM:INTERP_EN[7]		MMCM:DRP28[14]
57 ----------------------------MMCM:DRP28[13]MMCM:DRP28[12]
MMCM:INTERP_EN[6]
58 ----------------------------MMCM:DRP28[11]
MMCM:INTERP_EN[5]		MMCM:DRP28[10]
59 ----------------------------MMCM:DRP28[9]MMCM:DRP28[8]
MMCM:INTERP_EN[4]
60 ----------------------------MMCM:DRP28[7]
MMCM:INTERP_EN[3]		MMCM:DRP28[6]
61 ----------------------------MMCM:DRP28[5]MMCM:DRP28[4]
MMCM:INTERP_EN[2]
62 ----------------------------MMCM:DRP28[3]
MMCM:INTERP_EN[1]		MMCM:DRP28[2]
63 ----------------------------MMCM:DRP28[1]MMCM:DRP28[0]
MMCM:INTERP_EN[0]
CMT bittile 11
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP27[15]MMCM:DRP27[14]
1 ----------------------------MMCM:DRP27[13]MMCM:DRP27[12]
2 ----------------------------MMCM:DRP27[11]MMCM:DRP27[10]
3 ----------------------------MMCM:DRP27[9]MMCM:DRP27[8]
4 ----------------------------MMCM:DRP27[7]MMCM:DRP27[6]
5 ----------------------------MMCM:DRP27[5]MMCM:DRP27[4]
6 ----------------------------MMCM:DRP27[3]MMCM:DRP27[2]
7 ----------------------------MMCM:DRP27[1]MMCM:DRP27[0]
8 ----------------------------MMCM:DRP26[15]MMCM:DRP26[14]
9 ----------------------------MMCM:DRP26[13]MMCM:DRP26[12]
10 ----------------------------MMCM:DRP26[11]MMCM:DRP26[10]
11 ----------------------------MMCM:DRP26[9]MMCM:ANALOG_MISC[3]
MMCM:DRP26[8]
12 ----------------------------MMCM:ANALOG_MISC[2]
MMCM:DRP26[7]		MMCM:DRP26[6]
13 ----------------------------MMCM:DRP26[5]MMCM:ANALOG_MISC[1]
MMCM:DRP26[4]
14 ----------------------------MMCM:ANALOG_MISC[0]
MMCM:DRP26[3]		MMCM:DRP26[2]
15 ----------------------------MMCM:DRP26[1]MMCM:DRP26[0]
16 ----------------------------MMCM:DRP25[15]MMCM:DRP25[14]
17 ----------------------------MMCM:DRP25[13]MMCM:DRP25[12]
18 ----------------------------MMCM:DRP25[11]MMCM:DRP25[10]
19 ----------------------------MMCM:DRP25[9]MMCM:DRP25[8]
20 ----------------------------MMCM:DRP25[7]MMCM:DRP25[6]
21 ----------------------------MMCM:DRP25[5]MMCM:DRP25[4]
22 ----------------------------MMCM:DRP25[3]MMCM:DRP25[2]
23 ----------------------------MMCM:DRP25[1]MMCM:DRP25[0]
24 ----------------------------MMCM:DRP24[15]MMCM:DRP24[14]
25 ----------------------------MMCM:DRP24[13]MMCM:DRP24[12]
26 ----------------------------MMCM:DRP24[11]MMCM:DRP24[10]
27 ----------------------------MMCM:DRP24[9]MMCM:DRP24[8]
28 ----------------------------MMCM:DRP24[7]MMCM:DRP24[6]
29 ----------------------------MMCM:DRP24[5]MMCM:DRP24[4]
30 ----------------------------MMCM:DRP24[3]MMCM:DRP24[2]
31 ----------------------------MMCM:DRP24[1]MMCM:DRP24[0]
32 ----------------------------MMCM:DRP23[15]MMCM:DRP23[14]
33 ----------------------------MMCM:DRP23[13]MMCM:DRP23[12]
34 ----------------------------MMCM:DRP23[11]MMCM:DRP23[10]
35 ----------------------------MMCM:DRP23[9]MMCM:DRP23[8]
36 ----------------------------MMCM:DRP23[7]MMCM:DRP23[6]
37 ----------------------------MMCM:DRP23[5]MMCM:DRP23[4]
38 ----------------------------MMCM:DRP23[3]MMCM:DRP23[2]
39 ----------------------------MMCM:DRP23[1]MMCM:DRP23[0]
40 ----------------------------MMCM:DRP22[15]MMCM:DRP22[14]
41 ----------------------------MMCM:DRP22[13]MMCM:DRP22[12]
42 ----------------------------MMCM:DRP22[11]MMCM:DRP22[10]
43 ----------------------------MMCM:DRP22[9]MMCM:DRP22[8]
44 ----------------------------MMCM:DRP22[7]MMCM:DRP22[6]
45 ----------------------------MMCM:DRP22[5]MMCM:DRP22[4]
46 ----------------------------MMCM:DRP22[3]MMCM:DRP22[2]
MMCM:INTERP_TEST
47 ----------------------------MMCM:DRP22[1]
MMCM:EN_VCO_DIV1		MMCM:DRP22[0]
MMCM:EN_VCO_DIV6
48 ----------------------------MMCM:DRP21[15]MMCM:DRP21[14]
49 ----------------------------MMCM:DRP21[13]MMCM:DRP21[12]
50 ----------------------------MMCM:DRP21[11]MMCM:DRP21[10]
51 ----------------------------MMCM:DRP21[9]MMCM:DRP21[8]
52 ----------------------------MMCM:DRP21[7]MMCM:DRP21[6]
53 ----------------------------MMCM:DRP21[5]MMCM:DRP21[4]
54 ----------------------------MMCM:DRP21[3]MMCM:DRP21[2]
55 ----------------------------MMCM:DRP21[1]MMCM:DRP21[0]
56 ----------------------------MMCM:DRP20[15]MMCM:DRP20[14]
57 ----------------------------MMCM:DRP20[13]MMCM:DRP20[12]
58 ----------------------------MMCM:DRP20[11]MMCM:DRP20[10]
59 ----------------------------MMCM:DRP20[9]MMCM:DRP20[8]
60 ----------------------------MMCM:DRP20[7]MMCM:DRP20[6]
61 ----------------------------MMCM:DRP20[5]MMCM:DRP20[4]
62 ----------------------------MMCM:DRP20[3]MMCM:DRP20[2]
63 ----------------------------MMCM:DRP20[1]MMCM:DRP20[0]
CMT bittile 12
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP1F[15]MMCM:DRP1F[14]
1 ----------------------------MMCM:DRP1F[13]MMCM:DRP1F[12]
2 ----------------------------MMCM:DRP1F[11]MMCM:DRP1F[10]
3 ----------------------------MMCM:DRP1F[9]
MMCM:DVDD_COMP_SET[2]		MMCM:DRP1F[8]
MMCM:DVDD_COMP_SET[1]
4 ----------------------------MMCM:DRP1F[7]
MMCM:DVDD_COMP_SET[0]		MMCM:DRP1F[6]
MMCM:DVDD_VBG_PD[2]
5 ----------------------------MMCM:DRP1F[5]
MMCM:DVDD_VBG_PD[1]		MMCM:DRP1F[4]
MMCM:DVDD_VBG_PD[0]
6 ----------------------------MMCM:DRP1F[3]
MMCM:DVDD_VBG_SEL[3]		MMCM:DRP1F[2]
MMCM:DVDD_VBG_SEL[2]
7 ----------------------------MMCM:DRP1F[1]
MMCM:DVDD_VBG_SEL[1]		MMCM:DRP1F[0]
MMCM:DVDD_VBG_SEL[0]
8 ----------------------------MMCM:DRP1E[15]
MMCM:SUP_SEL_DREG		MMCM:DRP1E[14]
MMCM:SEL_LV_NMOS
9 ----------------------------MMCM:DRP1E[13]MMCM:DRP1E[12]
10 ----------------------------MMCM:DRP1E[11]MMCM:DRP1E[10]
11 ----------------------------MMCM:DRP1E[9]MMCM:DRP1E[8]
12 ----------------------------MMCM:DRP1E[7]MMCM:DRP1E[6]
13 ----------------------------MMCM:DRP1E[5]MMCM:DRP1E[4]
14 ----------------------------MMCM:DRP1E[3]MMCM:DRP1E[2]
15 ----------------------------MMCM:DRP1E[1]MMCM:DRP1E[0]
16 ----------------------------MMCM:DRP1D[15]MMCM:DRP1D[14]
17 ----------------------------MMCM:DRP1D[13]MMCM:DRP1D[12]
18 ----------------------------MMCM:DRP1D[11]
MMCM:SEL_SLIPD		MMCM:DRP1D[10]
MMCM:PFD[6]
19 ----------------------------MMCM:DRP1D[9]
MMCM:PFD[5]		MMCM:DRP1D[8]
MMCM:PFD[4]
20 ----------------------------MMCM:DRP1D[7]
MMCM:PFD[3]		MMCM:DRP1D[6]
MMCM:PFD[2]
21 ----------------------------MMCM:DRP1D[5]
MMCM:PFD[1]		MMCM:DRP1D[4]
MMCM:PFD[0]
22 ----------------------------MMCM:DRP1D[3]MMCM:DRP1D[2]
23 ----------------------------MMCM:DRP1D[1]MMCM:DRP1D[0]
24 ----------------------------MMCM:DRP1C[15]MMCM:DRP1C[14]
25 ----------------------------MMCM:DRP1C[13]MMCM:DRP1C[12]
26 ----------------------------MMCM:DRP1C[11]MMCM:DRP1C[10]
27 ----------------------------MMCM:DRP1C[9]MMCM:DRP1C[8]
28 ----------------------------MMCM:DRP1C[7]MMCM:DRP1C[6]
29 ----------------------------MMCM:DRP1C[5]MMCM:DRP1C[4]
MMCM:SPARE_DIGITAL[4]
30 ----------------------------MMCM:DRP1C[3]
MMCM:SPARE_DIGITAL[3]		MMCM:DRP1C[2]
MMCM:SPARE_DIGITAL[2]
31 ----------------------------MMCM:DRP1C[1]
MMCM:SPARE_DIGITAL[1]		MMCM:DRP1C[0]
MMCM:SPARE_DIGITAL[0]
32 ----------------------------MMCM:DRP1B[15]MMCM:DRP1B[14]
33 ----------------------------MMCM:DRP1B[13]MMCM:DRP1B[12]
34 ----------------------------MMCM:DRP1B[11]MMCM:DRP1B[10]
35 ----------------------------MMCM:DRP1B[9]MMCM:DRP1B[8]
36 ----------------------------MMCM:DRP1B[7]MMCM:DRP1B[6]
37 ----------------------------MMCM:DRP1B[5]MMCM:DRP1B[4]
38 ----------------------------MMCM:DRP1B[3]MMCM:DRP1B[2]
39 ----------------------------MMCM:DRP1B[1]MMCM:DRP1B[0]
MMCM:FREQ_COMP[1]
40 ----------------------------MMCM:DRP1A[15]
MMCM:FREQ_COMP[0]		MMCM:DRP1A[14]
MMCM:LOCK_REF_DLY[4]
41 ----------------------------MMCM:DRP1A[13]
MMCM:LOCK_REF_DLY[3]		MMCM:DRP1A[12]
MMCM:LOCK_REF_DLY[2]
42 ----------------------------MMCM:DRP1A[11]
MMCM:LOCK_REF_DLY[1]		MMCM:DRP1A[10]
MMCM:LOCK_REF_DLY[0]
43 ----------------------------MMCM:DRP1A[9]
MMCM:LOCK_SAT_HIGH[9]		MMCM:DRP1A[8]
MMCM:LOCK_SAT_HIGH[8]
44 ----------------------------MMCM:DRP1A[7]
MMCM:LOCK_SAT_HIGH[7]		MMCM:DRP1A[6]
MMCM:LOCK_SAT_HIGH[6]
45 ----------------------------MMCM:DRP1A[5]
MMCM:LOCK_SAT_HIGH[5]		MMCM:DRP1A[4]
MMCM:LOCK_SAT_HIGH[4]
46 ----------------------------MMCM:DRP1A[3]
MMCM:LOCK_SAT_HIGH[3]		MMCM:DRP1A[2]
MMCM:LOCK_SAT_HIGH[2]
47 ----------------------------MMCM:DRP1A[1]
MMCM:LOCK_SAT_HIGH[1]		MMCM:DRP1A[0]
MMCM:LOCK_SAT_HIGH[0]
48 ----------------------------MMCM:DRP19[15]MMCM:DRP19[14]
MMCM:LOCK_FB_DLY[4]
49 ----------------------------MMCM:DRP19[13]
MMCM:LOCK_FB_DLY[3]		MMCM:DRP19[12]
MMCM:LOCK_FB_DLY[2]
50 ----------------------------MMCM:DRP19[11]
MMCM:LOCK_FB_DLY[1]		MMCM:DRP19[10]
MMCM:LOCK_FB_DLY[0]
51 ----------------------------MMCM:DRP19[9]
MMCM:UNLOCK_CNT[9]		MMCM:DRP19[8]
MMCM:UNLOCK_CNT[8]
52 ----------------------------MMCM:DRP19[7]
MMCM:UNLOCK_CNT[7]		MMCM:DRP19[6]
MMCM:UNLOCK_CNT[6]
53 ----------------------------MMCM:DRP19[5]
MMCM:UNLOCK_CNT[5]		MMCM:DRP19[4]
MMCM:UNLOCK_CNT[4]
54 ----------------------------MMCM:DRP19[3]
MMCM:UNLOCK_CNT[3]		MMCM:DRP19[2]
MMCM:UNLOCK_CNT[2]
55 ----------------------------MMCM:DRP19[1]
MMCM:UNLOCK_CNT[1]		MMCM:DRP19[0]
MMCM:UNLOCK_CNT[0]
56 ----------------------------MMCM:DRP18[15]MMCM:DRP18[14]
57 ----------------------------MMCM:DRP18[13]MMCM:DRP18[12]
58 ----------------------------MMCM:DRP18[11]MMCM:DRP18[10]
59 ----------------------------MMCM:DRP18[9]
MMCM:LOCK_CNT[9]		MMCM:DRP18[8]
MMCM:LOCK_CNT[8]
60 ----------------------------MMCM:DRP18[7]
MMCM:LOCK_CNT[7]		MMCM:DRP18[6]
MMCM:LOCK_CNT[6]
61 ----------------------------MMCM:DRP18[5]
MMCM:LOCK_CNT[5]		MMCM:DRP18[4]
MMCM:LOCK_CNT[4]
62 ----------------------------MMCM:DRP18[3]
MMCM:LOCK_CNT[3]		MMCM:DRP18[2]
MMCM:LOCK_CNT[2]
63 ----------------------------MMCM:DRP18[1]
MMCM:LOCK_CNT[1]		MMCM:DRP18[0]
MMCM:LOCK_CNT[0]
CMT bittile 13
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP17[15]MMCM:DRP17[14]
1 ----------------------------MMCM:CLKFBIN_EDGE
MMCM:DRP17[13]		MMCM:CLKFBIN_NOCOUNT
MMCM:DRP17[12]
2 ----------------------------MMCM:CLKFBIN_HT[5]
MMCM:DRP17[11]		MMCM:CLKFBIN_HT[4]
MMCM:DRP17[10]
3 ----------------------------MMCM:CLKFBIN_HT[3]
MMCM:DRP17[9]		MMCM:CLKFBIN_HT[2]
MMCM:DRP17[8]
4 ----------------------------MMCM:CLKFBIN_HT[1]
MMCM:DRP17[7]		MMCM:CLKFBIN_HT[0]
MMCM:DRP17[6]
5 ----------------------------MMCM:CLKFBIN_LT[5]
MMCM:DRP17[5]		MMCM:CLKFBIN_LT[4]
MMCM:DRP17[4]
6 ----------------------------MMCM:CLKFBIN_LT[3]
MMCM:DRP17[3]		MMCM:CLKFBIN_LT[2]
MMCM:DRP17[2]
7 ----------------------------MMCM:CLKFBIN_LT[1]
MMCM:DRP17[1]		MMCM:CLKFBIN_LT[0]
MMCM:DRP17[0]
8 ----------------------------MMCM:DRP16[15]MMCM:DRP16[14]
9 ----------------------------MMCM:DIVCLK_EDGE
MMCM:DRP16[13]		MMCM:DIVCLK_NOCOUNT
MMCM:DRP16[12]
10 ----------------------------MMCM:DIVCLK_HT[5]
MMCM:DRP16[11]		MMCM:DIVCLK_HT[4]
MMCM:DRP16[10]
11 ----------------------------MMCM:DIVCLK_HT[3]
MMCM:DRP16[9]		MMCM:DIVCLK_HT[2]
MMCM:DRP16[8]
12 ----------------------------MMCM:DIVCLK_HT[1]
MMCM:DRP16[7]		MMCM:DIVCLK_HT[0]
MMCM:DRP16[6]
13 ----------------------------MMCM:DIVCLK_LT[5]
MMCM:DRP16[5]		MMCM:DIVCLK_LT[4]
MMCM:DRP16[4]
14 ----------------------------MMCM:DIVCLK_LT[3]
MMCM:DRP16[3]		MMCM:DIVCLK_LT[2]
MMCM:DRP16[2]
15 ----------------------------MMCM:DIVCLK_LT[1]
MMCM:DRP16[1]		MMCM:DIVCLK_LT[0]
MMCM:DRP16[0]
16 ----------------------------MMCM:DRP15[15]MMCM:CLKFBOUT_FRAC[2]
MMCM:DRP15[14]
17 ----------------------------MMCM:CLKFBOUT_FRAC[1]
MMCM:DRP15[13]		MMCM:CLKFBOUT_FRAC[0]
MMCM:DRP15[12]
18 ----------------------------MMCM:CLKFBOUT_FRAC_EN
MMCM:DRP15[11]		MMCM:CLKFBOUT_FRAC_WF_RISE
MMCM:DRP15[10]
19 ----------------------------MMCM:CLKFBOUT_MX[1]
MMCM:DRP15[9]		MMCM:CLKFBOUT_MX[0]
MMCM:CLKFBOUT_USE_FINE_PS
MMCM:DRP15[8]
20 ----------------------------MMCM:CLKFBOUT_EDGE
MMCM:DRP15[7]		MMCM:CLKFBOUT_NOCOUNT
MMCM:DRP15[6]
21 ----------------------------MMCM:CLKFBOUT_DT[5]
MMCM:DRP15[5]		MMCM:CLKFBOUT_DT[4]
MMCM:DRP15[4]
22 ----------------------------MMCM:CLKFBOUT_DT[3]
MMCM:DRP15[3]		MMCM:CLKFBOUT_DT[2]
MMCM:DRP15[2]
23 ----------------------------MMCM:CLKFBOUT_DT[1]
MMCM:DRP15[1]		MMCM:CLKFBOUT_DT[0]
MMCM:DRP15[0]
24 ----------------------------MMCM:CLKFBOUT_PM_RISE[2]
MMCM:DRP14[15]		MMCM:CLKFBOUT_PM_RISE[1]
MMCM:DRP14[14]
25 ----------------------------MMCM:CLKFBOUT_PM_RISE[0]
MMCM:DRP14[13]		MMCM:CLKFBOUT_EN
MMCM:DRP14[12]
26 ----------------------------MMCM:CLKFBOUT_HT[5]
MMCM:DRP14[11]		MMCM:CLKFBOUT_HT[4]
MMCM:DRP14[10]
27 ----------------------------MMCM:CLKFBOUT_HT[3]
MMCM:DRP14[9]		MMCM:CLKFBOUT_HT[2]
MMCM:DRP14[8]
28 ----------------------------MMCM:CLKFBOUT_HT[1]
MMCM:DRP14[7]		MMCM:CLKFBOUT_HT[0]
MMCM:DRP14[6]
29 ----------------------------MMCM:CLKFBOUT_LT[5]
MMCM:DRP14[5]		MMCM:CLKFBOUT_LT[4]
MMCM:DRP14[4]
30 ----------------------------MMCM:CLKFBOUT_LT[3]
MMCM:DRP14[3]		MMCM:CLKFBOUT_LT[2]
MMCM:DRP14[2]
31 ----------------------------MMCM:CLKFBOUT_LT[1]
MMCM:DRP14[1]		MMCM:CLKFBOUT_LT[0]
MMCM:DRP14[0]
32 ----------------------------MMCM:DRP13[15]MMCM:DRP13[14]
33 ----------------------------MMCM:CLKFBOUT_PM_FALL[2]
MMCM:DRP13[13]		MMCM:CLKFBOUT_PM_FALL[1]
MMCM:DRP13[12]
34 ----------------------------MMCM:CLKFBOUT_PM_FALL[0]
MMCM:DRP13[11]		MMCM:CLKFBOUT_FRAC_WF_FALL
MMCM:DRP13[10]
35 ----------------------------MMCM:CLKOUT6_MX[1]
MMCM:DRP13[9]		MMCM:CLKOUT6_MX[0]
MMCM:CLKOUT6_USE_FINE_PS
MMCM:DRP13[8]
36 ----------------------------MMCM:CLKOUT6_EDGE
MMCM:DRP13[7]		MMCM:CLKOUT6_NOCOUNT
MMCM:DRP13[6]
37 ----------------------------MMCM:CLKOUT6_DT[5]
MMCM:DRP13[5]		MMCM:CLKOUT6_DT[4]
MMCM:DRP13[4]
38 ----------------------------MMCM:CLKOUT6_DT[3]
MMCM:DRP13[3]		MMCM:CLKOUT6_DT[2]
MMCM:DRP13[2]
39 ----------------------------MMCM:CLKOUT6_DT[1]
MMCM:DRP13[1]		MMCM:CLKOUT6_DT[0]
MMCM:DRP13[0]
40 ----------------------------MMCM:CLKOUT6_PM[2]
MMCM:DRP12[15]		MMCM:CLKOUT6_PM[1]
MMCM:DRP12[14]
41 ----------------------------MMCM:CLKOUT6_PM[0]
MMCM:DRP12[13]		MMCM:CLKOUT6_EN
MMCM:DRP12[12]
42 ----------------------------MMCM:CLKOUT6_HT[5]
MMCM:DRP12[11]		MMCM:CLKOUT6_HT[4]
MMCM:DRP12[10]
43 ----------------------------MMCM:CLKOUT6_HT[3]
MMCM:DRP12[9]		MMCM:CLKOUT6_HT[2]
MMCM:DRP12[8]
44 ----------------------------MMCM:CLKOUT6_HT[1]
MMCM:DRP12[7]		MMCM:CLKOUT6_HT[0]
MMCM:DRP12[6]
45 ----------------------------MMCM:CLKOUT6_LT[5]
MMCM:DRP12[5]		MMCM:CLKOUT6_LT[4]
MMCM:DRP12[4]
46 ----------------------------MMCM:CLKOUT6_LT[3]
MMCM:DRP12[3]		MMCM:CLKOUT6_LT[2]
MMCM:DRP12[2]
47 ----------------------------MMCM:CLKOUT6_LT[1]
MMCM:DRP12[1]		MMCM:CLKOUT6_LT[0]
MMCM:DRP12[0]
48 ----------------------------MMCM:DRP11[15]MMCM:DRP11[14]
49 ----------------------------MMCM:DRP11[13]MMCM:DRP11[12]
50 ----------------------------MMCM:DRP11[11]MMCM:DRP11[10]
51 ----------------------------MMCM:CLKOUT4_CASCADE
MMCM:CLKOUT4_MX[1]
MMCM:DRP11[9]		MMCM:CLKOUT4_MX[0]
MMCM:CLKOUT4_USE_FINE_PS
MMCM:DRP11[8]
52 ----------------------------MMCM:CLKOUT4_EDGE
MMCM:DRP11[7]		MMCM:CLKOUT4_NOCOUNT
MMCM:DRP11[6]
53 ----------------------------MMCM:CLKOUT4_DT[5]
MMCM:DRP11[5]		MMCM:CLKOUT4_DT[4]
MMCM:DRP11[4]
54 ----------------------------MMCM:CLKOUT4_DT[3]
MMCM:DRP11[3]		MMCM:CLKOUT4_DT[2]
MMCM:DRP11[2]
55 ----------------------------MMCM:CLKOUT4_DT[1]
MMCM:DRP11[1]		MMCM:CLKOUT4_DT[0]
MMCM:DRP11[0]
56 ----------------------------MMCM:CLKOUT4_PM[2]
MMCM:DRP10[15]		MMCM:CLKOUT4_PM[1]
MMCM:DRP10[14]
57 ----------------------------MMCM:CLKOUT4_PM[0]
MMCM:DRP10[13]		MMCM:CLKOUT4_EN
MMCM:DRP10[12]
58 ----------------------------MMCM:CLKOUT4_HT[5]
MMCM:DRP10[11]		MMCM:CLKOUT4_HT[4]
MMCM:DRP10[10]
59 ----------------------------MMCM:CLKOUT4_HT[3]
MMCM:DRP10[9]		MMCM:CLKOUT4_HT[2]
MMCM:DRP10[8]
60 ----------------------------MMCM:CLKOUT4_HT[1]
MMCM:DRP10[7]		MMCM:CLKOUT4_HT[0]
MMCM:DRP10[6]
61 ----------------------------MMCM:CLKOUT4_LT[5]
MMCM:DRP10[5]		MMCM:CLKOUT4_LT[4]
MMCM:DRP10[4]
62 ----------------------------MMCM:CLKOUT4_LT[3]
MMCM:DRP10[3]		MMCM:CLKOUT4_LT[2]
MMCM:DRP10[2]
63 ----------------------------MMCM:CLKOUT4_LT[1]
MMCM:DRP10[1]		MMCM:CLKOUT4_LT[0]
MMCM:DRP10[0]
CMT bittile 14
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP0F[15]MMCM:DRP0F[14]
1 ----------------------------MMCM:DRP0F[13]MMCM:DRP0F[12]
2 ----------------------------MMCM:DRP0F[11]MMCM:DRP0F[10]
3 ----------------------------MMCM:CLKOUT3_MX[1]
MMCM:DRP0F[9]		MMCM:CLKOUT3_MX[0]
MMCM:CLKOUT3_USE_FINE_PS
MMCM:DRP0F[8]
4 ----------------------------MMCM:CLKOUT3_EDGE
MMCM:DRP0F[7]		MMCM:CLKOUT3_NOCOUNT
MMCM:DRP0F[6]
5 ----------------------------MMCM:CLKOUT3_DT[5]
MMCM:DRP0F[5]		MMCM:CLKOUT3_DT[4]
MMCM:DRP0F[4]
6 ----------------------------MMCM:CLKOUT3_DT[3]
MMCM:DRP0F[3]		MMCM:CLKOUT3_DT[2]
MMCM:DRP0F[2]
7 ----------------------------MMCM:CLKOUT3_DT[1]
MMCM:DRP0F[1]		MMCM:CLKOUT3_DT[0]
MMCM:DRP0F[0]
8 ----------------------------MMCM:CLKOUT3_PM[2]
MMCM:DRP0E[15]		MMCM:CLKOUT3_PM[1]
MMCM:DRP0E[14]
9 ----------------------------MMCM:CLKOUT3_PM[0]
MMCM:DRP0E[13]		MMCM:CLKOUT3_EN
MMCM:DRP0E[12]
10 ----------------------------MMCM:CLKOUT3_HT[5]
MMCM:DRP0E[11]		MMCM:CLKOUT3_HT[4]
MMCM:DRP0E[10]
11 ----------------------------MMCM:CLKOUT3_HT[3]
MMCM:DRP0E[9]		MMCM:CLKOUT3_HT[2]
MMCM:DRP0E[8]
12 ----------------------------MMCM:CLKOUT3_HT[1]
MMCM:DRP0E[7]		MMCM:CLKOUT3_HT[0]
MMCM:DRP0E[6]
13 ----------------------------MMCM:CLKOUT3_LT[5]
MMCM:DRP0E[5]		MMCM:CLKOUT3_LT[4]
MMCM:DRP0E[4]
14 ----------------------------MMCM:CLKOUT3_LT[3]
MMCM:DRP0E[3]		MMCM:CLKOUT3_LT[2]
MMCM:DRP0E[2]
15 ----------------------------MMCM:CLKOUT3_LT[1]
MMCM:DRP0E[1]		MMCM:CLKOUT3_LT[0]
MMCM:DRP0E[0]
16 ----------------------------MMCM:DRP0D[15]MMCM:DRP0D[14]
17 ----------------------------MMCM:DRP0D[13]MMCM:DRP0D[12]
18 ----------------------------MMCM:DRP0D[11]MMCM:DRP0D[10]
19 ----------------------------MMCM:CLKOUT2_MX[1]
MMCM:DRP0D[9]		MMCM:CLKOUT2_MX[0]
MMCM:CLKOUT2_USE_FINE_PS
MMCM:DRP0D[8]
20 ----------------------------MMCM:CLKOUT2_EDGE
MMCM:DRP0D[7]		MMCM:CLKOUT2_NOCOUNT
MMCM:DRP0D[6]
21 ----------------------------MMCM:CLKOUT2_DT[5]
MMCM:DRP0D[5]		MMCM:CLKOUT2_DT[4]
MMCM:DRP0D[4]
22 ----------------------------MMCM:CLKOUT2_DT[3]
MMCM:DRP0D[3]		MMCM:CLKOUT2_DT[2]
MMCM:DRP0D[2]
23 ----------------------------MMCM:CLKOUT2_DT[1]
MMCM:DRP0D[1]		MMCM:CLKOUT2_DT[0]
MMCM:DRP0D[0]
24 ----------------------------MMCM:CLKOUT2_PM[2]
MMCM:DRP0C[15]		MMCM:CLKOUT2_PM[1]
MMCM:DRP0C[14]
25 ----------------------------MMCM:CLKOUT2_PM[0]
MMCM:DRP0C[13]		MMCM:CLKOUT2_EN
MMCM:DRP0C[12]
26 ----------------------------MMCM:CLKOUT2_HT[5]
MMCM:DRP0C[11]		MMCM:CLKOUT2_HT[4]
MMCM:DRP0C[10]
27 ----------------------------MMCM:CLKOUT2_HT[3]
MMCM:DRP0C[9]		MMCM:CLKOUT2_HT[2]
MMCM:DRP0C[8]
28 ----------------------------MMCM:CLKOUT2_HT[1]
MMCM:DRP0C[7]		MMCM:CLKOUT2_HT[0]
MMCM:DRP0C[6]
29 ----------------------------MMCM:CLKOUT2_LT[5]
MMCM:DRP0C[5]		MMCM:CLKOUT2_LT[4]
MMCM:DRP0C[4]
30 ----------------------------MMCM:CLKOUT2_LT[3]
MMCM:DRP0C[3]		MMCM:CLKOUT2_LT[2]
MMCM:DRP0C[2]
31 ----------------------------MMCM:CLKOUT2_LT[1]
MMCM:DRP0C[1]		MMCM:CLKOUT2_LT[0]
MMCM:DRP0C[0]
32 ----------------------------MMCM:DRP0B[15]MMCM:DRP0B[14]
33 ----------------------------MMCM:DRP0B[13]MMCM:DRP0B[12]
34 ----------------------------MMCM:DRP0B[11]MMCM:DRP0B[10]
35 ----------------------------MMCM:CLKOUT1_MX[1]
MMCM:DRP0B[9]		MMCM:CLKOUT1_MX[0]
MMCM:CLKOUT1_USE_FINE_PS
MMCM:DRP0B[8]
36 ----------------------------MMCM:CLKOUT1_EDGE
MMCM:DRP0B[7]		MMCM:CLKOUT1_NOCOUNT
MMCM:DRP0B[6]
37 ----------------------------MMCM:CLKOUT1_DT[5]
MMCM:DRP0B[5]		MMCM:CLKOUT1_DT[4]
MMCM:DRP0B[4]
38 ----------------------------MMCM:CLKOUT1_DT[3]
MMCM:DRP0B[3]		MMCM:CLKOUT1_DT[2]
MMCM:DRP0B[2]
39 ----------------------------MMCM:CLKOUT1_DT[1]
MMCM:DRP0B[1]		MMCM:CLKOUT1_DT[0]
MMCM:DRP0B[0]
40 ----------------------------MMCM:CLKOUT1_PM[2]
MMCM:DRP0A[15]		MMCM:CLKOUT1_PM[1]
MMCM:DRP0A[14]
41 ----------------------------MMCM:CLKOUT1_PM[0]
MMCM:DRP0A[13]		MMCM:CLKOUT1_EN
MMCM:DRP0A[12]
42 ----------------------------MMCM:CLKOUT1_HT[5]
MMCM:DRP0A[11]		MMCM:CLKOUT1_HT[4]
MMCM:DRP0A[10]
43 ----------------------------MMCM:CLKOUT1_HT[3]
MMCM:DRP0A[9]		MMCM:CLKOUT1_HT[2]
MMCM:DRP0A[8]
44 ----------------------------MMCM:CLKOUT1_HT[1]
MMCM:DRP0A[7]		MMCM:CLKOUT1_HT[0]
MMCM:DRP0A[6]
45 ----------------------------MMCM:CLKOUT1_LT[5]
MMCM:DRP0A[5]		MMCM:CLKOUT1_LT[4]
MMCM:DRP0A[4]
46 ----------------------------MMCM:CLKOUT1_LT[3]
MMCM:DRP0A[3]		MMCM:CLKOUT1_LT[2]
MMCM:DRP0A[2]
47 ----------------------------MMCM:CLKOUT1_LT[1]
MMCM:DRP0A[1]		MMCM:CLKOUT1_LT[0]
MMCM:DRP0A[0]
48 ----------------------------MMCM:DRP09[15]MMCM:CLKOUT0_FRAC[2]
MMCM:DRP09[14]
49 ----------------------------MMCM:CLKOUT0_FRAC[1]
MMCM:DRP09[13]		MMCM:CLKOUT0_FRAC[0]
MMCM:DRP09[12]
50 ----------------------------MMCM:CLKOUT0_FRAC_EN
MMCM:DRP09[11]		MMCM:CLKOUT0_FRAC_WF_RISE
MMCM:DRP09[10]
51 ----------------------------MMCM:CLKOUT0_MX[1]
MMCM:DRP09[9]		MMCM:CLKOUT0_MX[0]
MMCM:CLKOUT0_USE_FINE_PS
MMCM:DRP09[8]
52 ----------------------------MMCM:CLKOUT0_EDGE
MMCM:DRP09[7]		MMCM:CLKOUT0_NOCOUNT
MMCM:DRP09[6]
53 ----------------------------MMCM:CLKOUT0_DT[5]
MMCM:DRP09[5]		MMCM:CLKOUT0_DT[4]
MMCM:DRP09[4]
54 ----------------------------MMCM:CLKOUT0_DT[3]
MMCM:DRP09[3]		MMCM:CLKOUT0_DT[2]
MMCM:DRP09[2]
55 ----------------------------MMCM:CLKOUT0_DT[1]
MMCM:DRP09[1]		MMCM:CLKOUT0_DT[0]
MMCM:DRP09[0]
56 ----------------------------MMCM:CLKOUT0_PM_RISE[2]
MMCM:DRP08[15]		MMCM:CLKOUT0_PM_RISE[1]
MMCM:DRP08[14]
57 ----------------------------MMCM:CLKOUT0_PM_RISE[0]
MMCM:DRP08[13]		MMCM:CLKOUT0_EN
MMCM:DRP08[12]
58 ----------------------------MMCM:CLKOUT0_HT[5]
MMCM:DRP08[11]		MMCM:CLKOUT0_HT[4]
MMCM:DRP08[10]
59 ----------------------------MMCM:CLKOUT0_HT[3]
MMCM:DRP08[9]		MMCM:CLKOUT0_HT[2]
MMCM:DRP08[8]
60 ----------------------------MMCM:CLKOUT0_HT[1]
MMCM:DRP08[7]		MMCM:CLKOUT0_HT[0]
MMCM:DRP08[6]
61 ----------------------------MMCM:CLKOUT0_LT[5]
MMCM:DRP08[5]		MMCM:CLKOUT0_LT[4]
MMCM:DRP08[4]
62 ----------------------------MMCM:CLKOUT0_LT[3]
MMCM:DRP08[3]		MMCM:CLKOUT0_LT[2]
MMCM:DRP08[2]
63 ----------------------------MMCM:CLKOUT0_LT[1]
MMCM:DRP08[1]		MMCM:CLKOUT0_LT[0]
MMCM:DRP08[0]
CMT bittile 15
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------MMCM:DRP07[15]MMCM:DRP07[14]
1 ----------------------------MMCM:CLKOUT0_PM_FALL[2]
MMCM:DRP07[13]		MMCM:CLKOUT0_PM_FALL[1]
MMCM:DRP07[12]
2 ----------------------------MMCM:CLKOUT0_PM_FALL[0]
MMCM:DRP07[11]		MMCM:CLKOUT0_FRAC_WF_FALL
MMCM:DRP07[10]
3 ----------------------------MMCM:CLKOUT5_MX[1]
MMCM:DRP07[9]		MMCM:CLKOUT5_MX[0]
MMCM:CLKOUT5_USE_FINE_PS
MMCM:DRP07[8]
4 ----------------------------MMCM:CLKOUT5_EDGE
MMCM:DRP07[7]		MMCM:CLKOUT5_NOCOUNT
MMCM:DRP07[6]
5 ----------------------------MMCM:CLKOUT5_DT[5]
MMCM:DRP07[5]		MMCM:CLKOUT5_DT[4]
MMCM:DRP07[4]
6 ----------------------------MMCM:CLKOUT5_DT[3]
MMCM:DRP07[3]		MMCM:CLKOUT5_DT[2]
MMCM:DRP07[2]
7 ----------------------------MMCM:CLKOUT5_DT[1]
MMCM:DRP07[1]		MMCM:CLKOUT5_DT[0]
MMCM:DRP07[0]
8 ----------------------------MMCM:CLKOUT5_PM[2]
MMCM:DRP06[15]		MMCM:CLKOUT5_PM[1]
MMCM:DRP06[14]
9 ----------------------------MMCM:CLKOUT5_PM[0]
MMCM:DRP06[13]		MMCM:CLKOUT5_EN
MMCM:DRP06[12]
10 ----------------------------MMCM:CLKOUT5_HT[5]
MMCM:DRP06[11]		MMCM:CLKOUT5_HT[4]
MMCM:DRP06[10]
11 ----------------------------MMCM:CLKOUT5_HT[3]
MMCM:DRP06[9]		MMCM:CLKOUT5_HT[2]
MMCM:DRP06[8]
12 ----------------------------MMCM:CLKOUT5_HT[1]
MMCM:DRP06[7]		MMCM:CLKOUT5_HT[0]
MMCM:DRP06[6]
13 ----------------------------MMCM:CLKOUT5_LT[5]
MMCM:DRP06[5]		MMCM:CLKOUT5_LT[4]
MMCM:DRP06[4]
14 ----------------------------MMCM:CLKOUT5_LT[3]
MMCM:DRP06[3]		MMCM:CLKOUT5_LT[2]
MMCM:DRP06[2]
15 ----------------------------MMCM:CLKOUT5_LT[1]
MMCM:DRP06[1]		MMCM:CLKOUT5_LT[0]
MMCM:DRP06[0]
16 ----------------------------MMCM:DRP05[15]
MMCM:IN_DLY_SET[5]		MMCM:DRP05[14]
MMCM:IN_DLY_SET[4]
17 ----------------------------MMCM:DRP05[13]
MMCM:IN_DLY_SET[3]		MMCM:DRP05[12]
MMCM:IN_DLY_SET[2]
18 ----------------------------MMCM:DRP05[11]
MMCM:IN_DLY_SET[1]		MMCM:DRP05[10]
MMCM:IN_DLY_SET[0]
19 ----------------------------MMCM:DRP05[9]
MMCM:IN_DLY_MX_DVDD[5]		MMCM:DRP05[8]
MMCM:IN_DLY_MX_DVDD[4]
20 ----------------------------MMCM:DRP05[7]
MMCM:IN_DLY_MX_DVDD[3]		MMCM:DRP05[6]
MMCM:IN_DLY_MX_DVDD[2]
21 ----------------------------MMCM:DRP05[5]
MMCM:IN_DLY_MX_DVDD[1]		MMCM:DRP05[4]
MMCM:IN_DLY_MX_DVDD[0]
22 ----------------------------MMCM:DIRECT_PATH_CNTRL
MMCM:DRP05[3]		MMCM:DRP05[2]
MMCM:IN_DLY_EN
23 ----------------------------MMCM:DRP05[1]MMCM:DRP05[0]
24 ----------------------------MMCM:DRP04[15]
MMCM:TMUX_MUX_SEL[1]		MMCM:DRP04[14]
MMCM:TMUX_MUX_SEL[0]
25 ----------------------------MMCM:CLKBURST_REPEAT
MMCM:DRP04[13]		MMCM:CLKBURST_ENABLE
MMCM:DRP04[12]
26 ----------------------------MMCM:CLKBURST_CNT[3]
MMCM:DRP04[11]		MMCM:CLKBURST_CNT[2]
MMCM:DRP04[10]
27 ----------------------------MMCM:CLKBURST_CNT[1]
MMCM:DRP04[9]		MMCM:CLKBURST_CNT[0]
MMCM:DRP04[8]
28 ----------------------------MMCM:DRP04[7]MMCM:DRP04[6]
29 ----------------------------MMCM:DRP04[5]
MMCM:SS_STEPS_INIT[2]		MMCM:DRP04[4]
MMCM:SS_STEPS_INIT[1]
30 ----------------------------MMCM:DRP04[3]
MMCM:SS_STEPS_INIT[0]		MMCM:DRP04[2]
MMCM:SS_STEPS[2]
31 ----------------------------MMCM:DRP04[1]
MMCM:SS_STEPS[1]		MMCM:DRP04[0]
MMCM:SS_STEPS[0]
32 ----------------------------MMCM:DRP03[15]
MMCM:MUX.PERF3[0]		MMCM:DRP03[14]
MMCM:MUX.PERF3[1]
33 ----------------------------MMCM:DRP03[13]
MMCM:MUX.PERF3[2]		MMCM:DRP03[12]
MMCM:MUX.PERF2[0]
34 ----------------------------MMCM:DRP03[11]
MMCM:MUX.PERF2[1]		MMCM:DRP03[10]
MMCM:MUX.PERF2[2]
35 ----------------------------MMCM:DRP03[9]
MMCM:MUX.PERF1[0]		MMCM:DRP03[8]
MMCM:MUX.PERF1[1]
36 ----------------------------MMCM:DRP03[7]
MMCM:MUX.PERF1[2]		MMCM:DRP03[6]
MMCM:MUX.PERF0[0]
37 ----------------------------MMCM:DRP03[5]
MMCM:MUX.PERF0[1]		MMCM:DRP03[4]
MMCM:MUX.PERF0[2]
38 ----------------------------MMCM:DRP03[3]
MMCM:SKEW_FLOP_INV[3]		MMCM:DRP03[2]
MMCM:SKEW_FLOP_INV[2]
39 ----------------------------MMCM:DRP03[1]
MMCM:SKEW_FLOP_INV[1]		MMCM:DRP03[0]
MMCM:SKEW_FLOP_INV[0]
40 ----------------------------MMCM:DRP02[15]MMCM:DRP02[14]
41 ----------------------------MMCM:DRP02[13]MMCM:DRP02[12]
42 ----------------------------MMCM:DRP02[11]MMCM:DRP02[10]
43 ----------------------------MMCM:DRP02[9]MMCM:DRP02[8]
44 ----------------------------MMCM:DRP02[7]MMCM:DRP02[6]
45 ----------------------------MMCM:DRP02[5]MMCM:DRP02[4]
46 ----------------------------MMCM:DRP02[3]MMCM:DRP02[2]
47 ----------------------------MMCM:DRP02[1]
MMCM:SYNTH_CLK_DIV[1]		MMCM:DRP02[0]
MMCM:SYNTH_CLK_DIV[0]
48 ----------------------------MMCM:DRP01[15]MMCM:DRP01[14]
49 ----------------------------MMCM:DRP01[13]MMCM:DRP01[12]
50 ----------------------------MMCM:BUF.CLKOUT3_FREQ_BB
MMCM:DRP01[11]		MMCM:BUF.CLKOUT2_FREQ_BB
MMCM:DRP01[10]
51 ----------------------------MMCM:BUF.CLKOUT1_FREQ_BB
MMCM:DRP01[9]		MMCM:BUF.CLKOUT0_FREQ_BB
MMCM:DRP01[8]
52 ----------------------------MMCM:DRP01[7]
MMCM:MUX.CLKFBIN[0]		MMCM:DRP01[6]
MMCM:MUX.CLKFBIN[1]
53 ----------------------------MMCM:DRP01[5]
MMCM:MUX.CLKFBIN[2]		MMCM:DRP01[4]
MMCM:MUX.CLKIN1[0]
54 ----------------------------MMCM:DRP01[3]
MMCM:MUX.CLKIN1[1]		MMCM:DRP01[2]
MMCM:MUX.CLKIN1[2]
55 ----------------------------MMCM:DRP01[1]
MMCM:MUX.CLKIN2[0]		MMCM:DRP01[0]
MMCM:MUX.CLKIN2[1]
56 ----------------------------MMCM:DRP00[15]
MMCM:MUX.CLKIN2[2]		MMCM:DRP00[14]
MMCM:HROW_DLY_SET[2]
57 ----------------------------MMCM:DRP00[13]
MMCM:HROW_DLY_SET[1]		MMCM:DRP00[12]
MMCM:HROW_DLY_SET[0]
58 ----------------------------MMCM:DRP00[11]
MMCM:IN_DLY_MX_CVDD[5]		MMCM:DRP00[10]
MMCM:IN_DLY_MX_CVDD[4]
59 ----------------------------MMCM:DRP00[9]
MMCM:IN_DLY_MX_CVDD[3]		MMCM:DRP00[8]
MMCM:IN_DLY_MX_CVDD[2]
60 ----------------------------MMCM:DRP00[7]
MMCM:IN_DLY_MX_CVDD[1]		MMCM:DRP00[6]
MMCM:IN_DLY_MX_CVDD[0]
61 ----------------------------MMCM:DRP00[5]MMCM:DRP00[4]
62 ----------------------------MMCM:DRP00[3]
MMCM:MUX.PERF3[3]		MMCM:DRP00[2]
MMCM:MUX.PERF2[3]
63 ----------------------------MMCM:DRP00[1]
MMCM:MUX.PERF1[3]		MMCM:DRP00[0]
MMCM:MUX.PERF0[3]
CMT bittile 16
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------CMT_BOT:ENABLE.SYNC_BB_SCMT_BOT:ENABLE.FREQ_BB0[2]
33 ----------------------------CMT_BOT:ENABLE.FREQ_BB1[0]CMT_BOT:ENABLE.FREQ_BB2[2]
34 ----------------------------CMT_BOT:ENABLE.FREQ_BB3[0]CMT_BOT:MUX.FREQ_BB0[0]
35 ----------------------------CMT_BOT:MUX.FREQ_BB1[0]CMT_BOT:MUX.FREQ_BB2[0]
36 ----------------------------CMT_BOT:MUX.FREQ_BB3[0]-
37 ------------------------------
38 ----------------------------CMT_BOT:BUF.SYNC_BB.DCMT_BOT:ENABLE.SYNC_BB
39 ----------------------------CMT_BOT:BUF.SYNC_BB.U-
40 ------------------------------
41 -----------------------------CMT_BOT:ENABLE.FREQ_BB0_S[0]
42 ----------------------------CMT_BOT:ENABLE.FREQ_BB0[0]CMT_BOT:ENABLE.FREQ_BB1_S[0]
43 ----------------------------CMT_BOT:ENABLE.FREQ_BB1[1]CMT_BOT:ENABLE.FREQ_BB2_S[0]
44 ----------------------------CMT_BOT:ENABLE.FREQ_BB2[0]CMT_BOT:ENABLE.FREQ_BB3_S[0]
45 ----------------------------CMT_BOT:ENABLE.FREQ_BB3[1]CMT_BOT:BUF.FREQ_BB0.D[1]
46 ----------------------------CMT_BOT:BUF.FREQ_BB0.U[0]CMT_BOT:BUF.FREQ_BB1.D[1]
47 ----------------------------CMT_BOT:BUF.FREQ_BB1.U[0]CMT_BOT:BUF.FREQ_BB2.D[1]
48 ----------------------------CMT_BOT:BUF.FREQ_BB2.U[0]CMT_BOT:BUF.FREQ_BB3.D[1]
49 ----------------------------CMT_BOT:BUF.FREQ_BB3.U[0]CMT_BOT:ENABLE.FREQ_BB0_S[1]
50 ----------------------------CMT_BOT:ENABLE.FREQ_BB0[1]CMT_BOT:ENABLE.FREQ_BB1_S[1]
51 ----------------------------CMT_BOT:ENABLE.FREQ_BB1[2]CMT_BOT:ENABLE.FREQ_BB2_S[1]
52 ----------------------------CMT_BOT:ENABLE.FREQ_BB2[1]CMT_BOT:ENABLE.FREQ_BB3_S[1]
53 ----------------------------CMT_BOT:ENABLE.FREQ_BB3[2]CMT_BOT:BUF.FREQ_BB0.U[1]
54 ----------------------------CMT_BOT:BUF.FREQ_BB0.D[0]CMT_BOT:BUF.FREQ_BB1.U[1]
55 ----------------------------CMT_BOT:BUF.FREQ_BB1.D[0]CMT_BOT:BUF.FREQ_BB2.U[1]
56 ----------------------------CMT_BOT:BUF.FREQ_BB2.D[0]CMT_BOT:BUF.FREQ_BB3.U[1]
57 ----------------------------CMT_BOT:BUF.FREQ_BB3.D[0]-
58 ------------------------------
59 -----------------------------CMT_BOT:MUX.FREQ_BB0[1]
60 ----------------------------CMT_BOT:MUX.FREQ_BB0[2]CMT_BOT:MUX.FREQ_BB1[1]
61 ----------------------------CMT_BOT:MUX.FREQ_BB1[2]CMT_BOT:MUX.FREQ_BB2[1]
62 ----------------------------CMT_BOT:MUX.FREQ_BB2[2]CMT_BOT:MUX.FREQ_BB3[1]
63 ----------------------------CMT_BOT:MUX.FREQ_BB3[2]-
CMT bittile 17
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PHASER_OUT0:TEST_OPT[0]PHASER_OUT0:TEST_OPT[1]
17 ----------------------------PHASER_OUT0:TEST_OPT[2]PHASER_OUT0:TEST_OPT[3]
18 ----------------------------PHASER_OUT0:TEST_OPT[4]PHASER_OUT0:TEST_OPT[5]
19 ----------------------------PHASER_OUT0:TEST_OPT[6]PHASER_OUT0:TEST_OPT[7]
20 ----------------------------PHASER_OUT0:TEST_OPT[8]PHASER_OUT0:TEST_OPT[9]
21 ----------------------------PHASER_OUT0:TEST_OPT[10]PHASER_OUT0:DATA_RD_CYCLES
22 ----------------------------PHASER_OUT0:OCLKDELAY_INVPHASER_OUT0:PHASER_OUT_EN
23 ----------------------------PHASER_OUT0:EN_OSERDES_RSTPHASER_OUT0:COARSE_BYPASS
24 ----------------------------PHASER_OUT0:OUTPUT_CLK_SRC[0]PHASER_OUT0:OUTPUT_CLK_SRC[1]
25 ----------------------------PHASER_OUT0:STG1_BYPASSPHASER_OUT0:OCLK_DELAY[0]
26 ----------------------------PHASER_OUT0:OCLK_DELAY[1]PHASER_OUT0:OCLK_DELAY[2]
27 ----------------------------PHASER_OUT0:OCLK_DELAY[3]PHASER_OUT0:OCLK_DELAY[4]
28 ----------------------------PHASER_OUT0:OCLK_DELAY[5]PHASER_OUT0:EN_TEST_RING
29 ----------------------------PHASER_OUT0:DATA_CTL_NPHASER_OUT0:CTL_MODE
30 ----------------------------PHASER_OUT0:CLKOUT_DIV[0]PHASER_OUT0:CLKOUT_DIV[1]
31 ----------------------------PHASER_OUT0:CLKOUT_DIV[2]PHASER_OUT0:CLKOUT_DIV[3]
CMT bittile 18
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHASER_OUT0:INV.RSTPHASER_OUT0:MUX.PHASEREFCLK[0]
1 ----------------------------PHASER_OUT0:MUX.PHASEREFCLK[1]PHASER_OUT0:MUX.PHASEREFCLK[2]
2 ----------------------------PHASER_OUT0:MUX.PHASEREFCLK[3]PHASER_OUT0:COARSE_DELAY[0]
3 ----------------------------PHASER_OUT0:COARSE_DELAY[1]PHASER_OUT0:COARSE_DELAY[2]
4 ----------------------------PHASER_OUT0:COARSE_DELAY[3]PHASER_OUT0:COARSE_DELAY[4]
5 ----------------------------PHASER_OUT0:COARSE_DELAY[5]PHASER_OUT0:FINE_DELAY[0]
6 ----------------------------PHASER_OUT0:FINE_DELAY[1]PHASER_OUT0:FINE_DELAY[2]
7 ----------------------------PHASER_OUT0:FINE_DELAY[3]PHASER_OUT0:FINE_DELAY[4]
8 ----------------------------PHASER_OUT0:FINE_DELAY[5]PHASER_OUT0:SYNC_IN_DIV_RST
9 ----------------------------PHASER_OUT0:CLKOUT_DIV_ST[0]PHASER_OUT0:CLKOUT_DIV_ST[1]
10 ----------------------------PHASER_OUT0:CLKOUT_DIV_ST[2]PHASER_OUT0:CLKOUT_DIV_ST[3]
11 ----------------------------PHASER_OUT0:CLKOUT_DIV[4]PHASER_OUT0:CLKOUT_DIV[5]
12 ----------------------------PHASER_OUT0:CLKOUT_DIV[6]PHASER_OUT0:CLKOUT_DIV[7]
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ----------------------------PHASER_IN0:UPDATE_NONACTIVEPHASER_IN0:TEST_BP
49 ----------------------------PHASER_IN0:DQS_AUTO_RECALPHASER_IN0:DQS_BIAS_MODE
50 ----------------------------PHASER_IN0:REG_OPT_1PHASER_IN0:REG_OPT_4
51 ----------------------------PHASER_IN0:RD_ADDR_INIT[0]PHASER_IN0:RD_ADDR_INIT[1]
52 ----------------------------PHASER_IN0:SEL_OUTPHASER_IN0:SEL_CLK_OFFSET[0]
53 ----------------------------PHASER_IN0:SEL_CLK_OFFSET[1]PHASER_IN0:OUTPUT_CLK_SRC[0]
54 ----------------------------PHASER_IN0:OUTPUT_CLK_SRC[1]PHASER_IN0:WR_CYCLES
55 ----------------------------PHASER_IN0:PHASER_IN_ENPHASER_IN0:EN_ISERDES_RST
56 ----------------------------PHASER_IN0:ICLK_TO_RCLK_BYPASSPHASER_IN0:OUTPUT_CLK_SRC[2]
57 ----------------------------PHASER_IN0:OUTPUT_CLK_SRC[3]PHASER_IN0:STG1_PD_UPDATE[0]
58 ----------------------------PHASER_IN0:STG1_PD_UPDATE[1]PHASER_IN0:STG1_PD_UPDATE[2]
59 ----------------------------PHASER_IN0:INV.RSTPHASER_IN0:MUX.PHASEREFCLK[0]
60 ----------------------------PHASER_IN0:HALF_CYCLE_ADJPHASER_IN0:SEL_CLK_OFFSET[2]
61 ----------------------------PHASER_IN0:RST_SELPHASER_IN0:REG_OPT_2
CMT bittile 19
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ----------------------------PHASER_IN0:PD_REVERSE[0]PHASER_IN0:PD_REVERSE[1]
20 ----------------------------PHASER_IN0:PD_REVERSE[2]-
21 ----------------------------PHASER_IN0:FREQ_REF_DIV[0]PHASER_IN0:FREQ_REF_DIV[1]
22 ----------------------------PHASER_IN0:DQS_FIND_PATTERN[0]PHASER_IN0:DQS_FIND_PATTERN[1]
23 ----------------------------PHASER_IN0:DQS_FIND_PATTERN[2]PHASER_IN0:EN_TEST_RING
24 ----------------------------PHASER_IN0:CTL_MODEPHASER_IN0:CLKOUT_DIV[0]
25 ----------------------------PHASER_IN0:CLKOUT_DIV[1]PHASER_IN0:CLKOUT_DIV[2]
26 ----------------------------PHASER_IN0:CLKOUT_DIV[3]PHASER_IN0:BURST_MODE
27 ----------------------------PHASER_IN0:MUX.PHASEREFCLK[1]PHASER_IN0:MUX.PHASEREFCLK[2]
28 ----------------------------PHASER_IN0:MUX.PHASEREFCLK[3]-
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ------------------------------
49 ------------------------------
50 ------------------------------
51 ----------------------------PHASER_IN0:FINE_DELAY[0]PHASER_IN0:FINE_DELAY[1]
52 ----------------------------PHASER_IN0:FINE_DELAY[2]PHASER_IN0:FINE_DELAY[3]
53 ----------------------------PHASER_IN0:FINE_DELAY[4]PHASER_IN0:FINE_DELAY[5]
54 ----------------------------PHASER_IN0:SYNC_IN_DIV_RSTPHASER_IN0:CLKOUT_DIV_ST[0]
55 ----------------------------PHASER_IN0:CLKOUT_DIV_ST[1]PHASER_IN0:CLKOUT_DIV_ST[2]
56 ----------------------------PHASER_IN0:CLKOUT_DIV_ST[3]PHASER_IN0:CLKOUT_DIV[4]
57 ----------------------------PHASER_IN0:CLKOUT_DIV[5]PHASER_IN0:CLKOUT_DIV[6]
58 ----------------------------PHASER_IN0:CLKOUT_DIV[7]-
CMT bittile 20
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ----------------------------PHASER_OUT1:TEST_OPT[0]PHASER_OUT1:TEST_OPT[1]
49 ----------------------------PHASER_OUT1:TEST_OPT[2]PHASER_OUT1:TEST_OPT[3]
50 ----------------------------PHASER_OUT1:TEST_OPT[4]PHASER_OUT1:TEST_OPT[5]
51 ----------------------------PHASER_OUT1:TEST_OPT[6]PHASER_OUT1:TEST_OPT[7]
52 ----------------------------PHASER_OUT1:TEST_OPT[8]PHASER_OUT1:TEST_OPT[9]
53 ----------------------------PHASER_OUT1:TEST_OPT[10]PHASER_OUT1:DATA_RD_CYCLES
54 ----------------------------PHASER_OUT1:OCLKDELAY_INVPHASER_OUT1:PHASER_OUT_EN
55 ----------------------------PHASER_OUT1:EN_OSERDES_RSTPHASER_OUT1:COARSE_BYPASS
56 ----------------------------PHASER_OUT1:OUTPUT_CLK_SRC[0]PHASER_OUT1:OUTPUT_CLK_SRC[1]
57 ----------------------------PHASER_OUT1:STG1_BYPASSPHASER_OUT1:OCLK_DELAY[0]
58 ----------------------------PHASER_OUT1:OCLK_DELAY[1]PHASER_OUT1:OCLK_DELAY[2]
59 ----------------------------PHASER_OUT1:OCLK_DELAY[3]PHASER_OUT1:OCLK_DELAY[4]
60 ----------------------------PHASER_OUT1:OCLK_DELAY[5]PHASER_OUT1:EN_TEST_RING
61 ----------------------------PHASER_OUT1:DATA_CTL_NPHASER_OUT1:CTL_MODE
62 ----------------------------PHASER_OUT1:CLKOUT_DIV[0]PHASER_OUT1:CLKOUT_DIV[1]
63 ----------------------------PHASER_OUT1:CLKOUT_DIV[2]PHASER_OUT1:CLKOUT_DIV[3]
CMT bittile 21
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PHASER_OUT1:INV.RSTPHASER_OUT1:MUX.PHASEREFCLK[0]
33 ----------------------------PHASER_OUT1:MUX.PHASEREFCLK[1]PHASER_OUT1:MUX.PHASEREFCLK[2]
34 ----------------------------PHASER_OUT1:MUX.PHASEREFCLK[3]PHASER_OUT1:COARSE_DELAY[0]
35 ----------------------------PHASER_OUT1:COARSE_DELAY[1]PHASER_OUT1:COARSE_DELAY[2]
36 ----------------------------PHASER_OUT1:COARSE_DELAY[3]PHASER_OUT1:COARSE_DELAY[4]
37 ----------------------------PHASER_OUT1:COARSE_DELAY[5]PHASER_OUT1:FINE_DELAY[0]
38 ----------------------------PHASER_OUT1:FINE_DELAY[1]PHASER_OUT1:FINE_DELAY[2]
39 ----------------------------PHASER_OUT1:FINE_DELAY[3]PHASER_OUT1:FINE_DELAY[4]
40 ----------------------------PHASER_OUT1:FINE_DELAY[5]PHASER_OUT1:SYNC_IN_DIV_RST
41 ----------------------------PHASER_OUT1:CLKOUT_DIV_ST[0]PHASER_OUT1:CLKOUT_DIV_ST[1]
42 ----------------------------PHASER_OUT1:CLKOUT_DIV_ST[2]PHASER_OUT1:CLKOUT_DIV_ST[3]
43 ----------------------------PHASER_OUT1:CLKOUT_DIV[4]PHASER_OUT1:CLKOUT_DIV[5]
44 ----------------------------PHASER_OUT1:CLKOUT_DIV[6]PHASER_OUT1:CLKOUT_DIV[7]
CMT bittile 22
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PHASER_IN1:UPDATE_NONACTIVEPHASER_IN1:TEST_BP
17 ----------------------------PHASER_IN1:DQS_AUTO_RECALPHASER_IN1:DQS_BIAS_MODE
18 ----------------------------PHASER_IN1:REG_OPT_1PHASER_IN1:REG_OPT_4
19 ----------------------------PHASER_IN1:RD_ADDR_INIT[0]PHASER_IN1:RD_ADDR_INIT[1]
20 ----------------------------PHASER_IN1:SEL_OUTPHASER_IN1:SEL_CLK_OFFSET[0]
21 ----------------------------PHASER_IN1:SEL_CLK_OFFSET[1]PHASER_IN1:OUTPUT_CLK_SRC[0]
22 ----------------------------PHASER_IN1:OUTPUT_CLK_SRC[1]PHASER_IN1:WR_CYCLES
23 ----------------------------PHASER_IN1:PHASER_IN_ENPHASER_IN1:EN_ISERDES_RST
24 ----------------------------PHASER_IN1:ICLK_TO_RCLK_BYPASSPHASER_IN1:OUTPUT_CLK_SRC[2]
25 ----------------------------PHASER_IN1:OUTPUT_CLK_SRC[3]PHASER_IN1:STG1_PD_UPDATE[0]
26 ----------------------------PHASER_IN1:STG1_PD_UPDATE[1]PHASER_IN1:STG1_PD_UPDATE[2]
27 ----------------------------PHASER_IN1:INV.RSTPHASER_IN1:MUX.PHASEREFCLK[0]
28 ----------------------------PHASER_IN1:HALF_CYCLE_ADJPHASER_IN1:SEL_CLK_OFFSET[2]
29 ----------------------------PHASER_IN1:RST_SELPHASER_IN1:REG_OPT_2
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ------------------------------
49 ------------------------------
50 ------------------------------
51 ----------------------------PHASER_IN1:PD_REVERSE[0]PHASER_IN1:PD_REVERSE[1]
52 ----------------------------PHASER_IN1:PD_REVERSE[2]-
53 ----------------------------PHASER_IN1:FREQ_REF_DIV[0]PHASER_IN1:FREQ_REF_DIV[1]
54 ----------------------------PHASER_IN1:DQS_FIND_PATTERN[0]PHASER_IN1:DQS_FIND_PATTERN[1]
55 ----------------------------PHASER_IN1:DQS_FIND_PATTERN[2]PHASER_IN1:EN_TEST_RING
56 ----------------------------PHASER_IN1:CTL_MODEPHASER_IN1:CLKOUT_DIV[0]
57 ----------------------------PHASER_IN1:CLKOUT_DIV[1]PHASER_IN1:CLKOUT_DIV[2]
58 ----------------------------PHASER_IN1:CLKOUT_DIV[3]PHASER_IN1:BURST_MODE
59 ----------------------------PHASER_IN1:MUX.PHASEREFCLK[1]PHASER_IN1:MUX.PHASEREFCLK[2]
60 ----------------------------PHASER_IN1:MUX.PHASEREFCLK[3]-
CMT bittile 23
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ----------------------------PHASER_IN1:FINE_DELAY[0]PHASER_IN1:FINE_DELAY[1]
20 ----------------------------PHASER_IN1:FINE_DELAY[2]PHASER_IN1:FINE_DELAY[3]
21 ----------------------------PHASER_IN1:FINE_DELAY[4]PHASER_IN1:FINE_DELAY[5]
22 ----------------------------PHASER_IN1:SYNC_IN_DIV_RSTPHASER_IN1:CLKOUT_DIV_ST[0]
23 ----------------------------PHASER_IN1:CLKOUT_DIV_ST[1]PHASER_IN1:CLKOUT_DIV_ST[2]
24 ----------------------------PHASER_IN1:CLKOUT_DIV_ST[3]PHASER_IN1:CLKOUT_DIV[4]
25 ----------------------------PHASER_IN1:CLKOUT_DIV[5]PHASER_IN1:CLKOUT_DIV[6]
26 ----------------------------PHASER_IN1:CLKOUT_DIV[7]-
CMT bittile 24
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 --------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE1[0]HCLK_CMT:MUX.LCLK0_CMT_D[7]-HCLK_CMT:MUX.LCLK1_CMT_D[7]
17 --------------------------HCLK_CMT:MUX.LCLK0_CMT_D[8]HCLK_CMT:MUX.LCLK0_CMT_D[6]HCLK_CMT:MUX.LCLK1_CMT_D[8]HCLK_CMT:MUX.LCLK1_CMT_D[6]
18 --------------------------HCLK_CMT:MUX.LCLK0_CMT_D[5]HCLK_CMT:MUX.LCLK0_CMT_D[4]HCLK_CMT:MUX.LCLK1_CMT_D[5]HCLK_CMT:MUX.LCLK1_CMT_D[4]
19 --------------------------HCLK_CMT:MUX.LCLK0_CMT_D[3]HCLK_CMT:MUX.LCLK0_CMT_D[2]HCLK_CMT:MUX.LCLK1_CMT_D[3]HCLK_CMT:MUX.LCLK1_CMT_D[2]
20 --------------------------HCLK_CMT:MUX.LCLK0_CMT_D[1]HCLK_CMT:MUX.LCLK0_CMT_D[0]HCLK_CMT:MUX.LCLK1_CMT_D[1]HCLK_CMT:MUX.LCLK1_CMT_D[0]
21 --------------------------MMCM:MUX.CLKIN2_HCLK[6]MMCM:MUX.CLKIN2_HCLK[7]MMCM:MUX.CLKIN1_HCLK[6]MMCM:MUX.CLKIN1_HCLK[7]
22 --------------------------MMCM:MUX.CLKIN2_HCLK[8]MMCM:MUX.CLKIN2_HCLK[9]MMCM:MUX.CLKIN1_HCLK[8]MMCM:MUX.CLKIN1_HCLK[9]
23 --------------------------MMCM:MUX.CLKIN2_HCLK[10]MMCM:MUX.CLKIN2_HCLK[5]MMCM:MUX.CLKIN1_HCLK[10]MMCM:MUX.CLKIN1_HCLK[5]
24 --------------------------MMCM:MUX.CLKIN2_HCLK[4]MMCM:MUX.CLKIN2_HCLK[3]MMCM:MUX.CLKIN1_HCLK[4]MMCM:MUX.CLKIN1_HCLK[3]
25 --------------------------MMCM:MUX.CLKIN2_HCLK[2]MMCM:MUX.CLKIN2_HCLK[1]MMCM:MUX.CLKIN1_HCLK[2]MMCM:MUX.CLKIN1_HCLK[1]
26 --------------------------MMCM:MUX.CLKIN2_HCLK[0]MMCM:MUX.CLKFBIN_HCLK[6]MMCM:MUX.CLKIN1_HCLK[0]-
27 --------------------------MMCM:MUX.CLKFBIN_HCLK[7]MMCM:MUX.CLKFBIN_HCLK[8]--
28 --------------------------MMCM:MUX.CLKFBIN_HCLK[9]MMCM:MUX.CLKFBIN_HCLK[10]--
29 --------------------------MMCM:MUX.CLKFBIN_HCLK[5]MMCM:MUX.CLKFBIN_HCLK[4]--
30 --------------------------MMCM:MUX.CLKFBIN_HCLK[3]MMCM:MUX.CLKFBIN_HCLK[2]--
31 --------------------------MMCM:MUX.CLKFBIN_HCLK[1]MMCM:MUX.CLKFBIN_HCLK[0]--
32 --------------------------HCLK_CMT:MUX.HOUT6[7]HCLK_CMT:MUX.HOUT6[5]--
33 --------------------------HCLK_CMT:MUX.HOUT6[6]HCLK_CMT:MUX.HOUT6[0]--
34 --------------------------HCLK_CMT:MUX.HOUT6[1]HCLK_CMT:MUX.HOUT6[4]--
35 --------------------------HCLK_CMT:MUX.HOUT6[2]HCLK_CMT:MUX.HOUT6[3]PHASER_IN3:ENABLE.RCLKPHASER_IN2:ENABLE.RCLK
36 --------------------------HCLK_CMT:MUX.HOUT6[13]HCLK_CMT:MUX.HOUT6[12]PHASER_IN1:ENABLE.RCLKPHASER_IN0:ENABLE.RCLK
37 --------------------------HCLK_CMT:MUX.HOUT6[11]HCLK_CMT:MUX.HOUT6[10]MMCM:ENABLE.PERF3MMCM:ENABLE.PERF2
38 --------------------------HCLK_CMT:MUX.HOUT6[9]HCLK_CMT:MUX.HOUT6[8]MMCM:ENABLE.PERF1MMCM:ENABLE.PERF0
39 --------------------------HCLK_CMT:MUX.HOUT4[7]HCLK_CMT:MUX.HOUT4[5]HCLK_CMT:MUX.HOUT5[7]HCLK_CMT:MUX.HOUT5[5]
40 --------------------------HCLK_CMT:MUX.HOUT4[6]HCLK_CMT:MUX.HOUT4[0]HCLK_CMT:MUX.HOUT5[6]HCLK_CMT:MUX.HOUT5[0]
41 --------------------------HCLK_CMT:MUX.HOUT4[1]HCLK_CMT:MUX.HOUT4[4]HCLK_CMT:MUX.HOUT5[1]HCLK_CMT:MUX.HOUT5[4]
42 --------------------------HCLK_CMT:MUX.HOUT4[2]HCLK_CMT:MUX.HOUT4[3]HCLK_CMT:MUX.HOUT5[2]HCLK_CMT:MUX.HOUT5[3]
43 --------------------------HCLK_CMT:MUX.HOUT4[13]HCLK_CMT:MUX.HOUT4[12]HCLK_CMT:MUX.HOUT5[13]HCLK_CMT:MUX.HOUT5[12]
44 --------------------------HCLK_CMT:MUX.HOUT4[11]HCLK_CMT:MUX.HOUT4[10]HCLK_CMT:MUX.HOUT5[11]HCLK_CMT:MUX.HOUT5[10]
45 --------------------------HCLK_CMT:MUX.HOUT4[9]HCLK_CMT:MUX.HOUT4[8]HCLK_CMT:MUX.HOUT5[9]HCLK_CMT:MUX.HOUT5[8]
46 --------------------------HCLK_CMT:MUX.HOUT2[7]HCLK_CMT:MUX.HOUT2[5]HCLK_CMT:MUX.HOUT3[7]HCLK_CMT:MUX.HOUT3[5]
47 --------------------------HCLK_CMT:MUX.HOUT2[6]HCLK_CMT:MUX.HOUT2[0]HCLK_CMT:MUX.HOUT3[6]HCLK_CMT:MUX.HOUT3[0]
48 --------------------------HCLK_CMT:MUX.HOUT2[1]HCLK_CMT:MUX.HOUT2[4]HCLK_CMT:MUX.HOUT3[1]HCLK_CMT:MUX.HOUT3[4]
49 --------------------------HCLK_CMT:MUX.HOUT2[2]HCLK_CMT:MUX.HOUT2[3]HCLK_CMT:MUX.HOUT3[2]HCLK_CMT:MUX.HOUT3[3]
50 --------------------------HCLK_CMT:MUX.HOUT2[13]HCLK_CMT:MUX.HOUT2[12]HCLK_CMT:MUX.HOUT3[13]HCLK_CMT:MUX.HOUT3[12]
51 --------------------------HCLK_CMT:MUX.HOUT2[11]HCLK_CMT:MUX.HOUT2[10]HCLK_CMT:MUX.HOUT3[11]HCLK_CMT:MUX.HOUT3[10]
52 --------------------------HCLK_CMT:MUX.HOUT2[9]HCLK_CMT:MUX.HOUT2[8]HCLK_CMT:MUX.HOUT3[9]HCLK_CMT:MUX.HOUT3[8]
53 --------------------------HCLK_CMT:MUX.HOUT0[7]HCLK_CMT:MUX.HOUT0[5]HCLK_CMT:MUX.HOUT1[7]HCLK_CMT:MUX.HOUT1[5]
54 --------------------------HCLK_CMT:MUX.HOUT0[6]HCLK_CMT:MUX.HOUT0[0]HCLK_CMT:MUX.HOUT1[6]HCLK_CMT:MUX.HOUT1[0]
55 --------------------------HCLK_CMT:MUX.HOUT0[1]HCLK_CMT:MUX.HOUT0[4]HCLK_CMT:MUX.HOUT1[1]HCLK_CMT:MUX.HOUT1[4]
56 --------------------------HCLK_CMT:MUX.HOUT0[2]HCLK_CMT:MUX.HOUT0[3]HCLK_CMT:MUX.HOUT1[2]HCLK_CMT:MUX.HOUT1[3]
57 --------------------------HCLK_CMT:MUX.HOUT0[13]HCLK_CMT:MUX.HOUT0[12]HCLK_CMT:MUX.HOUT1[13]HCLK_CMT:MUX.HOUT1[12]
58 --------------------------HCLK_CMT:MUX.HOUT0[11]HCLK_CMT:MUX.HOUT0[10]HCLK_CMT:MUX.HOUT1[11]HCLK_CMT:MUX.HOUT1[10]
59 --------------------------HCLK_CMT:MUX.HOUT0[9]HCLK_CMT:MUX.HOUT0[8]HCLK_CMT:MUX.HOUT1[9]HCLK_CMT:MUX.HOUT1[8]
60 --------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE1[2]HCLK_CMT:MUX.PHASER_REF_BOUNCE0[1]HCLK_CMT:ENABLE.FREQ_BB3HCLK_CMT:ENABLE.FREQ_BB2
61 --------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE0[0]HCLK_CMT:MUX.PHASER_REF_BOUNCE0[2]HCLK_CMT:ENABLE.FREQ_BB1HCLK_CMT:ENABLE.FREQ_BB0
62 --------------------------HCLK_CMT:ENABLE.CCIO3HCLK_CMT:ENABLE.CCIO2HCLK_CMT:MUX.FREQ_BB3[0]HCLK_CMT:MUX.FREQ_BB2[0]
63 --------------------------HCLK_CMT:ENABLE.CCIO1HCLK_CMT:ENABLE.CCIO0HCLK_CMT:MUX.FREQ_BB1[0]HCLK_CMT:MUX.FREQ_BB0[0]
CMT bittile 25
RowColumn
01234567891011121314151617181920212223242526272829
0 --------------------------BUFMRCE0:MUX.I[3]BUFMRCE0:MUX.I[4]HCLK_CMT:MUX.FREQ_BB2[2]HCLK_CMT:MUX.FREQ_BB2[1]
1 --------------------------BUFMRCE0:MUX.I[5]BUFMRCE1:MUX.I[3]HCLK_CMT:MUX.FREQ_BB1[2]HCLK_CMT:MUX.FREQ_BB1[1]
2 --------------------------BUFMRCE1:MUX.I[4]BUFMRCE1:MUX.I[5]BUFMRCE0:MUX.I[0]BUFMRCE0:MUX.I[1]
3 --------------------------HCLK_CMT:MUX.FREQ_BB3[2]HCLK_CMT:MUX.FREQ_BB3[1]HCLK_CMT:MUX.FREQ_BB0[2]HCLK_CMT:MUX.FREQ_BB0[1]
4 --------------------------HCLK_CMT:MUX.HOUT7[8]HCLK_CMT:MUX.HOUT7[9]HCLK_CMT:MUX.HOUT8[8]HCLK_CMT:MUX.HOUT8[9]
5 --------------------------HCLK_CMT:MUX.HOUT7[10]HCLK_CMT:MUX.HOUT7[11]HCLK_CMT:MUX.HOUT8[10]HCLK_CMT:MUX.HOUT8[11]
6 --------------------------HCLK_CMT:MUX.HOUT7[12]HCLK_CMT:MUX.HOUT7[13]HCLK_CMT:MUX.HOUT8[12]HCLK_CMT:MUX.HOUT8[13]
7 --------------------------HCLK_CMT:MUX.HOUT7[3]HCLK_CMT:MUX.HOUT7[2]HCLK_CMT:MUX.HOUT8[3]HCLK_CMT:MUX.HOUT8[2]
8 --------------------------HCLK_CMT:MUX.HOUT7[4]HCLK_CMT:MUX.HOUT7[1]HCLK_CMT:MUX.HOUT8[4]HCLK_CMT:MUX.HOUT8[1]
9 --------------------------HCLK_CMT:MUX.HOUT7[0]HCLK_CMT:MUX.HOUT7[6]HCLK_CMT:MUX.HOUT8[0]HCLK_CMT:MUX.HOUT8[6]
10 --------------------------HCLK_CMT:MUX.HOUT7[5]HCLK_CMT:MUX.HOUT7[7]HCLK_CMT:MUX.HOUT8[5]HCLK_CMT:MUX.HOUT8[7]
11 --------------------------HCLK_CMT:MUX.HOUT9[8]HCLK_CMT:MUX.HOUT9[9]HCLK_CMT:MUX.HOUT10[8]HCLK_CMT:MUX.HOUT10[9]
12 --------------------------HCLK_CMT:MUX.HOUT9[10]HCLK_CMT:MUX.HOUT9[11]HCLK_CMT:MUX.HOUT10[10]HCLK_CMT:MUX.HOUT10[11]
13 --------------------------HCLK_CMT:MUX.HOUT9[12]HCLK_CMT:MUX.HOUT9[13]HCLK_CMT:MUX.HOUT10[12]HCLK_CMT:MUX.HOUT10[13]
14 --------------------------HCLK_CMT:MUX.HOUT9[3]HCLK_CMT:MUX.HOUT9[2]HCLK_CMT:MUX.HOUT10[3]HCLK_CMT:MUX.HOUT10[2]
15 --------------------------HCLK_CMT:MUX.HOUT9[4]HCLK_CMT:MUX.HOUT9[1]HCLK_CMT:MUX.HOUT10[4]HCLK_CMT:MUX.HOUT10[1]
16 --------------------------HCLK_CMT:MUX.HOUT9[0]HCLK_CMT:MUX.HOUT9[6]HCLK_CMT:MUX.HOUT10[0]HCLK_CMT:MUX.HOUT10[6]
17 --------------------------HCLK_CMT:MUX.HOUT9[5]HCLK_CMT:MUX.HOUT9[7]HCLK_CMT:MUX.HOUT10[5]HCLK_CMT:MUX.HOUT10[7]
18 --------------------------HCLK_CMT:MUX.HOUT11[8]HCLK_CMT:MUX.HOUT11[9]HCLK_CMT:MUX.HOUT12[8]HCLK_CMT:MUX.HOUT12[9]
19 --------------------------HCLK_CMT:MUX.HOUT11[10]HCLK_CMT:MUX.HOUT11[11]HCLK_CMT:MUX.HOUT12[10]HCLK_CMT:MUX.HOUT12[11]
20 --------------------------HCLK_CMT:MUX.HOUT11[12]HCLK_CMT:MUX.HOUT11[13]HCLK_CMT:MUX.HOUT12[12]HCLK_CMT:MUX.HOUT12[13]
21 --------------------------HCLK_CMT:MUX.HOUT11[3]HCLK_CMT:MUX.HOUT11[2]HCLK_CMT:MUX.HOUT12[3]HCLK_CMT:MUX.HOUT12[2]
22 --------------------------HCLK_CMT:MUX.HOUT11[4]HCLK_CMT:MUX.HOUT11[1]HCLK_CMT:MUX.HOUT12[4]HCLK_CMT:MUX.HOUT12[1]
23 --------------------------HCLK_CMT:MUX.HOUT11[0]HCLK_CMT:MUX.HOUT11[6]HCLK_CMT:MUX.HOUT12[0]HCLK_CMT:MUX.HOUT12[6]
24 --------------------------HCLK_CMT:MUX.HOUT11[5]HCLK_CMT:MUX.HOUT11[7]HCLK_CMT:MUX.HOUT12[5]HCLK_CMT:MUX.HOUT12[7]
25 --------------------------HCLK_CMT:MUX.HOUT13[8]HCLK_CMT:MUX.HOUT13[9]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[2]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[0]
26 --------------------------HCLK_CMT:MUX.HOUT13[10]HCLK_CMT:MUX.HOUT13[11]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[1]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[2]
27 --------------------------HCLK_CMT:MUX.HOUT13[12]HCLK_CMT:MUX.HOUT13[13]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[0]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[1]
28 --------------------------HCLK_CMT:MUX.HOUT13[3]HCLK_CMT:MUX.HOUT13[2]--
29 --------------------------HCLK_CMT:MUX.HOUT13[4]HCLK_CMT:MUX.HOUT13[1]--
30 --------------------------HCLK_CMT:MUX.HOUT13[0]HCLK_CMT:MUX.HOUT13[6]--
31 --------------------------HCLK_CMT:MUX.HOUT13[5]HCLK_CMT:MUX.HOUT13[7]--
32 --------------------------PLL:MUX.CLKFBIN_HCLK[0]PLL:MUX.CLKFBIN_HCLK[1]--
33 --------------------------PLL:MUX.CLKFBIN_HCLK[2]PLL:MUX.CLKFBIN_HCLK[3]--
34 --------------------------PLL:MUX.CLKFBIN_HCLK[4]PLL:MUX.CLKFBIN_HCLK[5]--
35 --------------------------PLL:MUX.CLKFBIN_HCLK[10]PLL:MUX.CLKFBIN_HCLK[9]--
36 --------------------------PLL:MUX.CLKFBIN_HCLK[8]PLL:MUX.CLKFBIN_HCLK[7]--
37 --------------------------PLL:MUX.CLKFBIN_HCLK[6]PLL:MUX.CLKIN2_HCLK[0]-PLL:MUX.CLKIN1_HCLK[0]
38 --------------------------PLL:MUX.CLKIN2_HCLK[1]PLL:MUX.CLKIN2_HCLK[2]PLL:MUX.CLKIN1_HCLK[1]PLL:MUX.CLKIN1_HCLK[2]
39 --------------------------PLL:MUX.CLKIN2_HCLK[3]PLL:MUX.CLKIN2_HCLK[4]PLL:MUX.CLKIN1_HCLK[3]PLL:MUX.CLKIN1_HCLK[4]
40 --------------------------PLL:MUX.CLKIN2_HCLK[5]PLL:MUX.CLKIN2_HCLK[10]PLL:MUX.CLKIN1_HCLK[5]PLL:MUX.CLKIN1_HCLK[10]
41 --------------------------PLL:MUX.CLKIN2_HCLK[9]PLL:MUX.CLKIN2_HCLK[8]PLL:MUX.CLKIN1_HCLK[9]PLL:MUX.CLKIN1_HCLK[8]
42 --------------------------PLL:MUX.CLKIN2_HCLK[7]PLL:MUX.CLKIN2_HCLK[6]PLL:MUX.CLKIN1_HCLK[7]PLL:MUX.CLKIN1_HCLK[6]
43 --------------------------HCLK_CMT:MUX.LCLK0_CMT_U[0]HCLK_CMT:MUX.LCLK0_CMT_U[1]HCLK_CMT:MUX.LCLK1_CMT_U[0]HCLK_CMT:MUX.LCLK1_CMT_U[1]
44 --------------------------HCLK_CMT:MUX.LCLK0_CMT_U[2]HCLK_CMT:MUX.LCLK0_CMT_U[3]HCLK_CMT:MUX.LCLK1_CMT_U[2]HCLK_CMT:MUX.LCLK1_CMT_U[3]
45 --------------------------HCLK_CMT:MUX.LCLK0_CMT_U[4]HCLK_CMT:MUX.LCLK0_CMT_U[5]HCLK_CMT:MUX.LCLK1_CMT_U[4]HCLK_CMT:MUX.LCLK1_CMT_U[5]
46 --------------------------HCLK_CMT:MUX.LCLK0_CMT_U[6]HCLK_CMT:MUX.LCLK0_CMT_U[8]HCLK_CMT:MUX.LCLK1_CMT_U[6]HCLK_CMT:MUX.LCLK1_CMT_U[8]
47 --------------------------HCLK_CMT:MUX.LCLK0_CMT_U[7]HCLK_CMT:MUX.PHASER_REF_BOUNCE1[1]HCLK_CMT:MUX.LCLK1_CMT_U[7]-
CMT bittile 26
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHASER_REF:PHASER_REF_MISC[0]PHASER_REF:PHASER_REF_MISC[1]
1 ----------------------------PHASER_REF:PHASER_REF_MISC[2]PHASER_REF:CP_BIAS_TRIP_SET
2 ----------------------------PHASER_REF:TMUX_MUX_SEL[0]PHASER_REF:TMUX_MUX_SEL[1]
3 ----------------------------PHASER_REF:SEL_SLIPDPHASER_REF:LOCK_REF_DLY[0]
4 ----------------------------PHASER_REF:LOCK_REF_DLY[1]PHASER_REF:LOCK_REF_DLY[2]
5 ----------------------------PHASER_REF:LOCK_REF_DLY[3]PHASER_REF:LOCK_REF_DLY[4]
6 ----------------------------PHASER_REF:SEL_LF_HIGH[0]PHASER_REF:SEL_LF_HIGH[1]
7 ----------------------------PHASER_REF:SEL_LF_HIGH[2]PHASER_REF:SUP_SEL_AREG
8 ----------------------------PHASER_REF:CONTROL_3[0]PHASER_REF:CONTROL_3[1]
9 ----------------------------PHASER_REF:CONTROL_3[2]PHASER_REF:CONTROL_3[3]
10 ----------------------------PHASER_REF:CONTROL_3[4]PHASER_REF:CONTROL_3[5]
11 ----------------------------PHASER_REF:CONTROL_3[6]PHASER_REF:CONTROL_3[7]
12 ----------------------------PHASER_REF:CONTROL_3[8]PHASER_REF:CONTROL_3[9]
13 ----------------------------PHASER_REF:CONTROL_3[10]PHASER_REF:CONTROL_3[11]
14 ----------------------------PHASER_REF:CONTROL_3[12]PHASER_REF:CONTROL_3[13]
15 ----------------------------PHASER_REF:CONTROL_3[14]PHASER_REF:CONTROL_3[15]
16 ----------------------------PHASER_REF:INV.RSTPHASER_REF:MAN_LF[0]
17 ----------------------------PHASER_REF:MAN_LF[1]PHASER_REF:MAN_LF[2]
18 ----------------------------PHASER_REF:PFD[0]PHASER_REF:PFD[1]
19 ----------------------------PHASER_REF:PFD[2]PHASER_REF:PFD[3]
20 ----------------------------PHASER_REF:PFD[4]PHASER_REF:PFD[5]
21 ----------------------------PHASER_REF:PFD[6]PHASER_REF:LOCK_FB_DLY[0]
22 ----------------------------PHASER_REF:LOCK_FB_DLY[1]PHASER_REF:LOCK_FB_DLY[2]
23 ----------------------------PHASER_REF:LOCK_FB_DLY[3]PHASER_REF:LOCK_FB_DLY[4]
24 ----------------------------PHASER_REF:INV.PWRDWNPHASER_REF:PHASER_REF_EN
25 ----------------------------PHASER_REF:LOCK_CNT[0]PHASER_REF:LOCK_CNT[1]
26 ----------------------------PHASER_REF:LOCK_CNT[2]PHASER_REF:LOCK_CNT[3]
27 ----------------------------PHASER_REF:LOCK_CNT[4]PHASER_REF:LOCK_CNT[5]
28 ----------------------------PHASER_REF:LOCK_CNT[6]PHASER_REF:LOCK_CNT[7]
29 ----------------------------PHASER_REF:LOCK_CNT[8]PHASER_REF:LOCK_CNT[9]
30 ----------------------------PHASER_REF:LF_PEN[0]PHASER_REF:LF_PEN[1]
31 ----------------------------PHASER_REF:LF_NEN[0]PHASER_REF:LF_NEN[1]
32 ----------------------------PHASER_REF:CONTROL_2[0]PHASER_REF:CONTROL_2[1]
33 ----------------------------PHASER_REF:CONTROL_2[2]PHASER_REF:CONTROL_2[3]
34 ----------------------------PHASER_REF:CONTROL_2[4]PHASER_REF:CONTROL_2[5]
35 ----------------------------PHASER_REF:CONTROL_2[6]PHASER_REF:CONTROL_2[7]
36 ----------------------------PHASER_REF:CONTROL_2[8]PHASER_REF:CONTROL_2[9]
37 ----------------------------PHASER_REF:CONTROL_2[10]PHASER_REF:CONTROL_2[11]
38 ----------------------------PHASER_REF:CONTROL_2[12]PHASER_REF:CONTROL_2[13]
39 ----------------------------PHASER_REF:CONTROL_2[14]PHASER_REF:CONTROL_2[15]
40 ----------------------------PHASER_REF:CONTROL_1[0]PHASER_REF:CONTROL_1[1]
41 ----------------------------PHASER_REF:CONTROL_1[2]PHASER_REF:CONTROL_1[3]
42 ----------------------------PHASER_REF:CONTROL_1[4]PHASER_REF:CONTROL_1[5]
43 ----------------------------PHASER_REF:CONTROL_1[6]PHASER_REF:CONTROL_1[7]
44 ----------------------------PHASER_REF:CONTROL_1[8]PHASER_REF:CONTROL_1[9]
45 ----------------------------PHASER_REF:CONTROL_1[10]PHASER_REF:CONTROL_1[11]
46 ----------------------------PHASER_REF:CONTROL_1[12]PHASER_REF:CONTROL_1[13]
47 ----------------------------PHASER_REF:CONTROL_1[14]PHASER_REF:CONTROL_1[15]
48 ----------------------------PHASER_REF:CONTROL_0[0]PHASER_REF:CONTROL_0[1]
49 ----------------------------PHASER_REF:CONTROL_0[2]PHASER_REF:CONTROL_0[3]
50 ----------------------------PHASER_REF:CONTROL_0[4]PHASER_REF:CONTROL_0[5]
51 ----------------------------PHASER_REF:CONTROL_0[6]PHASER_REF:CONTROL_0[7]
52 ----------------------------PHASER_REF:CONTROL_0[8]PHASER_REF:CONTROL_0[9]
53 ----------------------------PHASER_REF:CONTROL_0[10]PHASER_REF:CONTROL_0[11]
54 ----------------------------PHASER_REF:CONTROL_0[12]PHASER_REF:CONTROL_0[13]
55 ----------------------------PHASER_REF:CONTROL_0[14]PHASER_REF:CONTROL_0[15]
56 ----------------------------PHASER_REF:CP_RES[0]PHASER_REF:CP_RES[1]
57 ----------------------------PHASER_REF:CP[0]PHASER_REF:CP[1]
58 ----------------------------PHASER_REF:CP[2]PHASER_REF:CP[3]
59 ----------------------------PHASER_REF:AVDD_VBG_SEL[0]PHASER_REF:AVDD_VBG_SEL[1]
60 ----------------------------PHASER_REF:AVDD_VBG_SEL[2]PHASER_REF:AVDD_VBG_SEL[3]
61 ----------------------------PHASER_REF:AVDD_VBG_PD[0]PHASER_REF:AVDD_VBG_PD[1]
62 ----------------------------PHASER_REF:AVDD_VBG_PD[2]PHASER_REF:AVDD_COMP_SET[0]
63 ----------------------------PHASER_REF:AVDD_COMP_SET[1]PHASER_REF:AVDD_COMP_SET[2]
CMT bittile 27
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHASER_REF:CONTROL_4[0]PHASER_REF:CONTROL_4[1]
1 ----------------------------PHASER_REF:CONTROL_4[2]PHASER_REF:CONTROL_4[3]
2 ----------------------------PHASER_REF:CONTROL_4[4]PHASER_REF:CONTROL_4[5]
3 ----------------------------PHASER_REF:CONTROL_4[6]PHASER_REF:CONTROL_4[7]
4 ----------------------------PHASER_REF:CONTROL_4[8]PHASER_REF:CONTROL_4[9]
5 ----------------------------PHASER_REF:CONTROL_4[10]PHASER_REF:CONTROL_4[11]
6 ----------------------------PHASER_REF:CONTROL_4[12]PHASER_REF:CONTROL_4[13]
7 ----------------------------PHASER_REF:CONTROL_4[14]PHASER_REF:CONTROL_4[15]
8 ----------------------------PHASER_REF:CONTROL_5[0]PHASER_REF:CONTROL_5[1]
9 ----------------------------PHASER_REF:CONTROL_5[2]PHASER_REF:CONTROL_5[3]
10 ----------------------------PHASER_REF:CONTROL_5[4]PHASER_REF:CONTROL_5[5]
11 ----------------------------PHASER_REF:CONTROL_5[6]PHASER_REF:CONTROL_5[7]
12 ----------------------------PHASER_REF:CONTROL_5[8]PHASER_REF:CONTROL_5[9]
13 ----------------------------PHASER_REF:CONTROL_5[10]PHASER_REF:CONTROL_5[11]
14 ----------------------------PHASER_REF:CONTROL_5[12]PHASER_REF:CONTROL_5[13]
15 ----------------------------PHASER_REF:CONTROL_5[14]PHASER_REF:CONTROL_5[15]
16 ----------------------------PHASER_OUT2:TEST_OPT[0]PHASER_OUT2:TEST_OPT[1]
17 ----------------------------PHASER_OUT2:TEST_OPT[2]PHASER_OUT2:TEST_OPT[3]
18 ----------------------------PHASER_OUT2:TEST_OPT[4]PHASER_OUT2:TEST_OPT[5]
19 ----------------------------PHASER_OUT2:TEST_OPT[6]PHASER_OUT2:TEST_OPT[7]
20 ----------------------------PHASER_OUT2:TEST_OPT[8]PHASER_OUT2:TEST_OPT[9]
21 ----------------------------PHASER_OUT2:TEST_OPT[10]PHASER_OUT2:DATA_RD_CYCLES
22 ----------------------------PHASER_OUT2:OCLKDELAY_INVPHASER_OUT2:PHASER_OUT_EN
23 ----------------------------PHASER_OUT2:EN_OSERDES_RSTPHASER_OUT2:COARSE_BYPASS
24 ----------------------------PHASER_OUT2:OUTPUT_CLK_SRC[0]PHASER_OUT2:OUTPUT_CLK_SRC[1]
25 ----------------------------PHASER_OUT2:STG1_BYPASSPHASER_OUT2:OCLK_DELAY[0]
26 ----------------------------PHASER_OUT2:OCLK_DELAY[1]PHASER_OUT2:OCLK_DELAY[2]
27 ----------------------------PHASER_OUT2:OCLK_DELAY[3]PHASER_OUT2:OCLK_DELAY[4]
28 ----------------------------PHASER_OUT2:OCLK_DELAY[5]PHASER_OUT2:EN_TEST_RING
29 ----------------------------PHASER_OUT2:DATA_CTL_NPHASER_OUT2:CTL_MODE
30 ----------------------------PHASER_OUT2:CLKOUT_DIV[0]PHASER_OUT2:CLKOUT_DIV[1]
31 ----------------------------PHASER_OUT2:CLKOUT_DIV[2]PHASER_OUT2:CLKOUT_DIV[3]
CMT bittile 28
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHASER_OUT2:INV.RSTPHASER_OUT2:MUX.PHASEREFCLK[0]
1 ----------------------------PHASER_OUT2:MUX.PHASEREFCLK[1]PHASER_OUT2:MUX.PHASEREFCLK[2]
2 ----------------------------PHASER_OUT2:MUX.PHASEREFCLK[3]PHASER_OUT2:COARSE_DELAY[0]
3 ----------------------------PHASER_OUT2:COARSE_DELAY[1]PHASER_OUT2:COARSE_DELAY[2]
4 ----------------------------PHASER_OUT2:COARSE_DELAY[3]PHASER_OUT2:COARSE_DELAY[4]
5 ----------------------------PHASER_OUT2:COARSE_DELAY[5]PHASER_OUT2:FINE_DELAY[0]
6 ----------------------------PHASER_OUT2:FINE_DELAY[1]PHASER_OUT2:FINE_DELAY[2]
7 ----------------------------PHASER_OUT2:FINE_DELAY[3]PHASER_OUT2:FINE_DELAY[4]
8 ----------------------------PHASER_OUT2:FINE_DELAY[5]PHASER_OUT2:SYNC_IN_DIV_RST
9 ----------------------------PHASER_OUT2:CLKOUT_DIV_ST[0]PHASER_OUT2:CLKOUT_DIV_ST[1]
10 ----------------------------PHASER_OUT2:CLKOUT_DIV_ST[2]PHASER_OUT2:CLKOUT_DIV_ST[3]
11 ----------------------------PHASER_OUT2:CLKOUT_DIV[4]PHASER_OUT2:CLKOUT_DIV[5]
12 ----------------------------PHASER_OUT2:CLKOUT_DIV[6]PHASER_OUT2:CLKOUT_DIV[7]
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ----------------------------PHASER_IN2:UPDATE_NONACTIVEPHASER_IN2:TEST_BP
49 ----------------------------PHASER_IN2:DQS_AUTO_RECALPHASER_IN2:DQS_BIAS_MODE
50 ----------------------------PHASER_IN2:REG_OPT_1PHASER_IN2:REG_OPT_4
51 ----------------------------PHASER_IN2:RD_ADDR_INIT[0]PHASER_IN2:RD_ADDR_INIT[1]
52 ----------------------------PHASER_IN2:SEL_OUTPHASER_IN2:SEL_CLK_OFFSET[0]
53 ----------------------------PHASER_IN2:SEL_CLK_OFFSET[1]PHASER_IN2:OUTPUT_CLK_SRC[0]
54 ----------------------------PHASER_IN2:OUTPUT_CLK_SRC[1]PHASER_IN2:WR_CYCLES
55 ----------------------------PHASER_IN2:PHASER_IN_ENPHASER_IN2:EN_ISERDES_RST
56 ----------------------------PHASER_IN2:ICLK_TO_RCLK_BYPASSPHASER_IN2:OUTPUT_CLK_SRC[2]
57 ----------------------------PHASER_IN2:OUTPUT_CLK_SRC[3]PHASER_IN2:STG1_PD_UPDATE[0]
58 ----------------------------PHASER_IN2:STG1_PD_UPDATE[1]PHASER_IN2:STG1_PD_UPDATE[2]
59 ----------------------------PHASER_IN2:INV.RSTPHASER_IN2:MUX.PHASEREFCLK[0]
60 ----------------------------PHASER_IN2:HALF_CYCLE_ADJPHASER_IN2:SEL_CLK_OFFSET[2]
61 ----------------------------PHASER_IN2:RST_SELPHASER_IN2:REG_OPT_2
CMT bittile 29
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ----------------------------PHASER_IN2:PD_REVERSE[0]PHASER_IN2:PD_REVERSE[1]
20 ----------------------------PHASER_IN2:PD_REVERSE[2]-
21 ----------------------------PHASER_IN2:FREQ_REF_DIV[0]PHASER_IN2:FREQ_REF_DIV[1]
22 ----------------------------PHASER_IN2:DQS_FIND_PATTERN[0]PHASER_IN2:DQS_FIND_PATTERN[1]
23 ----------------------------PHASER_IN2:DQS_FIND_PATTERN[2]PHASER_IN2:EN_TEST_RING
24 ----------------------------PHASER_IN2:CTL_MODEPHASER_IN2:CLKOUT_DIV[0]
25 ----------------------------PHASER_IN2:CLKOUT_DIV[1]PHASER_IN2:CLKOUT_DIV[2]
26 ----------------------------PHASER_IN2:CLKOUT_DIV[3]PHASER_IN2:BURST_MODE
27 ----------------------------PHASER_IN2:MUX.PHASEREFCLK[1]PHASER_IN2:MUX.PHASEREFCLK[2]
28 ----------------------------PHASER_IN2:MUX.PHASEREFCLK[3]-
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ------------------------------
49 ------------------------------
50 ------------------------------
51 ----------------------------PHASER_IN2:FINE_DELAY[0]PHASER_IN2:FINE_DELAY[1]
52 ----------------------------PHASER_IN2:FINE_DELAY[2]PHASER_IN2:FINE_DELAY[3]
53 ----------------------------PHASER_IN2:FINE_DELAY[4]PHASER_IN2:FINE_DELAY[5]
54 ----------------------------PHASER_IN2:SYNC_IN_DIV_RSTPHASER_IN2:CLKOUT_DIV_ST[0]
55 ----------------------------PHASER_IN2:CLKOUT_DIV_ST[1]PHASER_IN2:CLKOUT_DIV_ST[2]
56 ----------------------------PHASER_IN2:CLKOUT_DIV_ST[3]PHASER_IN2:CLKOUT_DIV[4]
57 ----------------------------PHASER_IN2:CLKOUT_DIV[5]PHASER_IN2:CLKOUT_DIV[6]
58 ----------------------------PHASER_IN2:CLKOUT_DIV[7]-
CMT bittile 30
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ----------------------------PHASER_OUT3:TEST_OPT[0]PHASER_OUT3:TEST_OPT[1]
49 ----------------------------PHASER_OUT3:TEST_OPT[2]PHASER_OUT3:TEST_OPT[3]
50 ----------------------------PHASER_OUT3:TEST_OPT[4]PHASER_OUT3:TEST_OPT[5]
51 ----------------------------PHASER_OUT3:TEST_OPT[6]PHASER_OUT3:TEST_OPT[7]
52 ----------------------------PHASER_OUT3:TEST_OPT[8]PHASER_OUT3:TEST_OPT[9]
53 ----------------------------PHASER_OUT3:TEST_OPT[10]PHASER_OUT3:DATA_RD_CYCLES
54 ----------------------------PHASER_OUT3:OCLKDELAY_INVPHASER_OUT3:PHASER_OUT_EN
55 ----------------------------PHASER_OUT3:EN_OSERDES_RSTPHASER_OUT3:COARSE_BYPASS
56 ----------------------------PHASER_OUT3:OUTPUT_CLK_SRC[0]PHASER_OUT3:OUTPUT_CLK_SRC[1]
57 ----------------------------PHASER_OUT3:STG1_BYPASSPHASER_OUT3:OCLK_DELAY[0]
58 ----------------------------PHASER_OUT3:OCLK_DELAY[1]PHASER_OUT3:OCLK_DELAY[2]
59 ----------------------------PHASER_OUT3:OCLK_DELAY[3]PHASER_OUT3:OCLK_DELAY[4]
60 ----------------------------PHASER_OUT3:OCLK_DELAY[5]PHASER_OUT3:EN_TEST_RING
61 ----------------------------PHASER_OUT3:DATA_CTL_NPHASER_OUT3:CTL_MODE
62 ----------------------------PHASER_OUT3:CLKOUT_DIV[0]PHASER_OUT3:CLKOUT_DIV[1]
63 ----------------------------PHASER_OUT3:CLKOUT_DIV[2]PHASER_OUT3:CLKOUT_DIV[3]
CMT bittile 31
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PHASER_OUT3:INV.RSTPHASER_OUT3:MUX.PHASEREFCLK[0]
33 ----------------------------PHASER_OUT3:MUX.PHASEREFCLK[1]PHASER_OUT3:MUX.PHASEREFCLK[2]
34 ----------------------------PHASER_OUT3:MUX.PHASEREFCLK[3]PHASER_OUT3:COARSE_DELAY[0]
35 ----------------------------PHASER_OUT3:COARSE_DELAY[1]PHASER_OUT3:COARSE_DELAY[2]
36 ----------------------------PHASER_OUT3:COARSE_DELAY[3]PHASER_OUT3:COARSE_DELAY[4]
37 ----------------------------PHASER_OUT3:COARSE_DELAY[5]PHASER_OUT3:FINE_DELAY[0]
38 ----------------------------PHASER_OUT3:FINE_DELAY[1]PHASER_OUT3:FINE_DELAY[2]
39 ----------------------------PHASER_OUT3:FINE_DELAY[3]PHASER_OUT3:FINE_DELAY[4]
40 ----------------------------PHASER_OUT3:FINE_DELAY[5]PHASER_OUT3:SYNC_IN_DIV_RST
41 ----------------------------PHASER_OUT3:CLKOUT_DIV_ST[0]PHASER_OUT3:CLKOUT_DIV_ST[1]
42 ----------------------------PHASER_OUT3:CLKOUT_DIV_ST[2]PHASER_OUT3:CLKOUT_DIV_ST[3]
43 ----------------------------PHASER_OUT3:CLKOUT_DIV[4]PHASER_OUT3:CLKOUT_DIV[5]
44 ----------------------------PHASER_OUT3:CLKOUT_DIV[6]PHASER_OUT3:CLKOUT_DIV[7]
CMT bittile 32
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PHASER_IN3:UPDATE_NONACTIVEPHASER_IN3:TEST_BP
17 ----------------------------PHASER_IN3:DQS_AUTO_RECALPHASER_IN3:DQS_BIAS_MODE
18 ----------------------------PHASER_IN3:REG_OPT_1PHASER_IN3:REG_OPT_4
19 ----------------------------PHASER_IN3:RD_ADDR_INIT[0]PHASER_IN3:RD_ADDR_INIT[1]
20 ----------------------------PHASER_IN3:SEL_OUTPHASER_IN3:SEL_CLK_OFFSET[0]
21 ----------------------------PHASER_IN3:SEL_CLK_OFFSET[1]PHASER_IN3:OUTPUT_CLK_SRC[0]
22 ----------------------------PHASER_IN3:OUTPUT_CLK_SRC[1]PHASER_IN3:WR_CYCLES
23 ----------------------------PHASER_IN3:PHASER_IN_ENPHASER_IN3:EN_ISERDES_RST
24 ----------------------------PHASER_IN3:ICLK_TO_RCLK_BYPASSPHASER_IN3:OUTPUT_CLK_SRC[2]
25 ----------------------------PHASER_IN3:OUTPUT_CLK_SRC[3]PHASER_IN3:STG1_PD_UPDATE[0]
26 ----------------------------PHASER_IN3:STG1_PD_UPDATE[1]PHASER_IN3:STG1_PD_UPDATE[2]
27 ----------------------------PHASER_IN3:INV.RSTPHASER_IN3:MUX.PHASEREFCLK[0]
28 ----------------------------PHASER_IN3:HALF_CYCLE_ADJPHASER_IN3:SEL_CLK_OFFSET[2]
29 ----------------------------PHASER_IN3:RST_SELPHASER_IN3:REG_OPT_2
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ------------------------------
41 ------------------------------
42 ------------------------------
43 ------------------------------
44 ------------------------------
45 ------------------------------
46 ------------------------------
47 ------------------------------
48 ------------------------------
49 ------------------------------
50 ------------------------------
51 ----------------------------PHASER_IN3:PD_REVERSE[0]PHASER_IN3:PD_REVERSE[1]
52 ----------------------------PHASER_IN3:PD_REVERSE[2]-
53 ----------------------------PHASER_IN3:FREQ_REF_DIV[0]PHASER_IN3:FREQ_REF_DIV[1]
54 ----------------------------PHASER_IN3:DQS_FIND_PATTERN[0]PHASER_IN3:DQS_FIND_PATTERN[1]
55 ----------------------------PHASER_IN3:DQS_FIND_PATTERN[2]PHASER_IN3:EN_TEST_RING
56 ----------------------------PHASER_IN3:CTL_MODEPHASER_IN3:CLKOUT_DIV[0]
57 ----------------------------PHASER_IN3:CLKOUT_DIV[1]PHASER_IN3:CLKOUT_DIV[2]
58 ----------------------------PHASER_IN3:CLKOUT_DIV[3]PHASER_IN3:BURST_MODE
59 ----------------------------PHASER_IN3:MUX.PHASEREFCLK[1]PHASER_IN3:MUX.PHASEREFCLK[2]
60 ----------------------------PHASER_IN3:MUX.PHASEREFCLK[3]-
CMT bittile 33
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ----------------------------PHASER_IN3:FINE_DELAY[0]PHASER_IN3:FINE_DELAY[1]
20 ----------------------------PHASER_IN3:FINE_DELAY[2]PHASER_IN3:FINE_DELAY[3]
21 ----------------------------PHASER_IN3:FINE_DELAY[4]PHASER_IN3:FINE_DELAY[5]
22 ----------------------------PHASER_IN3:SYNC_IN_DIV_RSTPHASER_IN3:CLKOUT_DIV_ST[0]
23 ----------------------------PHASER_IN3:CLKOUT_DIV_ST[1]PHASER_IN3:CLKOUT_DIV_ST[2]
24 ----------------------------PHASER_IN3:CLKOUT_DIV_ST[3]PHASER_IN3:CLKOUT_DIV[4]
25 ----------------------------PHASER_IN3:CLKOUT_DIV[5]PHASER_IN3:CLKOUT_DIV[6]
26 ----------------------------PHASER_IN3:CLKOUT_DIV[7]-
CMT bittile 34
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHY_CONTROL:RD_DURATION_0[0]PHY_CONTROL:RD_DURATION_0[1]
1 ----------------------------PHY_CONTROL:RD_DURATION_0[2]PHY_CONTROL:RD_DURATION_0[3]
2 ----------------------------PHY_CONTROL:RD_DURATION_0[4]PHY_CONTROL:RD_DURATION_0[5]
3 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[0]PHY_CONTROL:RD_CMD_OFFSET_0[1]
4 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[2]PHY_CONTROL:RD_CMD_OFFSET_0[3]
5 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[4]PHY_CONTROL:RD_CMD_OFFSET_0[5]
6 ----------------------------PHY_CONTROL:WR_DURATION_0[0]PHY_CONTROL:WR_DURATION_0[1]
7 ----------------------------PHY_CONTROL:WR_DURATION_0[2]PHY_CONTROL:WR_DURATION_0[3]
8 ----------------------------PHY_CONTROL:WR_DURATION_0[4]PHY_CONTROL:WR_DURATION_0[5]
9 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[0]PHY_CONTROL:WR_CMD_OFFSET_0[1]
10 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[2]PHY_CONTROL:WR_CMD_OFFSET_0[3]
11 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[4]PHY_CONTROL:WR_CMD_OFFSET_0[5]
12 ----------------------------PHY_CONTROL:DO_DURATION[0]PHY_CONTROL:DO_DURATION[1]
13 ----------------------------PHY_CONTROL:DO_DURATION[2]PHY_CONTROL:SPARE
14 ----------------------------PHY_CONTROL:MULTI_REGIONPHY_CONTROL:SYNC_MODE
15 ----------------------------PHY_CONTROL:DISABLE_SEQ_MATCH-
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PHY_CONTROL:RD_DURATION_1[0]PHY_CONTROL:RD_DURATION_1[1]
33 ----------------------------PHY_CONTROL:RD_DURATION_1[2]PHY_CONTROL:RD_DURATION_1[3]
34 ----------------------------PHY_CONTROL:RD_DURATION_1[4]PHY_CONTROL:RD_DURATION_1[5]
35 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[0]PHY_CONTROL:RD_CMD_OFFSET_1[1]
36 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[2]PHY_CONTROL:RD_CMD_OFFSET_1[3]
37 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[4]PHY_CONTROL:RD_CMD_OFFSET_1[5]
38 ----------------------------PHY_CONTROL:WR_DURATION_1[0]PHY_CONTROL:WR_DURATION_1[1]
39 ----------------------------PHY_CONTROL:WR_DURATION_1[2]PHY_CONTROL:WR_DURATION_1[3]
40 ----------------------------PHY_CONTROL:WR_DURATION_1[4]PHY_CONTROL:WR_DURATION_1[5]
41 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[0]PHY_CONTROL:WR_CMD_OFFSET_1[1]
42 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[2]PHY_CONTROL:WR_CMD_OFFSET_1[3]
43 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[4]PHY_CONTROL:WR_CMD_OFFSET_1[5]
44 ----------------------------PHY_CONTROL:CLK_RATIO[0]PHY_CONTROL:CLK_RATIO[1]
45 ----------------------------PHY_CONTROL:CLK_RATIO[2]PHY_CONTROL:DI_DURATION[0]
46 ----------------------------PHY_CONTROL:DI_DURATION[1]PHY_CONTROL:DI_DURATION[2]
47 ------------------------------
48 ----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[0]PHY_CONTROL:FOUR_WINDOW_CLOCKS[1]
49 ----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[2]PHY_CONTROL:FOUR_WINDOW_CLOCKS[3]
50 ----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[4]PHY_CONTROL:FOUR_WINDOW_CLOCKS[5]
51 ----------------------------PHY_CONTROL:EVENTS_DELAY[0]PHY_CONTROL:EVENTS_DELAY[1]
52 ----------------------------PHY_CONTROL:EVENTS_DELAY[2]PHY_CONTROL:EVENTS_DELAY[3]
53 ----------------------------PHY_CONTROL:EVENTS_DELAY[4]PHY_CONTROL:EVENTS_DELAY[5]
54 ----------------------------PHY_CONTROL:AO_TOGGLE[0]PHY_CONTROL:AO_TOGGLE[1]
55 ----------------------------PHY_CONTROL:AO_TOGGLE[2]PHY_CONTROL:AO_TOGGLE[3]
56 ----------------------------PHY_CONTROL:CMD_OFFSET[0]PHY_CONTROL:CMD_OFFSET[1]
57 ----------------------------PHY_CONTROL:CMD_OFFSET[2]PHY_CONTROL:CMD_OFFSET[3]
58 ----------------------------PHY_CONTROL:CMD_OFFSET[4]PHY_CONTROL:CMD_OFFSET[5]
CMT bittile 35
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PHY_CONTROL:RD_DURATION_2[0]PHY_CONTROL:RD_DURATION_2[1]
1 ----------------------------PHY_CONTROL:RD_DURATION_2[2]PHY_CONTROL:RD_DURATION_2[3]
2 ----------------------------PHY_CONTROL:RD_DURATION_2[4]PHY_CONTROL:RD_DURATION_2[5]
3 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[0]PHY_CONTROL:RD_CMD_OFFSET_2[1]
4 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[2]PHY_CONTROL:RD_CMD_OFFSET_2[3]
5 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[4]PHY_CONTROL:RD_CMD_OFFSET_2[5]
6 ----------------------------PHY_CONTROL:WR_DURATION_2[0]PHY_CONTROL:WR_DURATION_2[1]
7 ----------------------------PHY_CONTROL:WR_DURATION_2[2]PHY_CONTROL:WR_DURATION_2[3]
8 ----------------------------PHY_CONTROL:WR_DURATION_2[4]PHY_CONTROL:WR_DURATION_2[5]
9 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[0]PHY_CONTROL:WR_CMD_OFFSET_2[1]
10 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[2]PHY_CONTROL:WR_CMD_OFFSET_2[3]
11 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[4]PHY_CONTROL:WR_CMD_OFFSET_2[5]
12 ----------------------------PHY_CONTROL:CO_DURATION[0]PHY_CONTROL:CO_DURATION[1]
13 ----------------------------PHY_CONTROL:CO_DURATION[2]PHY_CONTROL:AO_WRLVL_EN[0]
14 ----------------------------PHY_CONTROL:AO_WRLVL_EN[1]PHY_CONTROL:AO_WRLVL_EN[2]
15 ----------------------------PHY_CONTROL:AO_WRLVL_EN[3]PHY_CONTROL:PHY_COUNT_ENABLE
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PHY_CONTROL:RD_DURATION_3[0]PHY_CONTROL:RD_DURATION_3[1]
33 ----------------------------PHY_CONTROL:RD_DURATION_3[2]PHY_CONTROL:RD_DURATION_3[3]
34 ----------------------------PHY_CONTROL:RD_DURATION_3[4]PHY_CONTROL:RD_DURATION_3[5]
35 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[0]PHY_CONTROL:RD_CMD_OFFSET_3[1]
36 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[2]PHY_CONTROL:RD_CMD_OFFSET_3[3]
37 ----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[4]PHY_CONTROL:RD_CMD_OFFSET_3[5]
38 ----------------------------PHY_CONTROL:WR_DURATION_3[0]PHY_CONTROL:WR_DURATION_3[1]
39 ----------------------------PHY_CONTROL:WR_DURATION_3[2]PHY_CONTROL:WR_DURATION_3[3]
40 ----------------------------PHY_CONTROL:WR_DURATION_3[4]PHY_CONTROL:WR_DURATION_3[5]
41 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[0]PHY_CONTROL:WR_CMD_OFFSET_3[1]
42 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[2]PHY_CONTROL:WR_CMD_OFFSET_3[3]
43 ----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[4]PHY_CONTROL:WR_CMD_OFFSET_3[5]
44 ----------------------------PHY_CONTROL:DATA_CTL_A_NPHY_CONTROL:DATA_CTL_B_N
45 ----------------------------PHY_CONTROL:DATA_CTL_C_NPHY_CONTROL:DATA_CTL_D_N
46 ----------------------------PHY_CONTROL:BURST_MODE-
CMT bittile 36
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ------------------------------
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------CMT_TOP:ENABLE.SYNC_BB[0]CMT_TOP:ENABLE.FREQ_BB0[0]
33 ----------------------------CMT_TOP:ENABLE.FREQ_BB1[0]CMT_TOP:ENABLE.FREQ_BB2[0]
34 ----------------------------CMT_TOP:ENABLE.FREQ_BB3[0]CMT_TOP:MUX.FREQ_BB0[0]
35 ----------------------------CMT_TOP:MUX.FREQ_BB1[0]CMT_TOP:MUX.FREQ_BB2[0]
36 ----------------------------CMT_TOP:MUX.FREQ_BB3[0]CMT_TOP:MUX.FREQREFCLK[0]
37 ----------------------------CMT_TOP:MUX.FREQREFCLK[1]CMT_TOP:MUX.FREQREFCLK[2]
38 ----------------------------CMT_TOP:BUF.SYNC_BB.DCMT_TOP:ENABLE.SYNC_BB_N
39 ----------------------------CMT_TOP:BUF.SYNC_BB.UCMT_TOP:ENABLE.SYNC_BB[1]
40 ----------------------------CMT_TOP:DRIVE.SYNC_BBCMT_TOP:MUX.MEMREFCLK[0]
41 ----------------------------CMT_TOP:MUX.MEMREFCLK[1]CMT_TOP:ENABLE.FREQ_BB0[1]
42 ----------------------------CMT_TOP:ENABLE.FREQ_BB0_N[0]CMT_TOP:ENABLE.FREQ_BB1[1]
43 ----------------------------CMT_TOP:ENABLE.FREQ_BB1_N[0]CMT_TOP:ENABLE.FREQ_BB2[1]
44 ----------------------------CMT_TOP:ENABLE.FREQ_BB2_N[0]CMT_TOP:ENABLE.FREQ_BB3[1]
45 ----------------------------CMT_TOP:ENABLE.FREQ_BB3_N[0]CMT_TOP:BUF.FREQ_BB0.D[1]
46 ----------------------------CMT_TOP:BUF.FREQ_BB0.U[0]CMT_TOP:BUF.FREQ_BB1.D[1]
47 ----------------------------CMT_TOP:BUF.FREQ_BB1.U[0]CMT_TOP:BUF.FREQ_BB2.D[1]
48 ----------------------------CMT_TOP:BUF.FREQ_BB2.U[0]CMT_TOP:BUF.FREQ_BB3.D[1]
49 ----------------------------CMT_TOP:BUF.FREQ_BB3.U[0]CMT_TOP:ENABLE.FREQ_BB0[2]
50 ----------------------------CMT_TOP:ENABLE.FREQ_BB0_N[1]CMT_TOP:ENABLE.FREQ_BB1[2]
51 ----------------------------CMT_TOP:ENABLE.FREQ_BB1_N[1]CMT_TOP:ENABLE.FREQ_BB2[2]
52 ----------------------------CMT_TOP:ENABLE.FREQ_BB2_N[1]CMT_TOP:ENABLE.FREQ_BB3[2]
53 ----------------------------CMT_TOP:ENABLE.FREQ_BB3_N[1]CMT_TOP:BUF.FREQ_BB0.U[1]
54 ----------------------------CMT_TOP:BUF.FREQ_BB0.D[0]CMT_TOP:BUF.FREQ_BB1.U[1]
55 ----------------------------CMT_TOP:BUF.FREQ_BB1.D[0]CMT_TOP:BUF.FREQ_BB2.U[1]
56 ----------------------------CMT_TOP:BUF.FREQ_BB2.D[0]CMT_TOP:BUF.FREQ_BB3.U[1]
57 ----------------------------CMT_TOP:BUF.FREQ_BB3.D[0]CMT_TOP:MUX.MEMREFCLK[2]
58 ----------------------------CMT_TOP:MUX.SYNCIN[0]CMT_TOP:MUX.SYNCIN[1]
59 ----------------------------CMT_TOP:MUX.SYNCIN[2]CMT_TOP:MUX.FREQ_BB0[1]
60 ----------------------------CMT_TOP:MUX.FREQ_BB0[2]CMT_TOP:MUX.FREQ_BB1[1]
61 ----------------------------CMT_TOP:MUX.FREQ_BB1[2]CMT_TOP:MUX.FREQ_BB2[1]
62 ----------------------------CMT_TOP:MUX.FREQ_BB2[2]CMT_TOP:MUX.FREQ_BB3[1]
63 ----------------------------CMT_TOP:MUX.FREQ_BB3[2]-
CMT bittile 37
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP00[0]PLL:DRP00[1]
1 ----------------------------PLL:DRP00[2]PLL:DRP00[3]
2 ----------------------------PLL:DRP00[4]PLL:DRP00[5]
3 ----------------------------PLL:DRP00[6]
PLL:IN_DLY_MX_CVDD[0]		PLL:DRP00[7]
PLL:IN_DLY_MX_CVDD[1]
4 ----------------------------PLL:DRP00[8]
PLL:IN_DLY_MX_CVDD[2]		PLL:DRP00[9]
PLL:IN_DLY_MX_CVDD[3]
5 ----------------------------PLL:DRP00[10]
PLL:IN_DLY_MX_CVDD[4]		PLL:DRP00[11]
PLL:IN_DLY_MX_CVDD[5]
6 ----------------------------PLL:DRP00[12]
PLL:HROW_DLY_SET[0]		PLL:DRP00[13]
PLL:HROW_DLY_SET[1]
7 ----------------------------PLL:DRP00[14]
PLL:HROW_DLY_SET[2]		PLL:DRP00[15]
PLL:MUX.CLKIN2[0]
8 ----------------------------PLL:DRP01[0]
PLL:MUX.CLKIN2[1]		PLL:DRP01[1]
PLL:MUX.CLKIN2[2]
9 ----------------------------PLL:DRP01[2]
PLL:MUX.CLKIN1[0]		PLL:DRP01[3]
PLL:MUX.CLKIN1[1]
10 ----------------------------PLL:DRP01[4]
PLL:MUX.CLKIN1[2]		PLL:DRP01[5]
PLL:MUX.CLKFBIN[0]
11 ----------------------------PLL:DRP01[6]
PLL:MUX.CLKFBIN[1]		PLL:DRP01[7]
PLL:MUX.CLKFBIN[2]
12 ----------------------------PLL:BUF.CLKOUT0_FREQ_BB
PLL:DRP01[8]		PLL:BUF.CLKOUT1_FREQ_BB
PLL:DRP01[9]
13 ----------------------------PLL:BUF.CLKOUT2_FREQ_BB
PLL:DRP01[10]		PLL:BUF.CLKOUT3_FREQ_BB
PLL:DRP01[11]
14 ----------------------------PLL:DRP01[12]PLL:DRP01[13]
15 ----------------------------PLL:DRP01[14]PLL:DRP01[15]
16 ----------------------------PLL:DRP02[0]
PLL:SYNTH_CLK_DIV[0]		PLL:DRP02[1]
PLL:SYNTH_CLK_DIV[1]
17 ----------------------------PLL:DRP02[2]PLL:DRP02[3]
18 ----------------------------PLL:DRP02[4]PLL:DRP02[5]
19 ----------------------------PLL:DRP02[6]PLL:DRP02[7]
20 ----------------------------PLL:DRP02[8]PLL:DRP02[9]
21 ----------------------------PLL:DRP02[10]PLL:DRP02[11]
22 ----------------------------PLL:DRP02[12]PLL:DRP02[13]
23 ----------------------------PLL:DRP02[14]PLL:DRP02[15]
24 ----------------------------PLL:DRP03[0]
PLL:SKEW_FLOP_INV[0]		PLL:DRP03[1]
PLL:SKEW_FLOP_INV[1]
25 ----------------------------PLL:DRP03[2]
PLL:SKEW_FLOP_INV[2]		PLL:DRP03[3]
PLL:SKEW_FLOP_INV[3]
26 ----------------------------PLL:DRP03[4]PLL:DRP03[5]
27 ----------------------------PLL:DRP03[6]PLL:DRP03[7]
28 ----------------------------PLL:DRP03[8]PLL:DRP03[9]
29 ----------------------------PLL:DRP03[10]PLL:DRP03[11]
30 ----------------------------PLL:DRP03[12]PLL:DRP03[13]
31 ----------------------------PLL:DRP03[14]PLL:DRP03[15]
32 ----------------------------PLL:DRP04[0]PLL:DRP04[1]
33 ----------------------------PLL:DRP04[2]PLL:DRP04[3]
34 ----------------------------PLL:DRP04[4]PLL:DRP04[5]
35 ----------------------------PLL:DRP04[6]PLL:DRP04[7]
36 ----------------------------PLL:DRP04[8]PLL:DRP04[9]
37 ----------------------------PLL:DRP04[10]PLL:DRP04[11]
38 ----------------------------PLL:DRP04[12]PLL:DRP04[13]
39 ----------------------------PLL:DRP04[14]
PLL:TMUX_MUX_SEL[0]		PLL:DRP04[15]
PLL:TMUX_MUX_SEL[1]
40 ----------------------------PLL:DRP05[0]PLL:DRP05[1]
41 ----------------------------PLL:DRP05[2]
PLL:IN_DLY_EN		PLL:DIRECT_PATH_CNTRL
PLL:DRP05[3]
42 ----------------------------PLL:DRP05[4]
PLL:IN_DLY_MX_DVDD[0]		PLL:DRP05[5]
PLL:IN_DLY_MX_DVDD[1]
43 ----------------------------PLL:DRP05[6]
PLL:IN_DLY_MX_DVDD[2]		PLL:DRP05[7]
PLL:IN_DLY_MX_DVDD[3]
44 ----------------------------PLL:DRP05[8]
PLL:IN_DLY_MX_DVDD[4]		PLL:DRP05[9]
PLL:IN_DLY_MX_DVDD[5]
45 ----------------------------PLL:DRP05[10]
PLL:IN_DLY_SET[0]		PLL:DRP05[11]
PLL:IN_DLY_SET[1]
46 ----------------------------PLL:DRP05[12]
PLL:IN_DLY_SET[2]		PLL:DRP05[13]
PLL:IN_DLY_SET[3]
47 ----------------------------PLL:DRP05[14]
PLL:IN_DLY_SET[4]		PLL:DRP05[15]
PLL:IN_DLY_SET[5]
48 ----------------------------PLL:CLKOUT5_LT[0]
PLL:DRP06[0]		PLL:CLKOUT5_LT[1]
PLL:DRP06[1]
49 ----------------------------PLL:CLKOUT5_LT[2]
PLL:DRP06[2]		PLL:CLKOUT5_LT[3]
PLL:DRP06[3]
50 ----------------------------PLL:CLKOUT5_LT[4]
PLL:DRP06[4]		PLL:CLKOUT5_LT[5]
PLL:DRP06[5]
51 ----------------------------PLL:CLKOUT5_HT[0]
PLL:DRP06[6]		PLL:CLKOUT5_HT[1]
PLL:DRP06[7]
52 ----------------------------PLL:CLKOUT5_HT[2]
PLL:DRP06[8]		PLL:CLKOUT5_HT[3]
PLL:DRP06[9]
53 ----------------------------PLL:CLKOUT5_HT[4]
PLL:DRP06[10]		PLL:CLKOUT5_HT[5]
PLL:DRP06[11]
54 ----------------------------PLL:CLKOUT5_EN
PLL:DRP06[12]		PLL:CLKOUT5_PM[0]
PLL:DRP06[13]
55 ----------------------------PLL:CLKOUT5_PM[1]
PLL:DRP06[14]		PLL:CLKOUT5_PM[2]
PLL:DRP06[15]
56 ----------------------------PLL:CLKOUT5_DT[0]
PLL:DRP07[0]		PLL:CLKOUT5_DT[1]
PLL:DRP07[1]
57 ----------------------------PLL:CLKOUT5_DT[2]
PLL:DRP07[2]		PLL:CLKOUT5_DT[3]
PLL:DRP07[3]
58 ----------------------------PLL:CLKOUT5_DT[4]
PLL:DRP07[4]		PLL:CLKOUT5_DT[5]
PLL:DRP07[5]
59 ----------------------------PLL:CLKOUT5_NOCOUNT
PLL:DRP07[6]		PLL:CLKOUT5_EDGE
PLL:DRP07[7]
60 ----------------------------PLL:CLKOUT5_MX[0]
PLL:DRP07[8]		PLL:CLKOUT5_MX[1]
PLL:DRP07[9]
61 ----------------------------PLL:DRP07[10]PLL:DRP07[11]
62 ----------------------------PLL:DRP07[12]PLL:DRP07[13]
63 ----------------------------PLL:DRP07[14]PLL:DRP07[15]
CMT bittile 38
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:CLKOUT0_LT[0]
PLL:DRP08[0]		PLL:CLKOUT0_LT[1]
PLL:DRP08[1]
1 ----------------------------PLL:CLKOUT0_LT[2]
PLL:DRP08[2]		PLL:CLKOUT0_LT[3]
PLL:DRP08[3]
2 ----------------------------PLL:CLKOUT0_LT[4]
PLL:DRP08[4]		PLL:CLKOUT0_LT[5]
PLL:DRP08[5]
3 ----------------------------PLL:CLKOUT0_HT[0]
PLL:DRP08[6]		PLL:CLKOUT0_HT[1]
PLL:DRP08[7]
4 ----------------------------PLL:CLKOUT0_HT[2]
PLL:DRP08[8]		PLL:CLKOUT0_HT[3]
PLL:DRP08[9]
5 ----------------------------PLL:CLKOUT0_HT[4]
PLL:DRP08[10]		PLL:CLKOUT0_HT[5]
PLL:DRP08[11]
6 ----------------------------PLL:CLKOUT0_EN
PLL:DRP08[12]		PLL:CLKOUT0_PM[0]
PLL:DRP08[13]
7 ----------------------------PLL:CLKOUT0_PM[1]
PLL:DRP08[14]		PLL:CLKOUT0_PM[2]
PLL:DRP08[15]
8 ----------------------------PLL:CLKOUT0_DT[0]
PLL:DRP09[0]		PLL:CLKOUT0_DT[1]
PLL:DRP09[1]
9 ----------------------------PLL:CLKOUT0_DT[2]
PLL:DRP09[2]		PLL:CLKOUT0_DT[3]
PLL:DRP09[3]
10 ----------------------------PLL:CLKOUT0_DT[4]
PLL:DRP09[4]		PLL:CLKOUT0_DT[5]
PLL:DRP09[5]
11 ----------------------------PLL:CLKOUT0_NOCOUNT
PLL:DRP09[6]		PLL:CLKOUT0_EDGE
PLL:DRP09[7]
12 ----------------------------PLL:CLKOUT0_MX[0]
PLL:DRP09[8]		PLL:CLKOUT0_MX[1]
PLL:DRP09[9]
13 ----------------------------PLL:DRP09[10]PLL:DRP09[11]
14 ----------------------------PLL:DRP09[12]PLL:DRP09[13]
15 ----------------------------PLL:DRP09[14]PLL:DRP09[15]
16 ----------------------------PLL:CLKOUT1_LT[0]
PLL:DRP0A[0]		PLL:CLKOUT1_LT[1]
PLL:DRP0A[1]
17 ----------------------------PLL:CLKOUT1_LT[2]
PLL:DRP0A[2]		PLL:CLKOUT1_LT[3]
PLL:DRP0A[3]
18 ----------------------------PLL:CLKOUT1_LT[4]
PLL:DRP0A[4]		PLL:CLKOUT1_LT[5]
PLL:DRP0A[5]
19 ----------------------------PLL:CLKOUT1_HT[0]
PLL:DRP0A[6]		PLL:CLKOUT1_HT[1]
PLL:DRP0A[7]
20 ----------------------------PLL:CLKOUT1_HT[2]
PLL:DRP0A[8]		PLL:CLKOUT1_HT[3]
PLL:DRP0A[9]
21 ----------------------------PLL:CLKOUT1_HT[4]
PLL:DRP0A[10]		PLL:CLKOUT1_HT[5]
PLL:DRP0A[11]
22 ----------------------------PLL:CLKOUT1_EN
PLL:DRP0A[12]		PLL:CLKOUT1_PM[0]
PLL:DRP0A[13]
23 ----------------------------PLL:CLKOUT1_PM[1]
PLL:DRP0A[14]		PLL:CLKOUT1_PM[2]
PLL:DRP0A[15]
24 ----------------------------PLL:CLKOUT1_DT[0]
PLL:DRP0B[0]		PLL:CLKOUT1_DT[1]
PLL:DRP0B[1]
25 ----------------------------PLL:CLKOUT1_DT[2]
PLL:DRP0B[2]		PLL:CLKOUT1_DT[3]
PLL:DRP0B[3]
26 ----------------------------PLL:CLKOUT1_DT[4]
PLL:DRP0B[4]		PLL:CLKOUT1_DT[5]
PLL:DRP0B[5]
27 ----------------------------PLL:CLKOUT1_NOCOUNT
PLL:DRP0B[6]		PLL:CLKOUT1_EDGE
PLL:DRP0B[7]
28 ----------------------------PLL:CLKOUT1_MX[0]
PLL:DRP0B[8]		PLL:CLKOUT1_MX[1]
PLL:DRP0B[9]
29 ----------------------------PLL:DRP0B[10]PLL:DRP0B[11]
30 ----------------------------PLL:DRP0B[12]PLL:DRP0B[13]
31 ----------------------------PLL:DRP0B[14]PLL:DRP0B[15]
32 ----------------------------PLL:CLKOUT2_LT[0]
PLL:DRP0C[0]		PLL:CLKOUT2_LT[1]
PLL:DRP0C[1]
33 ----------------------------PLL:CLKOUT2_LT[2]
PLL:DRP0C[2]		PLL:CLKOUT2_LT[3]
PLL:DRP0C[3]
34 ----------------------------PLL:CLKOUT2_LT[4]
PLL:DRP0C[4]		PLL:CLKOUT2_LT[5]
PLL:DRP0C[5]
35 ----------------------------PLL:CLKOUT2_HT[0]
PLL:DRP0C[6]		PLL:CLKOUT2_HT[1]
PLL:DRP0C[7]
36 ----------------------------PLL:CLKOUT2_HT[2]
PLL:DRP0C[8]		PLL:CLKOUT2_HT[3]
PLL:DRP0C[9]
37 ----------------------------PLL:CLKOUT2_HT[4]
PLL:DRP0C[10]		PLL:CLKOUT2_HT[5]
PLL:DRP0C[11]
38 ----------------------------PLL:CLKOUT2_EN
PLL:DRP0C[12]		PLL:CLKOUT2_PM[0]
PLL:DRP0C[13]
39 ----------------------------PLL:CLKOUT2_PM[1]
PLL:DRP0C[14]		PLL:CLKOUT2_PM[2]
PLL:DRP0C[15]
40 ----------------------------PLL:CLKOUT2_DT[0]
PLL:DRP0D[0]		PLL:CLKOUT2_DT[1]
PLL:DRP0D[1]
41 ----------------------------PLL:CLKOUT2_DT[2]
PLL:DRP0D[2]		PLL:CLKOUT2_DT[3]
PLL:DRP0D[3]
42 ----------------------------PLL:CLKOUT2_DT[4]
PLL:DRP0D[4]		PLL:CLKOUT2_DT[5]
PLL:DRP0D[5]
43 ----------------------------PLL:CLKOUT2_NOCOUNT
PLL:DRP0D[6]		PLL:CLKOUT2_EDGE
PLL:DRP0D[7]
44 ----------------------------PLL:CLKOUT2_MX[0]
PLL:DRP0D[8]		PLL:CLKOUT2_MX[1]
PLL:DRP0D[9]
45 ----------------------------PLL:DRP0D[10]PLL:DRP0D[11]
46 ----------------------------PLL:DRP0D[12]PLL:DRP0D[13]
47 ----------------------------PLL:DRP0D[14]PLL:DRP0D[15]
48 ----------------------------PLL:CLKOUT3_LT[0]
PLL:DRP0E[0]		PLL:CLKOUT3_LT[1]
PLL:DRP0E[1]
49 ----------------------------PLL:CLKOUT3_LT[2]
PLL:DRP0E[2]		PLL:CLKOUT3_LT[3]
PLL:DRP0E[3]
50 ----------------------------PLL:CLKOUT3_LT[4]
PLL:DRP0E[4]		PLL:CLKOUT3_LT[5]
PLL:DRP0E[5]
51 ----------------------------PLL:CLKOUT3_HT[0]
PLL:DRP0E[6]		PLL:CLKOUT3_HT[1]
PLL:DRP0E[7]
52 ----------------------------PLL:CLKOUT3_HT[2]
PLL:DRP0E[8]		PLL:CLKOUT3_HT[3]
PLL:DRP0E[9]
53 ----------------------------PLL:CLKOUT3_HT[4]
PLL:DRP0E[10]		PLL:CLKOUT3_HT[5]
PLL:DRP0E[11]
54 ----------------------------PLL:CLKOUT3_EN
PLL:DRP0E[12]		PLL:CLKOUT3_PM[0]
PLL:DRP0E[13]
55 ----------------------------PLL:CLKOUT3_PM[1]
PLL:DRP0E[14]		PLL:CLKOUT3_PM[2]
PLL:DRP0E[15]
56 ----------------------------PLL:CLKOUT3_DT[0]
PLL:DRP0F[0]		PLL:CLKOUT3_DT[1]
PLL:DRP0F[1]
57 ----------------------------PLL:CLKOUT3_DT[2]
PLL:DRP0F[2]		PLL:CLKOUT3_DT[3]
PLL:DRP0F[3]
58 ----------------------------PLL:CLKOUT3_DT[4]
PLL:DRP0F[4]		PLL:CLKOUT3_DT[5]
PLL:DRP0F[5]
59 ----------------------------PLL:CLKOUT3_NOCOUNT
PLL:DRP0F[6]		PLL:CLKOUT3_EDGE
PLL:DRP0F[7]
60 ----------------------------PLL:CLKOUT3_MX[0]
PLL:DRP0F[8]		PLL:CLKOUT3_MX[1]
PLL:DRP0F[9]
61 ----------------------------PLL:DRP0F[10]PLL:DRP0F[11]
62 ----------------------------PLL:DRP0F[12]PLL:DRP0F[13]
63 ----------------------------PLL:DRP0F[14]PLL:DRP0F[15]
CMT bittile 39
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:CLKOUT4_LT[0]
PLL:DRP10[0]		PLL:CLKOUT4_LT[1]
PLL:DRP10[1]
1 ----------------------------PLL:CLKOUT4_LT[2]
PLL:DRP10[2]		PLL:CLKOUT4_LT[3]
PLL:DRP10[3]
2 ----------------------------PLL:CLKOUT4_LT[4]
PLL:DRP10[4]		PLL:CLKOUT4_LT[5]
PLL:DRP10[5]
3 ----------------------------PLL:CLKOUT4_HT[0]
PLL:DRP10[6]		PLL:CLKOUT4_HT[1]
PLL:DRP10[7]
4 ----------------------------PLL:CLKOUT4_HT[2]
PLL:DRP10[8]		PLL:CLKOUT4_HT[3]
PLL:DRP10[9]
5 ----------------------------PLL:CLKOUT4_HT[4]
PLL:DRP10[10]		PLL:CLKOUT4_HT[5]
PLL:DRP10[11]
6 ----------------------------PLL:CLKOUT4_EN
PLL:DRP10[12]		PLL:CLKOUT4_PM[0]
PLL:DRP10[13]
7 ----------------------------PLL:CLKOUT4_PM[1]
PLL:DRP10[14]		PLL:CLKOUT4_PM[2]
PLL:DRP10[15]
8 ----------------------------PLL:CLKOUT4_DT[0]
PLL:DRP11[0]		PLL:CLKOUT4_DT[1]
PLL:DRP11[1]
9 ----------------------------PLL:CLKOUT4_DT[2]
PLL:DRP11[2]		PLL:CLKOUT4_DT[3]
PLL:DRP11[3]
10 ----------------------------PLL:CLKOUT4_DT[4]
PLL:DRP11[4]		PLL:CLKOUT4_DT[5]
PLL:DRP11[5]
11 ----------------------------PLL:CLKOUT4_NOCOUNT
PLL:DRP11[6]		PLL:CLKOUT4_EDGE
PLL:DRP11[7]
12 ----------------------------PLL:CLKOUT4_MX[0]
PLL:DRP11[8]		PLL:CLKOUT4_MX[1]
PLL:DRP11[9]
13 ----------------------------PLL:DRP11[10]PLL:DRP11[11]
14 ----------------------------PLL:DRP11[12]PLL:DRP11[13]
15 ----------------------------PLL:DRP11[14]PLL:DRP11[15]
16 ----------------------------PLL:DRP12[0]PLL:DRP12[1]
17 ----------------------------PLL:DRP12[2]PLL:DRP12[3]
18 ----------------------------PLL:DRP12[4]PLL:DRP12[5]
19 ----------------------------PLL:DRP12[6]PLL:DRP12[7]
20 ----------------------------PLL:DRP12[8]PLL:DRP12[9]
21 ----------------------------PLL:DRP12[10]PLL:DRP12[11]
22 ----------------------------PLL:DRP12[12]PLL:DRP12[13]
23 ----------------------------PLL:DRP12[14]PLL:DRP12[15]
24 ----------------------------PLL:DRP13[0]PLL:DRP13[1]
25 ----------------------------PLL:DRP13[2]PLL:DRP13[3]
26 ----------------------------PLL:DRP13[4]PLL:DRP13[5]
27 ----------------------------PLL:DRP13[6]PLL:DRP13[7]
28 ----------------------------PLL:DRP13[8]PLL:DRP13[9]
29 ----------------------------PLL:DRP13[10]PLL:DRP13[11]
30 ----------------------------PLL:DRP13[12]PLL:DRP13[13]
31 ----------------------------PLL:DRP13[14]PLL:DRP13[15]
32 ----------------------------PLL:CLKFBOUT_LT[0]
PLL:DRP14[0]		PLL:CLKFBOUT_LT[1]
PLL:DRP14[1]
33 ----------------------------PLL:CLKFBOUT_LT[2]
PLL:DRP14[2]		PLL:CLKFBOUT_LT[3]
PLL:DRP14[3]
34 ----------------------------PLL:CLKFBOUT_LT[4]
PLL:DRP14[4]		PLL:CLKFBOUT_LT[5]
PLL:DRP14[5]
35 ----------------------------PLL:CLKFBOUT_HT[0]
PLL:DRP14[6]		PLL:CLKFBOUT_HT[1]
PLL:DRP14[7]
36 ----------------------------PLL:CLKFBOUT_HT[2]
PLL:DRP14[8]		PLL:CLKFBOUT_HT[3]
PLL:DRP14[9]
37 ----------------------------PLL:CLKFBOUT_HT[4]
PLL:DRP14[10]		PLL:CLKFBOUT_HT[5]
PLL:DRP14[11]
38 ----------------------------PLL:CLKFBOUT_EN
PLL:DRP14[12]		PLL:CLKFBOUT_PM[0]
PLL:DRP14[13]
39 ----------------------------PLL:CLKFBOUT_PM[1]
PLL:DRP14[14]		PLL:CLKFBOUT_PM[2]
PLL:DRP14[15]
40 ----------------------------PLL:CLKFBOUT_DT[0]
PLL:DRP15[0]		PLL:CLKFBOUT_DT[1]
PLL:DRP15[1]
41 ----------------------------PLL:CLKFBOUT_DT[2]
PLL:DRP15[2]		PLL:CLKFBOUT_DT[3]
PLL:DRP15[3]
42 ----------------------------PLL:CLKFBOUT_DT[4]
PLL:DRP15[4]		PLL:CLKFBOUT_DT[5]
PLL:DRP15[5]
43 ----------------------------PLL:CLKFBOUT_NOCOUNT
PLL:DRP15[6]		PLL:CLKFBOUT_EDGE
PLL:DRP15[7]
44 ----------------------------PLL:CLKFBOUT_MX[0]
PLL:DRP15[8]		PLL:CLKFBOUT_MX[1]
PLL:DRP15[9]
45 ----------------------------PLL:DRP15[10]PLL:DRP15[11]
46 ----------------------------PLL:DRP15[12]PLL:DRP15[13]
47 ----------------------------PLL:DRP15[14]PLL:DRP15[15]
48 ----------------------------PLL:DIVCLK_LT[0]
PLL:DRP16[0]		PLL:DIVCLK_LT[1]
PLL:DRP16[1]
49 ----------------------------PLL:DIVCLK_LT[2]
PLL:DRP16[2]		PLL:DIVCLK_LT[3]
PLL:DRP16[3]
50 ----------------------------PLL:DIVCLK_LT[4]
PLL:DRP16[4]		PLL:DIVCLK_LT[5]
PLL:DRP16[5]
51 ----------------------------PLL:DIVCLK_HT[0]
PLL:DRP16[6]		PLL:DIVCLK_HT[1]
PLL:DRP16[7]
52 ----------------------------PLL:DIVCLK_HT[2]
PLL:DRP16[8]		PLL:DIVCLK_HT[3]
PLL:DRP16[9]
53 ----------------------------PLL:DIVCLK_HT[4]
PLL:DRP16[10]		PLL:DIVCLK_HT[5]
PLL:DRP16[11]
54 ----------------------------PLL:DIVCLK_NOCOUNT
PLL:DRP16[12]		PLL:DIVCLK_EDGE
PLL:DRP16[13]
55 ----------------------------PLL:DRP16[14]PLL:DRP16[15]
56 ----------------------------PLL:CLKFBIN_LT[0]
PLL:DRP17[0]		PLL:CLKFBIN_LT[1]
PLL:DRP17[1]
57 ----------------------------PLL:CLKFBIN_LT[2]
PLL:DRP17[2]		PLL:CLKFBIN_LT[3]
PLL:DRP17[3]
58 ----------------------------PLL:CLKFBIN_LT[4]
PLL:DRP17[4]		PLL:CLKFBIN_LT[5]
PLL:DRP17[5]
59 ----------------------------PLL:CLKFBIN_HT[0]
PLL:DRP17[6]		PLL:CLKFBIN_HT[1]
PLL:DRP17[7]
60 ----------------------------PLL:CLKFBIN_HT[2]
PLL:DRP17[8]		PLL:CLKFBIN_HT[3]
PLL:DRP17[9]
61 ----------------------------PLL:CLKFBIN_HT[4]
PLL:DRP17[10]		PLL:CLKFBIN_HT[5]
PLL:DRP17[11]
62 ----------------------------PLL:CLKFBIN_NOCOUNT
PLL:DRP17[12]		PLL:CLKFBIN_EDGE
PLL:DRP17[13]
63 ----------------------------PLL:DRP17[14]PLL:DRP17[15]
CMT bittile 40
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP18[0]
PLL:LOCK_CNT[0]		PLL:DRP18[1]
PLL:LOCK_CNT[1]
1 ----------------------------PLL:DRP18[2]
PLL:LOCK_CNT[2]		PLL:DRP18[3]
PLL:LOCK_CNT[3]
2 ----------------------------PLL:DRP18[4]
PLL:LOCK_CNT[4]		PLL:DRP18[5]
PLL:LOCK_CNT[5]
3 ----------------------------PLL:DRP18[6]
PLL:LOCK_CNT[6]		PLL:DRP18[7]
PLL:LOCK_CNT[7]
4 ----------------------------PLL:DRP18[8]
PLL:LOCK_CNT[8]		PLL:DRP18[9]
PLL:LOCK_CNT[9]
5 ----------------------------PLL:DRP18[10]PLL:DRP18[11]
6 ----------------------------PLL:DRP18[12]PLL:DRP18[13]
7 ----------------------------PLL:DRP18[14]PLL:DRP18[15]
8 ----------------------------PLL:DRP19[0]
PLL:UNLOCK_CNT[0]		PLL:DRP19[1]
PLL:UNLOCK_CNT[1]
9 ----------------------------PLL:DRP19[2]
PLL:UNLOCK_CNT[2]		PLL:DRP19[3]
PLL:UNLOCK_CNT[3]
10 ----------------------------PLL:DRP19[4]
PLL:UNLOCK_CNT[4]		PLL:DRP19[5]
PLL:UNLOCK_CNT[5]
11 ----------------------------PLL:DRP19[6]
PLL:UNLOCK_CNT[6]		PLL:DRP19[7]
PLL:UNLOCK_CNT[7]
12 ----------------------------PLL:DRP19[8]
PLL:UNLOCK_CNT[8]		PLL:DRP19[9]
PLL:UNLOCK_CNT[9]
13 ----------------------------PLL:DRP19[10]
PLL:LOCK_FB_DLY[0]		PLL:DRP19[11]
PLL:LOCK_FB_DLY[1]
14 ----------------------------PLL:DRP19[12]
PLL:LOCK_FB_DLY[2]		PLL:DRP19[13]
PLL:LOCK_FB_DLY[3]
15 ----------------------------PLL:DRP19[14]
PLL:LOCK_FB_DLY[4]		PLL:DRP19[15]
16 ----------------------------PLL:DRP1A[0]
PLL:LOCK_SAT_HIGH[0]		PLL:DRP1A[1]
PLL:LOCK_SAT_HIGH[1]
17 ----------------------------PLL:DRP1A[2]
PLL:LOCK_SAT_HIGH[2]		PLL:DRP1A[3]
PLL:LOCK_SAT_HIGH[3]
18 ----------------------------PLL:DRP1A[4]
PLL:LOCK_SAT_HIGH[4]		PLL:DRP1A[5]
PLL:LOCK_SAT_HIGH[5]
19 ----------------------------PLL:DRP1A[6]
PLL:LOCK_SAT_HIGH[6]		PLL:DRP1A[7]
PLL:LOCK_SAT_HIGH[7]
20 ----------------------------PLL:DRP1A[8]
PLL:LOCK_SAT_HIGH[8]		PLL:DRP1A[9]
PLL:LOCK_SAT_HIGH[9]
21 ----------------------------PLL:DRP1A[10]
PLL:LOCK_REF_DLY[0]		PLL:DRP1A[11]
PLL:LOCK_REF_DLY[1]
22 ----------------------------PLL:DRP1A[12]
PLL:LOCK_REF_DLY[2]		PLL:DRP1A[13]
PLL:LOCK_REF_DLY[3]
23 ----------------------------PLL:DRP1A[14]
PLL:LOCK_REF_DLY[4]		PLL:DRP1A[15]
PLL:FREQ_COMP[0]
24 ----------------------------PLL:DRP1B[0]
PLL:FREQ_COMP[1]		PLL:DRP1B[1]
25 ----------------------------PLL:DRP1B[2]PLL:DRP1B[3]
26 ----------------------------PLL:DRP1B[4]PLL:DRP1B[5]
27 ----------------------------PLL:DRP1B[6]PLL:DRP1B[7]
28 ----------------------------PLL:DRP1B[8]PLL:DRP1B[9]
29 ----------------------------PLL:DRP1B[10]PLL:DRP1B[11]
30 ----------------------------PLL:DRP1B[12]PLL:DRP1B[13]
31 ----------------------------PLL:DRP1B[14]PLL:DRP1B[15]
32 ----------------------------PLL:DRP1C[0]
PLL:SPARE_DIGITAL[0]		PLL:DRP1C[1]
PLL:SPARE_DIGITAL[1]
33 ----------------------------PLL:DRP1C[2]
PLL:SPARE_DIGITAL[2]		PLL:DRP1C[3]
PLL:SPARE_DIGITAL[3]
34 ----------------------------PLL:DRP1C[4]
PLL:SPARE_DIGITAL[4]		PLL:DRP1C[5]
35 ----------------------------PLL:DRP1C[6]PLL:DRP1C[7]
36 ----------------------------PLL:DRP1C[8]PLL:DRP1C[9]
37 ----------------------------PLL:DRP1C[10]PLL:DRP1C[11]
38 ----------------------------PLL:DRP1C[12]PLL:DRP1C[13]
39 ----------------------------PLL:DRP1C[14]PLL:DRP1C[15]
40 ----------------------------PLL:DRP1D[0]PLL:DRP1D[1]
41 ----------------------------PLL:DRP1D[2]PLL:DRP1D[3]
42 ----------------------------PLL:DRP1D[4]
PLL:PFD[0]		PLL:DRP1D[5]
PLL:PFD[1]
43 ----------------------------PLL:DRP1D[6]
PLL:PFD[2]		PLL:DRP1D[7]
PLL:PFD[3]
44 ----------------------------PLL:DRP1D[8]
PLL:PFD[4]		PLL:DRP1D[9]
PLL:PFD[5]
45 ----------------------------PLL:DRP1D[10]
PLL:PFD[6]		PLL:DRP1D[11]
46 ----------------------------PLL:DRP1D[12]PLL:DRP1D[13]
47 ----------------------------PLL:DRP1D[14]PLL:DRP1D[15]
48 ----------------------------PLL:DRP1E[0]PLL:DRP1E[1]
49 ----------------------------PLL:DRP1E[2]PLL:DRP1E[3]
50 ----------------------------PLL:DRP1E[4]PLL:DRP1E[5]
51 ----------------------------PLL:DRP1E[6]PLL:DRP1E[7]
52 ----------------------------PLL:DRP1E[8]PLL:DRP1E[9]
53 ----------------------------PLL:DRP1E[10]PLL:DRP1E[11]
54 ----------------------------PLL:DRP1E[12]PLL:DRP1E[13]
55 ----------------------------PLL:DRP1E[14]
PLL:SEL_LV_NMOS		PLL:DRP1E[15]
PLL:SUP_SEL_DREG
56 ----------------------------PLL:DRP1F[0]
PLL:DVDD_VBG_SEL[0]		PLL:DRP1F[1]
PLL:DVDD_VBG_SEL[1]
57 ----------------------------PLL:DRP1F[2]
PLL:DVDD_VBG_SEL[2]		PLL:DRP1F[3]
PLL:DVDD_VBG_SEL[3]
58 ----------------------------PLL:DRP1F[4]
PLL:DVDD_VBG_PD[0]		PLL:DRP1F[5]
PLL:DVDD_VBG_PD[1]
59 ----------------------------PLL:DRP1F[6]
PLL:DVDD_VBG_PD[2]		PLL:DRP1F[7]
PLL:DVDD_COMP_SET[0]
60 ----------------------------PLL:DRP1F[8]
PLL:DVDD_COMP_SET[1]		PLL:DRP1F[9]
PLL:DVDD_COMP_SET[2]
61 ----------------------------PLL:DRP1F[10]PLL:DRP1F[11]
62 ----------------------------PLL:DRP1F[12]PLL:DRP1F[13]
63 ----------------------------PLL:DRP1F[14]PLL:DRP1F[15]
CMT bittile 41
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP20[0]PLL:DRP20[1]
1 ----------------------------PLL:DRP20[2]PLL:DRP20[3]
2 ----------------------------PLL:DRP20[4]PLL:DRP20[5]
3 ----------------------------PLL:DRP20[6]PLL:DRP20[7]
4 ----------------------------PLL:DRP20[8]PLL:DRP20[9]
5 ----------------------------PLL:DRP20[10]PLL:DRP20[11]
6 ----------------------------PLL:DRP20[12]PLL:DRP20[13]
7 ----------------------------PLL:DRP20[14]PLL:DRP20[15]
8 ----------------------------PLL:DRP21[0]PLL:DRP21[1]
9 ----------------------------PLL:DRP21[2]PLL:DRP21[3]
10 ----------------------------PLL:DRP21[4]PLL:DRP21[5]
11 ----------------------------PLL:DRP21[6]PLL:DRP21[7]
12 ----------------------------PLL:DRP21[8]PLL:DRP21[9]
13 ----------------------------PLL:DRP21[10]PLL:DRP21[11]
14 ----------------------------PLL:DRP21[12]PLL:DRP21[13]
15 ----------------------------PLL:DRP21[14]PLL:DRP21[15]
16 ----------------------------PLL:DRP22[0]
PLL:EN_VCO_DIV6		PLL:DRP22[1]
PLL:EN_VCO_DIV1
17 ----------------------------PLL:DRP22[2]PLL:DRP22[3]
18 ----------------------------PLL:DRP22[4]PLL:DRP22[5]
19 ----------------------------PLL:DRP22[6]PLL:DRP22[7]
20 ----------------------------PLL:DRP22[8]PLL:DRP22[9]
21 ----------------------------PLL:DRP22[10]PLL:DRP22[11]
22 ----------------------------PLL:DRP22[12]PLL:DRP22[13]
23 ----------------------------PLL:DRP22[14]PLL:DRP22[15]
24 ----------------------------PLL:DRP23[0]PLL:DRP23[1]
25 ----------------------------PLL:DRP23[2]PLL:DRP23[3]
26 ----------------------------PLL:DRP23[4]PLL:DRP23[5]
27 ----------------------------PLL:DRP23[6]PLL:DRP23[7]
28 ----------------------------PLL:DRP23[8]PLL:DRP23[9]
29 ----------------------------PLL:DRP23[10]PLL:DRP23[11]
30 ----------------------------PLL:DRP23[12]PLL:DRP23[13]
31 ----------------------------PLL:DRP23[14]PLL:DRP23[15]
32 ----------------------------PLL:DRP24[0]PLL:DRP24[1]
33 ----------------------------PLL:DRP24[2]PLL:DRP24[3]
34 ----------------------------PLL:DRP24[4]PLL:DRP24[5]
35 ----------------------------PLL:DRP24[6]PLL:DRP24[7]
36 ----------------------------PLL:DRP24[8]PLL:DRP24[9]
37 ----------------------------PLL:DRP24[10]PLL:DRP24[11]
38 ----------------------------PLL:DRP24[12]PLL:DRP24[13]
39 ----------------------------PLL:DRP24[14]PLL:DRP24[15]
40 ----------------------------PLL:DRP25[0]PLL:DRP25[1]
41 ----------------------------PLL:DRP25[2]PLL:DRP25[3]
42 ----------------------------PLL:DRP25[4]PLL:DRP25[5]
43 ----------------------------PLL:DRP25[6]PLL:DRP25[7]
44 ----------------------------PLL:DRP25[8]PLL:DRP25[9]
45 ----------------------------PLL:DRP25[10]PLL:DRP25[11]
46 ----------------------------PLL:DRP25[12]PLL:DRP25[13]
47 ----------------------------PLL:DRP25[14]PLL:DRP25[15]
48 ----------------------------PLL:DRP26[0]PLL:DRP26[1]
49 ----------------------------PLL:DRP26[2]PLL:ANALOG_MISC[0]
PLL:DRP26[3]
50 ----------------------------PLL:ANALOG_MISC[1]
PLL:DRP26[4]		PLL:DRP26[5]
51 ----------------------------PLL:DRP26[6]PLL:ANALOG_MISC[2]
PLL:DRP26[7]
52 ----------------------------PLL:ANALOG_MISC[3]
PLL:DRP26[8]		PLL:DRP26[9]
53 ----------------------------PLL:DRP26[10]PLL:DRP26[11]
54 ----------------------------PLL:DRP26[12]PLL:DRP26[13]
55 ----------------------------PLL:DRP26[14]PLL:DRP26[15]
56 ----------------------------PLL:DRP27[0]PLL:DRP27[1]
57 ----------------------------PLL:DRP27[2]PLL:DRP27[3]
58 ----------------------------PLL:DRP27[4]PLL:DRP27[5]
59 ----------------------------PLL:DRP27[6]PLL:DRP27[7]
60 ----------------------------PLL:DRP27[8]PLL:DRP27[9]
61 ----------------------------PLL:DRP27[10]PLL:DRP27[11]
62 ----------------------------PLL:DRP27[12]PLL:DRP27[13]
63 ----------------------------PLL:DRP27[14]PLL:DRP27[15]
CMT bittile 42
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP28[0]PLL:DRP28[1]
1 ----------------------------PLL:DRP28[2]PLL:DRP28[3]
2 ----------------------------PLL:DRP28[4]PLL:DRP28[5]
3 ----------------------------PLL:DRP28[6]PLL:DRP28[7]
4 ----------------------------PLL:DRP28[8]PLL:DRP28[9]
5 ----------------------------PLL:DRP28[10]PLL:DRP28[11]
6 ----------------------------PLL:DRP28[12]PLL:DRP28[13]
7 ----------------------------PLL:DRP28[14]PLL:DRP28[15]
8 ----------------------------PLL:DRP29[0]PLL:DRP29[1]
9 ----------------------------PLL:DRP29[2]PLL:DRP29[3]
10 ----------------------------PLL:DRP29[4]PLL:DRP29[5]
11 ----------------------------PLL:DRP29[6]PLL:DRP29[7]
12 ----------------------------PLL:DRP29[8]PLL:DRP29[9]
13 ----------------------------PLL:DRP29[10]PLL:DRP29[11]
14 ----------------------------PLL:DRP29[12]PLL:DRP29[13]
15 ----------------------------PLL:DRP29[14]PLL:DRP29[15]
16 ----------------------------PLL:DRP2A[0]PLL:DRP2A[1]
17 ----------------------------PLL:DRP2A[2]PLL:DRP2A[3]
18 ----------------------------PLL:DRP2A[4]PLL:DRP2A[5]
19 ----------------------------PLL:DRP2A[6]PLL:DRP2A[7]
20 ----------------------------PLL:DRP2A[8]PLL:DRP2A[9]
21 ----------------------------PLL:DRP2A[10]PLL:DRP2A[11]
22 ----------------------------PLL:DRP2A[12]PLL:DRP2A[13]
23 ----------------------------PLL:DRP2A[14]PLL:DRP2A[15]
24 ----------------------------PLL:DRP2B[0]PLL:DRP2B[1]
25 ----------------------------PLL:DRP2B[2]PLL:DRP2B[3]
26 ----------------------------PLL:DRP2B[4]PLL:DRP2B[5]
27 ----------------------------PLL:DRP2B[6]PLL:DRP2B[7]
28 ----------------------------PLL:DRP2B[8]PLL:DRP2B[9]
29 ----------------------------PLL:DRP2B[10]PLL:DRP2B[11]
30 ----------------------------PLL:DRP2B[12]PLL:DRP2B[13]
31 ----------------------------PLL:DRP2B[14]PLL:DRP2B[15]
32 ----------------------------PLL:DRP2C[0]PLL:DRP2C[1]
33 ----------------------------PLL:DRP2C[2]PLL:DRP2C[3]
34 ----------------------------PLL:DRP2C[4]PLL:DRP2C[5]
35 ----------------------------PLL:DRP2C[6]PLL:DRP2C[7]
36 ----------------------------PLL:DRP2C[8]PLL:DRP2C[9]
37 ----------------------------PLL:DRP2C[10]PLL:DRP2C[11]
38 ----------------------------PLL:DRP2C[12]PLL:DRP2C[13]
39 ----------------------------PLL:DRP2C[14]PLL:DRP2C[15]
40 ----------------------------PLL:DRP2D[0]PLL:DRP2D[1]
41 ----------------------------PLL:DRP2D[2]PLL:DRP2D[3]
42 ----------------------------PLL:DRP2D[4]PLL:DRP2D[5]
43 ----------------------------PLL:DRP2D[6]PLL:DRP2D[7]
44 ----------------------------PLL:DRP2D[8]PLL:DRP2D[9]
45 ----------------------------PLL:DRP2D[10]PLL:DRP2D[11]
46 ----------------------------PLL:DRP2D[12]PLL:DRP2D[13]
47 ----------------------------PLL:DRP2D[14]PLL:DRP2D[15]
48 ----------------------------PLL:DRP2E[0]PLL:DRP2E[1]
49 ----------------------------PLL:DRP2E[2]PLL:DRP2E[3]
50 ----------------------------PLL:DRP2E[4]PLL:DRP2E[5]
51 ----------------------------PLL:DRP2E[6]PLL:DRP2E[7]
52 ----------------------------PLL:DRP2E[8]PLL:DRP2E[9]
53 ----------------------------PLL:DRP2E[10]PLL:DRP2E[11]
54 ----------------------------PLL:DRP2E[12]PLL:DRP2E[13]
55 ----------------------------PLL:DRP2E[14]PLL:DRP2E[15]
56 ----------------------------PLL:DRP2F[0]PLL:DRP2F[1]
57 ----------------------------PLL:DRP2F[2]PLL:DRP2F[3]
58 ----------------------------PLL:DRP2F[4]PLL:DRP2F[5]
59 ----------------------------PLL:DRP2F[6]PLL:DRP2F[7]
60 ----------------------------PLL:DRP2F[8]PLL:DRP2F[9]
61 ----------------------------PLL:DRP2F[10]PLL:DRP2F[11]
62 ----------------------------PLL:DRP2F[12]PLL:DRP2F[13]
63 ----------------------------PLL:DRP2F[14]PLL:DRP2F[15]
CMT bittile 43
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP30[0]PLL:DRP30[1]
1 ----------------------------PLL:DRP30[2]PLL:DRP30[3]
2 ----------------------------PLL:DRP30[4]PLL:DRP30[5]
3 ----------------------------PLL:DRP30[6]PLL:DRP30[7]
4 ----------------------------PLL:DRP30[8]PLL:DRP30[9]
5 ----------------------------PLL:DRP30[10]PLL:DRP30[11]
6 ----------------------------PLL:DRP30[12]PLL:DRP30[13]
7 ----------------------------PLL:DRP30[14]PLL:DRP30[15]
8 ----------------------------PLL:DRP31[0]PLL:DRP31[1]
9 ----------------------------PLL:DRP31[2]PLL:DRP31[3]
10 ----------------------------PLL:DRP31[4]PLL:DRP31[5]
11 ----------------------------PLL:DRP31[6]PLL:DRP31[7]
12 ----------------------------PLL:DRP31[8]PLL:DRP31[9]
13 ----------------------------PLL:DRP31[10]PLL:DRP31[11]
14 ----------------------------PLL:DRP31[12]PLL:DRP31[13]
15 ----------------------------PLL:DRP31[14]PLL:DRP31[15]
16 ----------------------------PLL:DRP32[0]PLL:DRP32[1]
17 ----------------------------PLL:DRP32[2]PLL:DRP32[3]
18 ----------------------------PLL:DRP32[4]PLL:DRP32[5]
19 ----------------------------PLL:DRP32[6]PLL:DRP32[7]
20 ----------------------------PLL:DRP32[8]PLL:DRP32[9]
21 ----------------------------PLL:DRP32[10]PLL:DRP32[11]
22 ----------------------------PLL:DRP32[12]PLL:DRP32[13]
23 ----------------------------PLL:DRP32[14]PLL:DRP32[15]
24 ----------------------------PLL:DRP33[0]PLL:DRP33[1]
25 ----------------------------PLL:DRP33[2]PLL:DRP33[3]
26 ----------------------------PLL:DRP33[4]PLL:DRP33[5]
27 ----------------------------PLL:DRP33[6]PLL:DRP33[7]
28 ----------------------------PLL:DRP33[8]PLL:DRP33[9]
29 ----------------------------PLL:DRP33[10]PLL:DRP33[11]
30 ----------------------------PLL:DRP33[12]PLL:DRP33[13]
31 ----------------------------PLL:DRP33[14]PLL:DRP33[15]
32 ----------------------------PLL:DRP34[0]PLL:DRP34[1]
33 ----------------------------PLL:DRP34[2]PLL:DRP34[3]
34 ----------------------------PLL:DRP34[4]PLL:DRP34[5]
35 ----------------------------PLL:DRP34[6]PLL:DRP34[7]
36 ----------------------------PLL:DRP34[8]PLL:DRP34[9]
37 ----------------------------PLL:DRP34[10]PLL:DRP34[11]
38 ----------------------------PLL:DRP34[12]PLL:DRP34[13]
39 ----------------------------PLL:DRP34[14]PLL:DRP34[15]
40 ----------------------------PLL:DRP35[0]PLL:DRP35[1]
41 ----------------------------PLL:DRP35[2]PLL:DRP35[3]
42 ----------------------------PLL:DRP35[4]PLL:DRP35[5]
43 ----------------------------PLL:DRP35[6]PLL:DRP35[7]
44 ----------------------------PLL:DRP35[8]PLL:DRP35[9]
45 ----------------------------PLL:DRP35[10]PLL:DRP35[11]
46 ----------------------------PLL:DRP35[12]PLL:DRP35[13]
47 ----------------------------PLL:DRP35[14]PLL:DRP35[15]
48 ----------------------------PLL:DRP36[0]PLL:DRP36[1]
49 ----------------------------PLL:DRP36[2]PLL:DRP36[3]
50 ----------------------------PLL:DRP36[4]PLL:DRP36[5]
51 ----------------------------PLL:DRP36[6]PLL:DRP36[7]
52 ----------------------------PLL:DRP36[8]PLL:DRP36[9]
53 ----------------------------PLL:DRP36[10]PLL:DRP36[11]
54 ----------------------------PLL:DRP36[12]PLL:DRP36[13]
55 ----------------------------PLL:DRP36[14]PLL:DRP36[15]
56 ----------------------------PLL:DRP37[0]PLL:DRP37[1]
57 ----------------------------PLL:DRP37[2]PLL:DRP37[3]
58 ----------------------------PLL:DRP37[4]PLL:DRP37[5]
59 ----------------------------PLL:DRP37[6]PLL:DRP37[7]
60 ----------------------------PLL:DRP37[8]PLL:DRP37[9]
61 ----------------------------PLL:DRP37[10]PLL:DRP37[11]
62 ----------------------------PLL:DRP37[12]PLL:DRP37[13]
63 ----------------------------PLL:DRP37[14]PLL:DRP37[15]
CMT bittile 44
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP38[0]PLL:DRP38[1]
1 ----------------------------PLL:DRP38[2]PLL:DRP38[3]
2 ----------------------------PLL:DRP38[4]PLL:DRP38[5]
3 ----------------------------PLL:DRP38[6]PLL:DRP38[7]
4 ----------------------------PLL:DRP38[8]PLL:DRP38[9]
5 ----------------------------PLL:DRP38[10]PLL:DRP38[11]
6 ----------------------------PLL:DRP38[12]PLL:DRP38[13]
7 ----------------------------PLL:DRP38[14]PLL:DRP38[15]
8 ----------------------------PLL:DRP39[0]PLL:DRP39[1]
9 ----------------------------PLL:DRP39[2]PLL:DRP39[3]
10 ----------------------------PLL:DRP39[4]PLL:DRP39[5]
11 ----------------------------PLL:DRP39[6]PLL:DRP39[7]
12 ----------------------------PLL:DRP39[8]PLL:DRP39[9]
13 ----------------------------PLL:DRP39[10]PLL:DRP39[11]
14 ----------------------------PLL:DRP39[12]PLL:DRP39[13]
15 ----------------------------PLL:DRP39[14]PLL:DRP39[15]
16 ----------------------------PLL:DRP3A[0]PLL:DRP3A[1]
17 ----------------------------PLL:DRP3A[2]PLL:DRP3A[3]
18 ----------------------------PLL:DRP3A[4]PLL:DRP3A[5]
19 ----------------------------PLL:DRP3A[6]PLL:DRP3A[7]
20 ----------------------------PLL:DRP3A[8]PLL:DRP3A[9]
21 ----------------------------PLL:DRP3A[10]PLL:DRP3A[11]
22 ----------------------------PLL:DRP3A[12]PLL:DRP3A[13]
23 ----------------------------PLL:DRP3A[14]PLL:DRP3A[15]
24 ----------------------------PLL:DRP3B[0]PLL:DRP3B[1]
25 ----------------------------PLL:DRP3B[2]PLL:DRP3B[3]
26 ----------------------------PLL:DRP3B[4]PLL:DRP3B[5]
27 ----------------------------PLL:DRP3B[6]PLL:DRP3B[7]
28 ----------------------------PLL:DRP3B[8]PLL:DRP3B[9]
29 ----------------------------PLL:DRP3B[10]PLL:DRP3B[11]
30 ----------------------------PLL:DRP3B[12]PLL:DRP3B[13]
31 ----------------------------PLL:DRP3B[14]PLL:DRP3B[15]
32 ----------------------------PLL:DRP3C[0]PLL:DRP3C[1]
33 ----------------------------PLL:DRP3C[2]PLL:DRP3C[3]
34 ----------------------------PLL:DRP3C[4]PLL:DRP3C[5]
35 ----------------------------PLL:DRP3C[6]PLL:DRP3C[7]
36 ----------------------------PLL:DRP3C[8]PLL:DRP3C[9]
37 ----------------------------PLL:DRP3C[10]PLL:DRP3C[11]
38 ----------------------------PLL:DRP3C[12]PLL:DRP3C[13]
39 ----------------------------PLL:DRP3C[14]PLL:DRP3C[15]
40 ----------------------------PLL:DRP3D[0]PLL:DRP3D[1]
41 ----------------------------PLL:DRP3D[2]PLL:DRP3D[3]
42 ----------------------------PLL:DRP3D[4]PLL:DRP3D[5]
43 ----------------------------PLL:DRP3D[6]PLL:DRP3D[7]
44 ----------------------------PLL:DRP3D[8]PLL:DRP3D[9]
45 ----------------------------PLL:DRP3D[10]PLL:DRP3D[11]
46 ----------------------------PLL:DRP3D[12]PLL:DRP3D[13]
47 ----------------------------PLL:DRP3D[14]PLL:DRP3D[15]
48 ----------------------------PLL:DRP3E[0]PLL:DRP3E[1]
49 ----------------------------PLL:DRP3E[2]PLL:DRP3E[3]
50 ----------------------------PLL:DRP3E[4]PLL:DRP3E[5]
51 ----------------------------PLL:DRP3E[6]PLL:DRP3E[7]
52 ----------------------------PLL:DRP3E[8]PLL:DRP3E[9]
53 ----------------------------PLL:DRP3E[10]PLL:DRP3E[11]
54 ----------------------------PLL:DRP3E[12]PLL:DRP3E[13]
55 ----------------------------PLL:DRP3E[14]PLL:DRP3E[15]
56 ----------------------------PLL:DRP3F[0]PLL:DRP3F[1]
57 ----------------------------PLL:DRP3F[2]PLL:DRP3F[3]
58 ----------------------------PLL:DRP3F[4]PLL:DRP3F[5]
59 ----------------------------PLL:DRP3F[6]PLL:DRP3F[7]
60 ----------------------------PLL:DRP3F[8]PLL:DRP3F[9]
61 ----------------------------PLL:DRP3F[10]PLL:DRP3F[11]
62 ----------------------------PLL:DRP3F[12]PLL:DRP3F[13]
63 ----------------------------PLL:DRP3F[14]PLL:DRP3F[15]
CMT bittile 45
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP40[0]PLL:DRP40[1]
1 ----------------------------PLL:DRP40[2]PLL:DRP40[3]
2 ----------------------------PLL:DRP40[4]PLL:DRP40[5]
3 ----------------------------PLL:DRP40[6]PLL:DRP40[7]
4 ----------------------------PLL:DRP40[8]PLL:DRP40[9]
5 ----------------------------PLL:DRP40[10]PLL:DRP40[11]
6 ----------------------------PLL:DRP40[12]PLL:DRP40[13]
7 ----------------------------PLL:DRP40[14]PLL:DRP40[15]
8 ----------------------------PLL:DRP41[0]PLL:DRP41[1]
9 ----------------------------PLL:DRP41[2]PLL:DRP41[3]
10 ----------------------------PLL:DRP41[4]PLL:DRP41[5]
11 ----------------------------PLL:DRP41[6]PLL:DRP41[7]
12 ----------------------------PLL:DRP41[8]PLL:DRP41[9]
13 ----------------------------PLL:DRP41[10]PLL:DRP41[11]
14 ----------------------------PLL:DRP41[12]PLL:DRP41[13]
15 ----------------------------PLL:DRP41[14]PLL:DRP41[15]
16 ----------------------------PLL:DRP42[0]
PLL:MAN_LF[0]		PLL:DRP42[1]
17 ----------------------------PLL:DRP42[2]PLL:DRP42[3]
PLL:MAN_LF[1]
18 ----------------------------PLL:DRP42[4]
PLL:MAN_LF[2]		PLL:DRP42[5]
19 ----------------------------PLL:DRP42[6]PLL:DRP42[7]
PLL:VLF_HIGH_DIS_B
20 ----------------------------PLL:DRP42[8]
PLL:LF_PEN[0]		PLL:DRP42[9]
21 ----------------------------PLL:DRP42[10]PLL:DRP42[11]
PLL:LF_PEN[1]
22 ----------------------------PLL:DRP42[12]
PLL:LF_NEN[0]		PLL:DRP42[13]
23 ----------------------------PLL:DRP42[14]PLL:DRP42[15]
PLL:LF_NEN[1]
24 ----------------------------PLL:DRP43[0]
PLL:LF_LOW_SEL		PLL:DRP43[1]
25 ----------------------------PLL:DRP43[2]PLL:DRP43[3]
26 ----------------------------PLL:DRP43[4]PLL:DRP43[5]
27 ----------------------------PLL:DRP43[6]PLL:DRP43[7]
28 ----------------------------PLL:DRP43[8]PLL:DRP43[9]
29 ----------------------------PLL:DRP43[10]PLL:DRP43[11]
30 ----------------------------PLL:DRP43[12]PLL:DRP43[13]
31 ----------------------------PLL:DRP43[14]PLL:DRP43[15]
32 ----------------------------PLL:DRP44[0]
PLL:SPARE_ANALOG[0]		PLL:DRP44[1]
33 ----------------------------PLL:DRP44[2]PLL:DRP44[3]
PLL:SPARE_ANALOG[1]
34 ----------------------------PLL:DRP44[4]
PLL:SPARE_ANALOG[2]		PLL:DRP44[5]
35 ----------------------------PLL:DRP44[6]PLL:DRP44[7]
PLL:SPARE_ANALOG[3]
36 ----------------------------PLL:DRP44[8]
PLL:SPARE_ANALOG[4]		PLL:DRP44[9]
37 ----------------------------PLL:DRP44[10]PLL:DRP44[11]
38 ----------------------------PLL:DRP44[12]PLL:DRP44[13]
39 ----------------------------PLL:DRP44[14]PLL:DRP44[15]
40 ----------------------------PLL:DRP45[0]PLL:DRP45[1]
41 ----------------------------PLL:DRP45[2]PLL:DRP45[3]
42 ----------------------------PLL:DRP45[4]PLL:DRP45[5]
43 ----------------------------PLL:DRP45[6]PLL:DRP45[7]
44 ----------------------------PLL:DRP45[8]PLL:DRP45[9]
45 ----------------------------PLL:DRP45[10]PLL:DRP45[11]
PLL:VREF_START[0]
46 ----------------------------PLL:DRP45[12]
PLL:VREF_START[1]		PLL:DRP45[13]
47 ----------------------------PLL:DRP45[14]PLL:DRP45[15]
48 ----------------------------PLL:DRP46[0]
PLL:VLF_HIGH_PWDN_B		PLL:DRP46[1]
49 ----------------------------PLL:DRP46[2]PLL:DRP46[3]
50 ----------------------------PLL:DRP46[4]PLL:DRP46[5]
51 ----------------------------PLL:DRP46[6]PLL:DRP46[7]
52 ----------------------------PLL:DRP46[8]PLL:DRP46[9]
53 ----------------------------PLL:DRP46[10]PLL:DRP46[11]
54 ----------------------------PLL:DRP46[12]PLL:DRP46[13]
55 ----------------------------PLL:DRP46[14]PLL:DRP46[15]
56 ----------------------------PLL:DRP47[0]PLL:DRP47[1]
57 ----------------------------PLL:DRP47[2]PLL:DRP47[3]
58 ----------------------------PLL:DRP47[4]PLL:DRP47[5]
59 ----------------------------PLL:DRP47[6]PLL:DRP47[7]
60 ----------------------------PLL:DRP47[8]PLL:DRP47[9]
61 ----------------------------PLL:DRP47[10]PLL:DRP47[11]
62 ----------------------------PLL:DRP47[12]PLL:DRP47[13]
63 ----------------------------PLL:DRP47[14]PLL:DRP47[15]
CMT bittile 46
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP48[0]PLL:DRP48[1]
1 ----------------------------PLL:DRP48[2]PLL:DRP48[3]
2 ----------------------------PLL:DRP48[4]PLL:DRP48[5]
3 ----------------------------PLL:DRP48[6]PLL:DRP48[7]
4 ----------------------------PLL:DRP48[8]PLL:DRP48[9]
5 ----------------------------PLL:DRP48[10]PLL:DRP48[11]
6 ----------------------------PLL:DRP48[12]PLL:DRP48[13]
7 ----------------------------PLL:DRP48[14]PLL:DRP48[15]
8 ----------------------------PLL:DRP49[0]PLL:DRP49[1]
9 ----------------------------PLL:DRP49[2]PLL:DRP49[3]
10 ----------------------------PLL:DRP49[4]PLL:DRP49[5]
11 ----------------------------PLL:DRP49[6]PLL:DRP49[7]
12 ----------------------------PLL:DRP49[8]PLL:DRP49[9]
13 ----------------------------PLL:DRP49[10]
PLL:SEL_HV_NMOS		PLL:DRP49[11]
PLL:MVDD_SEL[0]
14 ----------------------------PLL:DRP49[12]
PLL:MVDD_SEL[1]		PLL:DRP49[13]
PLL:EN_CURR_SINK[0]
15 ----------------------------PLL:DRP49[14]
PLL:EN_CURR_SINK[1]		PLL:DRP49[15]
PLL:SUP_SEL_AREG
16 ----------------------------PLL:AVDD_VBG_SEL[0]
PLL:DRP4A[0]		PLL:AVDD_VBG_SEL[1]
PLL:DRP4A[1]
17 ----------------------------PLL:AVDD_VBG_SEL[2]
PLL:DRP4A[2]		PLL:AVDD_VBG_SEL[3]
PLL:DRP4A[3]
18 ----------------------------PLL:AVDD_VBG_PD[0]
PLL:DRP4A[4]		PLL:AVDD_VBG_PD[1]
PLL:DRP4A[5]
19 ----------------------------PLL:AVDD_VBG_PD[2]
PLL:DRP4A[6]		PLL:AVDD_COMP_SET[0]
PLL:DRP4A[7]
20 ----------------------------PLL:AVDD_COMP_SET[1]
PLL:DRP4A[8]		PLL:AVDD_COMP_SET[2]
PLL:DRP4A[9]
21 ----------------------------PLL:DRP4A[10]PLL:DRP4A[11]
22 ----------------------------PLL:DRP4A[12]PLL:DRP4A[13]
23 ----------------------------PLL:DRP4A[14]PLL:DRP4A[15]
24 ----------------------------PLL:DRP4B[0]PLL:DRP4B[1]
25 ----------------------------PLL:DRP4B[2]PLL:DRP4B[3]
26 ----------------------------PLL:DRP4B[4]PLL:DRP4B[5]
27 ----------------------------PLL:DRP4B[6]PLL:DRP4B[7]
28 ----------------------------PLL:DRP4B[8]PLL:DRP4B[9]
29 ----------------------------PLL:DRP4B[10]PLL:DRP4B[11]
30 ----------------------------PLL:DRP4B[12]PLL:DRP4B[13]
31 ----------------------------PLL:DRP4B[14]PLL:DRP4B[15]
32 ----------------------------PLL:DRP4C[0]
PLL:HVLF_CNT_TEST[0]		PLL:DRP4C[1]
33 ----------------------------PLL:DRP4C[2]PLL:DRP4C[3]
PLL:HVLF_CNT_TEST[1]
34 ----------------------------PLL:DRP4C[4]
PLL:HVLF_CNT_TEST[2]		PLL:DRP4C[5]
35 ----------------------------PLL:DRP4C[6]PLL:DRP4C[7]
PLL:HVLF_CNT_TEST[3]
36 ----------------------------PLL:DRP4C[8]
PLL:HVLF_CNT_TEST[4]		PLL:DRP4C[9]
37 ----------------------------PLL:DRP4C[10]PLL:DRP4C[11]
PLL:HVLF_CNT_TEST[5]
38 ----------------------------PLL:DRP4C[12]
PLL:HVLF_CNT_TEST_EN		PLL:DRP4C[13]
39 ----------------------------PLL:DRP4C[14]PLL:DRP4C[15]
40 ----------------------------PLL:DRP4D[0]PLL:DRP4D[1]
41 ----------------------------PLL:DRP4D[2]PLL:DRP4D[3]
42 ----------------------------PLL:DRP4D[4]PLL:DRP4D[5]
43 ----------------------------PLL:DRP4D[6]PLL:DRP4D[7]
44 ----------------------------PLL:DRP4D[8]PLL:DRP4D[9]
45 ----------------------------PLL:DRP4D[10]PLL:DRP4D[11]
46 ----------------------------PLL:DRP4D[12]PLL:DRP4D[13]
47 ----------------------------PLL:DRP4D[14]PLL:DRP4D[15]
48 ----------------------------PLL:DRP4E[0]PLL:DRP4E[1]
49 ----------------------------PLL:DRP4E[2]PLL:CP_RES[0]
PLL:DRP4E[3]
50 ----------------------------PLL:CP_RES[1]
PLL:DRP4E[4]		PLL:DRP4E[5]
51 ----------------------------PLL:DRP4E[6]PLL:CP_BIAS_TRIP_SET
PLL:DRP4E[7]
52 ----------------------------PLL:CP[0]
PLL:DRP4E[8]		PLL:DRP4E[9]
53 ----------------------------PLL:DRP4E[10]PLL:CP[1]
PLL:DRP4E[11]
54 ----------------------------PLL:CP[2]
PLL:DRP4E[12]		PLL:DRP4E[13]
55 ----------------------------PLL:DRP4E[14]PLL:CP[3]
PLL:DRP4E[15]
56 ----------------------------PLL:DRP4F[0]PLL:DRP4F[1]
57 ----------------------------PLL:DRP4F[2]PLL:DRP4F[3]
58 ----------------------------PLL:DRP4F[4]
PLL:LFHF[0]		PLL:DRP4F[5]
59 ----------------------------PLL:DRP4F[6]PLL:DRP4F[7]
PLL:LFHF[1]
60 ----------------------------PLL:DRP4F[8]
PLL:RES[0]		PLL:DRP4F[9]
61 ----------------------------PLL:DRP4F[10]PLL:DRP4F[11]
PLL:RES[1]
62 ----------------------------PLL:DRP4F[12]
PLL:RES[2]		PLL:DRP4F[13]
63 ----------------------------PLL:DRP4F[14]PLL:DRP4F[15]
PLL:RES[3]
CMT bittile 47
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP50[0]PLL:DRP50[1]
1 ----------------------------PLL:DRP50[2]PLL:DRP50[3]
2 ----------------------------PLL:DRP50[4]PLL:DRP50[5]
3 ----------------------------PLL:DRP50[6]PLL:DRP50[7]
4 ----------------------------PLL:DRP50[8]PLL:DRP50[9]
5 ----------------------------PLL:DRP50[10]PLL:DRP50[11]
6 ----------------------------PLL:DRP50[12]PLL:DRP50[13]
7 ----------------------------PLL:DRP50[14]PLL:DRP50[15]
8 ----------------------------PLL:DRP51[0]PLL:DRP51[1]
9 ----------------------------PLL:DRP51[2]PLL:DRP51[3]
10 ----------------------------PLL:DRP51[4]PLL:DRP51[5]
11 ----------------------------PLL:DRP51[6]PLL:DRP51[7]
12 ----------------------------PLL:DRP51[8]PLL:DRP51[9]
13 ----------------------------PLL:DRP51[10]PLL:DRP51[11]
14 ----------------------------PLL:DRP51[12]PLL:DRP51[13]
15 ----------------------------PLL:DRP51[14]PLL:DRP51[15]
16 ----------------------------PLL:DRP52[0]PLL:DRP52[1]
17 ----------------------------PLL:DRP52[2]PLL:DRP52[3]
18 ----------------------------PLL:DRP52[4]PLL:DRP52[5]
19 ----------------------------PLL:DRP52[6]PLL:DRP52[7]
20 ----------------------------PLL:DRP52[8]PLL:DRP52[9]
21 ----------------------------PLL:DRP52[10]PLL:DRP52[11]
22 ----------------------------PLL:DRP52[12]PLL:DRP52[13]
23 ----------------------------PLL:DRP52[14]PLL:DRP52[15]
24 ----------------------------PLL:DRP53[0]PLL:DRP53[1]
25 ----------------------------PLL:DRP53[2]PLL:DRP53[3]
26 ----------------------------PLL:DRP53[4]PLL:DRP53[5]
27 ----------------------------PLL:DRP53[6]PLL:DRP53[7]
28 ----------------------------PLL:DRP53[8]PLL:DRP53[9]
29 ----------------------------PLL:DRP53[10]PLL:DRP53[11]
30 ----------------------------PLL:DRP53[12]PLL:DRP53[13]
31 ----------------------------PLL:DRP53[14]PLL:DRP53[15]
32 ----------------------------PLL:DRP54[0]PLL:DRP54[1]
33 ----------------------------PLL:DRP54[2]PLL:DRP54[3]
34 ----------------------------PLL:DRP54[4]PLL:DRP54[5]
35 ----------------------------PLL:DRP54[6]PLL:DRP54[7]
36 ----------------------------PLL:DRP54[8]PLL:DRP54[9]
37 ----------------------------PLL:DRP54[10]PLL:DRP54[11]
38 ----------------------------PLL:DRP54[12]PLL:DRP54[13]
39 ----------------------------PLL:DRP54[14]PLL:DRP54[15]
40 ----------------------------PLL:DRP55[0]PLL:DRP55[1]
41 ----------------------------PLL:DRP55[2]PLL:DRP55[3]
42 ----------------------------PLL:DRP55[4]PLL:DRP55[5]
43 ----------------------------PLL:DRP55[6]PLL:DRP55[7]
44 ----------------------------PLL:DRP55[8]PLL:DRP55[9]
45 ----------------------------PLL:DRP55[10]PLL:DRP55[11]
46 ----------------------------PLL:DRP55[12]PLL:DRP55[13]
47 ----------------------------PLL:DRP55[14]PLL:DRP55[15]
48 ----------------------------PLL:DRP56[0]PLL:DRP56[1]
49 ----------------------------PLL:DRP56[2]PLL:DRP56[3]
50 ----------------------------PLL:DRP56[4]PLL:DRP56[5]
51 ----------------------------PLL:DRP56[6]PLL:DRP56[7]
52 ----------------------------PLL:DRP56[8]PLL:DRP56[9]
53 ----------------------------PLL:DRP56[10]PLL:DRP56[11]
54 ----------------------------PLL:DRP56[12]PLL:DRP56[13]
55 ----------------------------PLL:DRP56[14]PLL:DRP56[15]
56 ----------------------------PLL:DRP57[0]PLL:DRP57[1]
57 ----------------------------PLL:DRP57[2]PLL:DRP57[3]
58 ----------------------------PLL:DRP57[4]PLL:DRP57[5]
59 ----------------------------PLL:DRP57[6]PLL:DRP57[7]
60 ----------------------------PLL:DRP57[8]PLL:DRP57[9]
61 ----------------------------PLL:DRP57[10]PLL:DRP57[11]
62 ----------------------------PLL:DRP57[12]PLL:DRP57[13]
63 ----------------------------PLL:DRP57[14]PLL:DRP57[15]
CMT bittile 48
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:DRP58[0]PLL:DRP58[1]
1 ----------------------------PLL:DRP58[2]PLL:DRP58[3]
2 ----------------------------PLL:DRP58[4]PLL:DRP58[5]
3 ----------------------------PLL:DRP58[6]PLL:DRP58[7]
4 ----------------------------PLL:DRP58[8]PLL:DRP58[9]
5 ----------------------------PLL:DRP58[10]PLL:DRP58[11]
6 ----------------------------PLL:DRP58[12]PLL:DRP58[13]
7 ----------------------------PLL:DRP58[14]PLL:DRP58[15]
8 ----------------------------PLL:DRP59[0]PLL:DRP59[1]
9 ----------------------------PLL:DRP59[2]PLL:DRP59[3]
10 ----------------------------PLL:DRP59[4]PLL:DRP59[5]
11 ----------------------------PLL:DRP59[6]PLL:DRP59[7]
12 ----------------------------PLL:DRP59[8]PLL:DRP59[9]
13 ----------------------------PLL:DRP59[10]PLL:DRP59[11]
14 ----------------------------PLL:DRP59[12]PLL:DRP59[13]
15 ----------------------------PLL:DRP59[14]PLL:DRP59[15]
16 ----------------------------PLL:DRP5A[0]
PLL:INV.RST		PLL:DRP5A[1]
PLL:INV.PWRDWN
17 ----------------------------PLL:DRP5A[2]PLL:DRP5A[3]
18 ----------------------------PLL:DRP5A[4]
PLL:INV.CLKINSEL		PLL:DRP5A[5]
19 ----------------------------PLL:DRP5A[6]PLL:DRP5A[7]
20 ----------------------------PLL:DRP5A[8]PLL:DRP5A[9]
21 ----------------------------PLL:DRP5A[10]PLL:DRP5A[11]
22 ----------------------------PLL:DRP5A[12]PLL:DRP5A[13]
23 ----------------------------PLL:DRP5A[14]PLL:DRP5A[15]
24 ----------------------------PLL:DRP5B[0]PLL:DRP5B[1]
25 ----------------------------PLL:DRP5B[2]PLL:DRP5B[3]
26 ----------------------------PLL:DRP5B[4]PLL:DRP5B[5]
27 ----------------------------PLL:DRP5B[6]PLL:DRP5B[7]
28 ----------------------------PLL:DRP5B[8]PLL:DRP5B[9]
29 ----------------------------PLL:DRP5B[10]PLL:DRP5B[11]
30 ----------------------------PLL:DRP5B[12]PLL:DRP5B[13]
31 ----------------------------PLL:DRP5B[14]PLL:DRP5B[15]
32 ----------------------------PLL:DRP5C[0]
PLL:PLL_EN		PLL:DRP5C[1]
33 ----------------------------PLL:DRP5C[2]
PLL:STARTUP_WAIT		PLL:DRP5C[3]
PLL:GTS_WAIT
34 ----------------------------PLL:DRP5C[4]PLL:DRP5C[5]
35 ----------------------------PLL:DRP5C[6]PLL:DRP5C[7]
36 ----------------------------PLL:DRP5C[8]PLL:DRP5C[9]
37 ----------------------------PLL:DRP5C[10]PLL:DRP5C[11]
38 ----------------------------PLL:DRP5C[12]PLL:DRP5C[13]
39 ----------------------------PLL:DRP5C[14]PLL:DRP5C[15]
40 ----------------------------PLL:DRP5D[0]PLL:DRP5D[1]
41 ----------------------------PLL:DRP5D[2]PLL:DRP5D[3]
42 ----------------------------PLL:DRP5D[4]PLL:DRP5D[5]
43 ----------------------------PLL:DRP5D[6]PLL:DRP5D[7]
44 ----------------------------PLL:DRP5D[8]PLL:DRP5D[9]
45 ----------------------------PLL:DRP5D[10]PLL:DRP5D[11]
46 ----------------------------PLL:DRP5D[12]PLL:DRP5D[13]
47 ----------------------------PLL:DRP5D[14]PLL:DRP5D[15]
48 ----------------------------PLL:CONTROL_0[0]
PLL:DRP5E[0]		PLL:CONTROL_0[1]
PLL:DRP5E[1]
49 ----------------------------PLL:CONTROL_0[2]
PLL:DRP5E[2]		PLL:CONTROL_0[3]
PLL:DRP5E[3]
50 ----------------------------PLL:CONTROL_0[4]
PLL:DRP5E[4]		PLL:CONTROL_0[5]
PLL:DRP5E[5]
51 ----------------------------PLL:CONTROL_0[6]
PLL:DRP5E[6]		PLL:CONTROL_0[7]
PLL:DRP5E[7]
52 ----------------------------PLL:CONTROL_0[8]
PLL:DRP5E[8]		PLL:CONTROL_0[9]
PLL:DRP5E[9]
53 ----------------------------PLL:CONTROL_0[10]
PLL:DRP5E[10]		PLL:CONTROL_0[11]
PLL:DRP5E[11]
54 ----------------------------PLL:CONTROL_0[12]
PLL:DRP5E[12]		PLL:CONTROL_0[13]
PLL:DRP5E[13]
55 ----------------------------PLL:CONTROL_0[14]
PLL:DRP5E[14]		PLL:CONTROL_0[15]
PLL:DRP5E[15]
56 ----------------------------PLL:CONTROL_1[0]
PLL:DRP5F[0]		PLL:CONTROL_1[1]
PLL:DRP5F[1]
57 ----------------------------PLL:CONTROL_1[2]
PLL:DRP5F[2]		PLL:CONTROL_1[3]
PLL:DRP5F[3]
58 ----------------------------PLL:CONTROL_1[4]
PLL:DRP5F[4]		PLL:CONTROL_1[5]
PLL:DRP5F[5]
59 ----------------------------PLL:CONTROL_1[6]
PLL:DRP5F[6]		PLL:CONTROL_1[7]
PLL:DRP5F[7]
60 ----------------------------PLL:CONTROL_1[8]
PLL:DRP5F[8]		PLL:CONTROL_1[9]
PLL:DRP5F[9]
61 ----------------------------PLL:CONTROL_1[10]
PLL:DRP5F[10]		PLL:CONTROL_1[11]
PLL:DRP5F[11]
62 ----------------------------PLL:CONTROL_1[12]
PLL:DRP5F[12]		PLL:CONTROL_1[13]
PLL:DRP5F[13]
63 ----------------------------PLL:CONTROL_1[14]
PLL:DRP5F[14]		PLL:CONTROL_1[15]
PLL:DRP5F[15]
CMT bittile 49
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PLL:CONTROL_2[0]
PLL:DRP60[0]		PLL:CONTROL_2[1]
PLL:DRP60[1]
1 ----------------------------PLL:CONTROL_2[2]
PLL:DRP60[2]		PLL:CONTROL_2[3]
PLL:DRP60[3]
2 ----------------------------PLL:CONTROL_2[4]
PLL:DRP60[4]		PLL:CONTROL_2[5]
PLL:DRP60[5]
3 ----------------------------PLL:CONTROL_2[6]
PLL:DRP60[6]		PLL:CONTROL_2[7]
PLL:DRP60[7]
4 ----------------------------PLL:CONTROL_2[8]
PLL:DRP60[8]		PLL:CONTROL_2[9]
PLL:DRP60[9]
5 ----------------------------PLL:CONTROL_2[10]
PLL:DRP60[10]		PLL:CONTROL_2[11]
PLL:DRP60[11]
6 ----------------------------PLL:CONTROL_2[12]
PLL:DRP60[12]		PLL:CONTROL_2[13]
PLL:DRP60[13]
7 ----------------------------PLL:CONTROL_2[14]
PLL:DRP60[14]		PLL:CONTROL_2[15]
PLL:DRP60[15]
8 ----------------------------PLL:CONTROL_3[0]
PLL:DRP61[0]		PLL:CONTROL_3[1]
PLL:DRP61[1]
9 ----------------------------PLL:CONTROL_3[2]
PLL:DRP61[2]		PLL:CONTROL_3[3]
PLL:DRP61[3]
10 ----------------------------PLL:CONTROL_3[4]
PLL:DRP61[4]		PLL:CONTROL_3[5]
PLL:DRP61[5]
11 ----------------------------PLL:CONTROL_3[6]
PLL:DRP61[6]		PLL:CONTROL_3[7]
PLL:DRP61[7]
12 ----------------------------PLL:CONTROL_3[8]
PLL:DRP61[8]		PLL:CONTROL_3[9]
PLL:DRP61[9]
13 ----------------------------PLL:CONTROL_3[10]
PLL:DRP61[10]		PLL:CONTROL_3[11]
PLL:DRP61[11]
14 ----------------------------PLL:CONTROL_3[12]
PLL:DRP61[12]		PLL:CONTROL_3[13]
PLL:DRP61[13]
15 ----------------------------PLL:CONTROL_3[14]
PLL:DRP61[14]		PLL:CONTROL_3[15]
PLL:DRP61[15]
16 ----------------------------PLL:CONTROL_4[0]
PLL:DRP62[0]		PLL:CONTROL_4[1]
PLL:DRP62[1]
17 ----------------------------PLL:CONTROL_4[2]
PLL:DRP62[2]		PLL:CONTROL_4[3]
PLL:DRP62[3]
18 ----------------------------PLL:CONTROL_4[4]
PLL:DRP62[4]		PLL:CONTROL_4[5]
PLL:DRP62[5]
19 ----------------------------PLL:CONTROL_4[6]
PLL:DRP62[6]		PLL:CONTROL_4[7]
PLL:DRP62[7]
20 ----------------------------PLL:CONTROL_4[8]
PLL:DRP62[8]		PLL:CONTROL_4[9]
PLL:DRP62[9]
21 ----------------------------PLL:CONTROL_4[10]
PLL:DRP62[10]		PLL:CONTROL_4[11]
PLL:DRP62[11]
22 ----------------------------PLL:CONTROL_4[12]
PLL:DRP62[12]		PLL:CONTROL_4[13]
PLL:DRP62[13]
23 ----------------------------PLL:CONTROL_4[14]
PLL:DRP62[14]		PLL:CONTROL_4[15]
PLL:DRP62[15]
24 ----------------------------PLL:CONTROL_5[0]
PLL:DRP63[0]		PLL:CONTROL_5[1]
PLL:DRP63[1]
25 ----------------------------PLL:CONTROL_5[2]
PLL:DRP63[2]		PLL:CONTROL_5[3]
PLL:DRP63[3]
26 ----------------------------PLL:CONTROL_5[4]
PLL:DRP63[4]		PLL:CONTROL_5[5]
PLL:DRP63[5]
27 ----------------------------PLL:CONTROL_5[6]
PLL:DRP63[6]		PLL:CONTROL_5[7]
PLL:DRP63[7]
28 ----------------------------PLL:CONTROL_5[8]
PLL:DRP63[8]		PLL:CONTROL_5[9]
PLL:DRP63[9]
29 ----------------------------PLL:CONTROL_5[10]
PLL:DRP63[10]		PLL:CONTROL_5[11]
PLL:DRP63[11]
30 ----------------------------PLL:CONTROL_5[12]
PLL:DRP63[12]		PLL:CONTROL_5[13]
PLL:DRP63[13]
31 ----------------------------PLL:CONTROL_5[14]
PLL:DRP63[14]		PLL:CONTROL_5[15]
PLL:DRP63[15]
32 ----------------------------PLL:CONTROL_6[0]
PLL:DRP64[0]		PLL:CONTROL_6[1]
PLL:DRP64[1]
33 ----------------------------PLL:CONTROL_6[2]
PLL:DRP64[2]		PLL:CONTROL_6[3]
PLL:DRP64[3]
34 ----------------------------PLL:CONTROL_6[4]
PLL:DRP64[4]		PLL:CONTROL_6[5]
PLL:DRP64[5]
35 ----------------------------PLL:CONTROL_6[6]
PLL:DRP64[6]		PLL:CONTROL_6[7]
PLL:DRP64[7]
36 ----------------------------PLL:CONTROL_6[8]
PLL:DRP64[8]		PLL:CONTROL_6[9]
PLL:DRP64[9]
37 ----------------------------PLL:CONTROL_6[10]
PLL:DRP64[10]		PLL:CONTROL_6[11]
PLL:DRP64[11]
38 ----------------------------PLL:CONTROL_6[12]
PLL:DRP64[12]		PLL:CONTROL_6[13]
PLL:DRP64[13]
39 ----------------------------PLL:CONTROL_6[14]
PLL:DRP64[14]		PLL:CONTROL_6[15]
PLL:DRP64[15]
40 ----------------------------PLL:CONTROL_7[0]
PLL:DRP65[0]		PLL:CONTROL_7[1]
PLL:DRP65[1]
41 ----------------------------PLL:CONTROL_7[2]
PLL:DRP65[2]		PLL:CONTROL_7[3]
PLL:DRP65[3]
42 ----------------------------PLL:CONTROL_7[4]
PLL:DRP65[4]		PLL:CONTROL_7[5]
PLL:DRP65[5]
43 ----------------------------PLL:CONTROL_7[6]
PLL:DRP65[6]		PLL:CONTROL_7[7]
PLL:DRP65[7]
44 ----------------------------PLL:CONTROL_7[8]
PLL:DRP65[8]		PLL:CONTROL_7[9]
PLL:DRP65[9]
45 ----------------------------PLL:CONTROL_7[10]
PLL:DRP65[10]		PLL:CONTROL_7[11]
PLL:DRP65[11]
46 ----------------------------PLL:CONTROL_7[12]
PLL:DRP65[12]		PLL:CONTROL_7[13]
PLL:DRP65[13]
47 ----------------------------PLL:CONTROL_7[14]
PLL:DRP65[14]		PLL:CONTROL_7[15]
PLL:DRP65[15]
48 ----------------------------PLL:DRP66[0]PLL:DRP66[1]
49 ----------------------------PLL:DRP66[2]PLL:DRP66[3]
50 ----------------------------PLL:DRP66[4]PLL:DRP66[5]
51 ----------------------------PLL:DRP66[6]PLL:DRP66[7]
52 ----------------------------PLL:DRP66[8]PLL:DRP66[9]
53 ----------------------------PLL:DRP66[10]PLL:DRP66[11]
54 ----------------------------PLL:DRP66[12]PLL:DRP66[13]
55 ----------------------------PLL:DRP66[14]PLL:DRP66[15]
56 ----------------------------PLL:DRP67[0]PLL:DRP67[1]
57 ----------------------------PLL:DRP67[2]PLL:DRP67[3]
58 ----------------------------PLL:DRP67[4]PLL:DRP67[5]
59 ----------------------------PLL:DRP67[6]PLL:DRP67[7]
60 ----------------------------PLL:DRP67[8]PLL:DRP67[9]
61 ----------------------------PLL:DRP67[10]PLL:DRP67[11]
62 ----------------------------PLL:DRP67[12]PLL:DRP67[13]
63 ----------------------------PLL:DRP67[14]PLL:DRP67[15]
CMT bittile 50
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 --------------------------HCLK_CMT:ENABLE.CKINT0HCLK_CMT:ENABLE.CKINT1HCLK_CMT:ENABLE.RCLK0HCLK_CMT:ENABLE.RCLK1
15 --------------------------HCLK_CMT:ENABLE.CKINT2HCLK_CMT:ENABLE.CKINT3HCLK_CMT:ENABLE.RCLK2HCLK_CMT:ENABLE.RCLK3
16 --------------------------HCLK_CMT:MUX.PERF0[0]HCLK_CMT:MUX.PERF1[0]HCLK_CMT:MUX.PERF2[0]HCLK_CMT:MUX.PERF3[0]
17 --------------------------HCLK_CMT:MUX.PERF0[1]HCLK_CMT:MUX.PERF1[1]HCLK_CMT:MUX.PERF2[1]HCLK_CMT:MUX.PERF3[1]
18 --------------------------HCLK_CMT:MUX.PERF0[2]HCLK_CMT:MUX.PERF1[2]HCLK_CMT:MUX.PERF2[2]HCLK_CMT:MUX.PERF3[2]
19 --------------------------HCLK_CMT:MUX.PERF1[3]HCLK_CMT:MUX.PERF0[3]HCLK_CMT:MUX.PERF3[3]HCLK_CMT:MUX.PERF2[3]
20 --------------------------HCLK_CMT:MUX.PERF0[4]HCLK_CMT:MUX.PERF1[4]HCLK_CMT:MUX.PERF2[4]HCLK_CMT:MUX.PERF3[4]
21 --------------------------HCLK_CMT:ENABLE.HCLK9HCLK_CMT:ENABLE.HCLK8HCLK_CMT:ENABLE.HIN4HCLK_CMT:ENABLE.HIN5
22 --------------------------HCLK_CMT:ENABLE.HCLK7HCLK_CMT:ENABLE.HCLK6HCLK_CMT:ENABLE.HIN6HCLK_CMT:ENABLE.HIN7
23 --------------------------HCLK_CMT:ENABLE.HCLK5HCLK_CMT:ENABLE.HCLK4HCLK_CMT:ENABLE.HIN8HCLK_CMT:ENABLE.HIN9
24 --------------------------HCLK_CMT:ENABLE.HCLK3HCLK_CMT:ENABLE.HCLK2HCLK_CMT:ENABLE.HIN10HCLK_CMT:ENABLE.HIN11
25 --------------------------HCLK_CMT:ENABLE.HCLK1HCLK_CMT:ENABLE.HCLK0HCLK_CMT:ENABLE.HIN12HCLK_CMT:ENABLE.HIN13
26 --------------------------BUFMRCE1:MUX.I[0]BUFMRCE1:MUX.I[1]HCLK_CMT:ENABLE.HCLK10HCLK_CMT:ENABLE.HCLK11
27 --------------------------BUFMRCE1:MUX.I[2]BUFMRCE1:MUX.I[7]BUFMRCE0:ENABLEBUFMRCE1:ENABLE
28 --------------------------BUFMRCE0:MUX.I[2]BUFMRCE0:MUX.I[7]~BUFMRCE0:INV.CE~BUFMRCE1:INV.CE
29 --------------------------BUFMRCE1:MUX.I[6]BUFMRCE1:MUX.I[8]BUFMRCE0:INIT_OUTBUFMRCE1:INIT_OUT
30 --------------------------BUFMRCE1:MUX.I[9]BUFMRCE0:MUX.I[6]--
31 --------------------------BUFMRCE0:MUX.I[8]BUFMRCE0:MUX.I[9]BUFMRCE0:CE_TYPEBUFMRCE1:CE_TYPE
MMCM:CONTROL_0[1, 28, 8][1, 29, 8][1, 28, 9][1, 29, 9][1, 28, 10][1, 29, 10][1, 28, 11][1, 29, 11][1, 28, 12][1, 29, 12][1, 28, 13][1, 29, 13][1, 28, 14][1, 29, 14][1, 28, 15][1, 29, 15]
MMCM:CONTROL_1[1, 28, 0][1, 29, 0][1, 28, 1][1, 29, 1][1, 28, 2][1, 29, 2][1, 28, 3][1, 29, 3][1, 28, 4][1, 29, 4][1, 28, 5][1, 29, 5][1, 28, 6][1, 29, 6][1, 28, 7][1, 29, 7]
MMCM:CONTROL_2[0, 28, 56][0, 29, 56][0, 28, 57][0, 29, 57][0, 28, 58][0, 29, 58][0, 28, 59][0, 29, 59][0, 28, 60][0, 29, 60][0, 28, 61][0, 29, 61][0, 28, 62][0, 29, 62][0, 28, 63][0, 29, 63]
MMCM:CONTROL_3[0, 28, 48][0, 29, 48][0, 28, 49][0, 29, 49][0, 28, 50][0, 29, 50][0, 28, 51][0, 29, 51][0, 28, 52][0, 29, 52][0, 28, 53][0, 29, 53][0, 28, 54][0, 29, 54][0, 28, 55][0, 29, 55]
MMCM:CONTROL_4[0, 28, 40][0, 29, 40][0, 28, 41][0, 29, 41][0, 28, 42][0, 29, 42][0, 28, 43][0, 29, 43][0, 28, 44][0, 29, 44][0, 28, 45][0, 29, 45][0, 28, 46][0, 29, 46][0, 28, 47][0, 29, 47]
MMCM:CONTROL_5[0, 28, 32][0, 29, 32][0, 28, 33][0, 29, 33][0, 28, 34][0, 29, 34][0, 28, 35][0, 29, 35][0, 28, 36][0, 29, 36][0, 28, 37][0, 29, 37][0, 28, 38][0, 29, 38][0, 28, 39][0, 29, 39]
MMCM:CONTROL_6[0, 28, 24][0, 29, 24][0, 28, 25][0, 29, 25][0, 28, 26][0, 29, 26][0, 28, 27][0, 29, 27][0, 28, 28][0, 29, 28][0, 28, 29][0, 29, 29][0, 28, 30][0, 29, 30][0, 28, 31][0, 29, 31]
MMCM:CONTROL_7[0, 28, 16][0, 29, 16][0, 28, 17][0, 29, 17][0, 28, 18][0, 29, 18][0, 28, 19][0, 29, 19][0, 28, 20][0, 29, 20][0, 28, 21][0, 29, 21][0, 28, 22][0, 29, 22][0, 28, 23][0, 29, 23]
MMCM:DRP00[15, 28, 56][15, 29, 56][15, 28, 57][15, 29, 57][15, 28, 58][15, 29, 58][15, 28, 59][15, 29, 59][15, 28, 60][15, 29, 60][15, 28, 61][15, 29, 61][15, 28, 62][15, 29, 62][15, 28, 63][15, 29, 63]
MMCM:DRP01[15, 28, 48][15, 29, 48][15, 28, 49][15, 29, 49][15, 28, 50][15, 29, 50][15, 28, 51][15, 29, 51][15, 28, 52][15, 29, 52][15, 28, 53][15, 29, 53][15, 28, 54][15, 29, 54][15, 28, 55][15, 29, 55]
MMCM:DRP02[15, 28, 40][15, 29, 40][15, 28, 41][15, 29, 41][15, 28, 42][15, 29, 42][15, 28, 43][15, 29, 43][15, 28, 44][15, 29, 44][15, 28, 45][15, 29, 45][15, 28, 46][15, 29, 46][15, 28, 47][15, 29, 47]
MMCM:DRP03[15, 28, 32][15, 29, 32][15, 28, 33][15, 29, 33][15, 28, 34][15, 29, 34][15, 28, 35][15, 29, 35][15, 28, 36][15, 29, 36][15, 28, 37][15, 29, 37][15, 28, 38][15, 29, 38][15, 28, 39][15, 29, 39]
MMCM:DRP04[15, 28, 24][15, 29, 24][15, 28, 25][15, 29, 25][15, 28, 26][15, 29, 26][15, 28, 27][15, 29, 27][15, 28, 28][15, 29, 28][15, 28, 29][15, 29, 29][15, 28, 30][15, 29, 30][15, 28, 31][15, 29, 31]
MMCM:DRP05[15, 28, 16][15, 29, 16][15, 28, 17][15, 29, 17][15, 28, 18][15, 29, 18][15, 28, 19][15, 29, 19][15, 28, 20][15, 29, 20][15, 28, 21][15, 29, 21][15, 28, 22][15, 29, 22][15, 28, 23][15, 29, 23]
MMCM:DRP06[15, 28, 8][15, 29, 8][15, 28, 9][15, 29, 9][15, 28, 10][15, 29, 10][15, 28, 11][15, 29, 11][15, 28, 12][15, 29, 12][15, 28, 13][15, 29, 13][15, 28, 14][15, 29, 14][15, 28, 15][15, 29, 15]
MMCM:DRP07[15, 28, 0][15, 29, 0][15, 28, 1][15, 29, 1][15, 28, 2][15, 29, 2][15, 28, 3][15, 29, 3][15, 28, 4][15, 29, 4][15, 28, 5][15, 29, 5][15, 28, 6][15, 29, 6][15, 28, 7][15, 29, 7]
MMCM:DRP08[14, 28, 56][14, 29, 56][14, 28, 57][14, 29, 57][14, 28, 58][14, 29, 58][14, 28, 59][14, 29, 59][14, 28, 60][14, 29, 60][14, 28, 61][14, 29, 61][14, 28, 62][14, 29, 62][14, 28, 63][14, 29, 63]
MMCM:DRP09[14, 28, 48][14, 29, 48][14, 28, 49][14, 29, 49][14, 28, 50][14, 29, 50][14, 28, 51][14, 29, 51][14, 28, 52][14, 29, 52][14, 28, 53][14, 29, 53][14, 28, 54][14, 29, 54][14, 28, 55][14, 29, 55]
MMCM:DRP0A[14, 28, 40][14, 29, 40][14, 28, 41][14, 29, 41][14, 28, 42][14, 29, 42][14, 28, 43][14, 29, 43][14, 28, 44][14, 29, 44][14, 28, 45][14, 29, 45][14, 28, 46][14, 29, 46][14, 28, 47][14, 29, 47]
MMCM:DRP0B[14, 28, 32][14, 29, 32][14, 28, 33][14, 29, 33][14, 28, 34][14, 29, 34][14, 28, 35][14, 29, 35][14, 28, 36][14, 29, 36][14, 28, 37][14, 29, 37][14, 28, 38][14, 29, 38][14, 28, 39][14, 29, 39]
MMCM:DRP0C[14, 28, 24][14, 29, 24][14, 28, 25][14, 29, 25][14, 28, 26][14, 29, 26][14, 28, 27][14, 29, 27][14, 28, 28][14, 29, 28][14, 28, 29][14, 29, 29][14, 28, 30][14, 29, 30][14, 28, 31][14, 29, 31]
MMCM:DRP0D[14, 28, 16][14, 29, 16][14, 28, 17][14, 29, 17][14, 28, 18][14, 29, 18][14, 28, 19][14, 29, 19][14, 28, 20][14, 29, 20][14, 28, 21][14, 29, 21][14, 28, 22][14, 29, 22][14, 28, 23][14, 29, 23]
MMCM:DRP0E[14, 28, 8][14, 29, 8][14, 28, 9][14, 29, 9][14, 28, 10][14, 29, 10][14, 28, 11][14, 29, 11][14, 28, 12][14, 29, 12][14, 28, 13][14, 29, 13][14, 28, 14][14, 29, 14][14, 28, 15][14, 29, 15]
MMCM:DRP0F[14, 28, 0][14, 29, 0][14, 28, 1][14, 29, 1][14, 28, 2][14, 29, 2][14, 28, 3][14, 29, 3][14, 28, 4][14, 29, 4][14, 28, 5][14, 29, 5][14, 28, 6][14, 29, 6][14, 28, 7][14, 29, 7]
MMCM:DRP10[13, 28, 56][13, 29, 56][13, 28, 57][13, 29, 57][13, 28, 58][13, 29, 58][13, 28, 59][13, 29, 59][13, 28, 60][13, 29, 60][13, 28, 61][13, 29, 61][13, 28, 62][13, 29, 62][13, 28, 63][13, 29, 63]
MMCM:DRP11[13, 28, 48][13, 29, 48][13, 28, 49][13, 29, 49][13, 28, 50][13, 29, 50][13, 28, 51][13, 29, 51][13, 28, 52][13, 29, 52][13, 28, 53][13, 29, 53][13, 28, 54][13, 29, 54][13, 28, 55][13, 29, 55]
MMCM:DRP12[13, 28, 40][13, 29, 40][13, 28, 41][13, 29, 41][13, 28, 42][13, 29, 42][13, 28, 43][13, 29, 43][13, 28, 44][13, 29, 44][13, 28, 45][13, 29, 45][13, 28, 46][13, 29, 46][13, 28, 47][13, 29, 47]
MMCM:DRP13[13, 28, 32][13, 29, 32][13, 28, 33][13, 29, 33][13, 28, 34][13, 29, 34][13, 28, 35][13, 29, 35][13, 28, 36][13, 29, 36][13, 28, 37][13, 29, 37][13, 28, 38][13, 29, 38][13, 28, 39][13, 29, 39]
MMCM:DRP14[13, 28, 24][13, 29, 24][13, 28, 25][13, 29, 25][13, 28, 26][13, 29, 26][13, 28, 27][13, 29, 27][13, 28, 28][13, 29, 28][13, 28, 29][13, 29, 29][13, 28, 30][13, 29, 30][13, 28, 31][13, 29, 31]
MMCM:DRP15[13, 28, 16][13, 29, 16][13, 28, 17][13, 29, 17][13, 28, 18][13, 29, 18][13, 28, 19][13, 29, 19][13, 28, 20][13, 29, 20][13, 28, 21][13, 29, 21][13, 28, 22][13, 29, 22][13, 28, 23][13, 29, 23]
MMCM:DRP16[13, 28, 8][13, 29, 8][13, 28, 9][13, 29, 9][13, 28, 10][13, 29, 10][13, 28, 11][13, 29, 11][13, 28, 12][13, 29, 12][13, 28, 13][13, 29, 13][13, 28, 14][13, 29, 14][13, 28, 15][13, 29, 15]
MMCM:DRP17[13, 28, 0][13, 29, 0][13, 28, 1][13, 29, 1][13, 28, 2][13, 29, 2][13, 28, 3][13, 29, 3][13, 28, 4][13, 29, 4][13, 28, 5][13, 29, 5][13, 28, 6][13, 29, 6][13, 28, 7][13, 29, 7]
MMCM:DRP18[12, 28, 56][12, 29, 56][12, 28, 57][12, 29, 57][12, 28, 58][12, 29, 58][12, 28, 59][12, 29, 59][12, 28, 60][12, 29, 60][12, 28, 61][12, 29, 61][12, 28, 62][12, 29, 62][12, 28, 63][12, 29, 63]
MMCM:DRP19[12, 28, 48][12, 29, 48][12, 28, 49][12, 29, 49][12, 28, 50][12, 29, 50][12, 28, 51][12, 29, 51][12, 28, 52][12, 29, 52][12, 28, 53][12, 29, 53][12, 28, 54][12, 29, 54][12, 28, 55][12, 29, 55]
MMCM:DRP1A[12, 28, 40][12, 29, 40][12, 28, 41][12, 29, 41][12, 28, 42][12, 29, 42][12, 28, 43][12, 29, 43][12, 28, 44][12, 29, 44][12, 28, 45][12, 29, 45][12, 28, 46][12, 29, 46][12, 28, 47][12, 29, 47]
MMCM:DRP1B[12, 28, 32][12, 29, 32][12, 28, 33][12, 29, 33][12, 28, 34][12, 29, 34][12, 28, 35][12, 29, 35][12, 28, 36][12, 29, 36][12, 28, 37][12, 29, 37][12, 28, 38][12, 29, 38][12, 28, 39][12, 29, 39]
MMCM:DRP1C[12, 28, 24][12, 29, 24][12, 28, 25][12, 29, 25][12, 28, 26][12, 29, 26][12, 28, 27][12, 29, 27][12, 28, 28][12, 29, 28][12, 28, 29][12, 29, 29][12, 28, 30][12, 29, 30][12, 28, 31][12, 29, 31]
MMCM:DRP1D[12, 28, 16][12, 29, 16][12, 28, 17][12, 29, 17][12, 28, 18][12, 29, 18][12, 28, 19][12, 29, 19][12, 28, 20][12, 29, 20][12, 28, 21][12, 29, 21][12, 28, 22][12, 29, 22][12, 28, 23][12, 29, 23]
MMCM:DRP1E[12, 28, 8][12, 29, 8][12, 28, 9][12, 29, 9][12, 28, 10][12, 29, 10][12, 28, 11][12, 29, 11][12, 28, 12][12, 29, 12][12, 28, 13][12, 29, 13][12, 28, 14][12, 29, 14][12, 28, 15][12, 29, 15]
MMCM:DRP1F[12, 28, 0][12, 29, 0][12, 28, 1][12, 29, 1][12, 28, 2][12, 29, 2][12, 28, 3][12, 29, 3][12, 28, 4][12, 29, 4][12, 28, 5][12, 29, 5][12, 28, 6][12, 29, 6][12, 28, 7][12, 29, 7]
MMCM:DRP20[11, 28, 56][11, 29, 56][11, 28, 57][11, 29, 57][11, 28, 58][11, 29, 58][11, 28, 59][11, 29, 59][11, 28, 60][11, 29, 60][11, 28, 61][11, 29, 61][11, 28, 62][11, 29, 62][11, 28, 63][11, 29, 63]
MMCM:DRP21[11, 28, 48][11, 29, 48][11, 28, 49][11, 29, 49][11, 28, 50][11, 29, 50][11, 28, 51][11, 29, 51][11, 28, 52][11, 29, 52][11, 28, 53][11, 29, 53][11, 28, 54][11, 29, 54][11, 28, 55][11, 29, 55]
MMCM:DRP22[11, 28, 40][11, 29, 40][11, 28, 41][11, 29, 41][11, 28, 42][11, 29, 42][11, 28, 43][11, 29, 43][11, 28, 44][11, 29, 44][11, 28, 45][11, 29, 45][11, 28, 46][11, 29, 46][11, 28, 47][11, 29, 47]
MMCM:DRP23[11, 28, 32][11, 29, 32][11, 28, 33][11, 29, 33][11, 28, 34][11, 29, 34][11, 28, 35][11, 29, 35][11, 28, 36][11, 29, 36][11, 28, 37][11, 29, 37][11, 28, 38][11, 29, 38][11, 28, 39][11, 29, 39]
MMCM:DRP24[11, 28, 24][11, 29, 24][11, 28, 25][11, 29, 25][11, 28, 26][11, 29, 26][11, 28, 27][11, 29, 27][11, 28, 28][11, 29, 28][11, 28, 29][11, 29, 29][11, 28, 30][11, 29, 30][11, 28, 31][11, 29, 31]
MMCM:DRP25[11, 28, 16][11, 29, 16][11, 28, 17][11, 29, 17][11, 28, 18][11, 29, 18][11, 28, 19][11, 29, 19][11, 28, 20][11, 29, 20][11, 28, 21][11, 29, 21][11, 28, 22][11, 29, 22][11, 28, 23][11, 29, 23]
MMCM:DRP26[11, 28, 8][11, 29, 8][11, 28, 9][11, 29, 9][11, 28, 10][11, 29, 10][11, 28, 11][11, 29, 11][11, 28, 12][11, 29, 12][11, 28, 13][11, 29, 13][11, 28, 14][11, 29, 14][11, 28, 15][11, 29, 15]
MMCM:DRP27[11, 28, 0][11, 29, 0][11, 28, 1][11, 29, 1][11, 28, 2][11, 29, 2][11, 28, 3][11, 29, 3][11, 28, 4][11, 29, 4][11, 28, 5][11, 29, 5][11, 28, 6][11, 29, 6][11, 28, 7][11, 29, 7]
MMCM:DRP28[10, 28, 56][10, 29, 56][10, 28, 57][10, 29, 57][10, 28, 58][10, 29, 58][10, 28, 59][10, 29, 59][10, 28, 60][10, 29, 60][10, 28, 61][10, 29, 61][10, 28, 62][10, 29, 62][10, 28, 63][10, 29, 63]
MMCM:DRP29[10, 28, 48][10, 29, 48][10, 28, 49][10, 29, 49][10, 28, 50][10, 29, 50][10, 28, 51][10, 29, 51][10, 28, 52][10, 29, 52][10, 28, 53][10, 29, 53][10, 28, 54][10, 29, 54][10, 28, 55][10, 29, 55]
MMCM:DRP2A[10, 28, 40][10, 29, 40][10, 28, 41][10, 29, 41][10, 28, 42][10, 29, 42][10, 28, 43][10, 29, 43][10, 28, 44][10, 29, 44][10, 28, 45][10, 29, 45][10, 28, 46][10, 29, 46][10, 28, 47][10, 29, 47]
MMCM:DRP2B[10, 28, 32][10, 29, 32][10, 28, 33][10, 29, 33][10, 28, 34][10, 29, 34][10, 28, 35][10, 29, 35][10, 28, 36][10, 29, 36][10, 28, 37][10, 29, 37][10, 28, 38][10, 29, 38][10, 28, 39][10, 29, 39]
MMCM:DRP2C[10, 28, 24][10, 29, 24][10, 28, 25][10, 29, 25][10, 28, 26][10, 29, 26][10, 28, 27][10, 29, 27][10, 28, 28][10, 29, 28][10, 28, 29][10, 29, 29][10, 28, 30][10, 29, 30][10, 28, 31][10, 29, 31]
MMCM:DRP2D[10, 28, 16][10, 29, 16][10, 28, 17][10, 29, 17][10, 28, 18][10, 29, 18][10, 28, 19][10, 29, 19][10, 28, 20][10, 29, 20][10, 28, 21][10, 29, 21][10, 28, 22][10, 29, 22][10, 28, 23][10, 29, 23]
MMCM:DRP2E[10, 28, 8][10, 29, 8][10, 28, 9][10, 29, 9][10, 28, 10][10, 29, 10][10, 28, 11][10, 29, 11][10, 28, 12][10, 29, 12][10, 28, 13][10, 29, 13][10, 28, 14][10, 29, 14][10, 28, 15][10, 29, 15]
MMCM:DRP2F[10, 28, 0][10, 29, 0][10, 28, 1][10, 29, 1][10, 28, 2][10, 29, 2][10, 28, 3][10, 29, 3][10, 28, 4][10, 29, 4][10, 28, 5][10, 29, 5][10, 28, 6][10, 29, 6][10, 28, 7][10, 29, 7]
MMCM:DRP30[9, 28, 56][9, 29, 56][9, 28, 57][9, 29, 57][9, 28, 58][9, 29, 58][9, 28, 59][9, 29, 59][9, 28, 60][9, 29, 60][9, 28, 61][9, 29, 61][9, 28, 62][9, 29, 62][9, 28, 63][9, 29, 63]
MMCM:DRP31[9, 28, 48][9, 29, 48][9, 28, 49][9, 29, 49][9, 28, 50][9, 29, 50][9, 28, 51][9, 29, 51][9, 28, 52][9, 29, 52][9, 28, 53][9, 29, 53][9, 28, 54][9, 29, 54][9, 28, 55][9, 29, 55]
MMCM:DRP32[9, 28, 40][9, 29, 40][9, 28, 41][9, 29, 41][9, 28, 42][9, 29, 42][9, 28, 43][9, 29, 43][9, 28, 44][9, 29, 44][9, 28, 45][9, 29, 45][9, 28, 46][9, 29, 46][9, 28, 47][9, 29, 47]
MMCM:DRP33[9, 28, 32][9, 29, 32][9, 28, 33][9, 29, 33][9, 28, 34][9, 29, 34][9, 28, 35][9, 29, 35][9, 28, 36][9, 29, 36][9, 28, 37][9, 29, 37][9, 28, 38][9, 29, 38][9, 28, 39][9, 29, 39]
MMCM:DRP34[9, 28, 24][9, 29, 24][9, 28, 25][9, 29, 25][9, 28, 26][9, 29, 26][9, 28, 27][9, 29, 27][9, 28, 28][9, 29, 28][9, 28, 29][9, 29, 29][9, 28, 30][9, 29, 30][9, 28, 31][9, 29, 31]
MMCM:DRP35[9, 28, 16][9, 29, 16][9, 28, 17][9, 29, 17][9, 28, 18][9, 29, 18][9, 28, 19][9, 29, 19][9, 28, 20][9, 29, 20][9, 28, 21][9, 29, 21][9, 28, 22][9, 29, 22][9, 28, 23][9, 29, 23]
MMCM:DRP36[9, 28, 8][9, 29, 8][9, 28, 9][9, 29, 9][9, 28, 10][9, 29, 10][9, 28, 11][9, 29, 11][9, 28, 12][9, 29, 12][9, 28, 13][9, 29, 13][9, 28, 14][9, 29, 14][9, 28, 15][9, 29, 15]
MMCM:DRP37[9, 28, 0][9, 29, 0][9, 28, 1][9, 29, 1][9, 28, 2][9, 29, 2][9, 28, 3][9, 29, 3][9, 28, 4][9, 29, 4][9, 28, 5][9, 29, 5][9, 28, 6][9, 29, 6][9, 28, 7][9, 29, 7]
MMCM:DRP38[8, 28, 56][8, 29, 56][8, 28, 57][8, 29, 57][8, 28, 58][8, 29, 58][8, 28, 59][8, 29, 59][8, 28, 60][8, 29, 60][8, 28, 61][8, 29, 61][8, 28, 62][8, 29, 62][8, 28, 63][8, 29, 63]
MMCM:DRP39[8, 28, 48][8, 29, 48][8, 28, 49][8, 29, 49][8, 28, 50][8, 29, 50][8, 28, 51][8, 29, 51][8, 28, 52][8, 29, 52][8, 28, 53][8, 29, 53][8, 28, 54][8, 29, 54][8, 28, 55][8, 29, 55]
MMCM:DRP3A[8, 28, 40][8, 29, 40][8, 28, 41][8, 29, 41][8, 28, 42][8, 29, 42][8, 28, 43][8, 29, 43][8, 28, 44][8, 29, 44][8, 28, 45][8, 29, 45][8, 28, 46][8, 29, 46][8, 28, 47][8, 29, 47]
MMCM:DRP3B[8, 28, 32][8, 29, 32][8, 28, 33][8, 29, 33][8, 28, 34][8, 29, 34][8, 28, 35][8, 29, 35][8, 28, 36][8, 29, 36][8, 28, 37][8, 29, 37][8, 28, 38][8, 29, 38][8, 28, 39][8, 29, 39]
MMCM:DRP3C[8, 28, 24][8, 29, 24][8, 28, 25][8, 29, 25][8, 28, 26][8, 29, 26][8, 28, 27][8, 29, 27][8, 28, 28][8, 29, 28][8, 28, 29][8, 29, 29][8, 28, 30][8, 29, 30][8, 28, 31][8, 29, 31]
MMCM:DRP3D[8, 28, 16][8, 29, 16][8, 28, 17][8, 29, 17][8, 28, 18][8, 29, 18][8, 28, 19][8, 29, 19][8, 28, 20][8, 29, 20][8, 28, 21][8, 29, 21][8, 28, 22][8, 29, 22][8, 28, 23][8, 29, 23]
MMCM:DRP3E[8, 28, 8][8, 29, 8][8, 28, 9][8, 29, 9][8, 28, 10][8, 29, 10][8, 28, 11][8, 29, 11][8, 28, 12][8, 29, 12][8, 28, 13][8, 29, 13][8, 28, 14][8, 29, 14][8, 28, 15][8, 29, 15]
MMCM:DRP3F[8, 28, 0][8, 29, 0][8, 28, 1][8, 29, 1][8, 28, 2][8, 29, 2][8, 28, 3][8, 29, 3][8, 28, 4][8, 29, 4][8, 28, 5][8, 29, 5][8, 28, 6][8, 29, 6][8, 28, 7][8, 29, 7]
MMCM:DRP40[7, 28, 56][7, 29, 56][7, 28, 57][7, 29, 57][7, 28, 58][7, 29, 58][7, 28, 59][7, 29, 59][7, 28, 60][7, 29, 60][7, 28, 61][7, 29, 61][7, 28, 62][7, 29, 62][7, 28, 63][7, 29, 63]
MMCM:DRP41[7, 28, 48][7, 29, 48][7, 28, 49][7, 29, 49][7, 28, 50][7, 29, 50][7, 28, 51][7, 29, 51][7, 28, 52][7, 29, 52][7, 28, 53][7, 29, 53][7, 28, 54][7, 29, 54][7, 28, 55][7, 29, 55]
MMCM:DRP42[7, 28, 40][7, 29, 40][7, 28, 41][7, 29, 41][7, 28, 42][7, 29, 42][7, 28, 43][7, 29, 43][7, 28, 44][7, 29, 44][7, 28, 45][7, 29, 45][7, 28, 46][7, 29, 46][7, 28, 47][7, 29, 47]
MMCM:DRP43[7, 28, 32][7, 29, 32][7, 28, 33][7, 29, 33][7, 28, 34][7, 29, 34][7, 28, 35][7, 29, 35][7, 28, 36][7, 29, 36][7, 28, 37][7, 29, 37][7, 28, 38][7, 29, 38][7, 28, 39][7, 29, 39]
MMCM:DRP44[7, 28, 24][7, 29, 24][7, 28, 25][7, 29, 25][7, 28, 26][7, 29, 26][7, 28, 27][7, 29, 27][7, 28, 28][7, 29, 28][7, 28, 29][7, 29, 29][7, 28, 30][7, 29, 30][7, 28, 31][7, 29, 31]
MMCM:DRP45[7, 28, 16][7, 29, 16][7, 28, 17][7, 29, 17][7, 28, 18][7, 29, 18][7, 28, 19][7, 29, 19][7, 28, 20][7, 29, 20][7, 28, 21][7, 29, 21][7, 28, 22][7, 29, 22][7, 28, 23][7, 29, 23]
MMCM:DRP46[7, 28, 8][7, 29, 8][7, 28, 9][7, 29, 9][7, 28, 10][7, 29, 10][7, 28, 11][7, 29, 11][7, 28, 12][7, 29, 12][7, 28, 13][7, 29, 13][7, 28, 14][7, 29, 14][7, 28, 15][7, 29, 15]
MMCM:DRP47[7, 28, 0][7, 29, 0][7, 28, 1][7, 29, 1][7, 28, 2][7, 29, 2][7, 28, 3][7, 29, 3][7, 28, 4][7, 29, 4][7, 28, 5][7, 29, 5][7, 28, 6][7, 29, 6][7, 28, 7][7, 29, 7]
MMCM:DRP48[6, 28, 56][6, 29, 56][6, 28, 57][6, 29, 57][6, 28, 58][6, 29, 58][6, 28, 59][6, 29, 59][6, 28, 60][6, 29, 60][6, 28, 61][6, 29, 61][6, 28, 62][6, 29, 62][6, 28, 63][6, 29, 63]
MMCM:DRP49[6, 28, 48][6, 29, 48][6, 28, 49][6, 29, 49][6, 28, 50][6, 29, 50][6, 28, 51][6, 29, 51][6, 28, 52][6, 29, 52][6, 28, 53][6, 29, 53][6, 28, 54][6, 29, 54][6, 28, 55][6, 29, 55]
MMCM:DRP4A[6, 28, 40][6, 29, 40][6, 28, 41][6, 29, 41][6, 28, 42][6, 29, 42][6, 28, 43][6, 29, 43][6, 28, 44][6, 29, 44][6, 28, 45][6, 29, 45][6, 28, 46][6, 29, 46][6, 28, 47][6, 29, 47]
MMCM:DRP4B[6, 28, 32][6, 29, 32][6, 28, 33][6, 29, 33][6, 28, 34][6, 29, 34][6, 28, 35][6, 29, 35][6, 28, 36][6, 29, 36][6, 28, 37][6, 29, 37][6, 28, 38][6, 29, 38][6, 28, 39][6, 29, 39]
MMCM:DRP4C[6, 28, 24][6, 29, 24][6, 28, 25][6, 29, 25][6, 28, 26][6, 29, 26][6, 28, 27][6, 29, 27][6, 28, 28][6, 29, 28][6, 28, 29][6, 29, 29][6, 28, 30][6, 29, 30][6, 28, 31][6, 29, 31]
MMCM:DRP4D[6, 28, 16][6, 29, 16][6, 28, 17][6, 29, 17][6, 28, 18][6, 29, 18][6, 28, 19][6, 29, 19][6, 28, 20][6, 29, 20][6, 28, 21][6, 29, 21][6, 28, 22][6, 29, 22][6, 28, 23][6, 29, 23]
MMCM:DRP4E[6, 28, 8][6, 29, 8][6, 28, 9][6, 29, 9][6, 28, 10][6, 29, 10][6, 28, 11][6, 29, 11][6, 28, 12][6, 29, 12][6, 28, 13][6, 29, 13][6, 28, 14][6, 29, 14][6, 28, 15][6, 29, 15]
MMCM:DRP4F[6, 28, 0][6, 29, 0][6, 28, 1][6, 29, 1][6, 28, 2][6, 29, 2][6, 28, 3][6, 29, 3][6, 28, 4][6, 29, 4][6, 28, 5][6, 29, 5][6, 28, 6][6, 29, 6][6, 28, 7][6, 29, 7]
MMCM:DRP50[5, 28, 56][5, 29, 56][5, 28, 57][5, 29, 57][5, 28, 58][5, 29, 58][5, 28, 59][5, 29, 59][5, 28, 60][5, 29, 60][5, 28, 61][5, 29, 61][5, 28, 62][5, 29, 62][5, 28, 63][5, 29, 63]
MMCM:DRP51[5, 28, 48][5, 29, 48][5, 28, 49][5, 29, 49][5, 28, 50][5, 29, 50][5, 28, 51][5, 29, 51][5, 28, 52][5, 29, 52][5, 28, 53][5, 29, 53][5, 28, 54][5, 29, 54][5, 28, 55][5, 29, 55]
MMCM:DRP52[5, 28, 40][5, 29, 40][5, 28, 41][5, 29, 41][5, 28, 42][5, 29, 42][5, 28, 43][5, 29, 43][5, 28, 44][5, 29, 44][5, 28, 45][5, 29, 45][5, 28, 46][5, 29, 46][5, 28, 47][5, 29, 47]
MMCM:DRP53[5, 28, 32][5, 29, 32][5, 28, 33][5, 29, 33][5, 28, 34][5, 29, 34][5, 28, 35][5, 29, 35][5, 28, 36][5, 29, 36][5, 28, 37][5, 29, 37][5, 28, 38][5, 29, 38][5, 28, 39][5, 29, 39]
MMCM:DRP54[5, 28, 24][5, 29, 24][5, 28, 25][5, 29, 25][5, 28, 26][5, 29, 26][5, 28, 27][5, 29, 27][5, 28, 28][5, 29, 28][5, 28, 29][5, 29, 29][5, 28, 30][5, 29, 30][5, 28, 31][5, 29, 31]
MMCM:DRP55[5, 28, 16][5, 29, 16][5, 28, 17][5, 29, 17][5, 28, 18][5, 29, 18][5, 28, 19][5, 29, 19][5, 28, 20][5, 29, 20][5, 28, 21][5, 29, 21][5, 28, 22][5, 29, 22][5, 28, 23][5, 29, 23]
MMCM:DRP56[5, 28, 8][5, 29, 8][5, 28, 9][5, 29, 9][5, 28, 10][5, 29, 10][5, 28, 11][5, 29, 11][5, 28, 12][5, 29, 12][5, 28, 13][5, 29, 13][5, 28, 14][5, 29, 14][5, 28, 15][5, 29, 15]
MMCM:DRP57[5, 28, 0][5, 29, 0][5, 28, 1][5, 29, 1][5, 28, 2][5, 29, 2][5, 28, 3][5, 29, 3][5, 28, 4][5, 29, 4][5, 28, 5][5, 29, 5][5, 28, 6][5, 29, 6][5, 28, 7][5, 29, 7]
MMCM:DRP58[4, 28, 56][4, 29, 56][4, 28, 57][4, 29, 57][4, 28, 58][4, 29, 58][4, 28, 59][4, 29, 59][4, 28, 60][4, 29, 60][4, 28, 61][4, 29, 61][4, 28, 62][4, 29, 62][4, 28, 63][4, 29, 63]
MMCM:DRP59[4, 28, 48][4, 29, 48][4, 28, 49][4, 29, 49][4, 28, 50][4, 29, 50][4, 28, 51][4, 29, 51][4, 28, 52][4, 29, 52][4, 28, 53][4, 29, 53][4, 28, 54][4, 29, 54][4, 28, 55][4, 29, 55]
MMCM:DRP5A[4, 28, 40][4, 29, 40][4, 28, 41][4, 29, 41][4, 28, 42][4, 29, 42][4, 28, 43][4, 29, 43][4, 28, 44][4, 29, 44][4, 28, 45][4, 29, 45][4, 28, 46][4, 29, 46][4, 28, 47][4, 29, 47]
MMCM:DRP5B[4, 28, 32][4, 29, 32][4, 28, 33][4, 29, 33][4, 28, 34][4, 29, 34][4, 28, 35][4, 29, 35][4, 28, 36][4, 29, 36][4, 28, 37][4, 29, 37][4, 28, 38][4, 29, 38][4, 28, 39][4, 29, 39]
MMCM:DRP5C[4, 28, 24][4, 29, 24][4, 28, 25][4, 29, 25][4, 28, 26][4, 29, 26][4, 28, 27][4, 29, 27][4, 28, 28][4, 29, 28][4, 28, 29][4, 29, 29][4, 28, 30][4, 29, 30][4, 28, 31][4, 29, 31]
MMCM:DRP5D[4, 28, 16][4, 29, 16][4, 28, 17][4, 29, 17][4, 28, 18][4, 29, 18][4, 28, 19][4, 29, 19][4, 28, 20][4, 29, 20][4, 28, 21][4, 29, 21][4, 28, 22][4, 29, 22][4, 28, 23][4, 29, 23]
MMCM:DRP5E[4, 28, 8][4, 29, 8][4, 28, 9][4, 29, 9][4, 28, 10][4, 29, 10][4, 28, 11][4, 29, 11][4, 28, 12][4, 29, 12][4, 28, 13][4, 29, 13][4, 28, 14][4, 29, 14][4, 28, 15][4, 29, 15]
MMCM:DRP5F[4, 28, 0][4, 29, 0][4, 28, 1][4, 29, 1][4, 28, 2][4, 29, 2][4, 28, 3][4, 29, 3][4, 28, 4][4, 29, 4][4, 28, 5][4, 29, 5][4, 28, 6][4, 29, 6][4, 28, 7][4, 29, 7]
MMCM:DRP60[3, 28, 56][3, 29, 56][3, 28, 57][3, 29, 57][3, 28, 58][3, 29, 58][3, 28, 59][3, 29, 59][3, 28, 60][3, 29, 60][3, 28, 61][3, 29, 61][3, 28, 62][3, 29, 62][3, 28, 63][3, 29, 63]
MMCM:DRP61[3, 28, 48][3, 29, 48][3, 28, 49][3, 29, 49][3, 28, 50][3, 29, 50][3, 28, 51][3, 29, 51][3, 28, 52][3, 29, 52][3, 28, 53][3, 29, 53][3, 28, 54][3, 29, 54][3, 28, 55][3, 29, 55]
MMCM:DRP62[3, 28, 40][3, 29, 40][3, 28, 41][3, 29, 41][3, 28, 42][3, 29, 42][3, 28, 43][3, 29, 43][3, 28, 44][3, 29, 44][3, 28, 45][3, 29, 45][3, 28, 46][3, 29, 46][3, 28, 47][3, 29, 47]
MMCM:DRP63[3, 28, 32][3, 29, 32][3, 28, 33][3, 29, 33][3, 28, 34][3, 29, 34][3, 28, 35][3, 29, 35][3, 28, 36][3, 29, 36][3, 28, 37][3, 29, 37][3, 28, 38][3, 29, 38][3, 28, 39][3, 29, 39]
MMCM:DRP64[3, 28, 24][3, 29, 24][3, 28, 25][3, 29, 25][3, 28, 26][3, 29, 26][3, 28, 27][3, 29, 27][3, 28, 28][3, 29, 28][3, 28, 29][3, 29, 29][3, 28, 30][3, 29, 30][3, 28, 31][3, 29, 31]
MMCM:DRP65[3, 28, 16][3, 29, 16][3, 28, 17][3, 29, 17][3, 28, 18][3, 29, 18][3, 28, 19][3, 29, 19][3, 28, 20][3, 29, 20][3, 28, 21][3, 29, 21][3, 28, 22][3, 29, 22][3, 28, 23][3, 29, 23]
MMCM:DRP66[3, 28, 8][3, 29, 8][3, 28, 9][3, 29, 9][3, 28, 10][3, 29, 10][3, 28, 11][3, 29, 11][3, 28, 12][3, 29, 12][3, 28, 13][3, 29, 13][3, 28, 14][3, 29, 14][3, 28, 15][3, 29, 15]
MMCM:DRP67[3, 28, 0][3, 29, 0][3, 28, 1][3, 29, 1][3, 28, 2][3, 29, 2][3, 28, 3][3, 29, 3][3, 28, 4][3, 29, 4][3, 28, 5][3, 29, 5][3, 28, 6][3, 29, 6][3, 28, 7][3, 29, 7]
MMCM:DRP68[2, 28, 56][2, 29, 56][2, 28, 57][2, 29, 57][2, 28, 58][2, 29, 58][2, 28, 59][2, 29, 59][2, 28, 60][2, 29, 60][2, 28, 61][2, 29, 61][2, 28, 62][2, 29, 62][2, 28, 63][2, 29, 63]
MMCM:DRP69[2, 28, 48][2, 29, 48][2, 28, 49][2, 29, 49][2, 28, 50][2, 29, 50][2, 28, 51][2, 29, 51][2, 28, 52][2, 29, 52][2, 28, 53][2, 29, 53][2, 28, 54][2, 29, 54][2, 28, 55][2, 29, 55]
MMCM:DRP6A[2, 28, 40][2, 29, 40][2, 28, 41][2, 29, 41][2, 28, 42][2, 29, 42][2, 28, 43][2, 29, 43][2, 28, 44][2, 29, 44][2, 28, 45][2, 29, 45][2, 28, 46][2, 29, 46][2, 28, 47][2, 29, 47]
MMCM:DRP6B[2, 28, 32][2, 29, 32][2, 28, 33][2, 29, 33][2, 28, 34][2, 29, 34][2, 28, 35][2, 29, 35][2, 28, 36][2, 29, 36][2, 28, 37][2, 29, 37][2, 28, 38][2, 29, 38][2, 28, 39][2, 29, 39]
MMCM:DRP6C[2, 28, 24][2, 29, 24][2, 28, 25][2, 29, 25][2, 28, 26][2, 29, 26][2, 28, 27][2, 29, 27][2, 28, 28][2, 29, 28][2, 28, 29][2, 29, 29][2, 28, 30][2, 29, 30][2, 28, 31][2, 29, 31]
MMCM:DRP6D[2, 28, 16][2, 29, 16][2, 28, 17][2, 29, 17][2, 28, 18][2, 29, 18][2, 28, 19][2, 29, 19][2, 28, 20][2, 29, 20][2, 28, 21][2, 29, 21][2, 28, 22][2, 29, 22][2, 28, 23][2, 29, 23]
MMCM:DRP6E[2, 28, 8][2, 29, 8][2, 28, 9][2, 29, 9][2, 28, 10][2, 29, 10][2, 28, 11][2, 29, 11][2, 28, 12][2, 29, 12][2, 28, 13][2, 29, 13][2, 28, 14][2, 29, 14][2, 28, 15][2, 29, 15]
MMCM:DRP6F[2, 28, 0][2, 29, 0][2, 28, 1][2, 29, 1][2, 28, 2][2, 29, 2][2, 28, 3][2, 29, 3][2, 28, 4][2, 29, 4][2, 28, 5][2, 29, 5][2, 28, 6][2, 29, 6][2, 28, 7][2, 29, 7]
MMCM:DRP70[1, 28, 56][1, 29, 56][1, 28, 57][1, 29, 57][1, 28, 58][1, 29, 58][1, 28, 59][1, 29, 59][1, 28, 60][1, 29, 60][1, 28, 61][1, 29, 61][1, 28, 62][1, 29, 62][1, 28, 63][1, 29, 63]
MMCM:DRP71[1, 28, 48][1, 29, 48][1, 28, 49][1, 29, 49][1, 28, 50][1, 29, 50][1, 28, 51][1, 29, 51][1, 28, 52][1, 29, 52][1, 28, 53][1, 29, 53][1, 28, 54][1, 29, 54][1, 28, 55][1, 29, 55]
MMCM:DRP72[1, 28, 40][1, 29, 40][1, 28, 41][1, 29, 41][1, 28, 42][1, 29, 42][1, 28, 43][1, 29, 43][1, 28, 44][1, 29, 44][1, 28, 45][1, 29, 45][1, 28, 46][1, 29, 46][1, 28, 47][1, 29, 47]
MMCM:DRP73[1, 28, 32][1, 29, 32][1, 28, 33][1, 29, 33][1, 28, 34][1, 29, 34][1, 28, 35][1, 29, 35][1, 28, 36][1, 29, 36][1, 28, 37][1, 29, 37][1, 28, 38][1, 29, 38][1, 28, 39][1, 29, 39]
MMCM:DRP74[1, 28, 24][1, 29, 24][1, 28, 25][1, 29, 25][1, 28, 26][1, 29, 26][1, 28, 27][1, 29, 27][1, 28, 28][1, 29, 28][1, 28, 29][1, 29, 29][1, 28, 30][1, 29, 30][1, 28, 31][1, 29, 31]
MMCM:DRP75[1, 28, 16][1, 29, 16][1, 28, 17][1, 29, 17][1, 28, 18][1, 29, 18][1, 28, 19][1, 29, 19][1, 28, 20][1, 29, 20][1, 28, 21][1, 29, 21][1, 28, 22][1, 29, 22][1, 28, 23][1, 29, 23]
MMCM:DRP76[1, 28, 8][1, 29, 8][1, 28, 9][1, 29, 9][1, 28, 10][1, 29, 10][1, 28, 11][1, 29, 11][1, 28, 12][1, 29, 12][1, 28, 13][1, 29, 13][1, 28, 14][1, 29, 14][1, 28, 15][1, 29, 15]
MMCM:DRP77[1, 28, 0][1, 29, 0][1, 28, 1][1, 29, 1][1, 28, 2][1, 29, 2][1, 28, 3][1, 29, 3][1, 28, 4][1, 29, 4][1, 28, 5][1, 29, 5][1, 28, 6][1, 29, 6][1, 28, 7][1, 29, 7]
MMCM:DRP78[0, 28, 56][0, 29, 56][0, 28, 57][0, 29, 57][0, 28, 58][0, 29, 58][0, 28, 59][0, 29, 59][0, 28, 60][0, 29, 60][0, 28, 61][0, 29, 61][0, 28, 62][0, 29, 62][0, 28, 63][0, 29, 63]
MMCM:DRP79[0, 28, 48][0, 29, 48][0, 28, 49][0, 29, 49][0, 28, 50][0, 29, 50][0, 28, 51][0, 29, 51][0, 28, 52][0, 29, 52][0, 28, 53][0, 29, 53][0, 28, 54][0, 29, 54][0, 28, 55][0, 29, 55]
MMCM:DRP7A[0, 28, 40][0, 29, 40][0, 28, 41][0, 29, 41][0, 28, 42][0, 29, 42][0, 28, 43][0, 29, 43][0, 28, 44][0, 29, 44][0, 28, 45][0, 29, 45][0, 28, 46][0, 29, 46][0, 28, 47][0, 29, 47]
MMCM:DRP7B[0, 28, 32][0, 29, 32][0, 28, 33][0, 29, 33][0, 28, 34][0, 29, 34][0, 28, 35][0, 29, 35][0, 28, 36][0, 29, 36][0, 28, 37][0, 29, 37][0, 28, 38][0, 29, 38][0, 28, 39][0, 29, 39]
MMCM:DRP7C[0, 28, 24][0, 29, 24][0, 28, 25][0, 29, 25][0, 28, 26][0, 29, 26][0, 28, 27][0, 29, 27][0, 28, 28][0, 29, 28][0, 28, 29][0, 29, 29][0, 28, 30][0, 29, 30][0, 28, 31][0, 29, 31]
MMCM:DRP7D[0, 28, 16][0, 29, 16][0, 28, 17][0, 29, 17][0, 28, 18][0, 29, 18][0, 28, 19][0, 29, 19][0, 28, 20][0, 29, 20][0, 28, 21][0, 29, 21][0, 28, 22][0, 29, 22][0, 28, 23][0, 29, 23]
MMCM:DRP7E[0, 28, 8][0, 29, 8][0, 28, 9][0, 29, 9][0, 28, 10][0, 29, 10][0, 28, 11][0, 29, 11][0, 28, 12][0, 29, 12][0, 28, 13][0, 29, 13][0, 28, 14][0, 29, 14][0, 28, 15][0, 29, 15]
MMCM:DRP7F[0, 28, 0][0, 29, 0][0, 28, 1][0, 29, 1][0, 28, 2][0, 29, 2][0, 28, 3][0, 29, 3][0, 28, 4][0, 29, 4][0, 28, 5][0, 29, 5][0, 28, 6][0, 29, 6][0, 28, 7][0, 29, 7]
PHASER_REF:CONTROL_0[26, 29, 55][26, 28, 55][26, 29, 54][26, 28, 54][26, 29, 53][26, 28, 53][26, 29, 52][26, 28, 52][26, 29, 51][26, 28, 51][26, 29, 50][26, 28, 50][26, 29, 49][26, 28, 49][26, 29, 48][26, 28, 48]
PHASER_REF:CONTROL_1[26, 29, 47][26, 28, 47][26, 29, 46][26, 28, 46][26, 29, 45][26, 28, 45][26, 29, 44][26, 28, 44][26, 29, 43][26, 28, 43][26, 29, 42][26, 28, 42][26, 29, 41][26, 28, 41][26, 29, 40][26, 28, 40]
PHASER_REF:CONTROL_2[26, 29, 39][26, 28, 39][26, 29, 38][26, 28, 38][26, 29, 37][26, 28, 37][26, 29, 36][26, 28, 36][26, 29, 35][26, 28, 35][26, 29, 34][26, 28, 34][26, 29, 33][26, 28, 33][26, 29, 32][26, 28, 32]
PHASER_REF:CONTROL_3[26, 29, 15][26, 28, 15][26, 29, 14][26, 28, 14][26, 29, 13][26, 28, 13][26, 29, 12][26, 28, 12][26, 29, 11][26, 28, 11][26, 29, 10][26, 28, 10][26, 29, 9][26, 28, 9][26, 29, 8][26, 28, 8]
PHASER_REF:CONTROL_4[27, 29, 7][27, 28, 7][27, 29, 6][27, 28, 6][27, 29, 5][27, 28, 5][27, 29, 4][27, 28, 4][27, 29, 3][27, 28, 3][27, 29, 2][27, 28, 2][27, 29, 1][27, 28, 1][27, 29, 0][27, 28, 0]
PHASER_REF:CONTROL_5[27, 29, 15][27, 28, 15][27, 29, 14][27, 28, 14][27, 29, 13][27, 28, 13][27, 29, 12][27, 28, 12][27, 29, 11][27, 28, 11][27, 29, 10][27, 28, 10][27, 29, 9][27, 28, 9][27, 29, 8][27, 28, 8]
PLL:CONTROL_0[48, 29, 55][48, 28, 55][48, 29, 54][48, 28, 54][48, 29, 53][48, 28, 53][48, 29, 52][48, 28, 52][48, 29, 51][48, 28, 51][48, 29, 50][48, 28, 50][48, 29, 49][48, 28, 49][48, 29, 48][48, 28, 48]
PLL:CONTROL_1[48, 29, 63][48, 28, 63][48, 29, 62][48, 28, 62][48, 29, 61][48, 28, 61][48, 29, 60][48, 28, 60][48, 29, 59][48, 28, 59][48, 29, 58][48, 28, 58][48, 29, 57][48, 28, 57][48, 29, 56][48, 28, 56]
PLL:CONTROL_2[49, 29, 7][49, 28, 7][49, 29, 6][49, 28, 6][49, 29, 5][49, 28, 5][49, 29, 4][49, 28, 4][49, 29, 3][49, 28, 3][49, 29, 2][49, 28, 2][49, 29, 1][49, 28, 1][49, 29, 0][49, 28, 0]
PLL:CONTROL_3[49, 29, 15][49, 28, 15][49, 29, 14][49, 28, 14][49, 29, 13][49, 28, 13][49, 29, 12][49, 28, 12][49, 29, 11][49, 28, 11][49, 29, 10][49, 28, 10][49, 29, 9][49, 28, 9][49, 29, 8][49, 28, 8]
PLL:CONTROL_4[49, 29, 23][49, 28, 23][49, 29, 22][49, 28, 22][49, 29, 21][49, 28, 21][49, 29, 20][49, 28, 20][49, 29, 19][49, 28, 19][49, 29, 18][49, 28, 18][49, 29, 17][49, 28, 17][49, 29, 16][49, 28, 16]
PLL:CONTROL_5[49, 29, 31][49, 28, 31][49, 29, 30][49, 28, 30][49, 29, 29][49, 28, 29][49, 29, 28][49, 28, 28][49, 29, 27][49, 28, 27][49, 29, 26][49, 28, 26][49, 29, 25][49, 28, 25][49, 29, 24][49, 28, 24]
PLL:CONTROL_6[49, 29, 39][49, 28, 39][49, 29, 38][49, 28, 38][49, 29, 37][49, 28, 37][49, 29, 36][49, 28, 36][49, 29, 35][49, 28, 35][49, 29, 34][49, 28, 34][49, 29, 33][49, 28, 33][49, 29, 32][49, 28, 32]
PLL:CONTROL_7[49, 29, 47][49, 28, 47][49, 29, 46][49, 28, 46][49, 29, 45][49, 28, 45][49, 29, 44][49, 28, 44][49, 29, 43][49, 28, 43][49, 29, 42][49, 28, 42][49, 29, 41][49, 28, 41][49, 29, 40][49, 28, 40]
PLL:DRP00[37, 29, 7][37, 28, 7][37, 29, 6][37, 28, 6][37, 29, 5][37, 28, 5][37, 29, 4][37, 28, 4][37, 29, 3][37, 28, 3][37, 29, 2][37, 28, 2][37, 29, 1][37, 28, 1][37, 29, 0][37, 28, 0]
PLL:DRP01[37, 29, 15][37, 28, 15][37, 29, 14][37, 28, 14][37, 29, 13][37, 28, 13][37, 29, 12][37, 28, 12][37, 29, 11][37, 28, 11][37, 29, 10][37, 28, 10][37, 29, 9][37, 28, 9][37, 29, 8][37, 28, 8]
PLL:DRP02[37, 29, 23][37, 28, 23][37, 29, 22][37, 28, 22][37, 29, 21][37, 28, 21][37, 29, 20][37, 28, 20][37, 29, 19][37, 28, 19][37, 29, 18][37, 28, 18][37, 29, 17][37, 28, 17][37, 29, 16][37, 28, 16]
PLL:DRP03[37, 29, 31][37, 28, 31][37, 29, 30][37, 28, 30][37, 29, 29][37, 28, 29][37, 29, 28][37, 28, 28][37, 29, 27][37, 28, 27][37, 29, 26][37, 28, 26][37, 29, 25][37, 28, 25][37, 29, 24][37, 28, 24]
PLL:DRP04[37, 29, 39][37, 28, 39][37, 29, 38][37, 28, 38][37, 29, 37][37, 28, 37][37, 29, 36][37, 28, 36][37, 29, 35][37, 28, 35][37, 29, 34][37, 28, 34][37, 29, 33][37, 28, 33][37, 29, 32][37, 28, 32]
PLL:DRP05[37, 29, 47][37, 28, 47][37, 29, 46][37, 28, 46][37, 29, 45][37, 28, 45][37, 29, 44][37, 28, 44][37, 29, 43][37, 28, 43][37, 29, 42][37, 28, 42][37, 29, 41][37, 28, 41][37, 29, 40][37, 28, 40]
PLL:DRP06[37, 29, 55][37, 28, 55][37, 29, 54][37, 28, 54][37, 29, 53][37, 28, 53][37, 29, 52][37, 28, 52][37, 29, 51][37, 28, 51][37, 29, 50][37, 28, 50][37, 29, 49][37, 28, 49][37, 29, 48][37, 28, 48]
PLL:DRP07[37, 29, 63][37, 28, 63][37, 29, 62][37, 28, 62][37, 29, 61][37, 28, 61][37, 29, 60][37, 28, 60][37, 29, 59][37, 28, 59][37, 29, 58][37, 28, 58][37, 29, 57][37, 28, 57][37, 29, 56][37, 28, 56]
PLL:DRP08[38, 29, 7][38, 28, 7][38, 29, 6][38, 28, 6][38, 29, 5][38, 28, 5][38, 29, 4][38, 28, 4][38, 29, 3][38, 28, 3][38, 29, 2][38, 28, 2][38, 29, 1][38, 28, 1][38, 29, 0][38, 28, 0]
PLL:DRP09[38, 29, 15][38, 28, 15][38, 29, 14][38, 28, 14][38, 29, 13][38, 28, 13][38, 29, 12][38, 28, 12][38, 29, 11][38, 28, 11][38, 29, 10][38, 28, 10][38, 29, 9][38, 28, 9][38, 29, 8][38, 28, 8]
PLL:DRP0A[38, 29, 23][38, 28, 23][38, 29, 22][38, 28, 22][38, 29, 21][38, 28, 21][38, 29, 20][38, 28, 20][38, 29, 19][38, 28, 19][38, 29, 18][38, 28, 18][38, 29, 17][38, 28, 17][38, 29, 16][38, 28, 16]
PLL:DRP0B[38, 29, 31][38, 28, 31][38, 29, 30][38, 28, 30][38, 29, 29][38, 28, 29][38, 29, 28][38, 28, 28][38, 29, 27][38, 28, 27][38, 29, 26][38, 28, 26][38, 29, 25][38, 28, 25][38, 29, 24][38, 28, 24]
PLL:DRP0C[38, 29, 39][38, 28, 39][38, 29, 38][38, 28, 38][38, 29, 37][38, 28, 37][38, 29, 36][38, 28, 36][38, 29, 35][38, 28, 35][38, 29, 34][38, 28, 34][38, 29, 33][38, 28, 33][38, 29, 32][38, 28, 32]
PLL:DRP0D[38, 29, 47][38, 28, 47][38, 29, 46][38, 28, 46][38, 29, 45][38, 28, 45][38, 29, 44][38, 28, 44][38, 29, 43][38, 28, 43][38, 29, 42][38, 28, 42][38, 29, 41][38, 28, 41][38, 29, 40][38, 28, 40]
PLL:DRP0E[38, 29, 55][38, 28, 55][38, 29, 54][38, 28, 54][38, 29, 53][38, 28, 53][38, 29, 52][38, 28, 52][38, 29, 51][38, 28, 51][38, 29, 50][38, 28, 50][38, 29, 49][38, 28, 49][38, 29, 48][38, 28, 48]
PLL:DRP0F[38, 29, 63][38, 28, 63][38, 29, 62][38, 28, 62][38, 29, 61][38, 28, 61][38, 29, 60][38, 28, 60][38, 29, 59][38, 28, 59][38, 29, 58][38, 28, 58][38, 29, 57][38, 28, 57][38, 29, 56][38, 28, 56]
PLL:DRP10[39, 29, 7][39, 28, 7][39, 29, 6][39, 28, 6][39, 29, 5][39, 28, 5][39, 29, 4][39, 28, 4][39, 29, 3][39, 28, 3][39, 29, 2][39, 28, 2][39, 29, 1][39, 28, 1][39, 29, 0][39, 28, 0]
PLL:DRP11[39, 29, 15][39, 28, 15][39, 29, 14][39, 28, 14][39, 29, 13][39, 28, 13][39, 29, 12][39, 28, 12][39, 29, 11][39, 28, 11][39, 29, 10][39, 28, 10][39, 29, 9][39, 28, 9][39, 29, 8][39, 28, 8]
PLL:DRP12[39, 29, 23][39, 28, 23][39, 29, 22][39, 28, 22][39, 29, 21][39, 28, 21][39, 29, 20][39, 28, 20][39, 29, 19][39, 28, 19][39, 29, 18][39, 28, 18][39, 29, 17][39, 28, 17][39, 29, 16][39, 28, 16]
PLL:DRP13[39, 29, 31][39, 28, 31][39, 29, 30][39, 28, 30][39, 29, 29][39, 28, 29][39, 29, 28][39, 28, 28][39, 29, 27][39, 28, 27][39, 29, 26][39, 28, 26][39, 29, 25][39, 28, 25][39, 29, 24][39, 28, 24]
PLL:DRP14[39, 29, 39][39, 28, 39][39, 29, 38][39, 28, 38][39, 29, 37][39, 28, 37][39, 29, 36][39, 28, 36][39, 29, 35][39, 28, 35][39, 29, 34][39, 28, 34][39, 29, 33][39, 28, 33][39, 29, 32][39, 28, 32]
PLL:DRP15[39, 29, 47][39, 28, 47][39, 29, 46][39, 28, 46][39, 29, 45][39, 28, 45][39, 29, 44][39, 28, 44][39, 29, 43][39, 28, 43][39, 29, 42][39, 28, 42][39, 29, 41][39, 28, 41][39, 29, 40][39, 28, 40]
PLL:DRP16[39, 29, 55][39, 28, 55][39, 29, 54][39, 28, 54][39, 29, 53][39, 28, 53][39, 29, 52][39, 28, 52][39, 29, 51][39, 28, 51][39, 29, 50][39, 28, 50][39, 29, 49][39, 28, 49][39, 29, 48][39, 28, 48]
PLL:DRP17[39, 29, 63][39, 28, 63][39, 29, 62][39, 28, 62][39, 29, 61][39, 28, 61][39, 29, 60][39, 28, 60][39, 29, 59][39, 28, 59][39, 29, 58][39, 28, 58][39, 29, 57][39, 28, 57][39, 29, 56][39, 28, 56]
PLL:DRP18[40, 29, 7][40, 28, 7][40, 29, 6][40, 28, 6][40, 29, 5][40, 28, 5][40, 29, 4][40, 28, 4][40, 29, 3][40, 28, 3][40, 29, 2][40, 28, 2][40, 29, 1][40, 28, 1][40, 29, 0][40, 28, 0]
PLL:DRP19[40, 29, 15][40, 28, 15][40, 29, 14][40, 28, 14][40, 29, 13][40, 28, 13][40, 29, 12][40, 28, 12][40, 29, 11][40, 28, 11][40, 29, 10][40, 28, 10][40, 29, 9][40, 28, 9][40, 29, 8][40, 28, 8]
PLL:DRP1A[40, 29, 23][40, 28, 23][40, 29, 22][40, 28, 22][40, 29, 21][40, 28, 21][40, 29, 20][40, 28, 20][40, 29, 19][40, 28, 19][40, 29, 18][40, 28, 18][40, 29, 17][40, 28, 17][40, 29, 16][40, 28, 16]
PLL:DRP1B[40, 29, 31][40, 28, 31][40, 29, 30][40, 28, 30][40, 29, 29][40, 28, 29][40, 29, 28][40, 28, 28][40, 29, 27][40, 28, 27][40, 29, 26][40, 28, 26][40, 29, 25][40, 28, 25][40, 29, 24][40, 28, 24]
PLL:DRP1C[40, 29, 39][40, 28, 39][40, 29, 38][40, 28, 38][40, 29, 37][40, 28, 37][40, 29, 36][40, 28, 36][40, 29, 35][40, 28, 35][40, 29, 34][40, 28, 34][40, 29, 33][40, 28, 33][40, 29, 32][40, 28, 32]
PLL:DRP1D[40, 29, 47][40, 28, 47][40, 29, 46][40, 28, 46][40, 29, 45][40, 28, 45][40, 29, 44][40, 28, 44][40, 29, 43][40, 28, 43][40, 29, 42][40, 28, 42][40, 29, 41][40, 28, 41][40, 29, 40][40, 28, 40]
PLL:DRP1E[40, 29, 55][40, 28, 55][40, 29, 54][40, 28, 54][40, 29, 53][40, 28, 53][40, 29, 52][40, 28, 52][40, 29, 51][40, 28, 51][40, 29, 50][40, 28, 50][40, 29, 49][40, 28, 49][40, 29, 48][40, 28, 48]
PLL:DRP1F[40, 29, 63][40, 28, 63][40, 29, 62][40, 28, 62][40, 29, 61][40, 28, 61][40, 29, 60][40, 28, 60][40, 29, 59][40, 28, 59][40, 29, 58][40, 28, 58][40, 29, 57][40, 28, 57][40, 29, 56][40, 28, 56]
PLL:DRP20[41, 29, 7][41, 28, 7][41, 29, 6][41, 28, 6][41, 29, 5][41, 28, 5][41, 29, 4][41, 28, 4][41, 29, 3][41, 28, 3][41, 29, 2][41, 28, 2][41, 29, 1][41, 28, 1][41, 29, 0][41, 28, 0]
PLL:DRP21[41, 29, 15][41, 28, 15][41, 29, 14][41, 28, 14][41, 29, 13][41, 28, 13][41, 29, 12][41, 28, 12][41, 29, 11][41, 28, 11][41, 29, 10][41, 28, 10][41, 29, 9][41, 28, 9][41, 29, 8][41, 28, 8]
PLL:DRP22[41, 29, 23][41, 28, 23][41, 29, 22][41, 28, 22][41, 29, 21][41, 28, 21][41, 29, 20][41, 28, 20][41, 29, 19][41, 28, 19][41, 29, 18][41, 28, 18][41, 29, 17][41, 28, 17][41, 29, 16][41, 28, 16]
PLL:DRP23[41, 29, 31][41, 28, 31][41, 29, 30][41, 28, 30][41, 29, 29][41, 28, 29][41, 29, 28][41, 28, 28][41, 29, 27][41, 28, 27][41, 29, 26][41, 28, 26][41, 29, 25][41, 28, 25][41, 29, 24][41, 28, 24]
PLL:DRP24[41, 29, 39][41, 28, 39][41, 29, 38][41, 28, 38][41, 29, 37][41, 28, 37][41, 29, 36][41, 28, 36][41, 29, 35][41, 28, 35][41, 29, 34][41, 28, 34][41, 29, 33][41, 28, 33][41, 29, 32][41, 28, 32]
PLL:DRP25[41, 29, 47][41, 28, 47][41, 29, 46][41, 28, 46][41, 29, 45][41, 28, 45][41, 29, 44][41, 28, 44][41, 29, 43][41, 28, 43][41, 29, 42][41, 28, 42][41, 29, 41][41, 28, 41][41, 29, 40][41, 28, 40]
PLL:DRP26[41, 29, 55][41, 28, 55][41, 29, 54][41, 28, 54][41, 29, 53][41, 28, 53][41, 29, 52][41, 28, 52][41, 29, 51][41, 28, 51][41, 29, 50][41, 28, 50][41, 29, 49][41, 28, 49][41, 29, 48][41, 28, 48]
PLL:DRP27[41, 29, 63][41, 28, 63][41, 29, 62][41, 28, 62][41, 29, 61][41, 28, 61][41, 29, 60][41, 28, 60][41, 29, 59][41, 28, 59][41, 29, 58][41, 28, 58][41, 29, 57][41, 28, 57][41, 29, 56][41, 28, 56]
PLL:DRP28[42, 29, 7][42, 28, 7][42, 29, 6][42, 28, 6][42, 29, 5][42, 28, 5][42, 29, 4][42, 28, 4][42, 29, 3][42, 28, 3][42, 29, 2][42, 28, 2][42, 29, 1][42, 28, 1][42, 29, 0][42, 28, 0]
PLL:DRP29[42, 29, 15][42, 28, 15][42, 29, 14][42, 28, 14][42, 29, 13][42, 28, 13][42, 29, 12][42, 28, 12][42, 29, 11][42, 28, 11][42, 29, 10][42, 28, 10][42, 29, 9][42, 28, 9][42, 29, 8][42, 28, 8]
PLL:DRP2A[42, 29, 23][42, 28, 23][42, 29, 22][42, 28, 22][42, 29, 21][42, 28, 21][42, 29, 20][42, 28, 20][42, 29, 19][42, 28, 19][42, 29, 18][42, 28, 18][42, 29, 17][42, 28, 17][42, 29, 16][42, 28, 16]
PLL:DRP2B[42, 29, 31][42, 28, 31][42, 29, 30][42, 28, 30][42, 29, 29][42, 28, 29][42, 29, 28][42, 28, 28][42, 29, 27][42, 28, 27][42, 29, 26][42, 28, 26][42, 29, 25][42, 28, 25][42, 29, 24][42, 28, 24]
PLL:DRP2C[42, 29, 39][42, 28, 39][42, 29, 38][42, 28, 38][42, 29, 37][42, 28, 37][42, 29, 36][42, 28, 36][42, 29, 35][42, 28, 35][42, 29, 34][42, 28, 34][42, 29, 33][42, 28, 33][42, 29, 32][42, 28, 32]
PLL:DRP2D[42, 29, 47][42, 28, 47][42, 29, 46][42, 28, 46][42, 29, 45][42, 28, 45][42, 29, 44][42, 28, 44][42, 29, 43][42, 28, 43][42, 29, 42][42, 28, 42][42, 29, 41][42, 28, 41][42, 29, 40][42, 28, 40]
PLL:DRP2E[42, 29, 55][42, 28, 55][42, 29, 54][42, 28, 54][42, 29, 53][42, 28, 53][42, 29, 52][42, 28, 52][42, 29, 51][42, 28, 51][42, 29, 50][42, 28, 50][42, 29, 49][42, 28, 49][42, 29, 48][42, 28, 48]
PLL:DRP2F[42, 29, 63][42, 28, 63][42, 29, 62][42, 28, 62][42, 29, 61][42, 28, 61][42, 29, 60][42, 28, 60][42, 29, 59][42, 28, 59][42, 29, 58][42, 28, 58][42, 29, 57][42, 28, 57][42, 29, 56][42, 28, 56]
PLL:DRP30[43, 29, 7][43, 28, 7][43, 29, 6][43, 28, 6][43, 29, 5][43, 28, 5][43, 29, 4][43, 28, 4][43, 29, 3][43, 28, 3][43, 29, 2][43, 28, 2][43, 29, 1][43, 28, 1][43, 29, 0][43, 28, 0]
PLL:DRP31[43, 29, 15][43, 28, 15][43, 29, 14][43, 28, 14][43, 29, 13][43, 28, 13][43, 29, 12][43, 28, 12][43, 29, 11][43, 28, 11][43, 29, 10][43, 28, 10][43, 29, 9][43, 28, 9][43, 29, 8][43, 28, 8]
PLL:DRP32[43, 29, 23][43, 28, 23][43, 29, 22][43, 28, 22][43, 29, 21][43, 28, 21][43, 29, 20][43, 28, 20][43, 29, 19][43, 28, 19][43, 29, 18][43, 28, 18][43, 29, 17][43, 28, 17][43, 29, 16][43, 28, 16]
PLL:DRP33[43, 29, 31][43, 28, 31][43, 29, 30][43, 28, 30][43, 29, 29][43, 28, 29][43, 29, 28][43, 28, 28][43, 29, 27][43, 28, 27][43, 29, 26][43, 28, 26][43, 29, 25][43, 28, 25][43, 29, 24][43, 28, 24]
PLL:DRP34[43, 29, 39][43, 28, 39][43, 29, 38][43, 28, 38][43, 29, 37][43, 28, 37][43, 29, 36][43, 28, 36][43, 29, 35][43, 28, 35][43, 29, 34][43, 28, 34][43, 29, 33][43, 28, 33][43, 29, 32][43, 28, 32]
PLL:DRP35[43, 29, 47][43, 28, 47][43, 29, 46][43, 28, 46][43, 29, 45][43, 28, 45][43, 29, 44][43, 28, 44][43, 29, 43][43, 28, 43][43, 29, 42][43, 28, 42][43, 29, 41][43, 28, 41][43, 29, 40][43, 28, 40]
PLL:DRP36[43, 29, 55][43, 28, 55][43, 29, 54][43, 28, 54][43, 29, 53][43, 28, 53][43, 29, 52][43, 28, 52][43, 29, 51][43, 28, 51][43, 29, 50][43, 28, 50][43, 29, 49][43, 28, 49][43, 29, 48][43, 28, 48]
PLL:DRP37[43, 29, 63][43, 28, 63][43, 29, 62][43, 28, 62][43, 29, 61][43, 28, 61][43, 29, 60][43, 28, 60][43, 29, 59][43, 28, 59][43, 29, 58][43, 28, 58][43, 29, 57][43, 28, 57][43, 29, 56][43, 28, 56]
PLL:DRP38[44, 29, 7][44, 28, 7][44, 29, 6][44, 28, 6][44, 29, 5][44, 28, 5][44, 29, 4][44, 28, 4][44, 29, 3][44, 28, 3][44, 29, 2][44, 28, 2][44, 29, 1][44, 28, 1][44, 29, 0][44, 28, 0]
PLL:DRP39[44, 29, 15][44, 28, 15][44, 29, 14][44, 28, 14][44, 29, 13][44, 28, 13][44, 29, 12][44, 28, 12][44, 29, 11][44, 28, 11][44, 29, 10][44, 28, 10][44, 29, 9][44, 28, 9][44, 29, 8][44, 28, 8]
PLL:DRP3A[44, 29, 23][44, 28, 23][44, 29, 22][44, 28, 22][44, 29, 21][44, 28, 21][44, 29, 20][44, 28, 20][44, 29, 19][44, 28, 19][44, 29, 18][44, 28, 18][44, 29, 17][44, 28, 17][44, 29, 16][44, 28, 16]
PLL:DRP3B[44, 29, 31][44, 28, 31][44, 29, 30][44, 28, 30][44, 29, 29][44, 28, 29][44, 29, 28][44, 28, 28][44, 29, 27][44, 28, 27][44, 29, 26][44, 28, 26][44, 29, 25][44, 28, 25][44, 29, 24][44, 28, 24]
PLL:DRP3C[44, 29, 39][44, 28, 39][44, 29, 38][44, 28, 38][44, 29, 37][44, 28, 37][44, 29, 36][44, 28, 36][44, 29, 35][44, 28, 35][44, 29, 34][44, 28, 34][44, 29, 33][44, 28, 33][44, 29, 32][44, 28, 32]
PLL:DRP3D[44, 29, 47][44, 28, 47][44, 29, 46][44, 28, 46][44, 29, 45][44, 28, 45][44, 29, 44][44, 28, 44][44, 29, 43][44, 28, 43][44, 29, 42][44, 28, 42][44, 29, 41][44, 28, 41][44, 29, 40][44, 28, 40]
PLL:DRP3E[44, 29, 55][44, 28, 55][44, 29, 54][44, 28, 54][44, 29, 53][44, 28, 53][44, 29, 52][44, 28, 52][44, 29, 51][44, 28, 51][44, 29, 50][44, 28, 50][44, 29, 49][44, 28, 49][44, 29, 48][44, 28, 48]
PLL:DRP3F[44, 29, 63][44, 28, 63][44, 29, 62][44, 28, 62][44, 29, 61][44, 28, 61][44, 29, 60][44, 28, 60][44, 29, 59][44, 28, 59][44, 29, 58][44, 28, 58][44, 29, 57][44, 28, 57][44, 29, 56][44, 28, 56]
PLL:DRP40[45, 29, 7][45, 28, 7][45, 29, 6][45, 28, 6][45, 29, 5][45, 28, 5][45, 29, 4][45, 28, 4][45, 29, 3][45, 28, 3][45, 29, 2][45, 28, 2][45, 29, 1][45, 28, 1][45, 29, 0][45, 28, 0]
PLL:DRP41[45, 29, 15][45, 28, 15][45, 29, 14][45, 28, 14][45, 29, 13][45, 28, 13][45, 29, 12][45, 28, 12][45, 29, 11][45, 28, 11][45, 29, 10][45, 28, 10][45, 29, 9][45, 28, 9][45, 29, 8][45, 28, 8]
PLL:DRP42[45, 29, 23][45, 28, 23][45, 29, 22][45, 28, 22][45, 29, 21][45, 28, 21][45, 29, 20][45, 28, 20][45, 29, 19][45, 28, 19][45, 29, 18][45, 28, 18][45, 29, 17][45, 28, 17][45, 29, 16][45, 28, 16]
PLL:DRP43[45, 29, 31][45, 28, 31][45, 29, 30][45, 28, 30][45, 29, 29][45, 28, 29][45, 29, 28][45, 28, 28][45, 29, 27][45, 28, 27][45, 29, 26][45, 28, 26][45, 29, 25][45, 28, 25][45, 29, 24][45, 28, 24]
PLL:DRP44[45, 29, 39][45, 28, 39][45, 29, 38][45, 28, 38][45, 29, 37][45, 28, 37][45, 29, 36][45, 28, 36][45, 29, 35][45, 28, 35][45, 29, 34][45, 28, 34][45, 29, 33][45, 28, 33][45, 29, 32][45, 28, 32]
PLL:DRP45[45, 29, 47][45, 28, 47][45, 29, 46][45, 28, 46][45, 29, 45][45, 28, 45][45, 29, 44][45, 28, 44][45, 29, 43][45, 28, 43][45, 29, 42][45, 28, 42][45, 29, 41][45, 28, 41][45, 29, 40][45, 28, 40]
PLL:DRP46[45, 29, 55][45, 28, 55][45, 29, 54][45, 28, 54][45, 29, 53][45, 28, 53][45, 29, 52][45, 28, 52][45, 29, 51][45, 28, 51][45, 29, 50][45, 28, 50][45, 29, 49][45, 28, 49][45, 29, 48][45, 28, 48]
PLL:DRP47[45, 29, 63][45, 28, 63][45, 29, 62][45, 28, 62][45, 29, 61][45, 28, 61][45, 29, 60][45, 28, 60][45, 29, 59][45, 28, 59][45, 29, 58][45, 28, 58][45, 29, 57][45, 28, 57][45, 29, 56][45, 28, 56]
PLL:DRP48[46, 29, 7][46, 28, 7][46, 29, 6][46, 28, 6][46, 29, 5][46, 28, 5][46, 29, 4][46, 28, 4][46, 29, 3][46, 28, 3][46, 29, 2][46, 28, 2][46, 29, 1][46, 28, 1][46, 29, 0][46, 28, 0]
PLL:DRP49[46, 29, 15][46, 28, 15][46, 29, 14][46, 28, 14][46, 29, 13][46, 28, 13][46, 29, 12][46, 28, 12][46, 29, 11][46, 28, 11][46, 29, 10][46, 28, 10][46, 29, 9][46, 28, 9][46, 29, 8][46, 28, 8]
PLL:DRP4A[46, 29, 23][46, 28, 23][46, 29, 22][46, 28, 22][46, 29, 21][46, 28, 21][46, 29, 20][46, 28, 20][46, 29, 19][46, 28, 19][46, 29, 18][46, 28, 18][46, 29, 17][46, 28, 17][46, 29, 16][46, 28, 16]
PLL:DRP4B[46, 29, 31][46, 28, 31][46, 29, 30][46, 28, 30][46, 29, 29][46, 28, 29][46, 29, 28][46, 28, 28][46, 29, 27][46, 28, 27][46, 29, 26][46, 28, 26][46, 29, 25][46, 28, 25][46, 29, 24][46, 28, 24]
PLL:DRP4C[46, 29, 39][46, 28, 39][46, 29, 38][46, 28, 38][46, 29, 37][46, 28, 37][46, 29, 36][46, 28, 36][46, 29, 35][46, 28, 35][46, 29, 34][46, 28, 34][46, 29, 33][46, 28, 33][46, 29, 32][46, 28, 32]
PLL:DRP4D[46, 29, 47][46, 28, 47][46, 29, 46][46, 28, 46][46, 29, 45][46, 28, 45][46, 29, 44][46, 28, 44][46, 29, 43][46, 28, 43][46, 29, 42][46, 28, 42][46, 29, 41][46, 28, 41][46, 29, 40][46, 28, 40]
PLL:DRP4E[46, 29, 55][46, 28, 55][46, 29, 54][46, 28, 54][46, 29, 53][46, 28, 53][46, 29, 52][46, 28, 52][46, 29, 51][46, 28, 51][46, 29, 50][46, 28, 50][46, 29, 49][46, 28, 49][46, 29, 48][46, 28, 48]
PLL:DRP4F[46, 29, 63][46, 28, 63][46, 29, 62][46, 28, 62][46, 29, 61][46, 28, 61][46, 29, 60][46, 28, 60][46, 29, 59][46, 28, 59][46, 29, 58][46, 28, 58][46, 29, 57][46, 28, 57][46, 29, 56][46, 28, 56]
PLL:DRP50[47, 29, 7][47, 28, 7][47, 29, 6][47, 28, 6][47, 29, 5][47, 28, 5][47, 29, 4][47, 28, 4][47, 29, 3][47, 28, 3][47, 29, 2][47, 28, 2][47, 29, 1][47, 28, 1][47, 29, 0][47, 28, 0]
PLL:DRP51[47, 29, 15][47, 28, 15][47, 29, 14][47, 28, 14][47, 29, 13][47, 28, 13][47, 29, 12][47, 28, 12][47, 29, 11][47, 28, 11][47, 29, 10][47, 28, 10][47, 29, 9][47, 28, 9][47, 29, 8][47, 28, 8]
PLL:DRP52[47, 29, 23][47, 28, 23][47, 29, 22][47, 28, 22][47, 29, 21][47, 28, 21][47, 29, 20][47, 28, 20][47, 29, 19][47, 28, 19][47, 29, 18][47, 28, 18][47, 29, 17][47, 28, 17][47, 29, 16][47, 28, 16]
PLL:DRP53[47, 29, 31][47, 28, 31][47, 29, 30][47, 28, 30][47, 29, 29][47, 28, 29][47, 29, 28][47, 28, 28][47, 29, 27][47, 28, 27][47, 29, 26][47, 28, 26][47, 29, 25][47, 28, 25][47, 29, 24][47, 28, 24]
PLL:DRP54[47, 29, 39][47, 28, 39][47, 29, 38][47, 28, 38][47, 29, 37][47, 28, 37][47, 29, 36][47, 28, 36][47, 29, 35][47, 28, 35][47, 29, 34][47, 28, 34][47, 29, 33][47, 28, 33][47, 29, 32][47, 28, 32]
PLL:DRP55[47, 29, 47][47, 28, 47][47, 29, 46][47, 28, 46][47, 29, 45][47, 28, 45][47, 29, 44][47, 28, 44][47, 29, 43][47, 28, 43][47, 29, 42][47, 28, 42][47, 29, 41][47, 28, 41][47, 29, 40][47, 28, 40]
PLL:DRP56[47, 29, 55][47, 28, 55][47, 29, 54][47, 28, 54][47, 29, 53][47, 28, 53][47, 29, 52][47, 28, 52][47, 29, 51][47, 28, 51][47, 29, 50][47, 28, 50][47, 29, 49][47, 28, 49][47, 29, 48][47, 28, 48]
PLL:DRP57[47, 29, 63][47, 28, 63][47, 29, 62][47, 28, 62][47, 29, 61][47, 28, 61][47, 29, 60][47, 28, 60][47, 29, 59][47, 28, 59][47, 29, 58][47, 28, 58][47, 29, 57][47, 28, 57][47, 29, 56][47, 28, 56]
PLL:DRP58[48, 29, 7][48, 28, 7][48, 29, 6][48, 28, 6][48, 29, 5][48, 28, 5][48, 29, 4][48, 28, 4][48, 29, 3][48, 28, 3][48, 29, 2][48, 28, 2][48, 29, 1][48, 28, 1][48, 29, 0][48, 28, 0]
PLL:DRP59[48, 29, 15][48, 28, 15][48, 29, 14][48, 28, 14][48, 29, 13][48, 28, 13][48, 29, 12][48, 28, 12][48, 29, 11][48, 28, 11][48, 29, 10][48, 28, 10][48, 29, 9][48, 28, 9][48, 29, 8][48, 28, 8]
PLL:DRP5A[48, 29, 23][48, 28, 23][48, 29, 22][48, 28, 22][48, 29, 21][48, 28, 21][48, 29, 20][48, 28, 20][48, 29, 19][48, 28, 19][48, 29, 18][48, 28, 18][48, 29, 17][48, 28, 17][48, 29, 16][48, 28, 16]
PLL:DRP5B[48, 29, 31][48, 28, 31][48, 29, 30][48, 28, 30][48, 29, 29][48, 28, 29][48, 29, 28][48, 28, 28][48, 29, 27][48, 28, 27][48, 29, 26][48, 28, 26][48, 29, 25][48, 28, 25][48, 29, 24][48, 28, 24]
PLL:DRP5C[48, 29, 39][48, 28, 39][48, 29, 38][48, 28, 38][48, 29, 37][48, 28, 37][48, 29, 36][48, 28, 36][48, 29, 35][48, 28, 35][48, 29, 34][48, 28, 34][48, 29, 33][48, 28, 33][48, 29, 32][48, 28, 32]
PLL:DRP5D[48, 29, 47][48, 28, 47][48, 29, 46][48, 28, 46][48, 29, 45][48, 28, 45][48, 29, 44][48, 28, 44][48, 29, 43][48, 28, 43][48, 29, 42][48, 28, 42][48, 29, 41][48, 28, 41][48, 29, 40][48, 28, 40]
PLL:DRP5E[48, 29, 55][48, 28, 55][48, 29, 54][48, 28, 54][48, 29, 53][48, 28, 53][48, 29, 52][48, 28, 52][48, 29, 51][48, 28, 51][48, 29, 50][48, 28, 50][48, 29, 49][48, 28, 49][48, 29, 48][48, 28, 48]
PLL:DRP5F[48, 29, 63][48, 28, 63][48, 29, 62][48, 28, 62][48, 29, 61][48, 28, 61][48, 29, 60][48, 28, 60][48, 29, 59][48, 28, 59][48, 29, 58][48, 28, 58][48, 29, 57][48, 28, 57][48, 29, 56][48, 28, 56]
PLL:DRP60[49, 29, 7][49, 28, 7][49, 29, 6][49, 28, 6][49, 29, 5][49, 28, 5][49, 29, 4][49, 28, 4][49, 29, 3][49, 28, 3][49, 29, 2][49, 28, 2][49, 29, 1][49, 28, 1][49, 29, 0][49, 28, 0]
PLL:DRP61[49, 29, 15][49, 28, 15][49, 29, 14][49, 28, 14][49, 29, 13][49, 28, 13][49, 29, 12][49, 28, 12][49, 29, 11][49, 28, 11][49, 29, 10][49, 28, 10][49, 29, 9][49, 28, 9][49, 29, 8][49, 28, 8]
PLL:DRP62[49, 29, 23][49, 28, 23][49, 29, 22][49, 28, 22][49, 29, 21][49, 28, 21][49, 29, 20][49, 28, 20][49, 29, 19][49, 28, 19][49, 29, 18][49, 28, 18][49, 29, 17][49, 28, 17][49, 29, 16][49, 28, 16]
PLL:DRP63[49, 29, 31][49, 28, 31][49, 29, 30][49, 28, 30][49, 29, 29][49, 28, 29][49, 29, 28][49, 28, 28][49, 29, 27][49, 28, 27][49, 29, 26][49, 28, 26][49, 29, 25][49, 28, 25][49, 29, 24][49, 28, 24]
PLL:DRP64[49, 29, 39][49, 28, 39][49, 29, 38][49, 28, 38][49, 29, 37][49, 28, 37][49, 29, 36][49, 28, 36][49, 29, 35][49, 28, 35][49, 29, 34][49, 28, 34][49, 29, 33][49, 28, 33][49, 29, 32][49, 28, 32]
PLL:DRP65[49, 29, 47][49, 28, 47][49, 29, 46][49, 28, 46][49, 29, 45][49, 28, 45][49, 29, 44][49, 28, 44][49, 29, 43][49, 28, 43][49, 29, 42][49, 28, 42][49, 29, 41][49, 28, 41][49, 29, 40][49, 28, 40]
PLL:DRP66[49, 29, 55][49, 28, 55][49, 29, 54][49, 28, 54][49, 29, 53][49, 28, 53][49, 29, 52][49, 28, 52][49, 29, 51][49, 28, 51][49, 29, 50][49, 28, 50][49, 29, 49][49, 28, 49][49, 29, 48][49, 28, 48]
PLL:DRP67[49, 29, 63][49, 28, 63][49, 29, 62][49, 28, 62][49, 29, 61][49, 28, 61][49, 29, 60][49, 28, 60][49, 29, 59][49, 28, 59][49, 29, 58][49, 28, 58][49, 29, 57][49, 28, 57][49, 29, 56][49, 28, 56]
Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
MMCM:CLKFBIN_HT[13, 28, 2][13, 29, 2][13, 28, 3][13, 29, 3][13, 28, 4][13, 29, 4]
MMCM:CLKFBIN_LT[13, 28, 5][13, 29, 5][13, 28, 6][13, 29, 6][13, 28, 7][13, 29, 7]
MMCM:CLKFBOUT_DT[13, 28, 21][13, 29, 21][13, 28, 22][13, 29, 22][13, 28, 23][13, 29, 23]
MMCM:CLKFBOUT_HT[13, 28, 26][13, 29, 26][13, 28, 27][13, 29, 27][13, 28, 28][13, 29, 28]
MMCM:CLKFBOUT_LT[13, 28, 29][13, 29, 29][13, 28, 30][13, 29, 30][13, 28, 31][13, 29, 31]
MMCM:CLKOUT0_DT[14, 28, 53][14, 29, 53][14, 28, 54][14, 29, 54][14, 28, 55][14, 29, 55]
MMCM:CLKOUT0_HT[14, 28, 58][14, 29, 58][14, 28, 59][14, 29, 59][14, 28, 60][14, 29, 60]
MMCM:CLKOUT0_LT[14, 28, 61][14, 29, 61][14, 28, 62][14, 29, 62][14, 28, 63][14, 29, 63]
MMCM:CLKOUT1_DT[14, 28, 37][14, 29, 37][14, 28, 38][14, 29, 38][14, 28, 39][14, 29, 39]
MMCM:CLKOUT1_HT[14, 28, 42][14, 29, 42][14, 28, 43][14, 29, 43][14, 28, 44][14, 29, 44]
MMCM:CLKOUT1_LT[14, 28, 45][14, 29, 45][14, 28, 46][14, 29, 46][14, 28, 47][14, 29, 47]
MMCM:CLKOUT2_DT[14, 28, 21][14, 29, 21][14, 28, 22][14, 29, 22][14, 28, 23][14, 29, 23]
MMCM:CLKOUT2_HT[14, 28, 26][14, 29, 26][14, 28, 27][14, 29, 27][14, 28, 28][14, 29, 28]
MMCM:CLKOUT2_LT[14, 28, 29][14, 29, 29][14, 28, 30][14, 29, 30][14, 28, 31][14, 29, 31]
MMCM:CLKOUT3_DT[14, 28, 5][14, 29, 5][14, 28, 6][14, 29, 6][14, 28, 7][14, 29, 7]
MMCM:CLKOUT3_HT[14, 28, 10][14, 29, 10][14, 28, 11][14, 29, 11][14, 28, 12][14, 29, 12]
MMCM:CLKOUT3_LT[14, 28, 13][14, 29, 13][14, 28, 14][14, 29, 14][14, 28, 15][14, 29, 15]
MMCM:CLKOUT4_DT[13, 28, 53][13, 29, 53][13, 28, 54][13, 29, 54][13, 28, 55][13, 29, 55]
MMCM:CLKOUT4_HT[13, 28, 58][13, 29, 58][13, 28, 59][13, 29, 59][13, 28, 60][13, 29, 60]
MMCM:CLKOUT4_LT[13, 28, 61][13, 29, 61][13, 28, 62][13, 29, 62][13, 28, 63][13, 29, 63]
MMCM:CLKOUT5_DT[15, 28, 5][15, 29, 5][15, 28, 6][15, 29, 6][15, 28, 7][15, 29, 7]
MMCM:CLKOUT5_HT[15, 28, 10][15, 29, 10][15, 28, 11][15, 29, 11][15, 28, 12][15, 29, 12]
MMCM:CLKOUT5_LT[15, 28, 13][15, 29, 13][15, 28, 14][15, 29, 14][15, 28, 15][15, 29, 15]
MMCM:CLKOUT6_DT[13, 28, 37][13, 29, 37][13, 28, 38][13, 29, 38][13, 28, 39][13, 29, 39]
MMCM:CLKOUT6_HT[13, 28, 42][13, 29, 42][13, 28, 43][13, 29, 43][13, 28, 44][13, 29, 44]
MMCM:CLKOUT6_LT[13, 28, 45][13, 29, 45][13, 28, 46][13, 29, 46][13, 28, 47][13, 29, 47]
MMCM:DIVCLK_HT[13, 28, 10][13, 29, 10][13, 28, 11][13, 29, 11][13, 28, 12][13, 29, 12]
MMCM:DIVCLK_LT[13, 28, 13][13, 29, 13][13, 28, 14][13, 29, 14][13, 28, 15][13, 29, 15]
MMCM:FINE_PS_FRAC[1, 29, 26][1, 28, 27][1, 29, 27][1, 28, 28][1, 29, 28][1, 28, 29]
MMCM:HVLF_CNT_TEST[6, 28, 26][6, 29, 27][6, 28, 28][6, 29, 29][6, 28, 30][6, 29, 31]
MMCM:IN_DLY_MX_CVDD[15, 28, 58][15, 29, 58][15, 28, 59][15, 29, 59][15, 28, 60][15, 29, 60]
MMCM:IN_DLY_MX_DVDD[15, 28, 19][15, 29, 19][15, 28, 20][15, 29, 20][15, 28, 21][15, 29, 21]
MMCM:IN_DLY_SET[15, 28, 16][15, 29, 16][15, 28, 17][15, 29, 17][15, 28, 18][15, 29, 18]
PHASER_IN0:FINE_DELAY[19, 29, 53][19, 28, 53][19, 29, 52][19, 28, 52][19, 29, 51][19, 28, 51]
PHASER_IN1:FINE_DELAY[23, 29, 21][23, 28, 21][23, 29, 20][23, 28, 20][23, 29, 19][23, 28, 19]
PHASER_IN2:FINE_DELAY[29, 29, 53][29, 28, 53][29, 29, 52][29, 28, 52][29, 29, 51][29, 28, 51]
PHASER_IN3:FINE_DELAY[33, 29, 21][33, 28, 21][33, 29, 20][33, 28, 20][33, 29, 19][33, 28, 19]
PHASER_OUT0:COARSE_DELAY[18, 28, 5][18, 29, 4][18, 28, 4][18, 29, 3][18, 28, 3][18, 29, 2]
PHASER_OUT0:FINE_DELAY[18, 28, 8][18, 29, 7][18, 28, 7][18, 29, 6][18, 28, 6][18, 29, 5]
PHASER_OUT0:OCLK_DELAY[17, 28, 28][17, 29, 27][17, 28, 27][17, 29, 26][17, 28, 26][17, 29, 25]
PHASER_OUT1:COARSE_DELAY[21, 28, 37][21, 29, 36][21, 28, 36][21, 29, 35][21, 28, 35][21, 29, 34]
PHASER_OUT1:FINE_DELAY[21, 28, 40][21, 29, 39][21, 28, 39][21, 29, 38][21, 28, 38][21, 29, 37]
PHASER_OUT1:OCLK_DELAY[20, 28, 60][20, 29, 59][20, 28, 59][20, 29, 58][20, 28, 58][20, 29, 57]
PHASER_OUT2:COARSE_DELAY[28, 28, 5][28, 29, 4][28, 28, 4][28, 29, 3][28, 28, 3][28, 29, 2]
PHASER_OUT2:FINE_DELAY[28, 28, 8][28, 29, 7][28, 28, 7][28, 29, 6][28, 28, 6][28, 29, 5]
PHASER_OUT2:OCLK_DELAY[27, 28, 28][27, 29, 27][27, 28, 27][27, 29, 26][27, 28, 26][27, 29, 25]
PHASER_OUT3:COARSE_DELAY[31, 28, 37][31, 29, 36][31, 28, 36][31, 29, 35][31, 28, 35][31, 29, 34]
PHASER_OUT3:FINE_DELAY[31, 28, 40][31, 29, 39][31, 28, 39][31, 29, 38][31, 28, 38][31, 29, 37]
PHASER_OUT3:OCLK_DELAY[30, 28, 60][30, 29, 59][30, 28, 59][30, 29, 58][30, 28, 58][30, 29, 57]
PHY_CONTROL:CMD_OFFSET[34, 29, 58][34, 28, 58][34, 29, 57][34, 28, 57][34, 29, 56][34, 28, 56]
PHY_CONTROL:EVENTS_DELAY[34, 29, 53][34, 28, 53][34, 29, 52][34, 28, 52][34, 29, 51][34, 28, 51]
PHY_CONTROL:FOUR_WINDOW_CLOCKS[34, 29, 50][34, 28, 50][34, 29, 49][34, 28, 49][34, 29, 48][34, 28, 48]
PHY_CONTROL:RD_CMD_OFFSET_0[34, 29, 5][34, 28, 5][34, 29, 4][34, 28, 4][34, 29, 3][34, 28, 3]
PHY_CONTROL:RD_CMD_OFFSET_1[34, 29, 37][34, 28, 37][34, 29, 36][34, 28, 36][34, 29, 35][34, 28, 35]
PHY_CONTROL:RD_CMD_OFFSET_2[35, 29, 5][35, 28, 5][35, 29, 4][35, 28, 4][35, 29, 3][35, 28, 3]
PHY_CONTROL:RD_CMD_OFFSET_3[35, 29, 37][35, 28, 37][35, 29, 36][35, 28, 36][35, 29, 35][35, 28, 35]
PHY_CONTROL:RD_DURATION_0[34, 29, 2][34, 28, 2][34, 29, 1][34, 28, 1][34, 29, 0][34, 28, 0]
PHY_CONTROL:RD_DURATION_1[34, 29, 34][34, 28, 34][34, 29, 33][34, 28, 33][34, 29, 32][34, 28, 32]
PHY_CONTROL:RD_DURATION_2[35, 29, 2][35, 28, 2][35, 29, 1][35, 28, 1][35, 29, 0][35, 28, 0]
PHY_CONTROL:RD_DURATION_3[35, 29, 34][35, 28, 34][35, 29, 33][35, 28, 33][35, 29, 32][35, 28, 32]
PHY_CONTROL:WR_CMD_OFFSET_0[34, 29, 11][34, 28, 11][34, 29, 10][34, 28, 10][34, 29, 9][34, 28, 9]
PHY_CONTROL:WR_CMD_OFFSET_1[34, 29, 43][34, 28, 43][34, 29, 42][34, 28, 42][34, 29, 41][34, 28, 41]
PHY_CONTROL:WR_CMD_OFFSET_2[35, 29, 11][35, 28, 11][35, 29, 10][35, 28, 10][35, 29, 9][35, 28, 9]
PHY_CONTROL:WR_CMD_OFFSET_3[35, 29, 43][35, 28, 43][35, 29, 42][35, 28, 42][35, 29, 41][35, 28, 41]
PHY_CONTROL:WR_DURATION_0[34, 29, 8][34, 28, 8][34, 29, 7][34, 28, 7][34, 29, 6][34, 28, 6]
PHY_CONTROL:WR_DURATION_1[34, 29, 40][34, 28, 40][34, 29, 39][34, 28, 39][34, 29, 38][34, 28, 38]
PHY_CONTROL:WR_DURATION_2[35, 29, 8][35, 28, 8][35, 29, 7][35, 28, 7][35, 29, 6][35, 28, 6]
PHY_CONTROL:WR_DURATION_3[35, 29, 40][35, 28, 40][35, 29, 39][35, 28, 39][35, 29, 38][35, 28, 38]
PLL:CLKFBIN_HT[39, 29, 61][39, 28, 61][39, 29, 60][39, 28, 60][39, 29, 59][39, 28, 59]
PLL:CLKFBIN_LT[39, 29, 58][39, 28, 58][39, 29, 57][39, 28, 57][39, 29, 56][39, 28, 56]
PLL:CLKFBOUT_DT[39, 29, 42][39, 28, 42][39, 29, 41][39, 28, 41][39, 29, 40][39, 28, 40]
PLL:CLKFBOUT_HT[39, 29, 37][39, 28, 37][39, 29, 36][39, 28, 36][39, 29, 35][39, 28, 35]
PLL:CLKFBOUT_LT[39, 29, 34][39, 28, 34][39, 29, 33][39, 28, 33][39, 29, 32][39, 28, 32]
PLL:CLKOUT0_DT[38, 29, 10][38, 28, 10][38, 29, 9][38, 28, 9][38, 29, 8][38, 28, 8]
PLL:CLKOUT0_HT[38, 29, 5][38, 28, 5][38, 29, 4][38, 28, 4][38, 29, 3][38, 28, 3]
PLL:CLKOUT0_LT[38, 29, 2][38, 28, 2][38, 29, 1][38, 28, 1][38, 29, 0][38, 28, 0]
PLL:CLKOUT1_DT[38, 29, 26][38, 28, 26][38, 29, 25][38, 28, 25][38, 29, 24][38, 28, 24]
PLL:CLKOUT1_HT[38, 29, 21][38, 28, 21][38, 29, 20][38, 28, 20][38, 29, 19][38, 28, 19]
PLL:CLKOUT1_LT[38, 29, 18][38, 28, 18][38, 29, 17][38, 28, 17][38, 29, 16][38, 28, 16]
PLL:CLKOUT2_DT[38, 29, 42][38, 28, 42][38, 29, 41][38, 28, 41][38, 29, 40][38, 28, 40]
PLL:CLKOUT2_HT[38, 29, 37][38, 28, 37][38, 29, 36][38, 28, 36][38, 29, 35][38, 28, 35]
PLL:CLKOUT2_LT[38, 29, 34][38, 28, 34][38, 29, 33][38, 28, 33][38, 29, 32][38, 28, 32]
PLL:CLKOUT3_DT[38, 29, 58][38, 28, 58][38, 29, 57][38, 28, 57][38, 29, 56][38, 28, 56]
PLL:CLKOUT3_HT[38, 29, 53][38, 28, 53][38, 29, 52][38, 28, 52][38, 29, 51][38, 28, 51]
PLL:CLKOUT3_LT[38, 29, 50][38, 28, 50][38, 29, 49][38, 28, 49][38, 29, 48][38, 28, 48]
PLL:CLKOUT4_DT[39, 29, 10][39, 28, 10][39, 29, 9][39, 28, 9][39, 29, 8][39, 28, 8]
PLL:CLKOUT4_HT[39, 29, 5][39, 28, 5][39, 29, 4][39, 28, 4][39, 29, 3][39, 28, 3]
PLL:CLKOUT4_LT[39, 29, 2][39, 28, 2][39, 29, 1][39, 28, 1][39, 29, 0][39, 28, 0]
PLL:CLKOUT5_DT[37, 29, 58][37, 28, 58][37, 29, 57][37, 28, 57][37, 29, 56][37, 28, 56]
PLL:CLKOUT5_HT[37, 29, 53][37, 28, 53][37, 29, 52][37, 28, 52][37, 29, 51][37, 28, 51]
PLL:CLKOUT5_LT[37, 29, 50][37, 28, 50][37, 29, 49][37, 28, 49][37, 29, 48][37, 28, 48]
PLL:DIVCLK_HT[39, 29, 53][39, 28, 53][39, 29, 52][39, 28, 52][39, 29, 51][39, 28, 51]
PLL:DIVCLK_LT[39, 29, 50][39, 28, 50][39, 29, 49][39, 28, 49][39, 29, 48][39, 28, 48]
PLL:HVLF_CNT_TEST[46, 29, 37][46, 28, 36][46, 29, 35][46, 28, 34][46, 29, 33][46, 28, 32]
PLL:IN_DLY_MX_CVDD[37, 29, 5][37, 28, 5][37, 29, 4][37, 28, 4][37, 29, 3][37, 28, 3]
PLL:IN_DLY_MX_DVDD[37, 29, 44][37, 28, 44][37, 29, 43][37, 28, 43][37, 29, 42][37, 28, 42]
PLL:IN_DLY_SET[37, 29, 47][37, 28, 47][37, 29, 46][37, 28, 46][37, 29, 45][37, 28, 45]
Non-inverted[5][4][3][2][1][0]
BUFMRCE0:ENABLE[50, 28, 27]
BUFMRCE0:INIT_OUT[50, 28, 29]
BUFMRCE1:ENABLE[50, 29, 27]
BUFMRCE1:INIT_OUT[50, 29, 29]
CMT_BOT:BUF.SYNC_BB.D[16, 28, 38]
CMT_BOT:BUF.SYNC_BB.U[16, 28, 39]
CMT_BOT:ENABLE.SYNC_BB[16, 29, 38]
CMT_BOT:ENABLE.SYNC_BB_S[16, 28, 32]
CMT_TOP:BUF.SYNC_BB.D[36, 28, 38]
CMT_TOP:BUF.SYNC_BB.U[36, 28, 39]
CMT_TOP:DRIVE.SYNC_BB[36, 28, 40]
CMT_TOP:ENABLE.SYNC_BB_N[36, 29, 38]
HCLK_CMT:ENABLE.CCIO0[24, 27, 63]
HCLK_CMT:ENABLE.CCIO1[24, 26, 63]
HCLK_CMT:ENABLE.CCIO2[24, 27, 62]
HCLK_CMT:ENABLE.CCIO3[24, 26, 62]
HCLK_CMT:ENABLE.CKINT0[50, 26, 14]
HCLK_CMT:ENABLE.CKINT1[50, 27, 14]
HCLK_CMT:ENABLE.CKINT2[50, 26, 15]
HCLK_CMT:ENABLE.CKINT3[50, 27, 15]
HCLK_CMT:ENABLE.FREQ_BB0[24, 29, 61]
HCLK_CMT:ENABLE.FREQ_BB1[24, 28, 61]
HCLK_CMT:ENABLE.FREQ_BB2[24, 29, 60]
HCLK_CMT:ENABLE.FREQ_BB3[24, 28, 60]
HCLK_CMT:ENABLE.HCLK0[50, 27, 25]
HCLK_CMT:ENABLE.HCLK1[50, 26, 25]
HCLK_CMT:ENABLE.HCLK10[50, 28, 26]
HCLK_CMT:ENABLE.HCLK11[50, 29, 26]
HCLK_CMT:ENABLE.HCLK2[50, 27, 24]
HCLK_CMT:ENABLE.HCLK3[50, 26, 24]
HCLK_CMT:ENABLE.HCLK4[50, 27, 23]
HCLK_CMT:ENABLE.HCLK5[50, 26, 23]
HCLK_CMT:ENABLE.HCLK6[50, 27, 22]
HCLK_CMT:ENABLE.HCLK7[50, 26, 22]
HCLK_CMT:ENABLE.HCLK8[50, 27, 21]
HCLK_CMT:ENABLE.HCLK9[50, 26, 21]
HCLK_CMT:ENABLE.HIN10[50, 28, 24]
HCLK_CMT:ENABLE.HIN11[50, 29, 24]
HCLK_CMT:ENABLE.HIN12[50, 28, 25]
HCLK_CMT:ENABLE.HIN13[50, 29, 25]
HCLK_CMT:ENABLE.HIN4[50, 28, 21]
HCLK_CMT:ENABLE.HIN5[50, 29, 21]
HCLK_CMT:ENABLE.HIN6[50, 28, 22]
HCLK_CMT:ENABLE.HIN7[50, 29, 22]
HCLK_CMT:ENABLE.HIN8[50, 28, 23]
HCLK_CMT:ENABLE.HIN9[50, 29, 23]
HCLK_CMT:ENABLE.RCLK0[50, 28, 14]
HCLK_CMT:ENABLE.RCLK1[50, 29, 14]
HCLK_CMT:ENABLE.RCLK2[50, 28, 15]
HCLK_CMT:ENABLE.RCLK3[50, 29, 15]
MMCM:BUF.CLKOUT0_FREQ_BB[15, 29, 51]
MMCM:BUF.CLKOUT1_FREQ_BB[15, 28, 51]
MMCM:BUF.CLKOUT2_FREQ_BB[15, 29, 50]
MMCM:BUF.CLKOUT3_FREQ_BB[15, 28, 50]
MMCM:CLKBURST_ENABLE[15, 29, 25]
MMCM:CLKBURST_REPEAT[15, 28, 25]
MMCM:CLKFBIN_EDGE[13, 28, 1]
MMCM:CLKFBIN_NOCOUNT[13, 29, 1]
MMCM:CLKFBOUT_EDGE[13, 28, 20]
MMCM:CLKFBOUT_EN[13, 29, 25]
MMCM:CLKFBOUT_FRAC_EN[13, 28, 18]
MMCM:CLKFBOUT_FRAC_WF_FALL[13, 29, 34]
MMCM:CLKFBOUT_FRAC_WF_RISE[13, 29, 18]
MMCM:CLKFBOUT_NOCOUNT[13, 29, 20]
MMCM:CLKFBOUT_USE_FINE_PS[13, 29, 19]
MMCM:CLKOUT0_EDGE[14, 28, 52]
MMCM:CLKOUT0_EN[14, 29, 57]
MMCM:CLKOUT0_FRAC_EN[14, 28, 50]
MMCM:CLKOUT0_FRAC_WF_FALL[15, 29, 2]
MMCM:CLKOUT0_FRAC_WF_RISE[14, 29, 50]
MMCM:CLKOUT0_NOCOUNT[14, 29, 52]
MMCM:CLKOUT0_USE_FINE_PS[14, 29, 51]
MMCM:CLKOUT1_EDGE[14, 28, 36]
MMCM:CLKOUT1_EN[14, 29, 41]
MMCM:CLKOUT1_NOCOUNT[14, 29, 36]
MMCM:CLKOUT1_USE_FINE_PS[14, 29, 35]
MMCM:CLKOUT2_EDGE[14, 28, 20]
MMCM:CLKOUT2_EN[14, 29, 25]
MMCM:CLKOUT2_NOCOUNT[14, 29, 20]
MMCM:CLKOUT2_USE_FINE_PS[14, 29, 19]
MMCM:CLKOUT3_EDGE[14, 28, 4]
MMCM:CLKOUT3_EN[14, 29, 9]
MMCM:CLKOUT3_NOCOUNT[14, 29, 4]
MMCM:CLKOUT3_USE_FINE_PS[14, 29, 3]
MMCM:CLKOUT4_CASCADE[13, 28, 51]
MMCM:CLKOUT4_EDGE[13, 28, 52]
MMCM:CLKOUT4_EN[13, 29, 57]
MMCM:CLKOUT4_NOCOUNT[13, 29, 52]
MMCM:CLKOUT4_USE_FINE_PS[13, 29, 51]
MMCM:CLKOUT5_EDGE[15, 28, 4]
MMCM:CLKOUT5_EN[15, 29, 9]
MMCM:CLKOUT5_NOCOUNT[15, 29, 4]
MMCM:CLKOUT5_USE_FINE_PS[15, 29, 3]
MMCM:CLKOUT6_EDGE[13, 28, 36]
MMCM:CLKOUT6_EN[13, 29, 41]
MMCM:CLKOUT6_NOCOUNT[13, 29, 36]
MMCM:CLKOUT6_USE_FINE_PS[13, 29, 35]
MMCM:CP_BIAS_TRIP_SET[6, 28, 12]
MMCM:DIRECT_PATH_CNTRL[15, 28, 22]
MMCM:DIVCLK_EDGE[13, 28, 9]
MMCM:DIVCLK_NOCOUNT[13, 29, 9]
MMCM:ENABLE.PERF0[24, 29, 38]
MMCM:ENABLE.PERF1[24, 28, 38]
MMCM:ENABLE.PERF2[24, 29, 37]
MMCM:ENABLE.PERF3[24, 28, 37]
MMCM:EN_VCO_DIV1[11, 28, 47]
MMCM:EN_VCO_DIV6[11, 29, 47]
MMCM:GTS_WAIT[1, 28, 30]
MMCM:HVLF_CNT_TEST_EN[6, 29, 25]
MMCM:INTERP_TEST[11, 29, 46]
MMCM:INV.CLKINSEL[1, 29, 45]
MMCM:INV.PSEN[1, 28, 46]
MMCM:INV.PSINCDEC[1, 29, 46]
MMCM:INV.PWRDWN[1, 28, 47]
MMCM:INV.RST[1, 29, 47]
MMCM:IN_DLY_EN[15, 29, 22]
MMCM:LF_LOW_SEL[7, 29, 39]
MMCM:MMCM_EN[1, 29, 31]
MMCM:SEL_HV_NMOS[6, 29, 50]
MMCM:SEL_LV_NMOS[12, 29, 8]
MMCM:SEL_SLIPD[12, 28, 18]
MMCM:SS_EN[1, 28, 31]
MMCM:STARTUP_WAIT[1, 29, 30]
MMCM:SUP_SEL_AREG[6, 28, 48]
MMCM:SUP_SEL_DREG[12, 28, 8]
MMCM:VLF_HIGH_DIS_B[7, 28, 44]
MMCM:VLF_HIGH_PWDN_B[7, 29, 15]
PHASER_IN0:BURST_MODE[19, 29, 26]
PHASER_IN0:DQS_AUTO_RECAL[18, 28, 49]
PHASER_IN0:DQS_BIAS_MODE[18, 29, 49]
PHASER_IN0:ENABLE.RCLK[24, 29, 36]
PHASER_IN0:EN_ISERDES_RST[18, 29, 55]
PHASER_IN0:EN_TEST_RING[19, 29, 23]
PHASER_IN0:HALF_CYCLE_ADJ[18, 28, 60]
PHASER_IN0:ICLK_TO_RCLK_BYPASS[18, 28, 56]
PHASER_IN0:INV.RST[18, 28, 59]
PHASER_IN0:PHASER_IN_EN[18, 28, 55]
PHASER_IN0:REG_OPT_1[18, 28, 50]
PHASER_IN0:REG_OPT_2[18, 29, 61]
PHASER_IN0:REG_OPT_4[18, 29, 50]
PHASER_IN0:RST_SEL[18, 28, 61]
PHASER_IN0:SEL_OUT[18, 28, 52]
PHASER_IN0:SYNC_IN_DIV_RST[19, 28, 54]
PHASER_IN0:TEST_BP[18, 29, 48]
PHASER_IN0:UPDATE_NONACTIVE[18, 28, 48]
PHASER_IN0:WR_CYCLES[18, 29, 54]
PHASER_IN1:BURST_MODE[22, 29, 58]
PHASER_IN1:DQS_AUTO_RECAL[22, 28, 17]
PHASER_IN1:DQS_BIAS_MODE[22, 29, 17]
PHASER_IN1:ENABLE.RCLK[24, 28, 36]
PHASER_IN1:EN_ISERDES_RST[22, 29, 23]
PHASER_IN1:EN_TEST_RING[22, 29, 55]
PHASER_IN1:HALF_CYCLE_ADJ[22, 28, 28]
PHASER_IN1:ICLK_TO_RCLK_BYPASS[22, 28, 24]
PHASER_IN1:INV.RST[22, 28, 27]
PHASER_IN1:PHASER_IN_EN[22, 28, 23]
PHASER_IN1:REG_OPT_1[22, 28, 18]
PHASER_IN1:REG_OPT_2[22, 29, 29]
PHASER_IN1:REG_OPT_4[22, 29, 18]
PHASER_IN1:RST_SEL[22, 28, 29]
PHASER_IN1:SEL_OUT[22, 28, 20]
PHASER_IN1:SYNC_IN_DIV_RST[23, 28, 22]
PHASER_IN1:TEST_BP[22, 29, 16]
PHASER_IN1:UPDATE_NONACTIVE[22, 28, 16]
PHASER_IN1:WR_CYCLES[22, 29, 22]
PHASER_IN2:BURST_MODE[29, 29, 26]
PHASER_IN2:DQS_AUTO_RECAL[28, 28, 49]
PHASER_IN2:DQS_BIAS_MODE[28, 29, 49]
PHASER_IN2:ENABLE.RCLK[24, 29, 35]
PHASER_IN2:EN_ISERDES_RST[28, 29, 55]
PHASER_IN2:EN_TEST_RING[29, 29, 23]
PHASER_IN2:HALF_CYCLE_ADJ[28, 28, 60]
PHASER_IN2:ICLK_TO_RCLK_BYPASS[28, 28, 56]
PHASER_IN2:INV.RST[28, 28, 59]
PHASER_IN2:PHASER_IN_EN[28, 28, 55]
PHASER_IN2:REG_OPT_1[28, 28, 50]
PHASER_IN2:REG_OPT_2[28, 29, 61]
PHASER_IN2:REG_OPT_4[28, 29, 50]
PHASER_IN2:RST_SEL[28, 28, 61]
PHASER_IN2:SEL_OUT[28, 28, 52]
PHASER_IN2:SYNC_IN_DIV_RST[29, 28, 54]
PHASER_IN2:TEST_BP[28, 29, 48]
PHASER_IN2:UPDATE_NONACTIVE[28, 28, 48]
PHASER_IN2:WR_CYCLES[28, 29, 54]
PHASER_IN3:BURST_MODE[32, 29, 58]
PHASER_IN3:DQS_AUTO_RECAL[32, 28, 17]
PHASER_IN3:DQS_BIAS_MODE[32, 29, 17]
PHASER_IN3:ENABLE.RCLK[24, 28, 35]
PHASER_IN3:EN_ISERDES_RST[32, 29, 23]
PHASER_IN3:EN_TEST_RING[32, 29, 55]
PHASER_IN3:HALF_CYCLE_ADJ[32, 28, 28]
PHASER_IN3:ICLK_TO_RCLK_BYPASS[32, 28, 24]
PHASER_IN3:INV.RST[32, 28, 27]
PHASER_IN3:PHASER_IN_EN[32, 28, 23]
PHASER_IN3:REG_OPT_1[32, 28, 18]
PHASER_IN3:REG_OPT_2[32, 29, 29]
PHASER_IN3:REG_OPT_4[32, 29, 18]
PHASER_IN3:RST_SEL[32, 28, 29]
PHASER_IN3:SEL_OUT[32, 28, 20]
PHASER_IN3:SYNC_IN_DIV_RST[33, 28, 22]
PHASER_IN3:TEST_BP[32, 29, 16]
PHASER_IN3:UPDATE_NONACTIVE[32, 28, 16]
PHASER_IN3:WR_CYCLES[32, 29, 22]
PHASER_OUT0:COARSE_BYPASS[17, 29, 23]
PHASER_OUT0:DATA_CTL_N[17, 28, 29]
PHASER_OUT0:DATA_RD_CYCLES[17, 29, 21]
PHASER_OUT0:EN_OSERDES_RST[17, 28, 23]
PHASER_OUT0:EN_TEST_RING[17, 29, 28]
PHASER_OUT0:INV.RST[18, 28, 0]
PHASER_OUT0:OCLKDELAY_INV[17, 28, 22]
PHASER_OUT0:PHASER_OUT_EN[17, 29, 22]
PHASER_OUT0:SYNC_IN_DIV_RST[18, 29, 8]
PHASER_OUT1:COARSE_BYPASS[20, 29, 55]
PHASER_OUT1:DATA_CTL_N[20, 28, 61]
PHASER_OUT1:DATA_RD_CYCLES[20, 29, 53]
PHASER_OUT1:EN_OSERDES_RST[20, 28, 55]
PHASER_OUT1:EN_TEST_RING[20, 29, 60]
PHASER_OUT1:INV.RST[21, 28, 32]
PHASER_OUT1:OCLKDELAY_INV[20, 28, 54]
PHASER_OUT1:PHASER_OUT_EN[20, 29, 54]
PHASER_OUT1:SYNC_IN_DIV_RST[21, 29, 40]
PHASER_OUT2:COARSE_BYPASS[27, 29, 23]
PHASER_OUT2:DATA_CTL_N[27, 28, 29]
PHASER_OUT2:DATA_RD_CYCLES[27, 29, 21]
PHASER_OUT2:EN_OSERDES_RST[27, 28, 23]
PHASER_OUT2:EN_TEST_RING[27, 29, 28]
PHASER_OUT2:INV.RST[28, 28, 0]
PHASER_OUT2:OCLKDELAY_INV[27, 28, 22]
PHASER_OUT2:PHASER_OUT_EN[27, 29, 22]
PHASER_OUT2:SYNC_IN_DIV_RST[28, 29, 8]
PHASER_OUT3:COARSE_BYPASS[30, 29, 55]
PHASER_OUT3:DATA_CTL_N[30, 28, 61]
PHASER_OUT3:DATA_RD_CYCLES[30, 29, 53]
PHASER_OUT3:EN_OSERDES_RST[30, 28, 55]
PHASER_OUT3:EN_TEST_RING[30, 29, 60]
PHASER_OUT3:INV.RST[31, 28, 32]
PHASER_OUT3:OCLKDELAY_INV[30, 28, 54]
PHASER_OUT3:PHASER_OUT_EN[30, 29, 54]
PHASER_OUT3:SYNC_IN_DIV_RST[31, 29, 40]
PHASER_REF:CP_BIAS_TRIP_SET[26, 29, 1]
PHASER_REF:INV.PWRDWN[26, 28, 24]
PHASER_REF:INV.RST[26, 28, 16]
PHASER_REF:PHASER_REF_EN[26, 29, 24]
PHASER_REF:SEL_SLIPD[26, 28, 3]
PHASER_REF:SUP_SEL_AREG[26, 29, 7]
PHY_CONTROL:BURST_MODE[35, 28, 46]
PHY_CONTROL:DATA_CTL_A_N[35, 28, 44]
PHY_CONTROL:DATA_CTL_B_N[35, 29, 44]
PHY_CONTROL:DATA_CTL_C_N[35, 28, 45]
PHY_CONTROL:DATA_CTL_D_N[35, 29, 45]
PHY_CONTROL:DISABLE_SEQ_MATCH[34, 28, 15]
PHY_CONTROL:MULTI_REGION[34, 28, 14]
PHY_CONTROL:PHY_COUNT_ENABLE[35, 29, 15]
PHY_CONTROL:SPARE[34, 29, 13]
PHY_CONTROL:SYNC_MODE[34, 29, 14]
PLL:BUF.CLKOUT0_FREQ_BB[37, 28, 12]
PLL:BUF.CLKOUT1_FREQ_BB[37, 29, 12]
PLL:BUF.CLKOUT2_FREQ_BB[37, 28, 13]
PLL:BUF.CLKOUT3_FREQ_BB[37, 29, 13]
PLL:CLKFBIN_EDGE[39, 29, 62]
PLL:CLKFBIN_NOCOUNT[39, 28, 62]
PLL:CLKFBOUT_EDGE[39, 29, 43]
PLL:CLKFBOUT_EN[39, 28, 38]
PLL:CLKFBOUT_NOCOUNT[39, 28, 43]
PLL:CLKOUT0_EDGE[38, 29, 11]
PLL:CLKOUT0_EN[38, 28, 6]
PLL:CLKOUT0_NOCOUNT[38, 28, 11]
PLL:CLKOUT1_EDGE[38, 29, 27]
PLL:CLKOUT1_EN[38, 28, 22]
PLL:CLKOUT1_NOCOUNT[38, 28, 27]
PLL:CLKOUT2_EDGE[38, 29, 43]
PLL:CLKOUT2_EN[38, 28, 38]
PLL:CLKOUT2_NOCOUNT[38, 28, 43]
PLL:CLKOUT3_EDGE[38, 29, 59]
PLL:CLKOUT3_EN[38, 28, 54]
PLL:CLKOUT3_NOCOUNT[38, 28, 59]
PLL:CLKOUT4_EDGE[39, 29, 11]
PLL:CLKOUT4_EN[39, 28, 6]
PLL:CLKOUT4_NOCOUNT[39, 28, 11]
PLL:CLKOUT5_EDGE[37, 29, 59]
PLL:CLKOUT5_EN[37, 28, 54]
PLL:CLKOUT5_NOCOUNT[37, 28, 59]
PLL:CP_BIAS_TRIP_SET[46, 29, 51]
PLL:DIRECT_PATH_CNTRL[37, 29, 41]
PLL:DIVCLK_EDGE[39, 29, 54]
PLL:DIVCLK_NOCOUNT[39, 28, 54]
PLL:EN_VCO_DIV1[41, 29, 16]
PLL:EN_VCO_DIV6[41, 28, 16]
PLL:GTS_WAIT[48, 29, 33]
PLL:HVLF_CNT_TEST_EN[46, 28, 38]
PLL:INV.CLKINSEL[48, 28, 18]
PLL:INV.PWRDWN[48, 29, 16]
PLL:INV.RST[48, 28, 16]
PLL:IN_DLY_EN[37, 28, 41]
PLL:LF_LOW_SEL[45, 28, 24]
PLL:PLL_EN[48, 28, 32]
PLL:SEL_HV_NMOS[46, 28, 13]
PLL:SEL_LV_NMOS[40, 28, 55]
PLL:STARTUP_WAIT[48, 28, 33]
PLL:SUP_SEL_AREG[46, 29, 15]
PLL:SUP_SEL_DREG[40, 29, 55]
PLL:VLF_HIGH_DIS_B[45, 29, 19]
PLL:VLF_HIGH_PWDN_B[45, 28, 48]
Non-inverted[0]
CMT_BOT:BUF.FREQ_BB0.D[16, 29, 45][16, 28, 54]
CMT_BOT:BUF.FREQ_BB0.U[16, 29, 53][16, 28, 46]
CMT_BOT:BUF.FREQ_BB1.D[16, 29, 46][16, 28, 55]
CMT_BOT:BUF.FREQ_BB1.U[16, 29, 54][16, 28, 47]
CMT_BOT:BUF.FREQ_BB2.D[16, 29, 47][16, 28, 56]
CMT_BOT:BUF.FREQ_BB2.U[16, 29, 55][16, 28, 48]
CMT_BOT:BUF.FREQ_BB3.D[16, 29, 48][16, 28, 57]
CMT_BOT:BUF.FREQ_BB3.U[16, 29, 56][16, 28, 49]
CMT_BOT:ENABLE.FREQ_BB0_S[16, 29, 49][16, 29, 41]
CMT_BOT:ENABLE.FREQ_BB1_S[16, 29, 50][16, 29, 42]
CMT_BOT:ENABLE.FREQ_BB2_S[16, 29, 51][16, 29, 43]
CMT_BOT:ENABLE.FREQ_BB3_S[16, 29, 52][16, 29, 44]
CMT_TOP:BUF.FREQ_BB0.D[36, 29, 45][36, 28, 54]
CMT_TOP:BUF.FREQ_BB0.U[36, 29, 53][36, 28, 46]
CMT_TOP:BUF.FREQ_BB1.D[36, 29, 46][36, 28, 55]
CMT_TOP:BUF.FREQ_BB1.U[36, 29, 54][36, 28, 47]
CMT_TOP:BUF.FREQ_BB2.D[36, 29, 47][36, 28, 56]
CMT_TOP:BUF.FREQ_BB2.U[36, 29, 55][36, 28, 48]
CMT_TOP:BUF.FREQ_BB3.D[36, 29, 48][36, 28, 57]
CMT_TOP:BUF.FREQ_BB3.U[36, 29, 56][36, 28, 49]
CMT_TOP:ENABLE.FREQ_BB0_N[36, 28, 50][36, 28, 42]
CMT_TOP:ENABLE.FREQ_BB1_N[36, 28, 51][36, 28, 43]
CMT_TOP:ENABLE.FREQ_BB2_N[36, 28, 52][36, 28, 44]
CMT_TOP:ENABLE.FREQ_BB3_N[36, 28, 53][36, 28, 45]
CMT_TOP:ENABLE.SYNC_BB[36, 29, 39][36, 28, 32]
MMCM:CLKFBOUT_MX[13, 28, 19][13, 29, 19]
MMCM:CLKOUT0_MX[14, 28, 51][14, 29, 51]
MMCM:CLKOUT1_MX[14, 28, 35][14, 29, 35]
MMCM:CLKOUT2_MX[14, 28, 19][14, 29, 19]
MMCM:CLKOUT3_MX[14, 28, 3][14, 29, 3]
MMCM:CLKOUT4_MX[13, 28, 51][13, 29, 51]
MMCM:CLKOUT5_MX[15, 28, 3][15, 29, 3]
MMCM:CLKOUT6_MX[13, 28, 35][13, 29, 35]
MMCM:CP_RES[6, 29, 13][6, 28, 14]
MMCM:EN_CURR_SINK[6, 29, 48][6, 28, 49]
MMCM:FREQ_COMP[12, 29, 39][12, 28, 40]
MMCM:LFHF[6, 28, 4][6, 29, 5]
MMCM:LF_NEN[7, 28, 40][7, 29, 41]
MMCM:LF_PEN[7, 28, 42][7, 29, 43]
MMCM:MVDD_SEL[6, 29, 49][6, 28, 50]
MMCM:SYNTH_CLK_DIV[15, 28, 47][15, 29, 47]
MMCM:TMUX_MUX_SEL[15, 28, 24][15, 29, 24]
MMCM:VREF_START[7, 29, 17][7, 28, 18]
PHASER_IN0:RD_ADDR_INIT[18, 29, 51][18, 28, 51]
PHASER_IN1:RD_ADDR_INIT[22, 29, 19][22, 28, 19]
PHASER_IN2:RD_ADDR_INIT[28, 29, 51][28, 28, 51]
PHASER_IN3:RD_ADDR_INIT[32, 29, 19][32, 28, 19]
PHASER_REF:CP_RES[26, 29, 56][26, 28, 56]
PHASER_REF:LF_NEN[26, 29, 31][26, 28, 31]
PHASER_REF:LF_PEN[26, 29, 30][26, 28, 30]
PHASER_REF:TMUX_MUX_SEL[26, 29, 2][26, 28, 2]
PLL:CLKFBOUT_MX[39, 29, 44][39, 28, 44]
PLL:CLKOUT0_MX[38, 29, 12][38, 28, 12]
PLL:CLKOUT1_MX[38, 29, 28][38, 28, 28]
PLL:CLKOUT2_MX[38, 29, 44][38, 28, 44]
PLL:CLKOUT3_MX[38, 29, 60][38, 28, 60]
PLL:CLKOUT4_MX[39, 29, 12][39, 28, 12]
PLL:CLKOUT5_MX[37, 29, 60][37, 28, 60]
PLL:CP_RES[46, 28, 50][46, 29, 49]
PLL:EN_CURR_SINK[46, 28, 15][46, 29, 14]
PLL:FREQ_COMP[40, 28, 24][40, 29, 23]
PLL:LFHF[46, 29, 59][46, 28, 58]
PLL:LF_NEN[45, 29, 23][45, 28, 22]
PLL:LF_PEN[45, 29, 21][45, 28, 20]
PLL:MVDD_SEL[46, 28, 14][46, 29, 13]
PLL:SYNTH_CLK_DIV[37, 29, 16][37, 28, 16]
PLL:TMUX_MUX_SEL[37, 29, 39][37, 28, 39]
PLL:VREF_START[45, 28, 46][45, 29, 45]
Non-inverted[1][0]
CMT_BOT:ENABLE.FREQ_BB0[16, 29, 32][16, 28, 50][16, 28, 42]
CMT_BOT:ENABLE.FREQ_BB1[16, 28, 51][16, 28, 43][16, 28, 33]
CMT_BOT:ENABLE.FREQ_BB2[16, 29, 33][16, 28, 52][16, 28, 44]
CMT_BOT:ENABLE.FREQ_BB3[16, 28, 53][16, 28, 45][16, 28, 34]
CMT_TOP:ENABLE.FREQ_BB0[36, 29, 49][36, 29, 41][36, 29, 32]
CMT_TOP:ENABLE.FREQ_BB1[36, 29, 50][36, 29, 42][36, 28, 33]
CMT_TOP:ENABLE.FREQ_BB2[36, 29, 51][36, 29, 43][36, 29, 33]
CMT_TOP:ENABLE.FREQ_BB3[36, 29, 52][36, 29, 44][36, 28, 34]
MMCM:AVDD_COMP_SET[6, 28, 43][6, 29, 43][6, 28, 44]
MMCM:AVDD_VBG_PD[6, 29, 44][6, 28, 45][6, 29, 45]
MMCM:CLKFBOUT_FRAC[13, 29, 16][13, 28, 17][13, 29, 17]
MMCM:CLKFBOUT_PM_FALL[13, 28, 33][13, 29, 33][13, 28, 34]
MMCM:CLKFBOUT_PM_RISE[13, 28, 24][13, 29, 24][13, 28, 25]
MMCM:CLKOUT0_FRAC[14, 29, 48][14, 28, 49][14, 29, 49]
MMCM:CLKOUT0_PM_FALL[15, 28, 1][15, 29, 1][15, 28, 2]
MMCM:CLKOUT0_PM_RISE[14, 28, 56][14, 29, 56][14, 28, 57]
MMCM:CLKOUT1_PM[14, 28, 40][14, 29, 40][14, 28, 41]
MMCM:CLKOUT2_PM[14, 28, 24][14, 29, 24][14, 28, 25]
MMCM:CLKOUT3_PM[14, 28, 8][14, 29, 8][14, 28, 9]
MMCM:CLKOUT4_PM[13, 28, 56][13, 29, 56][13, 28, 57]
MMCM:CLKOUT5_PM[15, 28, 8][15, 29, 8][15, 28, 9]
MMCM:CLKOUT6_PM[13, 28, 40][13, 29, 40][13, 28, 41]
MMCM:DVDD_COMP_SET[12, 28, 3][12, 29, 3][12, 28, 4]
MMCM:DVDD_VBG_PD[12, 29, 4][12, 28, 5][12, 29, 5]
MMCM:HROW_DLY_SET[15, 29, 56][15, 28, 57][15, 29, 57]
MMCM:MAN_LF[7, 29, 45][7, 28, 46][7, 29, 47]
MMCM:SS_STEPS[15, 29, 30][15, 28, 31][15, 29, 31]
MMCM:SS_STEPS_INIT[15, 28, 29][15, 29, 29][15, 28, 30]
PHASER_IN0:DQS_FIND_PATTERN[19, 28, 23][19, 29, 22][19, 28, 22]
PHASER_IN0:SEL_CLK_OFFSET[18, 29, 60][18, 28, 53][18, 29, 52]
PHASER_IN1:DQS_FIND_PATTERN[22, 28, 55][22, 29, 54][22, 28, 54]
PHASER_IN1:SEL_CLK_OFFSET[22, 29, 28][22, 28, 21][22, 29, 20]
PHASER_IN2:DQS_FIND_PATTERN[29, 28, 23][29, 29, 22][29, 28, 22]
PHASER_IN2:SEL_CLK_OFFSET[28, 29, 60][28, 28, 53][28, 29, 52]
PHASER_IN3:DQS_FIND_PATTERN[32, 28, 55][32, 29, 54][32, 28, 54]
PHASER_IN3:SEL_CLK_OFFSET[32, 29, 28][32, 28, 21][32, 29, 20]
PHASER_REF:AVDD_COMP_SET[26, 29, 63][26, 28, 63][26, 29, 62]
PHASER_REF:AVDD_VBG_PD[26, 28, 62][26, 29, 61][26, 28, 61]
PHASER_REF:MAN_LF[26, 29, 17][26, 28, 17][26, 29, 16]
PHASER_REF:PHASER_REF_MISC[26, 28, 1][26, 29, 0][26, 28, 0]
PHASER_REF:SEL_LF_HIGH[26, 28, 7][26, 29, 6][26, 28, 6]
PHY_CONTROL:CO_DURATION[35, 28, 13][35, 29, 12][35, 28, 12]
PHY_CONTROL:DI_DURATION[34, 29, 46][34, 28, 46][34, 29, 45]
PHY_CONTROL:DO_DURATION[34, 28, 13][34, 29, 12][34, 28, 12]
PLL:AVDD_COMP_SET[46, 29, 20][46, 28, 20][46, 29, 19]
PLL:AVDD_VBG_PD[46, 28, 19][46, 29, 18][46, 28, 18]
PLL:CLKFBOUT_PM[39, 29, 39][39, 28, 39][39, 29, 38]
PLL:CLKOUT0_PM[38, 29, 7][38, 28, 7][38, 29, 6]
PLL:CLKOUT1_PM[38, 29, 23][38, 28, 23][38, 29, 22]
PLL:CLKOUT2_PM[38, 29, 39][38, 28, 39][38, 29, 38]
PLL:CLKOUT3_PM[38, 29, 55][38, 28, 55][38, 29, 54]
PLL:CLKOUT4_PM[39, 29, 7][39, 28, 7][39, 29, 6]
PLL:CLKOUT5_PM[37, 29, 55][37, 28, 55][37, 29, 54]
PLL:DVDD_COMP_SET[40, 29, 60][40, 28, 60][40, 29, 59]
PLL:DVDD_VBG_PD[40, 28, 59][40, 29, 58][40, 28, 58]
PLL:HROW_DLY_SET[37, 28, 7][37, 29, 6][37, 28, 6]
PLL:MAN_LF[45, 28, 18][45, 29, 17][45, 28, 16]
Non-inverted[2][1][0]
MMCM:ANALOG_MISC[11, 29, 11][11, 28, 12][11, 29, 13][11, 28, 14]
MMCM:AVDD_VBG_SEL[6, 28, 46][6, 29, 46][6, 28, 47][6, 29, 47]
MMCM:CLKBURST_CNT[15, 28, 26][15, 29, 26][15, 28, 27][15, 29, 27]
MMCM:CP[6, 28, 8][6, 29, 9][6, 28, 10][6, 29, 11]
MMCM:DVDD_VBG_SEL[12, 28, 6][12, 29, 6][12, 28, 7][12, 29, 7]
MMCM:RES[6, 28, 0][6, 29, 1][6, 28, 2][6, 29, 3]
MMCM:SKEW_FLOP_INV[15, 28, 38][15, 29, 38][15, 28, 39][15, 29, 39]
PHASER_IN0:CLKOUT_DIV_ST[19, 28, 56][19, 29, 55][19, 28, 55][19, 29, 54]
PHASER_IN1:CLKOUT_DIV_ST[23, 28, 24][23, 29, 23][23, 28, 23][23, 29, 22]
PHASER_IN2:CLKOUT_DIV_ST[29, 28, 56][29, 29, 55][29, 28, 55][29, 29, 54]
PHASER_IN3:CLKOUT_DIV_ST[33, 28, 24][33, 29, 23][33, 28, 23][33, 29, 22]
PHASER_OUT0:CLKOUT_DIV_ST[18, 29, 10][18, 28, 10][18, 29, 9][18, 28, 9]
PHASER_OUT1:CLKOUT_DIV_ST[21, 29, 42][21, 28, 42][21, 29, 41][21, 28, 41]
PHASER_OUT2:CLKOUT_DIV_ST[28, 29, 10][28, 28, 10][28, 29, 9][28, 28, 9]
PHASER_OUT3:CLKOUT_DIV_ST[31, 29, 42][31, 28, 42][31, 29, 41][31, 28, 41]
PHASER_REF:AVDD_VBG_SEL[26, 29, 60][26, 28, 60][26, 29, 59][26, 28, 59]
PHASER_REF:CP[26, 29, 58][26, 28, 58][26, 29, 57][26, 28, 57]
PHY_CONTROL:AO_TOGGLE[34, 29, 55][34, 28, 55][34, 29, 54][34, 28, 54]
PHY_CONTROL:AO_WRLVL_EN[35, 28, 15][35, 29, 14][35, 28, 14][35, 29, 13]
PLL:ANALOG_MISC[41, 28, 52][41, 29, 51][41, 28, 50][41, 29, 49]
PLL:AVDD_VBG_SEL[46, 29, 17][46, 28, 17][46, 29, 16][46, 28, 16]
PLL:CP[46, 29, 55][46, 28, 54][46, 29, 53][46, 28, 52]
PLL:DVDD_VBG_SEL[40, 29, 57][40, 28, 57][40, 29, 56][40, 28, 56]
PLL:RES[46, 29, 63][46, 28, 62][46, 29, 61][46, 28, 60]
PLL:SKEW_FLOP_INV[37, 29, 25][37, 28, 25][37, 29, 24][37, 28, 24]
Non-inverted[3][2][1][0]
MMCM:LOCK_FB_DLY[12, 29, 48][12, 28, 49][12, 29, 49][12, 28, 50][12, 29, 50]
MMCM:LOCK_REF_DLY[12, 29, 40][12, 28, 41][12, 29, 41][12, 28, 42][12, 29, 42]
MMCM:SPARE_ANALOG[7, 29, 27][7, 28, 28][7, 29, 29][7, 28, 30][7, 29, 31]
MMCM:SPARE_DIGITAL[12, 29, 29][12, 28, 30][12, 29, 30][12, 28, 31][12, 29, 31]
PHASER_REF:LOCK_FB_DLY[26, 29, 23][26, 28, 23][26, 29, 22][26, 28, 22][26, 29, 21]
PHASER_REF:LOCK_REF_DLY[26, 29, 5][26, 28, 5][26, 29, 4][26, 28, 4][26, 29, 3]
PLL:LOCK_FB_DLY[40, 28, 15][40, 29, 14][40, 28, 14][40, 29, 13][40, 28, 13]
PLL:LOCK_REF_DLY[40, 28, 23][40, 29, 22][40, 28, 22][40, 29, 21][40, 28, 21]
PLL:SPARE_ANALOG[45, 28, 36][45, 29, 35][45, 28, 34][45, 29, 33][45, 28, 32]
PLL:SPARE_DIGITAL[40, 28, 34][40, 29, 33][40, 28, 33][40, 29, 32][40, 28, 32]
Non-inverted[4][3][2][1][0]
MMCM:INTERP_EN[10, 28, 56][10, 29, 57][10, 28, 58][10, 29, 59][10, 28, 60][10, 29, 61][10, 28, 62][10, 29, 63]
Non-inverted[7][6][5][4][3][2][1][0]
MMCM:PFD[12, 29, 18][12, 28, 19][12, 29, 19][12, 28, 20][12, 29, 20][12, 28, 21][12, 29, 21]
PHASER_REF:PFD[26, 28, 21][26, 29, 20][26, 28, 20][26, 29, 19][26, 28, 19][26, 29, 18][26, 28, 18]
PLL:PFD[40, 28, 45][40, 29, 44][40, 28, 44][40, 29, 43][40, 28, 43][40, 29, 42][40, 28, 42]
Non-inverted[6][5][4][3][2][1][0]
MMCM:LOCK_CNT[12, 28, 59][12, 29, 59][12, 28, 60][12, 29, 60][12, 28, 61][12, 29, 61][12, 28, 62][12, 29, 62][12, 28, 63][12, 29, 63]
MMCM:LOCK_SAT_HIGH[12, 28, 43][12, 29, 43][12, 28, 44][12, 29, 44][12, 28, 45][12, 29, 45][12, 28, 46][12, 29, 46][12, 28, 47][12, 29, 47]
MMCM:UNLOCK_CNT[12, 28, 51][12, 29, 51][12, 28, 52][12, 29, 52][12, 28, 53][12, 29, 53][12, 28, 54][12, 29, 54][12, 28, 55][12, 29, 55]
PHASER_REF:LOCK_CNT[26, 29, 29][26, 28, 29][26, 29, 28][26, 28, 28][26, 29, 27][26, 28, 27][26, 29, 26][26, 28, 26][26, 29, 25][26, 28, 25]
PLL:LOCK_CNT[40, 29, 4][40, 28, 4][40, 29, 3][40, 28, 3][40, 29, 2][40, 28, 2][40, 29, 1][40, 28, 1][40, 29, 0][40, 28, 0]
PLL:LOCK_SAT_HIGH[40, 29, 20][40, 28, 20][40, 29, 19][40, 28, 19][40, 29, 18][40, 28, 18][40, 29, 17][40, 28, 17][40, 29, 16][40, 28, 16]
PLL:UNLOCK_CNT[40, 29, 12][40, 28, 12][40, 29, 11][40, 28, 11][40, 29, 10][40, 28, 10][40, 29, 9][40, 28, 9][40, 29, 8][40, 28, 8]
Non-inverted[9][8][7][6][5][4][3][2][1][0]
MMCM:MUX.PERF0[15, 29, 63][15, 29, 37][15, 28, 37][15, 29, 36]
MMCM:MUX.PERF1[15, 28, 63][15, 28, 36][15, 29, 35][15, 28, 35]
MMCM:MUX.PERF2[15, 29, 62][15, 29, 34][15, 28, 34][15, 29, 33]
MMCM:MUX.PERF3[15, 28, 62][15, 28, 33][15, 29, 32][15, 28, 32]
NONE0000
CLKOUT01000
CLKFBOUT1001
CLKOUT21010
CLKOUT11100
CLKOUT31110
MMCM:MUX.CLKFBIN[15, 28, 53][15, 29, 52][15, 28, 52]
FREQ_BB0000
CLKFBIN_HCLK001
FREQ_BB2010
FREQ_BB1100
CLKFBIN_CKINT101
FREQ_BB3110
MMCM:MUX.CLKIN2[15, 28, 56][15, 29, 55][15, 28, 55]
FREQ_BB0000
CLKIN2_HCLK001
FREQ_BB2010
FREQ_BB1100
CLKIN2_CKINT101
FREQ_BB3110
MMCM:MUX.CLKIN1[15, 29, 54][15, 28, 54][15, 29, 53]
FREQ_BB0000
CLKIN1_HCLK001
FREQ_BB2010
FREQ_BB1100
CLKIN1_CKINT101
FREQ_BB3110
CMT_BOT:MUX.FREQ_BB0[16, 28, 60][16, 29, 59][16, 29, 34]
CMT_BOT:MUX.FREQ_BB1[16, 28, 61][16, 29, 60][16, 28, 35]
CMT_BOT:MUX.FREQ_BB2[16, 28, 62][16, 29, 61][16, 29, 35]
CMT_BOT:MUX.FREQ_BB3[16, 28, 63][16, 29, 62][16, 28, 36]
NONE000
MMCM_CLKOUT0001
MMCM_CLKOUT1011
MMCM_CLKOUT2101
MMCM_CLKOUT3111
PHASER_OUT0:TEST_OPT[17, 28, 21][17, 29, 20][17, 28, 20][17, 29, 19][17, 28, 19][17, 29, 18][17, 28, 18][17, 29, 17][17, 28, 17][17, 29, 16][17, 28, 16]
PHASER_OUT1:TEST_OPT[20, 28, 53][20, 29, 52][20, 28, 52][20, 29, 51][20, 28, 51][20, 29, 50][20, 28, 50][20, 29, 49][20, 28, 49][20, 29, 48][20, 28, 48]
PHASER_OUT2:TEST_OPT[27, 28, 21][27, 29, 20][27, 28, 20][27, 29, 19][27, 28, 19][27, 29, 18][27, 28, 18][27, 29, 17][27, 28, 17][27, 29, 16][27, 28, 16]
PHASER_OUT3:TEST_OPT[30, 28, 53][30, 29, 52][30, 28, 52][30, 29, 51][30, 28, 51][30, 29, 50][30, 28, 50][30, 29, 49][30, 28, 49][30, 29, 48][30, 28, 48]
Non-inverted[10][9][8][7][6][5][4][3][2][1][0]
PHASER_OUT0:OUTPUT_CLK_SRC[17, 29, 24][17, 28, 24]
PHASER_OUT1:OUTPUT_CLK_SRC[20, 29, 56][20, 28, 56]
PHASER_OUT2:OUTPUT_CLK_SRC[27, 29, 24][27, 28, 24]
PHASER_OUT3:OUTPUT_CLK_SRC[30, 29, 56][30, 28, 56]
PHASE_REF00
DELAYED_REF01
FREQ_REF10
DELAYED_PHASE_REF11
PHASER_OUT0:STG1_BYPASS[17, 28, 25]
PHASER_OUT1:STG1_BYPASS[20, 28, 57]
PHASER_OUT2:STG1_BYPASS[27, 28, 25]
PHASER_OUT3:STG1_BYPASS[30, 28, 57]
PHASE_REF0
FREQ_REF1
PHASER_IN0:CLKOUT_DIV[19, 28, 58][19, 29, 57][19, 28, 57][19, 29, 56][19, 28, 26][19, 29, 25][19, 28, 25][19, 29, 24]
PHASER_IN1:CLKOUT_DIV[23, 28, 26][23, 29, 25][23, 28, 25][23, 29, 24][22, 28, 58][22, 29, 57][22, 28, 57][22, 29, 56]
PHASER_IN2:CLKOUT_DIV[29, 28, 58][29, 29, 57][29, 28, 57][29, 29, 56][29, 28, 26][29, 29, 25][29, 28, 25][29, 29, 24]
PHASER_IN3:CLKOUT_DIV[33, 28, 26][33, 29, 25][33, 28, 25][33, 29, 24][32, 28, 58][32, 29, 57][32, 28, 57][32, 29, 56]
PHASER_OUT0:CLKOUT_DIV[18, 29, 12][18, 28, 12][18, 29, 11][18, 28, 11][17, 29, 31][17, 28, 31][17, 29, 30][17, 28, 30]
PHASER_OUT1:CLKOUT_DIV[21, 29, 44][21, 28, 44][21, 29, 43][21, 28, 43][20, 29, 63][20, 28, 63][20, 29, 62][20, 28, 62]
PHASER_OUT2:CLKOUT_DIV[28, 29, 12][28, 28, 12][28, 29, 11][28, 28, 11][27, 29, 31][27, 28, 31][27, 29, 30][27, 28, 30]
PHASER_OUT3:CLKOUT_DIV[31, 29, 44][31, 28, 44][31, 29, 43][31, 28, 43][30, 29, 63][30, 28, 63][30, 29, 62][30, 28, 62]
NONE00000000
200010000
300010001
400100010
500100011
600110100
700110101
801000110
901000111
1001011000
1101011001
1201101010
1301101011
1401111100
1501111101
1610001110
PHASER_IN0:CTL_MODE[19, 28, 24]
PHASER_IN1:CTL_MODE[22, 28, 56]
PHASER_IN2:CTL_MODE[29, 28, 24]
PHASER_IN3:CTL_MODE[32, 28, 56]
PHASER_OUT0:CTL_MODE[17, 29, 29]
PHASER_OUT1:CTL_MODE[20, 29, 61]
PHASER_OUT2:CTL_MODE[27, 29, 29]
PHASER_OUT3:CTL_MODE[30, 29, 61]
SOFT0
HARD1
PHASER_OUT0:MUX.PHASEREFCLK[18, 28, 2][18, 29, 1][18, 28, 1][18, 29, 0]
PHASER_OUT1:MUX.PHASEREFCLK[21, 28, 34][21, 29, 33][21, 28, 33][21, 29, 32]
PHASER_OUT2:MUX.PHASEREFCLK[28, 28, 2][28, 29, 1][28, 28, 1][28, 29, 0]
PHASER_OUT3:MUX.PHASEREFCLK[31, 28, 34][31, 29, 33][31, 28, 33][31, 29, 32]
NONE0000
MRCLK0_N0001
MRCLK1_N0011
MRCLK00101
MRCLK10111
MRCLK0_S1001
MRCLK1_S1011
PHASER_IN0:OUTPUT_CLK_SRC[18, 28, 57][18, 29, 56][18, 28, 54][18, 29, 53]
PHASER_IN1:OUTPUT_CLK_SRC[22, 28, 25][22, 29, 24][22, 28, 22][22, 29, 21]
PHASER_IN2:OUTPUT_CLK_SRC[28, 28, 57][28, 29, 56][28, 28, 54][28, 29, 53]
PHASER_IN3:OUTPUT_CLK_SRC[32, 28, 25][32, 29, 24][32, 28, 22][32, 29, 21]
PHASE_REF0000
FREQ_REF0010
DELAYED_REF0100
DELAYED_MEM_REF0101
MEM_REF1000
DELAYED_PHASE_REF1100
PHASER_IN0:STG1_PD_UPDATE[18, 29, 58][18, 28, 58][18, 29, 57]
PHASER_IN1:STG1_PD_UPDATE[22, 29, 26][22, 28, 26][22, 29, 25]
PHASER_IN2:STG1_PD_UPDATE[28, 29, 58][28, 28, 58][28, 29, 57]
PHASER_IN3:STG1_PD_UPDATE[32, 29, 26][32, 28, 26][32, 29, 25]
2000
3001
4010
5011
6100
7101
8110
9111
PHASER_IN0:MUX.PHASEREFCLK[19, 28, 28][19, 29, 27][19, 28, 27][18, 29, 59]
PHASER_IN1:MUX.PHASEREFCLK[22, 28, 60][22, 29, 59][22, 28, 59][22, 29, 27]
PHASER_IN2:MUX.PHASEREFCLK[29, 28, 28][29, 29, 27][29, 28, 27][28, 29, 59]
PHASER_IN3:MUX.PHASEREFCLK[32, 28, 60][32, 29, 59][32, 28, 59][32, 29, 27]
DQS_PAD0000
MRCLK0_N0001
MRCLK1_N0011
MRCLK00101
MRCLK10111
MRCLK0_S1001
MRCLK1_S1011
PHASER_IN0:PD_REVERSE[19, 28, 20][19, 29, 19][19, 28, 19]
PHASER_IN1:PD_REVERSE[22, 28, 52][22, 29, 51][22, 28, 51]
PHASER_IN2:PD_REVERSE[29, 28, 20][29, 29, 19][29, 28, 19]
PHASER_IN3:PD_REVERSE[32, 28, 52][32, 29, 51][32, 28, 51]
1000
2001
3010
4011
5100
6101
7110
8111
PHASER_IN0:FREQ_REF_DIV[19, 29, 21][19, 28, 21]
PHASER_IN1:FREQ_REF_DIV[22, 29, 53][22, 28, 53]
PHASER_IN2:FREQ_REF_DIV[29, 29, 21][29, 28, 21]
PHASER_IN3:FREQ_REF_DIV[32, 29, 53][32, 28, 53]
NONE00
DIV201
DIV410
HCLK_CMT:MUX.PHASER_REF_BOUNCE1[24, 26, 60][25, 27, 47][24, 26, 16]
NONE000
CLKOUT001
TMUXOUT010
CCIO1100
MMCM:MUX.CLKFBIN_HCLK[24, 27, 28][24, 26, 28][24, 27, 27][24, 26, 27][24, 27, 26][24, 26, 29][24, 27, 29][24, 26, 30][24, 27, 30][24, 26, 31][24, 27, 31]
MMCM:MUX.CLKIN1_HCLK[24, 28, 23][24, 29, 22][24, 28, 22][24, 29, 21][24, 28, 21][24, 29, 23][24, 28, 24][24, 29, 24][24, 28, 25][24, 29, 25][24, 28, 26]
MMCM:MUX.CLKIN2_HCLK[24, 26, 23][24, 27, 22][24, 26, 22][24, 27, 21][24, 26, 21][24, 27, 23][24, 26, 24][24, 27, 24][24, 26, 25][24, 27, 25][24, 26, 26]
PLL:MUX.CLKFBIN_HCLK[25, 26, 35][25, 27, 35][25, 26, 36][25, 27, 36][25, 26, 37][25, 27, 34][25, 26, 34][25, 27, 33][25, 26, 33][25, 27, 32][25, 26, 32]
PLL:MUX.CLKIN1_HCLK[25, 29, 40][25, 28, 41][25, 29, 41][25, 28, 42][25, 29, 42][25, 28, 40][25, 29, 39][25, 28, 39][25, 29, 38][25, 28, 38][25, 29, 37]
PLL:MUX.CLKIN2_HCLK[25, 27, 40][25, 26, 41][25, 27, 41][25, 26, 42][25, 27, 42][25, 26, 40][25, 27, 39][25, 26, 39][25, 27, 38][25, 26, 38][25, 27, 37]
NONE00000000000
HCLK000001000001
HCLK100001000010
HCLK200001000100
HCLK300001001000
HCLK400001010000
HCLK500001100000
HCLK600010000001
HCLK700010000010
HCLK800010000100
HCLK900010001000
HCLK1000010010000
HCLK1100010100000
RCLK000100000001
RCLK100100000010
RCLK200100000100
RCLK300100001000
PHASER_REF_BOUNCE000100010000
PHASER_REF_BOUNCE100100100000
HIN401000000001
HIN501000000010
HIN601000000100
HIN701000001000
PHASER_REF_BOUNCE201000010000
PHASER_REF_BOUNCE301000100000
HIN810000000001
HIN910000000010
HIN1010000000100
HIN1110000001000
HIN1210000010000
HIN1310000100000
HCLK_CMT:MUX.PHASER_REF_BOUNCE0[24, 27, 61][24, 27, 60][24, 26, 61]
NONE000
CLKOUT001
TMUXOUT010
CCIO0100
HCLK_CMT:MUX.LCLK0_CMT_D[24, 26, 17][24, 27, 16][24, 27, 17][24, 26, 18][24, 27, 18][24, 26, 19][24, 27, 19][24, 26, 20][24, 27, 20]
HCLK_CMT:MUX.LCLK0_CMT_U[25, 27, 46][25, 26, 47][25, 26, 46][25, 27, 45][25, 26, 45][25, 27, 44][25, 26, 44][25, 27, 43][25, 26, 43]
HCLK_CMT:MUX.LCLK1_CMT_D[24, 28, 17][24, 29, 16][24, 29, 17][24, 28, 18][24, 29, 18][24, 28, 19][24, 29, 19][24, 28, 20][24, 29, 20]
HCLK_CMT:MUX.LCLK1_CMT_U[25, 29, 46][25, 28, 47][25, 28, 46][25, 29, 45][25, 28, 45][25, 29, 44][25, 28, 44][25, 29, 43][25, 28, 43]
NONE000000000
RCLK0001000001
RCLK1001000010
RCLK2001000100
RCLK3001001000
HCLK0010000001
HCLK1010000010
HCLK2010000100
HCLK3010001000
HCLK4010010000
HCLK5010100000
HCLK6100000001
HCLK7100000010
HCLK8100000100
HCLK9100001000
HCLK10100010000
HCLK11100100000
HCLK_CMT:MUX.HOUT0[24, 26, 57][24, 27, 57][24, 26, 58][24, 27, 58][24, 26, 59][24, 27, 59][24, 26, 53][24, 26, 54][24, 27, 53][24, 27, 55][24, 27, 56][24, 26, 56][24, 26, 55][24, 27, 54]
HCLK_CMT:MUX.HOUT1[24, 28, 57][24, 29, 57][24, 28, 58][24, 29, 58][24, 28, 59][24, 29, 59][24, 28, 53][24, 28, 54][24, 29, 53][24, 29, 55][24, 29, 56][24, 28, 56][24, 28, 55][24, 29, 54]
HCLK_CMT:MUX.HOUT10[25, 29, 13][25, 28, 13][25, 29, 12][25, 28, 12][25, 29, 11][25, 28, 11][25, 29, 17][25, 29, 16][25, 28, 17][25, 28, 15][25, 28, 14][25, 29, 14][25, 29, 15][25, 28, 16]
HCLK_CMT:MUX.HOUT11[25, 27, 20][25, 26, 20][25, 27, 19][25, 26, 19][25, 27, 18][25, 26, 18][25, 27, 24][25, 27, 23][25, 26, 24][25, 26, 22][25, 26, 21][25, 27, 21][25, 27, 22][25, 26, 23]
HCLK_CMT:MUX.HOUT12[25, 29, 20][25, 28, 20][25, 29, 19][25, 28, 19][25, 29, 18][25, 28, 18][25, 29, 24][25, 29, 23][25, 28, 24][25, 28, 22][25, 28, 21][25, 29, 21][25, 29, 22][25, 28, 23]
HCLK_CMT:MUX.HOUT13[25, 27, 27][25, 26, 27][25, 27, 26][25, 26, 26][25, 27, 25][25, 26, 25][25, 27, 31][25, 27, 30][25, 26, 31][25, 26, 29][25, 26, 28][25, 27, 28][25, 27, 29][25, 26, 30]
HCLK_CMT:MUX.HOUT2[24, 26, 50][24, 27, 50][24, 26, 51][24, 27, 51][24, 26, 52][24, 27, 52][24, 26, 46][24, 26, 47][24, 27, 46][24, 27, 48][24, 27, 49][24, 26, 49][24, 26, 48][24, 27, 47]
HCLK_CMT:MUX.HOUT3[24, 28, 50][24, 29, 50][24, 28, 51][24, 29, 51][24, 28, 52][24, 29, 52][24, 28, 46][24, 28, 47][24, 29, 46][24, 29, 48][24, 29, 49][24, 28, 49][24, 28, 48][24, 29, 47]
HCLK_CMT:MUX.HOUT4[24, 26, 43][24, 27, 43][24, 26, 44][24, 27, 44][24, 26, 45][24, 27, 45][24, 26, 39][24, 26, 40][24, 27, 39][24, 27, 41][24, 27, 42][24, 26, 42][24, 26, 41][24, 27, 40]
HCLK_CMT:MUX.HOUT5[24, 28, 43][24, 29, 43][24, 28, 44][24, 29, 44][24, 28, 45][24, 29, 45][24, 28, 39][24, 28, 40][24, 29, 39][24, 29, 41][24, 29, 42][24, 28, 42][24, 28, 41][24, 29, 40]
HCLK_CMT:MUX.HOUT6[24, 26, 36][24, 27, 36][24, 26, 37][24, 27, 37][24, 26, 38][24, 27, 38][24, 26, 32][24, 26, 33][24, 27, 32][24, 27, 34][24, 27, 35][24, 26, 35][24, 26, 34][24, 27, 33]
HCLK_CMT:MUX.HOUT7[25, 27, 6][25, 26, 6][25, 27, 5][25, 26, 5][25, 27, 4][25, 26, 4][25, 27, 10][25, 27, 9][25, 26, 10][25, 26, 8][25, 26, 7][25, 27, 7][25, 27, 8][25, 26, 9]
HCLK_CMT:MUX.HOUT8[25, 29, 6][25, 28, 6][25, 29, 5][25, 28, 5][25, 29, 4][25, 28, 4][25, 29, 10][25, 29, 9][25, 28, 10][25, 28, 8][25, 28, 7][25, 29, 7][25, 29, 8][25, 28, 9]
HCLK_CMT:MUX.HOUT9[25, 27, 13][25, 26, 13][25, 27, 12][25, 26, 12][25, 27, 11][25, 26, 11][25, 27, 17][25, 27, 16][25, 26, 17][25, 26, 15][25, 26, 14][25, 27, 14][25, 27, 15][25, 26, 16]
NONE00000000000000
HCLK000000100000001
HCLK600000100000010
HIN400000100000100
HIN800000100001000
MMCM_CLKOUT600000100010000
PLL_CLKFBOUT00000100100000
MMCM_CLKOUT200000101000000
PLL_CLKOUT000000110000000
HCLK100001000000001
HCLK700001000000010
HIN500001000000100
HIN900001000001000
MMCM_CLKFBOUT00001000010000
PLL_TMUXOUT00001000100000
MMCM_CLKOUT2B00001001000000
PLL_CLKOUT100001010000000
HCLK200010000000001
HCLK800010000000010
HIN600010000000100
HIN1000010000001000
MMCM_CLKFBOUTB00010000010000
MMCM_CLKOUT000010000100000
MMCM_CLKOUT300010001000000
PLL_CLKOUT200010010000000
HCLK300100000000001
HCLK900100000000010
HIN700100000000100
HIN1100100000001000
MMCM_TMUXOUT00100000010000
MMCM_CLKOUT0B00100000100000
MMCM_CLKOUT3B00100001000000
PLL_CLKOUT300100010000000
HCLK401000000000001
HCLK1001000000000010
PHASER_REF_BOUNCE201000000000100
HIN1201000000001000
PHASER_REF_BOUNCE001000000010000
MMCM_CLKOUT101000000100000
MMCM_CLKOUT401000001000000
PLL_CLKOUT401000010000000
HCLK510000000000001
HCLK1110000000000010
PHASER_REF_BOUNCE310000000000100
HIN1310000000001000
PHASER_REF_BOUNCE110000000010000
MMCM_CLKOUT1B10000000100000
MMCM_CLKOUT510000001000000
PLL_CLKOUT510000010000000
HCLK_CMT:MUX.FREQ_BB3[25, 26, 3][25, 27, 3][24, 28, 62]
NONE000
CKINT3011
CCIO3101
HCLK_CMT:MUX.FREQ_BB1[25, 28, 1][25, 29, 1][24, 28, 63]
NONE000
CKINT1011
CCIO1101
HCLK_CMT:MUX.FREQ_BB2[25, 28, 0][25, 29, 0][24, 29, 62]
NONE000
CKINT2011
CCIO2101
HCLK_CMT:MUX.FREQ_BB0[25, 28, 3][25, 29, 3][24, 29, 63]
NONE000
CKINT0011
CCIO0101
BUFMRCE0:MUX.I[50, 27, 31][50, 26, 31][50, 27, 28][50, 27, 30][25, 26, 1][25, 27, 0][25, 26, 0][50, 26, 28][25, 29, 2][25, 28, 2]
NONE0000000000
CCIO00000000001
HIN40000001110
HIN50000010110
HIN60000100110
HIN70001000110
HIN80010001010
HIN90010010010
HIN100010100010
HIN110011000010
CKINT00100000110
HIN120110000010
CKINT11000000110
HIN131010000010
HCLK_CMT:MUX.PHASER_REF_BOUNCE3[25, 29, 26][25, 29, 27][25, 28, 27]
NONE000
CLKOUT001
TMUXOUT010
CCIO3100
HCLK_CMT:MUX.PHASER_REF_BOUNCE2[25, 28, 25][25, 28, 26][25, 29, 25]
NONE000
CLKOUT001
TMUXOUT010
CCIO2100
PHY_CONTROL:CLK_RATIO[34, 28, 45][34, 29, 44][34, 28, 44]
1000
2001
4010
8100
CMT_TOP:MUX.FREQ_BB0[36, 28, 60][36, 29, 59][36, 29, 34]
CMT_TOP:MUX.FREQ_BB1[36, 28, 61][36, 29, 60][36, 28, 35]
CMT_TOP:MUX.FREQ_BB2[36, 28, 62][36, 29, 61][36, 29, 35]
CMT_TOP:MUX.FREQ_BB3[36, 28, 63][36, 29, 62][36, 28, 36]
NONE000
PLL_CLKOUT0001
PLL_CLKOUT1011
PLL_CLKOUT2101
PLL_CLKOUT3111
CMT_TOP:MUX.SYNCIN[36, 28, 59][36, 29, 58][36, 28, 58]
PLL_CLKOUT2000
FREQ_BB0001
FREQ_BB1011
FREQ_BB2101
FREQ_BB3111
CMT_TOP:MUX.FREQREFCLK[36, 29, 37][36, 28, 37][36, 29, 36]
PLL_CLKOUT0000
FREQ_BB0001
FREQ_BB1011
FREQ_BB2101
FREQ_BB3111
CMT_TOP:MUX.MEMREFCLK[36, 29, 57][36, 28, 41][36, 29, 40]
PLL_CLKOUT1000
FREQ_BB0001
FREQ_BB1011
FREQ_BB2101
FREQ_BB3111
PLL:MUX.CLKIN1[37, 28, 10][37, 29, 9][37, 28, 9]
FREQ_BB0000
FREQ_BB1001
FREQ_BB2010
FREQ_BB3011
CLKIN1_HCLK100
CLKIN1_CKINT101
PLL:MUX.CLKIN2[37, 29, 8][37, 28, 8][37, 29, 7]
FREQ_BB0000
FREQ_BB1001
FREQ_BB2010
FREQ_BB3011
CLKIN2_HCLK100
CLKIN2_CKINT101
PLL:MUX.CLKFBIN[37, 29, 11][37, 28, 11][37, 29, 10]
FREQ_BB0000
FREQ_BB1001
FREQ_BB2010
FREQ_BB3011
CLKFBIN_HCLK100
CLKFBIN_CKINT101
HCLK_CMT:MUX.PERF0[50, 26, 20][50, 27, 19][50, 26, 18][50, 26, 17][50, 26, 16]
HCLK_CMT:MUX.PERF1[50, 27, 20][50, 26, 19][50, 27, 18][50, 27, 17][50, 27, 16]
NONE00000
PHASER_IN_RCLK001001
PHASER_IN_RCLK101010
PHASER_IN_RCLK201100
MMCM_PERF010001
MMCM_PERF110010
PHASER_IN_RCLK310100
BUFMRCE1:MUX.I[50, 26, 30][50, 27, 29][50, 27, 27][50, 26, 29][25, 27, 2][25, 26, 2][25, 27, 1][50, 26, 27][50, 27, 26][50, 26, 26]
NONE0000000000
CCIO30000000001
HIN40000001110
HIN50000010110
HIN60000100110
HIN70001000110
HIN80010001010
HIN90010010010
HIN100010100010
HIN110011000010
CKINT00100000110
HIN120110000010
CKINT11000000110
HIN131010000010
HCLK_CMT:MUX.PERF2[50, 28, 20][50, 29, 19][50, 28, 18][50, 28, 17][50, 28, 16]
HCLK_CMT:MUX.PERF3[50, 29, 20][50, 28, 19][50, 29, 18][50, 29, 17][50, 29, 16]
NONE00000
PHASER_IN_RCLK001001
PHASER_IN_RCLK101010
PHASER_IN_RCLK201100
MMCM_PERF210001
MMCM_PERF310010
PHASER_IN_RCLK310100
BUFMRCE0:INV.CE[50, 28, 28]
BUFMRCE1:INV.CE[50, 29, 28]
Inverted~[0]
BUFMRCE0:CE_TYPE[50, 28, 31]
BUFMRCE1:CE_TYPE[50, 29, 31]
SYNC0
ASYNC1

CMT_FIFO

CMT_FIFO bittile 0
RowColumn
CMT_FIFO bittile 1
RowColumn
CMT_FIFO bittile 2
RowColumn
CMT_FIFO bittile 3
RowColumn
CMT_FIFO bittile 4
RowColumn
CMT_FIFO bittile 5
RowColumn
CMT_FIFO bittile 6
RowColumn
0123456789101112131415161718192021222324252627
0 ----------------------------
1 --------------------------OUT_FIFO:OUTPUT_DISABLEOUT_FIFO:SPARE[0]
2 --------------------------OUT_FIFO:SPARE[1]OUT_FIFO:SPARE[2]
3 --------------------------OUT_FIFO:SLOW_WR_CLKOUT_FIFO:SYNCHRONOUS_MODE
4 --------------------------OUT_FIFO:SLOW_RD_CLKOUT_FIFO:ARRAY_MODE
5 --------------------------OUT_FIFO:SPARE[3]-
6 ----------------------------
7 ----------------------------
8 ----------------------------
9 ----------------------------
10 ----------------------------
11 ----------------------------
12 ----------------------------
13 ----------------------------
14 ----------------------------
15 ----------------------------
16 ----------------------------
17 ----------------------------
18 ----------------------------
19 ----------------------------
20 ----------------------------
21 ----------------------------
22 ----------------------------
23 ----------------------------
24 ----------------------------
25 ----------------------------
26 ----------------------------
27 ----------------------------
28 ----------------------------
29 ---------------------------OUT_FIFO:MUX.RDEN
30 --------------------------OUT_FIFO:ALMOST_FULL_VALUE[0]OUT_FIFO:ALMOST_FULL_VALUE[2]
31 ----------------------------
32 ---------------------------OUT_FIFO:ALMOST_FULL_VALUE[3]
33 --------------------------OUT_FIFO:ALMOST_FULL_VALUE[1]-
34 --------------------------OUT_FIFO:MUX.RDCLK-
35 ----------------------------
36 ----------------------------
37 ----------------------------
38 ----------------------------
39 ----------------------------
40 ----------------------------
41 ----------------------------
42 ----------------------------
43 ----------------------------
44 ----------------------------
45 ----------------------------
46 ----------------------------
47 ----------------------------
48 ----------------------------
49 ----------------------------
50 ----------------------------
51 ----------------------------
52 ----------------------------
53 ----------------------------
54 ----------------------------
55 ----------------------------
56 ----------------------------
57 ----------------------------
58 --------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[0]OUT_FIFO:ALMOST_EMPTY_VALUE[2]
59 ----------------------------
60 ---------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[3]
61 --------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[1]-
CMT_FIFO bittile 7
RowColumn
0123456789101112131415161718192021222324252627
0 ----------------------------
1 --------------------------IN_FIFO:SPARE[0]IN_FIFO:SPARE[1]
2 --------------------------IN_FIFO:SPARE[2]IN_FIFO:SLOW_WR_CLK
3 --------------------------IN_FIFO:SYNCHRONOUS_MODEIN_FIFO:SLOW_RD_CLK
4 --------------------------IN_FIFO:ARRAY_MODEIN_FIFO:SPARE[3]
5 ----------------------------
6 ----------------------------
7 ----------------------------
8 ----------------------------
9 ----------------------------
10 ----------------------------
11 ----------------------------
12 ----------------------------
13 ----------------------------
14 ----------------------------
15 ----------------------------
16 ----------------------------
17 ----------------------------
18 ----------------------------
19 ----------------------------
20 ----------------------------
21 ----------------------------
22 ----------------------------
23 ----------------------------
24 ----------------------------
25 ----------------------------
26 ----------------------------
27 ----------------------------
28 ----------------------------
29 ---------------------------IN_FIFO:MUX.WREN
30 --------------------------IN_FIFO:ALMOST_FULL_VALUE[0]IN_FIFO:ALMOST_FULL_VALUE[2]
31 ----------------------------
32 ---------------------------IN_FIFO:ALMOST_FULL_VALUE[3]
33 --------------------------IN_FIFO:ALMOST_FULL_VALUE[1]-
34 --------------------------IN_FIFO:MUX.WRCLK-
35 ----------------------------
36 ----------------------------
37 ----------------------------
38 ----------------------------
39 ----------------------------
40 ----------------------------
41 ----------------------------
42 ----------------------------
43 ----------------------------
44 ----------------------------
45 ----------------------------
46 ----------------------------
47 ----------------------------
48 ----------------------------
49 ----------------------------
50 ----------------------------
51 ----------------------------
52 ----------------------------
53 ----------------------------
54 ----------------------------
55 ----------------------------
56 ----------------------------
57 ----------------------------
58 --------------------------IN_FIFO:ALMOST_EMPTY_VALUE[0]IN_FIFO:ALMOST_EMPTY_VALUE[2]
59 ----------------------------
60 ---------------------------IN_FIFO:ALMOST_EMPTY_VALUE[3]
61 --------------------------IN_FIFO:ALMOST_EMPTY_VALUE[1]-
IN_FIFO:SLOW_RD_CLK[7, 27, 3]
IN_FIFO:SLOW_WR_CLK[7, 27, 2]
IN_FIFO:SYNCHRONOUS_MODE[7, 26, 3]
OUT_FIFO:OUTPUT_DISABLE[6, 26, 1]
OUT_FIFO:SLOW_RD_CLK[6, 26, 4]
OUT_FIFO:SLOW_WR_CLK[6, 26, 3]
OUT_FIFO:SYNCHRONOUS_MODE[6, 27, 3]
Non-inverted[0]
IN_FIFO:ALMOST_EMPTY_VALUE[7, 27, 60][7, 27, 58][7, 26, 61][7, 26, 58]
IN_FIFO:ALMOST_FULL_VALUE[7, 27, 32][7, 27, 30][7, 26, 33][7, 26, 30]
OUT_FIFO:ALMOST_EMPTY_VALUE[6, 27, 60][6, 27, 58][6, 26, 61][6, 26, 58]
OUT_FIFO:ALMOST_FULL_VALUE[6, 27, 32][6, 27, 30][6, 26, 33][6, 26, 30]
NONE0000
10011
21111
IN_FIFO:MUX.WRCLK[7, 26, 34]
IN_FIFO:MUX.WREN[7, 27, 29]
OUT_FIFO:MUX.RDCLK[6, 26, 34]
OUT_FIFO:MUX.RDEN[6, 27, 29]
INT0
PHASER1
IN_FIFO:SPARE[7, 27, 4][7, 26, 2][7, 27, 1][7, 26, 1]
OUT_FIFO:SPARE[6, 26, 5][6, 27, 2][6, 26, 2][6, 27, 1]
Non-inverted[3][2][1][0]
OUT_FIFO:ARRAY_MODE[6, 27, 4]
ARRAY_MODE_4_X_40
ARRAY_MODE_8_X_41
IN_FIFO:ARRAY_MODE[7, 26, 4]
ARRAY_MODE_4_X_40
ARRAY_MODE_4_X_81

MMCM Tables

NameMMCM:CPMMCM:RESMMCM:LFHF
HIGH:1000
HIGH:101550
HIGH:111590
HIGH:121310
HIGH:131590
HIGH:141590
HIGH:151590
HIGH:161590
HIGH:171550
HIGH:181550
HIGH:191210
HIGH:24150
HIGH:201210
HIGH:211210
HIGH:225120
HIGH:235120
HIGH:245120
HIGH:255120
HIGH:26340
HIGH:27340
HIGH:28340
HIGH:29340
HIGH:35110
HIGH:30340
HIGH:31340
HIGH:32340
HIGH:33340
HIGH:34340
HIGH:35340
HIGH:36340
HIGH:37340
HIGH:38340
HIGH:39340
HIGH:4770
HIGH:40340
HIGH:41340
HIGH:42280
HIGH:43280
HIGH:44280
HIGH:45280
HIGH:46280
HIGH:47710
HIGH:48710
HIGH:494120
HIGH:51370
HIGH:504120
HIGH:514120
HIGH:524120
HIGH:53610
HIGH:54610
HIGH:55560
HIGH:56560
HIGH:57560
HIGH:58240
HIGH:59240
HIGH:614110
HIGH:60240
HIGH:61240
HIGH:624100
HIGH:633120
HIGH:643120
HIGH:714130
HIGH:81530
HIGH:91450
LOW:1000
LOW:10250
LOW:11290
LOW:122140
LOW:132140
LOW:142140
LOW:152140
LOW:16210
LOW:17210
LOW:18210
LOW:19260
LOW:22150
LOW:20260
LOW:21260
LOW:22260
LOW:23260
LOW:24260
LOW:25260
LOW:262100
LOW:272100
LOW:282100
LOW:292100
LOW:32150
LOW:302100
LOW:312120
LOW:322120
LOW:332120
LOW:342120
LOW:352120
LOW:362120
LOW:372120
LOW:382120
LOW:392120
LOW:42150
LOW:402120
LOW:412120
LOW:422120
LOW:432120
LOW:442120
LOW:452120
LOW:462120
LOW:472120
LOW:48220
LOW:49220
LOW:5270
LOW:50220
LOW:51220
LOW:52220
LOW:53220
LOW:54220
LOW:55220
LOW:56220
LOW:57220
LOW:58220
LOW:59220
LOW:62110
LOW:60220
LOW:61220
LOW:62220
LOW:63220
LOW:64220
LOW:72130
LOW:8230
LOW:9250
SS:1000
SS:10253
SS:11293
SS:122143
SS:132143
SS:142143
SS:152143
SS:16213
SS:17213
SS:18213
SS:19263
SS:22153
SS:20263
SS:21263
SS:22263
SS:23263
SS:24263
SS:25263
SS:262103
SS:272103
SS:282103
SS:292103
SS:32153
SS:302103
SS:312123
SS:322123
SS:332123
SS:342123
SS:352123
SS:362123
SS:372123
SS:382123
SS:392123
SS:42153
SS:402123
SS:412123
SS:422123
SS:432123
SS:442123
SS:452123
SS:462123
SS:472123
SS:48223
SS:49223
SS:5273
SS:50223
SS:51223
SS:52223
SS:53223
SS:54223
SS:55223
SS:56223
SS:57223
SS:58223
SS:59223
SS:62113
SS:60223
SS:61223
SS:62223
SS:63223
SS:64223
SS:72133
SS:8233
SS:9253
NameMMCM:LOCK_REF_DLYMMCM:LOCK_FB_DLYMMCM:LOCK_CNTMMCM:LOCK_SAT_HIGHMMCM:UNLOCK_CNT
166100010011
102828100010011
11313190010011
12313182510011
13313175010011
14313170010011
15313165010011
16313162510011
17313157510011
18313155010011
19313152510011
266100010011
20313150010011
21313147510011
22313145010011
23313142510011
24313140010011
25313140010011
26313137510011
27313135010011
28313135010011
29313132510011
388100010011
30313132510011
31313130010011
32313130010011
33313130010011
34313127510011
35313127510011
36313127510011
37313125010011
38313125010011
39313125010011
41111100010011
40313125010011
41313125010011
42313125010011
43313125010011
44313125010011
45313125010011
46313125010011
47313125010011
48313125010011
49313125010011
51414100010011
50313125010011
51313125010011
52313125010011
53313125010011
54313125010011
55313125010011
56313125010011
57313125010011
58313125010011
59313125010011
61717100010011
60313125010011
61313125010011
62313125010011
63313125010011
64313125010011
71919100010011
82222100010011
92525100010011

PLL Tables

NamePLL:CPPLL:RESPLL:LFHF
HIGH:1000
HIGH:101570
HIGH:1115110
HIGH:1215130
HIGH:131530
HIGH:141450
HIGH:151550
HIGH:161550
HIGH:171550
HIGH:181550
HIGH:19760
HIGH:2370
HIGH:20760
HIGH:21760
HIGH:22760
HIGH:235120
HIGH:245120
HIGH:255120
HIGH:261210
HIGH:271210
HIGH:281210
HIGH:291210
HIGH:35150
HIGH:301210
HIGH:311210
HIGH:321210
HIGH:331210
HIGH:34420
HIGH:35420
HIGH:36420
HIGH:37280
HIGH:38280
HIGH:39280
HIGH:47150
HIGH:40340
HIGH:41280
HIGH:42280
HIGH:43280
HIGH:44280
HIGH:45280
HIGH:46280
HIGH:47280
HIGH:48280
HIGH:49280
HIGH:57110
HIGH:50280
HIGH:51280
HIGH:52280
HIGH:53280
HIGH:544120
HIGH:554120
HIGH:564120
HIGH:574120
HIGH:584120
HIGH:594120
HIGH:61370
HIGH:604120
HIGH:61240
HIGH:62240
HIGH:63240
HIGH:64240
HIGH:714110
HIGH:814130
HIGH:915130
LOW:1000
LOW:10210
LOW:11210
LOW:12260
LOW:13260
LOW:14260
LOW:15260
LOW:162100
LOW:172100
LOW:182100
LOW:192100
LOW:22150
LOW:202120
LOW:212120
LOW:222120
LOW:232120
LOW:242120
LOW:252120
LOW:262120
LOW:272120
LOW:282120
LOW:292120
LOW:3270
LOW:302120
LOW:31220
LOW:32220
LOW:33220
LOW:34220
LOW:35220
LOW:36220
LOW:37220
LOW:38220
LOW:39220
LOW:42130
LOW:40220
LOW:413120
LOW:423120
LOW:433120
LOW:443120
LOW:453120
LOW:463120
LOW:473120
LOW:48240
LOW:49240
LOW:5250
LOW:50240
LOW:51240
LOW:52240
LOW:53240
LOW:54240
LOW:55240
LOW:56240
LOW:57240
LOW:58240
LOW:59240
LOW:6250
LOW:60240
LOW:61240
LOW:62240
LOW:63240
LOW:64240
LOW:7290
LOW:82140
LOW:92140
NamePLL:LOCK_REF_DLYPLL:LOCK_FB_DLYPLL:LOCK_CNTPLL:LOCK_SAT_HIGHPLL:UNLOCK_CNT
166100010011
102828100010011
11313190010011
12313182510011
13313175010011
14313170010011
15313165010011
16313162510011
17313157510011
18313155010011
19313152510011
266100010011
20313150010011
21313147510011
22313145010011
23313142510011
24313140010011
25313140010011
26313137510011
27313135010011
28313135010011
29313132510011
388100010011
30313132510011
31313130010011
32313130010011
33313130010011
34313127510011
35313127510011
36313127510011
37313125010011
38313125010011
39313125010011
41111100010011
40313125010011
41313125010011
42313125010011
43313125010011
44313125010011
45313125010011
46313125010011
47313125010011
48313125010011
49313125010011
51414100010011
50313125010011
51313125010011
52313125010011
53313125010011
54313125010011
55313125010011
56313125010011
57313125010011
58313125010011
59313125010011
61717100010011
60313125010011
61313125010011
62313125010011
63313125010011
64313125010011
71919100010011
82222100010011
92525100010011