Input/Output
I/O banks and special functions
Virtex 7 devices have a regular I/O bank structure. There are up to two I/O columns in the device: the left I/O column and the right I/O column. They contain one I/O bank per region (with the exception of regions that are covered up by the PS or GT holes).
There are two genders of I/O banks:
HP (high performance) banks, with 1.8V maximum voltage and DCI support
HR (high range) banks, with 3.3V maxumum voltage and no DCI
In both cases, banks are 50 rows high. They have the following structure:
row 0: contains a
IOS_HPorIOS_HRtile with a single unpaired IOBrows 1-2, 3-4, 5-6, 7-8, …, 45-46, 47-48: contain
IOP_HPorIOP_HRtiles, which are two rows high and contain two IOBs each, forming a differential pair;IOB0is located in the bottom (odd) row and is the “complemented” pin of the pair, whileIOB1is in the top (even) row and is the “true” pin of the pairrow 49: contains another
IOS_HPorIOS_HRtileHCLK row: contains an
HCLK_IO_HPorHCLK_IO_HRtile with common bank circuitry
The single IOB in row 0 is the VRP pin for DCI. The single IOB in row 49 is VRN pin.
The IOB1 pads in rows 24 and 26 are considered “multi-region clock capable”, and have dedicated routing to BUFIO and BUFR of this region and the two adjacent ones. The IOB1 pads in rows 22 and 28 are considered “single-region clock capable”, and can drive BUFIO and BUFR only within their own region.
The IOB0 pads in rows 11 and 37 can be used as VREF.
The IOB1 pads in rows 8, 20, 32, 44 can be used as DQS for byte groups. The byte groups are:
rows 1-12: byte group with DQS in row 8
rows 13-24: byte group with DQS in row 20
rows 25-36: byte group with DQS in row 32
rows 37-48: byte group with DQS in row 44
The banks are numbered as follows, where c is the region with the CFG tile (for multi-die packages, the CFG tile of the primary device):
the bank in left column region
c + iis14 + ithe bank in right column region
c + iis34 + i
In case of multi-die packages, this numbering continues across devices within the package.
In parallel or SPI configuration modes, some I/O pads in banks 14 and 15 are borrowed for configuration use:
bank 14 row 1:
A[0]/D[16]bank 14 row 2:
A[1]/D[17]bank 14 row 3:
A[2]/D[18]bank 14 row 4:
A[3]/D[19]bank 14 row 5:
A[4]/D[20]bank 14 row 6:
A[5]/D[21]bank 14 row 7:
A[6]/D[22]bank 14 row 9:
A[7]/D[23]bank 14 row 10:
A[8]/D[24]bank 14 row 11:
A[9]/D[25]bank 14 row 12:
A[10]/D[26]bank 14 row 13:
A[11]/D[27]bank 14 row 14:
A[12]/D[28]bank 14 row 15:
A[13]/D[29]bank 14 row 16:
A[14]/D[30]bank 14 row 17:
A[15]/D[31]bank 14 row 18:
CSI_Bbank 14 row 19:
DOUT/CSO_Bbank 14 row 20:
RDWR_Bbank 14 row 29:
D[15]bank 14 row 30:
D[14]bank 14 row 31:
D[13]bank 14 row 33:
D[12]bank 14 row 34:
D[11]bank 14 row 36:
D[10]bank 14 row 36:
D[9]bank 14 row 37:
D[8]bank 14 row 38:
FCS_Bbank 14 row 39:
D[7]bank 14 row 40:
D[6]bank 14 row 41:
D[5]bank 14 row 42:
D[4]bank 14 row 43:
EM_CCLKbank 14 row 44:
PUDC_Bbank 14 row 45:
D[3]bank 14 row 46:
D[2]bank 14 row 47:
D[1]/DINbank 14 row 48:
D[0]/MOSIbank 15 row 1:
RS[0]bank 15 row 2:
RS[1]bank 15 row 3:
FWE_Bbank 15 row 4:
FOE_Bbank 15 row 5:
A[16]bank 15 row 6:
A[17]bank 15 row 7:
A[18]bank 15 row 9:
A[19]bank 15 row 10:
A[20]bank 15 row 11:
A[21]bank 15 row 12:
A[22]bank 15 row 13:
A[23]bank 15 row 14:
A[24]bank 15 row 15:
A[25]bank 15 row 16:
A[26]bank 15 row 17:
A[27]bank 15 row 18:
A[28]bank 15 row 19:
ADV_B
Some
The devices with Processing System are not configured by normal means, so the above list is inapplicable. Furthermore, they do not have banks 14 and 15 at all — the place they would occupy is taken up by the PS itself. They do, however, have a special pin in bank 34 instead:
bank 34 row 44:
PUDC_B
Todo
really, Wanda, how surprised would you be if it turned out that they are configurable by normal means by just substituting banks 34+35 and poking at the reserved mode pins that definitely aren’t M0/M1/M2?
The XADC, if present on the device, can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. Depending on device banks present on the device, there are three different arrangements possible:
variant LR, used for devices that have both bank 15 and 35
variant L, used for devices without bank 35
variant R, used for devices without bank 15 (that is, devices with Processing System)
The IOBs for variant LR are:
VP0/VN0: bank 15 rows 47-48VP1/VN1: bank 15 rows 43-44VP2/VN2: bank 15 rows 35-36VP3/VN3: bank 15 rows 31-32VP4/VN4: bank 35 rows 47-48VP5/VN5: bank 35 rows 43-44VP6/VN6: bank 35 rows 35-31VP7/VN7: bank 35 rows 31-32VP8/VN8: bank 15 rows 45-46VP9/VN9: bank 15 rows 39-40VP10/VN10: bank 15 rows 33-34VP11/VN11: bank 15 rows 29-30VP12/VN12: bank 35 rows 45-46VP13/VN13: bank 35 rows 39-40VP14/VN14: bank 35 rows 33-34VP15/VN15: bank 35 rows 29-30
The IOBs for variant L are:
VP0/VN0: bank 15 rows 47-48VP1/VN1: bank 15 rows 43-44VP2/VN2: bank 15 rows 39-40VP3/VN3: bank 15 rows 33-34VP4/VN4: bank 15 rows 29-30VP5/VN5: bank 15 rows 25-26VP6/VN6: unconnectedVP7/VN7: unconnectedVP8/VN8: bank 15 rows 45-46VP9/VN9: bank 15 rows 41-42VP10/VN10: bank 15 rows 35-36VP11/VN11: bank 15 rows 31-32VP12/VN12: bank 15 rows 27-28VP13/VN13: unconnectedVP14/VN14: unconnectedVP15/VN15: unconnected
The IOBs for variant R are:
VP0/VN0: bank 35 rows 47-48VP1/VN1: bank 35 rows 43-44VP2/VN2: bank 35 rows 35-36VP3/VN3: bank 35 rows 31-32VP4/VN4: bank 35 rows 21-22VP5/VN5: bank 35 rows 15-16VP6/VN6: bank 35 rows 9-10VP7/VN7: bank 35 rows 5-6VP8/VN8: bank 35 rows 45-46VP9/VN9: bank 35 rows 39-40VP10/VN10: bank 35 rows 33-34VP11/VN11: bank 35 rows 29-30VP12/VN12: bank 35 rows 19-20VP13/VN13: bank 35 rows 13-14VP14/VN14: bank 35 rows 7-8VP15/VN15: bank 35 rows 1-2
The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:
CCLKCFGBVSDONEINIT_BM0,M1,M2PROGRAM_BTCK,TDI,TDO,TMS