Input/Output

I/O banks and special functions

Virtex 7 devices have a regular I/O bank structure. There are up to two I/O columns in the device: the left I/O column and the right I/O column. They contain one I/O bank per region (with the exception of regions that are covered up by the PS or GT holes).

There are two genders of I/O banks:

  • HP (high performance) banks, with 1.8V maximum voltage and DCI support

  • HR (high range) banks, with 3.3V maximum voltage and no DCI

In both cases, banks are 50 rows high. They have the following structure:

  • row 0: contains a IO_HP_BOT or IO_HR_BOT tile with a single unpaired IOB

  • rows 1-2, 3-4, 5-6, 7-8, …, 45-46, 47-48: contain IO_HP_PAIR or IO_HR_PAIR tiles, which are two rows high and contain two IOBs each, forming a differential pair; IOB0 is located in the bottom (odd) row and is the “complemented” pin of the pair, while IOB1 is in the top (even) row and is the “true” pin of the pair

  • row 49: contains another IO_HP_TOP or IO_HR_TOP tile

  • HCLK row: contains an HCLK_IO_HP or HCLK_IO_HR tile with common bank circuitry

The single IOB in row 0 is the VRP pin for DCI. The single IOB in row 49 is VRN pin.

The IOB1 pads in rows 24 and 26 are considered “multi-region clock capable”, and have dedicated routing to BUFIO and BUFR of this region and the two adjacent ones. The IOB1 pads in rows 22 and 28 are considered “single-region clock capable”, and can drive BUFIO and BUFR only within their own region.

The IOB0 pads in rows 11 and 37 can be used as VREF.

The IOB1 pads in rows 8, 20, 32, 44 can be used as DQS for byte groups. The byte groups are:

  • rows 1-12: byte group with DQS in row 8

  • rows 13-24: byte group with DQS in row 20

  • rows 25-36: byte group with DQS in row 32

  • rows 37-48: byte group with DQS in row 44

The banks are numbered as follows, where c is the region with the CFG tile (for multi-die packages, the CFG tile of the primary device):

  • the bank in left column region c + i is 14 + i

  • the bank in right column region c + i is 34 + i

In case of multi-die packages, this numbering continues across devices within the package.

In parallel or SPI configuration modes, some I/O pads in banks 14 and 15 are borrowed for configuration use:

  • bank 14 row 1: A[0]/D[16]

  • bank 14 row 2: A[1]/D[17]

  • bank 14 row 3: A[2]/D[18]

  • bank 14 row 4: A[3]/D[19]

  • bank 14 row 5: A[4]/D[20]

  • bank 14 row 6: A[5]/D[21]

  • bank 14 row 7: A[6]/D[22]

  • bank 14 row 9: A[7]/D[23]

  • bank 14 row 10: A[8]/D[24]

  • bank 14 row 11: A[9]/D[25]

  • bank 14 row 12: A[10]/D[26]

  • bank 14 row 13: A[11]/D[27]

  • bank 14 row 14: A[12]/D[28]

  • bank 14 row 15: A[13]/D[29]

  • bank 14 row 16: A[14]/D[30]

  • bank 14 row 17: A[15]/D[31]

  • bank 14 row 18: CSI_B

  • bank 14 row 19: DOUT/CSO_B

  • bank 14 row 20: RDWR_B

  • bank 14 row 29: D[15]

  • bank 14 row 30: D[14]

  • bank 14 row 31: D[13]

  • bank 14 row 33: D[12]

  • bank 14 row 34: D[11]

  • bank 14 row 36: D[10]

  • bank 14 row 36: D[9]

  • bank 14 row 37: D[8]

  • bank 14 row 38: FCS_B

  • bank 14 row 39: D[7]

  • bank 14 row 40: D[6]

  • bank 14 row 41: D[5]

  • bank 14 row 42: D[4]

  • bank 14 row 43: EM_CCLK

  • bank 14 row 44: PUDC_B

  • bank 14 row 45: D[3]

  • bank 14 row 46: D[2]

  • bank 14 row 47: D[1]/DIN

  • bank 14 row 48: D[0]/MOSI

  • bank 15 row 1: RS[0]

  • bank 15 row 2: RS[1]

  • bank 15 row 3: FWE_B

  • bank 15 row 4: FOE_B

  • bank 15 row 5: A[16]

  • bank 15 row 6: A[17]

  • bank 15 row 7: A[18]

  • bank 15 row 9: A[19]

  • bank 15 row 10: A[20]

  • bank 15 row 11: A[21]

  • bank 15 row 12: A[22]

  • bank 15 row 13: A[23]

  • bank 15 row 14: A[24]

  • bank 15 row 15: A[25]

  • bank 15 row 16: A[26]

  • bank 15 row 17: A[27]

  • bank 15 row 18: A[28]

  • bank 15 row 19: ADV_B

Some

The devices with Processing System are not configured by normal means, so the above list is inapplicable. Furthermore, they do not have banks 14 and 15 at all — the place they would occupy is taken up by the PS itself. They do, however, have a special pin in bank 34 instead:

  • bank 34 row 44: PUDC_B

Todo

really, Wanda, how surprised would you be if it turned out that they are configurable by normal means by just substituting banks 34+35 and poking at the reserved mode pins that definitely aren’t M0/M1/M2?

The XADC, if present on the device, can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. Depending on device banks present on the device, there are three different arrangements possible:

  • variant LR, used for devices that have both bank 15 and 35

  • variant L, used for devices without bank 35

  • variant R, used for devices without bank 15 (that is, devices with Processing System)

The IOBs for variant LR are:

  • VP0/VN0: bank 15 rows 47-48

  • VP1/VN1: bank 15 rows 43-44

  • VP2/VN2: bank 15 rows 35-36

  • VP3/VN3: bank 15 rows 31-32

  • VP4/VN4: bank 35 rows 47-48

  • VP5/VN5: bank 35 rows 43-44

  • VP6/VN6: bank 35 rows 35-31

  • VP7/VN7: bank 35 rows 31-32

  • VP8/VN8: bank 15 rows 45-46

  • VP9/VN9: bank 15 rows 39-40

  • VP10/VN10: bank 15 rows 33-34

  • VP11/VN11: bank 15 rows 29-30

  • VP12/VN12: bank 35 rows 45-46

  • VP13/VN13: bank 35 rows 39-40

  • VP14/VN14: bank 35 rows 33-34

  • VP15/VN15: bank 35 rows 29-30

The IOBs for variant L are:

  • VP0/VN0: bank 15 rows 47-48

  • VP1/VN1: bank 15 rows 43-44

  • VP2/VN2: bank 15 rows 39-40

  • VP3/VN3: bank 15 rows 33-34

  • VP4/VN4: bank 15 rows 29-30

  • VP5/VN5: bank 15 rows 25-26

  • VP6/VN6: unconnected

  • VP7/VN7: unconnected

  • VP8/VN8: bank 15 rows 45-46

  • VP9/VN9: bank 15 rows 41-42

  • VP10/VN10: bank 15 rows 35-36

  • VP11/VN11: bank 15 rows 31-32

  • VP12/VN12: bank 15 rows 27-28

  • VP13/VN13: unconnected

  • VP14/VN14: unconnected

  • VP15/VN15: unconnected

The IOBs for variant R are:

  • VP0/VN0: bank 35 rows 47-48

  • VP1/VN1: bank 35 rows 43-44

  • VP2/VN2: bank 35 rows 35-36

  • VP3/VN3: bank 35 rows 31-32

  • VP4/VN4: bank 35 rows 21-22

  • VP5/VN5: bank 35 rows 15-16

  • VP6/VN6: bank 35 rows 9-10

  • VP7/VN7: bank 35 rows 5-6

  • VP8/VN8: bank 35 rows 45-46

  • VP9/VN9: bank 35 rows 39-40

  • VP10/VN10: bank 35 rows 33-34

  • VP11/VN11: bank 35 rows 29-30

  • VP12/VN12: bank 35 rows 19-20

  • VP13/VN13: bank 35 rows 13-14

  • VP14/VN14: bank 35 rows 7-8

  • VP15/VN15: bank 35 rows 1-2

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

  • CCLK

  • CFGBVS

  • DONE

  • INIT_B

  • M0, M1, M2

  • PROGRAM_B

  • TCK, TDI, TDO, TMS

Bitstream — IO_HP_PAIR

IO_HP_PAIR bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC0:DYN_CLK_INV_EN--OLOGIC0:DATA_WIDTH[0]------IOB0:IBUF_MODE[0]-
1 ----------------------------OLOGIC0:MUX.CLKDIVF[1]~ILOGIC0:INV.CLK[2]OLOGIC0:DATA_WIDTH[1]OLOGIC0:MUX.CLKDIVFB[1]-------IOB0:IBUF_MODE[1]
2 ----------------------------~ILOGIC0:INV.CLK[0]OLOGIC0:MUX.CLKDIVF[3]OLOGIC0:MUX.CLKDIVFB[3]OLOGIC0:INV.D8------IOB0:IBUF_MODE[2]-
3 ----------------------------OLOGIC0:MUX.CLKDIVF[0]ILOGIC0:INV.OCLK2OLOGIC0:DATA_WIDTH[2]OLOGIC0:MUX.CLKDIVFB[0]-------IOB0:IBUF_MODE[3]
4 ----------------------------~ILOGIC0:INV.CLK[1]OLOGIC0:MUX.CLKDIVF[2]OLOGIC0:MUX.CLKDIVFB[2]OLOGIC0:DATA_WIDTH[5]------IOB0:PULL[2]-
5 ------------------------------OLOGIC0:MISR_CLK_SELECT[1]----IDELAY0:IDELAY_VALUE_INIT[0]-ODELAY0:ODELAY_VALUE_INIT[0]-IOB0:INPUT_MISC
6 ---------------------------ILOGIC0:INTERFACE_TYPE[0]-OLOGIC0:MUX.CLKDIVF[6]OLOGIC0:MUX.CLKDIVFB[6]OLOGIC0:DATA_WIDTH[3]------IOB0:PULL_DYNAMIC-
7 ------------------------------OLOGIC0:DATA_WIDTH[4]----~IDELAY0:IDELAY_VALUE_CUR[0]-~ODELAY0:ODELAY_VALUE_CUR[0]--
8 ---------------------------ILOGIC0:INV.CLKDIV-OLOGIC0:MUX.CLKDIVF[5]OLOGIC0:MUX.CLKDIVFB[5]OLOGIC0:MISR_RESET--IDELAY0:IDELAY_TYPE[0]-ODELAY0:ODELAY_TYPE[0]-IOB0:LVDS[0]-
9 --------------------------ILOGIC0:DYN_CLKDIV_INV_EN-OLOGIC0:MUX.CLKDIVF[4]-OLOGIC0:INV.D7OLOGIC0:MUX.CLKDIVFB[4]-------IOB0:OUTPUT_MISC[2]
10 ---------------------------ILOGIC0:INTERFACE_TYPE[2]---OLOGIC0:MISR_ENABLE_FDBK------IOB0:PULL[1]-
11 --------------------------ILOGIC0:DYN_CLKDIVP_INV_EN--ILOGIC0:IFF_DELAY_ENABLEOLOGIC0:DATA_WIDTH[6]----IDELAY0:IDELAY_VALUE_INIT[1]-ODELAY0:ODELAY_VALUE_INIT[1]-IOB0:OUTPUT_MISC[4]
12 ---------------------------ILOGIC0:INTERFACE_TYPE[4]---OLOGIC0:DATA_WIDTH[7]------IOB0:PULL[0]-
13 --------------------------ILOGIC0:INV.CLKDIVP---OLOGIC0:INV.D6----~IDELAY0:IDELAY_VALUE_CUR[1]-~ODELAY0:ODELAY_VALUE_CUR[1]-IOB0:PSLEW[4]
14 ---------------------------ILOGIC0:INTERFACE_TYPE[3]ILOGIC0:IFF_TSBYPASS_ENABLE--OLOGIC0:INV.D5OLOGIC0:OMUX[3]-IDELAY0:IDELAY_TYPE[1]-ODELAY0:ODELAY_TYPE[1]-IOB0:NSLEW[4]-
15 --------------------------ILOGIC0:DATA_WIDTH[0]---OLOGIC0:MISR_CLK_SELECT[0]--OLOGIC0:OFF_SR_USED-----IOB0:LVDS[1]
16 ---------------------------ILOGIC0:DATA_WIDTH[1]-OLOGIC0:MUX.CLKDIV[0]OLOGIC0:MUX.CLKDIVB[0]OLOGIC0:MISR_ENABLEOLOGIC0:OMUX[0]-----IOB0:PSLEW[3]-
17 --------------------------ILOGIC0:DATA_WIDTH[2]-OLOGIC0:MUX.CLKDIV[1]ILOGIC0:TSBYPASS_MUXOLOGIC0:INV.D4OLOGIC0:MUX.CLKDIVB[1]-OLOGIC0:OMUX[4]-IDELAY0:IDELAY_VALUE_INIT[2]-ODELAY0:ODELAY_VALUE_INIT[2]-IOB0:TMUX
18 ---------------------------ILOGIC0:DATA_WIDTH[3]~ILOGIC0:INV.D----IDELAY0:HIGH_PERFORMANCE_MODE-ODELAY0:HIGH_PERFORMANCE_MODE----
19 --------------------------ILOGIC0:DATA_RATE------~OLOGIC0:OFF_SRVAL[2]-~IDELAY0:IDELAY_VALUE_CUR[2]-~ODELAY0:ODELAY_VALUE_CUR[2]-IOB0:OUTPUT_MISC[5]
20 ---------------------------ILOGIC0:BITSLIP_ENABLE----~OLOGIC0:OFF_SRVAL[0]-----IOB0:NDRIVE[6]-
21 --------------------------ILOGIC0:SERDES_MODE---OLOGIC0:INV.D3----IDELAY0:PIPE_SEL-ODELAY0:PIPE_SEL-IOB0:LVDS[2]
22 ------------------------------------ODELAY0:FINEDELAY-IOB0:NSLEW[3]-
23 ---------------------------------------IOB0:PDRIVE[6]
24 ----------------------------ILOGIC0:I_TSBYPASS_ENABLE---------~IOB0:NDRIVE[5]-
25 --------------------------ILOGIC0:SERDES---OLOGIC0:INV.D2----IDELAY0:IDELAY_VALUE_INIT[3]-ODELAY0:ODELAY_VALUE_INIT[3]-IOB0:LVDS[3]
26 ---------------------------ILOGIC0:INTERFACE_TYPE[1]ILOGIC0:I_DELAY_ENABLE--OLOGIC0:DATA_WIDTH[8]------IOB0:PSLEW[2]-
27 --------------------------ILOGIC0:RANK23_DLY---OLOGIC0:CLK_RATIO[3]----~IDELAY0:IDELAY_VALUE_CUR[3]-~ODELAY0:ODELAY_VALUE_CUR[3]-IOB0:NDRIVE[1]
28 ---------------------------ILOGIC0:DDR_CLK_EDGE[1]-ILOGIC0:MUX.CLKDIVP[1]-OLOGIC0:CLK_RATIO[0]------IOB0:LVDS[4]-
29 --------------------------ILOGIC0:DDR_CLK_EDGE[0]-ILOGIC0:MUX.CLKDIVP[0]-OLOGIC0:CLK_RATIO[2]--------IOB0:DQS_BIAS_P
30 -----------------------------OLOGIC0:MUX.CLK[5]OLOGIC0:MUX.CLKB[5]OLOGIC0:INV.D1~OLOGIC0:OFF_INIT-----IOB0:PSLEW[1]-
31 ----------------------------OLOGIC0:MUX.CLK[7]-OLOGIC0:SELFHEALOLOGIC0:MUX.CLKB[7]---IDELAY0:IDELAY_VALUE_INIT[4]-ODELAY0:ODELAY_VALUE_INIT[4]-IOB0:PDRIVE[1]
32 -----------------------------OLOGIC0:MUX.CLK[4]OLOGIC0:MUX.CLKB[4]OLOGIC0:CLK_RATIO[1]~OLOGIC0:OFF_SRVAL[1]-----IOB0:OUTPUT_ENABLE[0]-
33 ----------------------------OLOGIC0:MUX.CLK[6]~ILOGIC0:IFF4_INITOLOGIC0:INV.CLKDIVFOLOGIC0:MUX.CLKB[6]-OLOGIC0:OFF_SR_SYNC-~IDELAY0:IDELAY_VALUE_CUR[4]-~ODELAY0:ODELAY_VALUE_CUR[4]-~IOB0:PDRIVE[5]
34 ----------------------------~ILOGIC0:IFF4_SRVALOLOGIC0:MUX.CLK[10]OLOGIC0:MUX.CLKB[10]-OLOGIC0:OMUX[1]-----IOB0:OUTPUT_ENABLE[1]-
35 ----------------------------OLOGIC0:MUX.CLK[9]-~OLOGIC0:INV.CLK2OLOGIC0:MUX.CLKB[9]-------IOB0:NDRIVE[4]
36 --------------------------------OLOGIC0:OMUX[2]-----IOB0:DQS_BIAS_N-
37 ------------------------------~OLOGIC0:INV.CLK1--OLOGIC0:TRISTATE_WIDTH-----IOB0:LVDS[5]
38 -----------------------------OLOGIC0:MUX.CLK[8]OLOGIC0:MUX.CLKB[8]-OLOGIC0:TFF_SR_USED-IDELAY0:CINVCTRL_SEL-ODELAY0:CINVCTRL_SEL-IOB0:NSLEW[2]-
39 ----------------------------OLOGIC0:MUX.CLK[3]--OLOGIC0:MUX.CLKB[3]---IDELAY0:INV.C-ODELAY0:INV.C-IOB0:IBUFDISABLE_SEL
40 --------------------------------------IOB0:LVDS[6]-
41 -----------------------------~ILOGIC0:IFF3_INIT~OLOGIC0:RANK3_USED--------IOB0:LVDS[8]
42 ----------------------------~ILOGIC0:IFF3_SRVAL--OLOGIC0:INV.CLKDIV------IOB0:DCI_MODE[0]-
43 ----------------------------OLOGIC0:MUX.CLK[2]--OLOGIC0:MUX.CLKB[2]-OLOGIC0:TBYTE_SRC-----IOB0:OMUX
44 -----------------------------OLOGIC0:MUX.CLK[0]OLOGIC0:MUX.CLKB[0]-OLOGIC0:SERDES_MODE-----IOB0:PDRIVE[4]-
45 ----------------------------OLOGIC0:MUX.CLK[1]--OLOGIC0:MUX.CLKB[1]-~OLOGIC0:TFF_SRVAL[2]-----IOB0:NSLEW[1]
46 -----------------------------ILOGIC0:MUX.CLK[5]ILOGIC0:MUX.CLKB[5]-~OLOGIC0:TFF_SRVAL[0]-IDELAY0:INV.DATAIN---IOB0:NSLEW[0]-
47 --------------------------ILOGIC0:NUM_CE-ILOGIC0:MUX.CLK[7]--ILOGIC0:MUX.CLKB[7]-OLOGIC0:TBYTE_CTL-----~IOB0:NDRIVE[3]
48 -----------------------------ILOGIC0:MUX.CLK[4]ILOGIC0:MUX.CLKB[4]~OLOGIC0:INV.T4------~IOB0:PDRIVE[2]-
49 ----------------------------ILOGIC0:MUX.CLK[6]--ILOGIC0:MUX.CLKB[6]-------~IOB0:PDRIVE[3]
50 -----------------------------ILOGIC0:MUX.CLK[10]ILOGIC0:MUX.CLKB[10]-------IOB0:PSLEW[0]-
51 ----------------------------ILOGIC0:MUX.CLK[9]~ILOGIC0:IFF2_INIT~OLOGIC0:INV.T3ILOGIC0:MUX.CLKB[9]-------IOB0:NDRIVE[0]
52 ----------------------------~ILOGIC0:IFF2_SRVALILOGIC0:MUX.CLK[8]ILOGIC0:MUX.CLKB[8]~OLOGIC0:TFF_INIT~OLOGIC0:TFF_SRVAL[1]-----IOB0:OUTPUT_DELAY-
53 ----------------------------ILOGIC0:MUX.CLK[3]--ILOGIC0:MUX.CLKB[3]-------IOB0:DCI_MODE[1]
54 --------------------------------OLOGIC0:SERDESIDELAY0:ENABLE-ODELAY0:ENABLE--IOB0:LVDS[7]-
55 -----------------------------~ILOGIC0:IFF1_INIT--IDELAY0:INV.IDATAINOLOGIC0:TFF_SR_SYNC~ODELAY0:INV.ODATAINIDELAY0:DELAY_SRC[0]-ODELAY0:DELAY_SRC[0]-IOB0:NDRIVE[2]
56 ---------------------------~ILOGIC0:IFF_LATCH~ILOGIC0:IFF1_SRVAL--~OLOGIC0:INV.T2--IDELAY0:DELAY_SRC[2]-ODELAY0:DELAY_SRC[1]-IOB0:DCIUPDATEMODE_QUIET-
57 --------------------------ILOGIC0:IFF_SR_USED------OLOGIC0:TMUX[2]-IDELAY0:DELAY_SRC[3]-ODELAY0:DELAY_SRC[2]-IOB0:OUTPUT_MISC[3]
58 ----------------------------IDELAY0:FINEDELAY---OLOGIC0:TMUX[1]-IDELAY0:DELAY_SRC[1]---IOB0:OUTPUT_MISC[0]-
59 ---------------------------------OLOGIC0:TMUX[3]-----IOB0:VREF_SYSMON
60 ----------------------------ILOGIC0:SRTYPEILOGIC0:MUX.CLK[2]ILOGIC0:MUX.CLKB[2]~OLOGIC0:INV.T1OLOGIC0:TMUX[4]-----IOB0:OUTPUT_MISC[1]-
61 ----------------------------ILOGIC0:MUX.CLK[0]ILOGIC0:D_EMU2-ILOGIC0:MUX.CLKB[0]-OLOGIC0:TMUX[0]-----IOB0:PDRIVE[0]
62 ----------------------------ILOGIC0:D_EMU1ILOGIC0:MUX.CLK[1]ILOGIC0:MUX.CLKB[1]-------IOB0:DCITERMDISABLE_SEL-
63 -----------------------------ILOGIC0:INV.OCLK1---------IOB0:DCI_T
IO_HP_PAIR bittile 1
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC1:INV.OCLK1---------IOB1:DCI_T-
1 ----------------------------ILOGIC1:MUX.CLK[1]ILOGIC1:D_EMU1-ILOGIC1:MUX.CLKB[1]-------IOB1:DCITERMDISABLE_SEL
2 ----------------------------ILOGIC1:D_EMU2ILOGIC1:MUX.CLK[0]ILOGIC1:MUX.CLKB[0]-OLOGIC1:TMUX[0]-----IOB1:PDRIVE[0]-
3 ----------------------------ILOGIC1:MUX.CLK[2]ILOGIC1:SRTYPE~OLOGIC1:INV.T1ILOGIC1:MUX.CLKB[2]-OLOGIC1:TMUX[4]-----IOB1:OUTPUT_MISC[1]
4 --------------------------------OLOGIC1:TMUX[3]-----IOB1:VREF_SYSMON-
5 -----------------------------IDELAY1:FINEDELAY---OLOGIC1:TMUX[1]-IDELAY1:DELAY_SRC[1]---IOB1:OUTPUT_MISC[0]
6 ---------------------------ILOGIC1:IFF_SR_USED----OLOGIC1:TMUX[2]-IDELAY1:DELAY_SRC[3]-ODELAY1:DELAY_SRC[2]-IOB1:OUTPUT_MISC[3]-
7 --------------------------~ILOGIC1:IFF_LATCH--~ILOGIC1:IFF1_SRVAL~OLOGIC1:INV.T2----IDELAY1:DELAY_SRC[2]-ODELAY1:DELAY_SRC[1]-IOB1:DCIUPDATEMODE_QUIET
8 ----------------------------~ILOGIC1:IFF1_INIT---OLOGIC1:TFF_SR_SYNCIDELAY1:INV.IDATAINIDELAY1:DELAY_SRC[0]~ODELAY1:INV.ODATAINODELAY1:DELAY_SRC[0]-IOB1:NDRIVE[2]-
9 --------------------------------IDELAY1:ENABLEOLOGIC1:SERDESODELAY1:ENABLE----IOB1:LVDS[7]
10 -----------------------------ILOGIC1:MUX.CLK[3]ILOGIC1:MUX.CLKB[3]-------IOB1:DCI_MODE[1]-
11 ----------------------------ILOGIC1:MUX.CLK[8]~ILOGIC1:IFF2_SRVAL~OLOGIC1:TFF_INITILOGIC1:MUX.CLKB[8]-~OLOGIC1:TFF_SRVAL[1]-----IOB1:OUTPUT_DELAY
12 ----------------------------~ILOGIC1:IFF2_INITILOGIC1:MUX.CLK[9]ILOGIC1:MUX.CLKB[9]~OLOGIC1:INV.T3------IOB1:NDRIVE[0]-
13 ----------------------------ILOGIC1:MUX.CLK[10]--ILOGIC1:MUX.CLKB[10]-------IOB1:PSLEW[0]
14 -----------------------------ILOGIC1:MUX.CLK[6]ILOGIC1:MUX.CLKB[6]-------~IOB1:PDRIVE[3]-
15 ----------------------------ILOGIC1:MUX.CLK[4]-~OLOGIC1:INV.T4ILOGIC1:MUX.CLKB[4]-------~IOB1:PDRIVE[2]
16 ---------------------------ILOGIC1:NUM_CE-ILOGIC1:MUX.CLK[7]ILOGIC1:MUX.CLKB[7]-OLOGIC1:TBYTE_CTL-----~IOB1:NDRIVE[3]-
17 ----------------------------ILOGIC1:MUX.CLK[5]--ILOGIC1:MUX.CLKB[5]-~OLOGIC1:TFF_SRVAL[2]-IDELAY1:INV.DATAIN---IOB1:NSLEW[0]
18 -----------------------------OLOGIC1:MUX.CLK[1]OLOGIC1:MUX.CLKB[1]-~OLOGIC1:TFF_SRVAL[0]-----IOB1:NSLEW[1]-
19 ----------------------------OLOGIC1:MUX.CLK[0]--OLOGIC1:MUX.CLKB[0]-OLOGIC1:SERDES_MODE-----IOB1:PDRIVE[4]
20 -----------------------------OLOGIC1:MUX.CLK[2]OLOGIC1:MUX.CLKB[2]-OLOGIC1:TBYTE_SRC-------
21 -----------------------------~ILOGIC1:IFF3_SRVALOLOGIC1:INV.CLKDIV--------IOB1:DCI_MODE[0]
22 ----------------------------~ILOGIC1:IFF3_INIT--~OLOGIC1:RANK3_USED------IOB1:LVDS[8]-
23 ---------------------------------------IOB1:LVDS[6]
24 -----------------------------OLOGIC1:MUX.CLK[3]OLOGIC1:MUX.CLKB[3]---IDELAY1:INV.C-ODELAY1:INV.C-IOB1:IBUFDISABLE_SEL-
25 ----------------------------OLOGIC1:MUX.CLK[8]--OLOGIC1:MUX.CLKB[8]-OLOGIC1:TFF_SR_USED-IDELAY1:CINVCTRL_SEL-ODELAY1:CINVCTRL_SEL-IOB1:NSLEW[2]
26 -------------------------------~OLOGIC1:INV.CLK1OLOGIC1:TRISTATE_WIDTH-----IOB1:LVDS[5]-
27 ---------------------------------OLOGIC1:OMUX[2]-----IOB1:DQS_BIAS_N
28 -----------------------------OLOGIC1:MUX.CLK[9]OLOGIC1:MUX.CLKB[9]~OLOGIC1:INV.CLK2------IOB1:NDRIVE[4]-
29 ----------------------------OLOGIC1:MUX.CLK[10]~ILOGIC1:IFF4_SRVAL-OLOGIC1:MUX.CLKB[10]-OLOGIC1:OMUX[1]-----IOB1:OUTPUT_ENABLE[0]
30 ----------------------------~ILOGIC1:IFF4_INITOLOGIC1:MUX.CLK[6]OLOGIC1:MUX.CLKB[6]OLOGIC1:INV.CLKDIVFOLOGIC1:OFF_SR_SYNC-~IDELAY1:IDELAY_VALUE_CUR[4]-~ODELAY1:ODELAY_VALUE_CUR[4]-~IOB1:PDRIVE[5]-
31 ----------------------------OLOGIC1:MUX.CLK[4]-OLOGIC1:CLK_RATIO[1]OLOGIC1:MUX.CLKB[4]-~OLOGIC1:OFF_SRVAL[1]-----IOB1:OUTPUT_ENABLE[1]
32 -----------------------------OLOGIC1:MUX.CLK[7]OLOGIC1:MUX.CLKB[7]OLOGIC1:SELFHEAL--IDELAY1:IDELAY_VALUE_INIT[4]-ODELAY1:ODELAY_VALUE_INIT[4]-IOB1:PDRIVE[1]-
33 ----------------------------OLOGIC1:MUX.CLK[5]-OLOGIC1:INV.D1OLOGIC1:MUX.CLKB[5]-~OLOGIC1:OFF_INIT-----IOB1:PSLEW[1]
34 ---------------------------ILOGIC1:DDR_CLK_EDGE[0]-ILOGIC1:MUX.CLKDIVP[0]-OLOGIC1:CLK_RATIO[2]------IOB1:DQS_BIAS_P-
35 --------------------------ILOGIC1:DDR_CLK_EDGE[1]-ILOGIC1:MUX.CLKDIVP[1]-OLOGIC1:CLK_RATIO[0]--------IOB1:LVDS[4]
36 ---------------------------ILOGIC1:RANK23_DLY---OLOGIC1:CLK_RATIO[3]--~IDELAY1:IDELAY_VALUE_CUR[3]-~ODELAY1:ODELAY_VALUE_CUR[3]-IOB1:NDRIVE[1]-
37 --------------------------ILOGIC1:INTERFACE_TYPE[1]--ILOGIC1:I_DELAY_ENABLEOLOGIC1:DATA_WIDTH[8]--------IOB1:PSLEW[2]
38 ---------------------------ILOGIC1:SERDES---OLOGIC1:INV.D2--IDELAY1:IDELAY_VALUE_INIT[3]-ODELAY1:ODELAY_VALUE_INIT[3]-IOB1:LVDS[3]-
39 -----------------------------ILOGIC1:I_TSBYPASS_ENABLE---------~IOB1:NDRIVE[5]
40 --------------------------------------IOB1:PDRIVE[6]-
41 -------------------------------------ODELAY1:FINEDELAY-IOB1:NSLEW[3]
42 ---------------------------ILOGIC1:SERDES_MODE---OLOGIC1:INV.D3--IDELAY1:PIPE_SEL-ODELAY1:PIPE_SEL-IOB1:LVDS[2]-
43 --------------------------ILOGIC1:BITSLIP_ENABLE------~OLOGIC1:OFF_SRVAL[2]-----IOB1:NDRIVE[6]
44 ---------------------------ILOGIC1:DATA_RATE----~OLOGIC1:OFF_SRVAL[0]-~IDELAY1:IDELAY_VALUE_CUR[2]-~ODELAY1:ODELAY_VALUE_CUR[2]-IOB1:OUTPUT_MISC[5]-
45 --------------------------ILOGIC1:DATA_WIDTH[3]--~ILOGIC1:INV.D--IDELAY1:HIGH_PERFORMANCE_MODE-ODELAY1:HIGH_PERFORMANCE_MODE-----
46 ---------------------------ILOGIC1:DATA_WIDTH[2]ILOGIC1:TSBYPASS_MUXOLOGIC1:MUX.CLKDIV[1]OLOGIC1:MUX.CLKDIVB[1]OLOGIC1:INV.D4OLOGIC1:OMUX[4]-IDELAY1:IDELAY_VALUE_INIT[2]-ODELAY1:ODELAY_VALUE_INIT[2]---
47 --------------------------ILOGIC1:DATA_WIDTH[1]-OLOGIC1:MUX.CLKDIV[0]-OLOGIC1:MISR_ENABLEOLOGIC1:MUX.CLKDIVB[0]-OLOGIC1:OMUX[0]-----IOB1:PSLEW[3]
48 ---------------------------ILOGIC1:DATA_WIDTH[0]---OLOGIC1:MISR_CLK_SELECT[0]OLOGIC1:OFF_SR_USED-----IOB1:LVDS[1]-
49 --------------------------ILOGIC1:INTERFACE_TYPE[3]--ILOGIC1:IFF_TSBYPASS_ENABLEOLOGIC1:INV.D5--OLOGIC1:OMUX[3]-IDELAY1:IDELAY_TYPE[1]-ODELAY1:ODELAY_TYPE[1]-IOB1:NSLEW[4]
50 ---------------------------ILOGIC1:INV.CLKDIVP---OLOGIC1:INV.D6--~IDELAY1:IDELAY_VALUE_CUR[1]-~ODELAY1:ODELAY_VALUE_CUR[1]-IOB1:PSLEW[4]-
51 --------------------------ILOGIC1:INTERFACE_TYPE[4]---OLOGIC1:DATA_WIDTH[7]--------IOB1:PULL[0]
52 ---------------------------ILOGIC1:DYN_CLKDIVP_INV_ENILOGIC1:IFF_DELAY_ENABLE--OLOGIC1:DATA_WIDTH[6]--IDELAY1:IDELAY_VALUE_INIT[1]-ODELAY1:ODELAY_VALUE_INIT[1]-IOB1:OUTPUT_MISC[4]-
53 --------------------------ILOGIC1:INTERFACE_TYPE[2]---OLOGIC1:MISR_ENABLE_FDBK--------IOB1:PULL[1]
54 ---------------------------ILOGIC1:DYN_CLKDIV_INV_EN-OLOGIC1:MUX.CLKDIVF[4]OLOGIC1:MUX.CLKDIVFB[4]OLOGIC1:INV.D7------IOB1:OUTPUT_MISC[2]-
55 --------------------------ILOGIC1:INV.CLKDIV-OLOGIC1:MUX.CLKDIVF[5]-OLOGIC1:MISR_RESETOLOGIC1:MUX.CLKDIVFB[5]---IDELAY1:IDELAY_TYPE[0]-ODELAY1:ODELAY_TYPE[0]-IOB1:LVDS[0]
56 -------------------------------OLOGIC1:DATA_WIDTH[4]--~IDELAY1:IDELAY_VALUE_CUR[0]-~ODELAY1:ODELAY_VALUE_CUR[0]---
57 --------------------------ILOGIC1:INTERFACE_TYPE[0]-OLOGIC1:MUX.CLKDIVF[6]-OLOGIC1:DATA_WIDTH[3]OLOGIC1:MUX.CLKDIVFB[6]-------IOB1:PULL_DYNAMIC
58 -------------------------------OLOGIC1:MISR_CLK_SELECT[1]--IDELAY1:IDELAY_VALUE_INIT[0]-ODELAY1:ODELAY_VALUE_INIT[0]-IOB1:INPUT_MISC-
59 ----------------------------OLOGIC1:MUX.CLKDIVF[2]~ILOGIC1:INV.CLK[1]OLOGIC1:DATA_WIDTH[5]OLOGIC1:MUX.CLKDIVFB[2]-------IOB1:PULL[2]
60 ----------------------------ILOGIC1:INV.OCLK2OLOGIC1:MUX.CLKDIVF[0]OLOGIC1:MUX.CLKDIVFB[0]OLOGIC1:DATA_WIDTH[2]------IOB1:IBUF_MODE[3]-
61 ----------------------------OLOGIC1:MUX.CLKDIVF[3]~ILOGIC1:INV.CLK[2]OLOGIC1:INV.D8OLOGIC1:MUX.CLKDIVFB[3]-------IOB1:IBUF_MODE[2]
62 ----------------------------~ILOGIC1:INV.CLK[0]OLOGIC1:MUX.CLKDIVF[1]OLOGIC1:MUX.CLKDIVFB[1]OLOGIC1:DATA_WIDTH[1]------IOB1:IBUF_MODE[1]-
63 -----------------------------ILOGIC1:DYN_CLK_INV_ENOLOGIC1:DATA_WIDTH[0]--------IOB1:IBUF_MODE[0]
IDELAY0:CINVCTRL_SEL[0, 34, 38]
IDELAY0:ENABLE[0, 33, 54]
IDELAY0:HIGH_PERFORMANCE_MODE[0, 33, 18]
IDELAY0:INV.C[0, 35, 39]
IDELAY0:INV.DATAIN[0, 34, 46]
IDELAY0:INV.IDATAIN[0, 32, 55]
IDELAY0:PIPE_SEL[0, 35, 21]
IDELAY1:CINVCTRL_SEL[1, 35, 25]
IDELAY1:ENABLE[1, 32, 9]
IDELAY1:HIGH_PERFORMANCE_MODE[1, 32, 45]
IDELAY1:INV.C[1, 34, 24]
IDELAY1:INV.DATAIN[1, 35, 17]
IDELAY1:INV.IDATAIN[1, 33, 8]
IDELAY1:PIPE_SEL[1, 34, 42]
ILOGIC0:BITSLIP_ENABLE[0, 27, 20]
ILOGIC0:DYN_CLKDIVP_INV_EN[0, 26, 11]
ILOGIC0:DYN_CLKDIV_INV_EN[0, 26, 9]
ILOGIC0:DYN_CLK_INV_EN[0, 28, 0]
ILOGIC0:D_EMU1[0, 28, 62]
ILOGIC0:D_EMU2[0, 29, 61]
ILOGIC0:IFF_DELAY_ENABLE[0, 29, 11]
ILOGIC0:IFF_SR_USED[0, 26, 57]
ILOGIC0:IFF_TSBYPASS_ENABLE[0, 28, 14]
ILOGIC0:INV.CLKDIV[0, 27, 8]
ILOGIC0:INV.CLKDIVP[0, 26, 13]
ILOGIC0:INV.OCLK1[0, 29, 63]
ILOGIC0:INV.OCLK2[0, 29, 3]
ILOGIC0:I_DELAY_ENABLE[0, 28, 26]
ILOGIC0:I_TSBYPASS_ENABLE[0, 28, 24]
ILOGIC0:RANK23_DLY[0, 26, 27]
ILOGIC0:SERDES[0, 26, 25]
ILOGIC1:BITSLIP_ENABLE[1, 26, 43]
ILOGIC1:DYN_CLKDIVP_INV_EN[1, 27, 52]
ILOGIC1:DYN_CLKDIV_INV_EN[1, 27, 54]
ILOGIC1:DYN_CLK_INV_EN[1, 29, 63]
ILOGIC1:D_EMU1[1, 29, 1]
ILOGIC1:D_EMU2[1, 28, 2]
ILOGIC1:IFF_DELAY_ENABLE[1, 28, 52]
ILOGIC1:IFF_SR_USED[1, 27, 6]
ILOGIC1:IFF_TSBYPASS_ENABLE[1, 29, 49]
ILOGIC1:INV.CLKDIV[1, 26, 55]
ILOGIC1:INV.CLKDIVP[1, 27, 50]
ILOGIC1:INV.OCLK1[1, 28, 0]
ILOGIC1:INV.OCLK2[1, 28, 60]
ILOGIC1:I_DELAY_ENABLE[1, 29, 37]
ILOGIC1:I_TSBYPASS_ENABLE[1, 29, 39]
ILOGIC1:RANK23_DLY[1, 27, 36]
ILOGIC1:SERDES[1, 27, 38]
IOB0:DCIUPDATEMODE_QUIET[0, 38, 56]
IOB0:DCI_T[0, 39, 63]
IOB0:DQS_BIAS_N[0, 38, 36]
IOB0:DQS_BIAS_P[0, 39, 29]
IOB0:INPUT_MISC[0, 39, 5]
IOB0:OUTPUT_DELAY[0, 38, 52]
IOB0:PULL_DYNAMIC[0, 38, 6]
IOB0:VREF_SYSMON[0, 39, 59]
IOB1:DCIUPDATEMODE_QUIET[1, 39, 7]
IOB1:DCI_T[1, 38, 0]
IOB1:DQS_BIAS_N[1, 39, 27]
IOB1:DQS_BIAS_P[1, 38, 34]
IOB1:INPUT_MISC[1, 38, 58]
IOB1:OUTPUT_DELAY[1, 39, 11]
IOB1:PULL_DYNAMIC[1, 39, 57]
IOB1:VREF_SYSMON[1, 38, 4]
ODELAY0:CINVCTRL_SEL[0, 36, 38]
ODELAY0:ENABLE[0, 35, 54]
ODELAY0:HIGH_PERFORMANCE_MODE[0, 35, 18]
ODELAY0:INV.C[0, 37, 39]
ODELAY0:PIPE_SEL[0, 37, 21]
ODELAY1:CINVCTRL_SEL[1, 37, 25]
ODELAY1:ENABLE[1, 34, 9]
ODELAY1:HIGH_PERFORMANCE_MODE[1, 34, 45]
ODELAY1:INV.C[1, 36, 24]
ODELAY1:PIPE_SEL[1, 36, 42]
OLOGIC0:INV.CLKDIV[0, 31, 42]
OLOGIC0:INV.CLKDIVF[0, 30, 33]
OLOGIC0:INV.D1[0, 31, 30]
OLOGIC0:INV.D2[0, 30, 25]
OLOGIC0:INV.D3[0, 30, 21]
OLOGIC0:INV.D4[0, 30, 17]
OLOGIC0:INV.D5[0, 31, 14]
OLOGIC0:INV.D6[0, 30, 13]
OLOGIC0:INV.D7[0, 30, 9]
OLOGIC0:INV.D8[0, 31, 2]
OLOGIC0:MISR_ENABLE[0, 31, 16]
OLOGIC0:MISR_ENABLE_FDBK[0, 31, 10]
OLOGIC0:MISR_RESET[0, 31, 8]
OLOGIC0:OFF_SR_SYNC[0, 33, 33]
OLOGIC0:OFF_SR_USED[0, 33, 15]
OLOGIC0:SELFHEAL[0, 30, 31]
OLOGIC0:SERDES[0, 32, 54]
OLOGIC0:TBYTE_CTL[0, 33, 47]
OLOGIC0:TBYTE_SRC[0, 33, 43]
OLOGIC0:TFF_SR_SYNC[0, 33, 55]
OLOGIC0:TFF_SR_USED[0, 32, 38]
OLOGIC1:INV.CLKDIV[1, 30, 21]
OLOGIC1:INV.CLKDIVF[1, 31, 30]
OLOGIC1:INV.D1[1, 30, 33]
OLOGIC1:INV.D2[1, 31, 38]
OLOGIC1:INV.D3[1, 31, 42]
OLOGIC1:INV.D4[1, 31, 46]
OLOGIC1:INV.D5[1, 30, 49]
OLOGIC1:INV.D6[1, 31, 50]
OLOGIC1:INV.D7[1, 31, 54]
OLOGIC1:INV.D8[1, 30, 61]
OLOGIC1:MISR_ENABLE[1, 30, 47]
OLOGIC1:MISR_ENABLE_FDBK[1, 30, 53]
OLOGIC1:MISR_RESET[1, 30, 55]
OLOGIC1:OFF_SR_SYNC[1, 32, 30]
OLOGIC1:OFF_SR_USED[1, 32, 48]
OLOGIC1:SELFHEAL[1, 31, 32]
OLOGIC1:SERDES[1, 33, 9]
OLOGIC1:TBYTE_CTL[1, 32, 16]
OLOGIC1:TBYTE_SRC[1, 32, 20]
OLOGIC1:TFF_SR_SYNC[1, 32, 8]
OLOGIC1:TFF_SR_USED[1, 33, 25]
Non-inverted[0]
ILOGIC0:DATA_WIDTH[0, 27, 18][0, 26, 17][0, 27, 16][0, 26, 15]
ILOGIC1:DATA_WIDTH[1, 26, 45][1, 27, 46][1, 26, 47][1, 27, 48]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
ILOGIC0:DATA_RATE[0, 26, 19]
ILOGIC1:DATA_RATE[1, 27, 44]
DDR0
SDR1
ILOGIC0:SERDES_MODE[0, 26, 21]
ILOGIC1:SERDES_MODE[1, 27, 42]
OLOGIC0:SERDES_MODE[0, 32, 44]
OLOGIC1:SERDES_MODE[1, 33, 19]
MASTER0
SLAVE1
ILOGIC0:DDR_CLK_EDGE[0, 27, 28][0, 26, 29]
ILOGIC1:DDR_CLK_EDGE[1, 26, 35][1, 27, 34]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC0:NUM_CE[0, 26, 47]
ILOGIC1:NUM_CE[1, 27, 16]
10
21
ILOGIC0:INTERFACE_TYPE[0, 27, 12][0, 27, 14][0, 27, 10][0, 27, 26][0, 27, 6]
ILOGIC1:INTERFACE_TYPE[1, 26, 51][1, 26, 49][1, 26, 53][1, 26, 37][1, 26, 57]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC0:IFF1_INIT[0, 29, 55]
ILOGIC0:IFF1_SRVAL[0, 28, 56]
ILOGIC0:IFF2_INIT[0, 29, 51]
ILOGIC0:IFF2_SRVAL[0, 28, 52]
ILOGIC0:IFF3_INIT[0, 29, 41]
ILOGIC0:IFF3_SRVAL[0, 28, 42]
ILOGIC0:IFF4_INIT[0, 29, 33]
ILOGIC0:IFF4_SRVAL[0, 28, 34]
ILOGIC0:IFF_LATCH[0, 27, 56]
ILOGIC0:INV.D[0, 28, 18]
ILOGIC1:IFF1_INIT[1, 28, 8]
ILOGIC1:IFF1_SRVAL[1, 29, 7]
ILOGIC1:IFF2_INIT[1, 28, 12]
ILOGIC1:IFF2_SRVAL[1, 29, 11]
ILOGIC1:IFF3_INIT[1, 28, 22]
ILOGIC1:IFF3_SRVAL[1, 29, 21]
ILOGIC1:IFF4_INIT[1, 28, 30]
ILOGIC1:IFF4_SRVAL[1, 29, 29]
ILOGIC1:IFF_LATCH[1, 26, 7]
ILOGIC1:INV.D[1, 29, 45]
ODELAY0:INV.ODATAIN[0, 34, 55]
ODELAY1:INV.ODATAIN[1, 35, 8]
OLOGIC0:INV.CLK1[0, 30, 37]
OLOGIC0:INV.CLK2[0, 30, 35]
OLOGIC0:INV.T1[0, 31, 60]
OLOGIC0:INV.T2[0, 31, 56]
OLOGIC0:INV.T3[0, 30, 51]
OLOGIC0:INV.T4[0, 31, 48]
OLOGIC0:OFF_INIT[0, 32, 30]
OLOGIC0:RANK3_USED[0, 30, 41]
OLOGIC0:TFF_INIT[0, 31, 52]
OLOGIC1:INV.CLK1[1, 31, 26]
OLOGIC1:INV.CLK2[1, 31, 28]
OLOGIC1:INV.T1[1, 30, 3]
OLOGIC1:INV.T2[1, 30, 7]
OLOGIC1:INV.T3[1, 31, 12]
OLOGIC1:INV.T4[1, 30, 15]
OLOGIC1:OFF_INIT[1, 33, 33]
OLOGIC1:RANK3_USED[1, 31, 22]
OLOGIC1:TFF_INIT[1, 30, 11]
Inverted~[0]
ILOGIC0:INV.CLK[0, 29, 1][0, 28, 4][0, 28, 2]
ILOGIC1:INV.CLK[1, 29, 61][1, 29, 59][1, 28, 62]
OLOGIC0:OFF_SRVAL[0, 33, 19][0, 32, 32][0, 32, 20]
OLOGIC0:TFF_SRVAL[0, 33, 45][0, 32, 52][0, 32, 46]
OLOGIC1:OFF_SRVAL[1, 33, 43][1, 33, 31][1, 32, 44]
OLOGIC1:TFF_SRVAL[1, 33, 17][1, 33, 11][1, 32, 18]
Inverted~[2]~[1]~[0]
OLOGIC0:MUX.CLKDIVF[0, 29, 6][0, 29, 8][0, 28, 9][0, 29, 2][0, 29, 4][0, 28, 1][0, 28, 3]
OLOGIC0:MUX.CLKDIVFB[0, 30, 6][0, 30, 8][0, 31, 9][0, 30, 2][0, 30, 4][0, 31, 1][0, 31, 3]
OLOGIC1:MUX.CLKDIVF[1, 28, 57][1, 28, 55][1, 29, 54][1, 28, 61][1, 28, 59][1, 29, 62][1, 29, 60]
OLOGIC1:MUX.CLKDIVFB[1, 31, 57][1, 31, 55][1, 30, 54][1, 31, 61][1, 31, 59][1, 30, 62][1, 30, 60]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
ILOGIC0:MUX.CLKDIVP[0, 29, 28][0, 28, 29]
ILOGIC1:MUX.CLKDIVP[1, 28, 35][1, 29, 34]
NONE00
CLKDIV01
PHASER10
IDELAY0:FINEDELAY[0, 28, 58]
IDELAY1:FINEDELAY[1, 29, 5]
ODELAY0:FINEDELAY[0, 36, 22]
ODELAY1:FINEDELAY[1, 37, 41]
BYPASS0
ADD_DLY1
ILOGIC0:SRTYPE[0, 28, 60]
ILOGIC1:SRTYPE[1, 29, 3]
ASYNC0
SYNC1
ILOGIC0:MUX.CLK[0, 29, 50][0, 28, 51][0, 29, 52][0, 28, 47][0, 28, 49][0, 29, 46][0, 29, 48][0, 28, 53][0, 29, 60][0, 29, 62][0, 28, 61]
ILOGIC0:MUX.CLKB[0, 30, 50][0, 31, 51][0, 30, 52][0, 31, 47][0, 31, 49][0, 30, 46][0, 30, 48][0, 31, 53][0, 30, 60][0, 30, 62][0, 31, 61]
ILOGIC1:MUX.CLK[1, 28, 13][1, 29, 12][1, 28, 11][1, 29, 16][1, 29, 14][1, 28, 17][1, 28, 15][1, 29, 10][1, 28, 3][1, 28, 1][1, 29, 2]
ILOGIC1:MUX.CLKB[1, 31, 13][1, 30, 12][1, 31, 11][1, 30, 16][1, 30, 14][1, 31, 17][1, 31, 15][1, 30, 10][1, 31, 3][1, 31, 1][1, 30, 2]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
OLOGIC0:MUX.CLKDIV[0, 28, 17][0, 29, 16]
OLOGIC1:MUX.CLKDIV[1, 29, 46][1, 28, 47]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
ILOGIC0:TSBYPASS_MUX[0, 29, 17]
ILOGIC1:TSBYPASS_MUX[1, 28, 46]
T0
GND1
OLOGIC0:MUX.CLK[0, 29, 34][0, 28, 35][0, 29, 38][0, 28, 31][0, 28, 33][0, 29, 30][0, 29, 32][0, 28, 39][0, 28, 43][0, 28, 45][0, 29, 44]
OLOGIC0:MUX.CLKB[0, 30, 34][0, 31, 35][0, 30, 38][0, 31, 31][0, 31, 33][0, 30, 30][0, 30, 32][0, 31, 39][0, 31, 43][0, 31, 45][0, 30, 44]
OLOGIC1:MUX.CLK[1, 28, 29][1, 29, 28][1, 28, 25][1, 29, 32][1, 29, 30][1, 28, 33][1, 28, 31][1, 29, 24][1, 29, 20][1, 29, 18][1, 28, 19]
OLOGIC1:MUX.CLKB[1, 31, 29][1, 30, 28][1, 31, 25][1, 30, 32][1, 30, 30][1, 31, 33][1, 31, 31][1, 30, 24][1, 30, 20][1, 30, 18][1, 31, 19]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
OLOGIC0:MISR_CLK_SELECT[0, 30, 5][0, 30, 15]
OLOGIC1:MISR_CLK_SELECT[1, 31, 58][1, 31, 48]
NONE00
CLK101
CLK210
OLOGIC0:MUX.CLKDIVB[0, 31, 17][0, 30, 16]
OLOGIC1:MUX.CLKDIVB[1, 30, 46][1, 31, 47]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC0:DATA_WIDTH[0, 31, 26][0, 31, 12][0, 30, 11][0, 31, 4][0, 30, 7][0, 31, 6][0, 30, 3][0, 30, 1][0, 31, 0]
OLOGIC1:DATA_WIDTH[1, 30, 37][1, 30, 51][1, 31, 52][1, 30, 59][1, 31, 56][1, 30, 57][1, 31, 60][1, 31, 62][1, 30, 63]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC0:CLK_RATIO[0, 30, 27][0, 30, 29][0, 31, 32][0, 31, 28]
OLOGIC1:CLK_RATIO[1, 31, 36][1, 31, 34][1, 30, 31][1, 30, 35]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC0:OMUX[0, 33, 17][0, 32, 14][0, 32, 36][0, 32, 34][0, 32, 16]
OLOGIC1:OMUX[1, 32, 46][1, 33, 49][1, 33, 27][1, 33, 29][1, 33, 47]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC0:TRISTATE_WIDTH[0, 33, 37]
OLOGIC1:TRISTATE_WIDTH[1, 32, 26]
10
41
OLOGIC0:TMUX[0, 32, 60][0, 33, 59][0, 33, 57][0, 32, 58][0, 33, 61]
OLOGIC1:TMUX[1, 33, 3][1, 32, 4][1, 32, 6][1, 33, 5][1, 32, 2]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY0:IDELAY_TYPE[0, 34, 14][0, 34, 8]
IDELAY1:IDELAY_TYPE[1, 35, 49][1, 35, 55]
ODELAY0:ODELAY_TYPE[0, 36, 14][0, 36, 8]
ODELAY1:ODELAY_TYPE[1, 37, 49][1, 37, 55]
FIXED00
VARIABLE01
VAR_LOAD11
IDELAY0:IDELAY_VALUE_INIT[0, 35, 31][0, 35, 25][0, 35, 17][0, 35, 11][0, 35, 5]
IDELAY1:IDELAY_VALUE_INIT[1, 34, 32][1, 34, 38][1, 34, 46][1, 34, 52][1, 34, 58]
IOB0:NSLEW[0, 38, 14][0, 38, 22][0, 38, 38][0, 39, 45][0, 38, 46]
IOB0:PSLEW[0, 39, 13][0, 38, 16][0, 38, 26][0, 38, 30][0, 38, 50]
IOB1:NSLEW[1, 39, 49][1, 39, 41][1, 39, 25][1, 38, 18][1, 39, 17]
IOB1:PSLEW[1, 38, 50][1, 39, 47][1, 39, 37][1, 39, 33][1, 39, 13]
ODELAY0:ODELAY_VALUE_INIT[0, 37, 31][0, 37, 25][0, 37, 17][0, 37, 11][0, 37, 5]
ODELAY1:ODELAY_VALUE_INIT[1, 36, 32][1, 36, 38][1, 36, 46][1, 36, 52][1, 36, 58]
Non-inverted[4][3][2][1][0]
IDELAY0:IDELAY_VALUE_CUR[0, 35, 33][0, 35, 27][0, 35, 19][0, 35, 13][0, 35, 7]
IDELAY1:IDELAY_VALUE_CUR[1, 34, 30][1, 34, 36][1, 34, 44][1, 34, 50][1, 34, 56]
ODELAY0:ODELAY_VALUE_CUR[0, 37, 33][0, 37, 27][0, 37, 19][0, 37, 13][0, 37, 7]
ODELAY1:ODELAY_VALUE_CUR[1, 36, 30][1, 36, 36][1, 36, 44][1, 36, 50][1, 36, 56]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY0:DELAY_SRC[0, 35, 57][0, 34, 56][0, 34, 58][0, 35, 55]
IDELAY1:DELAY_SRC[1, 34, 6][1, 35, 7][1, 35, 5][1, 34, 8]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
ODELAY0:DELAY_SRC[0, 37, 57][0, 36, 56][0, 37, 55]
ODELAY1:DELAY_SRC[1, 36, 6][1, 37, 7][1, 36, 8]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
IOB0:IBUF_MODE[0, 39, 3][0, 38, 2][0, 39, 1][0, 38, 0]
IOB1:IBUF_MODE[1, 38, 60][1, 39, 61][1, 38, 62][1, 39, 63]
OFF0000
VREF_LP0001
DIFF_LP0010
CMOS0011
VREF_HP0101
DIFF_HP1010
IOB0:LVDS[0, 39, 41][0, 38, 54][0, 38, 40][0, 39, 37][0, 38, 28][0, 39, 25][0, 39, 21][0, 39, 15][0, 38, 8]
IOB1:LVDS[1, 38, 22][1, 39, 9][1, 39, 23][1, 38, 26][1, 39, 35][1, 38, 38][1, 38, 42][1, 38, 48][1, 39, 55]
Non-inverted[8][7][6][5][4][3][2][1][0]
IOB0:PULL[0, 38, 4][0, 38, 10][0, 38, 12]
IOB1:PULL[1, 39, 59][1, 39, 53][1, 39, 51]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:OUTPUT_ENABLE[0, 38, 34][0, 38, 32]
IOB1:OUTPUT_ENABLE[1, 39, 31][1, 39, 29]
Non-inverted[1][0]
IOB0:DCI_MODE[0, 39, 53][0, 38, 42]
IOB1:DCI_MODE[1, 38, 10][1, 39, 21]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11
IOB0:OUTPUT_MISC[0, 39, 19][0, 39, 11][0, 39, 57][0, 39, 9][0, 38, 60][0, 38, 58]
IOB1:OUTPUT_MISC[1, 38, 44][1, 38, 52][1, 38, 6][1, 38, 54][1, 39, 3][1, 39, 5]
Non-inverted[5][4][3][2][1][0]
IOB0:DCITERMDISABLE_SEL[0, 38, 62]
IOB0:IBUFDISABLE_SEL[0, 39, 39]
IOB1:DCITERMDISABLE_SEL[1, 39, 1]
IOB1:IBUFDISABLE_SEL[1, 38, 24]
GND0
I1
IOB0:TMUX[0, 39, 17]
T0
OTHER_T1
IOB0:OMUX[0, 39, 43]
O0
OTHER_O_INV1
IOB0:NDRIVE[0, 38, 20][0, 38, 24][0, 39, 35][0, 39, 47][0, 39, 55][0, 39, 27][0, 39, 51]
IOB1:NDRIVE[1, 39, 43][1, 39, 39][1, 38, 28][1, 38, 16][1, 38, 8][1, 38, 36][1, 38, 12]
Mixed inversion[6]~[5][4]~[3][2][1][0]
IOB0:PDRIVE[0, 39, 23][0, 39, 33][0, 38, 44][0, 39, 49][0, 38, 48][0, 39, 31][0, 39, 61]
IOB1:PDRIVE[1, 38, 40][1, 38, 30][1, 39, 19][1, 38, 14][1, 39, 15][1, 38, 32][1, 38, 2]
Mixed inversion[6]~[5][4]~[3]~[2][1][0]

Bitstream — IO_HP_BOT

IO_HP_BOT bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC:INV.OCLK1---------IOB:DCI_T-
1 ----------------------------ILOGIC:MUX.CLK[1]ILOGIC:D_EMU1-ILOGIC:MUX.CLKB[1]-------IOB:DCITERMDISABLE_SEL
2 ----------------------------ILOGIC:D_EMU2ILOGIC:MUX.CLK[0]ILOGIC:MUX.CLKB[0]-OLOGIC:TMUX[0]-----IOB:PDRIVE[0]-
3 ----------------------------ILOGIC:MUX.CLK[2]ILOGIC:SRTYPE~OLOGIC:INV.T1ILOGIC:MUX.CLKB[2]-OLOGIC:TMUX[4]-----IOB:OUTPUT_MISC[1]
4 --------------------------------OLOGIC:TMUX[3]-------
5 -----------------------------IDELAY:FINEDELAY---OLOGIC:TMUX[1]-IDELAY:DELAY_SRC[1]---IOB:OUTPUT_MISC[0]
6 ---------------------------ILOGIC:IFF_SR_USED----OLOGIC:TMUX[2]-IDELAY:DELAY_SRC[3]-ODELAY:DELAY_SRC[2]-IOB:OUTPUT_MISC[3]-
7 --------------------------~ILOGIC:IFF_LATCH--~ILOGIC:IFF1_SRVAL~OLOGIC:INV.T2----IDELAY:DELAY_SRC[2]-ODELAY:DELAY_SRC[1]-IOB:DCIUPDATEMODE_QUIET
8 ----------------------------~ILOGIC:IFF1_INIT---OLOGIC:TFF_SR_SYNCIDELAY:INV.IDATAINIDELAY:DELAY_SRC[0]~ODELAY:INV.ODATAINODELAY:DELAY_SRC[0]-IOB:NDRIVE[2]-
9 --------------------------------IDELAY:ENABLEOLOGIC:SERDESODELAY:ENABLE----IOB:LVDS[7]
10 -----------------------------ILOGIC:MUX.CLK[3]ILOGIC:MUX.CLKB[3]-------IOB:DCI_MODE[1]-
11 ----------------------------ILOGIC:MUX.CLK[8]~ILOGIC:IFF2_SRVAL~OLOGIC:TFF_INITILOGIC:MUX.CLKB[8]-~OLOGIC:TFF_SRVAL[1]-----IOB:OUTPUT_DELAY
12 ----------------------------~ILOGIC:IFF2_INITILOGIC:MUX.CLK[9]ILOGIC:MUX.CLKB[9]~OLOGIC:INV.T3------IOB:NDRIVE[0]-
13 ----------------------------ILOGIC:MUX.CLK[10]--ILOGIC:MUX.CLKB[10]-------IOB:PSLEW[0]
14 -----------------------------ILOGIC:MUX.CLK[6]ILOGIC:MUX.CLKB[6]-------~IOB:PDRIVE[3]-
15 ----------------------------ILOGIC:MUX.CLK[4]-~OLOGIC:INV.T4ILOGIC:MUX.CLKB[4]-------~IOB:PDRIVE[2]
16 ---------------------------ILOGIC:NUM_CE-ILOGIC:MUX.CLK[7]ILOGIC:MUX.CLKB[7]-OLOGIC:TBYTE_CTL-----~IOB:NDRIVE[3]-
17 ----------------------------ILOGIC:MUX.CLK[5]--ILOGIC:MUX.CLKB[5]-~OLOGIC:TFF_SRVAL[2]-IDELAY:INV.DATAIN---IOB:NSLEW[0]
18 -----------------------------OLOGIC:MUX.CLK[1]OLOGIC:MUX.CLKB[1]-~OLOGIC:TFF_SRVAL[0]-----IOB:NSLEW[1]-
19 ----------------------------OLOGIC:MUX.CLK[0]--OLOGIC:MUX.CLKB[0]-OLOGIC:SERDES_MODE-----IOB:PDRIVE[4]
20 -----------------------------OLOGIC:MUX.CLK[2]OLOGIC:MUX.CLKB[2]-OLOGIC:TBYTE_SRC-------
21 -----------------------------~ILOGIC:IFF3_SRVALOLOGIC:INV.CLKDIV--------IOB:DCI_MODE[0]
22 ----------------------------~ILOGIC:IFF3_INIT--~OLOGIC:RANK3_USED------IOB:LVDS[8]-
23 ---------------------------------------IOB:LVDS[6]
24 -----------------------------OLOGIC:MUX.CLK[3]OLOGIC:MUX.CLKB[3]---IDELAY:INV.C-ODELAY:INV.C-IOB:IBUFDISABLE_SEL-
25 ----------------------------OLOGIC:MUX.CLK[8]--OLOGIC:MUX.CLKB[8]-OLOGIC:TFF_SR_USED-IDELAY:CINVCTRL_SEL-ODELAY:CINVCTRL_SEL-IOB:NSLEW[2]
26 -------------------------------~OLOGIC:INV.CLK1OLOGIC:TRISTATE_WIDTH-----IOB:LVDS[5]-
27 ---------------------------------OLOGIC:OMUX[2]-----IOB:DQS_BIAS_N
28 -----------------------------OLOGIC:MUX.CLK[9]OLOGIC:MUX.CLKB[9]~OLOGIC:INV.CLK2------IOB:NDRIVE[4]-
29 ----------------------------OLOGIC:MUX.CLK[10]~ILOGIC:IFF4_SRVAL-OLOGIC:MUX.CLKB[10]-OLOGIC:OMUX[1]-----IOB:OUTPUT_ENABLE[0]
30 ----------------------------~ILOGIC:IFF4_INITOLOGIC:MUX.CLK[6]OLOGIC:MUX.CLKB[6]OLOGIC:INV.CLKDIVFOLOGIC:OFF_SR_SYNC-~IDELAY:IDELAY_VALUE_CUR[4]-~ODELAY:ODELAY_VALUE_CUR[4]-~IOB:PDRIVE[5]-
31 ----------------------------OLOGIC:MUX.CLK[4]-OLOGIC:CLK_RATIO[1]OLOGIC:MUX.CLKB[4]-~OLOGIC:OFF_SRVAL[1]-----IOB:OUTPUT_ENABLE[1]
32 -----------------------------OLOGIC:MUX.CLK[7]OLOGIC:MUX.CLKB[7]OLOGIC:SELFHEAL--IDELAY:IDELAY_VALUE_INIT[4]-ODELAY:ODELAY_VALUE_INIT[4]-IOB:PDRIVE[1]-
33 ----------------------------OLOGIC:MUX.CLK[5]-OLOGIC:INV.D1OLOGIC:MUX.CLKB[5]-~OLOGIC:OFF_INIT-----IOB:PSLEW[1]
34 ---------------------------ILOGIC:DDR_CLK_EDGE[0]-ILOGIC:MUX.CLKDIVP[0]-OLOGIC:CLK_RATIO[2]------IOB:DQS_BIAS_P-
35 --------------------------ILOGIC:DDR_CLK_EDGE[1]-ILOGIC:MUX.CLKDIVP[1]-OLOGIC:CLK_RATIO[0]--------IOB:LVDS[4]
36 ---------------------------ILOGIC:RANK23_DLY---OLOGIC:CLK_RATIO[3]--~IDELAY:IDELAY_VALUE_CUR[3]-~ODELAY:ODELAY_VALUE_CUR[3]-IOB:NDRIVE[1]-
37 --------------------------ILOGIC:INTERFACE_TYPE[1]--ILOGIC:I_DELAY_ENABLEOLOGIC:DATA_WIDTH[8]--------IOB:PSLEW[2]
38 ---------------------------ILOGIC:SERDES---OLOGIC:INV.D2--IDELAY:IDELAY_VALUE_INIT[3]-ODELAY:ODELAY_VALUE_INIT[3]-IOB:LVDS[3]-
39 -----------------------------ILOGIC:I_TSBYPASS_ENABLE---------~IOB:NDRIVE[5]
40 --------------------------------------IOB:PDRIVE[6]-
41 -------------------------------------ODELAY:FINEDELAY-IOB:NSLEW[3]
42 ---------------------------ILOGIC:SERDES_MODE---OLOGIC:INV.D3--IDELAY:PIPE_SEL-ODELAY:PIPE_SEL-IOB:LVDS[2]-
43 --------------------------ILOGIC:BITSLIP_ENABLE------~OLOGIC:OFF_SRVAL[2]-----IOB:NDRIVE[6]
44 ---------------------------ILOGIC:DATA_RATE----~OLOGIC:OFF_SRVAL[0]-~IDELAY:IDELAY_VALUE_CUR[2]-~ODELAY:ODELAY_VALUE_CUR[2]-IOB:OUTPUT_MISC[5]-
45 --------------------------ILOGIC:DATA_WIDTH[3]--~ILOGIC:INV.D--IDELAY:HIGH_PERFORMANCE_MODE-ODELAY:HIGH_PERFORMANCE_MODE----IOB:VR
46 ---------------------------ILOGIC:DATA_WIDTH[2]ILOGIC:TSBYPASS_MUXOLOGIC:MUX.CLKDIV[1]OLOGIC:MUX.CLKDIVB[1]OLOGIC:INV.D4OLOGIC:OMUX[4]-IDELAY:IDELAY_VALUE_INIT[2]-ODELAY:ODELAY_VALUE_INIT[2]---
47 --------------------------ILOGIC:DATA_WIDTH[1]-OLOGIC:MUX.CLKDIV[0]-OLOGIC:MISR_ENABLEOLOGIC:MUX.CLKDIVB[0]-OLOGIC:OMUX[0]-----IOB:PSLEW[3]
48 ---------------------------ILOGIC:DATA_WIDTH[0]---OLOGIC:MISR_CLK_SELECT[0]OLOGIC:OFF_SR_USED-----IOB:LVDS[1]-
49 --------------------------ILOGIC:INTERFACE_TYPE[3]--ILOGIC:IFF_TSBYPASS_ENABLEOLOGIC:INV.D5--OLOGIC:OMUX[3]-IDELAY:IDELAY_TYPE[1]-ODELAY:ODELAY_TYPE[1]-IOB:NSLEW[4]
50 ---------------------------ILOGIC:INV.CLKDIVP---OLOGIC:INV.D6--~IDELAY:IDELAY_VALUE_CUR[1]-~ODELAY:ODELAY_VALUE_CUR[1]-IOB:PSLEW[4]-
51 --------------------------ILOGIC:INTERFACE_TYPE[4]---OLOGIC:DATA_WIDTH[7]--------IOB:PULL[0]
52 ---------------------------ILOGIC:DYN_CLKDIVP_INV_ENILOGIC:IFF_DELAY_ENABLE--OLOGIC:DATA_WIDTH[6]--IDELAY:IDELAY_VALUE_INIT[1]-ODELAY:ODELAY_VALUE_INIT[1]-IOB:OUTPUT_MISC[4]-
53 --------------------------ILOGIC:INTERFACE_TYPE[2]---OLOGIC:MISR_ENABLE_FDBK--------IOB:PULL[1]
54 ---------------------------ILOGIC:DYN_CLKDIV_INV_EN-OLOGIC:MUX.CLKDIVF[4]OLOGIC:MUX.CLKDIVFB[4]OLOGIC:INV.D7------IOB:OUTPUT_MISC[2]-
55 --------------------------ILOGIC:INV.CLKDIV-OLOGIC:MUX.CLKDIVF[5]-OLOGIC:MISR_RESETOLOGIC:MUX.CLKDIVFB[5]---IDELAY:IDELAY_TYPE[0]-ODELAY:ODELAY_TYPE[0]-IOB:LVDS[0]
56 -------------------------------OLOGIC:DATA_WIDTH[4]--~IDELAY:IDELAY_VALUE_CUR[0]-~ODELAY:ODELAY_VALUE_CUR[0]---
57 --------------------------ILOGIC:INTERFACE_TYPE[0]-OLOGIC:MUX.CLKDIVF[6]-OLOGIC:DATA_WIDTH[3]OLOGIC:MUX.CLKDIVFB[6]-------IOB:PULL_DYNAMIC
58 -------------------------------OLOGIC:MISR_CLK_SELECT[1]--IDELAY:IDELAY_VALUE_INIT[0]-ODELAY:ODELAY_VALUE_INIT[0]-IOB:INPUT_MISC-
59 ----------------------------OLOGIC:MUX.CLKDIVF[2]~ILOGIC:INV.CLK[1]OLOGIC:DATA_WIDTH[5]OLOGIC:MUX.CLKDIVFB[2]-------IOB:PULL[2]
60 ----------------------------ILOGIC:INV.OCLK2OLOGIC:MUX.CLKDIVF[0]OLOGIC:MUX.CLKDIVFB[0]OLOGIC:DATA_WIDTH[2]--------
61 ----------------------------OLOGIC:MUX.CLKDIVF[3]~ILOGIC:INV.CLK[2]OLOGIC:INV.D8OLOGIC:MUX.CLKDIVFB[3]-------IOB:IBUF_MODE[2]
62 ----------------------------~ILOGIC:INV.CLK[0]OLOGIC:MUX.CLKDIVF[1]OLOGIC:MUX.CLKDIVFB[1]OLOGIC:DATA_WIDTH[1]------IOB:IBUF_MODE[1]-
63 -----------------------------ILOGIC:DYN_CLK_INV_ENOLOGIC:DATA_WIDTH[0]--------IOB:IBUF_MODE[0]
ILOGIC:IFF1_INIT[0, 28, 8]
ILOGIC:IFF1_SRVAL[0, 29, 7]
ILOGIC:IFF2_INIT[0, 28, 12]
ILOGIC:IFF2_SRVAL[0, 29, 11]
ILOGIC:IFF3_INIT[0, 28, 22]
ILOGIC:IFF3_SRVAL[0, 29, 21]
ILOGIC:IFF4_INIT[0, 28, 30]
ILOGIC:IFF4_SRVAL[0, 29, 29]
ILOGIC:IFF_LATCH[0, 26, 7]
ILOGIC:INV.D[0, 29, 45]
ODELAY:INV.ODATAIN[0, 35, 8]
OLOGIC:INV.CLK1[0, 31, 26]
OLOGIC:INV.CLK2[0, 31, 28]
OLOGIC:INV.T1[0, 30, 3]
OLOGIC:INV.T2[0, 30, 7]
OLOGIC:INV.T3[0, 31, 12]
OLOGIC:INV.T4[0, 30, 15]
OLOGIC:OFF_INIT[0, 33, 33]
OLOGIC:RANK3_USED[0, 31, 22]
OLOGIC:TFF_INIT[0, 30, 11]
Inverted~[0]
IDELAY:CINVCTRL_SEL[0, 35, 25]
IDELAY:ENABLE[0, 32, 9]
IDELAY:HIGH_PERFORMANCE_MODE[0, 32, 45]
IDELAY:INV.C[0, 34, 24]
IDELAY:INV.DATAIN[0, 35, 17]
IDELAY:INV.IDATAIN[0, 33, 8]
IDELAY:PIPE_SEL[0, 34, 42]
ILOGIC:BITSLIP_ENABLE[0, 26, 43]
ILOGIC:DYN_CLKDIVP_INV_EN[0, 27, 52]
ILOGIC:DYN_CLKDIV_INV_EN[0, 27, 54]
ILOGIC:DYN_CLK_INV_EN[0, 29, 63]
ILOGIC:D_EMU1[0, 29, 1]
ILOGIC:D_EMU2[0, 28, 2]
ILOGIC:IFF_DELAY_ENABLE[0, 28, 52]
ILOGIC:IFF_SR_USED[0, 27, 6]
ILOGIC:IFF_TSBYPASS_ENABLE[0, 29, 49]
ILOGIC:INV.CLKDIV[0, 26, 55]
ILOGIC:INV.CLKDIVP[0, 27, 50]
ILOGIC:INV.OCLK1[0, 28, 0]
ILOGIC:INV.OCLK2[0, 28, 60]
ILOGIC:I_DELAY_ENABLE[0, 29, 37]
ILOGIC:I_TSBYPASS_ENABLE[0, 29, 39]
ILOGIC:RANK23_DLY[0, 27, 36]
ILOGIC:SERDES[0, 27, 38]
IOB:DCIUPDATEMODE_QUIET[0, 39, 7]
IOB:DCI_T[0, 38, 0]
IOB:DQS_BIAS_N[0, 39, 27]
IOB:DQS_BIAS_P[0, 38, 34]
IOB:INPUT_MISC[0, 38, 58]
IOB:OUTPUT_DELAY[0, 39, 11]
IOB:PULL_DYNAMIC[0, 39, 57]
IOB:VR[0, 39, 45]
ODELAY:CINVCTRL_SEL[0, 37, 25]
ODELAY:ENABLE[0, 34, 9]
ODELAY:HIGH_PERFORMANCE_MODE[0, 34, 45]
ODELAY:INV.C[0, 36, 24]
ODELAY:PIPE_SEL[0, 36, 42]
OLOGIC:INV.CLKDIV[0, 30, 21]
OLOGIC:INV.CLKDIVF[0, 31, 30]
OLOGIC:INV.D1[0, 30, 33]
OLOGIC:INV.D2[0, 31, 38]
OLOGIC:INV.D3[0, 31, 42]
OLOGIC:INV.D4[0, 31, 46]
OLOGIC:INV.D5[0, 30, 49]
OLOGIC:INV.D6[0, 31, 50]
OLOGIC:INV.D7[0, 31, 54]
OLOGIC:INV.D8[0, 30, 61]
OLOGIC:MISR_ENABLE[0, 30, 47]
OLOGIC:MISR_ENABLE_FDBK[0, 30, 53]
OLOGIC:MISR_RESET[0, 30, 55]
OLOGIC:OFF_SR_SYNC[0, 32, 30]
OLOGIC:OFF_SR_USED[0, 32, 48]
OLOGIC:SELFHEAL[0, 31, 32]
OLOGIC:SERDES[0, 33, 9]
OLOGIC:TBYTE_CTL[0, 32, 16]
OLOGIC:TBYTE_SRC[0, 32, 20]
OLOGIC:TFF_SR_SYNC[0, 32, 8]
OLOGIC:TFF_SR_USED[0, 33, 25]
Non-inverted[0]
ILOGIC:INTERFACE_TYPE[0, 26, 51][0, 26, 49][0, 26, 53][0, 26, 37][0, 26, 57]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC:NUM_CE[0, 27, 16]
10
21
ILOGIC:DDR_CLK_EDGE[0, 26, 35][0, 27, 34]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC:SERDES_MODE[0, 27, 42]
OLOGIC:SERDES_MODE[0, 33, 19]
MASTER0
SLAVE1
ILOGIC:DATA_RATE[0, 27, 44]
DDR0
SDR1
ILOGIC:DATA_WIDTH[0, 26, 45][0, 27, 46][0, 26, 47][0, 27, 48]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
OLOGIC:MUX.CLK[0, 28, 29][0, 29, 28][0, 28, 25][0, 29, 32][0, 29, 30][0, 28, 33][0, 28, 31][0, 29, 24][0, 29, 20][0, 29, 18][0, 28, 19]
OLOGIC:MUX.CLKB[0, 31, 29][0, 30, 28][0, 31, 25][0, 30, 32][0, 30, 30][0, 31, 33][0, 31, 31][0, 30, 24][0, 30, 20][0, 30, 18][0, 31, 19]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
ILOGIC:TSBYPASS_MUX[0, 28, 46]
T0
GND1
OLOGIC:MUX.CLKDIV[0, 29, 46][0, 28, 47]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
ILOGIC:INV.CLK[0, 29, 61][0, 29, 59][0, 28, 62]
OLOGIC:OFF_SRVAL[0, 33, 43][0, 33, 31][0, 32, 44]
OLOGIC:TFF_SRVAL[0, 33, 17][0, 33, 11][0, 32, 18]
Inverted~[2]~[1]~[0]
ILOGIC:MUX.CLK[0, 28, 13][0, 29, 12][0, 28, 11][0, 29, 16][0, 29, 14][0, 28, 17][0, 28, 15][0, 29, 10][0, 28, 3][0, 28, 1][0, 29, 2]
ILOGIC:MUX.CLKB[0, 31, 13][0, 30, 12][0, 31, 11][0, 30, 16][0, 30, 14][0, 31, 17][0, 31, 15][0, 30, 10][0, 31, 3][0, 31, 1][0, 30, 2]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
ILOGIC:SRTYPE[0, 29, 3]
ASYNC0
SYNC1
IDELAY:FINEDELAY[0, 29, 5]
ODELAY:FINEDELAY[0, 37, 41]
BYPASS0
ADD_DLY1
ILOGIC:MUX.CLKDIVP[0, 28, 35][0, 29, 34]
NONE00
CLKDIV01
PHASER10
OLOGIC:MUX.CLKDIVF[0, 28, 57][0, 28, 55][0, 29, 54][0, 28, 61][0, 28, 59][0, 29, 62][0, 29, 60]
OLOGIC:MUX.CLKDIVFB[0, 31, 57][0, 31, 55][0, 30, 54][0, 31, 61][0, 31, 59][0, 30, 62][0, 30, 60]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
OLOGIC:CLK_RATIO[0, 31, 36][0, 31, 34][0, 30, 31][0, 30, 35]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC:DATA_WIDTH[0, 30, 37][0, 30, 51][0, 31, 52][0, 30, 59][0, 31, 56][0, 30, 57][0, 31, 60][0, 31, 62][0, 30, 63]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC:MUX.CLKDIVB[0, 30, 46][0, 31, 47]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC:MISR_CLK_SELECT[0, 31, 58][0, 31, 48]
NONE00
CLK101
CLK210
OLOGIC:TMUX[0, 33, 3][0, 32, 4][0, 32, 6][0, 33, 5][0, 32, 2]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC:TRISTATE_WIDTH[0, 32, 26]
10
41
OLOGIC:OMUX[0, 32, 46][0, 33, 49][0, 33, 27][0, 33, 29][0, 33, 47]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY:DELAY_SRC[0, 34, 6][0, 35, 7][0, 35, 5][0, 34, 8]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
IDELAY:IDELAY_VALUE_CUR[0, 34, 30][0, 34, 36][0, 34, 44][0, 34, 50][0, 34, 56]
ODELAY:ODELAY_VALUE_CUR[0, 36, 30][0, 36, 36][0, 36, 44][0, 36, 50][0, 36, 56]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY:IDELAY_VALUE_INIT[0, 34, 32][0, 34, 38][0, 34, 46][0, 34, 52][0, 34, 58]
IOB:NSLEW[0, 39, 49][0, 39, 41][0, 39, 25][0, 38, 18][0, 39, 17]
IOB:PSLEW[0, 38, 50][0, 39, 47][0, 39, 37][0, 39, 33][0, 39, 13]
ODELAY:ODELAY_VALUE_INIT[0, 36, 32][0, 36, 38][0, 36, 46][0, 36, 52][0, 36, 58]
Non-inverted[4][3][2][1][0]
IDELAY:IDELAY_TYPE[0, 35, 49][0, 35, 55]
ODELAY:ODELAY_TYPE[0, 37, 49][0, 37, 55]
FIXED00
VARIABLE01
VAR_LOAD11
ODELAY:DELAY_SRC[0, 36, 6][0, 37, 7][0, 36, 8]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
IOB:PDRIVE[0, 38, 40][0, 38, 30][0, 39, 19][0, 38, 14][0, 39, 15][0, 38, 32][0, 38, 2]
Mixed inversion[6]~[5][4]~[3]~[2][1][0]
IOB:NDRIVE[0, 39, 43][0, 39, 39][0, 38, 28][0, 38, 16][0, 38, 8][0, 38, 36][0, 38, 12]
Mixed inversion[6]~[5][4]~[3][2][1][0]
IOB:DCITERMDISABLE_SEL[0, 39, 1]
IOB:IBUFDISABLE_SEL[0, 38, 24]
GND0
I1
IOB:OUTPUT_MISC[0, 38, 44][0, 38, 52][0, 38, 6][0, 38, 54][0, 39, 3][0, 39, 5]
Non-inverted[5][4][3][2][1][0]
IOB:DCI_MODE[0, 38, 10][0, 39, 21]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11
IOB:OUTPUT_ENABLE[0, 39, 31][0, 39, 29]
Non-inverted[1][0]
IOB:PULL[0, 39, 59][0, 39, 53][0, 39, 51]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB:LVDS[0, 38, 22][0, 39, 9][0, 39, 23][0, 38, 26][0, 39, 35][0, 38, 38][0, 38, 42][0, 38, 48][0, 39, 55]
Non-inverted[8][7][6][5][4][3][2][1][0]
IOB:IBUF_MODE[0, 39, 61][0, 38, 62][0, 39, 63]
OFF000
VREF_LP001
CMOS011
VREF_HP101

Bitstream — IO_HP_TOP

IO_HP_TOP bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC:DYN_CLK_INV_EN--OLOGIC:DATA_WIDTH[0]------IOB:IBUF_MODE[0]-
1 ----------------------------OLOGIC:MUX.CLKDIVF[1]~ILOGIC:INV.CLK[2]OLOGIC:DATA_WIDTH[1]OLOGIC:MUX.CLKDIVFB[1]-------IOB:IBUF_MODE[1]
2 ----------------------------~ILOGIC:INV.CLK[0]OLOGIC:MUX.CLKDIVF[3]OLOGIC:MUX.CLKDIVFB[3]OLOGIC:INV.D8------IOB:IBUF_MODE[2]-
3 ----------------------------OLOGIC:MUX.CLKDIVF[0]ILOGIC:INV.OCLK2OLOGIC:DATA_WIDTH[2]OLOGIC:MUX.CLKDIVFB[0]--------
4 ----------------------------~ILOGIC:INV.CLK[1]OLOGIC:MUX.CLKDIVF[2]OLOGIC:MUX.CLKDIVFB[2]OLOGIC:DATA_WIDTH[5]------IOB:PULL[2]-
5 ------------------------------OLOGIC:MISR_CLK_SELECT[1]----IDELAY:IDELAY_VALUE_INIT[0]-ODELAY:ODELAY_VALUE_INIT[0]-IOB:INPUT_MISC
6 ---------------------------ILOGIC:INTERFACE_TYPE[0]-OLOGIC:MUX.CLKDIVF[6]OLOGIC:MUX.CLKDIVFB[6]OLOGIC:DATA_WIDTH[3]------IOB:PULL_DYNAMIC-
7 ------------------------------OLOGIC:DATA_WIDTH[4]----~IDELAY:IDELAY_VALUE_CUR[0]-~ODELAY:ODELAY_VALUE_CUR[0]--
8 ---------------------------ILOGIC:INV.CLKDIV-OLOGIC:MUX.CLKDIVF[5]OLOGIC:MUX.CLKDIVFB[5]OLOGIC:MISR_RESET--IDELAY:IDELAY_TYPE[0]-ODELAY:ODELAY_TYPE[0]-IOB:LVDS[0]-
9 --------------------------ILOGIC:DYN_CLKDIV_INV_EN-OLOGIC:MUX.CLKDIVF[4]-OLOGIC:INV.D7OLOGIC:MUX.CLKDIVFB[4]-------IOB:OUTPUT_MISC[2]
10 ---------------------------ILOGIC:INTERFACE_TYPE[2]---OLOGIC:MISR_ENABLE_FDBK------IOB:PULL[1]-
11 --------------------------ILOGIC:DYN_CLKDIVP_INV_EN--ILOGIC:IFF_DELAY_ENABLEOLOGIC:DATA_WIDTH[6]----IDELAY:IDELAY_VALUE_INIT[1]-ODELAY:ODELAY_VALUE_INIT[1]-IOB:OUTPUT_MISC[4]
12 ---------------------------ILOGIC:INTERFACE_TYPE[4]---OLOGIC:DATA_WIDTH[7]------IOB:PULL[0]-
13 --------------------------ILOGIC:INV.CLKDIVP---OLOGIC:INV.D6----~IDELAY:IDELAY_VALUE_CUR[1]-~ODELAY:ODELAY_VALUE_CUR[1]-IOB:PSLEW[4]
14 ---------------------------ILOGIC:INTERFACE_TYPE[3]ILOGIC:IFF_TSBYPASS_ENABLE--OLOGIC:INV.D5OLOGIC:OMUX[3]-IDELAY:IDELAY_TYPE[1]-ODELAY:ODELAY_TYPE[1]-IOB:NSLEW[4]-
15 --------------------------ILOGIC:DATA_WIDTH[0]---OLOGIC:MISR_CLK_SELECT[0]--OLOGIC:OFF_SR_USED-----IOB:LVDS[1]
16 ---------------------------ILOGIC:DATA_WIDTH[1]-OLOGIC:MUX.CLKDIV[0]OLOGIC:MUX.CLKDIVB[0]OLOGIC:MISR_ENABLEOLOGIC:OMUX[0]-----IOB:PSLEW[3]-
17 --------------------------ILOGIC:DATA_WIDTH[2]-OLOGIC:MUX.CLKDIV[1]ILOGIC:TSBYPASS_MUXOLOGIC:INV.D4OLOGIC:MUX.CLKDIVB[1]-OLOGIC:OMUX[4]-IDELAY:IDELAY_VALUE_INIT[2]-ODELAY:ODELAY_VALUE_INIT[2]--
18 ---------------------------ILOGIC:DATA_WIDTH[3]~ILOGIC:INV.D----IDELAY:HIGH_PERFORMANCE_MODE-ODELAY:HIGH_PERFORMANCE_MODE--IOB:VR-
19 --------------------------ILOGIC:DATA_RATE------~OLOGIC:OFF_SRVAL[2]-~IDELAY:IDELAY_VALUE_CUR[2]-~ODELAY:ODELAY_VALUE_CUR[2]-IOB:OUTPUT_MISC[5]
20 ---------------------------ILOGIC:BITSLIP_ENABLE----~OLOGIC:OFF_SRVAL[0]-----IOB:NDRIVE[6]-
21 --------------------------ILOGIC:SERDES_MODE---OLOGIC:INV.D3----IDELAY:PIPE_SEL-ODELAY:PIPE_SEL-IOB:LVDS[2]
22 ------------------------------------ODELAY:FINEDELAY-IOB:NSLEW[3]-
23 ---------------------------------------IOB:PDRIVE[6]
24 ----------------------------ILOGIC:I_TSBYPASS_ENABLE---------~IOB:NDRIVE[5]-
25 --------------------------ILOGIC:SERDES---OLOGIC:INV.D2----IDELAY:IDELAY_VALUE_INIT[3]-ODELAY:ODELAY_VALUE_INIT[3]-IOB:LVDS[3]
26 ---------------------------ILOGIC:INTERFACE_TYPE[1]ILOGIC:I_DELAY_ENABLE--OLOGIC:DATA_WIDTH[8]------IOB:PSLEW[2]-
27 --------------------------ILOGIC:RANK23_DLY---OLOGIC:CLK_RATIO[3]----~IDELAY:IDELAY_VALUE_CUR[3]-~ODELAY:ODELAY_VALUE_CUR[3]-IOB:NDRIVE[1]
28 ---------------------------ILOGIC:DDR_CLK_EDGE[1]-ILOGIC:MUX.CLKDIVP[1]-OLOGIC:CLK_RATIO[0]------IOB:LVDS[4]-
29 --------------------------ILOGIC:DDR_CLK_EDGE[0]-ILOGIC:MUX.CLKDIVP[0]-OLOGIC:CLK_RATIO[2]--------IOB:DQS_BIAS_P
30 -----------------------------OLOGIC:MUX.CLK[5]OLOGIC:MUX.CLKB[5]OLOGIC:INV.D1~OLOGIC:OFF_INIT-----IOB:PSLEW[1]-
31 ----------------------------OLOGIC:MUX.CLK[7]-OLOGIC:SELFHEALOLOGIC:MUX.CLKB[7]---IDELAY:IDELAY_VALUE_INIT[4]-ODELAY:ODELAY_VALUE_INIT[4]-IOB:PDRIVE[1]
32 -----------------------------OLOGIC:MUX.CLK[4]OLOGIC:MUX.CLKB[4]OLOGIC:CLK_RATIO[1]~OLOGIC:OFF_SRVAL[1]-----IOB:OUTPUT_ENABLE[0]-
33 ----------------------------OLOGIC:MUX.CLK[6]~ILOGIC:IFF4_INITOLOGIC:INV.CLKDIVFOLOGIC:MUX.CLKB[6]-OLOGIC:OFF_SR_SYNC-~IDELAY:IDELAY_VALUE_CUR[4]-~ODELAY:ODELAY_VALUE_CUR[4]-~IOB:PDRIVE[5]
34 ----------------------------~ILOGIC:IFF4_SRVALOLOGIC:MUX.CLK[10]OLOGIC:MUX.CLKB[10]-OLOGIC:OMUX[1]-----IOB:OUTPUT_ENABLE[1]-
35 ----------------------------OLOGIC:MUX.CLK[9]-~OLOGIC:INV.CLK2OLOGIC:MUX.CLKB[9]-------IOB:NDRIVE[4]
36 --------------------------------OLOGIC:OMUX[2]-----IOB:DQS_BIAS_N-
37 ------------------------------~OLOGIC:INV.CLK1--OLOGIC:TRISTATE_WIDTH-----IOB:LVDS[5]
38 -----------------------------OLOGIC:MUX.CLK[8]OLOGIC:MUX.CLKB[8]-OLOGIC:TFF_SR_USED-IDELAY:CINVCTRL_SEL-ODELAY:CINVCTRL_SEL-IOB:NSLEW[2]-
39 ----------------------------OLOGIC:MUX.CLK[3]--OLOGIC:MUX.CLKB[3]---IDELAY:INV.C-ODELAY:INV.C-IOB:IBUFDISABLE_SEL
40 --------------------------------------IOB:LVDS[6]-
41 -----------------------------~ILOGIC:IFF3_INIT~OLOGIC:RANK3_USED--------IOB:LVDS[8]
42 ----------------------------~ILOGIC:IFF3_SRVAL--OLOGIC:INV.CLKDIV------IOB:DCI_MODE[0]-
43 ----------------------------OLOGIC:MUX.CLK[2]--OLOGIC:MUX.CLKB[2]-OLOGIC:TBYTE_SRC------
44 -----------------------------OLOGIC:MUX.CLK[0]OLOGIC:MUX.CLKB[0]-OLOGIC:SERDES_MODE-----IOB:PDRIVE[4]-
45 ----------------------------OLOGIC:MUX.CLK[1]--OLOGIC:MUX.CLKB[1]-~OLOGIC:TFF_SRVAL[2]-----IOB:NSLEW[1]
46 -----------------------------ILOGIC:MUX.CLK[5]ILOGIC:MUX.CLKB[5]-~OLOGIC:TFF_SRVAL[0]-IDELAY:INV.DATAIN---IOB:NSLEW[0]-
47 --------------------------ILOGIC:NUM_CE-ILOGIC:MUX.CLK[7]--ILOGIC:MUX.CLKB[7]-OLOGIC:TBYTE_CTL-----~IOB:NDRIVE[3]
48 -----------------------------ILOGIC:MUX.CLK[4]ILOGIC:MUX.CLKB[4]~OLOGIC:INV.T4------~IOB:PDRIVE[2]-
49 ----------------------------ILOGIC:MUX.CLK[6]--ILOGIC:MUX.CLKB[6]-------~IOB:PDRIVE[3]
50 -----------------------------ILOGIC:MUX.CLK[10]ILOGIC:MUX.CLKB[10]-------IOB:PSLEW[0]-
51 ----------------------------ILOGIC:MUX.CLK[9]~ILOGIC:IFF2_INIT~OLOGIC:INV.T3ILOGIC:MUX.CLKB[9]-------IOB:NDRIVE[0]
52 ----------------------------~ILOGIC:IFF2_SRVALILOGIC:MUX.CLK[8]ILOGIC:MUX.CLKB[8]~OLOGIC:TFF_INIT~OLOGIC:TFF_SRVAL[1]-----IOB:OUTPUT_DELAY-
53 ----------------------------ILOGIC:MUX.CLK[3]--ILOGIC:MUX.CLKB[3]-------IOB:DCI_MODE[1]
54 --------------------------------OLOGIC:SERDESIDELAY:ENABLE-ODELAY:ENABLE--IOB:LVDS[7]-
55 -----------------------------~ILOGIC:IFF1_INIT--IDELAY:INV.IDATAINOLOGIC:TFF_SR_SYNC~ODELAY:INV.ODATAINIDELAY:DELAY_SRC[0]-ODELAY:DELAY_SRC[0]-IOB:NDRIVE[2]
56 ---------------------------~ILOGIC:IFF_LATCH~ILOGIC:IFF1_SRVAL--~OLOGIC:INV.T2--IDELAY:DELAY_SRC[2]-ODELAY:DELAY_SRC[1]-IOB:DCIUPDATEMODE_QUIET-
57 --------------------------ILOGIC:IFF_SR_USED------OLOGIC:TMUX[2]-IDELAY:DELAY_SRC[3]-ODELAY:DELAY_SRC[2]-IOB:OUTPUT_MISC[3]
58 ----------------------------IDELAY:FINEDELAY---OLOGIC:TMUX[1]-IDELAY:DELAY_SRC[1]---IOB:OUTPUT_MISC[0]-
59 ---------------------------------OLOGIC:TMUX[3]------
60 ----------------------------ILOGIC:SRTYPEILOGIC:MUX.CLK[2]ILOGIC:MUX.CLKB[2]~OLOGIC:INV.T1OLOGIC:TMUX[4]-----IOB:OUTPUT_MISC[1]-
61 ----------------------------ILOGIC:MUX.CLK[0]ILOGIC:D_EMU2-ILOGIC:MUX.CLKB[0]-OLOGIC:TMUX[0]-----IOB:PDRIVE[0]
62 ----------------------------ILOGIC:D_EMU1ILOGIC:MUX.CLK[1]ILOGIC:MUX.CLKB[1]-------IOB:DCITERMDISABLE_SEL-
63 -----------------------------ILOGIC:INV.OCLK1---------IOB:DCI_T
IDELAY:CINVCTRL_SEL[0, 34, 38]
IDELAY:ENABLE[0, 33, 54]
IDELAY:HIGH_PERFORMANCE_MODE[0, 33, 18]
IDELAY:INV.C[0, 35, 39]
IDELAY:INV.DATAIN[0, 34, 46]
IDELAY:INV.IDATAIN[0, 32, 55]
IDELAY:PIPE_SEL[0, 35, 21]
ILOGIC:BITSLIP_ENABLE[0, 27, 20]
ILOGIC:DYN_CLKDIVP_INV_EN[0, 26, 11]
ILOGIC:DYN_CLKDIV_INV_EN[0, 26, 9]
ILOGIC:DYN_CLK_INV_EN[0, 28, 0]
ILOGIC:D_EMU1[0, 28, 62]
ILOGIC:D_EMU2[0, 29, 61]
ILOGIC:IFF_DELAY_ENABLE[0, 29, 11]
ILOGIC:IFF_SR_USED[0, 26, 57]
ILOGIC:IFF_TSBYPASS_ENABLE[0, 28, 14]
ILOGIC:INV.CLKDIV[0, 27, 8]
ILOGIC:INV.CLKDIVP[0, 26, 13]
ILOGIC:INV.OCLK1[0, 29, 63]
ILOGIC:INV.OCLK2[0, 29, 3]
ILOGIC:I_DELAY_ENABLE[0, 28, 26]
ILOGIC:I_TSBYPASS_ENABLE[0, 28, 24]
ILOGIC:RANK23_DLY[0, 26, 27]
ILOGIC:SERDES[0, 26, 25]
IOB:DCIUPDATEMODE_QUIET[0, 38, 56]
IOB:DCI_T[0, 39, 63]
IOB:DQS_BIAS_N[0, 38, 36]
IOB:DQS_BIAS_P[0, 39, 29]
IOB:INPUT_MISC[0, 39, 5]
IOB:OUTPUT_DELAY[0, 38, 52]
IOB:PULL_DYNAMIC[0, 38, 6]
IOB:VR[0, 38, 18]
ODELAY:CINVCTRL_SEL[0, 36, 38]
ODELAY:ENABLE[0, 35, 54]
ODELAY:HIGH_PERFORMANCE_MODE[0, 35, 18]
ODELAY:INV.C[0, 37, 39]
ODELAY:PIPE_SEL[0, 37, 21]
OLOGIC:INV.CLKDIV[0, 31, 42]
OLOGIC:INV.CLKDIVF[0, 30, 33]
OLOGIC:INV.D1[0, 31, 30]
OLOGIC:INV.D2[0, 30, 25]
OLOGIC:INV.D3[0, 30, 21]
OLOGIC:INV.D4[0, 30, 17]
OLOGIC:INV.D5[0, 31, 14]
OLOGIC:INV.D6[0, 30, 13]
OLOGIC:INV.D7[0, 30, 9]
OLOGIC:INV.D8[0, 31, 2]
OLOGIC:MISR_ENABLE[0, 31, 16]
OLOGIC:MISR_ENABLE_FDBK[0, 31, 10]
OLOGIC:MISR_RESET[0, 31, 8]
OLOGIC:OFF_SR_SYNC[0, 33, 33]
OLOGIC:OFF_SR_USED[0, 33, 15]
OLOGIC:SELFHEAL[0, 30, 31]
OLOGIC:SERDES[0, 32, 54]
OLOGIC:TBYTE_CTL[0, 33, 47]
OLOGIC:TBYTE_SRC[0, 33, 43]
OLOGIC:TFF_SR_SYNC[0, 33, 55]
OLOGIC:TFF_SR_USED[0, 32, 38]
Non-inverted[0]
ILOGIC:DATA_WIDTH[0, 27, 18][0, 26, 17][0, 27, 16][0, 26, 15]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
ILOGIC:DATA_RATE[0, 26, 19]
DDR0
SDR1
ILOGIC:SERDES_MODE[0, 26, 21]
OLOGIC:SERDES_MODE[0, 32, 44]
MASTER0
SLAVE1
ILOGIC:DDR_CLK_EDGE[0, 27, 28][0, 26, 29]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC:NUM_CE[0, 26, 47]
10
21
ILOGIC:INTERFACE_TYPE[0, 27, 12][0, 27, 14][0, 27, 10][0, 27, 26][0, 27, 6]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC:IFF1_INIT[0, 29, 55]
ILOGIC:IFF1_SRVAL[0, 28, 56]
ILOGIC:IFF2_INIT[0, 29, 51]
ILOGIC:IFF2_SRVAL[0, 28, 52]
ILOGIC:IFF3_INIT[0, 29, 41]
ILOGIC:IFF3_SRVAL[0, 28, 42]
ILOGIC:IFF4_INIT[0, 29, 33]
ILOGIC:IFF4_SRVAL[0, 28, 34]
ILOGIC:IFF_LATCH[0, 27, 56]
ILOGIC:INV.D[0, 28, 18]
ODELAY:INV.ODATAIN[0, 34, 55]
OLOGIC:INV.CLK1[0, 30, 37]
OLOGIC:INV.CLK2[0, 30, 35]
OLOGIC:INV.T1[0, 31, 60]
OLOGIC:INV.T2[0, 31, 56]
OLOGIC:INV.T3[0, 30, 51]
OLOGIC:INV.T4[0, 31, 48]
OLOGIC:OFF_INIT[0, 32, 30]
OLOGIC:RANK3_USED[0, 30, 41]
OLOGIC:TFF_INIT[0, 31, 52]
Inverted~[0]
ILOGIC:INV.CLK[0, 29, 1][0, 28, 4][0, 28, 2]
OLOGIC:OFF_SRVAL[0, 33, 19][0, 32, 32][0, 32, 20]
OLOGIC:TFF_SRVAL[0, 33, 45][0, 32, 52][0, 32, 46]
Inverted~[2]~[1]~[0]
OLOGIC:MUX.CLKDIVF[0, 29, 6][0, 29, 8][0, 28, 9][0, 29, 2][0, 29, 4][0, 28, 1][0, 28, 3]
OLOGIC:MUX.CLKDIVFB[0, 30, 6][0, 30, 8][0, 31, 9][0, 30, 2][0, 30, 4][0, 31, 1][0, 31, 3]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
ILOGIC:MUX.CLKDIVP[0, 29, 28][0, 28, 29]
NONE00
CLKDIV01
PHASER10
IDELAY:FINEDELAY[0, 28, 58]
ODELAY:FINEDELAY[0, 36, 22]
BYPASS0
ADD_DLY1
ILOGIC:SRTYPE[0, 28, 60]
ASYNC0
SYNC1
ILOGIC:MUX.CLK[0, 29, 50][0, 28, 51][0, 29, 52][0, 28, 47][0, 28, 49][0, 29, 46][0, 29, 48][0, 28, 53][0, 29, 60][0, 29, 62][0, 28, 61]
ILOGIC:MUX.CLKB[0, 30, 50][0, 31, 51][0, 30, 52][0, 31, 47][0, 31, 49][0, 30, 46][0, 30, 48][0, 31, 53][0, 30, 60][0, 30, 62][0, 31, 61]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
OLOGIC:MUX.CLKDIV[0, 28, 17][0, 29, 16]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
ILOGIC:TSBYPASS_MUX[0, 29, 17]
T0
GND1
OLOGIC:MUX.CLK[0, 29, 34][0, 28, 35][0, 29, 38][0, 28, 31][0, 28, 33][0, 29, 30][0, 29, 32][0, 28, 39][0, 28, 43][0, 28, 45][0, 29, 44]
OLOGIC:MUX.CLKB[0, 30, 34][0, 31, 35][0, 30, 38][0, 31, 31][0, 31, 33][0, 30, 30][0, 30, 32][0, 31, 39][0, 31, 43][0, 31, 45][0, 30, 44]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
OLOGIC:MISR_CLK_SELECT[0, 30, 5][0, 30, 15]
NONE00
CLK101
CLK210
OLOGIC:MUX.CLKDIVB[0, 31, 17][0, 30, 16]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC:DATA_WIDTH[0, 31, 26][0, 31, 12][0, 30, 11][0, 31, 4][0, 30, 7][0, 31, 6][0, 30, 3][0, 30, 1][0, 31, 0]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC:CLK_RATIO[0, 30, 27][0, 30, 29][0, 31, 32][0, 31, 28]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC:OMUX[0, 33, 17][0, 32, 14][0, 32, 36][0, 32, 34][0, 32, 16]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC:TRISTATE_WIDTH[0, 33, 37]
10
41
OLOGIC:TMUX[0, 32, 60][0, 33, 59][0, 33, 57][0, 32, 58][0, 33, 61]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY:IDELAY_TYPE[0, 34, 14][0, 34, 8]
ODELAY:ODELAY_TYPE[0, 36, 14][0, 36, 8]
FIXED00
VARIABLE01
VAR_LOAD11
IDELAY:IDELAY_VALUE_INIT[0, 35, 31][0, 35, 25][0, 35, 17][0, 35, 11][0, 35, 5]
IOB:NSLEW[0, 38, 14][0, 38, 22][0, 38, 38][0, 39, 45][0, 38, 46]
IOB:PSLEW[0, 39, 13][0, 38, 16][0, 38, 26][0, 38, 30][0, 38, 50]
ODELAY:ODELAY_VALUE_INIT[0, 37, 31][0, 37, 25][0, 37, 17][0, 37, 11][0, 37, 5]
Non-inverted[4][3][2][1][0]
IDELAY:IDELAY_VALUE_CUR[0, 35, 33][0, 35, 27][0, 35, 19][0, 35, 13][0, 35, 7]
ODELAY:ODELAY_VALUE_CUR[0, 37, 33][0, 37, 27][0, 37, 19][0, 37, 13][0, 37, 7]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY:DELAY_SRC[0, 35, 57][0, 34, 56][0, 34, 58][0, 35, 55]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
ODELAY:DELAY_SRC[0, 37, 57][0, 36, 56][0, 37, 55]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
IOB:IBUF_MODE[0, 38, 2][0, 39, 1][0, 38, 0]
OFF000
VREF_LP001
CMOS011
VREF_HP101
IOB:LVDS[0, 39, 41][0, 38, 54][0, 38, 40][0, 39, 37][0, 38, 28][0, 39, 25][0, 39, 21][0, 39, 15][0, 38, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
IOB:PULL[0, 38, 4][0, 38, 10][0, 38, 12]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB:OUTPUT_ENABLE[0, 38, 34][0, 38, 32]
Non-inverted[1][0]
IOB:DCI_MODE[0, 39, 53][0, 38, 42]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11
IOB:OUTPUT_MISC[0, 39, 19][0, 39, 11][0, 39, 57][0, 39, 9][0, 38, 60][0, 38, 58]
Non-inverted[5][4][3][2][1][0]
IOB:DCITERMDISABLE_SEL[0, 38, 62]
IOB:IBUFDISABLE_SEL[0, 39, 39]
GND0
I1
IOB:NDRIVE[0, 38, 20][0, 38, 24][0, 39, 35][0, 39, 47][0, 39, 55][0, 39, 27][0, 39, 51]
Mixed inversion[6]~[5][4]~[3][2][1][0]
IOB:PDRIVE[0, 39, 23][0, 39, 33][0, 38, 44][0, 39, 49][0, 38, 48][0, 39, 31][0, 39, 61]
Mixed inversion[6]~[5][4]~[3]~[2][1][0]

Bitstream — IO_HR_PAIR

IO_HR_PAIR bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC0:DYN_CLK_INV_EN--OLOGIC0:DATA_WIDTH[0]------IOB0:DRIVE[0]-
1 ----------------------------OLOGIC0:MUX.CLKDIVF[1]~ILOGIC0:INV.CLK[2]OLOGIC0:DATA_WIDTH[1]OLOGIC0:MUX.CLKDIVFB[1]-------IOB0:DRIVE[1]
2 ----------------------------~ILOGIC0:INV.CLK[0]OLOGIC0:MUX.CLKDIVF[3]OLOGIC0:MUX.CLKDIVFB[3]OLOGIC0:INV.D8------~IOB0:DRIVE[2]-
3 ----------------------------OLOGIC0:MUX.CLKDIVF[0]ILOGIC0:INV.OCLK2OLOGIC0:DATA_WIDTH[2]OLOGIC0:MUX.CLKDIVFB[0]-------IOB0:DRIVE[3]
4 ----------------------------~ILOGIC0:INV.CLK[1]OLOGIC0:MUX.CLKDIVF[2]OLOGIC0:MUX.CLKDIVFB[2]OLOGIC0:DATA_WIDTH[5]------IOB0:IN_TERM[0]-
5 ------------------------------OLOGIC0:MISR_CLK_SELECT[1]----IDELAY0:IDELAY_VALUE_INIT[0]---IOB0:IN_TERM[2]
6 ---------------------------ILOGIC0:INTERFACE_TYPE[0]-OLOGIC0:MUX.CLKDIVF[6]OLOGIC0:MUX.CLKDIVFB[6]OLOGIC0:DATA_WIDTH[3]------IOB0:IN_TERM[3]-
7 -----------------------------ILOGIC0:INV.ZHOLD_IFFOLOGIC0:DATA_WIDTH[4]----~IDELAY0:IDELAY_VALUE_CUR[0]---IOB0:IN_TERM[1]
8 ---------------------------ILOGIC0:INV.CLKDIVILOGIC0:IFF_ZHOLDOLOGIC0:MUX.CLKDIVF[5]OLOGIC0:MUX.CLKDIVFB[5]OLOGIC0:MISR_RESET--IDELAY0:IDELAY_TYPE[0]---~IOB0:DRIVE[4]-
9 --------------------------ILOGIC0:DYN_CLKDIV_INV_EN-OLOGIC0:MUX.CLKDIVF[4]ILOGIC0:IFFDELAY_VALUE[0]OLOGIC0:INV.D7OLOGIC0:MUX.CLKDIVFB[4]-------~IOB0:DRIVE[5]
10 ---------------------------ILOGIC0:INTERFACE_TYPE[2]ILOGIC0:IDELAY_VALUE[0]--OLOGIC0:MISR_ENABLE_FDBK------IOB0:DRIVE[6]-
11 --------------------------ILOGIC0:DYN_CLKDIVP_INV_EN--ILOGIC0:IFF_DELAY_ENABLEOLOGIC0:DATA_WIDTH[6]----IDELAY0:IDELAY_VALUE_INIT[1]---IOB0:OUTPUT_MISC[0]
12 ---------------------------ILOGIC0:INTERFACE_TYPE[4]---OLOGIC0:DATA_WIDTH[7]------IOB0:OUTPUT_MISC[1]-
13 --------------------------ILOGIC0:INV.CLKDIVP---OLOGIC0:INV.D6----~IDELAY0:IDELAY_VALUE_CUR[1]---IOB0:OUTPUT_MISC[2]
14 ---------------------------ILOGIC0:INTERFACE_TYPE[3]ILOGIC0:IFF_TSBYPASS_ENABLE--OLOGIC0:INV.D5OLOGIC0:OMUX[3]-IDELAY0:IDELAY_TYPE[1]---~IOB0:SLEW[0]-
15 --------------------------ILOGIC0:DATA_WIDTH[0]--ILOGIC0:IFFDELAY_VALUE[1]OLOGIC0:MISR_CLK_SELECT[0]--OLOGIC0:OFF_SR_USED-----IOB0:SLEW[1]
16 ---------------------------ILOGIC0:DATA_WIDTH[1]ILOGIC0:IDELAY_VALUE[1]OLOGIC0:MUX.CLKDIV[0]OLOGIC0:MUX.CLKDIVB[0]OLOGIC0:MISR_ENABLEOLOGIC0:OMUX[0]-----IOB0:SLEW[2]-
17 --------------------------ILOGIC0:DATA_WIDTH[2]-OLOGIC0:MUX.CLKDIV[1]ILOGIC0:TSBYPASS_MUXOLOGIC0:INV.D4OLOGIC0:MUX.CLKDIVB[1]-OLOGIC0:OMUX[4]-IDELAY0:IDELAY_VALUE_INIT[2]---IOB0:SLEW[3]
18 ---------------------------ILOGIC0:DATA_WIDTH[3]~ILOGIC0:INV.D----IDELAY0:HIGH_PERFORMANCE_MODE----IOB0:SLEW[4]-
19 --------------------------ILOGIC0:DATA_RATE------~OLOGIC0:OFF_SRVAL[2]-~IDELAY0:IDELAY_VALUE_CUR[2]---IOB0:SLEW[5]
20 ---------------------------ILOGIC0:BITSLIP_ENABLE----~OLOGIC0:OFF_SRVAL[0]-----IOB0:SLEW[6]-
21 --------------------------ILOGIC0:SERDES_MODE---OLOGIC0:INV.D3----IDELAY0:PIPE_SEL---IOB0:SLEW[7]
22 ----------------------------ILOGIC0:IFFDELAY_VALUE[2]---------IOB0:SLEW[8]-
23 -----------------------------ILOGIC0:IDELAY_VALUE[2]---------IOB0:SLEW[9]
24 ----------------------------ILOGIC0:I_TSBYPASS_ENABLE---------IOB0:LVDS_GROUP-
25 --------------------------ILOGIC0:SERDES--ILOGIC0:ZHOLD_ENABLEOLOGIC0:INV.D2----IDELAY0:IDELAY_VALUE_INIT[3]---IOB0:LVDS[12]
26 ---------------------------ILOGIC0:INTERFACE_TYPE[1]ILOGIC0:I_DELAY_ENABLE--OLOGIC0:DATA_WIDTH[8]------IOB0:LVDS[11]-
27 --------------------------ILOGIC0:RANK23_DLY---OLOGIC0:CLK_RATIO[3]----~IDELAY0:IDELAY_VALUE_CUR[3]---IOB0:LVDS[10]
28 ---------------------------ILOGIC0:DDR_CLK_EDGE[1]-ILOGIC0:MUX.CLKDIVP[1]-OLOGIC0:CLK_RATIO[0]------IOB0:LVDS[9]-
29 --------------------------ILOGIC0:DDR_CLK_EDGE[0]-ILOGIC0:MUX.CLKDIVP[0]-OLOGIC0:CLK_RATIO[2]--------IOB0:LVDS[8]
30 ----------------------------ILOGIC0:I_ZHOLDOLOGIC0:MUX.CLK[5]OLOGIC0:MUX.CLKB[5]OLOGIC0:INV.D1~OLOGIC0:OFF_INIT-----IOB0:LVDS[7]-
31 ----------------------------OLOGIC0:MUX.CLK[7]ILOGIC0:INV.ZHOLD_FABRICOLOGIC0:SELFHEALOLOGIC0:MUX.CLKB[7]---IDELAY0:IDELAY_VALUE_INIT[4]---IOB0:LVDS[6]
32 -----------------------------OLOGIC0:MUX.CLK[4]OLOGIC0:MUX.CLKB[4]OLOGIC0:CLK_RATIO[1]~OLOGIC0:OFF_SRVAL[1]-----IOB0:LOW_VOLTAGE-
33 ----------------------------OLOGIC0:MUX.CLK[6]~ILOGIC0:IFF4_INITOLOGIC0:INV.CLKDIVFOLOGIC0:MUX.CLKB[6]-OLOGIC0:OFF_SR_SYNC-~IDELAY0:IDELAY_VALUE_CUR[4]---IOB0:PULL[0]
34 ----------------------------~ILOGIC0:IFF4_SRVALOLOGIC0:MUX.CLK[10]OLOGIC0:MUX.CLKB[10]-OLOGIC0:OMUX[1]-----IOB0:PULL[1]-
35 ----------------------------OLOGIC0:MUX.CLK[9]-~OLOGIC0:INV.CLK2OLOGIC0:MUX.CLKB[9]-------IOB0:PULL[2]
36 --------------------------------OLOGIC0:OMUX[2]-----IOB0:PULL_DYNAMIC-
37 -----------------------------ILOGIC0:IFFDELAY_VALUE[3]~OLOGIC0:INV.CLK1--OLOGIC0:TRISTATE_WIDTH-----IOB0:DQS_BIAS
38 ----------------------------ILOGIC0:IDELAY_VALUE[3]OLOGIC0:MUX.CLK[8]OLOGIC0:MUX.CLKB[8]-OLOGIC0:TFF_SR_USED-IDELAY0:CINVCTRL_SEL---IOB0:INTERMDISABLE_SEL-
39 ----------------------------OLOGIC0:MUX.CLK[3]--OLOGIC0:MUX.CLKB[3]---IDELAY0:INV.C---IOB0:VREF_SYSMON
40 --------------------------------------IOB0:IBUF_MODE[0]-
41 -----------------------------~ILOGIC0:IFF3_INIT~OLOGIC0:RANK3_USED--------IOB0:IBUF_MODE[1]
42 ----------------------------~ILOGIC0:IFF3_SRVAL--OLOGIC0:INV.CLKDIV------IOB0:IBUF_MODE[2]-
43 ----------------------------OLOGIC0:MUX.CLK[2]--OLOGIC0:MUX.CLKB[2]-OLOGIC0:TBYTE_SRC-----IOB0:IBUF_MODE[4]
44 -----------------------------OLOGIC0:MUX.CLK[0]OLOGIC0:MUX.CLKB[0]-OLOGIC0:SERDES_MODE-----IOB0:IBUF_MODE[5]-
45 ----------------------------OLOGIC0:MUX.CLK[1]ILOGIC0:IFFDELAY_VALUE[4]-OLOGIC0:MUX.CLKB[1]-~OLOGIC0:TFF_SRVAL[2]-----IOB0:IBUFDISABLE_SEL
46 ----------------------------ILOGIC0:IDELAY_VALUE[4]ILOGIC0:MUX.CLK[5]ILOGIC0:MUX.CLKB[5]-~OLOGIC0:TFF_SRVAL[0]-IDELAY0:INV.DATAIN---IOB0:IBUF_MODE[3]-
47 --------------------------ILOGIC0:NUM_CE-ILOGIC0:MUX.CLK[7]--ILOGIC0:MUX.CLKB[7]-OLOGIC0:TBYTE_CTL-----IOB0:INPUT_MISC
48 -----------------------------ILOGIC0:MUX.CLK[4]ILOGIC0:MUX.CLKB[4]~OLOGIC0:INV.T4------IOB0:LVDS[5]-
49 ----------------------------ILOGIC0:MUX.CLK[6]--ILOGIC0:MUX.CLKB[6]-------IOB0:LVDS[4]
50 -----------------------------ILOGIC0:MUX.CLK[10]ILOGIC0:MUX.CLKB[10]-------IOB0:LVDS[3]-
51 ----------------------------ILOGIC0:MUX.CLK[9]~ILOGIC0:IFF2_INIT~OLOGIC0:INV.T3ILOGIC0:MUX.CLKB[9]-------IOB0:LVDS[2]
52 ----------------------------~ILOGIC0:IFF2_SRVALILOGIC0:MUX.CLK[8]ILOGIC0:MUX.CLKB[8]~OLOGIC0:TFF_INIT~OLOGIC0:TFF_SRVAL[1]-----IOB0:LVDS[1]-
53 ----------------------------ILOGIC0:MUX.CLK[3]--ILOGIC0:MUX.CLKB[3]-------IOB0:LVDS[0]
54 --------------------------------OLOGIC0:SERDESIDELAY0:ENABLE------
55 -----------------------------~ILOGIC0:IFF1_INIT--IDELAY0:INV.IDATAINOLOGIC0:TFF_SR_SYNC-IDELAY0:DELAY_SRC[0]----
56 ---------------------------~ILOGIC0:IFF_LATCH~ILOGIC0:IFF1_SRVAL--~OLOGIC0:INV.T2--IDELAY0:DELAY_SRC[2]-----
57 --------------------------ILOGIC0:IFF_SR_USED------OLOGIC0:TMUX[2]-IDELAY0:DELAY_SRC[3]----
58 --------------------------------OLOGIC0:TMUX[1]-IDELAY0:DELAY_SRC[1]-----
59 ---------------------------------OLOGIC0:TMUX[3]-----IOB0:OMUX[0]
60 ----------------------------ILOGIC0:SRTYPEILOGIC0:MUX.CLK[2]ILOGIC0:MUX.CLKB[2]~OLOGIC0:INV.T1OLOGIC0:TMUX[4]-----IOB0:OUTPUT_MISC_B-
61 ----------------------------ILOGIC0:MUX.CLK[0]ILOGIC0:D_EMU2-ILOGIC0:MUX.CLKB[0]-OLOGIC0:TMUX[0]-----IOB0:OMUX[1]
62 ----------------------------ILOGIC0:D_EMU1ILOGIC0:MUX.CLK[1]ILOGIC0:MUX.CLKB[1]-------IOB0:OUTPUT_ENABLE[0]-
63 -----------------------------ILOGIC0:INV.OCLK1---------IOB0:OUTPUT_ENABLE[1]
IO_HR_PAIR bittile 1
RowColumn
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0 ----------------------------ILOGIC1:INV.OCLK1---------IOB1:OUTPUT_ENABLE[1]-
1 ----------------------------ILOGIC1:MUX.CLK[1]ILOGIC1:D_EMU1-ILOGIC1:MUX.CLKB[1]-------IOB1:OUTPUT_ENABLE[0]
2 ----------------------------ILOGIC1:D_EMU2ILOGIC1:MUX.CLK[0]ILOGIC1:MUX.CLKB[0]-OLOGIC1:TMUX[0]-------
3 ----------------------------ILOGIC1:MUX.CLK[2]ILOGIC1:SRTYPE~OLOGIC1:INV.T1ILOGIC1:MUX.CLKB[2]-OLOGIC1:TMUX[4]-----IOB1:OUTPUT_MISC_B
4 --------------------------------OLOGIC1:TMUX[3]-------
5 ---------------------------------OLOGIC1:TMUX[1]-IDELAY1:DELAY_SRC[1]----
6 ---------------------------ILOGIC1:IFF_SR_USED----OLOGIC1:TMUX[2]-IDELAY1:DELAY_SRC[3]-----
7 --------------------------~ILOGIC1:IFF_LATCH--~ILOGIC1:IFF1_SRVAL~OLOGIC1:INV.T2----IDELAY1:DELAY_SRC[2]----
8 ----------------------------~ILOGIC1:IFF1_INIT---OLOGIC1:TFF_SR_SYNCIDELAY1:INV.IDATAINIDELAY1:DELAY_SRC[0]-----
9 --------------------------------IDELAY1:ENABLEOLOGIC1:SERDES------
10 -----------------------------ILOGIC1:MUX.CLK[3]ILOGIC1:MUX.CLKB[3]-------IOB1:LVDS[0]-
11 ----------------------------ILOGIC1:MUX.CLK[8]~ILOGIC1:IFF2_SRVAL~OLOGIC1:TFF_INITILOGIC1:MUX.CLKB[8]-~OLOGIC1:TFF_SRVAL[1]-----IOB1:LVDS[1]
12 ----------------------------~ILOGIC1:IFF2_INITILOGIC1:MUX.CLK[9]ILOGIC1:MUX.CLKB[9]~OLOGIC1:INV.T3------IOB1:LVDS[2]-
13 ----------------------------ILOGIC1:MUX.CLK[10]--ILOGIC1:MUX.CLKB[10]-------IOB1:LVDS[3]
14 -----------------------------ILOGIC1:MUX.CLK[6]ILOGIC1:MUX.CLKB[6]-------IOB1:LVDS[4]-
15 ----------------------------ILOGIC1:MUX.CLK[4]-~OLOGIC1:INV.T4ILOGIC1:MUX.CLKB[4]-------IOB1:LVDS[5]
16 ---------------------------ILOGIC1:NUM_CE-ILOGIC1:MUX.CLK[7]ILOGIC1:MUX.CLKB[7]-OLOGIC1:TBYTE_CTL-----IOB1:INPUT_MISC-
17 ----------------------------ILOGIC1:MUX.CLK[5]ILOGIC1:IDELAY_VALUE[4]-ILOGIC1:MUX.CLKB[5]-~OLOGIC1:TFF_SRVAL[2]-IDELAY1:INV.DATAIN---IOB1:IBUF_MODE[3]
18 ----------------------------ILOGIC1:IFFDELAY_VALUE[4]OLOGIC1:MUX.CLK[1]OLOGIC1:MUX.CLKB[1]-~OLOGIC1:TFF_SRVAL[0]-----IOB1:IBUFDISABLE_SEL-
19 ----------------------------OLOGIC1:MUX.CLK[0]--OLOGIC1:MUX.CLKB[0]-OLOGIC1:SERDES_MODE-----IOB1:IBUF_MODE[5]
20 -----------------------------OLOGIC1:MUX.CLK[2]OLOGIC1:MUX.CLKB[2]-OLOGIC1:TBYTE_SRC-----IOB1:IBUF_MODE[4]-
21 -----------------------------~ILOGIC1:IFF3_SRVALOLOGIC1:INV.CLKDIV--------IOB1:IBUF_MODE[2]
22 ----------------------------~ILOGIC1:IFF3_INIT--~OLOGIC1:RANK3_USED------IOB1:IBUF_MODE[1]-
23 ---------------------------------------IOB1:IBUF_MODE[0]
24 -----------------------------OLOGIC1:MUX.CLK[3]OLOGIC1:MUX.CLKB[3]---IDELAY1:INV.C---IOB1:VREF_SYSMON-
25 ----------------------------OLOGIC1:MUX.CLK[8]ILOGIC1:IDELAY_VALUE[3]-OLOGIC1:MUX.CLKB[8]-OLOGIC1:TFF_SR_USED-IDELAY1:CINVCTRL_SEL---IOB1:INTERMDISABLE_SEL
26 ----------------------------ILOGIC1:IFFDELAY_VALUE[3]--~OLOGIC1:INV.CLK1OLOGIC1:TRISTATE_WIDTH-----IOB1:DQS_BIAS-
27 ---------------------------------OLOGIC1:OMUX[2]-----IOB1:PULL_DYNAMIC
28 -----------------------------OLOGIC1:MUX.CLK[9]OLOGIC1:MUX.CLKB[9]~OLOGIC1:INV.CLK2------IOB1:PULL[2]-
29 ----------------------------OLOGIC1:MUX.CLK[10]~ILOGIC1:IFF4_SRVAL-OLOGIC1:MUX.CLKB[10]-OLOGIC1:OMUX[1]-----IOB1:PULL[1]
30 ----------------------------~ILOGIC1:IFF4_INITOLOGIC1:MUX.CLK[6]OLOGIC1:MUX.CLKB[6]OLOGIC1:INV.CLKDIVFOLOGIC1:OFF_SR_SYNC-~IDELAY1:IDELAY_VALUE_CUR[4]---IOB1:PULL[0]-
31 ----------------------------OLOGIC1:MUX.CLK[4]-OLOGIC1:CLK_RATIO[1]OLOGIC1:MUX.CLKB[4]-~OLOGIC1:OFF_SRVAL[1]-----IOB1:LOW_VOLTAGE
32 ----------------------------ILOGIC1:INV.ZHOLD_FABRICOLOGIC1:MUX.CLK[7]OLOGIC1:MUX.CLKB[7]OLOGIC1:SELFHEAL--IDELAY1:IDELAY_VALUE_INIT[4]---IOB1:LVDS[6]-
33 ----------------------------OLOGIC1:MUX.CLK[5]ILOGIC1:I_ZHOLDOLOGIC1:INV.D1OLOGIC1:MUX.CLKB[5]-~OLOGIC1:OFF_INIT-----IOB1:LVDS[7]
34 ---------------------------ILOGIC1:DDR_CLK_EDGE[0]-ILOGIC1:MUX.CLKDIVP[0]-OLOGIC1:CLK_RATIO[2]------IOB1:LVDS[8]-
35 --------------------------ILOGIC1:DDR_CLK_EDGE[1]-ILOGIC1:MUX.CLKDIVP[1]-OLOGIC1:CLK_RATIO[0]--------IOB1:LVDS[9]
36 ---------------------------ILOGIC1:RANK23_DLY---OLOGIC1:CLK_RATIO[3]--~IDELAY1:IDELAY_VALUE_CUR[3]---IOB1:LVDS[10]-
37 --------------------------ILOGIC1:INTERFACE_TYPE[1]--ILOGIC1:I_DELAY_ENABLEOLOGIC1:DATA_WIDTH[8]--------IOB1:LVDS[11]
38 ---------------------------ILOGIC1:SERDESILOGIC1:ZHOLD_ENABLE--OLOGIC1:INV.D2--IDELAY1:IDELAY_VALUE_INIT[3]---IOB1:LVDS[12]-
39 -----------------------------ILOGIC1:I_TSBYPASS_ENABLE---------IOB1:LVDS_GROUP
40 ----------------------------ILOGIC1:IDELAY_VALUE[2]---------IOB1:SLEW[9]-
41 -----------------------------ILOGIC1:IFFDELAY_VALUE[2]---------IOB1:SLEW[8]
42 ---------------------------ILOGIC1:SERDES_MODE---OLOGIC1:INV.D3--IDELAY1:PIPE_SEL---IOB1:SLEW[7]-
43 --------------------------ILOGIC1:BITSLIP_ENABLE------~OLOGIC1:OFF_SRVAL[2]-----IOB1:SLEW[6]
44 ---------------------------ILOGIC1:DATA_RATE----~OLOGIC1:OFF_SRVAL[0]-~IDELAY1:IDELAY_VALUE_CUR[2]---IOB1:SLEW[5]-
45 --------------------------ILOGIC1:DATA_WIDTH[3]--~ILOGIC1:INV.D--IDELAY1:HIGH_PERFORMANCE_MODE------IOB1:SLEW[4]
46 ---------------------------ILOGIC1:DATA_WIDTH[2]ILOGIC1:TSBYPASS_MUXOLOGIC1:MUX.CLKDIV[1]OLOGIC1:MUX.CLKDIVB[1]OLOGIC1:INV.D4OLOGIC1:OMUX[4]-IDELAY1:IDELAY_VALUE_INIT[2]---IOB1:SLEW[3]-
47 --------------------------ILOGIC1:DATA_WIDTH[1]-OLOGIC1:MUX.CLKDIV[0]ILOGIC1:IDELAY_VALUE[1]OLOGIC1:MISR_ENABLEOLOGIC1:MUX.CLKDIVB[0]-OLOGIC1:OMUX[0]-----IOB1:SLEW[2]
48 ---------------------------ILOGIC1:DATA_WIDTH[0]ILOGIC1:IFFDELAY_VALUE[1]--OLOGIC1:MISR_CLK_SELECT[0]OLOGIC1:OFF_SR_USED-----IOB1:SLEW[1]-
49 --------------------------ILOGIC1:INTERFACE_TYPE[3]--ILOGIC1:IFF_TSBYPASS_ENABLEOLOGIC1:INV.D5--OLOGIC1:OMUX[3]-IDELAY1:IDELAY_TYPE[1]---~IOB1:SLEW[0]
50 ---------------------------ILOGIC1:INV.CLKDIVP---OLOGIC1:INV.D6--~IDELAY1:IDELAY_VALUE_CUR[1]---IOB1:OUTPUT_MISC[2]-
51 --------------------------ILOGIC1:INTERFACE_TYPE[4]---OLOGIC1:DATA_WIDTH[7]--------IOB1:OUTPUT_MISC[1]
52 ---------------------------ILOGIC1:DYN_CLKDIVP_INV_ENILOGIC1:IFF_DELAY_ENABLE--OLOGIC1:DATA_WIDTH[6]--IDELAY1:IDELAY_VALUE_INIT[1]---IOB1:OUTPUT_MISC[0]-
53 --------------------------ILOGIC1:INTERFACE_TYPE[2]--ILOGIC1:IDELAY_VALUE[0]OLOGIC1:MISR_ENABLE_FDBK--------IOB1:DRIVE[6]
54 ---------------------------ILOGIC1:DYN_CLKDIV_INV_ENILOGIC1:IFFDELAY_VALUE[0]OLOGIC1:MUX.CLKDIVF[4]OLOGIC1:MUX.CLKDIVFB[4]OLOGIC1:INV.D7------~IOB1:DRIVE[5]-
55 --------------------------ILOGIC1:INV.CLKDIV-OLOGIC1:MUX.CLKDIVF[5]ILOGIC1:IFF_ZHOLDOLOGIC1:MISR_RESETOLOGIC1:MUX.CLKDIVFB[5]---IDELAY1:IDELAY_TYPE[0]---~IOB1:DRIVE[4]
56 ----------------------------ILOGIC1:INV.ZHOLD_IFF--OLOGIC1:DATA_WIDTH[4]--~IDELAY1:IDELAY_VALUE_CUR[0]---IOB1:IN_TERM[0]-
57 --------------------------ILOGIC1:INTERFACE_TYPE[0]-OLOGIC1:MUX.CLKDIVF[6]-OLOGIC1:DATA_WIDTH[3]OLOGIC1:MUX.CLKDIVFB[6]-------IOB1:IN_TERM[3]
58 -------------------------------OLOGIC1:MISR_CLK_SELECT[1]--IDELAY1:IDELAY_VALUE_INIT[0]---IOB1:IN_TERM[2]-
59 ----------------------------OLOGIC1:MUX.CLKDIVF[2]~ILOGIC1:INV.CLK[1]OLOGIC1:DATA_WIDTH[5]OLOGIC1:MUX.CLKDIVFB[2]-------IOB1:IN_TERM[1]
60 ----------------------------ILOGIC1:INV.OCLK2OLOGIC1:MUX.CLKDIVF[0]OLOGIC1:MUX.CLKDIVFB[0]OLOGIC1:DATA_WIDTH[2]------IOB1:DRIVE[3]-
61 ----------------------------OLOGIC1:MUX.CLKDIVF[3]~ILOGIC1:INV.CLK[2]OLOGIC1:INV.D8OLOGIC1:MUX.CLKDIVFB[3]-------~IOB1:DRIVE[2]
62 ----------------------------~ILOGIC1:INV.CLK[0]OLOGIC1:MUX.CLKDIVF[1]OLOGIC1:MUX.CLKDIVFB[1]OLOGIC1:DATA_WIDTH[1]------IOB1:DRIVE[1]-
63 -----------------------------ILOGIC1:DYN_CLK_INV_ENOLOGIC1:DATA_WIDTH[0]--------IOB1:DRIVE[0]
IDELAY0:CINVCTRL_SEL[0, 34, 38]
IDELAY0:ENABLE[0, 33, 54]
IDELAY0:HIGH_PERFORMANCE_MODE[0, 33, 18]
IDELAY0:INV.C[0, 35, 39]
IDELAY0:INV.DATAIN[0, 34, 46]
IDELAY0:INV.IDATAIN[0, 32, 55]
IDELAY0:PIPE_SEL[0, 35, 21]
IDELAY1:CINVCTRL_SEL[1, 35, 25]
IDELAY1:ENABLE[1, 32, 9]
IDELAY1:HIGH_PERFORMANCE_MODE[1, 32, 45]
IDELAY1:INV.C[1, 34, 24]
IDELAY1:INV.DATAIN[1, 35, 17]
IDELAY1:INV.IDATAIN[1, 33, 8]
IDELAY1:PIPE_SEL[1, 34, 42]
ILOGIC0:BITSLIP_ENABLE[0, 27, 20]
ILOGIC0:DYN_CLKDIVP_INV_EN[0, 26, 11]
ILOGIC0:DYN_CLKDIV_INV_EN[0, 26, 9]
ILOGIC0:DYN_CLK_INV_EN[0, 28, 0]
ILOGIC0:D_EMU1[0, 28, 62]
ILOGIC0:D_EMU2[0, 29, 61]
ILOGIC0:IFF_DELAY_ENABLE[0, 29, 11]
ILOGIC0:IFF_SR_USED[0, 26, 57]
ILOGIC0:IFF_TSBYPASS_ENABLE[0, 28, 14]
ILOGIC0:IFF_ZHOLD[0, 28, 8]
ILOGIC0:INV.CLKDIV[0, 27, 8]
ILOGIC0:INV.CLKDIVP[0, 26, 13]
ILOGIC0:INV.OCLK1[0, 29, 63]
ILOGIC0:INV.OCLK2[0, 29, 3]
ILOGIC0:INV.ZHOLD_FABRIC[0, 29, 31]
ILOGIC0:INV.ZHOLD_IFF[0, 29, 7]
ILOGIC0:I_DELAY_ENABLE[0, 28, 26]
ILOGIC0:I_TSBYPASS_ENABLE[0, 28, 24]
ILOGIC0:I_ZHOLD[0, 28, 30]
ILOGIC0:RANK23_DLY[0, 26, 27]
ILOGIC0:SERDES[0, 26, 25]
ILOGIC0:ZHOLD_ENABLE[0, 29, 25]
ILOGIC1:BITSLIP_ENABLE[1, 26, 43]
ILOGIC1:DYN_CLKDIVP_INV_EN[1, 27, 52]
ILOGIC1:DYN_CLKDIV_INV_EN[1, 27, 54]
ILOGIC1:DYN_CLK_INV_EN[1, 29, 63]
ILOGIC1:D_EMU1[1, 29, 1]
ILOGIC1:D_EMU2[1, 28, 2]
ILOGIC1:IFF_DELAY_ENABLE[1, 28, 52]
ILOGIC1:IFF_SR_USED[1, 27, 6]
ILOGIC1:IFF_TSBYPASS_ENABLE[1, 29, 49]
ILOGIC1:IFF_ZHOLD[1, 29, 55]
ILOGIC1:INV.CLKDIV[1, 26, 55]
ILOGIC1:INV.CLKDIVP[1, 27, 50]
ILOGIC1:INV.OCLK1[1, 28, 0]
ILOGIC1:INV.OCLK2[1, 28, 60]
ILOGIC1:INV.ZHOLD_FABRIC[1, 28, 32]
ILOGIC1:INV.ZHOLD_IFF[1, 28, 56]
ILOGIC1:I_DELAY_ENABLE[1, 29, 37]
ILOGIC1:I_TSBYPASS_ENABLE[1, 29, 39]
ILOGIC1:I_ZHOLD[1, 29, 33]
ILOGIC1:RANK23_DLY[1, 27, 36]
ILOGIC1:SERDES[1, 27, 38]
ILOGIC1:ZHOLD_ENABLE[1, 28, 38]
IOB0:DQS_BIAS[0, 39, 37]
IOB0:INPUT_MISC[0, 39, 47]
IOB0:LOW_VOLTAGE[0, 38, 32]
IOB0:LVDS_GROUP[0, 38, 24]
IOB0:OUTPUT_MISC_B[0, 38, 60]
IOB0:PULL_DYNAMIC[0, 38, 36]
IOB0:VREF_SYSMON[0, 39, 39]
IOB1:DQS_BIAS[1, 38, 26]
IOB1:INPUT_MISC[1, 38, 16]
IOB1:LOW_VOLTAGE[1, 39, 31]
IOB1:LVDS_GROUP[1, 39, 39]
IOB1:OUTPUT_MISC_B[1, 39, 3]
IOB1:PULL_DYNAMIC[1, 39, 27]
IOB1:VREF_SYSMON[1, 38, 24]
OLOGIC0:INV.CLKDIV[0, 31, 42]
OLOGIC0:INV.CLKDIVF[0, 30, 33]
OLOGIC0:INV.D1[0, 31, 30]
OLOGIC0:INV.D2[0, 30, 25]
OLOGIC0:INV.D3[0, 30, 21]
OLOGIC0:INV.D4[0, 30, 17]
OLOGIC0:INV.D5[0, 31, 14]
OLOGIC0:INV.D6[0, 30, 13]
OLOGIC0:INV.D7[0, 30, 9]
OLOGIC0:INV.D8[0, 31, 2]
OLOGIC0:MISR_ENABLE[0, 31, 16]
OLOGIC0:MISR_ENABLE_FDBK[0, 31, 10]
OLOGIC0:MISR_RESET[0, 31, 8]
OLOGIC0:OFF_SR_SYNC[0, 33, 33]
OLOGIC0:OFF_SR_USED[0, 33, 15]
OLOGIC0:SELFHEAL[0, 30, 31]
OLOGIC0:SERDES[0, 32, 54]
OLOGIC0:TBYTE_CTL[0, 33, 47]
OLOGIC0:TBYTE_SRC[0, 33, 43]
OLOGIC0:TFF_SR_SYNC[0, 33, 55]
OLOGIC0:TFF_SR_USED[0, 32, 38]
OLOGIC1:INV.CLKDIV[1, 30, 21]
OLOGIC1:INV.CLKDIVF[1, 31, 30]
OLOGIC1:INV.D1[1, 30, 33]
OLOGIC1:INV.D2[1, 31, 38]
OLOGIC1:INV.D3[1, 31, 42]
OLOGIC1:INV.D4[1, 31, 46]
OLOGIC1:INV.D5[1, 30, 49]
OLOGIC1:INV.D6[1, 31, 50]
OLOGIC1:INV.D7[1, 31, 54]
OLOGIC1:INV.D8[1, 30, 61]
OLOGIC1:MISR_ENABLE[1, 30, 47]
OLOGIC1:MISR_ENABLE_FDBK[1, 30, 53]
OLOGIC1:MISR_RESET[1, 30, 55]
OLOGIC1:OFF_SR_SYNC[1, 32, 30]
OLOGIC1:OFF_SR_USED[1, 32, 48]
OLOGIC1:SELFHEAL[1, 31, 32]
OLOGIC1:SERDES[1, 33, 9]
OLOGIC1:TBYTE_CTL[1, 32, 16]
OLOGIC1:TBYTE_SRC[1, 32, 20]
OLOGIC1:TFF_SR_SYNC[1, 32, 8]
OLOGIC1:TFF_SR_USED[1, 33, 25]
Non-inverted[0]
ILOGIC0:DATA_WIDTH[0, 27, 18][0, 26, 17][0, 27, 16][0, 26, 15]
ILOGIC1:DATA_WIDTH[1, 26, 45][1, 27, 46][1, 26, 47][1, 27, 48]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
ILOGIC0:DATA_RATE[0, 26, 19]
ILOGIC1:DATA_RATE[1, 27, 44]
DDR0
SDR1
ILOGIC0:SERDES_MODE[0, 26, 21]
ILOGIC1:SERDES_MODE[1, 27, 42]
OLOGIC0:SERDES_MODE[0, 32, 44]
OLOGIC1:SERDES_MODE[1, 33, 19]
MASTER0
SLAVE1
ILOGIC0:DDR_CLK_EDGE[0, 27, 28][0, 26, 29]
ILOGIC1:DDR_CLK_EDGE[1, 26, 35][1, 27, 34]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC0:NUM_CE[0, 26, 47]
ILOGIC1:NUM_CE[1, 27, 16]
10
21
ILOGIC0:INTERFACE_TYPE[0, 27, 12][0, 27, 14][0, 27, 10][0, 27, 26][0, 27, 6]
ILOGIC1:INTERFACE_TYPE[1, 26, 51][1, 26, 49][1, 26, 53][1, 26, 37][1, 26, 57]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC0:IFF1_INIT[0, 29, 55]
ILOGIC0:IFF1_SRVAL[0, 28, 56]
ILOGIC0:IFF2_INIT[0, 29, 51]
ILOGIC0:IFF2_SRVAL[0, 28, 52]
ILOGIC0:IFF3_INIT[0, 29, 41]
ILOGIC0:IFF3_SRVAL[0, 28, 42]
ILOGIC0:IFF4_INIT[0, 29, 33]
ILOGIC0:IFF4_SRVAL[0, 28, 34]
ILOGIC0:IFF_LATCH[0, 27, 56]
ILOGIC0:INV.D[0, 28, 18]
ILOGIC1:IFF1_INIT[1, 28, 8]
ILOGIC1:IFF1_SRVAL[1, 29, 7]
ILOGIC1:IFF2_INIT[1, 28, 12]
ILOGIC1:IFF2_SRVAL[1, 29, 11]
ILOGIC1:IFF3_INIT[1, 28, 22]
ILOGIC1:IFF3_SRVAL[1, 29, 21]
ILOGIC1:IFF4_INIT[1, 28, 30]
ILOGIC1:IFF4_SRVAL[1, 29, 29]
ILOGIC1:IFF_LATCH[1, 26, 7]
ILOGIC1:INV.D[1, 29, 45]
OLOGIC0:INV.CLK1[0, 30, 37]
OLOGIC0:INV.CLK2[0, 30, 35]
OLOGIC0:INV.T1[0, 31, 60]
OLOGIC0:INV.T2[0, 31, 56]
OLOGIC0:INV.T3[0, 30, 51]
OLOGIC0:INV.T4[0, 31, 48]
OLOGIC0:OFF_INIT[0, 32, 30]
OLOGIC0:RANK3_USED[0, 30, 41]
OLOGIC0:TFF_INIT[0, 31, 52]
OLOGIC1:INV.CLK1[1, 31, 26]
OLOGIC1:INV.CLK2[1, 31, 28]
OLOGIC1:INV.T1[1, 30, 3]
OLOGIC1:INV.T2[1, 30, 7]
OLOGIC1:INV.T3[1, 31, 12]
OLOGIC1:INV.T4[1, 30, 15]
OLOGIC1:OFF_INIT[1, 33, 33]
OLOGIC1:RANK3_USED[1, 31, 22]
OLOGIC1:TFF_INIT[1, 30, 11]
Inverted~[0]
ILOGIC0:INV.CLK[0, 29, 1][0, 28, 4][0, 28, 2]
ILOGIC1:INV.CLK[1, 29, 61][1, 29, 59][1, 28, 62]
OLOGIC0:OFF_SRVAL[0, 33, 19][0, 32, 32][0, 32, 20]
OLOGIC0:TFF_SRVAL[0, 33, 45][0, 32, 52][0, 32, 46]
OLOGIC1:OFF_SRVAL[1, 33, 43][1, 33, 31][1, 32, 44]
OLOGIC1:TFF_SRVAL[1, 33, 17][1, 33, 11][1, 32, 18]
Inverted~[2]~[1]~[0]
OLOGIC0:MUX.CLKDIVF[0, 29, 6][0, 29, 8][0, 28, 9][0, 29, 2][0, 29, 4][0, 28, 1][0, 28, 3]
OLOGIC0:MUX.CLKDIVFB[0, 30, 6][0, 30, 8][0, 31, 9][0, 30, 2][0, 30, 4][0, 31, 1][0, 31, 3]
OLOGIC1:MUX.CLKDIVF[1, 28, 57][1, 28, 55][1, 29, 54][1, 28, 61][1, 28, 59][1, 29, 62][1, 29, 60]
OLOGIC1:MUX.CLKDIVFB[1, 31, 57][1, 31, 55][1, 30, 54][1, 31, 61][1, 31, 59][1, 30, 62][1, 30, 60]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
IDELAY0:IDELAY_VALUE_INIT[0, 35, 31][0, 35, 25][0, 35, 17][0, 35, 11][0, 35, 5]
IDELAY1:IDELAY_VALUE_INIT[1, 34, 32][1, 34, 38][1, 34, 46][1, 34, 52][1, 34, 58]
ILOGIC0:IDELAY_VALUE[0, 28, 46][0, 28, 38][0, 29, 23][0, 28, 16][0, 28, 10]
ILOGIC0:IFFDELAY_VALUE[0, 29, 45][0, 29, 37][0, 28, 22][0, 29, 15][0, 29, 9]
ILOGIC1:IDELAY_VALUE[1, 29, 17][1, 29, 25][1, 28, 40][1, 29, 47][1, 29, 53]
ILOGIC1:IFFDELAY_VALUE[1, 28, 18][1, 28, 26][1, 29, 41][1, 28, 48][1, 28, 54]
Non-inverted[4][3][2][1][0]
ILOGIC0:MUX.CLKDIVP[0, 29, 28][0, 28, 29]
ILOGIC1:MUX.CLKDIVP[1, 28, 35][1, 29, 34]
NONE00
CLKDIV01
PHASER10
ILOGIC0:SRTYPE[0, 28, 60]
ILOGIC1:SRTYPE[1, 29, 3]
ASYNC0
SYNC1
ILOGIC0:MUX.CLK[0, 29, 50][0, 28, 51][0, 29, 52][0, 28, 47][0, 28, 49][0, 29, 46][0, 29, 48][0, 28, 53][0, 29, 60][0, 29, 62][0, 28, 61]
ILOGIC0:MUX.CLKB[0, 30, 50][0, 31, 51][0, 30, 52][0, 31, 47][0, 31, 49][0, 30, 46][0, 30, 48][0, 31, 53][0, 30, 60][0, 30, 62][0, 31, 61]
ILOGIC1:MUX.CLK[1, 28, 13][1, 29, 12][1, 28, 11][1, 29, 16][1, 29, 14][1, 28, 17][1, 28, 15][1, 29, 10][1, 28, 3][1, 28, 1][1, 29, 2]
ILOGIC1:MUX.CLKB[1, 31, 13][1, 30, 12][1, 31, 11][1, 30, 16][1, 30, 14][1, 31, 17][1, 31, 15][1, 30, 10][1, 31, 3][1, 31, 1][1, 30, 2]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
OLOGIC0:MUX.CLKDIV[0, 28, 17][0, 29, 16]
OLOGIC1:MUX.CLKDIV[1, 29, 46][1, 28, 47]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
ILOGIC0:TSBYPASS_MUX[0, 29, 17]
ILOGIC1:TSBYPASS_MUX[1, 28, 46]
T0
GND1
OLOGIC0:MUX.CLK[0, 29, 34][0, 28, 35][0, 29, 38][0, 28, 31][0, 28, 33][0, 29, 30][0, 29, 32][0, 28, 39][0, 28, 43][0, 28, 45][0, 29, 44]
OLOGIC0:MUX.CLKB[0, 30, 34][0, 31, 35][0, 30, 38][0, 31, 31][0, 31, 33][0, 30, 30][0, 30, 32][0, 31, 39][0, 31, 43][0, 31, 45][0, 30, 44]
OLOGIC1:MUX.CLK[1, 28, 29][1, 29, 28][1, 28, 25][1, 29, 32][1, 29, 30][1, 28, 33][1, 28, 31][1, 29, 24][1, 29, 20][1, 29, 18][1, 28, 19]
OLOGIC1:MUX.CLKB[1, 31, 29][1, 30, 28][1, 31, 25][1, 30, 32][1, 30, 30][1, 31, 33][1, 31, 31][1, 30, 24][1, 30, 20][1, 30, 18][1, 31, 19]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
OLOGIC0:MISR_CLK_SELECT[0, 30, 5][0, 30, 15]
OLOGIC1:MISR_CLK_SELECT[1, 31, 58][1, 31, 48]
NONE00
CLK101
CLK210
OLOGIC0:MUX.CLKDIVB[0, 31, 17][0, 30, 16]
OLOGIC1:MUX.CLKDIVB[1, 30, 46][1, 31, 47]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC0:DATA_WIDTH[0, 31, 26][0, 31, 12][0, 30, 11][0, 31, 4][0, 30, 7][0, 31, 6][0, 30, 3][0, 30, 1][0, 31, 0]
OLOGIC1:DATA_WIDTH[1, 30, 37][1, 30, 51][1, 31, 52][1, 30, 59][1, 31, 56][1, 30, 57][1, 31, 60][1, 31, 62][1, 30, 63]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC0:CLK_RATIO[0, 30, 27][0, 30, 29][0, 31, 32][0, 31, 28]
OLOGIC1:CLK_RATIO[1, 31, 36][1, 31, 34][1, 30, 31][1, 30, 35]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC0:OMUX[0, 33, 17][0, 32, 14][0, 32, 36][0, 32, 34][0, 32, 16]
OLOGIC1:OMUX[1, 32, 46][1, 33, 49][1, 33, 27][1, 33, 29][1, 33, 47]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC0:TRISTATE_WIDTH[0, 33, 37]
OLOGIC1:TRISTATE_WIDTH[1, 32, 26]
10
41
OLOGIC0:TMUX[0, 32, 60][0, 33, 59][0, 33, 57][0, 32, 58][0, 33, 61]
OLOGIC1:TMUX[1, 33, 3][1, 32, 4][1, 32, 6][1, 33, 5][1, 32, 2]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY0:IDELAY_TYPE[0, 34, 14][0, 34, 8]
IDELAY1:IDELAY_TYPE[1, 35, 49][1, 35, 55]
FIXED00
VARIABLE01
VAR_LOAD11
IDELAY0:IDELAY_VALUE_CUR[0, 35, 33][0, 35, 27][0, 35, 19][0, 35, 13][0, 35, 7]
IDELAY1:IDELAY_VALUE_CUR[1, 34, 30][1, 34, 36][1, 34, 44][1, 34, 50][1, 34, 56]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY0:DELAY_SRC[0, 35, 57][0, 34, 56][0, 34, 58][0, 35, 55]
IDELAY1:DELAY_SRC[1, 34, 6][1, 35, 7][1, 35, 5][1, 34, 8]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
IOB0:DRIVE[0, 38, 10][0, 39, 9][0, 38, 8][0, 39, 3][0, 38, 2][0, 39, 1][0, 38, 0]
IOB1:DRIVE[1, 39, 53][1, 38, 54][1, 39, 55][1, 38, 60][1, 39, 61][1, 38, 62][1, 39, 63]
Mixed inversion[6]~[5]~[4][3]~[2][1][0]
IOB0:IN_TERM[0, 38, 6][0, 39, 5][0, 39, 7][0, 38, 4]
IOB1:IN_TERM[1, 39, 57][1, 38, 58][1, 39, 59][1, 38, 56]
NONE0000
UNTUNED_SPLIT_600011
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_401111
IOB0:SLEW[0, 39, 23][0, 38, 22][0, 39, 21][0, 38, 20][0, 39, 19][0, 38, 18][0, 39, 17][0, 38, 16][0, 39, 15][0, 38, 14]
IOB1:SLEW[1, 38, 40][1, 39, 41][1, 38, 42][1, 39, 43][1, 38, 44][1, 39, 45][1, 38, 46][1, 39, 47][1, 38, 48][1, 39, 49]
Mixed inversion[9][8][7][6][5][4][3][2][1]~[0]
IOB0:IBUFDISABLE_SEL[0, 39, 45]
IOB0:INTERMDISABLE_SEL[0, 38, 38]
IOB1:IBUFDISABLE_SEL[1, 38, 18]
IOB1:INTERMDISABLE_SEL[1, 39, 25]
GND0
I1
IOB0:IBUF_MODE[0, 38, 44][0, 39, 43][0, 38, 46][0, 38, 42][0, 39, 41][0, 38, 40]
IOB1:IBUF_MODE[1, 39, 19][1, 38, 20][1, 39, 17][1, 39, 21][1, 38, 22][1, 39, 23]
OFF000000
VREF_LP000001
TMDS_LP000010
DIFF_LP000011
CMOS_LV000110
CMOS_HV000111
PCI001111
VREF_HP010001
TMDS_HP100010
DIFF_HP100011
IOB0:OUTPUT_ENABLE[0, 39, 63][0, 38, 62]
IOB1:OUTPUT_ENABLE[1, 38, 0][1, 39, 1]
Non-inverted[1][0]
IOB0:OUTPUT_MISC[0, 39, 13][0, 38, 12][0, 39, 11]
IOB1:OUTPUT_MISC[1, 38, 50][1, 39, 51][1, 38, 52]
Non-inverted[2][1][0]
IOB0:PULL[0, 39, 35][0, 38, 34][0, 39, 33]
IOB1:PULL[1, 38, 28][1, 39, 29][1, 38, 30]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:LVDS[0, 39, 25][0, 38, 26][0, 39, 27][0, 38, 28][0, 39, 29][0, 38, 30][0, 39, 31][0, 38, 48][0, 39, 49][0, 38, 50][0, 39, 51][0, 38, 52][0, 39, 53]
IOB1:LVDS[1, 38, 38][1, 39, 37][1, 38, 36][1, 39, 35][1, 38, 34][1, 39, 33][1, 38, 32][1, 39, 15][1, 38, 14][1, 39, 13][1, 38, 12][1, 39, 11][1, 38, 10]
Non-inverted[12][11][10][9][8][7][6][5][4][3][2][1][0]
IOB0:OMUX[0, 39, 61][0, 39, 59]
O00
OTHER_O_INV11

Bitstream — IO_HR_BOT

IO_HR_BOT bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC:INV.OCLK1---------IOB:OUTPUT_ENABLE[1]-
1 ----------------------------ILOGIC:MUX.CLK[1]ILOGIC:D_EMU1-ILOGIC:MUX.CLKB[1]-------IOB:OUTPUT_ENABLE[0]
2 ----------------------------ILOGIC:D_EMU2ILOGIC:MUX.CLK[0]ILOGIC:MUX.CLKB[0]-OLOGIC:TMUX[0]-------
3 ----------------------------ILOGIC:MUX.CLK[2]ILOGIC:SRTYPE~OLOGIC:INV.T1ILOGIC:MUX.CLKB[2]-OLOGIC:TMUX[4]-----IOB:OUTPUT_MISC_B
4 --------------------------------OLOGIC:TMUX[3]-------
5 ---------------------------------OLOGIC:TMUX[1]-IDELAY:DELAY_SRC[1]----
6 ---------------------------ILOGIC:IFF_SR_USED----OLOGIC:TMUX[2]-IDELAY:DELAY_SRC[3]-----
7 --------------------------~ILOGIC:IFF_LATCH--~ILOGIC:IFF1_SRVAL~OLOGIC:INV.T2----IDELAY:DELAY_SRC[2]----
8 ----------------------------~ILOGIC:IFF1_INIT---OLOGIC:TFF_SR_SYNCIDELAY:INV.IDATAINIDELAY:DELAY_SRC[0]-----
9 --------------------------------IDELAY:ENABLEOLOGIC:SERDES------
10 -----------------------------ILOGIC:MUX.CLK[3]ILOGIC:MUX.CLKB[3]-------IOB:LVDS[0]-
11 ----------------------------ILOGIC:MUX.CLK[8]~ILOGIC:IFF2_SRVAL~OLOGIC:TFF_INITILOGIC:MUX.CLKB[8]-~OLOGIC:TFF_SRVAL[1]-----IOB:LVDS[1]
12 ----------------------------~ILOGIC:IFF2_INITILOGIC:MUX.CLK[9]ILOGIC:MUX.CLKB[9]~OLOGIC:INV.T3------IOB:LVDS[2]-
13 ----------------------------ILOGIC:MUX.CLK[10]--ILOGIC:MUX.CLKB[10]-------IOB:LVDS[3]
14 -----------------------------ILOGIC:MUX.CLK[6]ILOGIC:MUX.CLKB[6]-------IOB:LVDS[4]-
15 ----------------------------ILOGIC:MUX.CLK[4]-~OLOGIC:INV.T4ILOGIC:MUX.CLKB[4]-------IOB:LVDS[5]
16 ---------------------------ILOGIC:NUM_CE-ILOGIC:MUX.CLK[7]ILOGIC:MUX.CLKB[7]-OLOGIC:TBYTE_CTL-----IOB:INPUT_MISC-
17 ----------------------------ILOGIC:MUX.CLK[5]ILOGIC:IDELAY_VALUE[4]-ILOGIC:MUX.CLKB[5]-~OLOGIC:TFF_SRVAL[2]-IDELAY:INV.DATAIN---IOB:IBUF_MODE[3]
18 ----------------------------ILOGIC:IFFDELAY_VALUE[4]OLOGIC:MUX.CLK[1]OLOGIC:MUX.CLKB[1]-~OLOGIC:TFF_SRVAL[0]-----IOB:IBUFDISABLE_SEL-
19 ----------------------------OLOGIC:MUX.CLK[0]--OLOGIC:MUX.CLKB[0]-OLOGIC:SERDES_MODE------
20 -----------------------------OLOGIC:MUX.CLK[2]OLOGIC:MUX.CLKB[2]-OLOGIC:TBYTE_SRC-----IOB:IBUF_MODE[4]-
21 -----------------------------~ILOGIC:IFF3_SRVALOLOGIC:INV.CLKDIV--------IOB:IBUF_MODE[2]
22 ----------------------------~ILOGIC:IFF3_INIT--~OLOGIC:RANK3_USED------IOB:IBUF_MODE[1]-
23 ---------------------------------------IOB:IBUF_MODE[0]
24 -----------------------------OLOGIC:MUX.CLK[3]OLOGIC:MUX.CLKB[3]---IDELAY:INV.C-----
25 ----------------------------OLOGIC:MUX.CLK[8]ILOGIC:IDELAY_VALUE[3]-OLOGIC:MUX.CLKB[8]-OLOGIC:TFF_SR_USED-IDELAY:CINVCTRL_SEL---IOB:INTERMDISABLE_SEL
26 ----------------------------ILOGIC:IFFDELAY_VALUE[3]--~OLOGIC:INV.CLK1OLOGIC:TRISTATE_WIDTH-----IOB:DQS_BIAS-
27 ---------------------------------OLOGIC:OMUX[2]-----IOB:PULL_DYNAMIC
28 -----------------------------OLOGIC:MUX.CLK[9]OLOGIC:MUX.CLKB[9]~OLOGIC:INV.CLK2------IOB:PULL[2]-
29 ----------------------------OLOGIC:MUX.CLK[10]~ILOGIC:IFF4_SRVAL-OLOGIC:MUX.CLKB[10]-OLOGIC:OMUX[1]-----IOB:PULL[1]
30 ----------------------------~ILOGIC:IFF4_INITOLOGIC:MUX.CLK[6]OLOGIC:MUX.CLKB[6]OLOGIC:INV.CLKDIVFOLOGIC:OFF_SR_SYNC-~IDELAY:IDELAY_VALUE_CUR[4]---IOB:PULL[0]-
31 ----------------------------OLOGIC:MUX.CLK[4]-OLOGIC:CLK_RATIO[1]OLOGIC:MUX.CLKB[4]-~OLOGIC:OFF_SRVAL[1]-----IOB:LOW_VOLTAGE
32 ----------------------------ILOGIC:INV.ZHOLD_FABRICOLOGIC:MUX.CLK[7]OLOGIC:MUX.CLKB[7]OLOGIC:SELFHEAL--IDELAY:IDELAY_VALUE_INIT[4]---IOB:LVDS[6]-
33 ----------------------------OLOGIC:MUX.CLK[5]ILOGIC:I_ZHOLDOLOGIC:INV.D1OLOGIC:MUX.CLKB[5]-~OLOGIC:OFF_INIT-----IOB:LVDS[7]
34 ---------------------------ILOGIC:DDR_CLK_EDGE[0]-ILOGIC:MUX.CLKDIVP[0]-OLOGIC:CLK_RATIO[2]------IOB:LVDS[8]-
35 --------------------------ILOGIC:DDR_CLK_EDGE[1]-ILOGIC:MUX.CLKDIVP[1]-OLOGIC:CLK_RATIO[0]--------IOB:LVDS[9]
36 ---------------------------ILOGIC:RANK23_DLY---OLOGIC:CLK_RATIO[3]--~IDELAY:IDELAY_VALUE_CUR[3]---IOB:LVDS[10]-
37 --------------------------ILOGIC:INTERFACE_TYPE[1]--ILOGIC:I_DELAY_ENABLEOLOGIC:DATA_WIDTH[8]--------IOB:LVDS[11]
38 ---------------------------ILOGIC:SERDESILOGIC:ZHOLD_ENABLE--OLOGIC:INV.D2--IDELAY:IDELAY_VALUE_INIT[3]---IOB:LVDS[12]-
39 -----------------------------ILOGIC:I_TSBYPASS_ENABLE----------
40 ----------------------------ILOGIC:IDELAY_VALUE[2]---------IOB:SLEW[9]-
41 -----------------------------ILOGIC:IFFDELAY_VALUE[2]---------IOB:SLEW[8]
42 ---------------------------ILOGIC:SERDES_MODE---OLOGIC:INV.D3--IDELAY:PIPE_SEL---IOB:SLEW[7]-
43 --------------------------ILOGIC:BITSLIP_ENABLE------~OLOGIC:OFF_SRVAL[2]-----IOB:SLEW[6]
44 ---------------------------ILOGIC:DATA_RATE----~OLOGIC:OFF_SRVAL[0]-~IDELAY:IDELAY_VALUE_CUR[2]---IOB:SLEW[5]-
45 --------------------------ILOGIC:DATA_WIDTH[3]--~ILOGIC:INV.D--IDELAY:HIGH_PERFORMANCE_MODE------IOB:SLEW[4]
46 ---------------------------ILOGIC:DATA_WIDTH[2]ILOGIC:TSBYPASS_MUXOLOGIC:MUX.CLKDIV[1]OLOGIC:MUX.CLKDIVB[1]OLOGIC:INV.D4OLOGIC:OMUX[4]-IDELAY:IDELAY_VALUE_INIT[2]---IOB:SLEW[3]-
47 --------------------------ILOGIC:DATA_WIDTH[1]-OLOGIC:MUX.CLKDIV[0]ILOGIC:IDELAY_VALUE[1]OLOGIC:MISR_ENABLEOLOGIC:MUX.CLKDIVB[0]-OLOGIC:OMUX[0]-----IOB:SLEW[2]
48 ---------------------------ILOGIC:DATA_WIDTH[0]ILOGIC:IFFDELAY_VALUE[1]--OLOGIC:MISR_CLK_SELECT[0]OLOGIC:OFF_SR_USED-----IOB:SLEW[1]-
49 --------------------------ILOGIC:INTERFACE_TYPE[3]--ILOGIC:IFF_TSBYPASS_ENABLEOLOGIC:INV.D5--OLOGIC:OMUX[3]-IDELAY:IDELAY_TYPE[1]---~IOB:SLEW[0]
50 ---------------------------ILOGIC:INV.CLKDIVP---OLOGIC:INV.D6--~IDELAY:IDELAY_VALUE_CUR[1]---IOB:OUTPUT_MISC[2]-
51 --------------------------ILOGIC:INTERFACE_TYPE[4]---OLOGIC:DATA_WIDTH[7]--------IOB:OUTPUT_MISC[1]
52 ---------------------------ILOGIC:DYN_CLKDIVP_INV_ENILOGIC:IFF_DELAY_ENABLE--OLOGIC:DATA_WIDTH[6]--IDELAY:IDELAY_VALUE_INIT[1]---IOB:OUTPUT_MISC[0]-
53 --------------------------ILOGIC:INTERFACE_TYPE[2]--ILOGIC:IDELAY_VALUE[0]OLOGIC:MISR_ENABLE_FDBK--------IOB:DRIVE[6]
54 ---------------------------ILOGIC:DYN_CLKDIV_INV_ENILOGIC:IFFDELAY_VALUE[0]OLOGIC:MUX.CLKDIVF[4]OLOGIC:MUX.CLKDIVFB[4]OLOGIC:INV.D7------~IOB:DRIVE[5]-
55 --------------------------ILOGIC:INV.CLKDIV-OLOGIC:MUX.CLKDIVF[5]ILOGIC:IFF_ZHOLDOLOGIC:MISR_RESETOLOGIC:MUX.CLKDIVFB[5]---IDELAY:IDELAY_TYPE[0]---~IOB:DRIVE[4]
56 ----------------------------ILOGIC:INV.ZHOLD_IFF--OLOGIC:DATA_WIDTH[4]--~IDELAY:IDELAY_VALUE_CUR[0]---IOB:IN_TERM[0]-
57 --------------------------ILOGIC:INTERFACE_TYPE[0]-OLOGIC:MUX.CLKDIVF[6]-OLOGIC:DATA_WIDTH[3]OLOGIC:MUX.CLKDIVFB[6]-------IOB:IN_TERM[3]
58 -------------------------------OLOGIC:MISR_CLK_SELECT[1]--IDELAY:IDELAY_VALUE_INIT[0]---IOB:IN_TERM[2]-
59 ----------------------------OLOGIC:MUX.CLKDIVF[2]~ILOGIC:INV.CLK[1]OLOGIC:DATA_WIDTH[5]OLOGIC:MUX.CLKDIVFB[2]-------IOB:IN_TERM[1]
60 ----------------------------ILOGIC:INV.OCLK2OLOGIC:MUX.CLKDIVF[0]OLOGIC:MUX.CLKDIVFB[0]OLOGIC:DATA_WIDTH[2]------IOB:DRIVE[3]-
61 ----------------------------OLOGIC:MUX.CLKDIVF[3]~ILOGIC:INV.CLK[2]OLOGIC:INV.D8OLOGIC:MUX.CLKDIVFB[3]-------~IOB:DRIVE[2]
62 ----------------------------~ILOGIC:INV.CLK[0]OLOGIC:MUX.CLKDIVF[1]OLOGIC:MUX.CLKDIVFB[1]OLOGIC:DATA_WIDTH[1]------IOB:DRIVE[1]-
63 -----------------------------ILOGIC:DYN_CLK_INV_ENOLOGIC:DATA_WIDTH[0]--------IOB:DRIVE[0]
ILOGIC:IFF1_INIT[0, 28, 8]
ILOGIC:IFF1_SRVAL[0, 29, 7]
ILOGIC:IFF2_INIT[0, 28, 12]
ILOGIC:IFF2_SRVAL[0, 29, 11]
ILOGIC:IFF3_INIT[0, 28, 22]
ILOGIC:IFF3_SRVAL[0, 29, 21]
ILOGIC:IFF4_INIT[0, 28, 30]
ILOGIC:IFF4_SRVAL[0, 29, 29]
ILOGIC:IFF_LATCH[0, 26, 7]
ILOGIC:INV.D[0, 29, 45]
OLOGIC:INV.CLK1[0, 31, 26]
OLOGIC:INV.CLK2[0, 31, 28]
OLOGIC:INV.T1[0, 30, 3]
OLOGIC:INV.T2[0, 30, 7]
OLOGIC:INV.T3[0, 31, 12]
OLOGIC:INV.T4[0, 30, 15]
OLOGIC:OFF_INIT[0, 33, 33]
OLOGIC:RANK3_USED[0, 31, 22]
OLOGIC:TFF_INIT[0, 30, 11]
Inverted~[0]
IDELAY:CINVCTRL_SEL[0, 35, 25]
IDELAY:ENABLE[0, 32, 9]
IDELAY:HIGH_PERFORMANCE_MODE[0, 32, 45]
IDELAY:INV.C[0, 34, 24]
IDELAY:INV.DATAIN[0, 35, 17]
IDELAY:INV.IDATAIN[0, 33, 8]
IDELAY:PIPE_SEL[0, 34, 42]
ILOGIC:BITSLIP_ENABLE[0, 26, 43]
ILOGIC:DYN_CLKDIVP_INV_EN[0, 27, 52]
ILOGIC:DYN_CLKDIV_INV_EN[0, 27, 54]
ILOGIC:DYN_CLK_INV_EN[0, 29, 63]
ILOGIC:D_EMU1[0, 29, 1]
ILOGIC:D_EMU2[0, 28, 2]
ILOGIC:IFF_DELAY_ENABLE[0, 28, 52]
ILOGIC:IFF_SR_USED[0, 27, 6]
ILOGIC:IFF_TSBYPASS_ENABLE[0, 29, 49]
ILOGIC:IFF_ZHOLD[0, 29, 55]
ILOGIC:INV.CLKDIV[0, 26, 55]
ILOGIC:INV.CLKDIVP[0, 27, 50]
ILOGIC:INV.OCLK1[0, 28, 0]
ILOGIC:INV.OCLK2[0, 28, 60]
ILOGIC:INV.ZHOLD_FABRIC[0, 28, 32]
ILOGIC:INV.ZHOLD_IFF[0, 28, 56]
ILOGIC:I_DELAY_ENABLE[0, 29, 37]
ILOGIC:I_TSBYPASS_ENABLE[0, 29, 39]
ILOGIC:I_ZHOLD[0, 29, 33]
ILOGIC:RANK23_DLY[0, 27, 36]
ILOGIC:SERDES[0, 27, 38]
ILOGIC:ZHOLD_ENABLE[0, 28, 38]
IOB:DQS_BIAS[0, 38, 26]
IOB:INPUT_MISC[0, 38, 16]
IOB:LOW_VOLTAGE[0, 39, 31]
IOB:OUTPUT_MISC_B[0, 39, 3]
IOB:PULL_DYNAMIC[0, 39, 27]
OLOGIC:INV.CLKDIV[0, 30, 21]
OLOGIC:INV.CLKDIVF[0, 31, 30]
OLOGIC:INV.D1[0, 30, 33]
OLOGIC:INV.D2[0, 31, 38]
OLOGIC:INV.D3[0, 31, 42]
OLOGIC:INV.D4[0, 31, 46]
OLOGIC:INV.D5[0, 30, 49]
OLOGIC:INV.D6[0, 31, 50]
OLOGIC:INV.D7[0, 31, 54]
OLOGIC:INV.D8[0, 30, 61]
OLOGIC:MISR_ENABLE[0, 30, 47]
OLOGIC:MISR_ENABLE_FDBK[0, 30, 53]
OLOGIC:MISR_RESET[0, 30, 55]
OLOGIC:OFF_SR_SYNC[0, 32, 30]
OLOGIC:OFF_SR_USED[0, 32, 48]
OLOGIC:SELFHEAL[0, 31, 32]
OLOGIC:SERDES[0, 33, 9]
OLOGIC:TBYTE_CTL[0, 32, 16]
OLOGIC:TBYTE_SRC[0, 32, 20]
OLOGIC:TFF_SR_SYNC[0, 32, 8]
OLOGIC:TFF_SR_USED[0, 33, 25]
Non-inverted[0]
ILOGIC:INTERFACE_TYPE[0, 26, 51][0, 26, 49][0, 26, 53][0, 26, 37][0, 26, 57]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC:NUM_CE[0, 27, 16]
10
21
ILOGIC:DDR_CLK_EDGE[0, 26, 35][0, 27, 34]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC:SERDES_MODE[0, 27, 42]
OLOGIC:SERDES_MODE[0, 33, 19]
MASTER0
SLAVE1
ILOGIC:DATA_RATE[0, 27, 44]
DDR0
SDR1
ILOGIC:DATA_WIDTH[0, 26, 45][0, 27, 46][0, 26, 47][0, 27, 48]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
OLOGIC:MUX.CLK[0, 28, 29][0, 29, 28][0, 28, 25][0, 29, 32][0, 29, 30][0, 28, 33][0, 28, 31][0, 29, 24][0, 29, 20][0, 29, 18][0, 28, 19]
OLOGIC:MUX.CLKB[0, 31, 29][0, 30, 28][0, 31, 25][0, 30, 32][0, 30, 30][0, 31, 33][0, 31, 31][0, 30, 24][0, 30, 20][0, 30, 18][0, 31, 19]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
ILOGIC:TSBYPASS_MUX[0, 28, 46]
T0
GND1
OLOGIC:MUX.CLKDIV[0, 29, 46][0, 28, 47]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
IDELAY:IDELAY_VALUE_INIT[0, 34, 32][0, 34, 38][0, 34, 46][0, 34, 52][0, 34, 58]
ILOGIC:IDELAY_VALUE[0, 29, 17][0, 29, 25][0, 28, 40][0, 29, 47][0, 29, 53]
ILOGIC:IFFDELAY_VALUE[0, 28, 18][0, 28, 26][0, 29, 41][0, 28, 48][0, 28, 54]
Non-inverted[4][3][2][1][0]
ILOGIC:INV.CLK[0, 29, 61][0, 29, 59][0, 28, 62]
OLOGIC:OFF_SRVAL[0, 33, 43][0, 33, 31][0, 32, 44]
OLOGIC:TFF_SRVAL[0, 33, 17][0, 33, 11][0, 32, 18]
Inverted~[2]~[1]~[0]
ILOGIC:MUX.CLK[0, 28, 13][0, 29, 12][0, 28, 11][0, 29, 16][0, 29, 14][0, 28, 17][0, 28, 15][0, 29, 10][0, 28, 3][0, 28, 1][0, 29, 2]
ILOGIC:MUX.CLKB[0, 31, 13][0, 30, 12][0, 31, 11][0, 30, 16][0, 30, 14][0, 31, 17][0, 31, 15][0, 30, 10][0, 31, 3][0, 31, 1][0, 30, 2]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
ILOGIC:SRTYPE[0, 29, 3]
ASYNC0
SYNC1
ILOGIC:MUX.CLKDIVP[0, 28, 35][0, 29, 34]
NONE00
CLKDIV01
PHASER10
OLOGIC:MUX.CLKDIVF[0, 28, 57][0, 28, 55][0, 29, 54][0, 28, 61][0, 28, 59][0, 29, 62][0, 29, 60]
OLOGIC:MUX.CLKDIVFB[0, 31, 57][0, 31, 55][0, 30, 54][0, 31, 61][0, 31, 59][0, 30, 62][0, 30, 60]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
OLOGIC:CLK_RATIO[0, 31, 36][0, 31, 34][0, 30, 31][0, 30, 35]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC:DATA_WIDTH[0, 30, 37][0, 30, 51][0, 31, 52][0, 30, 59][0, 31, 56][0, 30, 57][0, 31, 60][0, 31, 62][0, 30, 63]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC:MUX.CLKDIVB[0, 30, 46][0, 31, 47]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC:MISR_CLK_SELECT[0, 31, 58][0, 31, 48]
NONE00
CLK101
CLK210
OLOGIC:TMUX[0, 33, 3][0, 32, 4][0, 32, 6][0, 33, 5][0, 32, 2]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC:TRISTATE_WIDTH[0, 32, 26]
10
41
OLOGIC:OMUX[0, 32, 46][0, 33, 49][0, 33, 27][0, 33, 29][0, 33, 47]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY:DELAY_SRC[0, 34, 6][0, 35, 7][0, 35, 5][0, 34, 8]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
IDELAY:IDELAY_VALUE_CUR[0, 34, 30][0, 34, 36][0, 34, 44][0, 34, 50][0, 34, 56]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY:IDELAY_TYPE[0, 35, 49][0, 35, 55]
FIXED00
VARIABLE01
VAR_LOAD11
IOB:LVDS[0, 38, 38][0, 39, 37][0, 38, 36][0, 39, 35][0, 38, 34][0, 39, 33][0, 38, 32][0, 39, 15][0, 38, 14][0, 39, 13][0, 38, 12][0, 39, 11][0, 38, 10]
Non-inverted[12][11][10][9][8][7][6][5][4][3][2][1][0]
IOB:IBUFDISABLE_SEL[0, 38, 18]
IOB:INTERMDISABLE_SEL[0, 39, 25]
GND0
I1
IOB:PULL[0, 38, 28][0, 39, 29][0, 38, 30]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB:OUTPUT_MISC[0, 38, 50][0, 39, 51][0, 38, 52]
Non-inverted[2][1][0]
IOB:IN_TERM[0, 39, 57][0, 38, 58][0, 39, 59][0, 38, 56]
NONE0000
UNTUNED_SPLIT_600011
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_401111
IOB:OUTPUT_ENABLE[0, 38, 0][0, 39, 1]
Non-inverted[1][0]
IOB:IBUF_MODE[0, 38, 20][0, 39, 17][0, 39, 21][0, 38, 22][0, 39, 23]
OFF00000
VREF_LP00001
CMOS_LV00110
CMOS_HV00111
PCI01111
VREF_HP10001
IOB:SLEW[0, 38, 40][0, 39, 41][0, 38, 42][0, 39, 43][0, 38, 44][0, 39, 45][0, 38, 46][0, 39, 47][0, 38, 48][0, 39, 49]
Mixed inversion[9][8][7][6][5][4][3][2][1]~[0]
IOB:DRIVE[0, 39, 53][0, 38, 54][0, 39, 55][0, 38, 60][0, 39, 61][0, 38, 62][0, 39, 63]
Mixed inversion[6]~[5]~[4][3]~[2][1][0]

Bitstream — IO_HR_TOP

IO_HR_TOP bittile 0
RowColumn
0123456789101112131415161718192021222324252627282930313233343536373839
0 ----------------------------ILOGIC:DYN_CLK_INV_EN--OLOGIC:DATA_WIDTH[0]------IOB:DRIVE[0]-
1 ----------------------------OLOGIC:MUX.CLKDIVF[1]~ILOGIC:INV.CLK[2]OLOGIC:DATA_WIDTH[1]OLOGIC:MUX.CLKDIVFB[1]-------IOB:DRIVE[1]
2 ----------------------------~ILOGIC:INV.CLK[0]OLOGIC:MUX.CLKDIVF[3]OLOGIC:MUX.CLKDIVFB[3]OLOGIC:INV.D8------~IOB:DRIVE[2]-
3 ----------------------------OLOGIC:MUX.CLKDIVF[0]ILOGIC:INV.OCLK2OLOGIC:DATA_WIDTH[2]OLOGIC:MUX.CLKDIVFB[0]-------IOB:DRIVE[3]
4 ----------------------------~ILOGIC:INV.CLK[1]OLOGIC:MUX.CLKDIVF[2]OLOGIC:MUX.CLKDIVFB[2]OLOGIC:DATA_WIDTH[5]------IOB:IN_TERM[0]-
5 ------------------------------OLOGIC:MISR_CLK_SELECT[1]----IDELAY:IDELAY_VALUE_INIT[0]---IOB:IN_TERM[2]
6 ---------------------------ILOGIC:INTERFACE_TYPE[0]-OLOGIC:MUX.CLKDIVF[6]OLOGIC:MUX.CLKDIVFB[6]OLOGIC:DATA_WIDTH[3]------IOB:IN_TERM[3]-
7 -----------------------------ILOGIC:INV.ZHOLD_IFFOLOGIC:DATA_WIDTH[4]----~IDELAY:IDELAY_VALUE_CUR[0]---IOB:IN_TERM[1]
8 ---------------------------ILOGIC:INV.CLKDIVILOGIC:IFF_ZHOLDOLOGIC:MUX.CLKDIVF[5]OLOGIC:MUX.CLKDIVFB[5]OLOGIC:MISR_RESET--IDELAY:IDELAY_TYPE[0]---~IOB:DRIVE[4]-
9 --------------------------ILOGIC:DYN_CLKDIV_INV_EN-OLOGIC:MUX.CLKDIVF[4]ILOGIC:IFFDELAY_VALUE[0]OLOGIC:INV.D7OLOGIC:MUX.CLKDIVFB[4]-------~IOB:DRIVE[5]
10 ---------------------------ILOGIC:INTERFACE_TYPE[2]ILOGIC:IDELAY_VALUE[0]--OLOGIC:MISR_ENABLE_FDBK------IOB:DRIVE[6]-
11 --------------------------ILOGIC:DYN_CLKDIVP_INV_EN--ILOGIC:IFF_DELAY_ENABLEOLOGIC:DATA_WIDTH[6]----IDELAY:IDELAY_VALUE_INIT[1]---IOB:OUTPUT_MISC[0]
12 ---------------------------ILOGIC:INTERFACE_TYPE[4]---OLOGIC:DATA_WIDTH[7]------IOB:OUTPUT_MISC[1]-
13 --------------------------ILOGIC:INV.CLKDIVP---OLOGIC:INV.D6----~IDELAY:IDELAY_VALUE_CUR[1]---IOB:OUTPUT_MISC[2]
14 ---------------------------ILOGIC:INTERFACE_TYPE[3]ILOGIC:IFF_TSBYPASS_ENABLE--OLOGIC:INV.D5OLOGIC:OMUX[3]-IDELAY:IDELAY_TYPE[1]---~IOB:SLEW[0]-
15 --------------------------ILOGIC:DATA_WIDTH[0]--ILOGIC:IFFDELAY_VALUE[1]OLOGIC:MISR_CLK_SELECT[0]--OLOGIC:OFF_SR_USED-----IOB:SLEW[1]
16 ---------------------------ILOGIC:DATA_WIDTH[1]ILOGIC:IDELAY_VALUE[1]OLOGIC:MUX.CLKDIV[0]OLOGIC:MUX.CLKDIVB[0]OLOGIC:MISR_ENABLEOLOGIC:OMUX[0]-----IOB:SLEW[2]-
17 --------------------------ILOGIC:DATA_WIDTH[2]-OLOGIC:MUX.CLKDIV[1]ILOGIC:TSBYPASS_MUXOLOGIC:INV.D4OLOGIC:MUX.CLKDIVB[1]-OLOGIC:OMUX[4]-IDELAY:IDELAY_VALUE_INIT[2]---IOB:SLEW[3]
18 ---------------------------ILOGIC:DATA_WIDTH[3]~ILOGIC:INV.D----IDELAY:HIGH_PERFORMANCE_MODE----IOB:SLEW[4]-
19 --------------------------ILOGIC:DATA_RATE------~OLOGIC:OFF_SRVAL[2]-~IDELAY:IDELAY_VALUE_CUR[2]---IOB:SLEW[5]
20 ---------------------------ILOGIC:BITSLIP_ENABLE----~OLOGIC:OFF_SRVAL[0]-----IOB:SLEW[6]-
21 --------------------------ILOGIC:SERDES_MODE---OLOGIC:INV.D3----IDELAY:PIPE_SEL---IOB:SLEW[7]
22 ----------------------------ILOGIC:IFFDELAY_VALUE[2]---------IOB:SLEW[8]-
23 -----------------------------ILOGIC:IDELAY_VALUE[2]---------IOB:SLEW[9]
24 ----------------------------ILOGIC:I_TSBYPASS_ENABLE-----------
25 --------------------------ILOGIC:SERDES--ILOGIC:ZHOLD_ENABLEOLOGIC:INV.D2----IDELAY:IDELAY_VALUE_INIT[3]---IOB:LVDS[12]
26 ---------------------------ILOGIC:INTERFACE_TYPE[1]ILOGIC:I_DELAY_ENABLE--OLOGIC:DATA_WIDTH[8]------IOB:LVDS[11]-
27 --------------------------ILOGIC:RANK23_DLY---OLOGIC:CLK_RATIO[3]----~IDELAY:IDELAY_VALUE_CUR[3]---IOB:LVDS[10]
28 ---------------------------ILOGIC:DDR_CLK_EDGE[1]-ILOGIC:MUX.CLKDIVP[1]-OLOGIC:CLK_RATIO[0]------IOB:LVDS[9]-
29 --------------------------ILOGIC:DDR_CLK_EDGE[0]-ILOGIC:MUX.CLKDIVP[0]-OLOGIC:CLK_RATIO[2]--------IOB:LVDS[8]
30 ----------------------------ILOGIC:I_ZHOLDOLOGIC:MUX.CLK[5]OLOGIC:MUX.CLKB[5]OLOGIC:INV.D1~OLOGIC:OFF_INIT-----IOB:LVDS[7]-
31 ----------------------------OLOGIC:MUX.CLK[7]ILOGIC:INV.ZHOLD_FABRICOLOGIC:SELFHEALOLOGIC:MUX.CLKB[7]---IDELAY:IDELAY_VALUE_INIT[4]---IOB:LVDS[6]
32 -----------------------------OLOGIC:MUX.CLK[4]OLOGIC:MUX.CLKB[4]OLOGIC:CLK_RATIO[1]~OLOGIC:OFF_SRVAL[1]-----IOB:LOW_VOLTAGE-
33 ----------------------------OLOGIC:MUX.CLK[6]~ILOGIC:IFF4_INITOLOGIC:INV.CLKDIVFOLOGIC:MUX.CLKB[6]-OLOGIC:OFF_SR_SYNC-~IDELAY:IDELAY_VALUE_CUR[4]---IOB:PULL[0]
34 ----------------------------~ILOGIC:IFF4_SRVALOLOGIC:MUX.CLK[10]OLOGIC:MUX.CLKB[10]-OLOGIC:OMUX[1]-----IOB:PULL[1]-
35 ----------------------------OLOGIC:MUX.CLK[9]-~OLOGIC:INV.CLK2OLOGIC:MUX.CLKB[9]-------IOB:PULL[2]
36 --------------------------------OLOGIC:OMUX[2]-----IOB:PULL_DYNAMIC-
37 -----------------------------ILOGIC:IFFDELAY_VALUE[3]~OLOGIC:INV.CLK1--OLOGIC:TRISTATE_WIDTH-----IOB:DQS_BIAS
38 ----------------------------ILOGIC:IDELAY_VALUE[3]OLOGIC:MUX.CLK[8]OLOGIC:MUX.CLKB[8]-OLOGIC:TFF_SR_USED-IDELAY:CINVCTRL_SEL---IOB:INTERMDISABLE_SEL-
39 ----------------------------OLOGIC:MUX.CLK[3]--OLOGIC:MUX.CLKB[3]---IDELAY:INV.C----
40 --------------------------------------IOB:IBUF_MODE[0]-
41 -----------------------------~ILOGIC:IFF3_INIT~OLOGIC:RANK3_USED--------IOB:IBUF_MODE[2]
42 ----------------------------~ILOGIC:IFF3_SRVAL--OLOGIC:INV.CLKDIV------IOB:IBUF_MODE[1]-
43 ----------------------------OLOGIC:MUX.CLK[2]--OLOGIC:MUX.CLKB[2]-OLOGIC:TBYTE_SRC-----IOB:IBUF_MODE[4]
44 -----------------------------OLOGIC:MUX.CLK[0]OLOGIC:MUX.CLKB[0]-OLOGIC:SERDES_MODE-------
45 ----------------------------OLOGIC:MUX.CLK[1]ILOGIC:IFFDELAY_VALUE[4]-OLOGIC:MUX.CLKB[1]-~OLOGIC:TFF_SRVAL[2]-----IOB:IBUFDISABLE_SEL
46 ----------------------------ILOGIC:IDELAY_VALUE[4]ILOGIC:MUX.CLK[5]ILOGIC:MUX.CLKB[5]-~OLOGIC:TFF_SRVAL[0]-IDELAY:INV.DATAIN---IOB:IBUF_MODE[3]-
47 --------------------------ILOGIC:NUM_CE-ILOGIC:MUX.CLK[7]--ILOGIC:MUX.CLKB[7]-OLOGIC:TBYTE_CTL-----IOB:INPUT_MISC
48 -----------------------------ILOGIC:MUX.CLK[4]ILOGIC:MUX.CLKB[4]~OLOGIC:INV.T4------IOB:LVDS[5]-
49 ----------------------------ILOGIC:MUX.CLK[6]--ILOGIC:MUX.CLKB[6]-------IOB:LVDS[4]
50 -----------------------------ILOGIC:MUX.CLK[10]ILOGIC:MUX.CLKB[10]-------IOB:LVDS[3]-
51 ----------------------------ILOGIC:MUX.CLK[9]~ILOGIC:IFF2_INIT~OLOGIC:INV.T3ILOGIC:MUX.CLKB[9]-------IOB:LVDS[2]
52 ----------------------------~ILOGIC:IFF2_SRVALILOGIC:MUX.CLK[8]ILOGIC:MUX.CLKB[8]~OLOGIC:TFF_INIT~OLOGIC:TFF_SRVAL[1]-----IOB:LVDS[1]-
53 ----------------------------ILOGIC:MUX.CLK[3]--ILOGIC:MUX.CLKB[3]-------IOB:LVDS[0]
54 --------------------------------OLOGIC:SERDESIDELAY:ENABLE------
55 -----------------------------~ILOGIC:IFF1_INIT--IDELAY:INV.IDATAINOLOGIC:TFF_SR_SYNC-IDELAY:DELAY_SRC[0]----
56 ---------------------------~ILOGIC:IFF_LATCH~ILOGIC:IFF1_SRVAL--~OLOGIC:INV.T2--IDELAY:DELAY_SRC[2]-----
57 --------------------------ILOGIC:IFF_SR_USED------OLOGIC:TMUX[2]-IDELAY:DELAY_SRC[3]----
58 --------------------------------OLOGIC:TMUX[1]-IDELAY:DELAY_SRC[1]-----
59 ---------------------------------OLOGIC:TMUX[3]------
60 ----------------------------ILOGIC:SRTYPEILOGIC:MUX.CLK[2]ILOGIC:MUX.CLKB[2]~OLOGIC:INV.T1OLOGIC:TMUX[4]-----IOB:OUTPUT_MISC_B-
61 ----------------------------ILOGIC:MUX.CLK[0]ILOGIC:D_EMU2-ILOGIC:MUX.CLKB[0]-OLOGIC:TMUX[0]------
62 ----------------------------ILOGIC:D_EMU1ILOGIC:MUX.CLK[1]ILOGIC:MUX.CLKB[1]-------IOB:OUTPUT_ENABLE[0]-
63 -----------------------------ILOGIC:INV.OCLK1---------IOB:OUTPUT_ENABLE[1]
IDELAY:CINVCTRL_SEL[0, 34, 38]
IDELAY:ENABLE[0, 33, 54]
IDELAY:HIGH_PERFORMANCE_MODE[0, 33, 18]
IDELAY:INV.C[0, 35, 39]
IDELAY:INV.DATAIN[0, 34, 46]
IDELAY:INV.IDATAIN[0, 32, 55]
IDELAY:PIPE_SEL[0, 35, 21]
ILOGIC:BITSLIP_ENABLE[0, 27, 20]
ILOGIC:DYN_CLKDIVP_INV_EN[0, 26, 11]
ILOGIC:DYN_CLKDIV_INV_EN[0, 26, 9]
ILOGIC:DYN_CLK_INV_EN[0, 28, 0]
ILOGIC:D_EMU1[0, 28, 62]
ILOGIC:D_EMU2[0, 29, 61]
ILOGIC:IFF_DELAY_ENABLE[0, 29, 11]
ILOGIC:IFF_SR_USED[0, 26, 57]
ILOGIC:IFF_TSBYPASS_ENABLE[0, 28, 14]
ILOGIC:IFF_ZHOLD[0, 28, 8]
ILOGIC:INV.CLKDIV[0, 27, 8]
ILOGIC:INV.CLKDIVP[0, 26, 13]
ILOGIC:INV.OCLK1[0, 29, 63]
ILOGIC:INV.OCLK2[0, 29, 3]
ILOGIC:INV.ZHOLD_FABRIC[0, 29, 31]
ILOGIC:INV.ZHOLD_IFF[0, 29, 7]
ILOGIC:I_DELAY_ENABLE[0, 28, 26]
ILOGIC:I_TSBYPASS_ENABLE[0, 28, 24]
ILOGIC:I_ZHOLD[0, 28, 30]
ILOGIC:RANK23_DLY[0, 26, 27]
ILOGIC:SERDES[0, 26, 25]
ILOGIC:ZHOLD_ENABLE[0, 29, 25]
IOB:DQS_BIAS[0, 39, 37]
IOB:INPUT_MISC[0, 39, 47]
IOB:LOW_VOLTAGE[0, 38, 32]
IOB:OUTPUT_MISC_B[0, 38, 60]
IOB:PULL_DYNAMIC[0, 38, 36]
OLOGIC:INV.CLKDIV[0, 31, 42]
OLOGIC:INV.CLKDIVF[0, 30, 33]
OLOGIC:INV.D1[0, 31, 30]
OLOGIC:INV.D2[0, 30, 25]
OLOGIC:INV.D3[0, 30, 21]
OLOGIC:INV.D4[0, 30, 17]
OLOGIC:INV.D5[0, 31, 14]
OLOGIC:INV.D6[0, 30, 13]
OLOGIC:INV.D7[0, 30, 9]
OLOGIC:INV.D8[0, 31, 2]
OLOGIC:MISR_ENABLE[0, 31, 16]
OLOGIC:MISR_ENABLE_FDBK[0, 31, 10]
OLOGIC:MISR_RESET[0, 31, 8]
OLOGIC:OFF_SR_SYNC[0, 33, 33]
OLOGIC:OFF_SR_USED[0, 33, 15]
OLOGIC:SELFHEAL[0, 30, 31]
OLOGIC:SERDES[0, 32, 54]
OLOGIC:TBYTE_CTL[0, 33, 47]
OLOGIC:TBYTE_SRC[0, 33, 43]
OLOGIC:TFF_SR_SYNC[0, 33, 55]
OLOGIC:TFF_SR_USED[0, 32, 38]
Non-inverted[0]
ILOGIC:DATA_WIDTH[0, 27, 18][0, 26, 17][0, 27, 16][0, 26, 15]
NONE0000
20010
30011
40100
50101
60110
70111
81000
101010
141110
ILOGIC:DATA_RATE[0, 26, 19]
DDR0
SDR1
ILOGIC:SERDES_MODE[0, 26, 21]
OLOGIC:SERDES_MODE[0, 32, 44]
MASTER0
SLAVE1
ILOGIC:DDR_CLK_EDGE[0, 27, 28][0, 26, 29]
SAME_EDGE_PIPELINED00
OPPOSITE_EDGE01
SAME_EDGE10
ILOGIC:NUM_CE[0, 26, 47]
10
21
ILOGIC:INTERFACE_TYPE[0, 27, 12][0, 27, 14][0, 27, 10][0, 27, 26][0, 27, 6]
MEMORY00000
NETWORKING00001
MEMORY_DDR300111
MEMORY_DDR3_V601011
OVERSAMPLE10011
ILOGIC:IFF1_INIT[0, 29, 55]
ILOGIC:IFF1_SRVAL[0, 28, 56]
ILOGIC:IFF2_INIT[0, 29, 51]
ILOGIC:IFF2_SRVAL[0, 28, 52]
ILOGIC:IFF3_INIT[0, 29, 41]
ILOGIC:IFF3_SRVAL[0, 28, 42]
ILOGIC:IFF4_INIT[0, 29, 33]
ILOGIC:IFF4_SRVAL[0, 28, 34]
ILOGIC:IFF_LATCH[0, 27, 56]
ILOGIC:INV.D[0, 28, 18]
OLOGIC:INV.CLK1[0, 30, 37]
OLOGIC:INV.CLK2[0, 30, 35]
OLOGIC:INV.T1[0, 31, 60]
OLOGIC:INV.T2[0, 31, 56]
OLOGIC:INV.T3[0, 30, 51]
OLOGIC:INV.T4[0, 31, 48]
OLOGIC:OFF_INIT[0, 32, 30]
OLOGIC:RANK3_USED[0, 30, 41]
OLOGIC:TFF_INIT[0, 31, 52]
Inverted~[0]
ILOGIC:INV.CLK[0, 29, 1][0, 28, 4][0, 28, 2]
OLOGIC:OFF_SRVAL[0, 33, 19][0, 32, 32][0, 32, 20]
OLOGIC:TFF_SRVAL[0, 33, 45][0, 32, 52][0, 32, 46]
Inverted~[2]~[1]~[0]
OLOGIC:MUX.CLKDIVF[0, 29, 6][0, 29, 8][0, 28, 9][0, 29, 2][0, 29, 4][0, 28, 1][0, 28, 3]
OLOGIC:MUX.CLKDIVFB[0, 30, 6][0, 30, 8][0, 31, 9][0, 30, 2][0, 30, 4][0, 31, 1][0, 31, 3]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
RCLK00100100
RCLK10101000
RCLK21000001
RCLK31000010
CKINT1000100
IDELAY:IDELAY_VALUE_INIT[0, 35, 31][0, 35, 25][0, 35, 17][0, 35, 11][0, 35, 5]
ILOGIC:IDELAY_VALUE[0, 28, 46][0, 28, 38][0, 29, 23][0, 28, 16][0, 28, 10]
ILOGIC:IFFDELAY_VALUE[0, 29, 45][0, 29, 37][0, 28, 22][0, 29, 15][0, 29, 9]
Non-inverted[4][3][2][1][0]
ILOGIC:MUX.CLKDIVP[0, 29, 28][0, 28, 29]
NONE00
CLKDIV01
PHASER10
ILOGIC:SRTYPE[0, 28, 60]
ASYNC0
SYNC1
ILOGIC:MUX.CLK[0, 29, 50][0, 28, 51][0, 29, 52][0, 28, 47][0, 28, 49][0, 29, 46][0, 29, 48][0, 28, 53][0, 29, 60][0, 29, 62][0, 28, 61]
ILOGIC:MUX.CLKB[0, 30, 50][0, 31, 51][0, 30, 52][0, 31, 47][0, 31, 49][0, 30, 46][0, 30, 48][0, 31, 53][0, 30, 60][0, 30, 62][0, 31, 61]
NONE00000000000
PHASER_ICLK00000000001
PHASER_OCLK00000000010
HCLK000000011100
HCLK100000101100
HCLK200001001100
HCLK300010001100
HCLK400100010100
HCLK500100100100
RCLK000101000100
RCLK100110000100
RCLK201000010100
RCLK301000100100
IOCLK001001000100
IOCLK101010000100
IOCLK210000010100
IOCLK310000100100
CKINT110001000100
CKINT010010000100
OLOGIC:MUX.CLKDIV[0, 28, 17][0, 29, 16]
NONE00
CLKDIVF01
PHASER_OCLKDIV10
ILOGIC:TSBYPASS_MUX[0, 29, 17]
T0
GND1
OLOGIC:MUX.CLK[0, 29, 34][0, 28, 35][0, 29, 38][0, 28, 31][0, 28, 33][0, 29, 30][0, 29, 32][0, 28, 39][0, 28, 43][0, 28, 45][0, 29, 44]
OLOGIC:MUX.CLKB[0, 30, 34][0, 31, 35][0, 30, 38][0, 31, 31][0, 31, 33][0, 30, 30][0, 30, 32][0, 31, 39][0, 31, 43][0, 31, 45][0, 30, 44]
NONE00000000000
PHASER_OCLK00000000010
PHASER_OCLK9000000000100
HCLK000000011001
HCLK100000101001
HCLK200001001001
HCLK300010001001
HCLK400100010001
HCLK500100100001
RCLK000101000001
RCLK100110000001
RCLK201000010001
RCLK301000100001
IOCLK001001000001
IOCLK101010000001
IOCLK210000010001
IOCLK310000100001
CKINT10001000001
OLOGIC:MISR_CLK_SELECT[0, 30, 5][0, 30, 15]
NONE00
CLK101
CLK210
OLOGIC:MUX.CLKDIVB[0, 31, 17][0, 30, 16]
NONE00
CLKDIVFB01
PHASER_OCLKDIV10
OLOGIC:DATA_WIDTH[0, 31, 26][0, 31, 12][0, 30, 11][0, 31, 4][0, 30, 7][0, 31, 6][0, 30, 3][0, 30, 1][0, 31, 0]
NONE000000000
2000000001
3000000010
4000000100
5000001000
6000010000
7000100000
8001000000
10010000000
14100000000
OLOGIC:CLK_RATIO[0, 30, 27][0, 30, 29][0, 31, 32][0, 31, 28]
NONE0000
20001
30010
40011
50101
7_81100
61101
OLOGIC:OMUX[0, 33, 17][0, 32, 14][0, 32, 36][0, 32, 34][0, 32, 16]
NONE00000
D100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
OLOGIC:TRISTATE_WIDTH[0, 33, 37]
10
41
OLOGIC:TMUX[0, 32, 60][0, 33, 59][0, 33, 57][0, 32, 58][0, 33, 61]
NONE00000
T100001
SERDES_SDR00010
DDR00100
FF01010
LATCH10010
IDELAY:IDELAY_TYPE[0, 34, 14][0, 34, 8]
FIXED00
VARIABLE01
VAR_LOAD11
IDELAY:IDELAY_VALUE_CUR[0, 35, 33][0, 35, 27][0, 35, 19][0, 35, 13][0, 35, 7]
Inverted~[4]~[3]~[2]~[1]~[0]
IDELAY:DELAY_SRC[0, 35, 57][0, 34, 56][0, 34, 58][0, 35, 55]
NONE0000
IDATAIN0001
DATAIN0010
OFB0100
DELAYCHAIN_OSC1000
IOB:DRIVE[0, 38, 10][0, 39, 9][0, 38, 8][0, 39, 3][0, 38, 2][0, 39, 1][0, 38, 0]
Mixed inversion[6]~[5]~[4][3]~[2][1][0]
IOB:IN_TERM[0, 38, 6][0, 39, 5][0, 39, 7][0, 38, 4]
NONE0000
UNTUNED_SPLIT_600011
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_401111
IOB:SLEW[0, 39, 23][0, 38, 22][0, 39, 21][0, 38, 20][0, 39, 19][0, 38, 18][0, 39, 17][0, 38, 16][0, 39, 15][0, 38, 14]
Mixed inversion[9][8][7][6][5][4][3][2][1]~[0]
IOB:IBUFDISABLE_SEL[0, 39, 45]
IOB:INTERMDISABLE_SEL[0, 38, 38]
GND0
I1
IOB:IBUF_MODE[0, 39, 43][0, 38, 46][0, 39, 41][0, 38, 42][0, 38, 40]
OFF00000
VREF_LP00001
CMOS_LV00110
CMOS_HV00111
PCI01111
VREF_HP10001
IOB:OUTPUT_ENABLE[0, 39, 63][0, 38, 62]
Non-inverted[1][0]
IOB:OUTPUT_MISC[0, 39, 13][0, 38, 12][0, 39, 11]
Non-inverted[2][1][0]
IOB:PULL[0, 39, 35][0, 38, 34][0, 39, 33]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB:LVDS[0, 39, 25][0, 38, 26][0, 39, 27][0, 38, 28][0, 39, 29][0, 38, 30][0, 39, 31][0, 38, 48][0, 39, 49][0, 38, 50][0, 39, 51][0, 38, 52][0, 39, 53]
Non-inverted[12][11][10][9][8][7][6][5][4][3][2][1][0]

Bitstream — HCLK_IOI_HP

HCLK_IOI_HP bittile 0
RowColumn
01234567891011121314151617181920212223242526272829303132333435363738394041
0 ------------------------------------------
1 ------------------------------------------
2 ------------------------------------------
3 ------------------------------------------
4 ------------------------------------------
5 ------------------------------------------
6 ------------------------------------------
7 ------------------------------------------
8 ------------------------------------------
9 ------------------------------------------
10 ------------------------------------------
11 ------------------------------------------
12 ------------------------------------------
13 ------------------------------------------
14 --------------------------HCLK_IOI:MUX.HCLK_IO_D3[6]HCLK_IOI:MUX.HCLK_IO_U3[5]HCLK_IOI:ENABLE.HCLK8HCLK_IOI:ENABLE.HCLK1HCLK_IOI:MUX.HCLK_IO_U5[2]HCLK_IOI:MUX.HCLK_IO_D5[2]HCLK_IOI:MUX.HCLK_IO_U4[6]BUFR3:BUFR_DIVIDE[0]--HCLK_IOI:ENABLE.PERF2HCLK_IOI:ENABLE.PERF3DCI:QUIET-DCI:PREF_OUTPUT_HALF[2]LVDS:LVDSBIAS[0]
15 --------------------------HCLK_IOI:MUX.HCLK_IO_U3[4]HCLK_IOI:MUX.HCLK_IO_D3[5]HCLK_IOI:ENABLE.HCLK0HCLK_IOI:ENABLE.HCLK9HCLK_IOI:MUX.HCLK_IO_D5[3]HCLK_IOI:MUX.HCLK_IO_U5[1]HCLK_IOI:MUX.HCLK_IO_U4[5]BUFR3:BUFR_DIVIDE[3]BUFR2:MUX.I[2]BUFR3:MUX.I[7]--DCI:TEST_ENABLE[0]-DCI:PREF_OUTPUT_HALF[1]LVDS:LVDSBIAS[1]
16 --------------------------HCLK_IOI:MUX.HCLK_IO_D3[4]HCLK_IOI:MUX.HCLK_IO_U3[6]-HCLK_IOI:ENABLE.HCLK2HCLK_IOI:MUX.HCLK_IO_U5[3]HCLK_IOI:MUX.HCLK_IO_D5[1]BUFR3:MUX.I[0]BUFR3:BUFR_DIVIDE[2]BUFR2:MUX.I[3]BUFR3:MUX.I[6]~BUFIO2:DELAY_BYPASS~BUFIO3:DELAY_BYPASS--DCI:PREF_OUTPUT_HALF[0]LVDS:LVDSBIAS[2]
17 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[6]HCLK_IOI:MUX.HCLK_IO_D1[0]HCLK_IOI:BUF.RCLK3HCLK_IOI:ENABLE.HCLK10HCLK_IOI:MUX.HCLK_IO_U5[4]HCLK_IOI:MUX.HCLK_IO_U5[0]-BUFR3:BUFR_DIVIDE[1]BUFR2:MUX.I[4]BUFR3:MUX.I[5]BUFIO2:MUX.IBUFIO3:MUX.I--DCI:PREF_OUTPUT[1]LVDS:LVDSBIAS[3]
18 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[5]HCLK_IOI:MUX.HCLK_IO_U1[0]HCLK_IOI:MUX.HCLK_IO_D0[5]HCLK_IOI:ENABLE.HCLK3HCLK_IOI:MUX.HCLK_IO_U5[5]HCLK_IOI:MUX.HCLK_IO_D5[0]-BUFR2:BUFR_DIVIDE[0]BUFR2:MUX.I[5]BUFR3:MUX.I[4]BUFIO2:ENABLEBUFIO3:ENABLE--DCI:PREF_OUTPUT[0]LVDS:LVDSBIAS[4]
19 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[4]HCLK_IOI:MUX.HCLK_IO_D0[1]HCLK_IOI:MUX.HCLK_IO_D1[6]HCLK_IOI:ENABLE.HCLK11HCLK_IOI:MUX.HCLK_IO_U5[6]HCLK_IOI:BUF.RCLK2BUFR3:ENABLEBUFR2:BUFR_DIVIDE[3]BUFR2:MUX.I[6]BUFR3:MUX.I[3]----INTERNAL_VREF:VREF[0]LVDS:LVDSBIAS[5]
20 --------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:MUX.HCLK_IO_D1[1]HCLK_IOI:MUX.HCLK_IO_D4[6]HCLK_IOI:MUX.HCLK_IO_U3[2]HCLK_IOI:MUX.HCLK_IO_U2[6]BUFR3:MUX.I[2]BUFR2:ENABLEBUFR2:BUFR_DIVIDE[2]BUFR2:MUX.I[7]-HCLK_IOI:ENABLE.PERF1----LVDS:LVDSBIAS[6]
21 --------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:MUX.HCLK_IO_U0[1]HCLK_IOI:MUX.HCLK_IO_U4[3]HCLK_IOI:MUX.HCLK_IO_D3[3]HCLK_IOI:MUX.HCLK_IO_U2[5]HCLK_IOI:MUX.HCLK_IO_D5[6]-BUFR2:BUFR_DIVIDE[1]-BUFR3:MUX.I[1]~BUFIO1:DELAY_BYPASSBUFIO1:MUX.IDCI:CASCADE_FROM_ABOVE--LVDS:LVDSBIAS[7]
22 --------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:MUX.HCLK_IO_U1[1]HCLK_IOI:MUX.HCLK_IO_D4[3]HCLK_IOI:MUX.HCLK_IO_U3[3]HCLK_IOI:MUX.HCLK_IO_U2[4]HCLK_IOI:MUX.HCLK_IO_D5[5]-----BUFIO1:ENABLEDCI:CASCADE_FROM_BELOW--LVDS:LVDSBIAS[8]
23 --------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:MUX.HCLK_IO_D0[2]HCLK_IOI:MUX.HCLK_IO_U4[2]HCLK_IOI:ENABLE.HCLK4HCLK_IOI:MUX.HCLK_IO_U2[3]HCLK_IOI:MUX.HCLK_IO_D5[4]HCLK_IOI:MUX.HCLK_IO_U4[4]BUFR1:BUFR_DIVIDE[0]BUFR1:MUX.I[2]BUFR0:MUX.I[0]---DCI:NREF_TERM_SPLIT[2]INTERNAL_VREF:VREF[6]LVDS:LVDSBIAS[9]
24 --------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:MUX.HCLK_IO_D1[2]HCLK_IOI:MUX.HCLK_IO_D3[2]HCLK_IOI:MUX.HCLK_IO_D0[4]HCLK_IOI:MUX.HCLK_IO_D2[3]HCLK_IOI:MUX.HCLK_IO_D2[5]HCLK_IOI:MUX.HCLK_IO_U1[4]BUFR1:BUFR_DIVIDE[3]BUFR1:MUX.I[3]BUFR0:MUX.I[1]BUFR2:MUX.I[0]IDELAYCTRL:MODE[2]-DCI:NREF_TERM_SPLIT[1]INTERNAL_VREF:VREF[5]LVDS:LVDSBIAS[10]
25 --------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:MUX.HCLK_IO_U0[2]HCLK_IOI:MUX.HCLK_IO_D4[2]HCLK_IOI:MUX.HCLK_IO_D0[6]HCLK_IOI:MUX.HCLK_IO_U2[2]HCLK_IOI:MUX.HCLK_IO_D2[4]HCLK_IOI:MUX.HCLK_IO_D1[4]BUFR1:BUFR_DIVIDE[2]BUFR1:MUX.I[4]BUFR0:MUX.I[3]BUFR2:MUX.I[1]--DCI:NREF_TERM_SPLIT[0]INTERNAL_VREF:VREF[4]LVDS:LVDSBIAS[11]
26 --------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.HCLK_IO_U1[2]HCLK_IOI:MUX.HCLK_IO_U3[1]HCLK_IOI:MUX.HCLK_IO_U0[3]HCLK_IOI:MUX.HCLK_IO_D2[2]HCLK_IOI:MUX.HCLK_IO_D2[6]BUFR1:ENABLEBUFR1:BUFR_DIVIDE[1]BUFR1:MUX.I[5]BUFR0:MUX.I[4]BUFR1:MUX.I[0]IDELAYCTRL:HIGH_PERFORMANCE_MODE-DCI:NREF_OUTPUT_HALF[2]INTERNAL_VREF:VREF[3]LVDS:LVDSBIAS[12]
27 --------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.HCLK_IO_D0[3]HCLK_IOI:MUX.HCLK_IO_U4[1]HCLK_IOI:ENABLE.HCLK5HCLK_IOI:MUX.HCLK_IO_U2[1]HCLK_IOI:MUX.HCLK_IO_D4[4]-BUFR0:BUFR_DIVIDE[0]-BUFR0:MUX.I[5]BUFR1:MUX.I[1]--DCI:NREF_OUTPUT_HALF[1]INTERNAL_VREF:VREF[1]LVDS:LVDSBIAS[13]
28 --------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.HCLK_IO_D1[3]HCLK_IOI:MUX.HCLK_IO_D3[1]HCLK_IOI:MUX.HCLK_IO_U0[0]HCLK_IOI:MUX.HCLK_IO_D2[1]HCLK_IOI:MUX.HCLK_IO_U1[6]-BUFR0:BUFR_DIVIDE[3]-BUFR0:MUX.I[6]HCLK_IOI:ENABLE.PERF0IDELAYCTRL:MODE[0]-DCI:NREF_OUTPUT_HALF[0]INTERNAL_VREF:VREF[2]LVDS:LVDSBIAS[14]
29 --------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.HCLK_IO_U1[3]HCLK_IOI:MUX.HCLK_IO_D4[1]HCLK_IOI:MUX.HCLK_IO_D0[0]HCLK_IOI:MUX.HCLK_IO_U2[0]HCLK_IOI:MUX.HCLK_IO_D1[5]HCLK_IOI:BUF.RCLK0BUFR0:BUFR_DIVIDE[2]BUFR1:MUX.I[7]BUFR0:MUX.I[7]BUFIO0:MUX.IIDELAYCTRL:MODE[1]-DCI:NREF_OUTPUT[1]-LVDS:LVDSBIAS[15]
30 --------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.HCLK_IO_D4[0]HCLK_IOI:MUX.HCLK_IO_U3[0]HCLK_IOI:ENABLE.HCLK6HCLK_IOI:MUX.HCLK_IO_D2[0]HCLK_IOI:MUX.HCLK_IO_D4[5]BUFR0:ENABLEBUFR0:BUFR_DIVIDE[1]BUFR1:MUX.I[6]----DCI:NREF_OUTPUT[0]-LVDS:LVDSBIAS[16]
31 --------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.HCLK_IO_D3[0]HCLK_IOI:MUX.HCLK_IO_U4[0]HCLK_IOI:ENABLE.HCLK7HCLK_IOI:BUF.RCLK1HCLK_IOI:MUX.HCLK_IO_U1[5]--BUFR0:MUX.I[2]-~BUFIO0:DELAY_BYPASSBUFIO0:ENABLEDCI:TEST_ENABLE[1]DCI:ENABLELVDS:LVDSBIAS[17]DCI:DYNAMIC_ENABLE
IDELAYCTRL:MUX.REFCLK[0, 26, 31][0, 26, 30][0, 26, 29][0, 26, 28][0, 26, 27][0, 26, 26][0, 26, 25][0, 26, 24][0, 26, 23][0, 26, 22][0, 26, 21][0, 26, 20]
NONE000000000000
HCLK_IO_D0000000000001
HCLK_IO_D1000000000010
HCLK_IO_D2000000000100
HCLK_IO_D3000000001000
HCLK_IO_D4000000010000
HCLK_IO_D5000000100000
HCLK_IO_U0000001000000
HCLK_IO_U1000010000000
HCLK_IO_U2000100000000
HCLK_IO_U3001000000000
HCLK_IO_U4010000000000
HCLK_IO_U5100000000000
HCLK_IOI:MUX.HCLK_IO_D0[0, 29, 25][0, 28, 18][0, 29, 24][0, 27, 27][0, 27, 23][0, 27, 19][0, 29, 29]
HCLK_IOI:MUX.HCLK_IO_D1[0, 28, 19][0, 31, 29][0, 32, 25][0, 27, 28][0, 27, 24][0, 27, 20][0, 27, 17]
HCLK_IOI:MUX.HCLK_IO_D2[0, 31, 26][0, 31, 24][0, 31, 25][0, 30, 24][0, 30, 26][0, 30, 28][0, 30, 30]
HCLK_IOI:MUX.HCLK_IO_D3[0, 26, 14][0, 27, 15][0, 26, 16][0, 29, 21][0, 28, 24][0, 28, 28][0, 27, 31]
HCLK_IOI:MUX.HCLK_IO_D4[0, 28, 20][0, 31, 30][0, 31, 27][0, 28, 22][0, 28, 25][0, 28, 29][0, 27, 30]
HCLK_IOI:MUX.HCLK_IO_D5[0, 31, 21][0, 31, 22][0, 31, 23][0, 30, 15][0, 31, 14][0, 31, 16][0, 31, 18]
HCLK_IOI:MUX.HCLK_IO_U0[0, 26, 17][0, 26, 18][0, 26, 19][0, 29, 26][0, 27, 25][0, 27, 21][0, 29, 28]
HCLK_IOI:MUX.HCLK_IO_U1[0, 31, 28][0, 31, 31][0, 32, 24][0, 27, 29][0, 27, 26][0, 27, 22][0, 27, 18]
HCLK_IOI:MUX.HCLK_IO_U2[0, 30, 20][0, 30, 21][0, 30, 22][0, 30, 23][0, 30, 25][0, 30, 27][0, 30, 29]
HCLK_IOI:MUX.HCLK_IO_U3[0, 27, 16][0, 27, 14][0, 26, 15][0, 29, 22][0, 29, 20][0, 28, 26][0, 28, 30]
HCLK_IOI:MUX.HCLK_IO_U4[0, 32, 14][0, 32, 15][0, 32, 23][0, 28, 21][0, 28, 23][0, 28, 27][0, 28, 31]
HCLK_IOI:MUX.HCLK_IO_U5[0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 30, 14][0, 31, 15][0, 31, 17]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
HCLK60100100
HCLK70101000
HCLK81000001
HCLK91000010
HCLK101000100
HCLK111001000
BUFIO0:ENABLE[0, 37, 31]
BUFIO1:ENABLE[0, 37, 22]
BUFIO2:ENABLE[0, 36, 18]
BUFIO3:ENABLE[0, 37, 18]
BUFR0:ENABLE[0, 32, 30]
BUFR1:ENABLE[0, 32, 26]
BUFR2:ENABLE[0, 32, 20]
BUFR3:ENABLE[0, 32, 19]
DCI:CASCADE_FROM_ABOVE[0, 38, 21]
DCI:CASCADE_FROM_BELOW[0, 38, 22]
DCI:DYNAMIC_ENABLE[0, 41, 31]
DCI:ENABLE[0, 39, 31]
DCI:QUIET[0, 38, 14]
HCLK_IOI:BUF.RCLK0[0, 32, 29]
HCLK_IOI:BUF.RCLK1[0, 30, 31]
HCLK_IOI:BUF.RCLK2[0, 31, 19]
HCLK_IOI:BUF.RCLK3[0, 28, 17]
HCLK_IOI:ENABLE.HCLK0[0, 28, 15]
HCLK_IOI:ENABLE.HCLK1[0, 29, 14]
HCLK_IOI:ENABLE.HCLK10[0, 29, 17]
HCLK_IOI:ENABLE.HCLK11[0, 29, 19]
HCLK_IOI:ENABLE.HCLK2[0, 29, 16]
HCLK_IOI:ENABLE.HCLK3[0, 29, 18]
HCLK_IOI:ENABLE.HCLK4[0, 29, 23]
HCLK_IOI:ENABLE.HCLK5[0, 29, 27]
HCLK_IOI:ENABLE.HCLK6[0, 29, 30]
HCLK_IOI:ENABLE.HCLK7[0, 29, 31]
HCLK_IOI:ENABLE.HCLK8[0, 28, 14]
HCLK_IOI:ENABLE.HCLK9[0, 29, 15]
HCLK_IOI:ENABLE.PERF0[0, 36, 28]
HCLK_IOI:ENABLE.PERF1[0, 36, 20]
HCLK_IOI:ENABLE.PERF2[0, 36, 14]
HCLK_IOI:ENABLE.PERF3[0, 37, 14]
IDELAYCTRL:HIGH_PERFORMANCE_MODE[0, 37, 26]
Non-inverted[0]
BUFR0:MUX.I[0, 35, 29][0, 35, 28][0, 35, 27][0, 35, 26][0, 35, 25][0, 34, 31][0, 35, 24][0, 35, 23]
BUFR1:MUX.I[0, 34, 29][0, 34, 30][0, 34, 26][0, 34, 25][0, 34, 24][0, 34, 23][0, 36, 27][0, 36, 26]
BUFR2:MUX.I[0, 34, 20][0, 34, 19][0, 34, 18][0, 34, 17][0, 34, 16][0, 34, 15][0, 36, 25][0, 36, 24]
BUFR3:MUX.I[0, 35, 15][0, 35, 16][0, 35, 17][0, 35, 18][0, 35, 19][0, 31, 20][0, 35, 21][0, 32, 16]
NONE00000000
BUFIO0_I00000001
BUFIO1_I00000010
BUFIO2_I00000100
BUFIO3_I00001000
CKINT000010000
CKINT100100000
CKINT201000000
CKINT310000000
BUFR0:BUFR_DIVIDE[0, 33, 28][0, 33, 29][0, 33, 30][0, 33, 27]
BUFR1:BUFR_DIVIDE[0, 33, 24][0, 33, 25][0, 33, 26][0, 33, 23]
BUFR2:BUFR_DIVIDE[0, 33, 19][0, 33, 20][0, 33, 21][0, 33, 18]
BUFR3:BUFR_DIVIDE[0, 33, 15][0, 33, 16][0, 33, 17][0, 33, 14]
BYPASS0000
10001
20011
30101
40111
51001
61011
71101
81111
BUFIO0:DELAY_BYPASS[0, 36, 31]
BUFIO1:DELAY_BYPASS[0, 36, 21]
BUFIO2:DELAY_BYPASS[0, 36, 16]
BUFIO3:DELAY_BYPASS[0, 37, 16]
Inverted~[0]
BUFIO0:MUX.I[0, 36, 29]
BUFIO1:MUX.I[0, 37, 21]
BUFIO2:MUX.I[0, 36, 17]
BUFIO3:MUX.I[0, 37, 17]
CCIO0
PERF1
IDELAYCTRL:MODE[0, 37, 24][0, 37, 29][0, 37, 28]
NONE000
DEFAULT001
FULL_0011
FULL_1111
DCI:NREF_OUTPUT[0, 39, 29][0, 39, 30]
DCI:PREF_OUTPUT[0, 40, 17][0, 40, 18]
DCI:TEST_ENABLE[0, 38, 31][0, 38, 15]
Non-inverted[1][0]
DCI:NREF_OUTPUT_HALF[0, 39, 26][0, 39, 27][0, 39, 28]
DCI:NREF_TERM_SPLIT[0, 39, 23][0, 39, 24][0, 39, 25]
DCI:PREF_OUTPUT_HALF[0, 40, 14][0, 40, 15][0, 40, 16]
Non-inverted[2][1][0]
INTERNAL_VREF:VREF[0, 40, 23][0, 40, 24][0, 40, 25][0, 40, 26][0, 40, 28][0, 40, 27][0, 40, 19]
OFF0000000
6000000011
6750000101
7500001001
9000010001
11000100001
12501000001
LVDS:LVDSBIAS[0, 40, 31][0, 41, 30][0, 41, 29][0, 41, 28][0, 41, 27][0, 41, 26][0, 41, 25][0, 41, 24][0, 41, 23][0, 41, 22][0, 41, 21][0, 41, 20][0, 41, 19][0, 41, 18][0, 41, 17][0, 41, 16][0, 41, 15][0, 41, 14]
Non-inverted[17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]

Bitstream — HCLK_IOI_HR

HCLK_IOI_HR bittile 0
RowColumn
01234567891011121314151617181920212223242526272829303132333435363738394041
0 ------------------------------------------
1 ------------------------------------------
2 ------------------------------------------
3 ------------------------------------------
4 ------------------------------------------
5 ------------------------------------------
6 ------------------------------------------
7 ------------------------------------------
8 ------------------------------------------
9 ------------------------------------------
10 ------------------------------------------
11 ------------------------------------------
12 ------------------------------------------
13 ------------------------------------------
14 --------------------------HCLK_IOI:MUX.HCLK_IO_D3[6]HCLK_IOI:MUX.HCLK_IO_U3[5]HCLK_IOI:ENABLE.HCLK8HCLK_IOI:ENABLE.HCLK1HCLK_IOI:MUX.HCLK_IO_U5[2]HCLK_IOI:MUX.HCLK_IO_D5[2]HCLK_IOI:MUX.HCLK_IO_U4[6]BUFR3:BUFR_DIVIDE[0]--HCLK_IOI:ENABLE.PERF2HCLK_IOI:ENABLE.PERF3DRIVERBIAS:DRIVERBIAS[3]DRIVERBIAS:DRIVERBIAS[14]LVDS:GROUP1[13]LVDS:GROUP0[6]
15 --------------------------HCLK_IOI:MUX.HCLK_IO_U3[4]HCLK_IOI:MUX.HCLK_IO_D3[5]HCLK_IOI:ENABLE.HCLK0HCLK_IOI:ENABLE.HCLK9HCLK_IOI:MUX.HCLK_IO_D5[3]HCLK_IOI:MUX.HCLK_IO_U5[1]HCLK_IOI:MUX.HCLK_IO_U4[5]BUFR3:BUFR_DIVIDE[3]BUFR2:MUX.I[2]BUFR3:MUX.I[7]--DRIVERBIAS:DRIVERBIAS[4]DRIVERBIAS:DRIVERBIAS[15]LVDS:GROUP1[12]LVDS:GROUP0[12]
16 --------------------------HCLK_IOI:MUX.HCLK_IO_D3[4]HCLK_IOI:MUX.HCLK_IO_U3[6]-HCLK_IOI:ENABLE.HCLK2HCLK_IOI:MUX.HCLK_IO_U5[3]HCLK_IOI:MUX.HCLK_IO_D5[1]BUFR3:MUX.I[0]BUFR3:BUFR_DIVIDE[2]BUFR2:MUX.I[3]BUFR3:MUX.I[6]~BUFIO2:DELAY_BYPASS~BUFIO3:DELAY_BYPASS-DRIVERBIAS:DRIVERBIAS[0]LVDS:GROUP1[11]LVDS:GROUP0[11]
17 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[6]HCLK_IOI:MUX.HCLK_IO_D1[0]HCLK_IOI:BUF.RCLK3HCLK_IOI:ENABLE.HCLK10HCLK_IOI:MUX.HCLK_IO_U5[4]HCLK_IOI:MUX.HCLK_IO_U5[0]-BUFR3:BUFR_DIVIDE[1]BUFR2:MUX.I[4]BUFR3:MUX.I[5]BUFIO2:MUX.IBUFIO3:MUX.I-DRIVERBIAS:DRIVERBIAS[1]LVDS:GROUP1[10]LVDS:GROUP0[10]
18 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[5]HCLK_IOI:MUX.HCLK_IO_U1[0]HCLK_IOI:MUX.HCLK_IO_D0[5]HCLK_IOI:ENABLE.HCLK3HCLK_IOI:MUX.HCLK_IO_U5[5]HCLK_IOI:MUX.HCLK_IO_D5[0]-BUFR2:BUFR_DIVIDE[0]BUFR2:MUX.I[5]BUFR3:MUX.I[4]BUFIO2:ENABLEBUFIO3:ENABLELVDS:GROUP1[0]DRIVERBIAS:DRIVERBIAS[2]LVDS:GROUP1[9]LVDS:GROUP0[9]
19 --------------------------HCLK_IOI:MUX.HCLK_IO_U0[4]HCLK_IOI:MUX.HCLK_IO_D0[1]HCLK_IOI:MUX.HCLK_IO_D1[6]HCLK_IOI:ENABLE.HCLK11HCLK_IOI:MUX.HCLK_IO_U5[6]HCLK_IOI:BUF.RCLK2BUFR3:ENABLEBUFR2:BUFR_DIVIDE[3]BUFR2:MUX.I[6]BUFR3:MUX.I[3]--LVDS:GROUP1[1]DRIVERBIAS:DRIVERBIAS[5]LVDS:GROUP1[8]LVDS:GROUP0[8]
20 --------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:MUX.HCLK_IO_D1[1]HCLK_IOI:MUX.HCLK_IO_D4[6]HCLK_IOI:MUX.HCLK_IO_U3[2]HCLK_IOI:MUX.HCLK_IO_U2[6]BUFR3:MUX.I[2]BUFR2:ENABLEBUFR2:BUFR_DIVIDE[2]BUFR2:MUX.I[7]-HCLK_IOI:ENABLE.PERF1-LVDS:GROUP1[2]DRIVERBIAS:DRIVERBIAS[6]LVDS:GROUP1[7]LVDS:GROUP0[7]
21 --------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:MUX.HCLK_IO_U0[1]HCLK_IOI:MUX.HCLK_IO_U4[3]HCLK_IOI:MUX.HCLK_IO_D3[3]HCLK_IOI:MUX.HCLK_IO_U2[5]HCLK_IOI:MUX.HCLK_IO_D5[6]-BUFR2:BUFR_DIVIDE[1]-BUFR3:MUX.I[1]~BUFIO1:DELAY_BYPASSBUFIO1:MUX.I-DRIVERBIAS:DRIVERBIAS[7]LVDS:GROUP1[6]DRIVERBIAS:DRIVERBIAS[13]
22 --------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:MUX.HCLK_IO_U1[1]HCLK_IOI:MUX.HCLK_IO_D4[3]HCLK_IOI:MUX.HCLK_IO_U3[3]HCLK_IOI:MUX.HCLK_IO_U2[4]HCLK_IOI:MUX.HCLK_IO_D5[5]-----BUFIO1:ENABLEVCCOSENSE:FLAGINTERNAL_VREF:VREF[2]LVDS:GROUP1[5]DRIVERBIAS:DRIVERBIAS[12]
23 --------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:MUX.HCLK_IO_D0[2]HCLK_IOI:MUX.HCLK_IO_U4[2]HCLK_IOI:ENABLE.HCLK4HCLK_IOI:MUX.HCLK_IO_U2[3]HCLK_IOI:MUX.HCLK_IO_D5[4]HCLK_IOI:MUX.HCLK_IO_U4[4]BUFR1:BUFR_DIVIDE[0]BUFR1:MUX.I[2]BUFR0:MUX.I[0]--LVDS:GROUP0[0]LVDS:COMMON[6]LVDS:GROUP1[4]DRIVERBIAS:DRIVERBIAS[11]
24 --------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:MUX.HCLK_IO_D1[2]HCLK_IOI:MUX.HCLK_IO_D3[2]HCLK_IOI:MUX.HCLK_IO_D0[4]HCLK_IOI:MUX.HCLK_IO_D2[3]HCLK_IOI:MUX.HCLK_IO_D2[5]HCLK_IOI:MUX.HCLK_IO_U1[4]BUFR1:BUFR_DIVIDE[3]BUFR1:MUX.I[3]BUFR0:MUX.I[1]BUFR2:MUX.I[0]IDELAYCTRL:MODE[2]LVDS:GROUP0[1]INTERNAL_VREF:VREF[3]LVDS:GROUP1[3]DRIVERBIAS:DRIVERBIAS[10]
25 --------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:MUX.HCLK_IO_U0[2]HCLK_IOI:MUX.HCLK_IO_D4[2]HCLK_IOI:MUX.HCLK_IO_D0[6]HCLK_IOI:MUX.HCLK_IO_U2[2]HCLK_IOI:MUX.HCLK_IO_D2[4]HCLK_IOI:MUX.HCLK_IO_D1[4]BUFR1:BUFR_DIVIDE[2]BUFR1:MUX.I[4]BUFR0:MUX.I[3]BUFR2:MUX.I[1]-LVDS:GROUP0[2]VCCOSENSE:MODE[0]LVDS:COMMON[4]DRIVERBIAS:DRIVERBIAS[9]
26 --------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.HCLK_IO_U1[2]HCLK_IOI:MUX.HCLK_IO_U3[1]HCLK_IOI:MUX.HCLK_IO_U0[3]HCLK_IOI:MUX.HCLK_IO_D2[2]HCLK_IOI:MUX.HCLK_IO_D2[6]BUFR1:ENABLEBUFR1:BUFR_DIVIDE[1]BUFR1:MUX.I[5]BUFR0:MUX.I[4]BUFR1:MUX.I[0]IDELAYCTRL:HIGH_PERFORMANCE_MODEINTERNAL_VREF:VREF[0]VCCOSENSE:MODE[1]LVDS:COMMON[3]DRIVERBIAS:DRIVERBIAS[8]
27 --------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.HCLK_IO_D0[3]HCLK_IOI:MUX.HCLK_IO_U4[1]HCLK_IOI:ENABLE.HCLK5HCLK_IOI:MUX.HCLK_IO_U2[1]HCLK_IOI:MUX.HCLK_IO_D4[4]-BUFR0:BUFR_DIVIDE[0]-BUFR0:MUX.I[5]BUFR1:MUX.I[1]-LVDS:GROUP0[14]VCCOSENSE:MODE[2]LVDS:COMMON[2]LVDS:GROUP0[5]
28 --------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.HCLK_IO_D1[3]HCLK_IOI:MUX.HCLK_IO_D3[1]HCLK_IOI:MUX.HCLK_IO_U0[0]HCLK_IOI:MUX.HCLK_IO_D2[1]HCLK_IOI:MUX.HCLK_IO_U1[6]-BUFR0:BUFR_DIVIDE[3]-BUFR0:MUX.I[6]HCLK_IOI:ENABLE.PERF0IDELAYCTRL:MODE[0]LVDS:GROUP0[13]VCCOSENSE:MODE[3]LVDS:COMMON[1]LVDS:GROUP0[4]
29 --------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.HCLK_IO_U1[3]HCLK_IOI:MUX.HCLK_IO_D4[1]HCLK_IOI:MUX.HCLK_IO_D0[0]HCLK_IOI:MUX.HCLK_IO_U2[0]HCLK_IOI:MUX.HCLK_IO_D1[5]HCLK_IOI:BUF.RCLK0BUFR0:BUFR_DIVIDE[2]BUFR1:MUX.I[7]BUFR0:MUX.I[7]BUFIO0:MUX.IIDELAYCTRL:MODE[1]INTERNAL_VREF:VREF[5]INTERNAL_VREF:VREF[4]LVDS:GROUP0[15]LVDS:GROUP0[3]
30 --------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.HCLK_IO_D4[0]HCLK_IOI:MUX.HCLK_IO_U3[0]HCLK_IOI:ENABLE.HCLK6HCLK_IOI:MUX.HCLK_IO_D2[0]HCLK_IOI:MUX.HCLK_IO_D4[5]BUFR0:ENABLEBUFR0:BUFR_DIVIDE[1]BUFR1:MUX.I[6]---INTERNAL_VREF:VREF[6]INTERNAL_VREF:VREF[1]LVDS:COMMON[0]LVDS:COMMON[8]
31 --------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.HCLK_IO_D3[0]HCLK_IOI:MUX.HCLK_IO_U4[0]HCLK_IOI:ENABLE.HCLK7HCLK_IOI:BUF.RCLK1HCLK_IOI:MUX.HCLK_IO_U1[5]--BUFR0:MUX.I[2]-~BUFIO0:DELAY_BYPASSBUFIO0:ENABLELVDS:GROUP1[15]LVDS:GROUP1[14]LVDS:COMMON[5]LVDS:COMMON[7]
IDELAYCTRL:MUX.REFCLK[0, 26, 31][0, 26, 30][0, 26, 29][0, 26, 28][0, 26, 27][0, 26, 26][0, 26, 25][0, 26, 24][0, 26, 23][0, 26, 22][0, 26, 21][0, 26, 20]
NONE000000000000
HCLK_IO_D0000000000001
HCLK_IO_D1000000000010
HCLK_IO_D2000000000100
HCLK_IO_D3000000001000
HCLK_IO_D4000000010000
HCLK_IO_D5000000100000
HCLK_IO_U0000001000000
HCLK_IO_U1000010000000
HCLK_IO_U2000100000000
HCLK_IO_U3001000000000
HCLK_IO_U4010000000000
HCLK_IO_U5100000000000
HCLK_IOI:MUX.HCLK_IO_D0[0, 29, 25][0, 28, 18][0, 29, 24][0, 27, 27][0, 27, 23][0, 27, 19][0, 29, 29]
HCLK_IOI:MUX.HCLK_IO_D1[0, 28, 19][0, 31, 29][0, 32, 25][0, 27, 28][0, 27, 24][0, 27, 20][0, 27, 17]
HCLK_IOI:MUX.HCLK_IO_D2[0, 31, 26][0, 31, 24][0, 31, 25][0, 30, 24][0, 30, 26][0, 30, 28][0, 30, 30]
HCLK_IOI:MUX.HCLK_IO_D3[0, 26, 14][0, 27, 15][0, 26, 16][0, 29, 21][0, 28, 24][0, 28, 28][0, 27, 31]
HCLK_IOI:MUX.HCLK_IO_D4[0, 28, 20][0, 31, 30][0, 31, 27][0, 28, 22][0, 28, 25][0, 28, 29][0, 27, 30]
HCLK_IOI:MUX.HCLK_IO_D5[0, 31, 21][0, 31, 22][0, 31, 23][0, 30, 15][0, 31, 14][0, 31, 16][0, 31, 18]
HCLK_IOI:MUX.HCLK_IO_U0[0, 26, 17][0, 26, 18][0, 26, 19][0, 29, 26][0, 27, 25][0, 27, 21][0, 29, 28]
HCLK_IOI:MUX.HCLK_IO_U1[0, 31, 28][0, 31, 31][0, 32, 24][0, 27, 29][0, 27, 26][0, 27, 22][0, 27, 18]
HCLK_IOI:MUX.HCLK_IO_U2[0, 30, 20][0, 30, 21][0, 30, 22][0, 30, 23][0, 30, 25][0, 30, 27][0, 30, 29]
HCLK_IOI:MUX.HCLK_IO_U3[0, 27, 16][0, 27, 14][0, 26, 15][0, 29, 22][0, 29, 20][0, 28, 26][0, 28, 30]
HCLK_IOI:MUX.HCLK_IO_U4[0, 32, 14][0, 32, 15][0, 32, 23][0, 28, 21][0, 28, 23][0, 28, 27][0, 28, 31]
HCLK_IOI:MUX.HCLK_IO_U5[0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 30, 14][0, 31, 15][0, 31, 17]
NONE0000000
HCLK00010001
HCLK10010010
HCLK20010100
HCLK30011000
HCLK40100001
HCLK50100010
HCLK60100100
HCLK70101000
HCLK81000001
HCLK91000010
HCLK101000100
HCLK111001000
BUFIO0:ENABLE[0, 37, 31]
BUFIO1:ENABLE[0, 37, 22]
BUFIO2:ENABLE[0, 36, 18]
BUFIO3:ENABLE[0, 37, 18]
BUFR0:ENABLE[0, 32, 30]
BUFR1:ENABLE[0, 32, 26]
BUFR2:ENABLE[0, 32, 20]
BUFR3:ENABLE[0, 32, 19]
HCLK_IOI:BUF.RCLK0[0, 32, 29]
HCLK_IOI:BUF.RCLK1[0, 30, 31]
HCLK_IOI:BUF.RCLK2[0, 31, 19]
HCLK_IOI:BUF.RCLK3[0, 28, 17]
HCLK_IOI:ENABLE.HCLK0[0, 28, 15]
HCLK_IOI:ENABLE.HCLK1[0, 29, 14]
HCLK_IOI:ENABLE.HCLK10[0, 29, 17]
HCLK_IOI:ENABLE.HCLK11[0, 29, 19]
HCLK_IOI:ENABLE.HCLK2[0, 29, 16]
HCLK_IOI:ENABLE.HCLK3[0, 29, 18]
HCLK_IOI:ENABLE.HCLK4[0, 29, 23]
HCLK_IOI:ENABLE.HCLK5[0, 29, 27]
HCLK_IOI:ENABLE.HCLK6[0, 29, 30]
HCLK_IOI:ENABLE.HCLK7[0, 29, 31]
HCLK_IOI:ENABLE.HCLK8[0, 28, 14]
HCLK_IOI:ENABLE.HCLK9[0, 29, 15]
HCLK_IOI:ENABLE.PERF0[0, 36, 28]
HCLK_IOI:ENABLE.PERF1[0, 36, 20]
HCLK_IOI:ENABLE.PERF2[0, 36, 14]
HCLK_IOI:ENABLE.PERF3[0, 37, 14]
IDELAYCTRL:HIGH_PERFORMANCE_MODE[0, 37, 26]
VCCOSENSE:FLAG[0, 38, 22]
Non-inverted[0]
BUFR0:MUX.I[0, 35, 29][0, 35, 28][0, 35, 27][0, 35, 26][0, 35, 25][0, 34, 31][0, 35, 24][0, 35, 23]
BUFR1:MUX.I[0, 34, 29][0, 34, 30][0, 34, 26][0, 34, 25][0, 34, 24][0, 34, 23][0, 36, 27][0, 36, 26]
BUFR2:MUX.I[0, 34, 20][0, 34, 19][0, 34, 18][0, 34, 17][0, 34, 16][0, 34, 15][0, 36, 25][0, 36, 24]
BUFR3:MUX.I[0, 35, 15][0, 35, 16][0, 35, 17][0, 35, 18][0, 35, 19][0, 31, 20][0, 35, 21][0, 32, 16]
NONE00000000
BUFIO0_I00000001
BUFIO1_I00000010
BUFIO2_I00000100
BUFIO3_I00001000
CKINT000010000
CKINT100100000
CKINT201000000
CKINT310000000
BUFR0:BUFR_DIVIDE[0, 33, 28][0, 33, 29][0, 33, 30][0, 33, 27]
BUFR1:BUFR_DIVIDE[0, 33, 24][0, 33, 25][0, 33, 26][0, 33, 23]
BUFR2:BUFR_DIVIDE[0, 33, 19][0, 33, 20][0, 33, 21][0, 33, 18]
BUFR3:BUFR_DIVIDE[0, 33, 15][0, 33, 16][0, 33, 17][0, 33, 14]
BYPASS0000
10001
20011
30101
40111
51001
61011
71101
81111
BUFIO0:DELAY_BYPASS[0, 36, 31]
BUFIO1:DELAY_BYPASS[0, 36, 21]
BUFIO2:DELAY_BYPASS[0, 36, 16]
BUFIO3:DELAY_BYPASS[0, 37, 16]
Inverted~[0]
BUFIO0:MUX.I[0, 36, 29]
BUFIO1:MUX.I[0, 37, 21]
BUFIO2:MUX.I[0, 36, 17]
BUFIO3:MUX.I[0, 37, 17]
CCIO0
PERF1
IDELAYCTRL:MODE[0, 37, 24][0, 37, 29][0, 37, 28]
NONE000
DEFAULT001
FULL_0011
FULL_1111
DRIVERBIAS:DRIVERBIAS[0, 39, 15][0, 39, 14][0, 41, 21][0, 41, 22][0, 41, 23][0, 41, 24][0, 41, 25][0, 41, 26][0, 39, 21][0, 39, 20][0, 39, 19][0, 38, 15][0, 38, 14][0, 39, 18][0, 39, 17][0, 39, 16]
LVDS:GROUP0[0, 40, 29][0, 38, 27][0, 38, 28][0, 41, 15][0, 41, 16][0, 41, 17][0, 41, 18][0, 41, 19][0, 41, 20][0, 41, 14][0, 41, 27][0, 41, 28][0, 41, 29][0, 38, 25][0, 38, 24][0, 38, 23]
LVDS:GROUP1[0, 38, 31][0, 39, 31][0, 40, 14][0, 40, 15][0, 40, 16][0, 40, 17][0, 40, 18][0, 40, 19][0, 40, 20][0, 40, 21][0, 40, 22][0, 40, 23][0, 40, 24][0, 38, 20][0, 38, 19][0, 38, 18]
Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
INTERNAL_VREF:VREF[0, 38, 30][0, 38, 29][0, 39, 29][0, 39, 24][0, 39, 22][0, 39, 30][0, 38, 26]
OFF0000000
6000000011
6750000101
7500001001
9000010001
11000100001
12501000001
VCCOSENSE:MODE[0, 39, 28][0, 39, 27][0, 39, 26][0, 39, 25]
ALWAYSACTIVE0000
OFF0111
FREEZE1000
LVDS:COMMON[0, 41, 30][0, 41, 31][0, 39, 23][0, 40, 31][0, 40, 25][0, 40, 26][0, 40, 27][0, 40, 28][0, 40, 30]
Non-inverted[8][7][6][5][4][3][2][1][0]

Tables — HP IO

NameHP_IOSTD:PDRIVEHP_IOSTD:NDRIVE
[6][5][4][3][2][1][0][6][5][4][3][2][1][0]
HSTL_I01010000011100
HSTL_II10101100111000
HSTL_II_1810000000111000
HSTL_II_DCI10100100111000
HSTL_II_DCI_1810000000111000
HSTL_II_T_DCI01010000011100
HSTL_II_T_DCI_1801000000011100
HSTL_I_1210101000100100
HSTL_I_1801000000011100
HSTL_I_DCI01010000011100
HSTL_I_DCI_1801000000011100
HSUL_1210000000100000
LVCMOS12.200100100001100
LVCMOS12.401000100010100
LVCMOS12.601110000011100
LVCMOS12.810011000100100
LVCMOS15.1210000100110000
LVCMOS15.1610110101000000
LVCMOS15.200011000001000
LVCMOS15.400101100010000
LVCMOS15.601000000011000
LVCMOS15.801011000100000
LVCMOS18.1201011000101000
LVCMOS18.1601110100110100
LVCMOS18.200010000001000
LVCMOS18.400011100001100
LVCMOS18.600111100010100
LVCMOS18.800111000011000
OFF00000000000000
SSTL1210110000101000
SSTL12_DCI10110000101000
SSTL12_T_DCI10110000101000
SSTL13510001000101000
SSTL135_DCI10001000101000
SSTL135_T_DCI10001000101000
SSTL1501100000100100
SSTL15_DCI01100000100100
SSTL15_T_DCI01100000100100
SSTL18_I00111000011000
SSTL18_II10101101001000
SSTL18_II_DCI01011000100000
SSTL18_II_T_DCI00101000010100
SSTL18_I_DCI00101000010100
NameHP_IOSTD:PSLEWHP_IOSTD:NSLEW
[4][3][2][1][0][4][3][2][1][0]
HSLVDCI_150011111111
HSLVDCI_180011011111
HSTL_I.FAST1110011111
HSTL_I.SLOW0001000001
HSTL_II.FAST0100011111
HSTL_II.SLOW0000100001
HSTL_II_18.FAST0010011111
HSTL_II_18.SLOW0000100010
HSTL_II_DCI.FAST0100011111
HSTL_II_DCI.SLOW0000100001
HSTL_II_DCI_18.FAST0010011111
HSTL_II_DCI_18.SLOW0000100010
HSTL_II_T_DCI.FAST1110011111
HSTL_II_T_DCI.SLOW0001000001
HSTL_II_T_DCI_18.FAST0011111111
HSTL_II_T_DCI_18.SLOW0000100011
HSTL_I_12.FAST1101111111
HSTL_I_12.SLOW0000100001
HSTL_I_18.FAST0011111111
HSTL_I_18.SLOW0000100011
HSTL_I_DCI.FAST1110011111
HSTL_I_DCI.SLOW0001000001
HSTL_I_DCI_18.FAST0011111111
HSTL_I_DCI_18.SLOW0000100011
HSUL_12.FAST0011111111
HSUL_12.SLOW0000100010
HSUL_12_DCI.FAST0011111111
HSUL_12_DCI.SLOW0000100010
LVCMOS12.2.FAST1111111000
LVCMOS12.2.SLOW0000000000
LVCMOS12.4.FAST1111111111
LVCMOS12.4.SLOW0000000000
LVCMOS12.6.FAST1111111111
LVCMOS12.6.SLOW0000000000
LVCMOS12.8.FAST1100111111
LVCMOS12.8.SLOW0000000000
LVCMOS15.12.FAST0100011111
LVCMOS15.12.SLOW0000000000
LVCMOS15.16.FAST0011011111
LVCMOS15.16.SLOW0000000000
LVCMOS15.2.FAST1111100001
LVCMOS15.2.SLOW0000000000
LVCMOS15.4.FAST1111111111
LVCMOS15.4.SLOW0000000000
LVCMOS15.6.FAST1111111111
LVCMOS15.6.SLOW0000000000
LVCMOS15.8.FAST0100111111
LVCMOS15.8.SLOW0000000000
LVCMOS18.12.FAST0111111111
LVCMOS18.12.SLOW0000000000
LVCMOS18.16.FAST0011011111
LVCMOS18.16.SLOW0000000000
LVCMOS18.2.FAST1000111111
LVCMOS18.2.SLOW0000000000
LVCMOS18.4.FAST1111111111
LVCMOS18.4.SLOW0000000000
LVCMOS18.6.FAST0011111111
LVCMOS18.6.SLOW0000000000
LVCMOS18.8.FAST0011011111
LVCMOS18.8.SLOW0000000000
LVDCI_150011111111
LVDCI_180011011111
LVDCI_DV2_150111111000
LVDCI_DV2_180110011000
OFF0000000000
SSTL12.FAST1101011111
SSTL12.SLOW0001100011
SSTL12_DCI.FAST1101011111
SSTL12_DCI.SLOW0001100011
SSTL12_T_DCI.FAST1101011111
SSTL12_T_DCI.SLOW0001100011
SSTL135.FAST1111011111
SSTL135.SLOW0001100011
SSTL135_DCI.FAST1111011111
SSTL135_DCI.SLOW0001100011
SSTL135_T_DCI.FAST1111011111
SSTL135_T_DCI.SLOW0001100011
SSTL15.FAST1111111010
SSTL15.SLOW0001100111
SSTL15_DCI.FAST1111111010
SSTL15_DCI.SLOW0001100111
SSTL15_T_DCI.FAST1111111010
SSTL15_T_DCI.SLOW0001100111
SSTL18_I.FAST0010111011
SSTL18_I.SLOW0000100011
SSTL18_II.FAST0001111111
SSTL18_II.SLOW0000000000
SSTL18_II_DCI.FAST0011111100
SSTL18_II_DCI.SLOW0001100101
SSTL18_II_T_DCI.FAST0010111111
SSTL18_II_T_DCI.SLOW0001100111
SSTL18_I_DCI.FAST0010111111
SSTL18_I_DCI.SLOW0001100111
VR1111111111
NameHP_IOSTD:LVDS_THP_IOSTD:LVDS_C
[8][7][6][5][4][3][2][1][0][8][7][6][5][4][3][2][1][0]
OFF000000000000000000
OUTPUT_LVDS110000000001110111
TERM_DYNAMIC_LVDS000000001101110111
TERM_LVDS000000000101110111
NameHP_IOSTD:LVDSBIAS
[17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
LVDS110000000000000010
OFF000000000000000000
NameHP_IOSTD:DCI:PREF_OUTPUTHP_IOSTD:DCI:NREF_OUTPUT
[1][0][1][0]
HSLVDCI_150000
HSLVDCI_180000
HSUL_12_DCI0110
LVDCI_150110
LVDCI_180110
OFF0000
NameHP_IOSTD:DCI:PREF_OUTPUT_HALFHP_IOSTD:DCI:NREF_OUTPUT_HALF
[2][1][0][2][1][0]
LVDCI_DV2_15011100
LVDCI_DV2_18101100
OFF000000
NameHP_IOSTD:DCI:NREF_TERM_SPLIT
[2][1][0]
HSTL_II_DCI001
HSTL_II_DCI_18001
HSTL_II_T_DCI001
HSTL_II_T_DCI_18001
HSTL_I_DCI001
HSTL_I_DCI_18001
OFF000
SSTL12_DCI001
SSTL12_T_DCI001
SSTL135_DCI001
SSTL135_T_DCI001
SSTL15_DCI001
SSTL15_T_DCI001
SSTL18_II_DCI001
SSTL18_II_T_DCI001
SSTL18_I_DCI001

Tables — HR IO

NameHR_IOSTD:DRIVE
[6][5][4][3][2][1][0]
BLVDS_251010110
HSTL_I0100011
HSTL_II1000110
HSTL_II_181100111
HSTL_I_180110011
HSUL_120110111
LVCMOS12.120110111
LVCMOS12.40010010
LVCMOS12.80100100
LVCMOS15.120110101
LVCMOS15.161010111
LVCMOS15.40010001
LVCMOS15.80100011
LVCMOS18.120100010
LVCMOS18.160110011
LVCMOS18.241100110
LVCMOS18.40010001
LVCMOS18.80100010
LVCMOS25.120110100
LVCMOS25.161010110
LVCMOS25.40010001
LVCMOS25.80100100
LVCMOS33.120110011
LVCMOS33.161010101
LVCMOS33.40010001
LVCMOS33.80100010
LVTTL.120100010
LVTTL.160110011
LVTTL.241100110
LVTTL.40010001
LVTTL.80100010
MOBILE_DDR0100010
OFF0000000
PCI33_31110111
SSTL1351000111
SSTL135_R0100100
SSTL151010111
SSTL15_R0100011
SSTL18_I0100010
SSTL18_II1010110
NameHR_IOSTD:SLEW
[9][8][7][6][5][4][3][2][1][0]
BLVDS_250000000010
HSTL_I.FAST0101000110
HSTL_I.SLOW0110011010
HSTL_II.FAST0101000110
HSTL_II.SLOW0110011010
HSTL_II_18.FAST0101010110
HSTL_II_18.SLOW0110011010
HSTL_I_18.FAST0101000110
HSTL_I_18.SLOW0110011010
HSUL_12.FAST0101011110
HSUL_12.SLOW0110011010
LVCMOS12.12.FAST0000000010
LVCMOS12.12.SLOW0110011010
LVCMOS12.4.FAST0000000010
LVCMOS12.4.SLOW0110011010
LVCMOS12.8.FAST0000000010
LVCMOS12.8.SLOW0110011010
LVCMOS15.12.FAST0000000010
LVCMOS15.12.SLOW0110011010
LVCMOS15.16.FAST0000000010
LVCMOS15.16.SLOW0110011010
LVCMOS15.4.FAST0000000010
LVCMOS15.4.SLOW0110011010
LVCMOS15.8.FAST0000000010
LVCMOS15.8.SLOW0110011010
LVCMOS18.12.FAST0000000010
LVCMOS18.12.SLOW0110011010
LVCMOS18.16.FAST0000000010
LVCMOS18.16.SLOW0110011010
LVCMOS18.24.FAST0000000010
LVCMOS18.24.SLOW0110011010
LVCMOS18.4.FAST0000000010
LVCMOS18.4.SLOW0110011010
LVCMOS18.8.FAST0000000010
LVCMOS18.8.SLOW0110011010
LVCMOS25.12.FAST0000000010
LVCMOS25.12.SLOW0110011010
LVCMOS25.16.FAST0000000010
LVCMOS25.16.SLOW0110011010
LVCMOS25.4.FAST0000000010
LVCMOS25.4.SLOW0110011010
LVCMOS25.8.FAST0000000010
LVCMOS25.8.SLOW0110011010
LVCMOS33.12.FAST0000000001
LVCMOS33.12.SLOW0110011001
LVCMOS33.16.FAST0000000001
LVCMOS33.16.SLOW0110011001
LVCMOS33.4.FAST0000000001
LVCMOS33.4.SLOW0110011001
LVCMOS33.8.FAST0000000001
LVCMOS33.8.SLOW0110011001
LVTTL.12.FAST0000000001
LVTTL.12.SLOW0110011001
LVTTL.16.FAST0000000001
LVTTL.16.SLOW0110011001
LVTTL.24.FAST0000000001
LVTTL.24.SLOW0110011001
LVTTL.4.FAST0000000001
LVTTL.4.SLOW0110011001
LVTTL.8.FAST0000000001
LVTTL.8.SLOW0110011001
MOBILE_DDR.FAST0000000010
MOBILE_DDR.SLOW0110011010
OFF0000000000
PCI33_30011001111
SSTL135.FAST0101011110
SSTL135.SLOW0110011010
SSTL135_R.FAST0101011110
SSTL135_R.SLOW0110011010
SSTL15.FAST0101011110
SSTL15.SLOW0110011010
SSTL15_R.FAST0101011110
SSTL15_R.SLOW0110011010
SSTL18_I.FAST0101010110
SSTL18_I.SLOW0110011010
SSTL18_II.FAST0101010110
SSTL18_II.SLOW0110011010
NameHR_IOSTD:OUTPUT_MISC
[2][1][0]
BLVDS_25000
HSTL_I000
HSTL_II000
HSTL_II_18000
HSTL_I_18000
HSUL_12000
LVCMOS12000
LVCMOS15000
LVCMOS18000
LVCMOS25000
LVCMOS33000
LVTTL000
MOBILE_DDR000
OFF000
PCI33_3001
SSTL135000
SSTL135_R000
SSTL15000
SSTL15_R000
SSTL18_I000
SSTL18_II000
NameHR_IOSTD:LVDS_THR_IOSTD:LVDS_C
[12][11][10][9][8][7][6][5][4][3][2][1][0][12][11][10][9][8][7][6][5][4][3][2][1][0]
OFF00000000000000000000000000
OUTPUT_LVDS_2510101100001110000000000000
OUTPUT_MINI_LVDS_2510101100000000000000000000
OUTPUT_PPDS_2510100100000000000000000000
OUTPUT_RSDS_2510100100000000000000000000
OUTPUT_TMDS_3301000000000000000000000000
TERM_LVDS_2500100100000000000000000000
TERM_MINI_LVDS_2500100100000000000000000000
TERM_PPDS_2500100100000000000000000000
TERM_RSDS_2500100100000000000000000000
NameHR_IOSTD:DRIVERBIAS
[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
12001100000000010001
13501100000000010001
15001100000000010001
18001100000000010001
25000000000000000000
33000000000000000000
OFF0000000000000000
NameHR_IOSTD:LVDSBIAS:COMMONHR_IOSTD:LVDSBIAS:GROUP
[8][7][6][5][4][3][2][1][0][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
LVDS_250110101011101111001111111
MINI_LVDS_250110101011101111001111111
OFF0000000000000000000000000
PPDS_250110101011001111000110111
RSDS_250110101011101111001111111
TMDS_330110101011110100100000000