Configuration registers

Todo

document

COR

REG.COR bittile 0
Row	Column
	0
0	STARTUP:GWE_CYCLE[0]
1	STARTUP:GWE_CYCLE[1]
2	STARTUP:GWE_CYCLE[2]
3	STARTUP:GTS_CYCLE[0]
4	STARTUP:GTS_CYCLE[1]
5	STARTUP:GTS_CYCLE[2]
6	STARTUP:LCK_CYCLE[0]
7	STARTUP:LCK_CYCLE[1]
8	STARTUP:LCK_CYCLE[2]
9	STARTUP:MATCH_CYCLE[0]
10	STARTUP:MATCH_CYCLE[1]
11	STARTUP:MATCH_CYCLE[2]
12	STARTUP:DONE_CYCLE[0]
13	STARTUP:DONE_CYCLE[1]
14	STARTUP:DONE_CYCLE[2]
15	STARTUP:STARTUPCLK[0]
16	STARTUP:STARTUPCLK[1]
17	STARTUP:CONFIG_RATE[0]
18	STARTUP:CONFIG_RATE[1]
19	STARTUP:CONFIG_RATE[2]
20	STARTUP:CONFIG_RATE[3]
21	CAPTURE:EXTMASTERCCLK_DIV[0] STARTUP:CONFIG_RATE[4]
22	CAPTURE:EXTMASTERCCLK_DIV[1] STARTUP:CONFIG_RATE[5]
23	CAPTURE:ONESHOT
24	STARTUP:DRIVE_DONE
25	STARTUP:DONE_PIPE
26	CAPTURE:EXTMASTERCCLK_EN
27	STARTUP:DONE_SIGNALS_POWERDOWN

STARTUP:GTS_CYCLE	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
STARTUP:GWE_CYCLE	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
5	1	0	0
6	1	0	1
DONE	1	1	0
KEEP	1	1	1

STARTUP:LCK_CYCLE	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
STARTUP:MATCH_CYCLE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
0	0	0	0
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0
NOWAIT	1	1	1

STARTUP:DONE_CYCLE	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
5	1	0	0
6	1	0	1
KEEP	1	1	1

STARTUP:STARTUPCLK	[0, 0, 16]	[0, 0, 15]
CCLK	0	0
USERCLK	0	1
JTAGCLK	1	0

STARTUP:CONFIG_RATE	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]
3	0	0	0	0	0	0
9	0	0	0	0	0	1
22	0	0	0	1	0	0
40	0	0	1	0	1	1
6	0	1	0	0	0	0
16	0	1	0	0	0	1
26	0	1	0	0	1	0
50	0	1	0	1	0	1
66	0	1	1	0	0	0
12	1	0	0	0	0	0
33	1	0	0	0	0	1

CAPTURE:EXTMASTERCCLK_DIV	[0, 0, 22]	[0, 0, 21]
8	0	0
4	0	1
2	1	0
1	1	1

CAPTURE:EXTMASTERCCLK_EN	[0, 0, 26]
CAPTURE:ONESHOT	[0, 0, 23]
STARTUP:DONE_PIPE	[0, 0, 25]
STARTUP:DONE_SIGNALS_POWERDOWN	[0, 0, 27]
STARTUP:DRIVE_DONE	[0, 0, 24]
Non-inverted	[0]

COR1

REG.COR1 bittile 0
Row	Column
	0
0	MISC:BPI_PAGE_SIZE[0]
1	MISC:BPI_PAGE_SIZE[1]
2	MISC:BPI_1ST_READ_CYCLE[0]
3	MISC:BPI_1ST_READ_CYCLE[1]
4	-
5	-
6	MISC:POST_CRC_RECONFIG
7	MISC:POST_CRC_SEL
8	MISC:POST_CRC_EN
9	~MISC:POST_CRC_INIT_FLAG
10	MISC:TRIM_REG[0]
11	MISC:TRIM_REG[1]
12	MISC:TRIM_BITSTREAM
13	-
14	-
15	~MISC:POST_CRC_KEEP
16	MISC:POST_CRC_CORRECT
17	MISC:PERSIST_DEASSERT_AT_DESYNC
18	-
19	-
20	-
21	MISC:CFG_IO_ACCESS_TDO
22	-
23	-
24	-
25	-
26	MISC:POST_CRC_CLK
27	MISC:POST_CRC_FREQ[0]
28	MISC:POST_CRC_FREQ[1]
29	MISC:POST_CRC_FREQ[2]
30	-
31	MISC:XADC_PARTIAL_RECONFIG

MISC:BPI_PAGE_SIZE	[0, 0, 1]	[0, 0, 0]
1	0	0
4	0	1
8	1	0

MISC:BPI_1ST_READ_CYCLE	[0, 0, 3]	[0, 0, 2]
1	0	0
2	0	1
3	1	0
4	1	1

MISC:CFG_IO_ACCESS_TDO	[0, 0, 21]
MISC:PERSIST_DEASSERT_AT_DESYNC	[0, 0, 17]
MISC:POST_CRC_CORRECT	[0, 0, 16]
MISC:POST_CRC_EN	[0, 0, 8]
MISC:POST_CRC_RECONFIG	[0, 0, 6]
MISC:POST_CRC_SEL	[0, 0, 7]
MISC:TRIM_BITSTREAM	[0, 0, 12]
MISC:XADC_PARTIAL_RECONFIG	[0, 0, 31]
Non-inverted	[0]

MISC:POST_CRC_INIT_FLAG	[0, 0, 9]
MISC:POST_CRC_KEEP	[0, 0, 15]
Inverted	~[0]

MISC:TRIM_REG	[0, 0, 11]	[0, 0, 10]
Non-inverted	[1]	[0]

MISC:POST_CRC_CLK	[0, 0, 26]
CFG_CLK	0
INTERNAL	1

MISC:POST_CRC_FREQ	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]
50	0	0	0
25	0	0	1
13	0	1	0
6	0	1	1
3	1	0	0
2	1	0	1
1	1	1	0

CTL

REG.CTL bittile 0
Row	Column
	0
0	MISC:GTS_USR_B
1	-
2	-
3	MISC:PERSIST
4	MISC:SECURITY[0]
5	MISC:SECURITY[1]
6	MISC:ENCRYPT
7	FRAME_ECC:FARSRC
8	~MISC:GLUTMASK
9	~MISC:SELECTMAP_ABORT
10	~MISC:CONFIG_FALLBACK
11	MISC:SEC_ERROR
12	MISC:OVERTEMP_POWERDOWN
13	~MISC:INIT_SIGNALS_ERROR
14	MISC:SEC_STATUS
15	-
16	-
17	-
18	-
19	-
20	-
21	-
22	-
23	-
24	-
25	-
26	-
27	-
28	-
29	MISC:SEC_ALL
30	MISC:ICAP_SELECT
31	MISC:ENCRYPT_KEY_SELECT

MISC:ENCRYPT	[0, 0, 6]
MISC:GTS_USR_B	[0, 0, 0]
MISC:OVERTEMP_POWERDOWN	[0, 0, 12]
MISC:PERSIST	[0, 0, 3]
MISC:SEC_ALL	[0, 0, 29]
MISC:SEC_ERROR	[0, 0, 11]
MISC:SEC_STATUS	[0, 0, 14]
Non-inverted	[0]

MISC:SECURITY	[0, 0, 5]	[0, 0, 4]
NONE	0	0
LEVEL1	0	1
LEVEL2	1	0

FRAME_ECC:FARSRC	[0, 0, 7]
EFAR	0
FAR	1

MISC:CONFIG_FALLBACK	[0, 0, 10]
MISC:GLUTMASK	[0, 0, 8]
MISC:INIT_SIGNALS_ERROR	[0, 0, 13]
MISC:SELECTMAP_ABORT	[0, 0, 9]
Inverted	~[0]

MISC:ICAP_SELECT	[0, 0, 30]
TOP	0
BOTTOM	1

MISC:ENCRYPT_KEY_SELECT	[0, 0, 31]
BBRAM	0
EFUSE	1

CTL1

REG.CTL1 bittile 0
Row	Column
	0
0	MISC:MODE_PIN_TEST[0]
1	MISC:MODE_PIN_TEST[1]
2	MISC:DIS_VGG_REG
3	MISC:ENABLE_VGG_CLAMP
4	MISC:VGG_POS_GAIN_SEL
5	-
6	MISC:VGG_NEG_GAIN_SEL[0]
7	MISC:VGG_NEG_GAIN_SEL[1]
8	MISC:VGG_NEG_GAIN_SEL[2]
9	MISC:VGG_NEG_GAIN_SEL[3]
10	MISC:VGG_NEG_GAIN_SEL[4]
11	-
12	-
13	MISC:VGG_SEL[0]
14	MISC:VGG_SEL[1]
15	MISC:VGG_SEL[2]
16	MISC:VGG_SEL[3]
17	MISC:VGG_SEL[4]
18	-
19	-
20	MISC:ICAP_ENCRYPTION

MISC:MODE_PIN_TEST	[0, 0, 1]	[0, 0, 0]
DISABLE	0	0
TEST0	0	1
TEST1	1	0

MISC:DIS_VGG_REG	[0, 0, 2]
MISC:ENABLE_VGG_CLAMP	[0, 0, 3]
MISC:ICAP_ENCRYPTION	[0, 0, 20]
MISC:VGG_POS_GAIN_SEL	[0, 0, 4]
Non-inverted	[0]

MISC:VGG_NEG_GAIN_SEL	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
MISC:VGG_SEL	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]
Non-inverted	[4]	[3]	[2]	[1]	[0]

BSPI

REG.BSPI bittile 0
Row	Column
	0
0	MISC:SPI_OPCODE[0]
1	MISC:SPI_OPCODE[1]
2	MISC:SPI_OPCODE[2]
3	MISC:SPI_OPCODE[3]
4	MISC:SPI_OPCODE[4]
5	MISC:SPI_OPCODE[5]
6	MISC:SPI_OPCODE[6]
7	MISC:SPI_OPCODE[7]
8	MISC:SPI_BUSWIDTH[0]
9	MISC:SPI_BUSWIDTH[1]
10	-
11	-
12	MISC:BPI_SYNC_MODE[0]
13	MISC:BPI_SYNC_MODE[1]
14	MISC:BPI_SYNC_MODE[2]
15	MISC:BPI_SYNC_MODE[3]
16	MISC:BPI_SYNC_MODE[4]
17	MISC:BPI_SYNC_MODE[5]
18	MISC:BPI_SYNC_MODE[6]
19	MISC:BPI_SYNC_MODE[7]
20	MISC:BPI_SYNC_MODE[8]
21	MISC:BPI_SYNC_MODE[9]
22	MISC:BPI_SYNC_MODE[10]
23	MISC:BPI_SYNC_MODE[11]
24	MISC:BPI_SYNC_MODE[12]
25	MISC:BPI_SYNC_MODE[13]
26	MISC:BPI_SYNC_MODE[14]
27	MISC:BPI_SYNC_MODE[15]

MISC:SPI_OPCODE	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:SPI_BUSWIDTH	[0, 0, 9]	[0, 0, 8]
1	0	0
2	0	1
4	1	0

MISC:BPI_SYNC_MODE	[0, 0, 27]	[0, 0, 26]	[0, 0, 25]	[0, 0, 24]	[0, 0, 23]	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]
NONE	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
TYPE2	1	0	1	0	1	0	0	1	1	1	0	0	1	1	1	1
TYPE1	1	1	0	1	1	0	0	1	1	1	0	0	1	1	1	1

WBSTAR

REG.WBSTAR bittile 0
Row	Column
	0
0	MISC:NEXT_CONFIG_ADDR[0]
1	MISC:NEXT_CONFIG_ADDR[1]
2	MISC:NEXT_CONFIG_ADDR[2]
3	MISC:NEXT_CONFIG_ADDR[3]
4	MISC:NEXT_CONFIG_ADDR[4]
5	MISC:NEXT_CONFIG_ADDR[5]
6	MISC:NEXT_CONFIG_ADDR[6]
7	MISC:NEXT_CONFIG_ADDR[7]
8	MISC:NEXT_CONFIG_ADDR[8]
9	MISC:NEXT_CONFIG_ADDR[9]
10	MISC:NEXT_CONFIG_ADDR[10]
11	MISC:NEXT_CONFIG_ADDR[11]
12	MISC:NEXT_CONFIG_ADDR[12]
13	MISC:NEXT_CONFIG_ADDR[13]
14	MISC:NEXT_CONFIG_ADDR[14]
15	MISC:NEXT_CONFIG_ADDR[15]
16	MISC:NEXT_CONFIG_ADDR[16]
17	MISC:NEXT_CONFIG_ADDR[17]
18	MISC:NEXT_CONFIG_ADDR[18]
19	MISC:NEXT_CONFIG_ADDR[19]
20	MISC:NEXT_CONFIG_ADDR[20]
21	MISC:NEXT_CONFIG_ADDR[21]
22	MISC:NEXT_CONFIG_ADDR[22]
23	MISC:NEXT_CONFIG_ADDR[23]
24	MISC:NEXT_CONFIG_ADDR[24]
25	MISC:NEXT_CONFIG_ADDR[25]
26	MISC:NEXT_CONFIG_ADDR[26]
27	MISC:NEXT_CONFIG_ADDR[27]
28	MISC:NEXT_CONFIG_ADDR[28]
29	MISC:REVISION_SELECT_TRISTATE
30	MISC:REVISION_SELECT[0]
31	MISC:REVISION_SELECT[1]

MISC:NEXT_CONFIG_ADDR	[0, 0, 28]	[0, 0, 27]	[0, 0, 26]	[0, 0, 25]	[0, 0, 24]	[0, 0, 23]	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:REVISION_SELECT_TRISTATE	[0, 0, 29]
Non-inverted	[0]

MISC:REVISION_SELECT	[0, 0, 31]	[0, 0, 30]
Non-inverted	[1]	[0]

TIMER

REG.TIMER bittile 0
Row	Column
	0
0	MISC:TIMER[0]
1	MISC:TIMER[1]
2	MISC:TIMER[2]
3	MISC:TIMER[3]
4	MISC:TIMER[4]
5	MISC:TIMER[5]
6	MISC:TIMER[6]
7	MISC:TIMER[7]
8	MISC:TIMER[8]
9	MISC:TIMER[9]
10	MISC:TIMER[10]
11	MISC:TIMER[11]
12	MISC:TIMER[12]
13	MISC:TIMER[13]
14	MISC:TIMER[14]
15	MISC:TIMER[15]
16	MISC:TIMER[16]
17	MISC:TIMER[17]
18	MISC:TIMER[18]
19	MISC:TIMER[19]
20	MISC:TIMER[20]
21	MISC:TIMER[21]
22	MISC:TIMER[22]
23	MISC:TIMER[23]
24	-
25	-
26	-
27	-
28	-
29	-
30	MISC:TIMER_CFG
31	MISC:TIMER_USR

MISC:TIMER	[0, 0, 23]	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:TIMER_CFG	[0, 0, 30]
MISC:TIMER_USR	[0, 0, 31]
Non-inverted	[0]

TESTMODE

REG.TESTMODE bittile 0
Row	Column
	0
0	-
1	-
2	-
3	-
4	-
5	-
6	-
7	-
8	MISC:TEST_VGG_SEL[0]
9	MISC:TEST_VGG_SEL[1]
10	MISC:TEST_VGG_SEL[2]
11	MISC:TEST_VGG_SEL[3]
12	MISC:TEST_NEG_SLOPE_VGG
13	-
14	-
15	-
16	-
17	-
18	-
19	-
20	-
21	MISC:TEST_VGG_ENABLE
22	-
23	-
24	-
25	-
26	-
27	-
28	MISC:TEST_REF_SEL[0]
29	MISC:TEST_REF_SEL[1]
30	MISC:TEST_REF_SEL[2]

MISC:TEST_VGG_SEL	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]
Non-inverted	[3]	[2]	[1]	[0]

MISC:TEST_NEG_SLOPE_VGG	[0, 0, 12]
MISC:TEST_VGG_ENABLE	[0, 0, 21]
Non-inverted	[0]

MISC:TEST_REF_SEL	[0, 0, 30]	[0, 0, 29]	[0, 0, 28]
Non-inverted	[2]	[1]	[0]

TRIM0

REG.TRIM0 bittile 0
Row	Column
	0
0	MISC:MPD_SEL[0]
1	MISC:MPD_SEL[1]
2	MISC:MPD_SEL[2]
3	MISC:MPD_OVERRIDE
4	MISC:MPD_DIS_OVERRIDE
5	MISC:TRIM_SPARE[0]
6	MISC:TRIM_SPARE[1]

MISC:MPD_SEL	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[2]	[1]	[0]

MISC:MPD_DIS_OVERRIDE	[0, 0, 4]
MISC:MPD_OVERRIDE	[0, 0, 3]
Non-inverted	[0]

MISC:TRIM_SPARE	[0, 0, 6]	[0, 0, 5]
Non-inverted	[1]	[0]

TRIM1

REG.TRIM1 bittile 0
Row	Column
	0
0	-
1	-
2	-
3	-
4	-
5	-
6	-
7	-
8	-
9	-
10	-
11	-
12	-
13	-
14	MISC:VBG_FLAT_SEL[0]
15	MISC:VBG_FLAT_SEL[1]
16	MISC:VBG_FLAT_SEL[2]
17	MISC:VBG_FLAT_SEL[3]
18	MISC:VBG_FLAT_SEL[4]
19	MISC:VBG_FLAT_SEL[5]
20	MISC:VGGSEL[0]
21	MISC:VGGSEL[1]
22	MISC:VGGSEL[2]
23	MISC:VGGSEL[3]
24	MISC:VGGSEL[4]
25	MISC:VGGSEL[5]
26	MISC:VGGSEL2[0]
27	MISC:VGGSEL2[1]
28	MISC:VGGSEL2[2]
29	MISC:VGGSEL2[3]
30	MISC:VGGSEL2[4]
31	MISC:VGGSEL2[5]

MISC:VBG_FLAT_SEL	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]
MISC:VGGSEL	[0, 0, 25]	[0, 0, 24]	[0, 0, 23]	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]
MISC:VGGSEL2	[0, 0, 31]	[0, 0, 30]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]	[0, 0, 26]
Non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

TRIM2

REG.TRIM2 bittile 0
Row	Column
	0
0	MISC:VGG_TRIM_TOP[0]
1	MISC:VGG_TRIM_TOP[1]
2	MISC:VGG_TRIM_TOP[2]
3	MISC:VGG_TRIM_TOP[3]
4	MISC:VGG_TRIM_TOP[4]
5	MISC:VGG_TRIM_TOP[5]
6	MISC:VGG_TRIM_TOP[6]
7	MISC:VGG_TRIM_TOP[7]
8	MISC:VGG_TRIM_TOP[8]
9	MISC:VGG_TRIM_TOP[9]
10	MISC:VGG_TRIM_TOP[10]
11	MISC:VGG_TRIM_TOP[11]
12	MISC:VGG_TRIM_BOT[0]
13	MISC:VGG_TRIM_BOT[1]
14	MISC:VGG_TRIM_BOT[2]
15	MISC:VGG_TRIM_BOT[3]
16	MISC:VGG_TRIM_BOT[4]
17	MISC:VGG_TRIM_BOT[5]
18	MISC:VGG_TRIM_BOT[6]
19	MISC:VGG_TRIM_BOT[7]
20	MISC:VGG_TRIM_BOT[8]
21	MISC:VGG_TRIM_BOT[9]
22	MISC:VGG_TRIM_BOT[10]
23	MISC:VGG_TRIM_BOT[11]

MISC:VGG_TRIM_BOT	[0, 0, 23]	[0, 0, 22]	[0, 0, 21]	[0, 0, 20]	[0, 0, 19]	[0, 0, 18]	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]	[0, 0, 14]	[0, 0, 13]	[0, 0, 12]
MISC:VGG_TRIM_TOP	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
Non-inverted	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]