PCI Express Gen3 cores
Bitstream
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Row | Column | |||||||||||||||||||||||||||||
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE | - |
1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[0] | PCIE3:LL_NP_FC_UPDATE_TIMER[1] |
9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[2] | PCIE3:LL_NP_FC_UPDATE_TIMER[3] |
10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[4] | PCIE3:LL_NP_FC_UPDATE_TIMER[5] |
11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[6] | PCIE3:LL_NP_FC_UPDATE_TIMER[7] |
12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[8] | PCIE3:LL_NP_FC_UPDATE_TIMER[9] |
13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[10] | PCIE3:LL_NP_FC_UPDATE_TIMER[11] |
14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[12] | PCIE3:LL_NP_FC_UPDATE_TIMER[13] |
15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[14] | PCIE3:LL_NP_FC_UPDATE_TIMER[15] |
16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE | - |
17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[0] | PCIE3:LL_FC_UPDATE_TIMER[1] |
25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[2] | PCIE3:LL_FC_UPDATE_TIMER[3] |
26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[4] | PCIE3:LL_FC_UPDATE_TIMER[5] |
27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[6] | PCIE3:LL_FC_UPDATE_TIMER[7] |
28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[8] | PCIE3:LL_FC_UPDATE_TIMER[9] |
29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[10] | PCIE3:LL_FC_UPDATE_TIMER[11] |
30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[12] | PCIE3:LL_FC_UPDATE_TIMER[13] |
31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[14] | PCIE3:LL_FC_UPDATE_TIMER[15] |
32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[0] |
33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[1] | PCIE3:TL_CREDITS_CD[2] |
34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[3] | PCIE3:TL_CREDITS_CD[4] |
35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[5] | PCIE3:TL_CREDITS_CD[6] |
36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[7] | PCIE3:TL_CREDITS_CD[8] |
37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[9] | PCIE3:TL_CREDITS_CD[10] |
38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[11] | - |
39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[0] | PCIE3:TL_CREDITS_CH[1] |
41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[2] | PCIE3:TL_CREDITS_CH[3] |
42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[4] | PCIE3:TL_CREDITS_CH[5] |
43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[6] | PCIE3:TL_CREDITS_CH[7] |
PCIE3 bittile 61 | ||||||||||||||||||||||||||||||
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0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[0] | PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[1] |
15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[0] | PCIE3:PF0_MSI_CAP_NEXTPTR[1] |
17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[2] | PCIE3:PF0_MSI_CAP_NEXTPTR[3] |
18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[4] | PCIE3:PF0_MSI_CAP_NEXTPTR[5] |
19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[6] | PCIE3:PF0_MSI_CAP_NEXTPTR[7] |
20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[0] | PCIE3:PF1_MSI_CAP_NEXTPTR[1] |
21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[2] | PCIE3:PF1_MSI_CAP_NEXTPTR[3] |
22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[4] | PCIE3:PF1_MSI_CAP_NEXTPTR[5] |
23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[6] | PCIE3:PF1_MSI_CAP_NEXTPTR[7] |
24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[0] | PCIE3:PF0_MSIX_CAP_NEXTPTR[1] |
41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[2] | PCIE3:PF0_MSIX_CAP_NEXTPTR[3] |
42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[4] | PCIE3:PF0_MSIX_CAP_NEXTPTR[5] |
43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[6] | PCIE3:PF0_MSIX_CAP_NEXTPTR[7] |
44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[0] | PCIE3:PF1_MSIX_CAP_NEXTPTR[1] |
45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[2] | PCIE3:PF1_MSIX_CAP_NEXTPTR[3] |
46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[4] | PCIE3:PF1_MSIX_CAP_NEXTPTR[5] |
47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[6] | PCIE3:PF1_MSIX_CAP_NEXTPTR[7] |
PCIE3 bittile 74 |
---|
Row | Column |
PCIE3:ARI_CAP_ENABLE | [75, 28, 24] |
---|---|
PCIE3:AXISTEN_IF_CC_ALIGNMENT_MODE | [50, 28, 3] |
PCIE3:AXISTEN_IF_CC_PARITY_CHK | [50, 29, 17] |
PCIE3:AXISTEN_IF_CQ_ALIGNMENT_MODE | [50, 29, 2] |
PCIE3:AXISTEN_IF_ENABLE_CLIENT_TAG | [50, 28, 18] |
PCIE3:AXISTEN_IF_ENABLE_RX_MSG_INTFC | [50, 28, 5] |
PCIE3:AXISTEN_IF_RC_ALIGNMENT_MODE | [50, 28, 4] |
PCIE3:AXISTEN_IF_RC_STRADDLE | [50, 29, 4] |
PCIE3:AXISTEN_IF_RQ_ALIGNMENT_MODE | [50, 29, 3] |
PCIE3:AXISTEN_IF_RQ_PARITY_CHK | [50, 28, 17] |
PCIE3:CRM_CORE_CLK_FREQ_500 | [50, 28, 0] |
PCIE3:GEN3_PCS_RX_ELECIDLE_INTERNAL | [87, 28, 24] |
PCIE3:LL_ACK_TIMEOUT_EN | [54, 28, 6] |
PCIE3:LL_CPL_FC_UPDATE_TIMER_OVERRIDE | [54, 29, 21] |
PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE | [55, 28, 16] |
PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE | [55, 28, 0] |
PCIE3:LL_P_FC_UPDATE_TIMER_OVERRIDE | [54, 28, 32] |
PCIE3:LL_REPLAY_TIMEOUT_EN | [54, 29, 13] |
PCIE3:LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE | [77, 29, 45] |
PCIE3:LTR_TX_MESSAGE_ON_LTR_ENABLE | [77, 28, 45] |
PCIE3:PF0_AER_CAP_ECRC_CHECK_CAPABLE | [75, 28, 22] |
PCIE3:PF0_AER_CAP_ECRC_GEN_CAPABLE | [75, 28, 23] |
Non-inverted | [0] |
PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE | [50, 29, 16] | [50, 28, 16] | [50, 29, 15] | [50, 28, 15] | [50, 29, 14] | [50, 28, 14] | [50, 29, 13] | [50, 28, 13] | [50, 29, 12] | [50, 28, 12] | [50, 29, 11] | [50, 28, 11] | [50, 29, 10] | [50, 28, 10] | [50, 29, 9] | [50, 28, 9] | [50, 29, 8] | [50, 28, 8] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Non-inverted | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:LL_CPL_FC_UPDATE_TIMER | [54, 29, 31] | [54, 28, 31] | [54, 29, 30] | [54, 28, 30] | [54, 29, 29] | [54, 28, 29] | [54, 29, 28] | [54, 28, 28] | [54, 29, 27] | [54, 28, 27] | [54, 29, 26] | [54, 28, 26] | [54, 29, 25] | [54, 28, 25] | [54, 29, 24] | [54, 28, 24] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:LL_FC_UPDATE_TIMER | [55, 29, 31] | [55, 28, 31] | [55, 29, 30] | [55, 28, 30] | [55, 29, 29] | [55, 28, 29] | [55, 29, 28] | [55, 28, 28] | [55, 29, 27] | [55, 28, 27] | [55, 29, 26] | [55, 28, 26] | [55, 29, 25] | [55, 28, 25] | [55, 29, 24] | [55, 28, 24] |
PCIE3:LL_NP_FC_UPDATE_TIMER | [55, 29, 15] | [55, 28, 15] | [55, 29, 14] | [55, 28, 14] | [55, 29, 13] | [55, 28, 13] | [55, 29, 12] | [55, 28, 12] | [55, 29, 11] | [55, 28, 11] | [55, 29, 10] | [55, 28, 10] | [55, 29, 9] | [55, 28, 9] | [55, 29, 8] | [55, 28, 8] |
PCIE3:LL_P_FC_UPDATE_TIMER | [54, 29, 47] | [54, 28, 47] | [54, 29, 46] | [54, 28, 46] | [54, 29, 45] | [54, 28, 45] | [54, 29, 44] | [54, 28, 44] | [54, 29, 43] | [54, 28, 43] | [54, 29, 42] | [54, 28, 42] | [54, 29, 41] | [54, 28, 41] | [54, 29, 40] | [54, 28, 40] |
PCIE3:PF0_DEVICE_ID | [57, 29, 23] | [57, 28, 23] | [57, 29, 22] | [57, 28, 22] | [57, 29, 21] | [57, 28, 21] | [57, 29, 20] | [57, 28, 20] | [57, 29, 19] | [57, 28, 19] | [57, 29, 18] | [57, 28, 18] | [57, 29, 17] | [57, 28, 17] | [57, 29, 16] | [57, 28, 16] |
PCIE3:PF0_SRIOV_CAP_INITIAL_VF | [80, 29, 31] | [80, 28, 31] | [80, 29, 30] | [80, 28, 30] | [80, 29, 29] | [80, 28, 29] | [80, 29, 28] | [80, 28, 28] | [80, 29, 27] | [80, 28, 27] | [80, 29, 26] | [80, 28, 26] | [80, 29, 25] | [80, 28, 25] | [80, 29, 24] | [80, 28, 24] |
PCIE3:PF0_SRIOV_CAP_TOTAL_VF | [80, 29, 47] | [80, 28, 47] | [80, 29, 46] | [80, 28, 46] | [80, 29, 45] | [80, 28, 45] | [80, 29, 44] | [80, 28, 44] | [80, 29, 43] | [80, 28, 43] | [80, 29, 42] | [80, 28, 42] | [80, 29, 41] | [80, 28, 41] | [80, 29, 40] | [80, 28, 40] |
PCIE3:PF0_SRIOV_FIRST_VF_OFFSET | [81, 29, 31] | [81, 28, 31] | [81, 29, 30] | [81, 28, 30] | [81, 29, 29] | [81, 28, 29] | [81, 29, 28] | [81, 28, 28] | [81, 29, 27] | [81, 28, 27] | [81, 29, 26] | [81, 28, 26] | [81, 29, 25] | [81, 28, 25] | [81, 29, 24] | [81, 28, 24] |
PCIE3:PF0_SRIOV_FUNC_DEP_LINK | [81, 29, 15] | [81, 28, 15] | [81, 29, 14] | [81, 28, 14] | [81, 29, 13] | [81, 28, 13] | [81, 29, 12] | [81, 28, 12] | [81, 29, 11] | [81, 28, 11] | [81, 29, 10] | [81, 28, 10] | [81, 29, 9] | [81, 28, 9] | [81, 29, 8] | [81, 28, 8] |
PCIE3:PF0_SRIOV_VF_DEVICE_ID | [81, 29, 47] | [81, 28, 47] | [81, 29, 46] | [81, 28, 46] | [81, 29, 45] | [81, 28, 45] | [81, 29, 44] | [81, 28, 44] | [81, 29, 43] | [81, 28, 43] | [81, 29, 42] | [81, 28, 42] | [81, 29, 41] | [81, 28, 41] | [81, 29, 40] | [81, 28, 40] |
PCIE3:PF0_SUBSYSTEM_ID | [58, 29, 31] | [58, 28, 31] | [58, 29, 30] | [58, 28, 30] | [58, 29, 29] | [58, 28, 29] | [58, 29, 28] | [58, 28, 28] | [58, 29, 27] | [58, 28, 27] | [58, 29, 26] | [58, 28, 26] | [58, 29, 25] | [58, 28, 25] | [58, 29, 24] | [58, 28, 24] |
PCIE3:PF1_DEVICE_ID | [57, 29, 31] | [57, 28, 31] | [57, 29, 30] | [57, 28, 30] | [57, 29, 29] | [57, 28, 29] | [57, 29, 28] | [57, 28, 28] | [57, 29, 27] | [57, 28, 27] | [57, 29, 26] | [57, 28, 26] | [57, 29, 25] | [57, 28, 25] | [57, 29, 24] | [57, 28, 24] |
PCIE3:PF1_SRIOV_CAP_INITIAL_VF | [80, 29, 39] | [80, 28, 39] | [80, 29, 38] | [80, 28, 38] | [80, 29, 37] | [80, 28, 37] | [80, 29, 36] | [80, 28, 36] | [80, 29, 35] | [80, 28, 35] | [80, 29, 34] | [80, 28, 34] | [80, 29, 33] | [80, 28, 33] | [80, 29, 32] | [80, 28, 32] |
PCIE3:PF1_SRIOV_CAP_TOTAL_VF | [81, 29, 7] | [81, 28, 7] | [81, 29, 6] | [81, 28, 6] | [81, 29, 5] | [81, 28, 5] | [81, 29, 4] | [81, 28, 4] | [81, 29, 3] | [81, 28, 3] | [81, 29, 2] | [81, 28, 2] | [81, 29, 1] | [81, 28, 1] | [81, 29, 0] | [81, 28, 0] |
PCIE3:PF1_SRIOV_FIRST_VF_OFFSET | [81, 29, 39] | [81, 28, 39] | [81, 29, 38] | [81, 28, 38] | [81, 29, 37] | [81, 28, 37] | [81, 29, 36] | [81, 28, 36] | [81, 29, 35] | [81, 28, 35] | [81, 29, 34] | [81, 28, 34] | [81, 29, 33] | [81, 28, 33] | [81, 29, 32] | [81, 28, 32] |
PCIE3:PF1_SRIOV_FUNC_DEP_LINK | [81, 29, 23] | [81, 28, 23] | [81, 29, 22] | [81, 28, 22] | [81, 29, 21] | [81, 28, 21] | [81, 29, 20] | [81, 28, 20] | [81, 29, 19] | [81, 28, 19] | [81, 29, 18] | [81, 28, 18] | [81, 29, 17] | [81, 28, 17] | [81, 29, 16] | [81, 28, 16] |
PCIE3:PF1_SRIOV_VF_DEVICE_ID | [82, 29, 7] | [82, 28, 7] | [82, 29, 6] | [82, 28, 6] | [82, 29, 5] | [82, 28, 5] | [82, 29, 4] | [82, 28, 4] | [82, 29, 3] | [82, 28, 3] | [82, 29, 2] | [82, 28, 2] | [82, 29, 1] | [82, 28, 1] | [82, 29, 0] | [82, 28, 0] |
PCIE3:PF1_SUBSYSTEM_ID | [58, 29, 39] | [58, 28, 39] | [58, 29, 38] | [58, 28, 38] | [58, 29, 37] | [58, 28, 37] | [58, 29, 36] | [58, 28, 36] | [58, 29, 35] | [58, 28, 35] | [58, 29, 34] | [58, 28, 34] | [58, 29, 33] | [58, 28, 33] | [58, 29, 32] | [58, 28, 32] |
PCIE3:PL_LANE0_EQ_CONTROL | [52, 29, 39] | [52, 28, 39] | [52, 29, 38] | [52, 28, 38] | [52, 29, 37] | [52, 28, 37] | [52, 29, 36] | [52, 28, 36] | [52, 29, 35] | [52, 28, 35] | [52, 29, 34] | [52, 28, 34] | [52, 29, 33] | [52, 28, 33] | [52, 29, 32] | [52, 28, 32] |
PCIE3:PL_LANE1_EQ_CONTROL | [52, 29, 47] | [52, 28, 47] | [52, 29, 46] | [52, 28, 46] | [52, 29, 45] | [52, 28, 45] | [52, 29, 44] | [52, 28, 44] | [52, 29, 43] | [52, 28, 43] | [52, 29, 42] | [52, 28, 42] | [52, 29, 41] | [52, 28, 41] | [52, 29, 40] | [52, 28, 40] |
PCIE3:PL_LANE2_EQ_CONTROL | [53, 29, 7] | [53, 28, 7] | [53, 29, 6] | [53, 28, 6] | [53, 29, 5] | [53, 28, 5] | [53, 29, 4] | [53, 28, 4] | [53, 29, 3] | [53, 28, 3] | [53, 29, 2] | [53, 28, 2] | [53, 29, 1] | [53, 28, 1] | [53, 29, 0] | [53, 28, 0] |
PCIE3:PL_LANE3_EQ_CONTROL | [53, 29, 15] | [53, 28, 15] | [53, 29, 14] | [53, 28, 14] | [53, 29, 13] | [53, 28, 13] | [53, 29, 12] | [53, 28, 12] | [53, 29, 11] | [53, 28, 11] | [53, 29, 10] | [53, 28, 10] | [53, 29, 9] | [53, 28, 9] | [53, 29, 8] | [53, 28, 8] |
PCIE3:PL_LANE4_EQ_CONTROL | [53, 29, 23] | [53, 28, 23] | [53, 29, 22] | [53, 28, 22] | [53, 29, 21] | [53, 28, 21] | [53, 29, 20] | [53, 28, 20] | [53, 29, 19] | [53, 28, 19] | [53, 29, 18] | [53, 28, 18] | [53, 29, 17] | [53, 28, 17] | [53, 29, 16] | [53, 28, 16] |
PCIE3:PL_LANE5_EQ_CONTROL | [53, 29, 31] | [53, 28, 31] | [53, 29, 30] | [53, 28, 30] | [53, 29, 29] | [53, 28, 29] | [53, 29, 28] | [53, 28, 28] | [53, 29, 27] | [53, 28, 27] | [53, 29, 26] | [53, 28, 26] | [53, 29, 25] | [53, 28, 25] | [53, 29, 24] | [53, 28, 24] |
PCIE3:PL_LANE6_EQ_CONTROL | [53, 29, 39] | [53, 28, 39] | [53, 29, 38] | [53, 28, 38] | [53, 29, 37] | [53, 28, 37] | [53, 29, 36] | [53, 28, 36] | [53, 29, 35] | [53, 28, 35] | [53, 29, 34] | [53, 28, 34] | [53, 29, 33] | [53, 28, 33] | [53, 29, 32] | [53, 28, 32] |
PCIE3:PL_LANE7_EQ_CONTROL | [53, 29, 47] | [53, 28, 47] | [53, 29, 46] | [53, 28, 46] | [53, 29, 45] | [53, 28, 45] | [53, 29, 44] | [53, 28, 44] | [53, 29, 43] | [53, 28, 43] | [53, 29, 42] | [53, 28, 42] | [53, 29, 41] | [53, 28, 41] | [53, 29, 40] | [53, 28, 40] |
PCIE3:PM_ASPML0S_TIMEOUT | [50, 29, 31] | [50, 28, 31] | [50, 29, 30] | [50, 28, 30] | [50, 29, 29] | [50, 28, 29] | [50, 29, 28] | [50, 28, 28] | [50, 29, 27] | [50, 28, 27] | [50, 29, 26] | [50, 28, 26] | [50, 29, 25] | [50, 28, 25] | [50, 29, 24] | [50, 28, 24] |
PCIE3:PM_PME_TURNOFF_ACK_DELAY | [51, 29, 39] | [51, 28, 39] | [51, 29, 38] | [51, 28, 38] | [51, 29, 37] | [51, 28, 37] | [51, 29, 36] | [51, 28, 36] | [51, 29, 35] | [51, 28, 35] | [51, 29, 34] | [51, 28, 34] | [51, 29, 33] | [51, 28, 33] | [51, 29, 32] | [51, 28, 32] |
Non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE | [82, 29, 23] | [82, 28, 23] | [82, 29, 22] | [82, 28, 22] | [82, 29, 21] | [82, 28, 21] | [82, 29, 20] | [82, 28, 20] | [82, 29, 19] | [82, 28, 19] | [82, 29, 18] | [82, 28, 18] | [82, 29, 17] | [82, 28, 17] | [82, 29, 16] | [82, 28, 16] | [82, 29, 15] | [82, 28, 15] | [82, 29, 14] | [82, 28, 14] | [82, 29, 13] | [82, 28, 13] | [82, 29, 12] | [82, 28, 12] | [82, 29, 11] | [82, 28, 11] | [82, 29, 10] | [82, 28, 10] | [82, 29, 9] | [82, 28, 9] | [82, 29, 8] | [82, 28, 8] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE | [82, 29, 39] | [82, 28, 39] | [82, 29, 38] | [82, 28, 38] | [82, 29, 37] | [82, 28, 37] | [82, 29, 36] | [82, 28, 36] | [82, 29, 35] | [82, 28, 35] | [82, 29, 34] | [82, 28, 34] | [82, 29, 33] | [82, 28, 33] | [82, 29, 32] | [82, 28, 32] | [82, 29, 31] | [82, 28, 31] | [82, 29, 30] | [82, 28, 30] | [82, 29, 29] | [82, 28, 29] | [82, 29, 28] | [82, 28, 28] | [82, 29, 27] | [82, 28, 27] | [82, 29, 26] | [82, 28, 26] | [82, 29, 25] | [82, 28, 25] | [82, 29, 24] | [82, 28, 24] |
PCIE3:PM_L1_REENTRY_DELAY | [50, 29, 47] | [50, 28, 47] | [50, 29, 46] | [50, 28, 46] | [50, 29, 45] | [50, 28, 45] | [50, 29, 44] | [50, 28, 44] | [50, 29, 43] | [50, 28, 43] | [50, 29, 42] | [50, 28, 42] | [50, 29, 41] | [50, 28, 41] | [50, 29, 40] | [50, 28, 40] | [50, 29, 39] | [50, 28, 39] | [50, 29, 38] | [50, 28, 38] | [50, 29, 37] | [50, 28, 37] | [50, 29, 36] | [50, 28, 36] | [50, 29, 35] | [50, 28, 35] | [50, 29, 34] | [50, 28, 34] | [50, 29, 33] | [50, 28, 33] | [50, 29, 32] | [50, 28, 32] |
PCIE3:SPARE_WORD0 | [88, 29, 15] | [88, 28, 15] | [88, 29, 14] | [88, 28, 14] | [88, 29, 13] | [88, 28, 13] | [88, 29, 12] | [88, 28, 12] | [88, 29, 11] | [88, 28, 11] | [88, 29, 10] | [88, 28, 10] | [88, 29, 9] | [88, 28, 9] | [88, 29, 8] | [88, 28, 8] | [88, 29, 7] | [88, 28, 7] | [88, 29, 6] | [88, 28, 6] | [88, 29, 5] | [88, 28, 5] | [88, 29, 4] | [88, 28, 4] | [88, 29, 3] | [88, 28, 3] | [88, 29, 2] | [88, 28, 2] | [88, 29, 1] | [88, 28, 1] | [88, 29, 0] | [88, 28, 0] |
PCIE3:SPARE_WORD1 | [88, 29, 31] | [88, 28, 31] | [88, 29, 30] | [88, 28, 30] | [88, 29, 29] | [88, 28, 29] | [88, 29, 28] | [88, 28, 28] | [88, 29, 27] | [88, 28, 27] | [88, 29, 26] | [88, 28, 26] | [88, 29, 25] | [88, 28, 25] | [88, 29, 24] | [88, 28, 24] | [88, 29, 23] | [88, 28, 23] | [88, 29, 22] | [88, 28, 22] | [88, 29, 21] | [88, 28, 21] | [88, 29, 20] | [88, 28, 20] | [88, 29, 19] | [88, 28, 19] | [88, 29, 18] | [88, 28, 18] | [88, 29, 17] | [88, 28, 17] | [88, 29, 16] | [88, 28, 16] |
PCIE3:SPARE_WORD2 | [88, 29, 47] | [88, 28, 47] | [88, 29, 46] | [88, 28, 46] | [88, 29, 45] | [88, 28, 45] | [88, 29, 44] | [88, 28, 44] | [88, 29, 43] | [88, 28, 43] | [88, 29, 42] | [88, 28, 42] | [88, 29, 41] | [88, 28, 41] | [88, 29, 40] | [88, 28, 40] | [88, 29, 39] | [88, 28, 39] | [88, 29, 38] | [88, 28, 38] | [88, 29, 37] | [88, 28, 37] | [88, 29, 36] | [88, 28, 36] | [88, 29, 35] | [88, 28, 35] | [88, 29, 34] | [88, 28, 34] | [88, 29, 33] | [88, 28, 33] | [88, 29, 32] | [88, 28, 32] |
PCIE3:SPARE_WORD3 | [89, 29, 15] | [89, 28, 15] | [89, 29, 14] | [89, 28, 14] | [89, 29, 13] | [89, 28, 13] | [89, 29, 12] | [89, 28, 12] | [89, 29, 11] | [89, 28, 11] | [89, 29, 10] | [89, 28, 10] | [89, 29, 9] | [89, 28, 9] | [89, 29, 8] | [89, 28, 8] | [89, 29, 7] | [89, 28, 7] | [89, 29, 6] | [89, 28, 6] | [89, 29, 5] | [89, 28, 5] | [89, 29, 4] | [89, 28, 4] | [89, 29, 3] | [89, 28, 3] | [89, 29, 2] | [89, 28, 2] | [89, 29, 1] | [89, 28, 1] | [89, 29, 0] | [89, 28, 0] |
Non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:AXISTEN_IF_WIDTH | [50, 28, 2] | [50, 29, 1] |
---|---|---|
PCIE3:CRM_USER_CLK_FREQ | [50, 28, 1] | [50, 29, 0] |
PCIE3:GEN3_PCS_AUTO_REALIGN | [87, 29, 23] | [87, 28, 23] |
PCIE3:LL_ACK_TIMEOUT_FUNC | [54, 28, 13] | [54, 29, 12] |
PCIE3:LL_REPLAY_TIMEOUT_FUNC | [54, 28, 21] | [54, 29, 20] |
PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT | [61, 29, 14] | [61, 28, 14] |
PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC | [85, 29, 30] | [85, 28, 30] |
PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC | [85, 29, 31] | [85, 28, 31] |
PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT | [54, 29, 3] | [54, 28, 3] |
PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC | [85, 29, 32] | [85, 28, 32] |
PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC | [85, 29, 33] | [85, 28, 33] |
PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC | [85, 29, 34] | [85, 28, 34] |
PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC | [85, 29, 35] | [85, 28, 35] |
PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC | [85, 29, 36] | [85, 28, 36] |
PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC | [85, 29, 37] | [85, 28, 37] |
Non-inverted | [1] | [0] |
PCIE3:PF0_RBAR_CAP_SIZE0 | [71, 29, 41] | [71, 28, 41] | [71, 29, 40] | [71, 28, 40] | [71, 29, 39] | [71, 28, 39] | [71, 29, 38] | [71, 28, 38] | [71, 29, 37] | [71, 28, 37] | [71, 29, 36] | [71, 28, 36] | [71, 29, 35] | [71, 28, 35] | [71, 29, 34] | [71, 28, 34] | [71, 29, 33] | [71, 28, 33] | [71, 29, 32] | [71, 28, 32] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF0_RBAR_CAP_SIZE1 | [72, 29, 25] | [72, 28, 25] | [72, 29, 24] | [72, 28, 24] | [72, 29, 23] | [72, 28, 23] | [72, 29, 22] | [72, 28, 22] | [72, 29, 21] | [72, 28, 21] | [72, 29, 20] | [72, 28, 20] | [72, 29, 19] | [72, 28, 19] | [72, 29, 18] | [72, 28, 18] | [72, 29, 17] | [72, 28, 17] | [72, 29, 16] | [72, 28, 16] |
PCIE3:PF0_RBAR_CAP_SIZE2 | [73, 29, 9] | [73, 28, 9] | [73, 29, 8] | [73, 28, 8] | [73, 29, 7] | [73, 28, 7] | [73, 29, 6] | [73, 28, 6] | [73, 29, 5] | [73, 28, 5] | [73, 29, 4] | [73, 28, 4] | [73, 29, 3] | [73, 28, 3] | [73, 29, 2] | [73, 28, 2] | [73, 29, 1] | [73, 28, 1] | [73, 29, 0] | [73, 28, 0] |
PCIE3:PF1_RBAR_CAP_SIZE0 | [72, 29, 9] | [72, 28, 9] | [72, 29, 8] | [72, 28, 8] | [72, 29, 7] | [72, 28, 7] | [72, 29, 6] | [72, 28, 6] | [72, 29, 5] | [72, 28, 5] | [72, 29, 4] | [72, 28, 4] | [72, 29, 3] | [72, 28, 3] | [72, 29, 2] | [72, 28, 2] | [72, 29, 1] | [72, 28, 1] | [72, 29, 0] | [72, 28, 0] |
PCIE3:PF1_RBAR_CAP_SIZE1 | [72, 29, 41] | [72, 28, 41] | [72, 29, 40] | [72, 28, 40] | [72, 29, 39] | [72, 28, 39] | [72, 29, 38] | [72, 28, 38] | [72, 29, 37] | [72, 28, 37] | [72, 29, 36] | [72, 28, 36] | [72, 29, 35] | [72, 28, 35] | [72, 29, 34] | [72, 28, 34] | [72, 29, 33] | [72, 28, 33] | [72, 29, 32] | [72, 28, 32] |
PCIE3:PF1_RBAR_CAP_SIZE2 | [73, 29, 25] | [73, 28, 25] | [73, 29, 24] | [73, 28, 24] | [73, 29, 23] | [73, 28, 23] | [73, 29, 22] | [73, 28, 22] | [73, 29, 21] | [73, 28, 21] | [73, 29, 20] | [73, 28, 20] | [73, 29, 19] | [73, 28, 19] | [73, 29, 18] | [73, 28, 18] | [73, 29, 17] | [73, 28, 17] | [73, 29, 16] | [73, 28, 16] |
PCIE3:PM_ASPML1_ENTRY_DELAY | [51, 29, 9] | [51, 28, 9] | [51, 29, 8] | [51, 28, 8] | [51, 29, 7] | [51, 28, 7] | [51, 29, 6] | [51, 28, 6] | [51, 29, 5] | [51, 28, 5] | [51, 29, 4] | [51, 28, 4] | [51, 29, 3] | [51, 28, 3] | [51, 29, 2] | [51, 28, 2] | [51, 29, 1] | [51, 28, 1] | [51, 29, 0] | [51, 28, 0] |
PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY | [51, 29, 25] | [51, 28, 25] | [51, 29, 24] | [51, 28, 24] | [51, 29, 23] | [51, 28, 23] | [51, 29, 22] | [51, 28, 22] | [51, 29, 21] | [51, 28, 21] | [51, 29, 20] | [51, 28, 20] | [51, 29, 19] | [51, 28, 19] | [51, 29, 18] | [51, 28, 18] | [51, 29, 17] | [51, 28, 17] | [51, 29, 16] | [51, 28, 16] |
Non-inverted | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_ARI_CAP_VER | [76, 29, 39] | [76, 28, 39] | [76, 29, 38] | [76, 28, 38] |
---|---|---|---|---|
PCIE3:PF0_DPA_CAP_VER | [78, 29, 23] | [78, 28, 23] | [78, 29, 22] | [78, 28, 22] |
PCIE3:PF0_LTR_CAP_VER | [77, 29, 31] | [77, 28, 31] | [77, 29, 30] | [77, 28, 30] |
PCIE3:PF0_PB_CAP_VER | [77, 29, 15] | [77, 28, 15] | [77, 29, 14] | [77, 28, 14] |
PCIE3:PF0_RBAR_CAP_VER | [71, 29, 1] | [71, 28, 1] | [71, 29, 0] | [71, 28, 0] |
PCIE3:PF0_SRIOV_CAP_VER | [80, 29, 15] | [80, 28, 15] | [80, 29, 14] | [80, 28, 14] |
PCIE3:PF0_TPHR_CAP_VER | [85, 29, 7] | [85, 28, 7] | [85, 29, 6] | [85, 28, 6] |
PCIE3:PF0_VC_CAP_VER | [73, 29, 47] | [73, 28, 47] | [73, 29, 46] | [73, 28, 46] |
PCIE3:PF1_DPA_CAP_VER | [78, 29, 25] | [78, 28, 25] | [78, 29, 24] | [78, 28, 24] |
PCIE3:PF1_PB_CAP_VER | [77, 29, 17] | [77, 28, 17] | [77, 29, 16] | [77, 28, 16] |
PCIE3:PF1_RBAR_CAP_VER | [71, 29, 3] | [71, 28, 3] | [71, 29, 2] | [71, 28, 2] |
PCIE3:PF1_SRIOV_CAP_VER | [80, 29, 17] | [80, 28, 17] | [80, 29, 16] | [80, 28, 16] |
PCIE3:PF1_TPHR_CAP_VER | [85, 29, 9] | [85, 28, 9] | [85, 29, 8] | [85, 28, 8] |
PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH | [51, 28, 42] | [51, 29, 41] | [51, 28, 41] | [51, 29, 40] |
PCIE3:VF0_TPHR_CAP_VER | [85, 29, 11] | [85, 28, 11] | [85, 29, 10] | [85, 28, 10] |
PCIE3:VF1_TPHR_CAP_VER | [85, 29, 13] | [85, 28, 13] | [85, 29, 12] | [85, 28, 12] |
PCIE3:VF2_TPHR_CAP_VER | [85, 29, 15] | [85, 28, 15] | [85, 29, 14] | [85, 28, 14] |
PCIE3:VF3_TPHR_CAP_VER | [85, 29, 17] | [85, 28, 17] | [85, 29, 16] | [85, 28, 16] |
PCIE3:VF4_TPHR_CAP_VER | [85, 29, 19] | [85, 28, 19] | [85, 29, 18] | [85, 28, 18] |
PCIE3:VF5_TPHR_CAP_VER | [85, 29, 21] | [85, 28, 21] | [85, 29, 20] | [85, 28, 20] |
Non-inverted | [3] | [2] | [1] | [0] |
PCIE3:PF0_BAR0_CONTROL | [59, 28, 25] | [59, 29, 24] | [59, 28, 24] |
---|---|---|---|
PCIE3:PF0_BAR1_CONTROL | [59, 28, 33] | [59, 29, 32] | [59, 28, 32] |
PCIE3:PF0_BAR2_CONTROL | [59, 28, 41] | [59, 29, 40] | [59, 28, 40] |
PCIE3:PF0_BAR3_CONTROL | [60, 28, 1] | [60, 29, 0] | [60, 28, 0] |
PCIE3:PF0_BAR4_CONTROL | [60, 28, 9] | [60, 29, 8] | [60, 28, 8] |
PCIE3:PF0_BAR5_CONTROL | [60, 28, 17] | [60, 29, 16] | [60, 28, 16] |
PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY | [60, 28, 35] | [60, 29, 34] | [60, 28, 34] |
PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY | [60, 29, 36] | [60, 28, 36] | [60, 29, 35] |
PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE | [60, 28, 31] | [60, 29, 30] | [60, 28, 30] |
PCIE3:PF0_INTERRUPT_PIN | [58, 28, 41] | [58, 29, 40] | [58, 28, 40] |
PCIE3:PF0_PM_CAP_VER_ID | [70, 28, 35] | [70, 29, 34] | [70, 28, 34] |
PCIE3:PF0_RBAR_CAP_INDEX0 | [71, 29, 26] | [71, 28, 26] | [71, 29, 25] |
PCIE3:PF0_RBAR_CAP_INDEX1 | [72, 28, 11] | [72, 29, 10] | [72, 28, 10] |
PCIE3:PF0_RBAR_CAP_INDEX2 | [72, 28, 43] | [72, 29, 42] | [72, 28, 42] |
PCIE3:PF0_RBAR_NUM | [71, 28, 23] | [71, 29, 22] | [71, 28, 22] |
PCIE3:PF0_SRIOV_BAR0_CONTROL | [82, 28, 41] | [82, 29, 40] | [82, 28, 40] |
PCIE3:PF0_SRIOV_BAR1_CONTROL | [83, 28, 1] | [83, 29, 0] | [83, 28, 0] |
PCIE3:PF0_SRIOV_BAR2_CONTROL | [83, 28, 9] | [83, 29, 8] | [83, 28, 8] |
PCIE3:PF0_SRIOV_BAR3_CONTROL | [83, 28, 17] | [83, 29, 16] | [83, 28, 16] |
PCIE3:PF0_SRIOV_BAR4_CONTROL | [83, 28, 25] | [83, 29, 24] | [83, 28, 24] |
PCIE3:PF0_SRIOV_BAR5_CONTROL | [83, 28, 33] | [83, 29, 32] | [83, 28, 32] |
PCIE3:PF0_TPHR_CAP_ST_MODE_SEL | [87, 29, 6] | [87, 28, 6] | [87, 29, 5] |
PCIE3:PF1_BAR0_CONTROL | [59, 29, 26] | [59, 28, 26] | [59, 29, 25] |
PCIE3:PF1_BAR1_CONTROL | [59, 29, 34] | [59, 28, 34] | [59, 29, 33] |
PCIE3:PF1_BAR2_CONTROL | [59, 29, 42] | [59, 28, 42] | [59, 29, 41] |
PCIE3:PF1_BAR3_CONTROL | [60, 29, 2] | [60, 28, 2] | [60, 29, 1] |
PCIE3:PF1_BAR4_CONTROL | [60, 29, 10] | [60, 28, 10] | [60, 29, 9] |
PCIE3:PF1_BAR5_CONTROL | [60, 29, 18] | [60, 28, 18] | [60, 29, 17] |
PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE | [60, 28, 33] | [60, 29, 32] | [60, 28, 32] |
PCIE3:PF1_INTERRUPT_PIN | [58, 29, 42] | [58, 28, 42] | [58, 29, 41] |
PCIE3:PF1_PM_CAP_VER_ID | [70, 29, 36] | [70, 28, 36] | [70, 29, 35] |
PCIE3:PF1_RBAR_CAP_INDEX0 | [71, 28, 28] | [71, 29, 27] | [71, 28, 27] |
PCIE3:PF1_RBAR_CAP_INDEX1 | [72, 29, 12] | [72, 28, 12] | [72, 29, 11] |
PCIE3:PF1_RBAR_CAP_INDEX2 | [72, 29, 44] | [72, 28, 44] | [72, 29, 43] |
PCIE3:PF1_RBAR_NUM | [71, 28, 25] | [71, 29, 24] | [71, 28, 24] |
PCIE3:PF1_SRIOV_BAR0_CONTROL | [82, 29, 42] | [82, 28, 42] | [82, 29, 41] |
PCIE3:PF1_SRIOV_BAR1_CONTROL | [83, 29, 2] | [83, 28, 2] | [83, 29, 1] |
PCIE3:PF1_SRIOV_BAR2_CONTROL | [83, 29, 10] | [83, 28, 10] | [83, 29, 9] |
PCIE3:PF1_SRIOV_BAR3_CONTROL | [83, 29, 18] | [83, 28, 18] | [83, 29, 17] |
PCIE3:PF1_SRIOV_BAR4_CONTROL | [83, 29, 26] | [83, 28, 26] | [83, 29, 25] |
PCIE3:PF1_SRIOV_BAR5_CONTROL | [83, 29, 34] | [83, 28, 34] | [83, 29, 33] |
PCIE3:PF1_TPHR_CAP_ST_MODE_SEL | [87, 28, 9] | [87, 29, 8] | [87, 28, 8] |
PCIE3:PL_LINK_CAP_MAX_LINK_SPEED | [51, 29, 43] | [51, 28, 43] | [51, 29, 42] |
PCIE3:VF0_PM_CAP_VER_ID | [70, 28, 38] | [70, 29, 37] | [70, 28, 37] |
PCIE3:VF0_TPHR_CAP_ST_MODE_SEL | [87, 29, 10] | [87, 28, 10] | [87, 29, 9] |
PCIE3:VF1_PM_CAP_VER_ID | [70, 29, 39] | [70, 28, 39] | [70, 29, 38] |
PCIE3:VF1_TPHR_CAP_ST_MODE_SEL | [87, 28, 12] | [87, 29, 11] | [87, 28, 11] |
PCIE3:VF2_PM_CAP_VER_ID | [70, 28, 41] | [70, 29, 40] | [70, 28, 40] |
PCIE3:VF2_TPHR_CAP_ST_MODE_SEL | [87, 29, 13] | [87, 28, 13] | [87, 29, 12] |
PCIE3:VF3_PM_CAP_VER_ID | [70, 29, 42] | [70, 28, 42] | [70, 29, 41] |
PCIE3:VF3_TPHR_CAP_ST_MODE_SEL | [87, 28, 15] | [87, 29, 14] | [87, 28, 14] |
PCIE3:VF4_PM_CAP_VER_ID | [70, 28, 44] | [70, 29, 43] | [70, 28, 43] |
PCIE3:VF4_TPHR_CAP_ST_MODE_SEL | [87, 28, 17] | [87, 29, 16] | [87, 28, 16] |
PCIE3:VF5_PM_CAP_VER_ID | [70, 29, 45] | [70, 28, 45] | [70, 29, 44] |
PCIE3:VF5_TPHR_CAP_ST_MODE_SEL | [87, 29, 18] | [87, 28, 18] | [87, 29, 17] |
Non-inverted | [2] | [1] | [0] |
PCIE3:DNSTREAM_LINK_NUM | [73, 29, 29] | [73, 28, 29] | [73, 29, 28] | [73, 28, 28] | [73, 29, 27] | [73, 28, 27] | [73, 29, 26] | [73, 28, 26] |
---|---|---|---|---|---|---|---|---|
PCIE3:PF0_ARI_CAP_NEXT_FUNC | [76, 29, 43] | [76, 28, 43] | [76, 29, 42] | [76, 28, 42] | [76, 29, 41] | [76, 28, 41] | [76, 29, 40] | [76, 28, 40] |
PCIE3:PF0_BIST_REGISTER | [59, 29, 7] | [59, 28, 7] | [59, 29, 6] | [59, 28, 6] | [59, 29, 5] | [59, 28, 5] | [59, 29, 4] | [59, 28, 4] |
PCIE3:PF0_CAPABILITY_POINTER | [59, 29, 15] | [59, 28, 15] | [59, 29, 14] | [59, 28, 14] | [59, 29, 13] | [59, 28, 13] | [59, 29, 12] | [59, 28, 12] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 | [78, 29, 35] | [78, 28, 35] | [78, 29, 34] | [78, 28, 34] | [78, 29, 33] | [78, 28, 33] | [78, 29, 32] | [78, 28, 32] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 | [78, 29, 43] | [78, 28, 43] | [78, 29, 42] | [78, 28, 42] | [78, 29, 41] | [78, 28, 41] | [78, 29, 40] | [78, 28, 40] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 | [79, 29, 3] | [79, 28, 3] | [79, 29, 2] | [79, 28, 2] | [79, 29, 1] | [79, 28, 1] | [79, 29, 0] | [79, 28, 0] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 | [79, 29, 11] | [79, 28, 11] | [79, 29, 10] | [79, 28, 10] | [79, 29, 9] | [79, 28, 9] | [79, 29, 8] | [79, 28, 8] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 | [79, 29, 19] | [79, 28, 19] | [79, 29, 18] | [79, 28, 18] | [79, 29, 17] | [79, 28, 17] | [79, 29, 16] | [79, 28, 16] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 | [79, 29, 27] | [79, 28, 27] | [79, 29, 26] | [79, 28, 26] | [79, 29, 25] | [79, 28, 25] | [79, 29, 24] | [79, 28, 24] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 | [79, 29, 35] | [79, 28, 35] | [79, 29, 34] | [79, 28, 34] | [79, 29, 33] | [79, 28, 33] | [79, 29, 32] | [79, 28, 32] |
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 | [79, 29, 43] | [79, 28, 43] | [79, 29, 42] | [79, 28, 42] | [79, 29, 41] | [79, 28, 41] | [79, 29, 40] | [79, 28, 40] |
PCIE3:PF0_INTERRUPT_LINE | [58, 29, 46] | [58, 28, 46] | [58, 29, 45] | [58, 28, 45] | [58, 29, 44] | [58, 28, 44] | [58, 29, 43] | [58, 28, 43] |
PCIE3:PF0_MSIX_CAP_NEXTPTR | [61, 29, 43] | [61, 28, 43] | [61, 29, 42] | [61, 28, 42] | [61, 29, 41] | [61, 28, 41] | [61, 29, 40] | [61, 28, 40] |
PCIE3:PF0_MSI_CAP_NEXTPTR | [61, 29, 19] | [61, 28, 19] | [61, 29, 18] | [61, 28, 18] | [61, 29, 17] | [61, 28, 17] | [61, 29, 16] | [61, 28, 16] |
PCIE3:PF0_PM_CAP_ID | [69, 29, 19] | [69, 28, 19] | [69, 29, 18] | [69, 28, 18] | [69, 29, 17] | [69, 28, 17] | [69, 29, 16] | [69, 28, 16] |
PCIE3:PF0_PM_CAP_NEXTPTR | [70, 29, 3] | [70, 28, 3] | [70, 29, 2] | [70, 28, 2] | [70, 29, 1] | [70, 28, 1] | [70, 29, 0] | [70, 28, 0] |
PCIE3:PF0_REVISION_ID | [57, 29, 35] | [57, 28, 35] | [57, 29, 34] | [57, 28, 34] | [57, 29, 33] | [57, 28, 33] | [57, 29, 32] | [57, 28, 32] |
PCIE3:PF1_ARI_CAP_NEXT_FUNC | [76, 29, 47] | [76, 28, 47] | [76, 29, 46] | [76, 28, 46] | [76, 29, 45] | [76, 28, 45] | [76, 29, 44] | [76, 28, 44] |
PCIE3:PF1_BIST_REGISTER | [59, 29, 11] | [59, 28, 11] | [59, 29, 10] | [59, 28, 10] | [59, 29, 9] | [59, 28, 9] | [59, 29, 8] | [59, 28, 8] |
PCIE3:PF1_CAPABILITY_POINTER | [59, 29, 19] | [59, 28, 19] | [59, 29, 18] | [59, 28, 18] | [59, 29, 17] | [59, 28, 17] | [59, 29, 16] | [59, 28, 16] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 | [78, 29, 39] | [78, 28, 39] | [78, 29, 38] | [78, 28, 38] | [78, 29, 37] | [78, 28, 37] | [78, 29, 36] | [78, 28, 36] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 | [78, 29, 47] | [78, 28, 47] | [78, 29, 46] | [78, 28, 46] | [78, 29, 45] | [78, 28, 45] | [78, 29, 44] | [78, 28, 44] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 | [79, 29, 7] | [79, 28, 7] | [79, 29, 6] | [79, 28, 6] | [79, 29, 5] | [79, 28, 5] | [79, 29, 4] | [79, 28, 4] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 | [79, 29, 15] | [79, 28, 15] | [79, 29, 14] | [79, 28, 14] | [79, 29, 13] | [79, 28, 13] | [79, 29, 12] | [79, 28, 12] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 | [79, 29, 23] | [79, 28, 23] | [79, 29, 22] | [79, 28, 22] | [79, 29, 21] | [79, 28, 21] | [79, 29, 20] | [79, 28, 20] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 | [79, 29, 31] | [79, 28, 31] | [79, 29, 30] | [79, 28, 30] | [79, 29, 29] | [79, 28, 29] | [79, 29, 28] | [79, 28, 28] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 | [79, 29, 39] | [79, 28, 39] | [79, 29, 38] | [79, 28, 38] | [79, 29, 37] | [79, 28, 37] | [79, 29, 36] | [79, 28, 36] |
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 | [79, 29, 47] | [79, 28, 47] | [79, 29, 46] | [79, 28, 46] | [79, 29, 45] | [79, 28, 45] | [79, 29, 44] | [79, 28, 44] |
PCIE3:PF1_INTERRUPT_LINE | [59, 29, 3] | [59, 28, 3] | [59, 29, 2] | [59, 28, 2] | [59, 29, 1] | [59, 28, 1] | [59, 29, 0] | [59, 28, 0] |
PCIE3:PF1_MSIX_CAP_NEXTPTR | [61, 29, 47] | [61, 28, 47] | [61, 29, 46] | [61, 28, 46] | [61, 29, 45] | [61, 28, 45] | [61, 29, 44] | [61, 28, 44] |
PCIE3:PF1_MSI_CAP_NEXTPTR | [61, 29, 23] | [61, 28, 23] | [61, 29, 22] | [61, 28, 22] | [61, 29, 21] | [61, 28, 21] | [61, 29, 20] | [61, 28, 20] |
PCIE3:PF1_PM_CAP_ID | [69, 29, 23] | [69, 28, 23] | [69, 29, 22] | [69, 28, 22] | [69, 29, 21] | [69, 28, 21] | [69, 29, 20] | [69, 28, 20] |
PCIE3:PF1_PM_CAP_NEXTPTR | [70, 29, 7] | [70, 28, 7] | [70, 29, 6] | [70, 28, 6] | [70, 29, 5] | [70, 28, 5] | [70, 29, 4] | [70, 28, 4] |
PCIE3:PF1_REVISION_ID | [57, 29, 39] | [57, 28, 39] | [57, 29, 38] | [57, 28, 38] | [57, 29, 37] | [57, 28, 37] | [57, 29, 36] | [57, 28, 36] |
PCIE3:PL_N_FTS_COMCLK_GEN1 | [52, 29, 3] | [52, 28, 3] | [52, 29, 2] | [52, 28, 2] | [52, 29, 1] | [52, 28, 1] | [52, 29, 0] | [52, 28, 0] |
PCIE3:PL_N_FTS_COMCLK_GEN2 | [52, 29, 11] | [52, 28, 11] | [52, 29, 10] | [52, 28, 10] | [52, 29, 9] | [52, 28, 9] | [52, 29, 8] | [52, 28, 8] |
PCIE3:PL_N_FTS_COMCLK_GEN3 | [52, 29, 19] | [52, 28, 19] | [52, 29, 18] | [52, 28, 18] | [52, 29, 17] | [52, 28, 17] | [52, 29, 16] | [52, 28, 16] |
PCIE3:PL_N_FTS_GEN1 | [52, 29, 7] | [52, 28, 7] | [52, 29, 6] | [52, 28, 6] | [52, 29, 5] | [52, 28, 5] | [52, 29, 4] | [52, 28, 4] |
PCIE3:PL_N_FTS_GEN2 | [52, 29, 15] | [52, 28, 15] | [52, 29, 14] | [52, 28, 14] | [52, 29, 13] | [52, 28, 13] | [52, 29, 12] | [52, 28, 12] |
PCIE3:PL_N_FTS_GEN3 | [52, 29, 23] | [52, 28, 23] | [52, 29, 22] | [52, 28, 22] | [52, 29, 21] | [52, 28, 21] | [52, 29, 20] | [52, 28, 20] |
PCIE3:SPARE_BYTE0 | [87, 29, 35] | [87, 28, 35] | [87, 29, 34] | [87, 28, 34] | [87, 29, 33] | [87, 28, 33] | [87, 29, 32] | [87, 28, 32] |
PCIE3:SPARE_BYTE1 | [87, 29, 39] | [87, 28, 39] | [87, 29, 38] | [87, 28, 38] | [87, 29, 37] | [87, 28, 37] | [87, 29, 36] | [87, 28, 36] |
PCIE3:SPARE_BYTE2 | [87, 29, 43] | [87, 28, 43] | [87, 29, 42] | [87, 28, 42] | [87, 29, 41] | [87, 28, 41] | [87, 29, 40] | [87, 28, 40] |
PCIE3:SPARE_BYTE3 | [87, 29, 47] | [87, 28, 47] | [87, 29, 46] | [87, 28, 46] | [87, 29, 45] | [87, 28, 45] | [87, 29, 44] | [87, 28, 44] |
PCIE3:TL_CREDITS_CH | [55, 29, 43] | [55, 28, 43] | [55, 29, 42] | [55, 28, 42] | [55, 29, 41] | [55, 28, 41] | [55, 29, 40] | [55, 28, 40] |
PCIE3:TL_CREDITS_NPH | [56, 29, 11] | [56, 28, 11] | [56, 29, 10] | [56, 28, 10] | [56, 29, 9] | [56, 28, 9] | [56, 29, 8] | [56, 28, 8] |
PCIE3:TL_CREDITS_PH | [56, 29, 27] | [56, 28, 27] | [56, 29, 26] | [56, 28, 26] | [56, 29, 25] | [56, 28, 25] | [56, 29, 24] | [56, 28, 24] |
PCIE3:VF0_CAPABILITY_POINTER | [59, 29, 23] | [59, 28, 23] | [59, 29, 22] | [59, 28, 22] | [59, 29, 21] | [59, 28, 21] | [59, 29, 20] | [59, 28, 20] |
PCIE3:VF0_PM_CAP_ID | [69, 29, 27] | [69, 28, 27] | [69, 29, 26] | [69, 28, 26] | [69, 29, 25] | [69, 28, 25] | [69, 29, 24] | [69, 28, 24] |
PCIE3:VF0_PM_CAP_NEXTPTR | [70, 29, 11] | [70, 28, 11] | [70, 29, 10] | [70, 28, 10] | [70, 29, 9] | [70, 28, 9] | [70, 29, 8] | [70, 28, 8] |
PCIE3:VF1_PM_CAP_ID | [69, 29, 31] | [69, 28, 31] | [69, 29, 30] | [69, 28, 30] | [69, 29, 29] | [69, 28, 29] | [69, 29, 28] | [69, 28, 28] |
PCIE3:VF1_PM_CAP_NEXTPTR | [70, 29, 15] | [70, 28, 15] | [70, 29, 14] | [70, 28, 14] | [70, 29, 13] | [70, 28, 13] | [70, 29, 12] | [70, 28, 12] |
PCIE3:VF2_PM_CAP_ID | [69, 29, 35] | [69, 28, 35] | [69, 29, 34] | [69, 28, 34] | [69, 29, 33] | [69, 28, 33] | [69, 29, 32] | [69, 28, 32] |
PCIE3:VF2_PM_CAP_NEXTPTR | [70, 29, 19] | [70, 28, 19] | [70, 29, 18] | [70, 28, 18] | [70, 29, 17] | [70, 28, 17] | [70, 29, 16] | [70, 28, 16] |
PCIE3:VF3_PM_CAP_ID | [69, 29, 39] | [69, 28, 39] | [69, 29, 38] | [69, 28, 38] | [69, 29, 37] | [69, 28, 37] | [69, 29, 36] | [69, 28, 36] |
PCIE3:VF3_PM_CAP_NEXTPTR | [70, 29, 23] | [70, 28, 23] | [70, 29, 22] | [70, 28, 22] | [70, 29, 21] | [70, 28, 21] | [70, 29, 20] | [70, 28, 20] |
PCIE3:VF4_PM_CAP_ID | [69, 29, 43] | [69, 28, 43] | [69, 29, 42] | [69, 28, 42] | [69, 29, 41] | [69, 28, 41] | [69, 29, 40] | [69, 28, 40] |
PCIE3:VF4_PM_CAP_NEXTPTR | [70, 29, 27] | [70, 28, 27] | [70, 29, 26] | [70, 28, 26] | [70, 29, 25] | [70, 28, 25] | [70, 29, 24] | [70, 28, 24] |
PCIE3:VF5_PM_CAP_ID | [69, 29, 47] | [69, 28, 47] | [69, 29, 46] | [69, 28, 46] | [69, 29, 45] | [69, 28, 45] | [69, 29, 44] | [69, 28, 44] |
PCIE3:VF5_PM_CAP_NEXTPTR | [70, 29, 31] | [70, 28, 31] | [70, 29, 30] | [70, 28, 30] | [70, 29, 29] | [70, 28, 29] | [70, 29, 28] | [70, 28, 28] |
Non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:LL_ACK_TIMEOUT | [54, 28, 12] | [54, 29, 11] | [54, 28, 11] | [54, 29, 10] | [54, 28, 10] | [54, 29, 9] | [54, 28, 9] | [54, 29, 8] | [54, 28, 8] |
---|---|---|---|---|---|---|---|---|---|
PCIE3:LL_REPLAY_TIMEOUT | [54, 28, 20] | [54, 29, 19] | [54, 28, 19] | [54, 29, 18] | [54, 28, 18] | [54, 29, 17] | [54, 28, 17] | [54, 29, 16] | [54, 28, 16] |
Non-inverted | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_BAR0_APERTURE_SIZE | [59, 28, 29] | [59, 29, 28] | [59, 28, 28] | [59, 29, 27] | [59, 28, 27] |
---|---|---|---|---|---|
PCIE3:PF0_BAR1_APERTURE_SIZE | [59, 28, 37] | [59, 29, 36] | [59, 28, 36] | [59, 29, 35] | [59, 28, 35] |
PCIE3:PF0_BAR2_APERTURE_SIZE | [59, 28, 45] | [59, 29, 44] | [59, 28, 44] | [59, 29, 43] | [59, 28, 43] |
PCIE3:PF0_BAR3_APERTURE_SIZE | [60, 28, 5] | [60, 29, 4] | [60, 28, 4] | [60, 29, 3] | [60, 28, 3] |
PCIE3:PF0_BAR4_APERTURE_SIZE | [60, 28, 13] | [60, 29, 12] | [60, 28, 12] | [60, 29, 11] | [60, 28, 11] |
PCIE3:PF0_BAR5_APERTURE_SIZE | [60, 28, 21] | [60, 29, 20] | [60, 28, 20] | [60, 29, 19] | [60, 28, 19] |
PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL | [78, 28, 29] | [78, 29, 28] | [78, 28, 28] | [78, 29, 27] | [78, 28, 27] |
PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE | [60, 28, 27] | [60, 29, 26] | [60, 28, 26] | [60, 29, 25] | [60, 28, 25] |
PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE | [82, 28, 45] | [82, 29, 44] | [82, 28, 44] | [82, 29, 43] | [82, 28, 43] |
PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE | [83, 28, 5] | [83, 29, 4] | [83, 28, 4] | [83, 29, 3] | [83, 28, 3] |
PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE | [83, 28, 13] | [83, 29, 12] | [83, 28, 12] | [83, 29, 11] | [83, 28, 11] |
PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE | [83, 28, 21] | [83, 29, 20] | [83, 28, 20] | [83, 29, 19] | [83, 28, 19] |
PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE | [83, 28, 29] | [83, 29, 28] | [83, 28, 28] | [83, 29, 27] | [83, 28, 27] |
PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE | [83, 28, 37] | [83, 29, 36] | [83, 28, 36] | [83, 29, 35] | [83, 28, 35] |
PCIE3:PF1_BAR0_APERTURE_SIZE | [59, 29, 31] | [59, 28, 31] | [59, 29, 30] | [59, 28, 30] | [59, 29, 29] |
PCIE3:PF1_BAR1_APERTURE_SIZE | [59, 29, 39] | [59, 28, 39] | [59, 29, 38] | [59, 28, 38] | [59, 29, 37] |
PCIE3:PF1_BAR2_APERTURE_SIZE | [59, 29, 47] | [59, 28, 47] | [59, 29, 46] | [59, 28, 46] | [59, 29, 45] |
PCIE3:PF1_BAR3_APERTURE_SIZE | [60, 29, 7] | [60, 28, 7] | [60, 29, 6] | [60, 28, 6] | [60, 29, 5] |
PCIE3:PF1_BAR4_APERTURE_SIZE | [60, 29, 15] | [60, 28, 15] | [60, 29, 14] | [60, 28, 14] | [60, 29, 13] |
PCIE3:PF1_BAR5_APERTURE_SIZE | [60, 29, 23] | [60, 28, 23] | [60, 29, 22] | [60, 28, 22] | [60, 29, 21] |
PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL | [78, 29, 31] | [78, 28, 31] | [78, 29, 30] | [78, 28, 30] | [78, 29, 29] |
PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE | [60, 29, 29] | [60, 28, 29] | [60, 29, 28] | [60, 28, 28] | [60, 29, 27] |
PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE | [82, 29, 47] | [82, 28, 47] | [82, 29, 46] | [82, 28, 46] | [82, 29, 45] |
PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE | [83, 29, 7] | [83, 28, 7] | [83, 29, 6] | [83, 28, 6] | [83, 29, 5] |
PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE | [83, 29, 15] | [83, 28, 15] | [83, 29, 14] | [83, 28, 14] | [83, 29, 13] |
PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE | [83, 29, 23] | [83, 28, 23] | [83, 29, 22] | [83, 28, 22] | [83, 29, 21] |
PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE | [83, 29, 31] | [83, 28, 31] | [83, 29, 30] | [83, 28, 30] | [83, 29, 29] |
PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE | [83, 29, 39] | [83, 28, 39] | [83, 29, 38] | [83, 28, 38] | [83, 29, 37] |
PCIE3:PL_EQ_ADAPT_ITER_COUNT | [54, 29, 2] | [54, 28, 2] | [54, 29, 1] | [54, 28, 1] | [54, 29, 0] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_AER_CAP_NEXTPTR | [75, 29, 13] | [75, 28, 13] | [75, 29, 12] | [75, 28, 12] | [75, 29, 11] | [75, 28, 11] | [75, 29, 10] | [75, 28, 10] | [75, 29, 9] | [75, 28, 9] | [75, 29, 8] | [75, 28, 8] |
---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF0_ARI_CAP_NEXTPTR | [75, 28, 30] | [75, 29, 29] | [75, 28, 29] | [75, 29, 28] | [75, 28, 28] | [75, 29, 27] | [75, 28, 27] | [75, 29, 26] | [75, 28, 26] | [75, 29, 25] | [75, 28, 25] | [75, 29, 24] |
PCIE3:PF0_DPA_CAP_NEXTPTR | [78, 29, 13] | [78, 28, 13] | [78, 29, 12] | [78, 28, 12] | [78, 29, 11] | [78, 28, 11] | [78, 29, 10] | [78, 28, 10] | [78, 29, 9] | [78, 28, 9] | [78, 29, 8] | [78, 28, 8] |
PCIE3:PF0_DSN_CAP_NEXTPTR | [73, 29, 37] | [73, 28, 37] | [73, 29, 36] | [73, 28, 36] | [73, 29, 35] | [73, 28, 35] | [73, 29, 34] | [73, 28, 34] | [73, 29, 33] | [73, 28, 33] | [73, 29, 32] | [73, 28, 32] |
PCIE3:PF0_LTR_CAP_NEXTPTR | [77, 29, 29] | [77, 28, 29] | [77, 29, 28] | [77, 28, 28] | [77, 29, 27] | [77, 28, 27] | [77, 29, 26] | [77, 28, 26] | [77, 29, 25] | [77, 28, 25] | [77, 29, 24] | [77, 28, 24] |
PCIE3:PF0_PB_CAP_NEXTPTR | [77, 29, 5] | [77, 28, 5] | [77, 29, 4] | [77, 28, 4] | [77, 29, 3] | [77, 28, 3] | [77, 29, 2] | [77, 28, 2] | [77, 29, 1] | [77, 28, 1] | [77, 29, 0] | [77, 28, 0] |
PCIE3:PF0_RBAR_CAP_NEXTPTR | [71, 29, 13] | [71, 28, 13] | [71, 29, 12] | [71, 28, 12] | [71, 29, 11] | [71, 28, 11] | [71, 29, 10] | [71, 28, 10] | [71, 29, 9] | [71, 28, 9] | [71, 29, 8] | [71, 28, 8] |
PCIE3:PF0_SRIOV_CAP_NEXTPTR | [80, 28, 6] | [80, 29, 5] | [80, 28, 5] | [80, 29, 4] | [80, 28, 4] | [80, 29, 3] | [80, 28, 3] | [80, 29, 2] | [80, 28, 2] | [80, 29, 1] | [80, 28, 1] | [80, 29, 0] |
PCIE3:PF0_TPHR_CAP_NEXTPTR | [83, 29, 45] | [83, 28, 45] | [83, 29, 44] | [83, 28, 44] | [83, 29, 43] | [83, 28, 43] | [83, 29, 42] | [83, 28, 42] | [83, 29, 41] | [83, 28, 41] | [83, 29, 40] | [83, 28, 40] |
PCIE3:PF0_VC_CAP_NEXTPTR | [75, 29, 5] | [75, 28, 5] | [75, 29, 4] | [75, 28, 4] | [75, 29, 3] | [75, 28, 3] | [75, 29, 2] | [75, 28, 2] | [75, 29, 1] | [75, 28, 1] | [75, 29, 0] | [75, 28, 0] |
PCIE3:PF1_AER_CAP_NEXTPTR | [75, 29, 21] | [75, 28, 21] | [75, 29, 20] | [75, 28, 20] | [75, 29, 19] | [75, 28, 19] | [75, 29, 18] | [75, 28, 18] | [75, 29, 17] | [75, 28, 17] | [75, 29, 16] | [75, 28, 16] |
PCIE3:PF1_ARI_CAP_NEXTPTR | [75, 29, 37] | [75, 28, 37] | [75, 29, 36] | [75, 28, 36] | [75, 29, 35] | [75, 28, 35] | [75, 29, 34] | [75, 28, 34] | [75, 29, 33] | [75, 28, 33] | [75, 29, 32] | [75, 28, 32] |
PCIE3:PF1_DPA_CAP_NEXTPTR | [78, 29, 21] | [78, 28, 21] | [78, 29, 20] | [78, 28, 20] | [78, 29, 19] | [78, 28, 19] | [78, 29, 18] | [78, 28, 18] | [78, 29, 17] | [78, 28, 17] | [78, 29, 16] | [78, 28, 16] |
PCIE3:PF1_DSN_CAP_NEXTPTR | [73, 29, 45] | [73, 28, 45] | [73, 29, 44] | [73, 28, 44] | [73, 29, 43] | [73, 28, 43] | [73, 29, 42] | [73, 28, 42] | [73, 29, 41] | [73, 28, 41] | [73, 29, 40] | [73, 28, 40] |
PCIE3:PF1_PB_CAP_NEXTPTR | [77, 29, 13] | [77, 28, 13] | [77, 29, 12] | [77, 28, 12] | [77, 29, 11] | [77, 28, 11] | [77, 29, 10] | [77, 28, 10] | [77, 29, 9] | [77, 28, 9] | [77, 29, 8] | [77, 28, 8] |
PCIE3:PF1_RBAR_CAP_NEXTPTR | [71, 29, 21] | [71, 28, 21] | [71, 29, 20] | [71, 28, 20] | [71, 29, 19] | [71, 28, 19] | [71, 29, 18] | [71, 28, 18] | [71, 29, 17] | [71, 28, 17] | [71, 29, 16] | [71, 28, 16] |
PCIE3:PF1_SRIOV_CAP_NEXTPTR | [80, 29, 13] | [80, 28, 13] | [80, 29, 12] | [80, 28, 12] | [80, 29, 11] | [80, 28, 11] | [80, 29, 10] | [80, 28, 10] | [80, 29, 9] | [80, 28, 9] | [80, 29, 8] | [80, 28, 8] |
PCIE3:PF1_TPHR_CAP_NEXTPTR | [84, 29, 5] | [84, 28, 5] | [84, 29, 4] | [84, 28, 4] | [84, 29, 3] | [84, 28, 3] | [84, 29, 2] | [84, 28, 2] | [84, 29, 1] | [84, 28, 1] | [84, 29, 0] | [84, 28, 0] |
PCIE3:TL_CREDITS_CD | [55, 28, 38] | [55, 29, 37] | [55, 28, 37] | [55, 29, 36] | [55, 28, 36] | [55, 29, 35] | [55, 28, 35] | [55, 29, 34] | [55, 28, 34] | [55, 29, 33] | [55, 28, 33] | [55, 29, 32] |
PCIE3:TL_CREDITS_NPD | [56, 29, 5] | [56, 28, 5] | [56, 29, 4] | [56, 28, 4] | [56, 29, 3] | [56, 28, 3] | [56, 29, 2] | [56, 28, 2] | [56, 29, 1] | [56, 28, 1] | [56, 29, 0] | [56, 28, 0] |
PCIE3:TL_CREDITS_PD | [56, 29, 21] | [56, 28, 21] | [56, 29, 20] | [56, 28, 20] | [56, 29, 19] | [56, 28, 19] | [56, 29, 18] | [56, 28, 18] | [56, 29, 17] | [56, 28, 17] | [56, 29, 16] | [56, 28, 16] |
PCIE3:VF0_ARI_CAP_NEXTPTR | [75, 29, 45] | [75, 28, 45] | [75, 29, 44] | [75, 28, 44] | [75, 29, 43] | [75, 28, 43] | [75, 29, 42] | [75, 28, 42] | [75, 29, 41] | [75, 28, 41] | [75, 29, 40] | [75, 28, 40] |
PCIE3:VF0_TPHR_CAP_NEXTPTR | [84, 29, 13] | [84, 28, 13] | [84, 29, 12] | [84, 28, 12] | [84, 29, 11] | [84, 28, 11] | [84, 29, 10] | [84, 28, 10] | [84, 29, 9] | [84, 28, 9] | [84, 29, 8] | [84, 28, 8] |
PCIE3:VF1_ARI_CAP_NEXTPTR | [76, 29, 5] | [76, 28, 5] | [76, 29, 4] | [76, 28, 4] | [76, 29, 3] | [76, 28, 3] | [76, 29, 2] | [76, 28, 2] | [76, 29, 1] | [76, 28, 1] | [76, 29, 0] | [76, 28, 0] |
PCIE3:VF1_TPHR_CAP_NEXTPTR | [84, 29, 21] | [84, 28, 21] | [84, 29, 20] | [84, 28, 20] | [84, 29, 19] | [84, 28, 19] | [84, 29, 18] | [84, 28, 18] | [84, 29, 17] | [84, 28, 17] | [84, 29, 16] | [84, 28, 16] |
PCIE3:VF2_ARI_CAP_NEXTPTR | [76, 29, 13] | [76, 28, 13] | [76, 29, 12] | [76, 28, 12] | [76, 29, 11] | [76, 28, 11] | [76, 29, 10] | [76, 28, 10] | [76, 29, 9] | [76, 28, 9] | [76, 29, 8] | [76, 28, 8] |
PCIE3:VF2_TPHR_CAP_NEXTPTR | [84, 29, 29] | [84, 28, 29] | [84, 29, 28] | [84, 28, 28] | [84, 29, 27] | [84, 28, 27] | [84, 29, 26] | [84, 28, 26] | [84, 29, 25] | [84, 28, 25] | [84, 29, 24] | [84, 28, 24] |
PCIE3:VF3_ARI_CAP_NEXTPTR | [76, 29, 21] | [76, 28, 21] | [76, 29, 20] | [76, 28, 20] | [76, 29, 19] | [76, 28, 19] | [76, 29, 18] | [76, 28, 18] | [76, 29, 17] | [76, 28, 17] | [76, 29, 16] | [76, 28, 16] |
PCIE3:VF3_TPHR_CAP_NEXTPTR | [84, 29, 37] | [84, 28, 37] | [84, 29, 36] | [84, 28, 36] | [84, 29, 35] | [84, 28, 35] | [84, 29, 34] | [84, 28, 34] | [84, 29, 33] | [84, 28, 33] | [84, 29, 32] | [84, 28, 32] |
PCIE3:VF4_ARI_CAP_NEXTPTR | [76, 29, 29] | [76, 28, 29] | [76, 29, 28] | [76, 28, 28] | [76, 29, 27] | [76, 28, 27] | [76, 29, 26] | [76, 28, 26] | [76, 29, 25] | [76, 28, 25] | [76, 29, 24] | [76, 28, 24] |
PCIE3:VF4_TPHR_CAP_NEXTPTR | [84, 29, 45] | [84, 28, 45] | [84, 29, 44] | [84, 28, 44] | [84, 29, 43] | [84, 28, 43] | [84, 29, 42] | [84, 28, 42] | [84, 29, 41] | [84, 28, 41] | [84, 29, 40] | [84, 28, 40] |
PCIE3:VF5_ARI_CAP_NEXTPTR | [76, 29, 37] | [76, 28, 37] | [76, 29, 36] | [76, 28, 36] | [76, 29, 35] | [76, 28, 35] | [76, 29, 34] | [76, 28, 34] | [76, 29, 33] | [76, 28, 33] | [76, 29, 32] | [76, 28, 32] |
PCIE3:VF5_TPHR_CAP_NEXTPTR | [85, 29, 5] | [85, 28, 5] | [85, 29, 4] | [85, 28, 4] | [85, 29, 3] | [85, 28, 3] | [85, 29, 2] | [85, 28, 2] | [85, 29, 1] | [85, 28, 1] | [85, 29, 0] | [85, 28, 0] |
Non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_CLASS_CODE | [58, 29, 3] | [58, 28, 3] | [58, 29, 2] | [58, 28, 2] | [58, 29, 1] | [58, 28, 1] | [58, 29, 0] | [58, 28, 0] | [57, 29, 47] | [57, 28, 47] | [57, 29, 46] | [57, 28, 46] | [57, 29, 45] | [57, 28, 45] | [57, 29, 44] | [57, 28, 44] | [57, 29, 43] | [57, 28, 43] | [57, 29, 42] | [57, 28, 42] | [57, 29, 41] | [57, 28, 41] | [57, 29, 40] | [57, 28, 40] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF1_CLASS_CODE | [58, 29, 19] | [58, 28, 19] | [58, 29, 18] | [58, 28, 18] | [58, 29, 17] | [58, 28, 17] | [58, 29, 16] | [58, 28, 16] | [58, 29, 15] | [58, 28, 15] | [58, 29, 14] | [58, 28, 14] | [58, 29, 13] | [58, 28, 13] | [58, 29, 12] | [58, 28, 12] | [58, 29, 11] | [58, 28, 11] | [58, 29, 10] | [58, 28, 10] | [58, 29, 9] | [58, 28, 9] | [58, 29, 8] | [58, 28, 8] |
PCIE3:TL_COMPL_TIMEOUT_REG0 | [56, 29, 43] | [56, 28, 43] | [56, 29, 42] | [56, 28, 42] | [56, 29, 41] | [56, 28, 41] | [56, 29, 40] | [56, 28, 40] | [56, 29, 39] | [56, 28, 39] | [56, 29, 38] | [56, 28, 38] | [56, 29, 37] | [56, 28, 37] | [56, 29, 36] | [56, 28, 36] | [56, 29, 35] | [56, 28, 35] | [56, 29, 34] | [56, 28, 34] | [56, 29, 33] | [56, 28, 33] | [56, 29, 32] | [56, 28, 32] |
Non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:TL_COMPL_TIMEOUT_REG1 | [57, 29, 13] | [57, 28, 13] | [57, 29, 12] | [57, 28, 12] | [57, 29, 11] | [57, 28, 11] | [57, 29, 10] | [57, 28, 10] | [57, 29, 9] | [57, 28, 9] | [57, 29, 8] | [57, 28, 8] | [57, 29, 7] | [57, 28, 7] | [57, 29, 6] | [57, 28, 6] | [57, 29, 5] | [57, 28, 5] | [57, 29, 4] | [57, 28, 4] | [57, 29, 3] | [57, 28, 3] | [57, 29, 2] | [57, 28, 2] | [57, 29, 1] | [57, 28, 1] | [57, 29, 0] | [57, 28, 0] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Non-inverted | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_MSIX_CAP_PBA_OFFSET | [62, 28, 30] | [62, 29, 29] | [62, 28, 29] | [62, 29, 28] | [62, 28, 28] | [62, 29, 27] | [62, 28, 27] | [62, 29, 26] | [62, 28, 26] | [62, 29, 25] | [62, 28, 25] | [62, 29, 24] | [62, 28, 24] | [62, 29, 23] | [62, 28, 23] | [62, 29, 22] | [62, 28, 22] | [62, 29, 21] | [62, 28, 21] | [62, 29, 20] | [62, 28, 20] | [62, 29, 19] | [62, 28, 19] | [62, 29, 18] | [62, 28, 18] | [62, 29, 17] | [62, 28, 17] | [62, 29, 16] | [62, 28, 16] |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF0_MSIX_CAP_TABLE_OFFSET | [65, 28, 30] | [65, 29, 29] | [65, 28, 29] | [65, 29, 28] | [65, 28, 28] | [65, 29, 27] | [65, 28, 27] | [65, 29, 26] | [65, 28, 26] | [65, 29, 25] | [65, 28, 25] | [65, 29, 24] | [65, 28, 24] | [65, 29, 23] | [65, 28, 23] | [65, 29, 22] | [65, 28, 22] | [65, 29, 21] | [65, 28, 21] | [65, 29, 20] | [65, 28, 20] | [65, 29, 19] | [65, 28, 19] | [65, 29, 18] | [65, 28, 18] | [65, 29, 17] | [65, 28, 17] | [65, 29, 16] | [65, 28, 16] |
PCIE3:PF1_MSIX_CAP_PBA_OFFSET | [62, 28, 46] | [62, 29, 45] | [62, 28, 45] | [62, 29, 44] | [62, 28, 44] | [62, 29, 43] | [62, 28, 43] | [62, 29, 42] | [62, 28, 42] | [62, 29, 41] | [62, 28, 41] | [62, 29, 40] | [62, 28, 40] | [62, 29, 39] | [62, 28, 39] | [62, 29, 38] | [62, 28, 38] | [62, 29, 37] | [62, 28, 37] | [62, 29, 36] | [62, 28, 36] | [62, 29, 35] | [62, 28, 35] | [62, 29, 34] | [62, 28, 34] | [62, 29, 33] | [62, 28, 33] | [62, 29, 32] | [62, 28, 32] |
PCIE3:PF1_MSIX_CAP_TABLE_OFFSET | [65, 28, 46] | [65, 29, 45] | [65, 28, 45] | [65, 29, 44] | [65, 28, 44] | [65, 29, 43] | [65, 28, 43] | [65, 29, 42] | [65, 28, 42] | [65, 29, 41] | [65, 28, 41] | [65, 29, 40] | [65, 28, 40] | [65, 29, 39] | [65, 28, 39] | [65, 29, 38] | [65, 28, 38] | [65, 29, 37] | [65, 28, 37] | [65, 29, 36] | [65, 28, 36] | [65, 29, 35] | [65, 28, 35] | [65, 29, 34] | [65, 28, 34] | [65, 29, 33] | [65, 28, 33] | [65, 29, 32] | [65, 28, 32] |
PCIE3:VF0_MSIX_CAP_PBA_OFFSET | [63, 28, 14] | [63, 29, 13] | [63, 28, 13] | [63, 29, 12] | [63, 28, 12] | [63, 29, 11] | [63, 28, 11] | [63, 29, 10] | [63, 28, 10] | [63, 29, 9] | [63, 28, 9] | [63, 29, 8] | [63, 28, 8] | [63, 29, 7] | [63, 28, 7] | [63, 29, 6] | [63, 28, 6] | [63, 29, 5] | [63, 28, 5] | [63, 29, 4] | [63, 28, 4] | [63, 29, 3] | [63, 28, 3] | [63, 29, 2] | [63, 28, 2] | [63, 29, 1] | [63, 28, 1] | [63, 29, 0] | [63, 28, 0] |
PCIE3:VF0_MSIX_CAP_TABLE_OFFSET | [66, 28, 14] | [66, 29, 13] | [66, 28, 13] | [66, 29, 12] | [66, 28, 12] | [66, 29, 11] | [66, 28, 11] | [66, 29, 10] | [66, 28, 10] | [66, 29, 9] | [66, 28, 9] | [66, 29, 8] | [66, 28, 8] | [66, 29, 7] | [66, 28, 7] | [66, 29, 6] | [66, 28, 6] | [66, 29, 5] | [66, 28, 5] | [66, 29, 4] | [66, 28, 4] | [66, 29, 3] | [66, 28, 3] | [66, 29, 2] | [66, 28, 2] | [66, 29, 1] | [66, 28, 1] | [66, 29, 0] | [66, 28, 0] |
PCIE3:VF1_MSIX_CAP_PBA_OFFSET | [63, 28, 30] | [63, 29, 29] | [63, 28, 29] | [63, 29, 28] | [63, 28, 28] | [63, 29, 27] | [63, 28, 27] | [63, 29, 26] | [63, 28, 26] | [63, 29, 25] | [63, 28, 25] | [63, 29, 24] | [63, 28, 24] | [63, 29, 23] | [63, 28, 23] | [63, 29, 22] | [63, 28, 22] | [63, 29, 21] | [63, 28, 21] | [63, 29, 20] | [63, 28, 20] | [63, 29, 19] | [63, 28, 19] | [63, 29, 18] | [63, 28, 18] | [63, 29, 17] | [63, 28, 17] | [63, 29, 16] | [63, 28, 16] |
PCIE3:VF1_MSIX_CAP_TABLE_OFFSET | [66, 28, 30] | [66, 29, 29] | [66, 28, 29] | [66, 29, 28] | [66, 28, 28] | [66, 29, 27] | [66, 28, 27] | [66, 29, 26] | [66, 28, 26] | [66, 29, 25] | [66, 28, 25] | [66, 29, 24] | [66, 28, 24] | [66, 29, 23] | [66, 28, 23] | [66, 29, 22] | [66, 28, 22] | [66, 29, 21] | [66, 28, 21] | [66, 29, 20] | [66, 28, 20] | [66, 29, 19] | [66, 28, 19] | [66, 29, 18] | [66, 28, 18] | [66, 29, 17] | [66, 28, 17] | [66, 29, 16] | [66, 28, 16] |
PCIE3:VF2_MSIX_CAP_PBA_OFFSET | [63, 28, 46] | [63, 29, 45] | [63, 28, 45] | [63, 29, 44] | [63, 28, 44] | [63, 29, 43] | [63, 28, 43] | [63, 29, 42] | [63, 28, 42] | [63, 29, 41] | [63, 28, 41] | [63, 29, 40] | [63, 28, 40] | [63, 29, 39] | [63, 28, 39] | [63, 29, 38] | [63, 28, 38] | [63, 29, 37] | [63, 28, 37] | [63, 29, 36] | [63, 28, 36] | [63, 29, 35] | [63, 28, 35] | [63, 29, 34] | [63, 28, 34] | [63, 29, 33] | [63, 28, 33] | [63, 29, 32] | [63, 28, 32] |
PCIE3:VF2_MSIX_CAP_TABLE_OFFSET | [66, 28, 46] | [66, 29, 45] | [66, 28, 45] | [66, 29, 44] | [66, 28, 44] | [66, 29, 43] | [66, 28, 43] | [66, 29, 42] | [66, 28, 42] | [66, 29, 41] | [66, 28, 41] | [66, 29, 40] | [66, 28, 40] | [66, 29, 39] | [66, 28, 39] | [66, 29, 38] | [66, 28, 38] | [66, 29, 37] | [66, 28, 37] | [66, 29, 36] | [66, 28, 36] | [66, 29, 35] | [66, 28, 35] | [66, 29, 34] | [66, 28, 34] | [66, 29, 33] | [66, 28, 33] | [66, 29, 32] | [66, 28, 32] |
PCIE3:VF3_MSIX_CAP_PBA_OFFSET | [64, 28, 14] | [64, 29, 13] | [64, 28, 13] | [64, 29, 12] | [64, 28, 12] | [64, 29, 11] | [64, 28, 11] | [64, 29, 10] | [64, 28, 10] | [64, 29, 9] | [64, 28, 9] | [64, 29, 8] | [64, 28, 8] | [64, 29, 7] | [64, 28, 7] | [64, 29, 6] | [64, 28, 6] | [64, 29, 5] | [64, 28, 5] | [64, 29, 4] | [64, 28, 4] | [64, 29, 3] | [64, 28, 3] | [64, 29, 2] | [64, 28, 2] | [64, 29, 1] | [64, 28, 1] | [64, 29, 0] | [64, 28, 0] |
PCIE3:VF3_MSIX_CAP_TABLE_OFFSET | [67, 28, 14] | [67, 29, 13] | [67, 28, 13] | [67, 29, 12] | [67, 28, 12] | [67, 29, 11] | [67, 28, 11] | [67, 29, 10] | [67, 28, 10] | [67, 29, 9] | [67, 28, 9] | [67, 29, 8] | [67, 28, 8] | [67, 29, 7] | [67, 28, 7] | [67, 29, 6] | [67, 28, 6] | [67, 29, 5] | [67, 28, 5] | [67, 29, 4] | [67, 28, 4] | [67, 29, 3] | [67, 28, 3] | [67, 29, 2] | [67, 28, 2] | [67, 29, 1] | [67, 28, 1] | [67, 29, 0] | [67, 28, 0] |
PCIE3:VF4_MSIX_CAP_PBA_OFFSET | [64, 28, 30] | [64, 29, 29] | [64, 28, 29] | [64, 29, 28] | [64, 28, 28] | [64, 29, 27] | [64, 28, 27] | [64, 29, 26] | [64, 28, 26] | [64, 29, 25] | [64, 28, 25] | [64, 29, 24] | [64, 28, 24] | [64, 29, 23] | [64, 28, 23] | [64, 29, 22] | [64, 28, 22] | [64, 29, 21] | [64, 28, 21] | [64, 29, 20] | [64, 28, 20] | [64, 29, 19] | [64, 28, 19] | [64, 29, 18] | [64, 28, 18] | [64, 29, 17] | [64, 28, 17] | [64, 29, 16] | [64, 28, 16] |
PCIE3:VF4_MSIX_CAP_TABLE_OFFSET | [67, 28, 30] | [67, 29, 29] | [67, 28, 29] | [67, 29, 28] | [67, 28, 28] | [67, 29, 27] | [67, 28, 27] | [67, 29, 26] | [67, 28, 26] | [67, 29, 25] | [67, 28, 25] | [67, 29, 24] | [67, 28, 24] | [67, 29, 23] | [67, 28, 23] | [67, 29, 22] | [67, 28, 22] | [67, 29, 21] | [67, 28, 21] | [67, 29, 20] | [67, 28, 20] | [67, 29, 19] | [67, 28, 19] | [67, 29, 18] | [67, 28, 18] | [67, 29, 17] | [67, 28, 17] | [67, 29, 16] | [67, 28, 16] |
PCIE3:VF5_MSIX_CAP_PBA_OFFSET | [64, 28, 46] | [64, 29, 45] | [64, 28, 45] | [64, 29, 44] | [64, 28, 44] | [64, 29, 43] | [64, 28, 43] | [64, 29, 42] | [64, 28, 42] | [64, 29, 41] | [64, 28, 41] | [64, 29, 40] | [64, 28, 40] | [64, 29, 39] | [64, 28, 39] | [64, 29, 38] | [64, 28, 38] | [64, 29, 37] | [64, 28, 37] | [64, 29, 36] | [64, 28, 36] | [64, 29, 35] | [64, 28, 35] | [64, 29, 34] | [64, 28, 34] | [64, 29, 33] | [64, 28, 33] | [64, 29, 32] | [64, 28, 32] |
PCIE3:VF5_MSIX_CAP_TABLE_OFFSET | [67, 28, 46] | [67, 29, 45] | [67, 28, 45] | [67, 29, 44] | [67, 28, 44] | [67, 29, 43] | [67, 28, 43] | [67, 29, 42] | [67, 28, 42] | [67, 29, 41] | [67, 28, 41] | [67, 29, 40] | [67, 28, 40] | [67, 29, 39] | [67, 28, 39] | [67, 29, 38] | [67, 28, 38] | [67, 29, 37] | [67, 28, 37] | [67, 29, 36] | [67, 28, 36] | [67, 29, 35] | [67, 28, 35] | [67, 29, 34] | [67, 28, 34] | [67, 29, 33] | [67, 28, 33] | [67, 29, 32] | [67, 28, 32] |
Non-inverted | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:PF0_MSIX_CAP_TABLE_SIZE | [68, 28, 5] | [68, 29, 4] | [68, 28, 4] | [68, 29, 3] | [68, 28, 3] | [68, 29, 2] | [68, 28, 2] | [68, 29, 1] | [68, 28, 1] | [68, 29, 0] | [68, 28, 0] |
---|---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE | [85, 28, 45] | [85, 29, 44] | [85, 28, 44] | [85, 29, 43] | [85, 28, 43] | [85, 29, 42] | [85, 28, 42] | [85, 29, 41] | [85, 28, 41] | [85, 29, 40] | [85, 28, 40] |
PCIE3:PF1_MSIX_CAP_TABLE_SIZE | [68, 28, 13] | [68, 29, 12] | [68, 28, 12] | [68, 29, 11] | [68, 28, 11] | [68, 29, 10] | [68, 28, 10] | [68, 29, 9] | [68, 28, 9] | [68, 29, 8] | [68, 28, 8] |
PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 5] | [86, 29, 4] | [86, 28, 4] | [86, 29, 3] | [86, 28, 3] | [86, 29, 2] | [86, 28, 2] | [86, 29, 1] | [86, 28, 1] | [86, 29, 0] | [86, 28, 0] |
PCIE3:VF0_MSIX_CAP_TABLE_SIZE | [68, 28, 21] | [68, 29, 20] | [68, 28, 20] | [68, 29, 19] | [68, 28, 19] | [68, 29, 18] | [68, 28, 18] | [68, 29, 17] | [68, 28, 17] | [68, 29, 16] | [68, 28, 16] |
PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 13] | [86, 29, 12] | [86, 28, 12] | [86, 29, 11] | [86, 28, 11] | [86, 29, 10] | [86, 28, 10] | [86, 29, 9] | [86, 28, 9] | [86, 29, 8] | [86, 28, 8] |
PCIE3:VF1_MSIX_CAP_TABLE_SIZE | [68, 28, 29] | [68, 29, 28] | [68, 28, 28] | [68, 29, 27] | [68, 28, 27] | [68, 29, 26] | [68, 28, 26] | [68, 29, 25] | [68, 28, 25] | [68, 29, 24] | [68, 28, 24] |
PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 21] | [86, 29, 20] | [86, 28, 20] | [86, 29, 19] | [86, 28, 19] | [86, 29, 18] | [86, 28, 18] | [86, 29, 17] | [86, 28, 17] | [86, 29, 16] | [86, 28, 16] |
PCIE3:VF2_MSIX_CAP_TABLE_SIZE | [68, 28, 37] | [68, 29, 36] | [68, 28, 36] | [68, 29, 35] | [68, 28, 35] | [68, 29, 34] | [68, 28, 34] | [68, 29, 33] | [68, 28, 33] | [68, 29, 32] | [68, 28, 32] |
PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 29] | [86, 29, 28] | [86, 28, 28] | [86, 29, 27] | [86, 28, 27] | [86, 29, 26] | [86, 28, 26] | [86, 29, 25] | [86, 28, 25] | [86, 29, 24] | [86, 28, 24] |
PCIE3:VF3_MSIX_CAP_TABLE_SIZE | [68, 28, 45] | [68, 29, 44] | [68, 28, 44] | [68, 29, 43] | [68, 28, 43] | [68, 29, 42] | [68, 28, 42] | [68, 29, 41] | [68, 28, 41] | [68, 29, 40] | [68, 28, 40] |
PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 37] | [86, 29, 36] | [86, 28, 36] | [86, 29, 35] | [86, 28, 35] | [86, 29, 34] | [86, 28, 34] | [86, 29, 33] | [86, 28, 33] | [86, 29, 32] | [86, 28, 32] |
PCIE3:VF4_MSIX_CAP_TABLE_SIZE | [69, 28, 5] | [69, 29, 4] | [69, 28, 4] | [69, 29, 3] | [69, 28, 3] | [69, 29, 2] | [69, 28, 2] | [69, 29, 1] | [69, 28, 1] | [69, 29, 0] | [69, 28, 0] |
PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE | [86, 28, 45] | [86, 29, 44] | [86, 28, 44] | [86, 29, 43] | [86, 28, 43] | [86, 29, 42] | [86, 28, 42] | [86, 29, 41] | [86, 28, 41] | [86, 29, 40] | [86, 28, 40] |
PCIE3:VF5_MSIX_CAP_TABLE_SIZE | [69, 28, 13] | [69, 29, 12] | [69, 28, 12] | [69, 29, 11] | [69, 28, 11] | [69, 29, 10] | [69, 28, 10] | [69, 29, 9] | [69, 28, 9] | [69, 29, 8] | [69, 28, 8] |
PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE | [87, 28, 5] | [87, 29, 4] | [87, 28, 4] | [87, 29, 3] | [87, 28, 3] | [87, 29, 2] | [87, 28, 2] | [87, 29, 1] | [87, 28, 1] | [87, 29, 0] | [87, 28, 0] |
Non-inverted | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL | [78, 29, 4] | [78, 28, 4] | [78, 29, 3] | [78, 28, 3] | [78, 29, 2] | [78, 28, 2] | [78, 29, 1] | [78, 28, 1] | [78, 29, 0] | [78, 28, 0] |
---|---|---|---|---|---|---|---|---|---|---|
PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT | [77, 29, 44] | [77, 28, 44] | [77, 29, 43] | [77, 28, 43] | [77, 29, 42] | [77, 28, 42] | [77, 29, 41] | [77, 28, 41] | [77, 29, 40] | [77, 28, 40] |
PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT | [77, 29, 36] | [77, 28, 36] | [77, 29, 35] | [77, 28, 35] | [77, 29, 34] | [77, 28, 34] | [77, 29, 33] | [77, 28, 33] | [77, 29, 32] | [77, 28, 32] |
Non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |