PCI Express Gen3 cores

Bitstream

PCIE3 bittile 0
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:CRM_CORE_CLK_FREQ_500PCIE3:CRM_USER_CLK_FREQ[0]
1 ----------------------------PCIE3:CRM_USER_CLK_FREQ[1]PCIE3:AXISTEN_IF_WIDTH[0]
2 ----------------------------PCIE3:AXISTEN_IF_WIDTH[1]PCIE3:AXISTEN_IF_CQ_ALIGNMENT_MODE
3 ----------------------------PCIE3:AXISTEN_IF_CC_ALIGNMENT_MODEPCIE3:AXISTEN_IF_RQ_ALIGNMENT_MODE
4 ----------------------------PCIE3:AXISTEN_IF_RC_ALIGNMENT_MODEPCIE3:AXISTEN_IF_RC_STRADDLE
5 ----------------------------PCIE3:AXISTEN_IF_ENABLE_RX_MSG_INTFC-
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[0]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[1]
9 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[2]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[3]
10 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[4]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[5]
11 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[6]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[7]
12 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[8]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[9]
13 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[10]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[11]
14 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[12]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[13]
15 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[14]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[15]
16 ----------------------------PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[16]PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[17]
17 ----------------------------PCIE3:AXISTEN_IF_RQ_PARITY_CHKPCIE3:AXISTEN_IF_CC_PARITY_CHK
18 ----------------------------PCIE3:AXISTEN_IF_ENABLE_CLIENT_TAG-
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[0]PCIE3:PM_ASPML0S_TIMEOUT[1]
25 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[2]PCIE3:PM_ASPML0S_TIMEOUT[3]
26 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[4]PCIE3:PM_ASPML0S_TIMEOUT[5]
27 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[6]PCIE3:PM_ASPML0S_TIMEOUT[7]
28 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[8]PCIE3:PM_ASPML0S_TIMEOUT[9]
29 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[10]PCIE3:PM_ASPML0S_TIMEOUT[11]
30 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[12]PCIE3:PM_ASPML0S_TIMEOUT[13]
31 ----------------------------PCIE3:PM_ASPML0S_TIMEOUT[14]PCIE3:PM_ASPML0S_TIMEOUT[15]
32 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[0]PCIE3:PM_L1_REENTRY_DELAY[1]
33 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[2]PCIE3:PM_L1_REENTRY_DELAY[3]
34 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[4]PCIE3:PM_L1_REENTRY_DELAY[5]
35 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[6]PCIE3:PM_L1_REENTRY_DELAY[7]
36 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[8]PCIE3:PM_L1_REENTRY_DELAY[9]
37 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[10]PCIE3:PM_L1_REENTRY_DELAY[11]
38 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[12]PCIE3:PM_L1_REENTRY_DELAY[13]
39 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[14]PCIE3:PM_L1_REENTRY_DELAY[15]
40 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[16]PCIE3:PM_L1_REENTRY_DELAY[17]
41 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[18]PCIE3:PM_L1_REENTRY_DELAY[19]
42 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[20]PCIE3:PM_L1_REENTRY_DELAY[21]
43 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[22]PCIE3:PM_L1_REENTRY_DELAY[23]
44 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[24]PCIE3:PM_L1_REENTRY_DELAY[25]
45 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[26]PCIE3:PM_L1_REENTRY_DELAY[27]
46 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[28]PCIE3:PM_L1_REENTRY_DELAY[29]
47 ----------------------------PCIE3:PM_L1_REENTRY_DELAY[30]PCIE3:PM_L1_REENTRY_DELAY[31]
PCIE3 bittile 1
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[0]PCIE3:PM_ASPML1_ENTRY_DELAY[1]
1 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[2]PCIE3:PM_ASPML1_ENTRY_DELAY[3]
2 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[4]PCIE3:PM_ASPML1_ENTRY_DELAY[5]
3 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[6]PCIE3:PM_ASPML1_ENTRY_DELAY[7]
4 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[8]PCIE3:PM_ASPML1_ENTRY_DELAY[9]
5 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[10]PCIE3:PM_ASPML1_ENTRY_DELAY[11]
6 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[12]PCIE3:PM_ASPML1_ENTRY_DELAY[13]
7 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[14]PCIE3:PM_ASPML1_ENTRY_DELAY[15]
8 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[16]PCIE3:PM_ASPML1_ENTRY_DELAY[17]
9 ----------------------------PCIE3:PM_ASPML1_ENTRY_DELAY[18]PCIE3:PM_ASPML1_ENTRY_DELAY[19]
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[0]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[1]
17 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[2]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[3]
18 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[4]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[5]
19 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[6]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[7]
20 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[8]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[9]
21 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[10]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[11]
22 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[12]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[13]
23 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[14]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[15]
24 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[16]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[17]
25 ----------------------------PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[18]PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[19]
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[0]PCIE3:PM_PME_TURNOFF_ACK_DELAY[1]
33 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[2]PCIE3:PM_PME_TURNOFF_ACK_DELAY[3]
34 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[4]PCIE3:PM_PME_TURNOFF_ACK_DELAY[5]
35 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[6]PCIE3:PM_PME_TURNOFF_ACK_DELAY[7]
36 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[8]PCIE3:PM_PME_TURNOFF_ACK_DELAY[9]
37 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[10]PCIE3:PM_PME_TURNOFF_ACK_DELAY[11]
38 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[12]PCIE3:PM_PME_TURNOFF_ACK_DELAY[13]
39 ----------------------------PCIE3:PM_PME_TURNOFF_ACK_DELAY[14]PCIE3:PM_PME_TURNOFF_ACK_DELAY[15]
40 -----------------------------PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[0]
41 ----------------------------PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[1]PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[2]
42 ----------------------------PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[3]PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[0]
43 ----------------------------PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[1]PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[2]
PCIE3 bittile 2
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN1[0]PCIE3:PL_N_FTS_COMCLK_GEN1[1]
1 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN1[2]PCIE3:PL_N_FTS_COMCLK_GEN1[3]
2 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN1[4]PCIE3:PL_N_FTS_COMCLK_GEN1[5]
3 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN1[6]PCIE3:PL_N_FTS_COMCLK_GEN1[7]
4 ----------------------------PCIE3:PL_N_FTS_GEN1[0]PCIE3:PL_N_FTS_GEN1[1]
5 ----------------------------PCIE3:PL_N_FTS_GEN1[2]PCIE3:PL_N_FTS_GEN1[3]
6 ----------------------------PCIE3:PL_N_FTS_GEN1[4]PCIE3:PL_N_FTS_GEN1[5]
7 ----------------------------PCIE3:PL_N_FTS_GEN1[6]PCIE3:PL_N_FTS_GEN1[7]
8 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN2[0]PCIE3:PL_N_FTS_COMCLK_GEN2[1]
9 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN2[2]PCIE3:PL_N_FTS_COMCLK_GEN2[3]
10 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN2[4]PCIE3:PL_N_FTS_COMCLK_GEN2[5]
11 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN2[6]PCIE3:PL_N_FTS_COMCLK_GEN2[7]
12 ----------------------------PCIE3:PL_N_FTS_GEN2[0]PCIE3:PL_N_FTS_GEN2[1]
13 ----------------------------PCIE3:PL_N_FTS_GEN2[2]PCIE3:PL_N_FTS_GEN2[3]
14 ----------------------------PCIE3:PL_N_FTS_GEN2[4]PCIE3:PL_N_FTS_GEN2[5]
15 ----------------------------PCIE3:PL_N_FTS_GEN2[6]PCIE3:PL_N_FTS_GEN2[7]
16 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN3[0]PCIE3:PL_N_FTS_COMCLK_GEN3[1]
17 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN3[2]PCIE3:PL_N_FTS_COMCLK_GEN3[3]
18 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN3[4]PCIE3:PL_N_FTS_COMCLK_GEN3[5]
19 ----------------------------PCIE3:PL_N_FTS_COMCLK_GEN3[6]PCIE3:PL_N_FTS_COMCLK_GEN3[7]
20 ----------------------------PCIE3:PL_N_FTS_GEN3[0]PCIE3:PL_N_FTS_GEN3[1]
21 ----------------------------PCIE3:PL_N_FTS_GEN3[2]PCIE3:PL_N_FTS_GEN3[3]
22 ----------------------------PCIE3:PL_N_FTS_GEN3[4]PCIE3:PL_N_FTS_GEN3[5]
23 ----------------------------PCIE3:PL_N_FTS_GEN3[6]PCIE3:PL_N_FTS_GEN3[7]
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[0]PCIE3:PL_LANE0_EQ_CONTROL[1]
33 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[2]PCIE3:PL_LANE0_EQ_CONTROL[3]
34 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[4]PCIE3:PL_LANE0_EQ_CONTROL[5]
35 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[6]PCIE3:PL_LANE0_EQ_CONTROL[7]
36 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[8]PCIE3:PL_LANE0_EQ_CONTROL[9]
37 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[10]PCIE3:PL_LANE0_EQ_CONTROL[11]
38 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[12]PCIE3:PL_LANE0_EQ_CONTROL[13]
39 ----------------------------PCIE3:PL_LANE0_EQ_CONTROL[14]PCIE3:PL_LANE0_EQ_CONTROL[15]
40 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[0]PCIE3:PL_LANE1_EQ_CONTROL[1]
41 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[2]PCIE3:PL_LANE1_EQ_CONTROL[3]
42 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[4]PCIE3:PL_LANE1_EQ_CONTROL[5]
43 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[6]PCIE3:PL_LANE1_EQ_CONTROL[7]
44 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[8]PCIE3:PL_LANE1_EQ_CONTROL[9]
45 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[10]PCIE3:PL_LANE1_EQ_CONTROL[11]
46 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[12]PCIE3:PL_LANE1_EQ_CONTROL[13]
47 ----------------------------PCIE3:PL_LANE1_EQ_CONTROL[14]PCIE3:PL_LANE1_EQ_CONTROL[15]
PCIE3 bittile 3
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[0]PCIE3:PL_LANE2_EQ_CONTROL[1]
1 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[2]PCIE3:PL_LANE2_EQ_CONTROL[3]
2 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[4]PCIE3:PL_LANE2_EQ_CONTROL[5]
3 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[6]PCIE3:PL_LANE2_EQ_CONTROL[7]
4 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[8]PCIE3:PL_LANE2_EQ_CONTROL[9]
5 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[10]PCIE3:PL_LANE2_EQ_CONTROL[11]
6 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[12]PCIE3:PL_LANE2_EQ_CONTROL[13]
7 ----------------------------PCIE3:PL_LANE2_EQ_CONTROL[14]PCIE3:PL_LANE2_EQ_CONTROL[15]
8 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[0]PCIE3:PL_LANE3_EQ_CONTROL[1]
9 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[2]PCIE3:PL_LANE3_EQ_CONTROL[3]
10 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[4]PCIE3:PL_LANE3_EQ_CONTROL[5]
11 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[6]PCIE3:PL_LANE3_EQ_CONTROL[7]
12 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[8]PCIE3:PL_LANE3_EQ_CONTROL[9]
13 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[10]PCIE3:PL_LANE3_EQ_CONTROL[11]
14 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[12]PCIE3:PL_LANE3_EQ_CONTROL[13]
15 ----------------------------PCIE3:PL_LANE3_EQ_CONTROL[14]PCIE3:PL_LANE3_EQ_CONTROL[15]
16 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[0]PCIE3:PL_LANE4_EQ_CONTROL[1]
17 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[2]PCIE3:PL_LANE4_EQ_CONTROL[3]
18 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[4]PCIE3:PL_LANE4_EQ_CONTROL[5]
19 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[6]PCIE3:PL_LANE4_EQ_CONTROL[7]
20 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[8]PCIE3:PL_LANE4_EQ_CONTROL[9]
21 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[10]PCIE3:PL_LANE4_EQ_CONTROL[11]
22 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[12]PCIE3:PL_LANE4_EQ_CONTROL[13]
23 ----------------------------PCIE3:PL_LANE4_EQ_CONTROL[14]PCIE3:PL_LANE4_EQ_CONTROL[15]
24 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[0]PCIE3:PL_LANE5_EQ_CONTROL[1]
25 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[2]PCIE3:PL_LANE5_EQ_CONTROL[3]
26 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[4]PCIE3:PL_LANE5_EQ_CONTROL[5]
27 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[6]PCIE3:PL_LANE5_EQ_CONTROL[7]
28 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[8]PCIE3:PL_LANE5_EQ_CONTROL[9]
29 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[10]PCIE3:PL_LANE5_EQ_CONTROL[11]
30 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[12]PCIE3:PL_LANE5_EQ_CONTROL[13]
31 ----------------------------PCIE3:PL_LANE5_EQ_CONTROL[14]PCIE3:PL_LANE5_EQ_CONTROL[15]
32 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[0]PCIE3:PL_LANE6_EQ_CONTROL[1]
33 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[2]PCIE3:PL_LANE6_EQ_CONTROL[3]
34 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[4]PCIE3:PL_LANE6_EQ_CONTROL[5]
35 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[6]PCIE3:PL_LANE6_EQ_CONTROL[7]
36 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[8]PCIE3:PL_LANE6_EQ_CONTROL[9]
37 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[10]PCIE3:PL_LANE6_EQ_CONTROL[11]
38 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[12]PCIE3:PL_LANE6_EQ_CONTROL[13]
39 ----------------------------PCIE3:PL_LANE6_EQ_CONTROL[14]PCIE3:PL_LANE6_EQ_CONTROL[15]
40 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[0]PCIE3:PL_LANE7_EQ_CONTROL[1]
41 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[2]PCIE3:PL_LANE7_EQ_CONTROL[3]
42 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[4]PCIE3:PL_LANE7_EQ_CONTROL[5]
43 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[6]PCIE3:PL_LANE7_EQ_CONTROL[7]
44 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[8]PCIE3:PL_LANE7_EQ_CONTROL[9]
45 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[10]PCIE3:PL_LANE7_EQ_CONTROL[11]
46 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[12]PCIE3:PL_LANE7_EQ_CONTROL[13]
47 ----------------------------PCIE3:PL_LANE7_EQ_CONTROL[14]PCIE3:PL_LANE7_EQ_CONTROL[15]
PCIE3 bittile 4
RowColumn
01234567891011121314151617181920212223242526272829
0 -----------------------------PCIE3:PL_EQ_ADAPT_ITER_COUNT[0]
1 ----------------------------PCIE3:PL_EQ_ADAPT_ITER_COUNT[1]PCIE3:PL_EQ_ADAPT_ITER_COUNT[2]
2 ----------------------------PCIE3:PL_EQ_ADAPT_ITER_COUNT[3]PCIE3:PL_EQ_ADAPT_ITER_COUNT[4]
3 ----------------------------PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT[0]PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT[1]
4 ------------------------------
5 ------------------------------
6 ----------------------------PCIE3:LL_ACK_TIMEOUT_EN-
7 ------------------------------
8 ----------------------------PCIE3:LL_ACK_TIMEOUT[0]PCIE3:LL_ACK_TIMEOUT[1]
9 ----------------------------PCIE3:LL_ACK_TIMEOUT[2]PCIE3:LL_ACK_TIMEOUT[3]
10 ----------------------------PCIE3:LL_ACK_TIMEOUT[4]PCIE3:LL_ACK_TIMEOUT[5]
11 ----------------------------PCIE3:LL_ACK_TIMEOUT[6]PCIE3:LL_ACK_TIMEOUT[7]
12 ----------------------------PCIE3:LL_ACK_TIMEOUT[8]PCIE3:LL_ACK_TIMEOUT_FUNC[0]
13 ----------------------------PCIE3:LL_ACK_TIMEOUT_FUNC[1]PCIE3:LL_REPLAY_TIMEOUT_EN
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:LL_REPLAY_TIMEOUT[0]PCIE3:LL_REPLAY_TIMEOUT[1]
17 ----------------------------PCIE3:LL_REPLAY_TIMEOUT[2]PCIE3:LL_REPLAY_TIMEOUT[3]
18 ----------------------------PCIE3:LL_REPLAY_TIMEOUT[4]PCIE3:LL_REPLAY_TIMEOUT[5]
19 ----------------------------PCIE3:LL_REPLAY_TIMEOUT[6]PCIE3:LL_REPLAY_TIMEOUT[7]
20 ----------------------------PCIE3:LL_REPLAY_TIMEOUT[8]PCIE3:LL_REPLAY_TIMEOUT_FUNC[0]
21 ----------------------------PCIE3:LL_REPLAY_TIMEOUT_FUNC[1]PCIE3:LL_CPL_FC_UPDATE_TIMER_OVERRIDE
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[0]PCIE3:LL_CPL_FC_UPDATE_TIMER[1]
25 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[2]PCIE3:LL_CPL_FC_UPDATE_TIMER[3]
26 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[4]PCIE3:LL_CPL_FC_UPDATE_TIMER[5]
27 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[6]PCIE3:LL_CPL_FC_UPDATE_TIMER[7]
28 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[8]PCIE3:LL_CPL_FC_UPDATE_TIMER[9]
29 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[10]PCIE3:LL_CPL_FC_UPDATE_TIMER[11]
30 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[12]PCIE3:LL_CPL_FC_UPDATE_TIMER[13]
31 ----------------------------PCIE3:LL_CPL_FC_UPDATE_TIMER[14]PCIE3:LL_CPL_FC_UPDATE_TIMER[15]
32 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER_OVERRIDE-
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[0]PCIE3:LL_P_FC_UPDATE_TIMER[1]
41 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[2]PCIE3:LL_P_FC_UPDATE_TIMER[3]
42 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[4]PCIE3:LL_P_FC_UPDATE_TIMER[5]
43 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[6]PCIE3:LL_P_FC_UPDATE_TIMER[7]
44 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[8]PCIE3:LL_P_FC_UPDATE_TIMER[9]
45 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[10]PCIE3:LL_P_FC_UPDATE_TIMER[11]
46 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[12]PCIE3:LL_P_FC_UPDATE_TIMER[13]
47 ----------------------------PCIE3:LL_P_FC_UPDATE_TIMER[14]PCIE3:LL_P_FC_UPDATE_TIMER[15]
PCIE3 bittile 5
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE-
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[0]PCIE3:LL_NP_FC_UPDATE_TIMER[1]
9 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[2]PCIE3:LL_NP_FC_UPDATE_TIMER[3]
10 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[4]PCIE3:LL_NP_FC_UPDATE_TIMER[5]
11 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[6]PCIE3:LL_NP_FC_UPDATE_TIMER[7]
12 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[8]PCIE3:LL_NP_FC_UPDATE_TIMER[9]
13 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[10]PCIE3:LL_NP_FC_UPDATE_TIMER[11]
14 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[12]PCIE3:LL_NP_FC_UPDATE_TIMER[13]
15 ----------------------------PCIE3:LL_NP_FC_UPDATE_TIMER[14]PCIE3:LL_NP_FC_UPDATE_TIMER[15]
16 ----------------------------PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE-
17 ------------------------------
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[0]PCIE3:LL_FC_UPDATE_TIMER[1]
25 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[2]PCIE3:LL_FC_UPDATE_TIMER[3]
26 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[4]PCIE3:LL_FC_UPDATE_TIMER[5]
27 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[6]PCIE3:LL_FC_UPDATE_TIMER[7]
28 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[8]PCIE3:LL_FC_UPDATE_TIMER[9]
29 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[10]PCIE3:LL_FC_UPDATE_TIMER[11]
30 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[12]PCIE3:LL_FC_UPDATE_TIMER[13]
31 ----------------------------PCIE3:LL_FC_UPDATE_TIMER[14]PCIE3:LL_FC_UPDATE_TIMER[15]
32 -----------------------------PCIE3:TL_CREDITS_CD[0]
33 ----------------------------PCIE3:TL_CREDITS_CD[1]PCIE3:TL_CREDITS_CD[2]
34 ----------------------------PCIE3:TL_CREDITS_CD[3]PCIE3:TL_CREDITS_CD[4]
35 ----------------------------PCIE3:TL_CREDITS_CD[5]PCIE3:TL_CREDITS_CD[6]
36 ----------------------------PCIE3:TL_CREDITS_CD[7]PCIE3:TL_CREDITS_CD[8]
37 ----------------------------PCIE3:TL_CREDITS_CD[9]PCIE3:TL_CREDITS_CD[10]
38 ----------------------------PCIE3:TL_CREDITS_CD[11]-
39 ------------------------------
40 ----------------------------PCIE3:TL_CREDITS_CH[0]PCIE3:TL_CREDITS_CH[1]
41 ----------------------------PCIE3:TL_CREDITS_CH[2]PCIE3:TL_CREDITS_CH[3]
42 ----------------------------PCIE3:TL_CREDITS_CH[4]PCIE3:TL_CREDITS_CH[5]
43 ----------------------------PCIE3:TL_CREDITS_CH[6]PCIE3:TL_CREDITS_CH[7]
PCIE3 bittile 6
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:TL_CREDITS_NPD[0]PCIE3:TL_CREDITS_NPD[1]
1 ----------------------------PCIE3:TL_CREDITS_NPD[2]PCIE3:TL_CREDITS_NPD[3]
2 ----------------------------PCIE3:TL_CREDITS_NPD[4]PCIE3:TL_CREDITS_NPD[5]
3 ----------------------------PCIE3:TL_CREDITS_NPD[6]PCIE3:TL_CREDITS_NPD[7]
4 ----------------------------PCIE3:TL_CREDITS_NPD[8]PCIE3:TL_CREDITS_NPD[9]
5 ----------------------------PCIE3:TL_CREDITS_NPD[10]PCIE3:TL_CREDITS_NPD[11]
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:TL_CREDITS_NPH[0]PCIE3:TL_CREDITS_NPH[1]
9 ----------------------------PCIE3:TL_CREDITS_NPH[2]PCIE3:TL_CREDITS_NPH[3]
10 ----------------------------PCIE3:TL_CREDITS_NPH[4]PCIE3:TL_CREDITS_NPH[5]
11 ----------------------------PCIE3:TL_CREDITS_NPH[6]PCIE3:TL_CREDITS_NPH[7]
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:TL_CREDITS_PD[0]PCIE3:TL_CREDITS_PD[1]
17 ----------------------------PCIE3:TL_CREDITS_PD[2]PCIE3:TL_CREDITS_PD[3]
18 ----------------------------PCIE3:TL_CREDITS_PD[4]PCIE3:TL_CREDITS_PD[5]
19 ----------------------------PCIE3:TL_CREDITS_PD[6]PCIE3:TL_CREDITS_PD[7]
20 ----------------------------PCIE3:TL_CREDITS_PD[8]PCIE3:TL_CREDITS_PD[9]
21 ----------------------------PCIE3:TL_CREDITS_PD[10]PCIE3:TL_CREDITS_PD[11]
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:TL_CREDITS_PH[0]PCIE3:TL_CREDITS_PH[1]
25 ----------------------------PCIE3:TL_CREDITS_PH[2]PCIE3:TL_CREDITS_PH[3]
26 ----------------------------PCIE3:TL_CREDITS_PH[4]PCIE3:TL_CREDITS_PH[5]
27 ----------------------------PCIE3:TL_CREDITS_PH[6]PCIE3:TL_CREDITS_PH[7]
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[0]PCIE3:TL_COMPL_TIMEOUT_REG0[1]
33 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[2]PCIE3:TL_COMPL_TIMEOUT_REG0[3]
34 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[4]PCIE3:TL_COMPL_TIMEOUT_REG0[5]
35 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[6]PCIE3:TL_COMPL_TIMEOUT_REG0[7]
36 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[8]PCIE3:TL_COMPL_TIMEOUT_REG0[9]
37 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[10]PCIE3:TL_COMPL_TIMEOUT_REG0[11]
38 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[12]PCIE3:TL_COMPL_TIMEOUT_REG0[13]
39 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[14]PCIE3:TL_COMPL_TIMEOUT_REG0[15]
40 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[16]PCIE3:TL_COMPL_TIMEOUT_REG0[17]
41 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[18]PCIE3:TL_COMPL_TIMEOUT_REG0[19]
42 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[20]PCIE3:TL_COMPL_TIMEOUT_REG0[21]
43 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG0[22]PCIE3:TL_COMPL_TIMEOUT_REG0[23]
PCIE3 bittile 7
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[0]PCIE3:TL_COMPL_TIMEOUT_REG1[1]
1 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[2]PCIE3:TL_COMPL_TIMEOUT_REG1[3]
2 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[4]PCIE3:TL_COMPL_TIMEOUT_REG1[5]
3 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[6]PCIE3:TL_COMPL_TIMEOUT_REG1[7]
4 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[8]PCIE3:TL_COMPL_TIMEOUT_REG1[9]
5 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[10]PCIE3:TL_COMPL_TIMEOUT_REG1[11]
6 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[12]PCIE3:TL_COMPL_TIMEOUT_REG1[13]
7 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[14]PCIE3:TL_COMPL_TIMEOUT_REG1[15]
8 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[16]PCIE3:TL_COMPL_TIMEOUT_REG1[17]
9 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[18]PCIE3:TL_COMPL_TIMEOUT_REG1[19]
10 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[20]PCIE3:TL_COMPL_TIMEOUT_REG1[21]
11 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[22]PCIE3:TL_COMPL_TIMEOUT_REG1[23]
12 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[24]PCIE3:TL_COMPL_TIMEOUT_REG1[25]
13 ----------------------------PCIE3:TL_COMPL_TIMEOUT_REG1[26]PCIE3:TL_COMPL_TIMEOUT_REG1[27]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF0_DEVICE_ID[0]PCIE3:PF0_DEVICE_ID[1]
17 ----------------------------PCIE3:PF0_DEVICE_ID[2]PCIE3:PF0_DEVICE_ID[3]
18 ----------------------------PCIE3:PF0_DEVICE_ID[4]PCIE3:PF0_DEVICE_ID[5]
19 ----------------------------PCIE3:PF0_DEVICE_ID[6]PCIE3:PF0_DEVICE_ID[7]
20 ----------------------------PCIE3:PF0_DEVICE_ID[8]PCIE3:PF0_DEVICE_ID[9]
21 ----------------------------PCIE3:PF0_DEVICE_ID[10]PCIE3:PF0_DEVICE_ID[11]
22 ----------------------------PCIE3:PF0_DEVICE_ID[12]PCIE3:PF0_DEVICE_ID[13]
23 ----------------------------PCIE3:PF0_DEVICE_ID[14]PCIE3:PF0_DEVICE_ID[15]
24 ----------------------------PCIE3:PF1_DEVICE_ID[0]PCIE3:PF1_DEVICE_ID[1]
25 ----------------------------PCIE3:PF1_DEVICE_ID[2]PCIE3:PF1_DEVICE_ID[3]
26 ----------------------------PCIE3:PF1_DEVICE_ID[4]PCIE3:PF1_DEVICE_ID[5]
27 ----------------------------PCIE3:PF1_DEVICE_ID[6]PCIE3:PF1_DEVICE_ID[7]
28 ----------------------------PCIE3:PF1_DEVICE_ID[8]PCIE3:PF1_DEVICE_ID[9]
29 ----------------------------PCIE3:PF1_DEVICE_ID[10]PCIE3:PF1_DEVICE_ID[11]
30 ----------------------------PCIE3:PF1_DEVICE_ID[12]PCIE3:PF1_DEVICE_ID[13]
31 ----------------------------PCIE3:PF1_DEVICE_ID[14]PCIE3:PF1_DEVICE_ID[15]
32 ----------------------------PCIE3:PF0_REVISION_ID[0]PCIE3:PF0_REVISION_ID[1]
33 ----------------------------PCIE3:PF0_REVISION_ID[2]PCIE3:PF0_REVISION_ID[3]
34 ----------------------------PCIE3:PF0_REVISION_ID[4]PCIE3:PF0_REVISION_ID[5]
35 ----------------------------PCIE3:PF0_REVISION_ID[6]PCIE3:PF0_REVISION_ID[7]
36 ----------------------------PCIE3:PF1_REVISION_ID[0]PCIE3:PF1_REVISION_ID[1]
37 ----------------------------PCIE3:PF1_REVISION_ID[2]PCIE3:PF1_REVISION_ID[3]
38 ----------------------------PCIE3:PF1_REVISION_ID[4]PCIE3:PF1_REVISION_ID[5]
39 ----------------------------PCIE3:PF1_REVISION_ID[6]PCIE3:PF1_REVISION_ID[7]
40 ----------------------------PCIE3:PF0_CLASS_CODE[0]PCIE3:PF0_CLASS_CODE[1]
41 ----------------------------PCIE3:PF0_CLASS_CODE[2]PCIE3:PF0_CLASS_CODE[3]
42 ----------------------------PCIE3:PF0_CLASS_CODE[4]PCIE3:PF0_CLASS_CODE[5]
43 ----------------------------PCIE3:PF0_CLASS_CODE[6]PCIE3:PF0_CLASS_CODE[7]
44 ----------------------------PCIE3:PF0_CLASS_CODE[8]PCIE3:PF0_CLASS_CODE[9]
45 ----------------------------PCIE3:PF0_CLASS_CODE[10]PCIE3:PF0_CLASS_CODE[11]
46 ----------------------------PCIE3:PF0_CLASS_CODE[12]PCIE3:PF0_CLASS_CODE[13]
47 ----------------------------PCIE3:PF0_CLASS_CODE[14]PCIE3:PF0_CLASS_CODE[15]
PCIE3 bittile 8
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_CLASS_CODE[16]PCIE3:PF0_CLASS_CODE[17]
1 ----------------------------PCIE3:PF0_CLASS_CODE[18]PCIE3:PF0_CLASS_CODE[19]
2 ----------------------------PCIE3:PF0_CLASS_CODE[20]PCIE3:PF0_CLASS_CODE[21]
3 ----------------------------PCIE3:PF0_CLASS_CODE[22]PCIE3:PF0_CLASS_CODE[23]
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF1_CLASS_CODE[0]PCIE3:PF1_CLASS_CODE[1]
9 ----------------------------PCIE3:PF1_CLASS_CODE[2]PCIE3:PF1_CLASS_CODE[3]
10 ----------------------------PCIE3:PF1_CLASS_CODE[4]PCIE3:PF1_CLASS_CODE[5]
11 ----------------------------PCIE3:PF1_CLASS_CODE[6]PCIE3:PF1_CLASS_CODE[7]
12 ----------------------------PCIE3:PF1_CLASS_CODE[8]PCIE3:PF1_CLASS_CODE[9]
13 ----------------------------PCIE3:PF1_CLASS_CODE[10]PCIE3:PF1_CLASS_CODE[11]
14 ----------------------------PCIE3:PF1_CLASS_CODE[12]PCIE3:PF1_CLASS_CODE[13]
15 ----------------------------PCIE3:PF1_CLASS_CODE[14]PCIE3:PF1_CLASS_CODE[15]
16 ----------------------------PCIE3:PF1_CLASS_CODE[16]PCIE3:PF1_CLASS_CODE[17]
17 ----------------------------PCIE3:PF1_CLASS_CODE[18]PCIE3:PF1_CLASS_CODE[19]
18 ----------------------------PCIE3:PF1_CLASS_CODE[20]PCIE3:PF1_CLASS_CODE[21]
19 ----------------------------PCIE3:PF1_CLASS_CODE[22]PCIE3:PF1_CLASS_CODE[23]
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[0]PCIE3:PF0_SUBSYSTEM_ID[1]
25 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[2]PCIE3:PF0_SUBSYSTEM_ID[3]
26 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[4]PCIE3:PF0_SUBSYSTEM_ID[5]
27 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[6]PCIE3:PF0_SUBSYSTEM_ID[7]
28 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[8]PCIE3:PF0_SUBSYSTEM_ID[9]
29 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[10]PCIE3:PF0_SUBSYSTEM_ID[11]
30 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[12]PCIE3:PF0_SUBSYSTEM_ID[13]
31 ----------------------------PCIE3:PF0_SUBSYSTEM_ID[14]PCIE3:PF0_SUBSYSTEM_ID[15]
32 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[0]PCIE3:PF1_SUBSYSTEM_ID[1]
33 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[2]PCIE3:PF1_SUBSYSTEM_ID[3]
34 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[4]PCIE3:PF1_SUBSYSTEM_ID[5]
35 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[6]PCIE3:PF1_SUBSYSTEM_ID[7]
36 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[8]PCIE3:PF1_SUBSYSTEM_ID[9]
37 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[10]PCIE3:PF1_SUBSYSTEM_ID[11]
38 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[12]PCIE3:PF1_SUBSYSTEM_ID[13]
39 ----------------------------PCIE3:PF1_SUBSYSTEM_ID[14]PCIE3:PF1_SUBSYSTEM_ID[15]
40 ----------------------------PCIE3:PF0_INTERRUPT_PIN[0]PCIE3:PF0_INTERRUPT_PIN[1]
41 ----------------------------PCIE3:PF0_INTERRUPT_PIN[2]PCIE3:PF1_INTERRUPT_PIN[0]
42 ----------------------------PCIE3:PF1_INTERRUPT_PIN[1]PCIE3:PF1_INTERRUPT_PIN[2]
43 ----------------------------PCIE3:PF0_INTERRUPT_LINE[0]PCIE3:PF0_INTERRUPT_LINE[1]
44 ----------------------------PCIE3:PF0_INTERRUPT_LINE[2]PCIE3:PF0_INTERRUPT_LINE[3]
45 ----------------------------PCIE3:PF0_INTERRUPT_LINE[4]PCIE3:PF0_INTERRUPT_LINE[5]
46 ----------------------------PCIE3:PF0_INTERRUPT_LINE[6]PCIE3:PF0_INTERRUPT_LINE[7]
PCIE3 bittile 9
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_INTERRUPT_LINE[0]PCIE3:PF1_INTERRUPT_LINE[1]
1 ----------------------------PCIE3:PF1_INTERRUPT_LINE[2]PCIE3:PF1_INTERRUPT_LINE[3]
2 ----------------------------PCIE3:PF1_INTERRUPT_LINE[4]PCIE3:PF1_INTERRUPT_LINE[5]
3 ----------------------------PCIE3:PF1_INTERRUPT_LINE[6]PCIE3:PF1_INTERRUPT_LINE[7]
4 ----------------------------PCIE3:PF0_BIST_REGISTER[0]PCIE3:PF0_BIST_REGISTER[1]
5 ----------------------------PCIE3:PF0_BIST_REGISTER[2]PCIE3:PF0_BIST_REGISTER[3]
6 ----------------------------PCIE3:PF0_BIST_REGISTER[4]PCIE3:PF0_BIST_REGISTER[5]
7 ----------------------------PCIE3:PF0_BIST_REGISTER[6]PCIE3:PF0_BIST_REGISTER[7]
8 ----------------------------PCIE3:PF1_BIST_REGISTER[0]PCIE3:PF1_BIST_REGISTER[1]
9 ----------------------------PCIE3:PF1_BIST_REGISTER[2]PCIE3:PF1_BIST_REGISTER[3]
10 ----------------------------PCIE3:PF1_BIST_REGISTER[4]PCIE3:PF1_BIST_REGISTER[5]
11 ----------------------------PCIE3:PF1_BIST_REGISTER[6]PCIE3:PF1_BIST_REGISTER[7]
12 ----------------------------PCIE3:PF0_CAPABILITY_POINTER[0]PCIE3:PF0_CAPABILITY_POINTER[1]
13 ----------------------------PCIE3:PF0_CAPABILITY_POINTER[2]PCIE3:PF0_CAPABILITY_POINTER[3]
14 ----------------------------PCIE3:PF0_CAPABILITY_POINTER[4]PCIE3:PF0_CAPABILITY_POINTER[5]
15 ----------------------------PCIE3:PF0_CAPABILITY_POINTER[6]PCIE3:PF0_CAPABILITY_POINTER[7]
16 ----------------------------PCIE3:PF1_CAPABILITY_POINTER[0]PCIE3:PF1_CAPABILITY_POINTER[1]
17 ----------------------------PCIE3:PF1_CAPABILITY_POINTER[2]PCIE3:PF1_CAPABILITY_POINTER[3]
18 ----------------------------PCIE3:PF1_CAPABILITY_POINTER[4]PCIE3:PF1_CAPABILITY_POINTER[5]
19 ----------------------------PCIE3:PF1_CAPABILITY_POINTER[6]PCIE3:PF1_CAPABILITY_POINTER[7]
20 ----------------------------PCIE3:VF0_CAPABILITY_POINTER[0]PCIE3:VF0_CAPABILITY_POINTER[1]
21 ----------------------------PCIE3:VF0_CAPABILITY_POINTER[2]PCIE3:VF0_CAPABILITY_POINTER[3]
22 ----------------------------PCIE3:VF0_CAPABILITY_POINTER[4]PCIE3:VF0_CAPABILITY_POINTER[5]
23 ----------------------------PCIE3:VF0_CAPABILITY_POINTER[6]PCIE3:VF0_CAPABILITY_POINTER[7]
24 ----------------------------PCIE3:PF0_BAR0_CONTROL[0]PCIE3:PF0_BAR0_CONTROL[1]
25 ----------------------------PCIE3:PF0_BAR0_CONTROL[2]PCIE3:PF1_BAR0_CONTROL[0]
26 ----------------------------PCIE3:PF1_BAR0_CONTROL[1]PCIE3:PF1_BAR0_CONTROL[2]
27 ----------------------------PCIE3:PF0_BAR0_APERTURE_SIZE[0]PCIE3:PF0_BAR0_APERTURE_SIZE[1]
28 ----------------------------PCIE3:PF0_BAR0_APERTURE_SIZE[2]PCIE3:PF0_BAR0_APERTURE_SIZE[3]
29 ----------------------------PCIE3:PF0_BAR0_APERTURE_SIZE[4]PCIE3:PF1_BAR0_APERTURE_SIZE[0]
30 ----------------------------PCIE3:PF1_BAR0_APERTURE_SIZE[1]PCIE3:PF1_BAR0_APERTURE_SIZE[2]
31 ----------------------------PCIE3:PF1_BAR0_APERTURE_SIZE[3]PCIE3:PF1_BAR0_APERTURE_SIZE[4]
32 ----------------------------PCIE3:PF0_BAR1_CONTROL[0]PCIE3:PF0_BAR1_CONTROL[1]
33 ----------------------------PCIE3:PF0_BAR1_CONTROL[2]PCIE3:PF1_BAR1_CONTROL[0]
34 ----------------------------PCIE3:PF1_BAR1_CONTROL[1]PCIE3:PF1_BAR1_CONTROL[2]
35 ----------------------------PCIE3:PF0_BAR1_APERTURE_SIZE[0]PCIE3:PF0_BAR1_APERTURE_SIZE[1]
36 ----------------------------PCIE3:PF0_BAR1_APERTURE_SIZE[2]PCIE3:PF0_BAR1_APERTURE_SIZE[3]
37 ----------------------------PCIE3:PF0_BAR1_APERTURE_SIZE[4]PCIE3:PF1_BAR1_APERTURE_SIZE[0]
38 ----------------------------PCIE3:PF1_BAR1_APERTURE_SIZE[1]PCIE3:PF1_BAR1_APERTURE_SIZE[2]
39 ----------------------------PCIE3:PF1_BAR1_APERTURE_SIZE[3]PCIE3:PF1_BAR1_APERTURE_SIZE[4]
40 ----------------------------PCIE3:PF0_BAR2_CONTROL[0]PCIE3:PF0_BAR2_CONTROL[1]
41 ----------------------------PCIE3:PF0_BAR2_CONTROL[2]PCIE3:PF1_BAR2_CONTROL[0]
42 ----------------------------PCIE3:PF1_BAR2_CONTROL[1]PCIE3:PF1_BAR2_CONTROL[2]
43 ----------------------------PCIE3:PF0_BAR2_APERTURE_SIZE[0]PCIE3:PF0_BAR2_APERTURE_SIZE[1]
44 ----------------------------PCIE3:PF0_BAR2_APERTURE_SIZE[2]PCIE3:PF0_BAR2_APERTURE_SIZE[3]
45 ----------------------------PCIE3:PF0_BAR2_APERTURE_SIZE[4]PCIE3:PF1_BAR2_APERTURE_SIZE[0]
46 ----------------------------PCIE3:PF1_BAR2_APERTURE_SIZE[1]PCIE3:PF1_BAR2_APERTURE_SIZE[2]
47 ----------------------------PCIE3:PF1_BAR2_APERTURE_SIZE[3]PCIE3:PF1_BAR2_APERTURE_SIZE[4]
PCIE3 bittile 10
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_BAR3_CONTROL[0]PCIE3:PF0_BAR3_CONTROL[1]
1 ----------------------------PCIE3:PF0_BAR3_CONTROL[2]PCIE3:PF1_BAR3_CONTROL[0]
2 ----------------------------PCIE3:PF1_BAR3_CONTROL[1]PCIE3:PF1_BAR3_CONTROL[2]
3 ----------------------------PCIE3:PF0_BAR3_APERTURE_SIZE[0]PCIE3:PF0_BAR3_APERTURE_SIZE[1]
4 ----------------------------PCIE3:PF0_BAR3_APERTURE_SIZE[2]PCIE3:PF0_BAR3_APERTURE_SIZE[3]
5 ----------------------------PCIE3:PF0_BAR3_APERTURE_SIZE[4]PCIE3:PF1_BAR3_APERTURE_SIZE[0]
6 ----------------------------PCIE3:PF1_BAR3_APERTURE_SIZE[1]PCIE3:PF1_BAR3_APERTURE_SIZE[2]
7 ----------------------------PCIE3:PF1_BAR3_APERTURE_SIZE[3]PCIE3:PF1_BAR3_APERTURE_SIZE[4]
8 ----------------------------PCIE3:PF0_BAR4_CONTROL[0]PCIE3:PF0_BAR4_CONTROL[1]
9 ----------------------------PCIE3:PF0_BAR4_CONTROL[2]PCIE3:PF1_BAR4_CONTROL[0]
10 ----------------------------PCIE3:PF1_BAR4_CONTROL[1]PCIE3:PF1_BAR4_CONTROL[2]
11 ----------------------------PCIE3:PF0_BAR4_APERTURE_SIZE[0]PCIE3:PF0_BAR4_APERTURE_SIZE[1]
12 ----------------------------PCIE3:PF0_BAR4_APERTURE_SIZE[2]PCIE3:PF0_BAR4_APERTURE_SIZE[3]
13 ----------------------------PCIE3:PF0_BAR4_APERTURE_SIZE[4]PCIE3:PF1_BAR4_APERTURE_SIZE[0]
14 ----------------------------PCIE3:PF1_BAR4_APERTURE_SIZE[1]PCIE3:PF1_BAR4_APERTURE_SIZE[2]
15 ----------------------------PCIE3:PF1_BAR4_APERTURE_SIZE[3]PCIE3:PF1_BAR4_APERTURE_SIZE[4]
16 ----------------------------PCIE3:PF0_BAR5_CONTROL[0]PCIE3:PF0_BAR5_CONTROL[1]
17 ----------------------------PCIE3:PF0_BAR5_CONTROL[2]PCIE3:PF1_BAR5_CONTROL[0]
18 ----------------------------PCIE3:PF1_BAR5_CONTROL[1]PCIE3:PF1_BAR5_CONTROL[2]
19 ----------------------------PCIE3:PF0_BAR5_APERTURE_SIZE[0]PCIE3:PF0_BAR5_APERTURE_SIZE[1]
20 ----------------------------PCIE3:PF0_BAR5_APERTURE_SIZE[2]PCIE3:PF0_BAR5_APERTURE_SIZE[3]
21 ----------------------------PCIE3:PF0_BAR5_APERTURE_SIZE[4]PCIE3:PF1_BAR5_APERTURE_SIZE[0]
22 ----------------------------PCIE3:PF1_BAR5_APERTURE_SIZE[1]PCIE3:PF1_BAR5_APERTURE_SIZE[2]
23 ----------------------------PCIE3:PF1_BAR5_APERTURE_SIZE[3]PCIE3:PF1_BAR5_APERTURE_SIZE[4]
24 ------------------------------
25 ----------------------------PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[0]PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[1]
26 ----------------------------PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[2]PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[3]
27 ----------------------------PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[4]PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[0]
28 ----------------------------PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[1]PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[2]
29 ----------------------------PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[3]PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[4]
30 ----------------------------PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[0]PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[1]
31 ----------------------------PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[2]-
32 ----------------------------PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[0]PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[1]
33 ----------------------------PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[2]-
34 ----------------------------PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[0]PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[1]
35 ----------------------------PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[2]PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[0]
36 ----------------------------PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[1]PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[2]
PCIE3 bittile 11
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ----------------------------PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[0]PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[1]
15 ------------------------------
16 ----------------------------PCIE3:PF0_MSI_CAP_NEXTPTR[0]PCIE3:PF0_MSI_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:PF0_MSI_CAP_NEXTPTR[2]PCIE3:PF0_MSI_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:PF0_MSI_CAP_NEXTPTR[4]PCIE3:PF0_MSI_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:PF0_MSI_CAP_NEXTPTR[6]PCIE3:PF0_MSI_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:PF1_MSI_CAP_NEXTPTR[0]PCIE3:PF1_MSI_CAP_NEXTPTR[1]
21 ----------------------------PCIE3:PF1_MSI_CAP_NEXTPTR[2]PCIE3:PF1_MSI_CAP_NEXTPTR[3]
22 ----------------------------PCIE3:PF1_MSI_CAP_NEXTPTR[4]PCIE3:PF1_MSI_CAP_NEXTPTR[5]
23 ----------------------------PCIE3:PF1_MSI_CAP_NEXTPTR[6]PCIE3:PF1_MSI_CAP_NEXTPTR[7]
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ------------------------------
33 ------------------------------
34 ------------------------------
35 ------------------------------
36 ------------------------------
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:PF0_MSIX_CAP_NEXTPTR[0]PCIE3:PF0_MSIX_CAP_NEXTPTR[1]
41 ----------------------------PCIE3:PF0_MSIX_CAP_NEXTPTR[2]PCIE3:PF0_MSIX_CAP_NEXTPTR[3]
42 ----------------------------PCIE3:PF0_MSIX_CAP_NEXTPTR[4]PCIE3:PF0_MSIX_CAP_NEXTPTR[5]
43 ----------------------------PCIE3:PF0_MSIX_CAP_NEXTPTR[6]PCIE3:PF0_MSIX_CAP_NEXTPTR[7]
44 ----------------------------PCIE3:PF1_MSIX_CAP_NEXTPTR[0]PCIE3:PF1_MSIX_CAP_NEXTPTR[1]
45 ----------------------------PCIE3:PF1_MSIX_CAP_NEXTPTR[2]PCIE3:PF1_MSIX_CAP_NEXTPTR[3]
46 ----------------------------PCIE3:PF1_MSIX_CAP_NEXTPTR[4]PCIE3:PF1_MSIX_CAP_NEXTPTR[5]
47 ----------------------------PCIE3:PF1_MSIX_CAP_NEXTPTR[6]PCIE3:PF1_MSIX_CAP_NEXTPTR[7]
PCIE3 bittile 12
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[0]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[1]
17 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[2]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[3]
18 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[4]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[5]
19 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[6]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[7]
20 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[8]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[9]
21 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[10]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[11]
22 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[12]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[13]
23 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[14]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[15]
24 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[16]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[17]
25 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[18]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[19]
26 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[20]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[21]
27 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[22]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[23]
28 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[24]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[25]
29 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[26]PCIE3:PF0_MSIX_CAP_PBA_OFFSET[27]
30 ----------------------------PCIE3:PF0_MSIX_CAP_PBA_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[0]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[1]
33 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[2]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[3]
34 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[4]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[5]
35 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[6]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[7]
36 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[8]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[9]
37 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[10]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[11]
38 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[12]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[13]
39 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[14]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[15]
40 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[16]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[17]
41 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[18]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[19]
42 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[20]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[21]
43 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[22]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[23]
44 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[24]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[25]
45 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[26]PCIE3:PF1_MSIX_CAP_PBA_OFFSET[27]
46 ----------------------------PCIE3:PF1_MSIX_CAP_PBA_OFFSET[28]-
PCIE3 bittile 13
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[1]
1 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[3]
2 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[5]
3 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[7]
4 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[9]
5 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[11]
6 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[13]
7 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[15]
8 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[17]
9 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[19]
10 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[21]
11 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[23]
12 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[25]
13 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF0_MSIX_CAP_PBA_OFFSET[27]
14 ----------------------------PCIE3:VF0_MSIX_CAP_PBA_OFFSET[28]-
15 ------------------------------
16 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[1]
17 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[3]
18 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[5]
19 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[7]
20 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[9]
21 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[11]
22 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[13]
23 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[15]
24 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[17]
25 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[19]
26 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[21]
27 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[23]
28 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[25]
29 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF1_MSIX_CAP_PBA_OFFSET[27]
30 ----------------------------PCIE3:VF1_MSIX_CAP_PBA_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[1]
33 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[3]
34 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[5]
35 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[7]
36 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[9]
37 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[11]
38 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[13]
39 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[15]
40 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[17]
41 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[19]
42 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[21]
43 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[23]
44 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[25]
45 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF2_MSIX_CAP_PBA_OFFSET[27]
46 ----------------------------PCIE3:VF2_MSIX_CAP_PBA_OFFSET[28]-
PCIE3 bittile 14
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[1]
1 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[3]
2 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[5]
3 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[7]
4 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[9]
5 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[11]
6 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[13]
7 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[15]
8 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[17]
9 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[19]
10 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[21]
11 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[23]
12 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[25]
13 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF3_MSIX_CAP_PBA_OFFSET[27]
14 ----------------------------PCIE3:VF3_MSIX_CAP_PBA_OFFSET[28]-
15 ------------------------------
16 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[1]
17 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[3]
18 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[5]
19 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[7]
20 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[9]
21 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[11]
22 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[13]
23 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[15]
24 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[17]
25 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[19]
26 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[21]
27 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[23]
28 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[25]
29 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF4_MSIX_CAP_PBA_OFFSET[27]
30 ----------------------------PCIE3:VF4_MSIX_CAP_PBA_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[0]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[1]
33 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[2]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[3]
34 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[4]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[5]
35 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[6]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[7]
36 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[8]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[9]
37 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[10]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[11]
38 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[12]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[13]
39 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[14]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[15]
40 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[16]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[17]
41 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[18]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[19]
42 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[20]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[21]
43 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[22]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[23]
44 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[24]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[25]
45 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[26]PCIE3:VF5_MSIX_CAP_PBA_OFFSET[27]
46 ----------------------------PCIE3:VF5_MSIX_CAP_PBA_OFFSET[28]-
PCIE3 bittile 15
RowColumn
01234567891011121314151617181920212223242526272829
0 ------------------------------
1 ------------------------------
2 ------------------------------
3 ------------------------------
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ------------------------------
9 ------------------------------
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[0]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[1]
17 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[2]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[3]
18 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[4]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[5]
19 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[6]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[7]
20 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[8]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[9]
21 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[10]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[11]
22 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[12]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[13]
23 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[14]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[15]
24 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[16]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[17]
25 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[18]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[19]
26 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[20]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[21]
27 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[22]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[23]
28 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[24]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[25]
29 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[26]PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[27]
30 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[0]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[1]
33 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[2]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[3]
34 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[4]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[5]
35 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[6]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[7]
36 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[8]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[9]
37 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[10]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[11]
38 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[12]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[13]
39 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[14]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[15]
40 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[16]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[17]
41 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[18]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[19]
42 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[20]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[21]
43 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[22]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[23]
44 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[24]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[25]
45 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[26]PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[27]
46 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[28]-
PCIE3 bittile 16
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[1]
1 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[3]
2 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[5]
3 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[7]
4 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[9]
5 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[11]
6 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[13]
7 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[15]
8 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[17]
9 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[19]
10 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[21]
11 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[23]
12 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[25]
13 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[27]
14 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[28]-
15 ------------------------------
16 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[1]
17 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[3]
18 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[5]
19 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[7]
20 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[9]
21 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[11]
22 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[13]
23 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[15]
24 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[17]
25 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[19]
26 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[21]
27 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[23]
28 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[25]
29 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[27]
30 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[1]
33 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[3]
34 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[5]
35 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[7]
36 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[9]
37 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[11]
38 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[13]
39 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[15]
40 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[17]
41 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[19]
42 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[21]
43 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[23]
44 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[25]
45 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[27]
46 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[28]-
PCIE3 bittile 17
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[1]
1 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[3]
2 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[5]
3 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[7]
4 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[9]
5 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[11]
6 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[13]
7 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[15]
8 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[17]
9 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[19]
10 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[21]
11 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[23]
12 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[25]
13 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[27]
14 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[28]-
15 ------------------------------
16 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[1]
17 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[3]
18 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[5]
19 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[7]
20 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[9]
21 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[11]
22 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[13]
23 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[15]
24 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[17]
25 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[19]
26 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[21]
27 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[23]
28 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[25]
29 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[27]
30 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[28]-
31 ------------------------------
32 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[0]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[1]
33 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[2]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[3]
34 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[4]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[5]
35 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[6]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[7]
36 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[8]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[9]
37 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[10]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[11]
38 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[12]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[13]
39 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[14]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[15]
40 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[16]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[17]
41 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[18]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[19]
42 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[20]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[21]
43 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[22]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[23]
44 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[24]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[25]
45 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[26]PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[27]
46 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[28]-
PCIE3 bittile 18
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[0]PCIE3:PF0_MSIX_CAP_TABLE_SIZE[1]
1 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[2]PCIE3:PF0_MSIX_CAP_TABLE_SIZE[3]
2 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[4]PCIE3:PF0_MSIX_CAP_TABLE_SIZE[5]
3 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[6]PCIE3:PF0_MSIX_CAP_TABLE_SIZE[7]
4 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[8]PCIE3:PF0_MSIX_CAP_TABLE_SIZE[9]
5 ----------------------------PCIE3:PF0_MSIX_CAP_TABLE_SIZE[10]-
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[0]PCIE3:PF1_MSIX_CAP_TABLE_SIZE[1]
9 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[2]PCIE3:PF1_MSIX_CAP_TABLE_SIZE[3]
10 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[4]PCIE3:PF1_MSIX_CAP_TABLE_SIZE[5]
11 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[6]PCIE3:PF1_MSIX_CAP_TABLE_SIZE[7]
12 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[8]PCIE3:PF1_MSIX_CAP_TABLE_SIZE[9]
13 ----------------------------PCIE3:PF1_MSIX_CAP_TABLE_SIZE[10]-
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF0_MSIX_CAP_TABLE_SIZE[1]
17 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF0_MSIX_CAP_TABLE_SIZE[3]
18 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF0_MSIX_CAP_TABLE_SIZE[5]
19 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF0_MSIX_CAP_TABLE_SIZE[7]
20 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF0_MSIX_CAP_TABLE_SIZE[9]
21 ----------------------------PCIE3:VF0_MSIX_CAP_TABLE_SIZE[10]-
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF1_MSIX_CAP_TABLE_SIZE[1]
25 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF1_MSIX_CAP_TABLE_SIZE[3]
26 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF1_MSIX_CAP_TABLE_SIZE[5]
27 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF1_MSIX_CAP_TABLE_SIZE[7]
28 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF1_MSIX_CAP_TABLE_SIZE[9]
29 ----------------------------PCIE3:VF1_MSIX_CAP_TABLE_SIZE[10]-
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF2_MSIX_CAP_TABLE_SIZE[1]
33 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF2_MSIX_CAP_TABLE_SIZE[3]
34 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF2_MSIX_CAP_TABLE_SIZE[5]
35 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF2_MSIX_CAP_TABLE_SIZE[7]
36 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF2_MSIX_CAP_TABLE_SIZE[9]
37 ----------------------------PCIE3:VF2_MSIX_CAP_TABLE_SIZE[10]-
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF3_MSIX_CAP_TABLE_SIZE[1]
41 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF3_MSIX_CAP_TABLE_SIZE[3]
42 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF3_MSIX_CAP_TABLE_SIZE[5]
43 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF3_MSIX_CAP_TABLE_SIZE[7]
44 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF3_MSIX_CAP_TABLE_SIZE[9]
45 ----------------------------PCIE3:VF3_MSIX_CAP_TABLE_SIZE[10]-
PCIE3 bittile 19
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF4_MSIX_CAP_TABLE_SIZE[1]
1 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF4_MSIX_CAP_TABLE_SIZE[3]
2 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF4_MSIX_CAP_TABLE_SIZE[5]
3 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF4_MSIX_CAP_TABLE_SIZE[7]
4 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF4_MSIX_CAP_TABLE_SIZE[9]
5 ----------------------------PCIE3:VF4_MSIX_CAP_TABLE_SIZE[10]-
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[0]PCIE3:VF5_MSIX_CAP_TABLE_SIZE[1]
9 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[2]PCIE3:VF5_MSIX_CAP_TABLE_SIZE[3]
10 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[4]PCIE3:VF5_MSIX_CAP_TABLE_SIZE[5]
11 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[6]PCIE3:VF5_MSIX_CAP_TABLE_SIZE[7]
12 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[8]PCIE3:VF5_MSIX_CAP_TABLE_SIZE[9]
13 ----------------------------PCIE3:VF5_MSIX_CAP_TABLE_SIZE[10]-
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF0_PM_CAP_ID[0]PCIE3:PF0_PM_CAP_ID[1]
17 ----------------------------PCIE3:PF0_PM_CAP_ID[2]PCIE3:PF0_PM_CAP_ID[3]
18 ----------------------------PCIE3:PF0_PM_CAP_ID[4]PCIE3:PF0_PM_CAP_ID[5]
19 ----------------------------PCIE3:PF0_PM_CAP_ID[6]PCIE3:PF0_PM_CAP_ID[7]
20 ----------------------------PCIE3:PF1_PM_CAP_ID[0]PCIE3:PF1_PM_CAP_ID[1]
21 ----------------------------PCIE3:PF1_PM_CAP_ID[2]PCIE3:PF1_PM_CAP_ID[3]
22 ----------------------------PCIE3:PF1_PM_CAP_ID[4]PCIE3:PF1_PM_CAP_ID[5]
23 ----------------------------PCIE3:PF1_PM_CAP_ID[6]PCIE3:PF1_PM_CAP_ID[7]
24 ----------------------------PCIE3:VF0_PM_CAP_ID[0]PCIE3:VF0_PM_CAP_ID[1]
25 ----------------------------PCIE3:VF0_PM_CAP_ID[2]PCIE3:VF0_PM_CAP_ID[3]
26 ----------------------------PCIE3:VF0_PM_CAP_ID[4]PCIE3:VF0_PM_CAP_ID[5]
27 ----------------------------PCIE3:VF0_PM_CAP_ID[6]PCIE3:VF0_PM_CAP_ID[7]
28 ----------------------------PCIE3:VF1_PM_CAP_ID[0]PCIE3:VF1_PM_CAP_ID[1]
29 ----------------------------PCIE3:VF1_PM_CAP_ID[2]PCIE3:VF1_PM_CAP_ID[3]
30 ----------------------------PCIE3:VF1_PM_CAP_ID[4]PCIE3:VF1_PM_CAP_ID[5]
31 ----------------------------PCIE3:VF1_PM_CAP_ID[6]PCIE3:VF1_PM_CAP_ID[7]
32 ----------------------------PCIE3:VF2_PM_CAP_ID[0]PCIE3:VF2_PM_CAP_ID[1]
33 ----------------------------PCIE3:VF2_PM_CAP_ID[2]PCIE3:VF2_PM_CAP_ID[3]
34 ----------------------------PCIE3:VF2_PM_CAP_ID[4]PCIE3:VF2_PM_CAP_ID[5]
35 ----------------------------PCIE3:VF2_PM_CAP_ID[6]PCIE3:VF2_PM_CAP_ID[7]
36 ----------------------------PCIE3:VF3_PM_CAP_ID[0]PCIE3:VF3_PM_CAP_ID[1]
37 ----------------------------PCIE3:VF3_PM_CAP_ID[2]PCIE3:VF3_PM_CAP_ID[3]
38 ----------------------------PCIE3:VF3_PM_CAP_ID[4]PCIE3:VF3_PM_CAP_ID[5]
39 ----------------------------PCIE3:VF3_PM_CAP_ID[6]PCIE3:VF3_PM_CAP_ID[7]
40 ----------------------------PCIE3:VF4_PM_CAP_ID[0]PCIE3:VF4_PM_CAP_ID[1]
41 ----------------------------PCIE3:VF4_PM_CAP_ID[2]PCIE3:VF4_PM_CAP_ID[3]
42 ----------------------------PCIE3:VF4_PM_CAP_ID[4]PCIE3:VF4_PM_CAP_ID[5]
43 ----------------------------PCIE3:VF4_PM_CAP_ID[6]PCIE3:VF4_PM_CAP_ID[7]
44 ----------------------------PCIE3:VF5_PM_CAP_ID[0]PCIE3:VF5_PM_CAP_ID[1]
45 ----------------------------PCIE3:VF5_PM_CAP_ID[2]PCIE3:VF5_PM_CAP_ID[3]
46 ----------------------------PCIE3:VF5_PM_CAP_ID[4]PCIE3:VF5_PM_CAP_ID[5]
47 ----------------------------PCIE3:VF5_PM_CAP_ID[6]PCIE3:VF5_PM_CAP_ID[7]
PCIE3 bittile 20
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_PM_CAP_NEXTPTR[0]PCIE3:PF0_PM_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:PF0_PM_CAP_NEXTPTR[2]PCIE3:PF0_PM_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:PF0_PM_CAP_NEXTPTR[4]PCIE3:PF0_PM_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:PF0_PM_CAP_NEXTPTR[6]PCIE3:PF0_PM_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:PF1_PM_CAP_NEXTPTR[0]PCIE3:PF1_PM_CAP_NEXTPTR[1]
5 ----------------------------PCIE3:PF1_PM_CAP_NEXTPTR[2]PCIE3:PF1_PM_CAP_NEXTPTR[3]
6 ----------------------------PCIE3:PF1_PM_CAP_NEXTPTR[4]PCIE3:PF1_PM_CAP_NEXTPTR[5]
7 ----------------------------PCIE3:PF1_PM_CAP_NEXTPTR[6]PCIE3:PF1_PM_CAP_NEXTPTR[7]
8 ----------------------------PCIE3:VF0_PM_CAP_NEXTPTR[0]PCIE3:VF0_PM_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:VF0_PM_CAP_NEXTPTR[2]PCIE3:VF0_PM_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:VF0_PM_CAP_NEXTPTR[4]PCIE3:VF0_PM_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:VF0_PM_CAP_NEXTPTR[6]PCIE3:VF0_PM_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:VF1_PM_CAP_NEXTPTR[0]PCIE3:VF1_PM_CAP_NEXTPTR[1]
13 ----------------------------PCIE3:VF1_PM_CAP_NEXTPTR[2]PCIE3:VF1_PM_CAP_NEXTPTR[3]
14 ----------------------------PCIE3:VF1_PM_CAP_NEXTPTR[4]PCIE3:VF1_PM_CAP_NEXTPTR[5]
15 ----------------------------PCIE3:VF1_PM_CAP_NEXTPTR[6]PCIE3:VF1_PM_CAP_NEXTPTR[7]
16 ----------------------------PCIE3:VF2_PM_CAP_NEXTPTR[0]PCIE3:VF2_PM_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:VF2_PM_CAP_NEXTPTR[2]PCIE3:VF2_PM_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:VF2_PM_CAP_NEXTPTR[4]PCIE3:VF2_PM_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:VF2_PM_CAP_NEXTPTR[6]PCIE3:VF2_PM_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:VF3_PM_CAP_NEXTPTR[0]PCIE3:VF3_PM_CAP_NEXTPTR[1]
21 ----------------------------PCIE3:VF3_PM_CAP_NEXTPTR[2]PCIE3:VF3_PM_CAP_NEXTPTR[3]
22 ----------------------------PCIE3:VF3_PM_CAP_NEXTPTR[4]PCIE3:VF3_PM_CAP_NEXTPTR[5]
23 ----------------------------PCIE3:VF3_PM_CAP_NEXTPTR[6]PCIE3:VF3_PM_CAP_NEXTPTR[7]
24 ----------------------------PCIE3:VF4_PM_CAP_NEXTPTR[0]PCIE3:VF4_PM_CAP_NEXTPTR[1]
25 ----------------------------PCIE3:VF4_PM_CAP_NEXTPTR[2]PCIE3:VF4_PM_CAP_NEXTPTR[3]
26 ----------------------------PCIE3:VF4_PM_CAP_NEXTPTR[4]PCIE3:VF4_PM_CAP_NEXTPTR[5]
27 ----------------------------PCIE3:VF4_PM_CAP_NEXTPTR[6]PCIE3:VF4_PM_CAP_NEXTPTR[7]
28 ----------------------------PCIE3:VF5_PM_CAP_NEXTPTR[0]PCIE3:VF5_PM_CAP_NEXTPTR[1]
29 ----------------------------PCIE3:VF5_PM_CAP_NEXTPTR[2]PCIE3:VF5_PM_CAP_NEXTPTR[3]
30 ----------------------------PCIE3:VF5_PM_CAP_NEXTPTR[4]PCIE3:VF5_PM_CAP_NEXTPTR[5]
31 ----------------------------PCIE3:VF5_PM_CAP_NEXTPTR[6]PCIE3:VF5_PM_CAP_NEXTPTR[7]
32 ------------------------------
33 ------------------------------
34 ----------------------------PCIE3:PF0_PM_CAP_VER_ID[0]PCIE3:PF0_PM_CAP_VER_ID[1]
35 ----------------------------PCIE3:PF0_PM_CAP_VER_ID[2]PCIE3:PF1_PM_CAP_VER_ID[0]
36 ----------------------------PCIE3:PF1_PM_CAP_VER_ID[1]PCIE3:PF1_PM_CAP_VER_ID[2]
37 ----------------------------PCIE3:VF0_PM_CAP_VER_ID[0]PCIE3:VF0_PM_CAP_VER_ID[1]
38 ----------------------------PCIE3:VF0_PM_CAP_VER_ID[2]PCIE3:VF1_PM_CAP_VER_ID[0]
39 ----------------------------PCIE3:VF1_PM_CAP_VER_ID[1]PCIE3:VF1_PM_CAP_VER_ID[2]
40 ----------------------------PCIE3:VF2_PM_CAP_VER_ID[0]PCIE3:VF2_PM_CAP_VER_ID[1]
41 ----------------------------PCIE3:VF2_PM_CAP_VER_ID[2]PCIE3:VF3_PM_CAP_VER_ID[0]
42 ----------------------------PCIE3:VF3_PM_CAP_VER_ID[1]PCIE3:VF3_PM_CAP_VER_ID[2]
43 ----------------------------PCIE3:VF4_PM_CAP_VER_ID[0]PCIE3:VF4_PM_CAP_VER_ID[1]
44 ----------------------------PCIE3:VF4_PM_CAP_VER_ID[2]PCIE3:VF5_PM_CAP_VER_ID[0]
45 ----------------------------PCIE3:VF5_PM_CAP_VER_ID[1]PCIE3:VF5_PM_CAP_VER_ID[2]
PCIE3 bittile 21
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_RBAR_CAP_VER[0]PCIE3:PF0_RBAR_CAP_VER[1]
1 ----------------------------PCIE3:PF0_RBAR_CAP_VER[2]PCIE3:PF0_RBAR_CAP_VER[3]
2 ----------------------------PCIE3:PF1_RBAR_CAP_VER[0]PCIE3:PF1_RBAR_CAP_VER[1]
3 ----------------------------PCIE3:PF1_RBAR_CAP_VER[2]PCIE3:PF1_RBAR_CAP_VER[3]
4 ------------------------------
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[0]PCIE3:PF0_RBAR_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[2]PCIE3:PF0_RBAR_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[4]PCIE3:PF0_RBAR_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[6]PCIE3:PF0_RBAR_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[8]PCIE3:PF0_RBAR_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:PF0_RBAR_CAP_NEXTPTR[10]PCIE3:PF0_RBAR_CAP_NEXTPTR[11]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[0]PCIE3:PF1_RBAR_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[2]PCIE3:PF1_RBAR_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[4]PCIE3:PF1_RBAR_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[6]PCIE3:PF1_RBAR_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[8]PCIE3:PF1_RBAR_CAP_NEXTPTR[9]
21 ----------------------------PCIE3:PF1_RBAR_CAP_NEXTPTR[10]PCIE3:PF1_RBAR_CAP_NEXTPTR[11]
22 ----------------------------PCIE3:PF0_RBAR_NUM[0]PCIE3:PF0_RBAR_NUM[1]
23 ----------------------------PCIE3:PF0_RBAR_NUM[2]-
24 ----------------------------PCIE3:PF1_RBAR_NUM[0]PCIE3:PF1_RBAR_NUM[1]
25 ----------------------------PCIE3:PF1_RBAR_NUM[2]PCIE3:PF0_RBAR_CAP_INDEX0[0]
26 ----------------------------PCIE3:PF0_RBAR_CAP_INDEX0[1]PCIE3:PF0_RBAR_CAP_INDEX0[2]
27 ----------------------------PCIE3:PF1_RBAR_CAP_INDEX0[0]PCIE3:PF1_RBAR_CAP_INDEX0[1]
28 ----------------------------PCIE3:PF1_RBAR_CAP_INDEX0[2]-
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[0]PCIE3:PF0_RBAR_CAP_SIZE0[1]
33 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[2]PCIE3:PF0_RBAR_CAP_SIZE0[3]
34 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[4]PCIE3:PF0_RBAR_CAP_SIZE0[5]
35 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[6]PCIE3:PF0_RBAR_CAP_SIZE0[7]
36 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[8]PCIE3:PF0_RBAR_CAP_SIZE0[9]
37 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[10]PCIE3:PF0_RBAR_CAP_SIZE0[11]
38 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[12]PCIE3:PF0_RBAR_CAP_SIZE0[13]
39 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[14]PCIE3:PF0_RBAR_CAP_SIZE0[15]
40 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[16]PCIE3:PF0_RBAR_CAP_SIZE0[17]
41 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE0[18]PCIE3:PF0_RBAR_CAP_SIZE0[19]
PCIE3 bittile 22
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[0]PCIE3:PF1_RBAR_CAP_SIZE0[1]
1 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[2]PCIE3:PF1_RBAR_CAP_SIZE0[3]
2 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[4]PCIE3:PF1_RBAR_CAP_SIZE0[5]
3 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[6]PCIE3:PF1_RBAR_CAP_SIZE0[7]
4 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[8]PCIE3:PF1_RBAR_CAP_SIZE0[9]
5 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[10]PCIE3:PF1_RBAR_CAP_SIZE0[11]
6 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[12]PCIE3:PF1_RBAR_CAP_SIZE0[13]
7 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[14]PCIE3:PF1_RBAR_CAP_SIZE0[15]
8 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[16]PCIE3:PF1_RBAR_CAP_SIZE0[17]
9 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE0[18]PCIE3:PF1_RBAR_CAP_SIZE0[19]
10 ----------------------------PCIE3:PF0_RBAR_CAP_INDEX1[0]PCIE3:PF0_RBAR_CAP_INDEX1[1]
11 ----------------------------PCIE3:PF0_RBAR_CAP_INDEX1[2]PCIE3:PF1_RBAR_CAP_INDEX1[0]
12 ----------------------------PCIE3:PF1_RBAR_CAP_INDEX1[1]PCIE3:PF1_RBAR_CAP_INDEX1[2]
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[0]PCIE3:PF0_RBAR_CAP_SIZE1[1]
17 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[2]PCIE3:PF0_RBAR_CAP_SIZE1[3]
18 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[4]PCIE3:PF0_RBAR_CAP_SIZE1[5]
19 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[6]PCIE3:PF0_RBAR_CAP_SIZE1[7]
20 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[8]PCIE3:PF0_RBAR_CAP_SIZE1[9]
21 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[10]PCIE3:PF0_RBAR_CAP_SIZE1[11]
22 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[12]PCIE3:PF0_RBAR_CAP_SIZE1[13]
23 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[14]PCIE3:PF0_RBAR_CAP_SIZE1[15]
24 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[16]PCIE3:PF0_RBAR_CAP_SIZE1[17]
25 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE1[18]PCIE3:PF0_RBAR_CAP_SIZE1[19]
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[0]PCIE3:PF1_RBAR_CAP_SIZE1[1]
33 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[2]PCIE3:PF1_RBAR_CAP_SIZE1[3]
34 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[4]PCIE3:PF1_RBAR_CAP_SIZE1[5]
35 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[6]PCIE3:PF1_RBAR_CAP_SIZE1[7]
36 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[8]PCIE3:PF1_RBAR_CAP_SIZE1[9]
37 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[10]PCIE3:PF1_RBAR_CAP_SIZE1[11]
38 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[12]PCIE3:PF1_RBAR_CAP_SIZE1[13]
39 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[14]PCIE3:PF1_RBAR_CAP_SIZE1[15]
40 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[16]PCIE3:PF1_RBAR_CAP_SIZE1[17]
41 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE1[18]PCIE3:PF1_RBAR_CAP_SIZE1[19]
42 ----------------------------PCIE3:PF0_RBAR_CAP_INDEX2[0]PCIE3:PF0_RBAR_CAP_INDEX2[1]
43 ----------------------------PCIE3:PF0_RBAR_CAP_INDEX2[2]PCIE3:PF1_RBAR_CAP_INDEX2[0]
44 ----------------------------PCIE3:PF1_RBAR_CAP_INDEX2[1]PCIE3:PF1_RBAR_CAP_INDEX2[2]
PCIE3 bittile 23
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[0]PCIE3:PF0_RBAR_CAP_SIZE2[1]
1 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[2]PCIE3:PF0_RBAR_CAP_SIZE2[3]
2 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[4]PCIE3:PF0_RBAR_CAP_SIZE2[5]
3 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[6]PCIE3:PF0_RBAR_CAP_SIZE2[7]
4 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[8]PCIE3:PF0_RBAR_CAP_SIZE2[9]
5 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[10]PCIE3:PF0_RBAR_CAP_SIZE2[11]
6 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[12]PCIE3:PF0_RBAR_CAP_SIZE2[13]
7 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[14]PCIE3:PF0_RBAR_CAP_SIZE2[15]
8 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[16]PCIE3:PF0_RBAR_CAP_SIZE2[17]
9 ----------------------------PCIE3:PF0_RBAR_CAP_SIZE2[18]PCIE3:PF0_RBAR_CAP_SIZE2[19]
10 ------------------------------
11 ------------------------------
12 ------------------------------
13 ------------------------------
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[0]PCIE3:PF1_RBAR_CAP_SIZE2[1]
17 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[2]PCIE3:PF1_RBAR_CAP_SIZE2[3]
18 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[4]PCIE3:PF1_RBAR_CAP_SIZE2[5]
19 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[6]PCIE3:PF1_RBAR_CAP_SIZE2[7]
20 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[8]PCIE3:PF1_RBAR_CAP_SIZE2[9]
21 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[10]PCIE3:PF1_RBAR_CAP_SIZE2[11]
22 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[12]PCIE3:PF1_RBAR_CAP_SIZE2[13]
23 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[14]PCIE3:PF1_RBAR_CAP_SIZE2[15]
24 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[16]PCIE3:PF1_RBAR_CAP_SIZE2[17]
25 ----------------------------PCIE3:PF1_RBAR_CAP_SIZE2[18]PCIE3:PF1_RBAR_CAP_SIZE2[19]
26 ----------------------------PCIE3:DNSTREAM_LINK_NUM[0]PCIE3:DNSTREAM_LINK_NUM[1]
27 ----------------------------PCIE3:DNSTREAM_LINK_NUM[2]PCIE3:DNSTREAM_LINK_NUM[3]
28 ----------------------------PCIE3:DNSTREAM_LINK_NUM[4]PCIE3:DNSTREAM_LINK_NUM[5]
29 ----------------------------PCIE3:DNSTREAM_LINK_NUM[6]PCIE3:DNSTREAM_LINK_NUM[7]
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[0]PCIE3:PF0_DSN_CAP_NEXTPTR[1]
33 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[2]PCIE3:PF0_DSN_CAP_NEXTPTR[3]
34 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[4]PCIE3:PF0_DSN_CAP_NEXTPTR[5]
35 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[6]PCIE3:PF0_DSN_CAP_NEXTPTR[7]
36 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[8]PCIE3:PF0_DSN_CAP_NEXTPTR[9]
37 ----------------------------PCIE3:PF0_DSN_CAP_NEXTPTR[10]PCIE3:PF0_DSN_CAP_NEXTPTR[11]
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[0]PCIE3:PF1_DSN_CAP_NEXTPTR[1]
41 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[2]PCIE3:PF1_DSN_CAP_NEXTPTR[3]
42 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[4]PCIE3:PF1_DSN_CAP_NEXTPTR[5]
43 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[6]PCIE3:PF1_DSN_CAP_NEXTPTR[7]
44 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[8]PCIE3:PF1_DSN_CAP_NEXTPTR[9]
45 ----------------------------PCIE3:PF1_DSN_CAP_NEXTPTR[10]PCIE3:PF1_DSN_CAP_NEXTPTR[11]
46 ----------------------------PCIE3:PF0_VC_CAP_VER[0]PCIE3:PF0_VC_CAP_VER[1]
47 ----------------------------PCIE3:PF0_VC_CAP_VER[2]PCIE3:PF0_VC_CAP_VER[3]
PCIE3 bittile 24
RowColumn
PCIE3 bittile 25
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[0]PCIE3:PF0_VC_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[2]PCIE3:PF0_VC_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[4]PCIE3:PF0_VC_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[6]PCIE3:PF0_VC_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[8]PCIE3:PF0_VC_CAP_NEXTPTR[9]
5 ----------------------------PCIE3:PF0_VC_CAP_NEXTPTR[10]PCIE3:PF0_VC_CAP_NEXTPTR[11]
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[0]PCIE3:PF0_AER_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[2]PCIE3:PF0_AER_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[4]PCIE3:PF0_AER_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[6]PCIE3:PF0_AER_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[8]PCIE3:PF0_AER_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:PF0_AER_CAP_NEXTPTR[10]PCIE3:PF0_AER_CAP_NEXTPTR[11]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[0]PCIE3:PF1_AER_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[2]PCIE3:PF1_AER_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[4]PCIE3:PF1_AER_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[6]PCIE3:PF1_AER_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[8]PCIE3:PF1_AER_CAP_NEXTPTR[9]
21 ----------------------------PCIE3:PF1_AER_CAP_NEXTPTR[10]PCIE3:PF1_AER_CAP_NEXTPTR[11]
22 ----------------------------PCIE3:PF0_AER_CAP_ECRC_CHECK_CAPABLE-
23 ----------------------------PCIE3:PF0_AER_CAP_ECRC_GEN_CAPABLE-
24 ----------------------------PCIE3:ARI_CAP_ENABLEPCIE3:PF0_ARI_CAP_NEXTPTR[0]
25 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[1]PCIE3:PF0_ARI_CAP_NEXTPTR[2]
26 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[3]PCIE3:PF0_ARI_CAP_NEXTPTR[4]
27 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[5]PCIE3:PF0_ARI_CAP_NEXTPTR[6]
28 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[7]PCIE3:PF0_ARI_CAP_NEXTPTR[8]
29 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[9]PCIE3:PF0_ARI_CAP_NEXTPTR[10]
30 ----------------------------PCIE3:PF0_ARI_CAP_NEXTPTR[11]-
31 ------------------------------
32 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[0]PCIE3:PF1_ARI_CAP_NEXTPTR[1]
33 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[2]PCIE3:PF1_ARI_CAP_NEXTPTR[3]
34 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[4]PCIE3:PF1_ARI_CAP_NEXTPTR[5]
35 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[6]PCIE3:PF1_ARI_CAP_NEXTPTR[7]
36 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[8]PCIE3:PF1_ARI_CAP_NEXTPTR[9]
37 ----------------------------PCIE3:PF1_ARI_CAP_NEXTPTR[10]PCIE3:PF1_ARI_CAP_NEXTPTR[11]
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[0]PCIE3:VF0_ARI_CAP_NEXTPTR[1]
41 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[2]PCIE3:VF0_ARI_CAP_NEXTPTR[3]
42 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[4]PCIE3:VF0_ARI_CAP_NEXTPTR[5]
43 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[6]PCIE3:VF0_ARI_CAP_NEXTPTR[7]
44 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[8]PCIE3:VF0_ARI_CAP_NEXTPTR[9]
45 ----------------------------PCIE3:VF0_ARI_CAP_NEXTPTR[10]PCIE3:VF0_ARI_CAP_NEXTPTR[11]
PCIE3 bittile 26
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[0]PCIE3:VF1_ARI_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[2]PCIE3:VF1_ARI_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[4]PCIE3:VF1_ARI_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[6]PCIE3:VF1_ARI_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[8]PCIE3:VF1_ARI_CAP_NEXTPTR[9]
5 ----------------------------PCIE3:VF1_ARI_CAP_NEXTPTR[10]PCIE3:VF1_ARI_CAP_NEXTPTR[11]
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[0]PCIE3:VF2_ARI_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[2]PCIE3:VF2_ARI_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[4]PCIE3:VF2_ARI_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[6]PCIE3:VF2_ARI_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[8]PCIE3:VF2_ARI_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:VF2_ARI_CAP_NEXTPTR[10]PCIE3:VF2_ARI_CAP_NEXTPTR[11]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[0]PCIE3:VF3_ARI_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[2]PCIE3:VF3_ARI_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[4]PCIE3:VF3_ARI_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[6]PCIE3:VF3_ARI_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[8]PCIE3:VF3_ARI_CAP_NEXTPTR[9]
21 ----------------------------PCIE3:VF3_ARI_CAP_NEXTPTR[10]PCIE3:VF3_ARI_CAP_NEXTPTR[11]
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[0]PCIE3:VF4_ARI_CAP_NEXTPTR[1]
25 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[2]PCIE3:VF4_ARI_CAP_NEXTPTR[3]
26 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[4]PCIE3:VF4_ARI_CAP_NEXTPTR[5]
27 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[6]PCIE3:VF4_ARI_CAP_NEXTPTR[7]
28 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[8]PCIE3:VF4_ARI_CAP_NEXTPTR[9]
29 ----------------------------PCIE3:VF4_ARI_CAP_NEXTPTR[10]PCIE3:VF4_ARI_CAP_NEXTPTR[11]
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[0]PCIE3:VF5_ARI_CAP_NEXTPTR[1]
33 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[2]PCIE3:VF5_ARI_CAP_NEXTPTR[3]
34 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[4]PCIE3:VF5_ARI_CAP_NEXTPTR[5]
35 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[6]PCIE3:VF5_ARI_CAP_NEXTPTR[7]
36 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[8]PCIE3:VF5_ARI_CAP_NEXTPTR[9]
37 ----------------------------PCIE3:VF5_ARI_CAP_NEXTPTR[10]PCIE3:VF5_ARI_CAP_NEXTPTR[11]
38 ----------------------------PCIE3:PF0_ARI_CAP_VER[0]PCIE3:PF0_ARI_CAP_VER[1]
39 ----------------------------PCIE3:PF0_ARI_CAP_VER[2]PCIE3:PF0_ARI_CAP_VER[3]
40 ----------------------------PCIE3:PF0_ARI_CAP_NEXT_FUNC[0]PCIE3:PF0_ARI_CAP_NEXT_FUNC[1]
41 ----------------------------PCIE3:PF0_ARI_CAP_NEXT_FUNC[2]PCIE3:PF0_ARI_CAP_NEXT_FUNC[3]
42 ----------------------------PCIE3:PF0_ARI_CAP_NEXT_FUNC[4]PCIE3:PF0_ARI_CAP_NEXT_FUNC[5]
43 ----------------------------PCIE3:PF0_ARI_CAP_NEXT_FUNC[6]PCIE3:PF0_ARI_CAP_NEXT_FUNC[7]
44 ----------------------------PCIE3:PF1_ARI_CAP_NEXT_FUNC[0]PCIE3:PF1_ARI_CAP_NEXT_FUNC[1]
45 ----------------------------PCIE3:PF1_ARI_CAP_NEXT_FUNC[2]PCIE3:PF1_ARI_CAP_NEXT_FUNC[3]
46 ----------------------------PCIE3:PF1_ARI_CAP_NEXT_FUNC[4]PCIE3:PF1_ARI_CAP_NEXT_FUNC[5]
47 ----------------------------PCIE3:PF1_ARI_CAP_NEXT_FUNC[6]PCIE3:PF1_ARI_CAP_NEXT_FUNC[7]
PCIE3 bittile 27
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[0]PCIE3:PF0_PB_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[2]PCIE3:PF0_PB_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[4]PCIE3:PF0_PB_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[6]PCIE3:PF0_PB_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[8]PCIE3:PF0_PB_CAP_NEXTPTR[9]
5 ----------------------------PCIE3:PF0_PB_CAP_NEXTPTR[10]PCIE3:PF0_PB_CAP_NEXTPTR[11]
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[0]PCIE3:PF1_PB_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[2]PCIE3:PF1_PB_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[4]PCIE3:PF1_PB_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[6]PCIE3:PF1_PB_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[8]PCIE3:PF1_PB_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:PF1_PB_CAP_NEXTPTR[10]PCIE3:PF1_PB_CAP_NEXTPTR[11]
14 ----------------------------PCIE3:PF0_PB_CAP_VER[0]PCIE3:PF0_PB_CAP_VER[1]
15 ----------------------------PCIE3:PF0_PB_CAP_VER[2]PCIE3:PF0_PB_CAP_VER[3]
16 ----------------------------PCIE3:PF1_PB_CAP_VER[0]PCIE3:PF1_PB_CAP_VER[1]
17 ----------------------------PCIE3:PF1_PB_CAP_VER[2]PCIE3:PF1_PB_CAP_VER[3]
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[0]PCIE3:PF0_LTR_CAP_NEXTPTR[1]
25 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[2]PCIE3:PF0_LTR_CAP_NEXTPTR[3]
26 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[4]PCIE3:PF0_LTR_CAP_NEXTPTR[5]
27 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[6]PCIE3:PF0_LTR_CAP_NEXTPTR[7]
28 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[8]PCIE3:PF0_LTR_CAP_NEXTPTR[9]
29 ----------------------------PCIE3:PF0_LTR_CAP_NEXTPTR[10]PCIE3:PF0_LTR_CAP_NEXTPTR[11]
30 ----------------------------PCIE3:PF0_LTR_CAP_VER[0]PCIE3:PF0_LTR_CAP_VER[1]
31 ----------------------------PCIE3:PF0_LTR_CAP_VER[2]PCIE3:PF0_LTR_CAP_VER[3]
32 ----------------------------PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[0]PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[1]
33 ----------------------------PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[2]PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[3]
34 ----------------------------PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[4]PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[5]
35 ----------------------------PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[6]PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[7]
36 ----------------------------PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[8]PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[9]
37 ------------------------------
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[0]PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[1]
41 ----------------------------PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[2]PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[3]
42 ----------------------------PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[4]PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[5]
43 ----------------------------PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[6]PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[7]
44 ----------------------------PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[8]PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[9]
45 ----------------------------PCIE3:LTR_TX_MESSAGE_ON_LTR_ENABLEPCIE3:LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE
PCIE3 bittile 28
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[0]PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[1]
1 ----------------------------PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[2]PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[3]
2 ----------------------------PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[4]PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[5]
3 ----------------------------PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[6]PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[7]
4 ----------------------------PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[8]PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[9]
5 ------------------------------
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[0]PCIE3:PF0_DPA_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[2]PCIE3:PF0_DPA_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[4]PCIE3:PF0_DPA_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[6]PCIE3:PF0_DPA_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[8]PCIE3:PF0_DPA_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:PF0_DPA_CAP_NEXTPTR[10]PCIE3:PF0_DPA_CAP_NEXTPTR[11]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[0]PCIE3:PF1_DPA_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[2]PCIE3:PF1_DPA_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[4]PCIE3:PF1_DPA_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[6]PCIE3:PF1_DPA_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[8]PCIE3:PF1_DPA_CAP_NEXTPTR[9]
21 ----------------------------PCIE3:PF1_DPA_CAP_NEXTPTR[10]PCIE3:PF1_DPA_CAP_NEXTPTR[11]
22 ----------------------------PCIE3:PF0_DPA_CAP_VER[0]PCIE3:PF0_DPA_CAP_VER[1]
23 ----------------------------PCIE3:PF0_DPA_CAP_VER[2]PCIE3:PF0_DPA_CAP_VER[3]
24 ----------------------------PCIE3:PF1_DPA_CAP_VER[0]PCIE3:PF1_DPA_CAP_VER[1]
25 ----------------------------PCIE3:PF1_DPA_CAP_VER[2]PCIE3:PF1_DPA_CAP_VER[3]
26 ------------------------------
27 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[0]PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[1]
28 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[2]PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[3]
29 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[4]PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[0]
30 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[1]PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[2]
31 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[3]PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[4]
32 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[1]
33 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[3]
34 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[5]
35 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[7]
36 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[1]
37 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[3]
38 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[5]
39 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[7]
40 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[1]
41 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[3]
42 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[5]
43 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[7]
44 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[1]
45 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[3]
46 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[5]
47 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[7]
PCIE3 bittile 29
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[1]
1 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[3]
2 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[5]
3 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[7]
4 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[1]
5 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[3]
6 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[5]
7 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[7]
8 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[1]
9 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[3]
10 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[5]
11 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[7]
12 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[1]
13 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[3]
14 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[5]
15 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[7]
16 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[1]
17 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[3]
18 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[5]
19 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[7]
20 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[1]
21 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[3]
22 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[5]
23 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[7]
24 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[1]
25 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[3]
26 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[5]
27 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[7]
28 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[1]
29 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[3]
30 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[5]
31 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[7]
32 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[1]
33 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[3]
34 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[5]
35 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[7]
36 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[1]
37 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[3]
38 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[5]
39 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[7]
40 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[0]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[1]
41 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[2]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[3]
42 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[4]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[5]
43 ----------------------------PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[6]PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[7]
44 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[0]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[1]
45 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[2]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[3]
46 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[4]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[5]
47 ----------------------------PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[6]PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[7]
PCIE3 bittile 30
RowColumn
01234567891011121314151617181920212223242526272829
0 -----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[0]
1 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[1]PCIE3:PF0_SRIOV_CAP_NEXTPTR[2]
2 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[3]PCIE3:PF0_SRIOV_CAP_NEXTPTR[4]
3 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[5]PCIE3:PF0_SRIOV_CAP_NEXTPTR[6]
4 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[7]PCIE3:PF0_SRIOV_CAP_NEXTPTR[8]
5 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[9]PCIE3:PF0_SRIOV_CAP_NEXTPTR[10]
6 ----------------------------PCIE3:PF0_SRIOV_CAP_NEXTPTR[11]-
7 ------------------------------
8 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[0]PCIE3:PF1_SRIOV_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[2]PCIE3:PF1_SRIOV_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[4]PCIE3:PF1_SRIOV_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[6]PCIE3:PF1_SRIOV_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[8]PCIE3:PF1_SRIOV_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:PF1_SRIOV_CAP_NEXTPTR[10]PCIE3:PF1_SRIOV_CAP_NEXTPTR[11]
14 ----------------------------PCIE3:PF0_SRIOV_CAP_VER[0]PCIE3:PF0_SRIOV_CAP_VER[1]
15 ----------------------------PCIE3:PF0_SRIOV_CAP_VER[2]PCIE3:PF0_SRIOV_CAP_VER[3]
16 ----------------------------PCIE3:PF1_SRIOV_CAP_VER[0]PCIE3:PF1_SRIOV_CAP_VER[1]
17 ----------------------------PCIE3:PF1_SRIOV_CAP_VER[2]PCIE3:PF1_SRIOV_CAP_VER[3]
18 ------------------------------
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[0]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[1]
25 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[2]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[3]
26 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[4]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[5]
27 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[6]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[7]
28 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[8]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[9]
29 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[10]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[11]
30 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[12]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[13]
31 ----------------------------PCIE3:PF0_SRIOV_CAP_INITIAL_VF[14]PCIE3:PF0_SRIOV_CAP_INITIAL_VF[15]
32 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[0]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[1]
33 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[2]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[3]
34 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[4]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[5]
35 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[6]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[7]
36 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[8]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[9]
37 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[10]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[11]
38 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[12]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[13]
39 ----------------------------PCIE3:PF1_SRIOV_CAP_INITIAL_VF[14]PCIE3:PF1_SRIOV_CAP_INITIAL_VF[15]
40 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[0]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[1]
41 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[2]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[3]
42 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[4]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[5]
43 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[6]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[7]
44 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[8]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[9]
45 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[10]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[11]
46 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[12]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[13]
47 ----------------------------PCIE3:PF0_SRIOV_CAP_TOTAL_VF[14]PCIE3:PF0_SRIOV_CAP_TOTAL_VF[15]
PCIE3 bittile 31
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[0]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[1]
1 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[2]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[3]
2 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[4]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[5]
3 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[6]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[7]
4 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[8]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[9]
5 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[10]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[11]
6 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[12]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[13]
7 ----------------------------PCIE3:PF1_SRIOV_CAP_TOTAL_VF[14]PCIE3:PF1_SRIOV_CAP_TOTAL_VF[15]
8 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[0]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[1]
9 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[2]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[3]
10 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[4]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[5]
11 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[6]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[7]
12 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[8]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[9]
13 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[10]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[11]
14 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[12]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[13]
15 ----------------------------PCIE3:PF0_SRIOV_FUNC_DEP_LINK[14]PCIE3:PF0_SRIOV_FUNC_DEP_LINK[15]
16 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[0]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[1]
17 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[2]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[3]
18 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[4]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[5]
19 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[6]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[7]
20 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[8]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[9]
21 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[10]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[11]
22 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[12]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[13]
23 ----------------------------PCIE3:PF1_SRIOV_FUNC_DEP_LINK[14]PCIE3:PF1_SRIOV_FUNC_DEP_LINK[15]
24 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[0]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[1]
25 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[2]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[3]
26 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[4]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[5]
27 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[6]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[7]
28 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[8]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[9]
29 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[10]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[11]
30 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[12]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[13]
31 ----------------------------PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[14]PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[15]
32 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[0]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[1]
33 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[2]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[3]
34 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[4]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[5]
35 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[6]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[7]
36 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[8]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[9]
37 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[10]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[11]
38 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[12]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[13]
39 ----------------------------PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[14]PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[15]
40 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[0]PCIE3:PF0_SRIOV_VF_DEVICE_ID[1]
41 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[2]PCIE3:PF0_SRIOV_VF_DEVICE_ID[3]
42 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[4]PCIE3:PF0_SRIOV_VF_DEVICE_ID[5]
43 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[6]PCIE3:PF0_SRIOV_VF_DEVICE_ID[7]
44 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[8]PCIE3:PF0_SRIOV_VF_DEVICE_ID[9]
45 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[10]PCIE3:PF0_SRIOV_VF_DEVICE_ID[11]
46 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[12]PCIE3:PF0_SRIOV_VF_DEVICE_ID[13]
47 ----------------------------PCIE3:PF0_SRIOV_VF_DEVICE_ID[14]PCIE3:PF0_SRIOV_VF_DEVICE_ID[15]
PCIE3 bittile 32
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[0]PCIE3:PF1_SRIOV_VF_DEVICE_ID[1]
1 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[2]PCIE3:PF1_SRIOV_VF_DEVICE_ID[3]
2 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[4]PCIE3:PF1_SRIOV_VF_DEVICE_ID[5]
3 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[6]PCIE3:PF1_SRIOV_VF_DEVICE_ID[7]
4 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[8]PCIE3:PF1_SRIOV_VF_DEVICE_ID[9]
5 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[10]PCIE3:PF1_SRIOV_VF_DEVICE_ID[11]
6 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[12]PCIE3:PF1_SRIOV_VF_DEVICE_ID[13]
7 ----------------------------PCIE3:PF1_SRIOV_VF_DEVICE_ID[14]PCIE3:PF1_SRIOV_VF_DEVICE_ID[15]
8 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[0]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[1]
9 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[2]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[3]
10 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[4]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[5]
11 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[6]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[7]
12 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[8]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[9]
13 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[10]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[11]
14 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[12]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[13]
15 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[14]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[15]
16 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[16]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[17]
17 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[18]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[19]
18 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[20]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[21]
19 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[22]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[23]
20 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[24]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[25]
21 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[26]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[27]
22 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[28]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[29]
23 ----------------------------PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[30]PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[31]
24 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[0]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[1]
25 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[2]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[3]
26 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[4]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[5]
27 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[6]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[7]
28 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[8]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[9]
29 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[10]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[11]
30 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[12]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[13]
31 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[14]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[15]
32 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[16]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[17]
33 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[18]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[19]
34 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[20]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[21]
35 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[22]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[23]
36 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[24]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[25]
37 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[26]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[27]
38 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[28]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[29]
39 ----------------------------PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[30]PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[31]
40 ----------------------------PCIE3:PF0_SRIOV_BAR0_CONTROL[0]PCIE3:PF0_SRIOV_BAR0_CONTROL[1]
41 ----------------------------PCIE3:PF0_SRIOV_BAR0_CONTROL[2]PCIE3:PF1_SRIOV_BAR0_CONTROL[0]
42 ----------------------------PCIE3:PF1_SRIOV_BAR0_CONTROL[1]PCIE3:PF1_SRIOV_BAR0_CONTROL[2]
43 ----------------------------PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[1]
44 ----------------------------PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[3]
45 ----------------------------PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[0]
46 ----------------------------PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[2]
47 ----------------------------PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[4]
PCIE3 bittile 33
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF0_SRIOV_BAR1_CONTROL[0]PCIE3:PF0_SRIOV_BAR1_CONTROL[1]
1 ----------------------------PCIE3:PF0_SRIOV_BAR1_CONTROL[2]PCIE3:PF1_SRIOV_BAR1_CONTROL[0]
2 ----------------------------PCIE3:PF1_SRIOV_BAR1_CONTROL[1]PCIE3:PF1_SRIOV_BAR1_CONTROL[2]
3 ----------------------------PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[1]
4 ----------------------------PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[3]
5 ----------------------------PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[0]
6 ----------------------------PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[2]
7 ----------------------------PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[4]
8 ----------------------------PCIE3:PF0_SRIOV_BAR2_CONTROL[0]PCIE3:PF0_SRIOV_BAR2_CONTROL[1]
9 ----------------------------PCIE3:PF0_SRIOV_BAR2_CONTROL[2]PCIE3:PF1_SRIOV_BAR2_CONTROL[0]
10 ----------------------------PCIE3:PF1_SRIOV_BAR2_CONTROL[1]PCIE3:PF1_SRIOV_BAR2_CONTROL[2]
11 ----------------------------PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[1]
12 ----------------------------PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[3]
13 ----------------------------PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[0]
14 ----------------------------PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[2]
15 ----------------------------PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[4]
16 ----------------------------PCIE3:PF0_SRIOV_BAR3_CONTROL[0]PCIE3:PF0_SRIOV_BAR3_CONTROL[1]
17 ----------------------------PCIE3:PF0_SRIOV_BAR3_CONTROL[2]PCIE3:PF1_SRIOV_BAR3_CONTROL[0]
18 ----------------------------PCIE3:PF1_SRIOV_BAR3_CONTROL[1]PCIE3:PF1_SRIOV_BAR3_CONTROL[2]
19 ----------------------------PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[1]
20 ----------------------------PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[3]
21 ----------------------------PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[0]
22 ----------------------------PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[2]
23 ----------------------------PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[4]
24 ----------------------------PCIE3:PF0_SRIOV_BAR4_CONTROL[0]PCIE3:PF0_SRIOV_BAR4_CONTROL[1]
25 ----------------------------PCIE3:PF0_SRIOV_BAR4_CONTROL[2]PCIE3:PF1_SRIOV_BAR4_CONTROL[0]
26 ----------------------------PCIE3:PF1_SRIOV_BAR4_CONTROL[1]PCIE3:PF1_SRIOV_BAR4_CONTROL[2]
27 ----------------------------PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[1]
28 ----------------------------PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[3]
29 ----------------------------PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[0]
30 ----------------------------PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[2]
31 ----------------------------PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[4]
32 ----------------------------PCIE3:PF0_SRIOV_BAR5_CONTROL[0]PCIE3:PF0_SRIOV_BAR5_CONTROL[1]
33 ----------------------------PCIE3:PF0_SRIOV_BAR5_CONTROL[2]PCIE3:PF1_SRIOV_BAR5_CONTROL[0]
34 ----------------------------PCIE3:PF1_SRIOV_BAR5_CONTROL[1]PCIE3:PF1_SRIOV_BAR5_CONTROL[2]
35 ----------------------------PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[0]PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[1]
36 ----------------------------PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[2]PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[3]
37 ----------------------------PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[4]PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[0]
38 ----------------------------PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[1]PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[2]
39 ----------------------------PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[3]PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[4]
40 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[0]PCIE3:PF0_TPHR_CAP_NEXTPTR[1]
41 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[2]PCIE3:PF0_TPHR_CAP_NEXTPTR[3]
42 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[4]PCIE3:PF0_TPHR_CAP_NEXTPTR[5]
43 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[6]PCIE3:PF0_TPHR_CAP_NEXTPTR[7]
44 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[8]PCIE3:PF0_TPHR_CAP_NEXTPTR[9]
45 ----------------------------PCIE3:PF0_TPHR_CAP_NEXTPTR[10]PCIE3:PF0_TPHR_CAP_NEXTPTR[11]
PCIE3 bittile 34
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[0]PCIE3:PF1_TPHR_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[2]PCIE3:PF1_TPHR_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[4]PCIE3:PF1_TPHR_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[6]PCIE3:PF1_TPHR_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[8]PCIE3:PF1_TPHR_CAP_NEXTPTR[9]
5 ----------------------------PCIE3:PF1_TPHR_CAP_NEXTPTR[10]PCIE3:PF1_TPHR_CAP_NEXTPTR[11]
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[0]PCIE3:VF0_TPHR_CAP_NEXTPTR[1]
9 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[2]PCIE3:VF0_TPHR_CAP_NEXTPTR[3]
10 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[4]PCIE3:VF0_TPHR_CAP_NEXTPTR[5]
11 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[6]PCIE3:VF0_TPHR_CAP_NEXTPTR[7]
12 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[8]PCIE3:VF0_TPHR_CAP_NEXTPTR[9]
13 ----------------------------PCIE3:VF0_TPHR_CAP_NEXTPTR[10]PCIE3:VF0_TPHR_CAP_NEXTPTR[11]
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[0]PCIE3:VF1_TPHR_CAP_NEXTPTR[1]
17 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[2]PCIE3:VF1_TPHR_CAP_NEXTPTR[3]
18 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[4]PCIE3:VF1_TPHR_CAP_NEXTPTR[5]
19 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[6]PCIE3:VF1_TPHR_CAP_NEXTPTR[7]
20 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[8]PCIE3:VF1_TPHR_CAP_NEXTPTR[9]
21 ----------------------------PCIE3:VF1_TPHR_CAP_NEXTPTR[10]PCIE3:VF1_TPHR_CAP_NEXTPTR[11]
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[0]PCIE3:VF2_TPHR_CAP_NEXTPTR[1]
25 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[2]PCIE3:VF2_TPHR_CAP_NEXTPTR[3]
26 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[4]PCIE3:VF2_TPHR_CAP_NEXTPTR[5]
27 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[6]PCIE3:VF2_TPHR_CAP_NEXTPTR[7]
28 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[8]PCIE3:VF2_TPHR_CAP_NEXTPTR[9]
29 ----------------------------PCIE3:VF2_TPHR_CAP_NEXTPTR[10]PCIE3:VF2_TPHR_CAP_NEXTPTR[11]
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[0]PCIE3:VF3_TPHR_CAP_NEXTPTR[1]
33 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[2]PCIE3:VF3_TPHR_CAP_NEXTPTR[3]
34 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[4]PCIE3:VF3_TPHR_CAP_NEXTPTR[5]
35 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[6]PCIE3:VF3_TPHR_CAP_NEXTPTR[7]
36 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[8]PCIE3:VF3_TPHR_CAP_NEXTPTR[9]
37 ----------------------------PCIE3:VF3_TPHR_CAP_NEXTPTR[10]PCIE3:VF3_TPHR_CAP_NEXTPTR[11]
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[0]PCIE3:VF4_TPHR_CAP_NEXTPTR[1]
41 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[2]PCIE3:VF4_TPHR_CAP_NEXTPTR[3]
42 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[4]PCIE3:VF4_TPHR_CAP_NEXTPTR[5]
43 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[6]PCIE3:VF4_TPHR_CAP_NEXTPTR[7]
44 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[8]PCIE3:VF4_TPHR_CAP_NEXTPTR[9]
45 ----------------------------PCIE3:VF4_TPHR_CAP_NEXTPTR[10]PCIE3:VF4_TPHR_CAP_NEXTPTR[11]
PCIE3 bittile 35
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[0]PCIE3:VF5_TPHR_CAP_NEXTPTR[1]
1 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[2]PCIE3:VF5_TPHR_CAP_NEXTPTR[3]
2 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[4]PCIE3:VF5_TPHR_CAP_NEXTPTR[5]
3 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[6]PCIE3:VF5_TPHR_CAP_NEXTPTR[7]
4 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[8]PCIE3:VF5_TPHR_CAP_NEXTPTR[9]
5 ----------------------------PCIE3:VF5_TPHR_CAP_NEXTPTR[10]PCIE3:VF5_TPHR_CAP_NEXTPTR[11]
6 ----------------------------PCIE3:PF0_TPHR_CAP_VER[0]PCIE3:PF0_TPHR_CAP_VER[1]
7 ----------------------------PCIE3:PF0_TPHR_CAP_VER[2]PCIE3:PF0_TPHR_CAP_VER[3]
8 ----------------------------PCIE3:PF1_TPHR_CAP_VER[0]PCIE3:PF1_TPHR_CAP_VER[1]
9 ----------------------------PCIE3:PF1_TPHR_CAP_VER[2]PCIE3:PF1_TPHR_CAP_VER[3]
10 ----------------------------PCIE3:VF0_TPHR_CAP_VER[0]PCIE3:VF0_TPHR_CAP_VER[1]
11 ----------------------------PCIE3:VF0_TPHR_CAP_VER[2]PCIE3:VF0_TPHR_CAP_VER[3]
12 ----------------------------PCIE3:VF1_TPHR_CAP_VER[0]PCIE3:VF1_TPHR_CAP_VER[1]
13 ----------------------------PCIE3:VF1_TPHR_CAP_VER[2]PCIE3:VF1_TPHR_CAP_VER[3]
14 ----------------------------PCIE3:VF2_TPHR_CAP_VER[0]PCIE3:VF2_TPHR_CAP_VER[1]
15 ----------------------------PCIE3:VF2_TPHR_CAP_VER[2]PCIE3:VF2_TPHR_CAP_VER[3]
16 ----------------------------PCIE3:VF3_TPHR_CAP_VER[0]PCIE3:VF3_TPHR_CAP_VER[1]
17 ----------------------------PCIE3:VF3_TPHR_CAP_VER[2]PCIE3:VF3_TPHR_CAP_VER[3]
18 ----------------------------PCIE3:VF4_TPHR_CAP_VER[0]PCIE3:VF4_TPHR_CAP_VER[1]
19 ----------------------------PCIE3:VF4_TPHR_CAP_VER[2]PCIE3:VF4_TPHR_CAP_VER[3]
20 ----------------------------PCIE3:VF5_TPHR_CAP_VER[0]PCIE3:VF5_TPHR_CAP_VER[1]
21 ----------------------------PCIE3:VF5_TPHR_CAP_VER[2]PCIE3:VF5_TPHR_CAP_VER[3]
22 ------------------------------
23 ------------------------------
24 ------------------------------
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC[1]
31 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC[1]
32 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC[1]
33 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC[1]
34 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC[1]
35 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC[1]
36 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC[1]
37 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC[0]PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC[1]
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[1]
41 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[3]
42 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[5]
43 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[7]
44 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[9]
45 ----------------------------PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[10]-
PCIE3 bittile 36
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[1]
1 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[3]
2 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[5]
3 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[7]
4 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[9]
5 ----------------------------PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[10]-
6 ------------------------------
7 ------------------------------
8 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[1]
9 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[3]
10 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[5]
11 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[7]
12 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[9]
13 ----------------------------PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[10]-
14 ------------------------------
15 ------------------------------
16 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[1]
17 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[3]
18 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[5]
19 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[7]
20 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[9]
21 ----------------------------PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[10]-
22 ------------------------------
23 ------------------------------
24 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[1]
25 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[3]
26 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[5]
27 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[7]
28 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[9]
29 ----------------------------PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[10]-
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[1]
33 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[3]
34 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[5]
35 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[7]
36 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[9]
37 ----------------------------PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[10]-
38 ------------------------------
39 ------------------------------
40 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[1]
41 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[3]
42 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[5]
43 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[7]
44 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[9]
45 ----------------------------PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[10]-
PCIE3 bittile 37
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[0]PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[1]
1 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[2]PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[3]
2 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[4]PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[5]
3 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[6]PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[7]
4 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[8]PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[9]
5 ----------------------------PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[10]PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[0]
6 ----------------------------PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[1]PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[2]
7 ------------------------------
8 ----------------------------PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[0]PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[1]
9 ----------------------------PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[2]PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[0]
10 ----------------------------PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[1]PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[2]
11 ----------------------------PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[0]PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[1]
12 ----------------------------PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[2]PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[0]
13 ----------------------------PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[1]PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[2]
14 ----------------------------PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[0]PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[1]
15 ----------------------------PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[2]-
16 ----------------------------PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[0]PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[1]
17 ----------------------------PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[2]PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[0]
18 ----------------------------PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[1]PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[2]
19 ------------------------------
20 ------------------------------
21 ------------------------------
22 ------------------------------
23 ----------------------------PCIE3:GEN3_PCS_AUTO_REALIGN[0]PCIE3:GEN3_PCS_AUTO_REALIGN[1]
24 ----------------------------PCIE3:GEN3_PCS_RX_ELECIDLE_INTERNAL-
25 ------------------------------
26 ------------------------------
27 ------------------------------
28 ------------------------------
29 ------------------------------
30 ------------------------------
31 ------------------------------
32 ----------------------------PCIE3:SPARE_BYTE0[0]PCIE3:SPARE_BYTE0[1]
33 ----------------------------PCIE3:SPARE_BYTE0[2]PCIE3:SPARE_BYTE0[3]
34 ----------------------------PCIE3:SPARE_BYTE0[4]PCIE3:SPARE_BYTE0[5]
35 ----------------------------PCIE3:SPARE_BYTE0[6]PCIE3:SPARE_BYTE0[7]
36 ----------------------------PCIE3:SPARE_BYTE1[0]PCIE3:SPARE_BYTE1[1]
37 ----------------------------PCIE3:SPARE_BYTE1[2]PCIE3:SPARE_BYTE1[3]
38 ----------------------------PCIE3:SPARE_BYTE1[4]PCIE3:SPARE_BYTE1[5]
39 ----------------------------PCIE3:SPARE_BYTE1[6]PCIE3:SPARE_BYTE1[7]
40 ----------------------------PCIE3:SPARE_BYTE2[0]PCIE3:SPARE_BYTE2[1]
41 ----------------------------PCIE3:SPARE_BYTE2[2]PCIE3:SPARE_BYTE2[3]
42 ----------------------------PCIE3:SPARE_BYTE2[4]PCIE3:SPARE_BYTE2[5]
43 ----------------------------PCIE3:SPARE_BYTE2[6]PCIE3:SPARE_BYTE2[7]
44 ----------------------------PCIE3:SPARE_BYTE3[0]PCIE3:SPARE_BYTE3[1]
45 ----------------------------PCIE3:SPARE_BYTE3[2]PCIE3:SPARE_BYTE3[3]
46 ----------------------------PCIE3:SPARE_BYTE3[4]PCIE3:SPARE_BYTE3[5]
47 ----------------------------PCIE3:SPARE_BYTE3[6]PCIE3:SPARE_BYTE3[7]
PCIE3 bittile 38
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:SPARE_WORD0[0]PCIE3:SPARE_WORD0[1]
1 ----------------------------PCIE3:SPARE_WORD0[2]PCIE3:SPARE_WORD0[3]
2 ----------------------------PCIE3:SPARE_WORD0[4]PCIE3:SPARE_WORD0[5]
3 ----------------------------PCIE3:SPARE_WORD0[6]PCIE3:SPARE_WORD0[7]
4 ----------------------------PCIE3:SPARE_WORD0[8]PCIE3:SPARE_WORD0[9]
5 ----------------------------PCIE3:SPARE_WORD0[10]PCIE3:SPARE_WORD0[11]
6 ----------------------------PCIE3:SPARE_WORD0[12]PCIE3:SPARE_WORD0[13]
7 ----------------------------PCIE3:SPARE_WORD0[14]PCIE3:SPARE_WORD0[15]
8 ----------------------------PCIE3:SPARE_WORD0[16]PCIE3:SPARE_WORD0[17]
9 ----------------------------PCIE3:SPARE_WORD0[18]PCIE3:SPARE_WORD0[19]
10 ----------------------------PCIE3:SPARE_WORD0[20]PCIE3:SPARE_WORD0[21]
11 ----------------------------PCIE3:SPARE_WORD0[22]PCIE3:SPARE_WORD0[23]
12 ----------------------------PCIE3:SPARE_WORD0[24]PCIE3:SPARE_WORD0[25]
13 ----------------------------PCIE3:SPARE_WORD0[26]PCIE3:SPARE_WORD0[27]
14 ----------------------------PCIE3:SPARE_WORD0[28]PCIE3:SPARE_WORD0[29]
15 ----------------------------PCIE3:SPARE_WORD0[30]PCIE3:SPARE_WORD0[31]
16 ----------------------------PCIE3:SPARE_WORD1[0]PCIE3:SPARE_WORD1[1]
17 ----------------------------PCIE3:SPARE_WORD1[2]PCIE3:SPARE_WORD1[3]
18 ----------------------------PCIE3:SPARE_WORD1[4]PCIE3:SPARE_WORD1[5]
19 ----------------------------PCIE3:SPARE_WORD1[6]PCIE3:SPARE_WORD1[7]
20 ----------------------------PCIE3:SPARE_WORD1[8]PCIE3:SPARE_WORD1[9]
21 ----------------------------PCIE3:SPARE_WORD1[10]PCIE3:SPARE_WORD1[11]
22 ----------------------------PCIE3:SPARE_WORD1[12]PCIE3:SPARE_WORD1[13]
23 ----------------------------PCIE3:SPARE_WORD1[14]PCIE3:SPARE_WORD1[15]
24 ----------------------------PCIE3:SPARE_WORD1[16]PCIE3:SPARE_WORD1[17]
25 ----------------------------PCIE3:SPARE_WORD1[18]PCIE3:SPARE_WORD1[19]
26 ----------------------------PCIE3:SPARE_WORD1[20]PCIE3:SPARE_WORD1[21]
27 ----------------------------PCIE3:SPARE_WORD1[22]PCIE3:SPARE_WORD1[23]
28 ----------------------------PCIE3:SPARE_WORD1[24]PCIE3:SPARE_WORD1[25]
29 ----------------------------PCIE3:SPARE_WORD1[26]PCIE3:SPARE_WORD1[27]
30 ----------------------------PCIE3:SPARE_WORD1[28]PCIE3:SPARE_WORD1[29]
31 ----------------------------PCIE3:SPARE_WORD1[30]PCIE3:SPARE_WORD1[31]
32 ----------------------------PCIE3:SPARE_WORD2[0]PCIE3:SPARE_WORD2[1]
33 ----------------------------PCIE3:SPARE_WORD2[2]PCIE3:SPARE_WORD2[3]
34 ----------------------------PCIE3:SPARE_WORD2[4]PCIE3:SPARE_WORD2[5]
35 ----------------------------PCIE3:SPARE_WORD2[6]PCIE3:SPARE_WORD2[7]
36 ----------------------------PCIE3:SPARE_WORD2[8]PCIE3:SPARE_WORD2[9]
37 ----------------------------PCIE3:SPARE_WORD2[10]PCIE3:SPARE_WORD2[11]
38 ----------------------------PCIE3:SPARE_WORD2[12]PCIE3:SPARE_WORD2[13]
39 ----------------------------PCIE3:SPARE_WORD2[14]PCIE3:SPARE_WORD2[15]
40 ----------------------------PCIE3:SPARE_WORD2[16]PCIE3:SPARE_WORD2[17]
41 ----------------------------PCIE3:SPARE_WORD2[18]PCIE3:SPARE_WORD2[19]
42 ----------------------------PCIE3:SPARE_WORD2[20]PCIE3:SPARE_WORD2[21]
43 ----------------------------PCIE3:SPARE_WORD2[22]PCIE3:SPARE_WORD2[23]
44 ----------------------------PCIE3:SPARE_WORD2[24]PCIE3:SPARE_WORD2[25]
45 ----------------------------PCIE3:SPARE_WORD2[26]PCIE3:SPARE_WORD2[27]
46 ----------------------------PCIE3:SPARE_WORD2[28]PCIE3:SPARE_WORD2[29]
47 ----------------------------PCIE3:SPARE_WORD2[30]PCIE3:SPARE_WORD2[31]
PCIE3 bittile 39
RowColumn
01234567891011121314151617181920212223242526272829
0 ----------------------------PCIE3:SPARE_WORD3[0]PCIE3:SPARE_WORD3[1]
1 ----------------------------PCIE3:SPARE_WORD3[2]PCIE3:SPARE_WORD3[3]
2 ----------------------------PCIE3:SPARE_WORD3[4]PCIE3:SPARE_WORD3[5]
3 ----------------------------PCIE3:SPARE_WORD3[6]PCIE3:SPARE_WORD3[7]
4 ----------------------------PCIE3:SPARE_WORD3[8]PCIE3:SPARE_WORD3[9]
5 ----------------------------PCIE3:SPARE_WORD3[10]PCIE3:SPARE_WORD3[11]
6 ----------------------------PCIE3:SPARE_WORD3[12]PCIE3:SPARE_WORD3[13]
7 ----------------------------PCIE3:SPARE_WORD3[14]PCIE3:SPARE_WORD3[15]
8 ----------------------------PCIE3:SPARE_WORD3[16]PCIE3:SPARE_WORD3[17]
9 ----------------------------PCIE3:SPARE_WORD3[18]PCIE3:SPARE_WORD3[19]
10 ----------------------------PCIE3:SPARE_WORD3[20]PCIE3:SPARE_WORD3[21]
11 ----------------------------PCIE3:SPARE_WORD3[22]PCIE3:SPARE_WORD3[23]
12 ----------------------------PCIE3:SPARE_WORD3[24]PCIE3:SPARE_WORD3[25]
13 ----------------------------PCIE3:SPARE_WORD3[26]PCIE3:SPARE_WORD3[27]
14 ----------------------------PCIE3:SPARE_WORD3[28]PCIE3:SPARE_WORD3[29]
15 ----------------------------PCIE3:SPARE_WORD3[30]PCIE3:SPARE_WORD3[31]
PCIE3:ARI_CAP_ENABLE[25, 28, 24]
PCIE3:AXISTEN_IF_CC_ALIGNMENT_MODE[0, 28, 3]
PCIE3:AXISTEN_IF_CC_PARITY_CHK[0, 29, 17]
PCIE3:AXISTEN_IF_CQ_ALIGNMENT_MODE[0, 29, 2]
PCIE3:AXISTEN_IF_ENABLE_CLIENT_TAG[0, 28, 18]
PCIE3:AXISTEN_IF_ENABLE_RX_MSG_INTFC[0, 28, 5]
PCIE3:AXISTEN_IF_RC_ALIGNMENT_MODE[0, 28, 4]
PCIE3:AXISTEN_IF_RC_STRADDLE[0, 29, 4]
PCIE3:AXISTEN_IF_RQ_ALIGNMENT_MODE[0, 29, 3]
PCIE3:AXISTEN_IF_RQ_PARITY_CHK[0, 28, 17]
PCIE3:CRM_CORE_CLK_FREQ_500[0, 28, 0]
PCIE3:GEN3_PCS_RX_ELECIDLE_INTERNAL[37, 28, 24]
PCIE3:LL_ACK_TIMEOUT_EN[4, 28, 6]
PCIE3:LL_CPL_FC_UPDATE_TIMER_OVERRIDE[4, 29, 21]
PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE[5, 28, 16]
PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE[5, 28, 0]
PCIE3:LL_P_FC_UPDATE_TIMER_OVERRIDE[4, 28, 32]
PCIE3:LL_REPLAY_TIMEOUT_EN[4, 29, 13]
PCIE3:LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE[27, 29, 45]
PCIE3:LTR_TX_MESSAGE_ON_LTR_ENABLE[27, 28, 45]
PCIE3:PF0_AER_CAP_ECRC_CHECK_CAPABLE[25, 28, 22]
PCIE3:PF0_AER_CAP_ECRC_GEN_CAPABLE[25, 28, 23]
Non-inverted[0]
PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[0, 29, 16][0, 28, 16][0, 29, 15][0, 28, 15][0, 29, 14][0, 28, 14][0, 29, 13][0, 28, 13][0, 29, 12][0, 28, 12][0, 29, 11][0, 28, 11][0, 29, 10][0, 28, 10][0, 29, 9][0, 28, 9][0, 29, 8][0, 28, 8]
Non-inverted[17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:LL_CPL_FC_UPDATE_TIMER[4, 29, 31][4, 28, 31][4, 29, 30][4, 28, 30][4, 29, 29][4, 28, 29][4, 29, 28][4, 28, 28][4, 29, 27][4, 28, 27][4, 29, 26][4, 28, 26][4, 29, 25][4, 28, 25][4, 29, 24][4, 28, 24]
PCIE3:LL_FC_UPDATE_TIMER[5, 29, 31][5, 28, 31][5, 29, 30][5, 28, 30][5, 29, 29][5, 28, 29][5, 29, 28][5, 28, 28][5, 29, 27][5, 28, 27][5, 29, 26][5, 28, 26][5, 29, 25][5, 28, 25][5, 29, 24][5, 28, 24]
PCIE3:LL_NP_FC_UPDATE_TIMER[5, 29, 15][5, 28, 15][5, 29, 14][5, 28, 14][5, 29, 13][5, 28, 13][5, 29, 12][5, 28, 12][5, 29, 11][5, 28, 11][5, 29, 10][5, 28, 10][5, 29, 9][5, 28, 9][5, 29, 8][5, 28, 8]
PCIE3:LL_P_FC_UPDATE_TIMER[4, 29, 47][4, 28, 47][4, 29, 46][4, 28, 46][4, 29, 45][4, 28, 45][4, 29, 44][4, 28, 44][4, 29, 43][4, 28, 43][4, 29, 42][4, 28, 42][4, 29, 41][4, 28, 41][4, 29, 40][4, 28, 40]
PCIE3:PF0_DEVICE_ID[7, 29, 23][7, 28, 23][7, 29, 22][7, 28, 22][7, 29, 21][7, 28, 21][7, 29, 20][7, 28, 20][7, 29, 19][7, 28, 19][7, 29, 18][7, 28, 18][7, 29, 17][7, 28, 17][7, 29, 16][7, 28, 16]
PCIE3:PF0_SRIOV_CAP_INITIAL_VF[30, 29, 31][30, 28, 31][30, 29, 30][30, 28, 30][30, 29, 29][30, 28, 29][30, 29, 28][30, 28, 28][30, 29, 27][30, 28, 27][30, 29, 26][30, 28, 26][30, 29, 25][30, 28, 25][30, 29, 24][30, 28, 24]
PCIE3:PF0_SRIOV_CAP_TOTAL_VF[30, 29, 47][30, 28, 47][30, 29, 46][30, 28, 46][30, 29, 45][30, 28, 45][30, 29, 44][30, 28, 44][30, 29, 43][30, 28, 43][30, 29, 42][30, 28, 42][30, 29, 41][30, 28, 41][30, 29, 40][30, 28, 40]
PCIE3:PF0_SRIOV_FIRST_VF_OFFSET[31, 29, 31][31, 28, 31][31, 29, 30][31, 28, 30][31, 29, 29][31, 28, 29][31, 29, 28][31, 28, 28][31, 29, 27][31, 28, 27][31, 29, 26][31, 28, 26][31, 29, 25][31, 28, 25][31, 29, 24][31, 28, 24]
PCIE3:PF0_SRIOV_FUNC_DEP_LINK[31, 29, 15][31, 28, 15][31, 29, 14][31, 28, 14][31, 29, 13][31, 28, 13][31, 29, 12][31, 28, 12][31, 29, 11][31, 28, 11][31, 29, 10][31, 28, 10][31, 29, 9][31, 28, 9][31, 29, 8][31, 28, 8]
PCIE3:PF0_SRIOV_VF_DEVICE_ID[31, 29, 47][31, 28, 47][31, 29, 46][31, 28, 46][31, 29, 45][31, 28, 45][31, 29, 44][31, 28, 44][31, 29, 43][31, 28, 43][31, 29, 42][31, 28, 42][31, 29, 41][31, 28, 41][31, 29, 40][31, 28, 40]
PCIE3:PF0_SUBSYSTEM_ID[8, 29, 31][8, 28, 31][8, 29, 30][8, 28, 30][8, 29, 29][8, 28, 29][8, 29, 28][8, 28, 28][8, 29, 27][8, 28, 27][8, 29, 26][8, 28, 26][8, 29, 25][8, 28, 25][8, 29, 24][8, 28, 24]
PCIE3:PF1_DEVICE_ID[7, 29, 31][7, 28, 31][7, 29, 30][7, 28, 30][7, 29, 29][7, 28, 29][7, 29, 28][7, 28, 28][7, 29, 27][7, 28, 27][7, 29, 26][7, 28, 26][7, 29, 25][7, 28, 25][7, 29, 24][7, 28, 24]
PCIE3:PF1_SRIOV_CAP_INITIAL_VF[30, 29, 39][30, 28, 39][30, 29, 38][30, 28, 38][30, 29, 37][30, 28, 37][30, 29, 36][30, 28, 36][30, 29, 35][30, 28, 35][30, 29, 34][30, 28, 34][30, 29, 33][30, 28, 33][30, 29, 32][30, 28, 32]
PCIE3:PF1_SRIOV_CAP_TOTAL_VF[31, 29, 7][31, 28, 7][31, 29, 6][31, 28, 6][31, 29, 5][31, 28, 5][31, 29, 4][31, 28, 4][31, 29, 3][31, 28, 3][31, 29, 2][31, 28, 2][31, 29, 1][31, 28, 1][31, 29, 0][31, 28, 0]
PCIE3:PF1_SRIOV_FIRST_VF_OFFSET[31, 29, 39][31, 28, 39][31, 29, 38][31, 28, 38][31, 29, 37][31, 28, 37][31, 29, 36][31, 28, 36][31, 29, 35][31, 28, 35][31, 29, 34][31, 28, 34][31, 29, 33][31, 28, 33][31, 29, 32][31, 28, 32]
PCIE3:PF1_SRIOV_FUNC_DEP_LINK[31, 29, 23][31, 28, 23][31, 29, 22][31, 28, 22][31, 29, 21][31, 28, 21][31, 29, 20][31, 28, 20][31, 29, 19][31, 28, 19][31, 29, 18][31, 28, 18][31, 29, 17][31, 28, 17][31, 29, 16][31, 28, 16]
PCIE3:PF1_SRIOV_VF_DEVICE_ID[32, 29, 7][32, 28, 7][32, 29, 6][32, 28, 6][32, 29, 5][32, 28, 5][32, 29, 4][32, 28, 4][32, 29, 3][32, 28, 3][32, 29, 2][32, 28, 2][32, 29, 1][32, 28, 1][32, 29, 0][32, 28, 0]
PCIE3:PF1_SUBSYSTEM_ID[8, 29, 39][8, 28, 39][8, 29, 38][8, 28, 38][8, 29, 37][8, 28, 37][8, 29, 36][8, 28, 36][8, 29, 35][8, 28, 35][8, 29, 34][8, 28, 34][8, 29, 33][8, 28, 33][8, 29, 32][8, 28, 32]
PCIE3:PL_LANE0_EQ_CONTROL[2, 29, 39][2, 28, 39][2, 29, 38][2, 28, 38][2, 29, 37][2, 28, 37][2, 29, 36][2, 28, 36][2, 29, 35][2, 28, 35][2, 29, 34][2, 28, 34][2, 29, 33][2, 28, 33][2, 29, 32][2, 28, 32]
PCIE3:PL_LANE1_EQ_CONTROL[2, 29, 47][2, 28, 47][2, 29, 46][2, 28, 46][2, 29, 45][2, 28, 45][2, 29, 44][2, 28, 44][2, 29, 43][2, 28, 43][2, 29, 42][2, 28, 42][2, 29, 41][2, 28, 41][2, 29, 40][2, 28, 40]
PCIE3:PL_LANE2_EQ_CONTROL[3, 29, 7][3, 28, 7][3, 29, 6][3, 28, 6][3, 29, 5][3, 28, 5][3, 29, 4][3, 28, 4][3, 29, 3][3, 28, 3][3, 29, 2][3, 28, 2][3, 29, 1][3, 28, 1][3, 29, 0][3, 28, 0]
PCIE3:PL_LANE3_EQ_CONTROL[3, 29, 15][3, 28, 15][3, 29, 14][3, 28, 14][3, 29, 13][3, 28, 13][3, 29, 12][3, 28, 12][3, 29, 11][3, 28, 11][3, 29, 10][3, 28, 10][3, 29, 9][3, 28, 9][3, 29, 8][3, 28, 8]
PCIE3:PL_LANE4_EQ_CONTROL[3, 29, 23][3, 28, 23][3, 29, 22][3, 28, 22][3, 29, 21][3, 28, 21][3, 29, 20][3, 28, 20][3, 29, 19][3, 28, 19][3, 29, 18][3, 28, 18][3, 29, 17][3, 28, 17][3, 29, 16][3, 28, 16]
PCIE3:PL_LANE5_EQ_CONTROL[3, 29, 31][3, 28, 31][3, 29, 30][3, 28, 30][3, 29, 29][3, 28, 29][3, 29, 28][3, 28, 28][3, 29, 27][3, 28, 27][3, 29, 26][3, 28, 26][3, 29, 25][3, 28, 25][3, 29, 24][3, 28, 24]
PCIE3:PL_LANE6_EQ_CONTROL[3, 29, 39][3, 28, 39][3, 29, 38][3, 28, 38][3, 29, 37][3, 28, 37][3, 29, 36][3, 28, 36][3, 29, 35][3, 28, 35][3, 29, 34][3, 28, 34][3, 29, 33][3, 28, 33][3, 29, 32][3, 28, 32]
PCIE3:PL_LANE7_EQ_CONTROL[3, 29, 47][3, 28, 47][3, 29, 46][3, 28, 46][3, 29, 45][3, 28, 45][3, 29, 44][3, 28, 44][3, 29, 43][3, 28, 43][3, 29, 42][3, 28, 42][3, 29, 41][3, 28, 41][3, 29, 40][3, 28, 40]
PCIE3:PM_ASPML0S_TIMEOUT[0, 29, 31][0, 28, 31][0, 29, 30][0, 28, 30][0, 29, 29][0, 28, 29][0, 29, 28][0, 28, 28][0, 29, 27][0, 28, 27][0, 29, 26][0, 28, 26][0, 29, 25][0, 28, 25][0, 29, 24][0, 28, 24]
PCIE3:PM_PME_TURNOFF_ACK_DELAY[1, 29, 39][1, 28, 39][1, 29, 38][1, 28, 38][1, 29, 37][1, 28, 37][1, 29, 36][1, 28, 36][1, 29, 35][1, 28, 35][1, 29, 34][1, 28, 34][1, 29, 33][1, 28, 33][1, 29, 32][1, 28, 32]
Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE[32, 29, 23][32, 28, 23][32, 29, 22][32, 28, 22][32, 29, 21][32, 28, 21][32, 29, 20][32, 28, 20][32, 29, 19][32, 28, 19][32, 29, 18][32, 28, 18][32, 29, 17][32, 28, 17][32, 29, 16][32, 28, 16][32, 29, 15][32, 28, 15][32, 29, 14][32, 28, 14][32, 29, 13][32, 28, 13][32, 29, 12][32, 28, 12][32, 29, 11][32, 28, 11][32, 29, 10][32, 28, 10][32, 29, 9][32, 28, 9][32, 29, 8][32, 28, 8]
PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE[32, 29, 39][32, 28, 39][32, 29, 38][32, 28, 38][32, 29, 37][32, 28, 37][32, 29, 36][32, 28, 36][32, 29, 35][32, 28, 35][32, 29, 34][32, 28, 34][32, 29, 33][32, 28, 33][32, 29, 32][32, 28, 32][32, 29, 31][32, 28, 31][32, 29, 30][32, 28, 30][32, 29, 29][32, 28, 29][32, 29, 28][32, 28, 28][32, 29, 27][32, 28, 27][32, 29, 26][32, 28, 26][32, 29, 25][32, 28, 25][32, 29, 24][32, 28, 24]
PCIE3:PM_L1_REENTRY_DELAY[0, 29, 47][0, 28, 47][0, 29, 46][0, 28, 46][0, 29, 45][0, 28, 45][0, 29, 44][0, 28, 44][0, 29, 43][0, 28, 43][0, 29, 42][0, 28, 42][0, 29, 41][0, 28, 41][0, 29, 40][0, 28, 40][0, 29, 39][0, 28, 39][0, 29, 38][0, 28, 38][0, 29, 37][0, 28, 37][0, 29, 36][0, 28, 36][0, 29, 35][0, 28, 35][0, 29, 34][0, 28, 34][0, 29, 33][0, 28, 33][0, 29, 32][0, 28, 32]
PCIE3:SPARE_WORD0[38, 29, 15][38, 28, 15][38, 29, 14][38, 28, 14][38, 29, 13][38, 28, 13][38, 29, 12][38, 28, 12][38, 29, 11][38, 28, 11][38, 29, 10][38, 28, 10][38, 29, 9][38, 28, 9][38, 29, 8][38, 28, 8][38, 29, 7][38, 28, 7][38, 29, 6][38, 28, 6][38, 29, 5][38, 28, 5][38, 29, 4][38, 28, 4][38, 29, 3][38, 28, 3][38, 29, 2][38, 28, 2][38, 29, 1][38, 28, 1][38, 29, 0][38, 28, 0]
PCIE3:SPARE_WORD1[38, 29, 31][38, 28, 31][38, 29, 30][38, 28, 30][38, 29, 29][38, 28, 29][38, 29, 28][38, 28, 28][38, 29, 27][38, 28, 27][38, 29, 26][38, 28, 26][38, 29, 25][38, 28, 25][38, 29, 24][38, 28, 24][38, 29, 23][38, 28, 23][38, 29, 22][38, 28, 22][38, 29, 21][38, 28, 21][38, 29, 20][38, 28, 20][38, 29, 19][38, 28, 19][38, 29, 18][38, 28, 18][38, 29, 17][38, 28, 17][38, 29, 16][38, 28, 16]
PCIE3:SPARE_WORD2[38, 29, 47][38, 28, 47][38, 29, 46][38, 28, 46][38, 29, 45][38, 28, 45][38, 29, 44][38, 28, 44][38, 29, 43][38, 28, 43][38, 29, 42][38, 28, 42][38, 29, 41][38, 28, 41][38, 29, 40][38, 28, 40][38, 29, 39][38, 28, 39][38, 29, 38][38, 28, 38][38, 29, 37][38, 28, 37][38, 29, 36][38, 28, 36][38, 29, 35][38, 28, 35][38, 29, 34][38, 28, 34][38, 29, 33][38, 28, 33][38, 29, 32][38, 28, 32]
PCIE3:SPARE_WORD3[39, 29, 15][39, 28, 15][39, 29, 14][39, 28, 14][39, 29, 13][39, 28, 13][39, 29, 12][39, 28, 12][39, 29, 11][39, 28, 11][39, 29, 10][39, 28, 10][39, 29, 9][39, 28, 9][39, 29, 8][39, 28, 8][39, 29, 7][39, 28, 7][39, 29, 6][39, 28, 6][39, 29, 5][39, 28, 5][39, 29, 4][39, 28, 4][39, 29, 3][39, 28, 3][39, 29, 2][39, 28, 2][39, 29, 1][39, 28, 1][39, 29, 0][39, 28, 0]
Non-inverted[31][30][29][28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:AXISTEN_IF_WIDTH[0, 28, 2][0, 29, 1]
PCIE3:CRM_USER_CLK_FREQ[0, 28, 1][0, 29, 0]
PCIE3:GEN3_PCS_AUTO_REALIGN[37, 29, 23][37, 28, 23]
PCIE3:LL_ACK_TIMEOUT_FUNC[4, 28, 13][4, 29, 12]
PCIE3:LL_REPLAY_TIMEOUT_FUNC[4, 28, 21][4, 29, 20]
PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[11, 29, 14][11, 28, 14]
PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC[35, 29, 30][35, 28, 30]
PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC[35, 29, 31][35, 28, 31]
PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT[4, 29, 3][4, 28, 3]
PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC[35, 29, 32][35, 28, 32]
PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC[35, 29, 33][35, 28, 33]
PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC[35, 29, 34][35, 28, 34]
PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC[35, 29, 35][35, 28, 35]
PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC[35, 29, 36][35, 28, 36]
PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC[35, 29, 37][35, 28, 37]
Non-inverted[1][0]
PCIE3:PF0_RBAR_CAP_SIZE0[21, 29, 41][21, 28, 41][21, 29, 40][21, 28, 40][21, 29, 39][21, 28, 39][21, 29, 38][21, 28, 38][21, 29, 37][21, 28, 37][21, 29, 36][21, 28, 36][21, 29, 35][21, 28, 35][21, 29, 34][21, 28, 34][21, 29, 33][21, 28, 33][21, 29, 32][21, 28, 32]
PCIE3:PF0_RBAR_CAP_SIZE1[22, 29, 25][22, 28, 25][22, 29, 24][22, 28, 24][22, 29, 23][22, 28, 23][22, 29, 22][22, 28, 22][22, 29, 21][22, 28, 21][22, 29, 20][22, 28, 20][22, 29, 19][22, 28, 19][22, 29, 18][22, 28, 18][22, 29, 17][22, 28, 17][22, 29, 16][22, 28, 16]
PCIE3:PF0_RBAR_CAP_SIZE2[23, 29, 9][23, 28, 9][23, 29, 8][23, 28, 8][23, 29, 7][23, 28, 7][23, 29, 6][23, 28, 6][23, 29, 5][23, 28, 5][23, 29, 4][23, 28, 4][23, 29, 3][23, 28, 3][23, 29, 2][23, 28, 2][23, 29, 1][23, 28, 1][23, 29, 0][23, 28, 0]
PCIE3:PF1_RBAR_CAP_SIZE0[22, 29, 9][22, 28, 9][22, 29, 8][22, 28, 8][22, 29, 7][22, 28, 7][22, 29, 6][22, 28, 6][22, 29, 5][22, 28, 5][22, 29, 4][22, 28, 4][22, 29, 3][22, 28, 3][22, 29, 2][22, 28, 2][22, 29, 1][22, 28, 1][22, 29, 0][22, 28, 0]
PCIE3:PF1_RBAR_CAP_SIZE1[22, 29, 41][22, 28, 41][22, 29, 40][22, 28, 40][22, 29, 39][22, 28, 39][22, 29, 38][22, 28, 38][22, 29, 37][22, 28, 37][22, 29, 36][22, 28, 36][22, 29, 35][22, 28, 35][22, 29, 34][22, 28, 34][22, 29, 33][22, 28, 33][22, 29, 32][22, 28, 32]
PCIE3:PF1_RBAR_CAP_SIZE2[23, 29, 25][23, 28, 25][23, 29, 24][23, 28, 24][23, 29, 23][23, 28, 23][23, 29, 22][23, 28, 22][23, 29, 21][23, 28, 21][23, 29, 20][23, 28, 20][23, 29, 19][23, 28, 19][23, 29, 18][23, 28, 18][23, 29, 17][23, 28, 17][23, 29, 16][23, 28, 16]
PCIE3:PM_ASPML1_ENTRY_DELAY[1, 29, 9][1, 28, 9][1, 29, 8][1, 28, 8][1, 29, 7][1, 28, 7][1, 29, 6][1, 28, 6][1, 29, 5][1, 28, 5][1, 29, 4][1, 28, 4][1, 29, 3][1, 28, 3][1, 29, 2][1, 28, 2][1, 29, 1][1, 28, 1][1, 29, 0][1, 28, 0]
PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[1, 29, 25][1, 28, 25][1, 29, 24][1, 28, 24][1, 29, 23][1, 28, 23][1, 29, 22][1, 28, 22][1, 29, 21][1, 28, 21][1, 29, 20][1, 28, 20][1, 29, 19][1, 28, 19][1, 29, 18][1, 28, 18][1, 29, 17][1, 28, 17][1, 29, 16][1, 28, 16]
Non-inverted[19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:PF0_ARI_CAP_VER[26, 29, 39][26, 28, 39][26, 29, 38][26, 28, 38]
PCIE3:PF0_DPA_CAP_VER[28, 29, 23][28, 28, 23][28, 29, 22][28, 28, 22]
PCIE3:PF0_LTR_CAP_VER[27, 29, 31][27, 28, 31][27, 29, 30][27, 28, 30]
PCIE3:PF0_PB_CAP_VER[27, 29, 15][27, 28, 15][27, 29, 14][27, 28, 14]
PCIE3:PF0_RBAR_CAP_VER[21, 29, 1][21, 28, 1][21, 29, 0][21, 28, 0]
PCIE3:PF0_SRIOV_CAP_VER[30, 29, 15][30, 28, 15][30, 29, 14][30, 28, 14]
PCIE3:PF0_TPHR_CAP_VER[35, 29, 7][35, 28, 7][35, 29, 6][35, 28, 6]
PCIE3:PF0_VC_CAP_VER[23, 29, 47][23, 28, 47][23, 29, 46][23, 28, 46]
PCIE3:PF1_DPA_CAP_VER[28, 29, 25][28, 28, 25][28, 29, 24][28, 28, 24]
PCIE3:PF1_PB_CAP_VER[27, 29, 17][27, 28, 17][27, 29, 16][27, 28, 16]
PCIE3:PF1_RBAR_CAP_VER[21, 29, 3][21, 28, 3][21, 29, 2][21, 28, 2]
PCIE3:PF1_SRIOV_CAP_VER[30, 29, 17][30, 28, 17][30, 29, 16][30, 28, 16]
PCIE3:PF1_TPHR_CAP_VER[35, 29, 9][35, 28, 9][35, 29, 8][35, 28, 8]
PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[1, 28, 42][1, 29, 41][1, 28, 41][1, 29, 40]
PCIE3:VF0_TPHR_CAP_VER[35, 29, 11][35, 28, 11][35, 29, 10][35, 28, 10]
PCIE3:VF1_TPHR_CAP_VER[35, 29, 13][35, 28, 13][35, 29, 12][35, 28, 12]
PCIE3:VF2_TPHR_CAP_VER[35, 29, 15][35, 28, 15][35, 29, 14][35, 28, 14]
PCIE3:VF3_TPHR_CAP_VER[35, 29, 17][35, 28, 17][35, 29, 16][35, 28, 16]
PCIE3:VF4_TPHR_CAP_VER[35, 29, 19][35, 28, 19][35, 29, 18][35, 28, 18]
PCIE3:VF5_TPHR_CAP_VER[35, 29, 21][35, 28, 21][35, 29, 20][35, 28, 20]
Non-inverted[3][2][1][0]
PCIE3:PF0_BAR0_CONTROL[9, 28, 25][9, 29, 24][9, 28, 24]
PCIE3:PF0_BAR1_CONTROL[9, 28, 33][9, 29, 32][9, 28, 32]
PCIE3:PF0_BAR2_CONTROL[9, 28, 41][9, 29, 40][9, 28, 40]
PCIE3:PF0_BAR3_CONTROL[10, 28, 1][10, 29, 0][10, 28, 0]
PCIE3:PF0_BAR4_CONTROL[10, 28, 9][10, 29, 8][10, 28, 8]
PCIE3:PF0_BAR5_CONTROL[10, 28, 17][10, 29, 16][10, 28, 16]
PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[10, 28, 35][10, 29, 34][10, 28, 34]
PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[10, 29, 36][10, 28, 36][10, 29, 35]
PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[10, 28, 31][10, 29, 30][10, 28, 30]
PCIE3:PF0_INTERRUPT_PIN[8, 28, 41][8, 29, 40][8, 28, 40]
PCIE3:PF0_PM_CAP_VER_ID[20, 28, 35][20, 29, 34][20, 28, 34]
PCIE3:PF0_RBAR_CAP_INDEX0[21, 29, 26][21, 28, 26][21, 29, 25]
PCIE3:PF0_RBAR_CAP_INDEX1[22, 28, 11][22, 29, 10][22, 28, 10]
PCIE3:PF0_RBAR_CAP_INDEX2[22, 28, 43][22, 29, 42][22, 28, 42]
PCIE3:PF0_RBAR_NUM[21, 28, 23][21, 29, 22][21, 28, 22]
PCIE3:PF0_SRIOV_BAR0_CONTROL[32, 28, 41][32, 29, 40][32, 28, 40]
PCIE3:PF0_SRIOV_BAR1_CONTROL[33, 28, 1][33, 29, 0][33, 28, 0]
PCIE3:PF0_SRIOV_BAR2_CONTROL[33, 28, 9][33, 29, 8][33, 28, 8]
PCIE3:PF0_SRIOV_BAR3_CONTROL[33, 28, 17][33, 29, 16][33, 28, 16]
PCIE3:PF0_SRIOV_BAR4_CONTROL[33, 28, 25][33, 29, 24][33, 28, 24]
PCIE3:PF0_SRIOV_BAR5_CONTROL[33, 28, 33][33, 29, 32][33, 28, 32]
PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[37, 29, 6][37, 28, 6][37, 29, 5]
PCIE3:PF1_BAR0_CONTROL[9, 29, 26][9, 28, 26][9, 29, 25]
PCIE3:PF1_BAR1_CONTROL[9, 29, 34][9, 28, 34][9, 29, 33]
PCIE3:PF1_BAR2_CONTROL[9, 29, 42][9, 28, 42][9, 29, 41]
PCIE3:PF1_BAR3_CONTROL[10, 29, 2][10, 28, 2][10, 29, 1]
PCIE3:PF1_BAR4_CONTROL[10, 29, 10][10, 28, 10][10, 29, 9]
PCIE3:PF1_BAR5_CONTROL[10, 29, 18][10, 28, 18][10, 29, 17]
PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[10, 28, 33][10, 29, 32][10, 28, 32]
PCIE3:PF1_INTERRUPT_PIN[8, 29, 42][8, 28, 42][8, 29, 41]
PCIE3:PF1_PM_CAP_VER_ID[20, 29, 36][20, 28, 36][20, 29, 35]
PCIE3:PF1_RBAR_CAP_INDEX0[21, 28, 28][21, 29, 27][21, 28, 27]
PCIE3:PF1_RBAR_CAP_INDEX1[22, 29, 12][22, 28, 12][22, 29, 11]
PCIE3:PF1_RBAR_CAP_INDEX2[22, 29, 44][22, 28, 44][22, 29, 43]
PCIE3:PF1_RBAR_NUM[21, 28, 25][21, 29, 24][21, 28, 24]
PCIE3:PF1_SRIOV_BAR0_CONTROL[32, 29, 42][32, 28, 42][32, 29, 41]
PCIE3:PF1_SRIOV_BAR1_CONTROL[33, 29, 2][33, 28, 2][33, 29, 1]
PCIE3:PF1_SRIOV_BAR2_CONTROL[33, 29, 10][33, 28, 10][33, 29, 9]
PCIE3:PF1_SRIOV_BAR3_CONTROL[33, 29, 18][33, 28, 18][33, 29, 17]
PCIE3:PF1_SRIOV_BAR4_CONTROL[33, 29, 26][33, 28, 26][33, 29, 25]
PCIE3:PF1_SRIOV_BAR5_CONTROL[33, 29, 34][33, 28, 34][33, 29, 33]
PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[37, 28, 9][37, 29, 8][37, 28, 8]
PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[1, 29, 43][1, 28, 43][1, 29, 42]
PCIE3:VF0_PM_CAP_VER_ID[20, 28, 38][20, 29, 37][20, 28, 37]
PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[37, 29, 10][37, 28, 10][37, 29, 9]
PCIE3:VF1_PM_CAP_VER_ID[20, 29, 39][20, 28, 39][20, 29, 38]
PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[37, 28, 12][37, 29, 11][37, 28, 11]
PCIE3:VF2_PM_CAP_VER_ID[20, 28, 41][20, 29, 40][20, 28, 40]
PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[37, 29, 13][37, 28, 13][37, 29, 12]
PCIE3:VF3_PM_CAP_VER_ID[20, 29, 42][20, 28, 42][20, 29, 41]
PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[37, 28, 15][37, 29, 14][37, 28, 14]
PCIE3:VF4_PM_CAP_VER_ID[20, 28, 44][20, 29, 43][20, 28, 43]
PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[37, 28, 17][37, 29, 16][37, 28, 16]
PCIE3:VF5_PM_CAP_VER_ID[20, 29, 45][20, 28, 45][20, 29, 44]
PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[37, 29, 18][37, 28, 18][37, 29, 17]
Non-inverted[2][1][0]
PCIE3:DNSTREAM_LINK_NUM[23, 29, 29][23, 28, 29][23, 29, 28][23, 28, 28][23, 29, 27][23, 28, 27][23, 29, 26][23, 28, 26]
PCIE3:PF0_ARI_CAP_NEXT_FUNC[26, 29, 43][26, 28, 43][26, 29, 42][26, 28, 42][26, 29, 41][26, 28, 41][26, 29, 40][26, 28, 40]
PCIE3:PF0_BIST_REGISTER[9, 29, 7][9, 28, 7][9, 29, 6][9, 28, 6][9, 29, 5][9, 28, 5][9, 29, 4][9, 28, 4]
PCIE3:PF0_CAPABILITY_POINTER[9, 29, 15][9, 28, 15][9, 29, 14][9, 28, 14][9, 29, 13][9, 28, 13][9, 29, 12][9, 28, 12]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[28, 29, 35][28, 28, 35][28, 29, 34][28, 28, 34][28, 29, 33][28, 28, 33][28, 29, 32][28, 28, 32]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[28, 29, 43][28, 28, 43][28, 29, 42][28, 28, 42][28, 29, 41][28, 28, 41][28, 29, 40][28, 28, 40]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[29, 29, 3][29, 28, 3][29, 29, 2][29, 28, 2][29, 29, 1][29, 28, 1][29, 29, 0][29, 28, 0]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[29, 29, 11][29, 28, 11][29, 29, 10][29, 28, 10][29, 29, 9][29, 28, 9][29, 29, 8][29, 28, 8]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[29, 29, 19][29, 28, 19][29, 29, 18][29, 28, 18][29, 29, 17][29, 28, 17][29, 29, 16][29, 28, 16]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[29, 29, 27][29, 28, 27][29, 29, 26][29, 28, 26][29, 29, 25][29, 28, 25][29, 29, 24][29, 28, 24]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[29, 29, 35][29, 28, 35][29, 29, 34][29, 28, 34][29, 29, 33][29, 28, 33][29, 29, 32][29, 28, 32]
PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[29, 29, 43][29, 28, 43][29, 29, 42][29, 28, 42][29, 29, 41][29, 28, 41][29, 29, 40][29, 28, 40]
PCIE3:PF0_INTERRUPT_LINE[8, 29, 46][8, 28, 46][8, 29, 45][8, 28, 45][8, 29, 44][8, 28, 44][8, 29, 43][8, 28, 43]
PCIE3:PF0_MSIX_CAP_NEXTPTR[11, 29, 43][11, 28, 43][11, 29, 42][11, 28, 42][11, 29, 41][11, 28, 41][11, 29, 40][11, 28, 40]
PCIE3:PF0_MSI_CAP_NEXTPTR[11, 29, 19][11, 28, 19][11, 29, 18][11, 28, 18][11, 29, 17][11, 28, 17][11, 29, 16][11, 28, 16]
PCIE3:PF0_PM_CAP_ID[19, 29, 19][19, 28, 19][19, 29, 18][19, 28, 18][19, 29, 17][19, 28, 17][19, 29, 16][19, 28, 16]
PCIE3:PF0_PM_CAP_NEXTPTR[20, 29, 3][20, 28, 3][20, 29, 2][20, 28, 2][20, 29, 1][20, 28, 1][20, 29, 0][20, 28, 0]
PCIE3:PF0_REVISION_ID[7, 29, 35][7, 28, 35][7, 29, 34][7, 28, 34][7, 29, 33][7, 28, 33][7, 29, 32][7, 28, 32]
PCIE3:PF1_ARI_CAP_NEXT_FUNC[26, 29, 47][26, 28, 47][26, 29, 46][26, 28, 46][26, 29, 45][26, 28, 45][26, 29, 44][26, 28, 44]
PCIE3:PF1_BIST_REGISTER[9, 29, 11][9, 28, 11][9, 29, 10][9, 28, 10][9, 29, 9][9, 28, 9][9, 29, 8][9, 28, 8]
PCIE3:PF1_CAPABILITY_POINTER[9, 29, 19][9, 28, 19][9, 29, 18][9, 28, 18][9, 29, 17][9, 28, 17][9, 29, 16][9, 28, 16]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0[28, 29, 39][28, 28, 39][28, 29, 38][28, 28, 38][28, 29, 37][28, 28, 37][28, 29, 36][28, 28, 36]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1[28, 29, 47][28, 28, 47][28, 29, 46][28, 28, 46][28, 29, 45][28, 28, 45][28, 29, 44][28, 28, 44]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2[29, 29, 7][29, 28, 7][29, 29, 6][29, 28, 6][29, 29, 5][29, 28, 5][29, 29, 4][29, 28, 4]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3[29, 29, 15][29, 28, 15][29, 29, 14][29, 28, 14][29, 29, 13][29, 28, 13][29, 29, 12][29, 28, 12]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4[29, 29, 23][29, 28, 23][29, 29, 22][29, 28, 22][29, 29, 21][29, 28, 21][29, 29, 20][29, 28, 20]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5[29, 29, 31][29, 28, 31][29, 29, 30][29, 28, 30][29, 29, 29][29, 28, 29][29, 29, 28][29, 28, 28]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6[29, 29, 39][29, 28, 39][29, 29, 38][29, 28, 38][29, 29, 37][29, 28, 37][29, 29, 36][29, 28, 36]
PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7[29, 29, 47][29, 28, 47][29, 29, 46][29, 28, 46][29, 29, 45][29, 28, 45][29, 29, 44][29, 28, 44]
PCIE3:PF1_INTERRUPT_LINE[9, 29, 3][9, 28, 3][9, 29, 2][9, 28, 2][9, 29, 1][9, 28, 1][9, 29, 0][9, 28, 0]
PCIE3:PF1_MSIX_CAP_NEXTPTR[11, 29, 47][11, 28, 47][11, 29, 46][11, 28, 46][11, 29, 45][11, 28, 45][11, 29, 44][11, 28, 44]
PCIE3:PF1_MSI_CAP_NEXTPTR[11, 29, 23][11, 28, 23][11, 29, 22][11, 28, 22][11, 29, 21][11, 28, 21][11, 29, 20][11, 28, 20]
PCIE3:PF1_PM_CAP_ID[19, 29, 23][19, 28, 23][19, 29, 22][19, 28, 22][19, 29, 21][19, 28, 21][19, 29, 20][19, 28, 20]
PCIE3:PF1_PM_CAP_NEXTPTR[20, 29, 7][20, 28, 7][20, 29, 6][20, 28, 6][20, 29, 5][20, 28, 5][20, 29, 4][20, 28, 4]
PCIE3:PF1_REVISION_ID[7, 29, 39][7, 28, 39][7, 29, 38][7, 28, 38][7, 29, 37][7, 28, 37][7, 29, 36][7, 28, 36]
PCIE3:PL_N_FTS_COMCLK_GEN1[2, 29, 3][2, 28, 3][2, 29, 2][2, 28, 2][2, 29, 1][2, 28, 1][2, 29, 0][2, 28, 0]
PCIE3:PL_N_FTS_COMCLK_GEN2[2, 29, 11][2, 28, 11][2, 29, 10][2, 28, 10][2, 29, 9][2, 28, 9][2, 29, 8][2, 28, 8]
PCIE3:PL_N_FTS_COMCLK_GEN3[2, 29, 19][2, 28, 19][2, 29, 18][2, 28, 18][2, 29, 17][2, 28, 17][2, 29, 16][2, 28, 16]
PCIE3:PL_N_FTS_GEN1[2, 29, 7][2, 28, 7][2, 29, 6][2, 28, 6][2, 29, 5][2, 28, 5][2, 29, 4][2, 28, 4]
PCIE3:PL_N_FTS_GEN2[2, 29, 15][2, 28, 15][2, 29, 14][2, 28, 14][2, 29, 13][2, 28, 13][2, 29, 12][2, 28, 12]
PCIE3:PL_N_FTS_GEN3[2, 29, 23][2, 28, 23][2, 29, 22][2, 28, 22][2, 29, 21][2, 28, 21][2, 29, 20][2, 28, 20]
PCIE3:SPARE_BYTE0[37, 29, 35][37, 28, 35][37, 29, 34][37, 28, 34][37, 29, 33][37, 28, 33][37, 29, 32][37, 28, 32]
PCIE3:SPARE_BYTE1[37, 29, 39][37, 28, 39][37, 29, 38][37, 28, 38][37, 29, 37][37, 28, 37][37, 29, 36][37, 28, 36]
PCIE3:SPARE_BYTE2[37, 29, 43][37, 28, 43][37, 29, 42][37, 28, 42][37, 29, 41][37, 28, 41][37, 29, 40][37, 28, 40]
PCIE3:SPARE_BYTE3[37, 29, 47][37, 28, 47][37, 29, 46][37, 28, 46][37, 29, 45][37, 28, 45][37, 29, 44][37, 28, 44]
PCIE3:TL_CREDITS_CH[5, 29, 43][5, 28, 43][5, 29, 42][5, 28, 42][5, 29, 41][5, 28, 41][5, 29, 40][5, 28, 40]
PCIE3:TL_CREDITS_NPH[6, 29, 11][6, 28, 11][6, 29, 10][6, 28, 10][6, 29, 9][6, 28, 9][6, 29, 8][6, 28, 8]
PCIE3:TL_CREDITS_PH[6, 29, 27][6, 28, 27][6, 29, 26][6, 28, 26][6, 29, 25][6, 28, 25][6, 29, 24][6, 28, 24]
PCIE3:VF0_CAPABILITY_POINTER[9, 29, 23][9, 28, 23][9, 29, 22][9, 28, 22][9, 29, 21][9, 28, 21][9, 29, 20][9, 28, 20]
PCIE3:VF0_PM_CAP_ID[19, 29, 27][19, 28, 27][19, 29, 26][19, 28, 26][19, 29, 25][19, 28, 25][19, 29, 24][19, 28, 24]
PCIE3:VF0_PM_CAP_NEXTPTR[20, 29, 11][20, 28, 11][20, 29, 10][20, 28, 10][20, 29, 9][20, 28, 9][20, 29, 8][20, 28, 8]
PCIE3:VF1_PM_CAP_ID[19, 29, 31][19, 28, 31][19, 29, 30][19, 28, 30][19, 29, 29][19, 28, 29][19, 29, 28][19, 28, 28]
PCIE3:VF1_PM_CAP_NEXTPTR[20, 29, 15][20, 28, 15][20, 29, 14][20, 28, 14][20, 29, 13][20, 28, 13][20, 29, 12][20, 28, 12]
PCIE3:VF2_PM_CAP_ID[19, 29, 35][19, 28, 35][19, 29, 34][19, 28, 34][19, 29, 33][19, 28, 33][19, 29, 32][19, 28, 32]
PCIE3:VF2_PM_CAP_NEXTPTR[20, 29, 19][20, 28, 19][20, 29, 18][20, 28, 18][20, 29, 17][20, 28, 17][20, 29, 16][20, 28, 16]
PCIE3:VF3_PM_CAP_ID[19, 29, 39][19, 28, 39][19, 29, 38][19, 28, 38][19, 29, 37][19, 28, 37][19, 29, 36][19, 28, 36]
PCIE3:VF3_PM_CAP_NEXTPTR[20, 29, 23][20, 28, 23][20, 29, 22][20, 28, 22][20, 29, 21][20, 28, 21][20, 29, 20][20, 28, 20]
PCIE3:VF4_PM_CAP_ID[19, 29, 43][19, 28, 43][19, 29, 42][19, 28, 42][19, 29, 41][19, 28, 41][19, 29, 40][19, 28, 40]
PCIE3:VF4_PM_CAP_NEXTPTR[20, 29, 27][20, 28, 27][20, 29, 26][20, 28, 26][20, 29, 25][20, 28, 25][20, 29, 24][20, 28, 24]
PCIE3:VF5_PM_CAP_ID[19, 29, 47][19, 28, 47][19, 29, 46][19, 28, 46][19, 29, 45][19, 28, 45][19, 29, 44][19, 28, 44]
PCIE3:VF5_PM_CAP_NEXTPTR[20, 29, 31][20, 28, 31][20, 29, 30][20, 28, 30][20, 29, 29][20, 28, 29][20, 29, 28][20, 28, 28]
Non-inverted[7][6][5][4][3][2][1][0]
PCIE3:LL_ACK_TIMEOUT[4, 28, 12][4, 29, 11][4, 28, 11][4, 29, 10][4, 28, 10][4, 29, 9][4, 28, 9][4, 29, 8][4, 28, 8]
PCIE3:LL_REPLAY_TIMEOUT[4, 28, 20][4, 29, 19][4, 28, 19][4, 29, 18][4, 28, 18][4, 29, 17][4, 28, 17][4, 29, 16][4, 28, 16]
Non-inverted[8][7][6][5][4][3][2][1][0]
PCIE3:PF0_BAR0_APERTURE_SIZE[9, 28, 29][9, 29, 28][9, 28, 28][9, 29, 27][9, 28, 27]
PCIE3:PF0_BAR1_APERTURE_SIZE[9, 28, 37][9, 29, 36][9, 28, 36][9, 29, 35][9, 28, 35]
PCIE3:PF0_BAR2_APERTURE_SIZE[9, 28, 45][9, 29, 44][9, 28, 44][9, 29, 43][9, 28, 43]
PCIE3:PF0_BAR3_APERTURE_SIZE[10, 28, 5][10, 29, 4][10, 28, 4][10, 29, 3][10, 28, 3]
PCIE3:PF0_BAR4_APERTURE_SIZE[10, 28, 13][10, 29, 12][10, 28, 12][10, 29, 11][10, 28, 11]
PCIE3:PF0_BAR5_APERTURE_SIZE[10, 28, 21][10, 29, 20][10, 28, 20][10, 29, 19][10, 28, 19]
PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL[28, 28, 29][28, 29, 28][28, 28, 28][28, 29, 27][28, 28, 27]
PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[10, 28, 27][10, 29, 26][10, 28, 26][10, 29, 25][10, 28, 25]
PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE[32, 28, 45][32, 29, 44][32, 28, 44][32, 29, 43][32, 28, 43]
PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE[33, 28, 5][33, 29, 4][33, 28, 4][33, 29, 3][33, 28, 3]
PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE[33, 28, 13][33, 29, 12][33, 28, 12][33, 29, 11][33, 28, 11]
PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE[33, 28, 21][33, 29, 20][33, 28, 20][33, 29, 19][33, 28, 19]
PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE[33, 28, 29][33, 29, 28][33, 28, 28][33, 29, 27][33, 28, 27]
PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE[33, 28, 37][33, 29, 36][33, 28, 36][33, 29, 35][33, 28, 35]
PCIE3:PF1_BAR0_APERTURE_SIZE[9, 29, 31][9, 28, 31][9, 29, 30][9, 28, 30][9, 29, 29]
PCIE3:PF1_BAR1_APERTURE_SIZE[9, 29, 39][9, 28, 39][9, 29, 38][9, 28, 38][9, 29, 37]
PCIE3:PF1_BAR2_APERTURE_SIZE[9, 29, 47][9, 28, 47][9, 29, 46][9, 28, 46][9, 29, 45]
PCIE3:PF1_BAR3_APERTURE_SIZE[10, 29, 7][10, 28, 7][10, 29, 6][10, 28, 6][10, 29, 5]
PCIE3:PF1_BAR4_APERTURE_SIZE[10, 29, 15][10, 28, 15][10, 29, 14][10, 28, 14][10, 29, 13]
PCIE3:PF1_BAR5_APERTURE_SIZE[10, 29, 23][10, 28, 23][10, 29, 22][10, 28, 22][10, 29, 21]
PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL[28, 29, 31][28, 28, 31][28, 29, 30][28, 28, 30][28, 29, 29]
PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[10, 29, 29][10, 28, 29][10, 29, 28][10, 28, 28][10, 29, 27]
PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE[32, 29, 47][32, 28, 47][32, 29, 46][32, 28, 46][32, 29, 45]
PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE[33, 29, 7][33, 28, 7][33, 29, 6][33, 28, 6][33, 29, 5]
PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE[33, 29, 15][33, 28, 15][33, 29, 14][33, 28, 14][33, 29, 13]
PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE[33, 29, 23][33, 28, 23][33, 29, 22][33, 28, 22][33, 29, 21]
PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE[33, 29, 31][33, 28, 31][33, 29, 30][33, 28, 30][33, 29, 29]
PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE[33, 29, 39][33, 28, 39][33, 29, 38][33, 28, 38][33, 29, 37]
PCIE3:PL_EQ_ADAPT_ITER_COUNT[4, 29, 2][4, 28, 2][4, 29, 1][4, 28, 1][4, 29, 0]
Non-inverted[4][3][2][1][0]
PCIE3:PF0_AER_CAP_NEXTPTR[25, 29, 13][25, 28, 13][25, 29, 12][25, 28, 12][25, 29, 11][25, 28, 11][25, 29, 10][25, 28, 10][25, 29, 9][25, 28, 9][25, 29, 8][25, 28, 8]
PCIE3:PF0_ARI_CAP_NEXTPTR[25, 28, 30][25, 29, 29][25, 28, 29][25, 29, 28][25, 28, 28][25, 29, 27][25, 28, 27][25, 29, 26][25, 28, 26][25, 29, 25][25, 28, 25][25, 29, 24]
PCIE3:PF0_DPA_CAP_NEXTPTR[28, 29, 13][28, 28, 13][28, 29, 12][28, 28, 12][28, 29, 11][28, 28, 11][28, 29, 10][28, 28, 10][28, 29, 9][28, 28, 9][28, 29, 8][28, 28, 8]
PCIE3:PF0_DSN_CAP_NEXTPTR[23, 29, 37][23, 28, 37][23, 29, 36][23, 28, 36][23, 29, 35][23, 28, 35][23, 29, 34][23, 28, 34][23, 29, 33][23, 28, 33][23, 29, 32][23, 28, 32]
PCIE3:PF0_LTR_CAP_NEXTPTR[27, 29, 29][27, 28, 29][27, 29, 28][27, 28, 28][27, 29, 27][27, 28, 27][27, 29, 26][27, 28, 26][27, 29, 25][27, 28, 25][27, 29, 24][27, 28, 24]
PCIE3:PF0_PB_CAP_NEXTPTR[27, 29, 5][27, 28, 5][27, 29, 4][27, 28, 4][27, 29, 3][27, 28, 3][27, 29, 2][27, 28, 2][27, 29, 1][27, 28, 1][27, 29, 0][27, 28, 0]
PCIE3:PF0_RBAR_CAP_NEXTPTR[21, 29, 13][21, 28, 13][21, 29, 12][21, 28, 12][21, 29, 11][21, 28, 11][21, 29, 10][21, 28, 10][21, 29, 9][21, 28, 9][21, 29, 8][21, 28, 8]
PCIE3:PF0_SRIOV_CAP_NEXTPTR[30, 28, 6][30, 29, 5][30, 28, 5][30, 29, 4][30, 28, 4][30, 29, 3][30, 28, 3][30, 29, 2][30, 28, 2][30, 29, 1][30, 28, 1][30, 29, 0]
PCIE3:PF0_TPHR_CAP_NEXTPTR[33, 29, 45][33, 28, 45][33, 29, 44][33, 28, 44][33, 29, 43][33, 28, 43][33, 29, 42][33, 28, 42][33, 29, 41][33, 28, 41][33, 29, 40][33, 28, 40]
PCIE3:PF0_VC_CAP_NEXTPTR[25, 29, 5][25, 28, 5][25, 29, 4][25, 28, 4][25, 29, 3][25, 28, 3][25, 29, 2][25, 28, 2][25, 29, 1][25, 28, 1][25, 29, 0][25, 28, 0]
PCIE3:PF1_AER_CAP_NEXTPTR[25, 29, 21][25, 28, 21][25, 29, 20][25, 28, 20][25, 29, 19][25, 28, 19][25, 29, 18][25, 28, 18][25, 29, 17][25, 28, 17][25, 29, 16][25, 28, 16]
PCIE3:PF1_ARI_CAP_NEXTPTR[25, 29, 37][25, 28, 37][25, 29, 36][25, 28, 36][25, 29, 35][25, 28, 35][25, 29, 34][25, 28, 34][25, 29, 33][25, 28, 33][25, 29, 32][25, 28, 32]
PCIE3:PF1_DPA_CAP_NEXTPTR[28, 29, 21][28, 28, 21][28, 29, 20][28, 28, 20][28, 29, 19][28, 28, 19][28, 29, 18][28, 28, 18][28, 29, 17][28, 28, 17][28, 29, 16][28, 28, 16]
PCIE3:PF1_DSN_CAP_NEXTPTR[23, 29, 45][23, 28, 45][23, 29, 44][23, 28, 44][23, 29, 43][23, 28, 43][23, 29, 42][23, 28, 42][23, 29, 41][23, 28, 41][23, 29, 40][23, 28, 40]
PCIE3:PF1_PB_CAP_NEXTPTR[27, 29, 13][27, 28, 13][27, 29, 12][27, 28, 12][27, 29, 11][27, 28, 11][27, 29, 10][27, 28, 10][27, 29, 9][27, 28, 9][27, 29, 8][27, 28, 8]
PCIE3:PF1_RBAR_CAP_NEXTPTR[21, 29, 21][21, 28, 21][21, 29, 20][21, 28, 20][21, 29, 19][21, 28, 19][21, 29, 18][21, 28, 18][21, 29, 17][21, 28, 17][21, 29, 16][21, 28, 16]
PCIE3:PF1_SRIOV_CAP_NEXTPTR[30, 29, 13][30, 28, 13][30, 29, 12][30, 28, 12][30, 29, 11][30, 28, 11][30, 29, 10][30, 28, 10][30, 29, 9][30, 28, 9][30, 29, 8][30, 28, 8]
PCIE3:PF1_TPHR_CAP_NEXTPTR[34, 29, 5][34, 28, 5][34, 29, 4][34, 28, 4][34, 29, 3][34, 28, 3][34, 29, 2][34, 28, 2][34, 29, 1][34, 28, 1][34, 29, 0][34, 28, 0]
PCIE3:TL_CREDITS_CD[5, 28, 38][5, 29, 37][5, 28, 37][5, 29, 36][5, 28, 36][5, 29, 35][5, 28, 35][5, 29, 34][5, 28, 34][5, 29, 33][5, 28, 33][5, 29, 32]
PCIE3:TL_CREDITS_NPD[6, 29, 5][6, 28, 5][6, 29, 4][6, 28, 4][6, 29, 3][6, 28, 3][6, 29, 2][6, 28, 2][6, 29, 1][6, 28, 1][6, 29, 0][6, 28, 0]
PCIE3:TL_CREDITS_PD[6, 29, 21][6, 28, 21][6, 29, 20][6, 28, 20][6, 29, 19][6, 28, 19][6, 29, 18][6, 28, 18][6, 29, 17][6, 28, 17][6, 29, 16][6, 28, 16]
PCIE3:VF0_ARI_CAP_NEXTPTR[25, 29, 45][25, 28, 45][25, 29, 44][25, 28, 44][25, 29, 43][25, 28, 43][25, 29, 42][25, 28, 42][25, 29, 41][25, 28, 41][25, 29, 40][25, 28, 40]
PCIE3:VF0_TPHR_CAP_NEXTPTR[34, 29, 13][34, 28, 13][34, 29, 12][34, 28, 12][34, 29, 11][34, 28, 11][34, 29, 10][34, 28, 10][34, 29, 9][34, 28, 9][34, 29, 8][34, 28, 8]
PCIE3:VF1_ARI_CAP_NEXTPTR[26, 29, 5][26, 28, 5][26, 29, 4][26, 28, 4][26, 29, 3][26, 28, 3][26, 29, 2][26, 28, 2][26, 29, 1][26, 28, 1][26, 29, 0][26, 28, 0]
PCIE3:VF1_TPHR_CAP_NEXTPTR[34, 29, 21][34, 28, 21][34, 29, 20][34, 28, 20][34, 29, 19][34, 28, 19][34, 29, 18][34, 28, 18][34, 29, 17][34, 28, 17][34, 29, 16][34, 28, 16]
PCIE3:VF2_ARI_CAP_NEXTPTR[26, 29, 13][26, 28, 13][26, 29, 12][26, 28, 12][26, 29, 11][26, 28, 11][26, 29, 10][26, 28, 10][26, 29, 9][26, 28, 9][26, 29, 8][26, 28, 8]
PCIE3:VF2_TPHR_CAP_NEXTPTR[34, 29, 29][34, 28, 29][34, 29, 28][34, 28, 28][34, 29, 27][34, 28, 27][34, 29, 26][34, 28, 26][34, 29, 25][34, 28, 25][34, 29, 24][34, 28, 24]
PCIE3:VF3_ARI_CAP_NEXTPTR[26, 29, 21][26, 28, 21][26, 29, 20][26, 28, 20][26, 29, 19][26, 28, 19][26, 29, 18][26, 28, 18][26, 29, 17][26, 28, 17][26, 29, 16][26, 28, 16]
PCIE3:VF3_TPHR_CAP_NEXTPTR[34, 29, 37][34, 28, 37][34, 29, 36][34, 28, 36][34, 29, 35][34, 28, 35][34, 29, 34][34, 28, 34][34, 29, 33][34, 28, 33][34, 29, 32][34, 28, 32]
PCIE3:VF4_ARI_CAP_NEXTPTR[26, 29, 29][26, 28, 29][26, 29, 28][26, 28, 28][26, 29, 27][26, 28, 27][26, 29, 26][26, 28, 26][26, 29, 25][26, 28, 25][26, 29, 24][26, 28, 24]
PCIE3:VF4_TPHR_CAP_NEXTPTR[34, 29, 45][34, 28, 45][34, 29, 44][34, 28, 44][34, 29, 43][34, 28, 43][34, 29, 42][34, 28, 42][34, 29, 41][34, 28, 41][34, 29, 40][34, 28, 40]
PCIE3:VF5_ARI_CAP_NEXTPTR[26, 29, 37][26, 28, 37][26, 29, 36][26, 28, 36][26, 29, 35][26, 28, 35][26, 29, 34][26, 28, 34][26, 29, 33][26, 28, 33][26, 29, 32][26, 28, 32]
PCIE3:VF5_TPHR_CAP_NEXTPTR[35, 29, 5][35, 28, 5][35, 29, 4][35, 28, 4][35, 29, 3][35, 28, 3][35, 29, 2][35, 28, 2][35, 29, 1][35, 28, 1][35, 29, 0][35, 28, 0]
Non-inverted[11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:PF0_CLASS_CODE[8, 29, 3][8, 28, 3][8, 29, 2][8, 28, 2][8, 29, 1][8, 28, 1][8, 29, 0][8, 28, 0][7, 29, 47][7, 28, 47][7, 29, 46][7, 28, 46][7, 29, 45][7, 28, 45][7, 29, 44][7, 28, 44][7, 29, 43][7, 28, 43][7, 29, 42][7, 28, 42][7, 29, 41][7, 28, 41][7, 29, 40][7, 28, 40]
PCIE3:PF1_CLASS_CODE[8, 29, 19][8, 28, 19][8, 29, 18][8, 28, 18][8, 29, 17][8, 28, 17][8, 29, 16][8, 28, 16][8, 29, 15][8, 28, 15][8, 29, 14][8, 28, 14][8, 29, 13][8, 28, 13][8, 29, 12][8, 28, 12][8, 29, 11][8, 28, 11][8, 29, 10][8, 28, 10][8, 29, 9][8, 28, 9][8, 29, 8][8, 28, 8]
PCIE3:TL_COMPL_TIMEOUT_REG0[6, 29, 43][6, 28, 43][6, 29, 42][6, 28, 42][6, 29, 41][6, 28, 41][6, 29, 40][6, 28, 40][6, 29, 39][6, 28, 39][6, 29, 38][6, 28, 38][6, 29, 37][6, 28, 37][6, 29, 36][6, 28, 36][6, 29, 35][6, 28, 35][6, 29, 34][6, 28, 34][6, 29, 33][6, 28, 33][6, 29, 32][6, 28, 32]
Non-inverted[23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:TL_COMPL_TIMEOUT_REG1[7, 29, 13][7, 28, 13][7, 29, 12][7, 28, 12][7, 29, 11][7, 28, 11][7, 29, 10][7, 28, 10][7, 29, 9][7, 28, 9][7, 29, 8][7, 28, 8][7, 29, 7][7, 28, 7][7, 29, 6][7, 28, 6][7, 29, 5][7, 28, 5][7, 29, 4][7, 28, 4][7, 29, 3][7, 28, 3][7, 29, 2][7, 28, 2][7, 29, 1][7, 28, 1][7, 29, 0][7, 28, 0]
Non-inverted[27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:PF0_MSIX_CAP_PBA_OFFSET[12, 28, 30][12, 29, 29][12, 28, 29][12, 29, 28][12, 28, 28][12, 29, 27][12, 28, 27][12, 29, 26][12, 28, 26][12, 29, 25][12, 28, 25][12, 29, 24][12, 28, 24][12, 29, 23][12, 28, 23][12, 29, 22][12, 28, 22][12, 29, 21][12, 28, 21][12, 29, 20][12, 28, 20][12, 29, 19][12, 28, 19][12, 29, 18][12, 28, 18][12, 29, 17][12, 28, 17][12, 29, 16][12, 28, 16]
PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[15, 28, 30][15, 29, 29][15, 28, 29][15, 29, 28][15, 28, 28][15, 29, 27][15, 28, 27][15, 29, 26][15, 28, 26][15, 29, 25][15, 28, 25][15, 29, 24][15, 28, 24][15, 29, 23][15, 28, 23][15, 29, 22][15, 28, 22][15, 29, 21][15, 28, 21][15, 29, 20][15, 28, 20][15, 29, 19][15, 28, 19][15, 29, 18][15, 28, 18][15, 29, 17][15, 28, 17][15, 29, 16][15, 28, 16]
PCIE3:PF1_MSIX_CAP_PBA_OFFSET[12, 28, 46][12, 29, 45][12, 28, 45][12, 29, 44][12, 28, 44][12, 29, 43][12, 28, 43][12, 29, 42][12, 28, 42][12, 29, 41][12, 28, 41][12, 29, 40][12, 28, 40][12, 29, 39][12, 28, 39][12, 29, 38][12, 28, 38][12, 29, 37][12, 28, 37][12, 29, 36][12, 28, 36][12, 29, 35][12, 28, 35][12, 29, 34][12, 28, 34][12, 29, 33][12, 28, 33][12, 29, 32][12, 28, 32]
PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[15, 28, 46][15, 29, 45][15, 28, 45][15, 29, 44][15, 28, 44][15, 29, 43][15, 28, 43][15, 29, 42][15, 28, 42][15, 29, 41][15, 28, 41][15, 29, 40][15, 28, 40][15, 29, 39][15, 28, 39][15, 29, 38][15, 28, 38][15, 29, 37][15, 28, 37][15, 29, 36][15, 28, 36][15, 29, 35][15, 28, 35][15, 29, 34][15, 28, 34][15, 29, 33][15, 28, 33][15, 29, 32][15, 28, 32]
PCIE3:VF0_MSIX_CAP_PBA_OFFSET[13, 28, 14][13, 29, 13][13, 28, 13][13, 29, 12][13, 28, 12][13, 29, 11][13, 28, 11][13, 29, 10][13, 28, 10][13, 29, 9][13, 28, 9][13, 29, 8][13, 28, 8][13, 29, 7][13, 28, 7][13, 29, 6][13, 28, 6][13, 29, 5][13, 28, 5][13, 29, 4][13, 28, 4][13, 29, 3][13, 28, 3][13, 29, 2][13, 28, 2][13, 29, 1][13, 28, 1][13, 29, 0][13, 28, 0]
PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[16, 28, 14][16, 29, 13][16, 28, 13][16, 29, 12][16, 28, 12][16, 29, 11][16, 28, 11][16, 29, 10][16, 28, 10][16, 29, 9][16, 28, 9][16, 29, 8][16, 28, 8][16, 29, 7][16, 28, 7][16, 29, 6][16, 28, 6][16, 29, 5][16, 28, 5][16, 29, 4][16, 28, 4][16, 29, 3][16, 28, 3][16, 29, 2][16, 28, 2][16, 29, 1][16, 28, 1][16, 29, 0][16, 28, 0]
PCIE3:VF1_MSIX_CAP_PBA_OFFSET[13, 28, 30][13, 29, 29][13, 28, 29][13, 29, 28][13, 28, 28][13, 29, 27][13, 28, 27][13, 29, 26][13, 28, 26][13, 29, 25][13, 28, 25][13, 29, 24][13, 28, 24][13, 29, 23][13, 28, 23][13, 29, 22][13, 28, 22][13, 29, 21][13, 28, 21][13, 29, 20][13, 28, 20][13, 29, 19][13, 28, 19][13, 29, 18][13, 28, 18][13, 29, 17][13, 28, 17][13, 29, 16][13, 28, 16]
PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[16, 28, 30][16, 29, 29][16, 28, 29][16, 29, 28][16, 28, 28][16, 29, 27][16, 28, 27][16, 29, 26][16, 28, 26][16, 29, 25][16, 28, 25][16, 29, 24][16, 28, 24][16, 29, 23][16, 28, 23][16, 29, 22][16, 28, 22][16, 29, 21][16, 28, 21][16, 29, 20][16, 28, 20][16, 29, 19][16, 28, 19][16, 29, 18][16, 28, 18][16, 29, 17][16, 28, 17][16, 29, 16][16, 28, 16]
PCIE3:VF2_MSIX_CAP_PBA_OFFSET[13, 28, 46][13, 29, 45][13, 28, 45][13, 29, 44][13, 28, 44][13, 29, 43][13, 28, 43][13, 29, 42][13, 28, 42][13, 29, 41][13, 28, 41][13, 29, 40][13, 28, 40][13, 29, 39][13, 28, 39][13, 29, 38][13, 28, 38][13, 29, 37][13, 28, 37][13, 29, 36][13, 28, 36][13, 29, 35][13, 28, 35][13, 29, 34][13, 28, 34][13, 29, 33][13, 28, 33][13, 29, 32][13, 28, 32]
PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[16, 28, 46][16, 29, 45][16, 28, 45][16, 29, 44][16, 28, 44][16, 29, 43][16, 28, 43][16, 29, 42][16, 28, 42][16, 29, 41][16, 28, 41][16, 29, 40][16, 28, 40][16, 29, 39][16, 28, 39][16, 29, 38][16, 28, 38][16, 29, 37][16, 28, 37][16, 29, 36][16, 28, 36][16, 29, 35][16, 28, 35][16, 29, 34][16, 28, 34][16, 29, 33][16, 28, 33][16, 29, 32][16, 28, 32]
PCIE3:VF3_MSIX_CAP_PBA_OFFSET[14, 28, 14][14, 29, 13][14, 28, 13][14, 29, 12][14, 28, 12][14, 29, 11][14, 28, 11][14, 29, 10][14, 28, 10][14, 29, 9][14, 28, 9][14, 29, 8][14, 28, 8][14, 29, 7][14, 28, 7][14, 29, 6][14, 28, 6][14, 29, 5][14, 28, 5][14, 29, 4][14, 28, 4][14, 29, 3][14, 28, 3][14, 29, 2][14, 28, 2][14, 29, 1][14, 28, 1][14, 29, 0][14, 28, 0]
PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[17, 28, 14][17, 29, 13][17, 28, 13][17, 29, 12][17, 28, 12][17, 29, 11][17, 28, 11][17, 29, 10][17, 28, 10][17, 29, 9][17, 28, 9][17, 29, 8][17, 28, 8][17, 29, 7][17, 28, 7][17, 29, 6][17, 28, 6][17, 29, 5][17, 28, 5][17, 29, 4][17, 28, 4][17, 29, 3][17, 28, 3][17, 29, 2][17, 28, 2][17, 29, 1][17, 28, 1][17, 29, 0][17, 28, 0]
PCIE3:VF4_MSIX_CAP_PBA_OFFSET[14, 28, 30][14, 29, 29][14, 28, 29][14, 29, 28][14, 28, 28][14, 29, 27][14, 28, 27][14, 29, 26][14, 28, 26][14, 29, 25][14, 28, 25][14, 29, 24][14, 28, 24][14, 29, 23][14, 28, 23][14, 29, 22][14, 28, 22][14, 29, 21][14, 28, 21][14, 29, 20][14, 28, 20][14, 29, 19][14, 28, 19][14, 29, 18][14, 28, 18][14, 29, 17][14, 28, 17][14, 29, 16][14, 28, 16]
PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[17, 28, 30][17, 29, 29][17, 28, 29][17, 29, 28][17, 28, 28][17, 29, 27][17, 28, 27][17, 29, 26][17, 28, 26][17, 29, 25][17, 28, 25][17, 29, 24][17, 28, 24][17, 29, 23][17, 28, 23][17, 29, 22][17, 28, 22][17, 29, 21][17, 28, 21][17, 29, 20][17, 28, 20][17, 29, 19][17, 28, 19][17, 29, 18][17, 28, 18][17, 29, 17][17, 28, 17][17, 29, 16][17, 28, 16]
PCIE3:VF5_MSIX_CAP_PBA_OFFSET[14, 28, 46][14, 29, 45][14, 28, 45][14, 29, 44][14, 28, 44][14, 29, 43][14, 28, 43][14, 29, 42][14, 28, 42][14, 29, 41][14, 28, 41][14, 29, 40][14, 28, 40][14, 29, 39][14, 28, 39][14, 29, 38][14, 28, 38][14, 29, 37][14, 28, 37][14, 29, 36][14, 28, 36][14, 29, 35][14, 28, 35][14, 29, 34][14, 28, 34][14, 29, 33][14, 28, 33][14, 29, 32][14, 28, 32]
PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[17, 28, 46][17, 29, 45][17, 28, 45][17, 29, 44][17, 28, 44][17, 29, 43][17, 28, 43][17, 29, 42][17, 28, 42][17, 29, 41][17, 28, 41][17, 29, 40][17, 28, 40][17, 29, 39][17, 28, 39][17, 29, 38][17, 28, 38][17, 29, 37][17, 28, 37][17, 29, 36][17, 28, 36][17, 29, 35][17, 28, 35][17, 29, 34][17, 28, 34][17, 29, 33][17, 28, 33][17, 29, 32][17, 28, 32]
Non-inverted[28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
PCIE3:PF0_MSIX_CAP_TABLE_SIZE[18, 28, 5][18, 29, 4][18, 28, 4][18, 29, 3][18, 28, 3][18, 29, 2][18, 28, 2][18, 29, 1][18, 28, 1][18, 29, 0][18, 28, 0]
PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[35, 28, 45][35, 29, 44][35, 28, 44][35, 29, 43][35, 28, 43][35, 29, 42][35, 28, 42][35, 29, 41][35, 28, 41][35, 29, 40][35, 28, 40]
PCIE3:PF1_MSIX_CAP_TABLE_SIZE[18, 28, 13][18, 29, 12][18, 28, 12][18, 29, 11][18, 28, 11][18, 29, 10][18, 28, 10][18, 29, 9][18, 28, 9][18, 29, 8][18, 28, 8]
PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[36, 28, 5][36, 29, 4][36, 28, 4][36, 29, 3][36, 28, 3][36, 29, 2][36, 28, 2][36, 29, 1][36, 28, 1][36, 29, 0][36, 28, 0]
PCIE3:VF0_MSIX_CAP_TABLE_SIZE[18, 28, 21][18, 29, 20][18, 28, 20][18, 29, 19][18, 28, 19][18, 29, 18][18, 28, 18][18, 29, 17][18, 28, 17][18, 29, 16][18, 28, 16]
PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[36, 28, 13][36, 29, 12][36, 28, 12][36, 29, 11][36, 28, 11][36, 29, 10][36, 28, 10][36, 29, 9][36, 28, 9][36, 29, 8][36, 28, 8]
PCIE3:VF1_MSIX_CAP_TABLE_SIZE[18, 28, 29][18, 29, 28][18, 28, 28][18, 29, 27][18, 28, 27][18, 29, 26][18, 28, 26][18, 29, 25][18, 28, 25][18, 29, 24][18, 28, 24]
PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[36, 28, 21][36, 29, 20][36, 28, 20][36, 29, 19][36, 28, 19][36, 29, 18][36, 28, 18][36, 29, 17][36, 28, 17][36, 29, 16][36, 28, 16]
PCIE3:VF2_MSIX_CAP_TABLE_SIZE[18, 28, 37][18, 29, 36][18, 28, 36][18, 29, 35][18, 28, 35][18, 29, 34][18, 28, 34][18, 29, 33][18, 28, 33][18, 29, 32][18, 28, 32]
PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[36, 28, 29][36, 29, 28][36, 28, 28][36, 29, 27][36, 28, 27][36, 29, 26][36, 28, 26][36, 29, 25][36, 28, 25][36, 29, 24][36, 28, 24]
PCIE3:VF3_MSIX_CAP_TABLE_SIZE[18, 28, 45][18, 29, 44][18, 28, 44][18, 29, 43][18, 28, 43][18, 29, 42][18, 28, 42][18, 29, 41][18, 28, 41][18, 29, 40][18, 28, 40]
PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[36, 28, 37][36, 29, 36][36, 28, 36][36, 29, 35][36, 28, 35][36, 29, 34][36, 28, 34][36, 29, 33][36, 28, 33][36, 29, 32][36, 28, 32]
PCIE3:VF4_MSIX_CAP_TABLE_SIZE[19, 28, 5][19, 29, 4][19, 28, 4][19, 29, 3][19, 28, 3][19, 29, 2][19, 28, 2][19, 29, 1][19, 28, 1][19, 29, 0][19, 28, 0]
PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[36, 28, 45][36, 29, 44][36, 28, 44][36, 29, 43][36, 28, 43][36, 29, 42][36, 28, 42][36, 29, 41][36, 28, 41][36, 29, 40][36, 28, 40]
PCIE3:VF5_MSIX_CAP_TABLE_SIZE[19, 28, 13][19, 29, 12][19, 28, 12][19, 29, 11][19, 28, 11][19, 29, 10][19, 28, 10][19, 29, 9][19, 28, 9][19, 29, 8][19, 28, 8]
PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[37, 28, 5][37, 29, 4][37, 28, 4][37, 29, 3][37, 28, 3][37, 29, 2][37, 28, 2][37, 29, 1][37, 28, 1][37, 29, 0][37, 28, 0]
Non-inverted[10][9][8][7][6][5][4][3][2][1][0]
PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL[28, 29, 4][28, 28, 4][28, 29, 3][28, 28, 3][28, 29, 2][28, 28, 2][28, 29, 1][28, 28, 1][28, 29, 0][28, 28, 0]
PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[27, 29, 44][27, 28, 44][27, 29, 43][27, 28, 43][27, 29, 42][27, 28, 42][27, 29, 41][27, 28, 41][27, 29, 40][27, 28, 40]
PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[27, 29, 36][27, 28, 36][27, 29, 35][27, 28, 35][27, 29, 34][27, 28, 34][27, 29, 33][27, 28, 33][27, 29, 32][27, 28, 32]
Non-inverted[9][8][7][6][5][4][3][2][1][0]