Configuration registers — Spartan 3, Spartan 3E
Todo
document
COR.S3
This is the Spartan 3 version of COR
.
REG.COR.S3 bittile 0 | |
---|---|
Row | Column |
0 | |
0 | STARTUP:GWE_CYCLE[0] |
1 | STARTUP:GWE_CYCLE[1] |
2 | STARTUP:GWE_CYCLE[2] |
3 | STARTUP:GTS_CYCLE[0] |
4 | STARTUP:GTS_CYCLE[1] |
5 | STARTUP:GTS_CYCLE[2] |
6 | STARTUP:LCK_CYCLE[0] |
7 | STARTUP:LCK_CYCLE[1] |
8 | STARTUP:LCK_CYCLE[2] |
9 | STARTUP:MATCH_CYCLE[0] |
10 | STARTUP:MATCH_CYCLE[1] |
11 | STARTUP:MATCH_CYCLE[2] |
12 | STARTUP:DONE_CYCLE[0] |
13 | STARTUP:DONE_CYCLE[1] |
14 | STARTUP:DONE_CYCLE[2] |
15 | STARTUP:STARTUPCLK[0] |
16 | STARTUP:STARTUPCLK[1] |
17 | STARTUP:BUSCLK_FREQ[0] |
18 | STARTUP:BUSCLK_FREQ[1] |
19 | STARTUP:CONFIG_RATE[0] |
20 | STARTUP:CONFIG_RATE[1] |
21 | STARTUP:CONFIG_RATE[2] |
22 | - |
23 | CAPTURE:ONESHOT |
24 | STARTUP:DRIVE_DONE |
25 | STARTUP:DONE_PIPE |
26 | STARTUP:DCM_SHUTDOWN |
27 | - |
28 | - |
29 | ~STARTUP:CRC |
30 | STARTUP:VRDSEL[0] |
31 | STARTUP:VRDSEL[1] |
STARTUP:GTS_CYCLE | [0, 0, 5] | [0, 0, 4] | [0, 0, 3] |
---|---|---|---|
STARTUP:GWE_CYCLE | [0, 0, 2] | [0, 0, 1] | [0, 0, 0] |
1 | 0 | 0 | 0 |
2 | 0 | 0 | 1 |
3 | 0 | 1 | 0 |
4 | 0 | 1 | 1 |
5 | 1 | 0 | 0 |
6 | 1 | 0 | 1 |
DONE | 1 | 1 | 0 |
KEEP | 1 | 1 | 1 |
STARTUP:LCK_CYCLE | [0, 0, 8] | [0, 0, 7] | [0, 0, 6] |
---|---|---|---|
STARTUP:MATCH_CYCLE | [0, 0, 11] | [0, 0, 10] | [0, 0, 9] |
0 | 0 | 0 | 0 |
1 | 0 | 0 | 1 |
2 | 0 | 1 | 0 |
3 | 0 | 1 | 1 |
4 | 1 | 0 | 0 |
5 | 1 | 0 | 1 |
6 | 1 | 1 | 0 |
NOWAIT | 1 | 1 | 1 |
STARTUP:DONE_CYCLE | [0, 0, 14] | [0, 0, 13] | [0, 0, 12] |
---|---|---|---|
1 | 0 | 0 | 0 |
2 | 0 | 0 | 1 |
3 | 0 | 1 | 0 |
4 | 0 | 1 | 1 |
5 | 1 | 0 | 0 |
6 | 1 | 0 | 1 |
KEEP | 1 | 1 | 1 |
STARTUP:STARTUPCLK | [0, 0, 16] | [0, 0, 15] |
---|---|---|
CCLK | 0 | 0 |
USERCLK | 0 | 1 |
JTAGCLK | 1 | 0 |
STARTUP:BUSCLK_FREQ | [0, 0, 18] | [0, 0, 17] |
---|---|---|
100 | 0 | 0 |
25 | 0 | 1 |
50 | 1 | 0 |
200 | 1 | 1 |
STARTUP:CONFIG_RATE | [0, 0, 21] | [0, 0, 20] | [0, 0, 19] |
---|---|---|---|
6 | 0 | 0 | 0 |
12 | 0 | 0 | 1 |
25 | 0 | 1 | 0 |
50 | 0 | 1 | 1 |
3 | 1 | 0 | 0 |
100 | 1 | 1 | 0 |
CAPTURE:ONESHOT | [0, 0, 23] |
---|---|
STARTUP:DCM_SHUTDOWN | [0, 0, 26] |
STARTUP:DONE_PIPE | [0, 0, 25] |
STARTUP:DRIVE_DONE | [0, 0, 24] |
Non-inverted | [0] |
STARTUP:CRC | [0, 0, 29] |
---|---|
Inverted | ~[0] |
STARTUP:VRDSEL | [0, 0, 31] | [0, 0, 30] |
---|---|---|
100 | 0 | 0 |
95 | 0 | 1 |
90 | 1 | 0 |
80 | 1 | 1 |
COR.S3E
This is the Spartan 3E version of COR
.
REG.COR.S3E bittile 0 | |
---|---|
Row | Column |
0 | |
0 | STARTUP:GWE_CYCLE[0] |
1 | STARTUP:GWE_CYCLE[1] |
2 | STARTUP:GWE_CYCLE[2] |
3 | STARTUP:GTS_CYCLE[0] |
4 | STARTUP:GTS_CYCLE[1] |
5 | STARTUP:GTS_CYCLE[2] |
6 | STARTUP:LCK_CYCLE[0] |
7 | STARTUP:LCK_CYCLE[1] |
8 | STARTUP:LCK_CYCLE[2] |
9 | - |
10 | - |
11 | - |
12 | STARTUP:DONE_CYCLE[0] |
13 | STARTUP:DONE_CYCLE[1] |
14 | STARTUP:DONE_CYCLE[2] |
15 | STARTUP:STARTUPCLK[0] |
16 | STARTUP:STARTUPCLK[1] |
17 | STARTUP:BUSCLK_FREQ[0] |
18 | STARTUP:BUSCLK_FREQ[1] |
19 | STARTUP:CONFIG_RATE[0] |
20 | STARTUP:CONFIG_RATE[1] |
21 | STARTUP:CONFIG_RATE[2] |
22 | - |
23 | CAPTURE:ONESHOT |
24 | STARTUP:DRIVE_DONE |
25 | STARTUP:DONE_PIPE |
26 | STARTUP:DCM_SHUTDOWN |
27 | - |
28 | STARTUP:MULTIBOOT_ENABLE |
29 | ~STARTUP:CRC |
30 | STARTUP:VRDSEL[0] |
31 | STARTUP:VRDSEL[1] |
STARTUP:GTS_CYCLE | [0, 0, 5] | [0, 0, 4] | [0, 0, 3] |
---|---|---|---|
STARTUP:GWE_CYCLE | [0, 0, 2] | [0, 0, 1] | [0, 0, 0] |
1 | 0 | 0 | 0 |
2 | 0 | 0 | 1 |
3 | 0 | 1 | 0 |
4 | 0 | 1 | 1 |
5 | 1 | 0 | 0 |
6 | 1 | 0 | 1 |
DONE | 1 | 1 | 0 |
KEEP | 1 | 1 | 1 |
STARTUP:LCK_CYCLE | [0, 0, 8] | [0, 0, 7] | [0, 0, 6] |
---|---|---|---|
0 | 0 | 0 | 0 |
1 | 0 | 0 | 1 |
2 | 0 | 1 | 0 |
3 | 0 | 1 | 1 |
4 | 1 | 0 | 0 |
5 | 1 | 0 | 1 |
6 | 1 | 1 | 0 |
NOWAIT | 1 | 1 | 1 |
STARTUP:DONE_CYCLE | [0, 0, 14] | [0, 0, 13] | [0, 0, 12] |
---|---|---|---|
1 | 0 | 0 | 0 |
2 | 0 | 0 | 1 |
3 | 0 | 1 | 0 |
4 | 0 | 1 | 1 |
5 | 1 | 0 | 0 |
6 | 1 | 0 | 1 |
KEEP | 1 | 1 | 1 |
STARTUP:STARTUPCLK | [0, 0, 16] | [0, 0, 15] |
---|---|---|
CCLK | 0 | 0 |
USERCLK | 0 | 1 |
JTAGCLK | 1 | 0 |
STARTUP:BUSCLK_FREQ | [0, 0, 18] | [0, 0, 17] |
---|---|---|
100 | 0 | 0 |
25 | 0 | 1 |
50 | 1 | 0 |
200 | 1 | 1 |
STARTUP:CONFIG_RATE | [0, 0, 21] | [0, 0, 20] | [0, 0, 19] |
---|---|---|---|
1 | 0 | 0 | 0 |
3 | 0 | 0 | 1 |
6 | 0 | 1 | 0 |
12 | 0 | 1 | 1 |
50 | 1 | 0 | 0 |
25 | 1 | 1 | 0 |
CAPTURE:ONESHOT | [0, 0, 23] |
---|---|
STARTUP:DCM_SHUTDOWN | [0, 0, 26] |
STARTUP:DONE_PIPE | [0, 0, 25] |
STARTUP:DRIVE_DONE | [0, 0, 24] |
STARTUP:MULTIBOOT_ENABLE | [0, 0, 28] |
Non-inverted | [0] |
STARTUP:CRC | [0, 0, 29] |
---|---|
Inverted | ~[0] |
STARTUP:VRDSEL | [0, 0, 31] | [0, 0, 30] |
---|---|---|
70_75 | 0 | 0 |
90 | 1 | 0 |
80 | 1 | 1 |
CTL.S3
This is the Spartan 3 and Spartan 3E version of CTL
.
REG.CTL.S3 bittile 0 | |
---|---|
Row | Column |
0 | |
0 | MISC:GTS_USR_B |
1 | MISC:VGG_TEST |
2 | MISC:BCLK_TEST |
3 | MISC:PERSIST |
4 | MISC:SECURITY[0] |
5 | MISC:SECURITY[1] |
MISC:BCLK_TEST | [0, 0, 2] |
---|---|
MISC:GTS_USR_B | [0, 0, 0] |
MISC:PERSIST | [0, 0, 3] |
MISC:VGG_TEST | [0, 0, 1] |
Non-inverted | [0] |
MISC:SECURITY | [0, 0, 5] | [0, 0, 4] |
---|---|---|
NONE | 0 | 0 |
LEVEL1 | 0 | 1 |
LEVEL2 | 1 | 0 |