Corners

Todo

document

Lower left

Todo

document

LL.S3

This tile is used on Spartan 3.

LL.S3 bittile 0
Row	Column
	0	1
0	-	MISC:DCI_CLK_ENABLE
1	-	MISC:GATE_GHIGH
2	-	MISC:DCI_OSC_SEL[0]
3	-	MISC:DCI_OSC_SEL[1]
4	-	MISC:DCI_OSC_SEL[2]
5	-	MISC:DCM_ENABLE
6	-	-
7	-	-
8	-	MISC:SEND_VGG[0]
9	-	MISC:SEND_VGG[1]
10	-	MISC:SEND_VGG[2]
11	-	MISC:SEND_VGG[3]
12	-	MISC:VGG_SENDMAX
13	-	MISC:VGG_ENABLE_OFFCHIP
14	-	-
15	-	-
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	-
23	DCI0:LVDSBIAS[1]	-
24	DCI0:LVDSBIAS[0]	-
25	MISC:M1PIN[1]	-
26	MISC:M1PIN[0]	-
27	MISC:M0PIN[1]	-
28	MISC:M0PIN[0]	-
29	MISC:M2PIN[1]	-
30	MISC:M2PIN[0]	-
31	-	DCI1:LVDSBIAS[1]
32	-	DCI1:LVDSBIAS[0]
33	DCI0:LVDSBIAS[12]	DCI1:LVDSBIAS[12]
34	DCI0:LVDSBIAS[11]	DCI1:LVDSBIAS[11]
35	DCI0:LVDSBIAS[10]	DCI1:LVDSBIAS[10]
36	DCI0:LVDSBIAS[9]	DCI1:LVDSBIAS[9]
37	DCI0:LVDSBIAS[8]	DCI1:LVDSBIAS[8]
38	DCI0:LVDSBIAS[7]	DCI1:LVDSBIAS[7]
39	DCI0:LVDSBIAS[6]	DCI1:LVDSBIAS[6]
40	DCI0:LVDSBIAS[5]	DCI1:LVDSBIAS[5]
41	DCI0:LVDSBIAS[4]	DCI1:LVDSBIAS[4]
42	DCI0:LVDSBIAS[3]	DCI1:LVDSBIAS[3]
43	DCI0:LVDSBIAS[2]	DCI1:LVDSBIAS[2]
44	DCI1:ENABLE	DCI0:ENABLE
45	DCI1:QUIET	DCI0:QUIET
46	DCI1:NMASK_TERM_SPLIT[0]	DCI0:NMASK_TERM_SPLIT[0]
47	DCI1:NMASK_TERM_SPLIT[1]	DCI0:NMASK_TERM_SPLIT[1]
48	DCI1:NMASK_TERM_SPLIT[2]	DCI0:NMASK_TERM_SPLIT[2]
49	DCI1:NMASK_TERM_SPLIT[3]	DCI0:NMASK_TERM_SPLIT[3]
50	-	MISC:DCI_TEST_MUX
51	DCI1:PMASK_TERM_VCC[0]	DCI0:PMASK_TERM_VCC[0]
52	DCI1:PMASK_TERM_VCC[1]	DCI0:PMASK_TERM_VCC[1]
53	DCI1:PMASK_TERM_VCC[2]	DCI0:PMASK_TERM_VCC[2]
54	DCI1:PMASK_TERM_VCC[3]	DCI0:PMASK_TERM_VCC[3]
55	-	-
56	DCI1:PMASK_TERM_SPLIT[0]	DCI0:PMASK_TERM_SPLIT[0]
57	DCI1:PMASK_TERM_SPLIT[1]	DCI0:PMASK_TERM_SPLIT[1]
58	DCI1:PMASK_TERM_SPLIT[2]	DCI0:PMASK_TERM_SPLIT[2]
59	DCI1:PMASK_TERM_SPLIT[3]	DCI0:PMASK_TERM_SPLIT[3]
60	-	-
61	DCI1:FORCE_DONE_HIGH	DCI0:FORCE_DONE_HIGH
62	DCI1:TEST_ENABLE	DCI0:TEST_ENABLE
63	DCIRESET1:ENABLE	DCIRESET0:ENABLE

DCI0:LVDSBIAS	[0, 0, 33]	[0, 0, 34]	[0, 0, 35]	[0, 0, 36]	[0, 0, 37]	[0, 0, 38]	[0, 0, 39]	[0, 0, 40]	[0, 0, 41]	[0, 0, 42]	[0, 0, 43]	[0, 0, 23]	[0, 0, 24]
DCI1:LVDSBIAS	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 31]	[0, 1, 32]
Non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:M0PIN	[0, 0, 27]	[0, 0, 28]
MISC:M1PIN	[0, 0, 25]	[0, 0, 26]
MISC:M2PIN	[0, 0, 29]	[0, 0, 30]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

DCI0:ENABLE	[0, 1, 44]
DCI0:FORCE_DONE_HIGH	[0, 1, 61]
DCI0:QUIET	[0, 1, 45]
DCI0:TEST_ENABLE	[0, 1, 62]
DCI1:ENABLE	[0, 0, 44]
DCI1:FORCE_DONE_HIGH	[0, 0, 61]
DCI1:QUIET	[0, 0, 45]
DCI1:TEST_ENABLE	[0, 0, 62]
DCIRESET0:ENABLE	[0, 1, 63]
DCIRESET1:ENABLE	[0, 0, 63]
MISC:DCI_CLK_ENABLE	[0, 1, 0]
MISC:DCM_ENABLE	[0, 1, 5]
MISC:GATE_GHIGH	[0, 1, 1]
MISC:VGG_ENABLE_OFFCHIP	[0, 1, 13]
MISC:VGG_SENDMAX	[0, 1, 12]
Non-inverted	[0]

DCI0:NMASK_TERM_SPLIT	[0, 1, 49]	[0, 1, 48]	[0, 1, 47]	[0, 1, 46]
DCI0:PMASK_TERM_SPLIT	[0, 1, 59]	[0, 1, 58]	[0, 1, 57]	[0, 1, 56]
DCI0:PMASK_TERM_VCC	[0, 1, 54]	[0, 1, 53]	[0, 1, 52]	[0, 1, 51]
DCI1:NMASK_TERM_SPLIT	[0, 0, 49]	[0, 0, 48]	[0, 0, 47]	[0, 0, 46]
DCI1:PMASK_TERM_SPLIT	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]	[0, 0, 56]
DCI1:PMASK_TERM_VCC	[0, 0, 54]	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
MISC:SEND_VGG	[0, 1, 11]	[0, 1, 10]	[0, 1, 9]	[0, 1, 8]
Non-inverted	[3]	[2]	[1]	[0]

MISC:DCI_OSC_SEL	[0, 1, 4]	[0, 1, 3]	[0, 1, 2]
Non-inverted	[2]	[1]	[0]

MISC:DCI_TEST_MUX	[0, 1, 50]
DCI0	0
DCI1	1

LL.S3E

This tile is used on Spartan 3E.

LL.S3E bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	-	MISC:SEND_VGG[0]
9	-	MISC:SEND_VGG[1]
10	-	MISC:SEND_VGG[2]
11	-	MISC:SEND_VGG[3]
12	-	MISC:VGG_SENDMAX
13	-	MISC:VGG_ENABLE_OFFCHIP
14	-	-
15	-	-
16	-	-
17	-	MISC:TEMPSENSOR[2]
18	-	MISC:TEMPSENSOR[1]
19	-	-
20	-	-
21	-	MISC:TEMPSENSOR[0]
22	-	BANK:LVDSBIAS_1[5]
23	-	BANK:LVDSBIAS_0[4]
24	-	BANK:LVDSBIAS_0[3]
25	-	BANK:LVDSBIAS_0[2]
26	-	BANK:LVDSBIAS_0[1]
27	-	BANK:LVDSBIAS_1[4]
28	-	BANK:LVDSBIAS_1[3]
29	-	BANK:LVDSBIAS_1[2]
30	-	BANK:LVDSBIAS_1[1]
31	-	BANK:LVDSBIAS_0[0]
32	-	BANK:LVDSBIAS_1[0]
33	-	BANK:LVDSBIAS_0[10]
34	-	BANK:LVDSBIAS_0[9]
35	-	BANK:LVDSBIAS_0[8]
36	-	BANK:LVDSBIAS_0[7]
37	-	BANK:LVDSBIAS_0[6]
38	-	BANK:LVDSBIAS_0[5]
39	-	BANK:LVDSBIAS_1[10]
40	-	BANK:LVDSBIAS_1[9]
41	-	BANK:LVDSBIAS_1[8]
42	-	BANK:LVDSBIAS_1[7]
43	-	BANK:LVDSBIAS_1[6]

MISC:SEND_VGG	[0, 1, 11]	[0, 1, 10]	[0, 1, 9]	[0, 1, 8]
Non-inverted	[3]	[2]	[1]	[0]

MISC:VGG_ENABLE_OFFCHIP	[0, 1, 13]
MISC:VGG_SENDMAX	[0, 1, 12]
Non-inverted	[0]

MISC:TEMPSENSOR	[0, 1, 17]	[0, 1, 18]	[0, 1, 21]
NONE	0	0	0
THERM	0	0	1
PGATE	0	1	1
BG	1	0	1
CGATE	1	1	1

BANK:LVDSBIAS_0	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 23]	[0, 1, 24]	[0, 1, 25]	[0, 1, 26]	[0, 1, 31]
BANK:LVDSBIAS_1	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 22]	[0, 1, 27]	[0, 1, 28]	[0, 1, 29]	[0, 1, 30]	[0, 1, 32]
Non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

LL.S3A

This tile is used on Spartan 3A.

LL.S3A bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	MISC:TEMPSENSOR[2]
4	-	MISC:TEMPSENSOR[3]
5	-	-
6	BANK:LVDSBIAS_1[11]	-
7	MISC:TEMPSENSOR[0]	MISC:TEMPSENSOR[1]
8	-	-
9	BANK:LVDSBIAS_0[11]	BANK:LVDSBIAS_1[7]
10	BANK:LVDSBIAS_0[6]	BANK:LVDSBIAS_0[10]
11	-	BANK:LVDSBIAS_0[7]
12	MISC:UNK_ALWAYS_SET[0]	MISC:UNK_ALWAYS_SET[2]
13	MISC:UNK_ALWAYS_SET[1]	-
14	-	MISC:UNK_ALWAYS_SET[3]
15	MISC:CCLK2PIN[0]	MISC:CCLK2PIN[1]
16	-	-
17	-	-
18	-	MISC:SEND_VGG[0]
19	-	MISC:SEND_VGG[1]
20	-	MISC:SEND_VGG[2]
21	-	MISC:SEND_VGG[3]
22	-	MISC:VGG_SENDMAX
23	-	MISC:VGG_ENABLE_OFFCHIP
24	MISC:MOSI2PIN[1]	MISC:MOSI2PIN[0]
25	-	-
26	BANK:LVDSBIAS_1[2]	BANK:LVDSBIAS_1[3]
27	BANK:LVDSBIAS_0[1]	BANK:LVDSBIAS_1[0]
28	BANK:LVDSBIAS_1[1]	BANK:LVDSBIAS_0[5]
29	BANK:LVDSBIAS_1[9]	-
30	BANK:LVDSBIAS_1[6]	BANK:LVDSBIAS_0[3]
31	BANK:LVDSBIAS_0[2]	-
32	-	BANK:LVDSBIAS_0[0]
33	-	BANK:LVDSBIAS_0[9]
34	-	BANK:LVDSBIAS_0[8]
35	-	BANK:LVDSBIAS_1[8]
36	-	BANK:LVDSBIAS_0[4]
37	-	-
38	-	-
39	-	-
40	-	-
41	-	-
42	-	-
43	-	-
44	-	-
45	-	-
46	-	-
47	-	-
48	-	-
49	-	-
50	-	-
51	-	-
52	-	-
53	-	-
54	-	-
55	-	-
56	-	-
57	-	-
58	-	-
59	-	-
60	-	-
61	-	-
62	BANK:LVDSBIAS_1[10]	BANK:LVDSBIAS_1[4]
63	-	BANK:LVDSBIAS_1[5]

MISC:TEMPSENSOR	[0, 1, 4]	[0, 1, 3]	[0, 1, 7]	[0, 0, 7]
NONE	0	0	0	0
THERM	0	0	1	1
PGATE	0	1	1	1
BG	1	0	1	1
CGATE	1	1	1	1

MISC:SEND_VGG	[0, 1, 21]	[0, 1, 20]	[0, 1, 19]	[0, 1, 18]
MISC:UNK_ALWAYS_SET	[0, 1, 14]	[0, 1, 12]	[0, 0, 13]	[0, 0, 12]
Non-inverted	[3]	[2]	[1]	[0]

MISC:CCLK2PIN	[0, 1, 15]	[0, 0, 15]
MISC:MOSI2PIN	[0, 0, 24]	[0, 1, 24]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:VGG_ENABLE_OFFCHIP	[0, 1, 23]
MISC:VGG_SENDMAX	[0, 1, 22]
Non-inverted	[0]

BANK:LVDSBIAS_0	[0, 0, 9]	[0, 1, 10]	[0, 1, 33]	[0, 1, 34]	[0, 1, 11]	[0, 0, 10]	[0, 1, 28]	[0, 1, 36]	[0, 1, 30]	[0, 0, 31]	[0, 0, 27]	[0, 1, 32]
BANK:LVDSBIAS_1	[0, 0, 6]	[0, 0, 62]	[0, 0, 29]	[0, 1, 35]	[0, 1, 9]	[0, 0, 30]	[0, 1, 63]	[0, 1, 62]	[0, 1, 26]	[0, 0, 26]	[0, 0, 28]	[0, 1, 27]
Non-inverted	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

Upper left

Todo

document

UL.S3

This tile is used on Spartan 3.

UL.S3 bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	MISC:DCM_ENABLE	-
9	-	-
10	-	-
11	-	-
12	-	-
13	-	-
14	-	-
15	-	-
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	-
23	-	-
24	-	-
25	-	MISC:PROGPIN
26	-	MISC:HSWAPENPIN[1]
27	-	MISC:HSWAPENPIN[0]
28	-	MISC:TDIPIN[0]
29	DCI1:LVDSBIAS[1]	MISC:TDIPIN[1]
30	-	DCI0:LVDSBIAS[1]
31	-	DCI0:LVDSBIAS[0]
32	DCI1:LVDSBIAS[0]	MISC:TEST_LL
33	DCI1:LVDSBIAS[12]	DCI0:LVDSBIAS[12]
34	DCI1:LVDSBIAS[11]	DCI0:LVDSBIAS[11]
35	DCI1:LVDSBIAS[10]	DCI0:LVDSBIAS[10]
36	DCI1:LVDSBIAS[9]	DCI0:LVDSBIAS[9]
37	DCI1:LVDSBIAS[8]	DCI0:LVDSBIAS[8]
38	DCI1:LVDSBIAS[7]	DCI0:LVDSBIAS[7]
39	DCI1:LVDSBIAS[6]	DCI0:LVDSBIAS[6]
40	DCI1:LVDSBIAS[5]	DCI0:LVDSBIAS[5]
41	DCI1:LVDSBIAS[4]	DCI0:LVDSBIAS[4]
42	DCI1:LVDSBIAS[3]	DCI0:LVDSBIAS[3]
43	DCI1:LVDSBIAS[2]	DCI0:LVDSBIAS[2]
44	DCI0:ENABLE	DCI1:ENABLE
45	DCI0:QUIET	DCI1:QUIET
46	DCI0:NMASK_TERM_SPLIT[0]	DCI1:NMASK_TERM_SPLIT[0]
47	DCI0:NMASK_TERM_SPLIT[1]	DCI1:NMASK_TERM_SPLIT[1]
48	DCI0:NMASK_TERM_SPLIT[2]	DCI1:NMASK_TERM_SPLIT[2]
49	DCI0:NMASK_TERM_SPLIT[3]	DCI1:NMASK_TERM_SPLIT[3]
50	MISC:DCI_TEST_MUX	-
51	DCI0:PMASK_TERM_VCC[0]	DCI1:PMASK_TERM_VCC[0]
52	DCI0:PMASK_TERM_VCC[1]	DCI1:PMASK_TERM_VCC[1]
53	DCI0:PMASK_TERM_VCC[2]	DCI1:PMASK_TERM_VCC[2]
54	DCI0:PMASK_TERM_VCC[3]	DCI1:PMASK_TERM_VCC[3]
55	-	-
56	DCI0:PMASK_TERM_SPLIT[0]	DCI1:PMASK_TERM_SPLIT[0]
57	DCI0:PMASK_TERM_SPLIT[1]	DCI1:PMASK_TERM_SPLIT[1]
58	DCI0:PMASK_TERM_SPLIT[2]	DCI1:PMASK_TERM_SPLIT[2]
59	DCI0:PMASK_TERM_SPLIT[3]	DCI1:PMASK_TERM_SPLIT[3]
60	-	-
61	DCI0:FORCE_DONE_HIGH	DCI1:FORCE_DONE_HIGH
62	DCI0:TEST_ENABLE	DCI1:TEST_ENABLE
63	DCIRESET0:ENABLE	DCIRESET1:ENABLE

DCI0:ENABLE	[0, 0, 44]
DCI0:FORCE_DONE_HIGH	[0, 0, 61]
DCI0:QUIET	[0, 0, 45]
DCI0:TEST_ENABLE	[0, 0, 62]
DCI1:ENABLE	[0, 1, 44]
DCI1:FORCE_DONE_HIGH	[0, 1, 61]
DCI1:QUIET	[0, 1, 45]
DCI1:TEST_ENABLE	[0, 1, 62]
DCIRESET0:ENABLE	[0, 0, 63]
DCIRESET1:ENABLE	[0, 1, 63]
MISC:DCM_ENABLE	[0, 0, 8]
MISC:TEST_LL	[0, 1, 32]
Non-inverted	[0]

DCI0:LVDSBIAS	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 30]	[0, 1, 31]
DCI1:LVDSBIAS	[0, 0, 33]	[0, 0, 34]	[0, 0, 35]	[0, 0, 36]	[0, 0, 37]	[0, 0, 38]	[0, 0, 39]	[0, 0, 40]	[0, 0, 41]	[0, 0, 42]	[0, 0, 43]	[0, 0, 29]	[0, 0, 32]
Non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCI0:NMASK_TERM_SPLIT	[0, 0, 49]	[0, 0, 48]	[0, 0, 47]	[0, 0, 46]
DCI0:PMASK_TERM_SPLIT	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]	[0, 0, 56]
DCI0:PMASK_TERM_VCC	[0, 0, 54]	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
DCI1:NMASK_TERM_SPLIT	[0, 1, 49]	[0, 1, 48]	[0, 1, 47]	[0, 1, 46]
DCI1:PMASK_TERM_SPLIT	[0, 1, 59]	[0, 1, 58]	[0, 1, 57]	[0, 1, 56]
DCI1:PMASK_TERM_VCC	[0, 1, 54]	[0, 1, 53]	[0, 1, 52]	[0, 1, 51]
Non-inverted	[3]	[2]	[1]	[0]

MISC:DCI_TEST_MUX	[0, 0, 50]
DCI0	0
DCI1	1

MISC:PROGPIN	[0, 1, 25]
PULLUP	0
PULLNONE	1

MISC:HSWAPENPIN	[0, 1, 26]	[0, 1, 27]
MISC:TDIPIN	[0, 1, 29]	[0, 1, 28]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

UL.S3E

This tile is used on Spartan 3E.

UL.S3E bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	-	-
9	-	-
10	-	-
11	-	-
12	-	-
13	-	-
14	-	-
15	-	-
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	BANK:LVDSBIAS_0[10]	-
23	BANK:LVDSBIAS_0[9]	-
24	BANK:LVDSBIAS_0[8]	-
25	BANK:LVDSBIAS_0[7]	MISC:PROGPIN
26	BANK:LVDSBIAS_0[6]	-
27	BANK:LVDSBIAS_0[5]	-
28	BANK:LVDSBIAS_1[10]	MISC:TDIPIN[0]
29	BANK:LVDSBIAS_1[9]	MISC:TDIPIN[1]
30	-	-
31	-	-
32	BANK:LVDSBIAS_1[8]	MISC:TEST_LL
33	BANK:LVDSBIAS_1[7]	-
34	BANK:LVDSBIAS_1[6]	-
35	BANK:LVDSBIAS_1[5]	-
36	BANK:LVDSBIAS_0[4]	-
37	BANK:LVDSBIAS_0[3]	-
38	BANK:LVDSBIAS_0[2]	-
39	BANK:LVDSBIAS_0[1]	-
40	BANK:LVDSBIAS_1[4]	-
41	BANK:LVDSBIAS_1[3]	-
42	BANK:LVDSBIAS_1[2]	-
43	BANK:LVDSBIAS_1[1]	-
44	BANK:LVDSBIAS_0[0]	-
45	BANK:LVDSBIAS_1[0]	-

BANK:LVDSBIAS_0	[0, 0, 22]	[0, 0, 23]	[0, 0, 24]	[0, 0, 25]	[0, 0, 26]	[0, 0, 27]	[0, 0, 36]	[0, 0, 37]	[0, 0, 38]	[0, 0, 39]	[0, 0, 44]
BANK:LVDSBIAS_1	[0, 0, 28]	[0, 0, 29]	[0, 0, 32]	[0, 0, 33]	[0, 0, 34]	[0, 0, 35]	[0, 0, 40]	[0, 0, 41]	[0, 0, 42]	[0, 0, 43]	[0, 0, 45]
Non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:PROGPIN	[0, 1, 25]
PULLUP	0
PULLNONE	1

MISC:TDIPIN	[0, 1, 29]	[0, 1, 28]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:TEST_LL	[0, 1, 32]
Non-inverted	[0]

UL.S3A

This tile is used on Spartan 3A.

UL.S3A bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	-	-
9	-	-
10	-	-
11	-	-
12	-	-
13	-	-
14	-	-
15	-	-
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	-
23	-	-
24	-	-
25	-	MISC:PROGPIN
26	-	-
27	-	-
28	-	MISC:TDIPIN[0]
29	-	MISC:TDIPIN[1]
30	MISC:TMSPIN[0]	-
31	MISC:TMSPIN[1]	-
32	-	MISC:TEST_LL
33	-	-
34	-	-
35	-	-
36	-	-
37	-	-
38	-	-
39	-	-
40	-	BANK:LVDSBIAS_0[11]
41	-	BANK:LVDSBIAS_0[10]
42	-	BANK:LVDSBIAS_0[9]
43	-	BANK:LVDSBIAS_0[8]
44	-	BANK:LVDSBIAS_0[7]
45	-	BANK:LVDSBIAS_0[6]
46	-	BANK:LVDSBIAS_1[11]
47	-	BANK:LVDSBIAS_1[10]
48	-	BANK:LVDSBIAS_1[9]
49	-	BANK:LVDSBIAS_1[8]
50	-	BANK:LVDSBIAS_1[7]
51	-	BANK:LVDSBIAS_1[6]
52	-	BANK:LVDSBIAS_0[5]
53	-	BANK:LVDSBIAS_0[4]
54	-	BANK:LVDSBIAS_0[3]
55	-	BANK:LVDSBIAS_0[2]
56	-	BANK:LVDSBIAS_1[5]
57	-	BANK:LVDSBIAS_1[4]
58	-	BANK:LVDSBIAS_1[3]
59	-	BANK:LVDSBIAS_1[2]
60	-	BANK:LVDSBIAS_0[1]
61	-	BANK:LVDSBIAS_1[1]
62	-	BANK:LVDSBIAS_0[0]
63	-	BANK:LVDSBIAS_1[0]

MISC:TDIPIN	[0, 1, 29]	[0, 1, 28]
MISC:TMSPIN	[0, 0, 31]	[0, 0, 30]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:PROGPIN	[0, 1, 25]
PULLUP	0
PULLNONE	1

MISC:TEST_LL	[0, 1, 32]
Non-inverted	[0]

BANK:LVDSBIAS_0	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 44]	[0, 1, 45]	[0, 1, 52]	[0, 1, 53]	[0, 1, 54]	[0, 1, 55]	[0, 1, 60]	[0, 1, 62]
BANK:LVDSBIAS_1	[0, 1, 46]	[0, 1, 47]	[0, 1, 48]	[0, 1, 49]	[0, 1, 50]	[0, 1, 51]	[0, 1, 56]	[0, 1, 57]	[0, 1, 58]	[0, 1, 59]	[0, 1, 61]	[0, 1, 63]
Non-inverted	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

Lower right

Todo

document

LR.S3

This tile is used on Spartan 3.

LR.S3 bittile 0
Row	Column
	0	1
0	-	STARTUP:GSR_SYNC
1	-	STARTUP:GTS_SYNC
2	-	-
3	-	ICAP:ENABLE
4	-	STARTUP:GTS_GSR_ENABLE
5	-	-
6	-	-
7	-	-
8	-	-
9	-	DCI0:LVDSBIAS[1]
10	-	DCI0:LVDSBIAS[0]
11	-	DCI1:LVDSBIAS[1]
12	-	DCI1:LVDSBIAS[0]
13	-	MISC:DCM_ENABLE
14	-	MISC:DONEPIN
15	-	MISC:CCLKPIN
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	DCI0:LVDSBIAS[12]
23	-	DCI0:LVDSBIAS[11]
24	-	DCI0:LVDSBIAS[10]
25	-	DCI0:LVDSBIAS[9]
26	-	DCI0:LVDSBIAS[8]
27	-	DCI0:LVDSBIAS[7]
28	-	DCI0:LVDSBIAS[6]
29	-	DCI0:LVDSBIAS[5]
30	-	DCI0:LVDSBIAS[4]
31	-	DCI0:LVDSBIAS[3]
32	-	DCI0:LVDSBIAS[2]
33	-	DCI1:LVDSBIAS[12]
34	-	DCI1:LVDSBIAS[11]
35	-	DCI1:LVDSBIAS[10]
36	-	DCI1:LVDSBIAS[9]
37	-	DCI1:LVDSBIAS[8]
38	-	DCI1:LVDSBIAS[7]
39	-	DCI1:LVDSBIAS[6]
40	-	DCI1:LVDSBIAS[5]
41	-	DCI1:LVDSBIAS[4]
42	-	DCI1:LVDSBIAS[3]
43	-	DCI1:LVDSBIAS[2]
44	DCI0:ENABLE	DCI1:ENABLE
45	DCI0:QUIET	DCI1:QUIET
46	DCI0:NMASK_TERM_SPLIT[0]	DCI1:NMASK_TERM_SPLIT[0]
47	DCI0:NMASK_TERM_SPLIT[1]	DCI1:NMASK_TERM_SPLIT[1]
48	DCI0:NMASK_TERM_SPLIT[2]	DCI1:NMASK_TERM_SPLIT[2]
49	DCI0:NMASK_TERM_SPLIT[3]	DCI1:NMASK_TERM_SPLIT[3]
50	MISC:DCI_TEST_MUX	-
51	DCI0:PMASK_TERM_VCC[0]	DCI1:PMASK_TERM_VCC[0]
52	DCI0:PMASK_TERM_VCC[1]	DCI1:PMASK_TERM_VCC[1]
53	DCI0:PMASK_TERM_VCC[2]	DCI1:PMASK_TERM_VCC[2]
54	DCI0:PMASK_TERM_VCC[3]	DCI1:PMASK_TERM_VCC[3]
55	-	-
56	DCI0:PMASK_TERM_SPLIT[0]	DCI1:PMASK_TERM_SPLIT[0]
57	DCI0:PMASK_TERM_SPLIT[1]	DCI1:PMASK_TERM_SPLIT[1]
58	DCI0:PMASK_TERM_SPLIT[2]	DCI1:PMASK_TERM_SPLIT[2]
59	DCI0:PMASK_TERM_SPLIT[3]	DCI1:PMASK_TERM_SPLIT[3]
60	-	-
61	DCI0:FORCE_DONE_HIGH	DCI1:FORCE_DONE_HIGH
62	DCI0:TEST_ENABLE	DCI1:TEST_ENABLE
63	DCIRESET0:ENABLE	DCIRESET1:ENABLE

DCI0:ENABLE	[0, 0, 44]
DCI0:FORCE_DONE_HIGH	[0, 0, 61]
DCI0:QUIET	[0, 0, 45]
DCI0:TEST_ENABLE	[0, 0, 62]
DCI1:ENABLE	[0, 1, 44]
DCI1:FORCE_DONE_HIGH	[0, 1, 61]
DCI1:QUIET	[0, 1, 45]
DCI1:TEST_ENABLE	[0, 1, 62]
DCIRESET0:ENABLE	[0, 0, 63]
DCIRESET1:ENABLE	[0, 1, 63]
ICAP:ENABLE	[0, 1, 3]
MISC:DCM_ENABLE	[0, 1, 13]
STARTUP:GSR_SYNC	[0, 1, 0]
STARTUP:GTS_GSR_ENABLE	[0, 1, 4]
STARTUP:GTS_SYNC	[0, 1, 1]
Non-inverted	[0]

DCI0:NMASK_TERM_SPLIT	[0, 0, 49]	[0, 0, 48]	[0, 0, 47]	[0, 0, 46]
DCI0:PMASK_TERM_SPLIT	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]	[0, 0, 56]
DCI0:PMASK_TERM_VCC	[0, 0, 54]	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
DCI1:NMASK_TERM_SPLIT	[0, 1, 49]	[0, 1, 48]	[0, 1, 47]	[0, 1, 46]
DCI1:PMASK_TERM_SPLIT	[0, 1, 59]	[0, 1, 58]	[0, 1, 57]	[0, 1, 56]
DCI1:PMASK_TERM_VCC	[0, 1, 54]	[0, 1, 53]	[0, 1, 52]	[0, 1, 51]
Non-inverted	[3]	[2]	[1]	[0]

MISC:DCI_TEST_MUX	[0, 0, 50]
DCI0	0
DCI1	1

DCI0:LVDSBIAS	[0, 1, 22]	[0, 1, 23]	[0, 1, 24]	[0, 1, 25]	[0, 1, 26]	[0, 1, 27]	[0, 1, 28]	[0, 1, 29]	[0, 1, 30]	[0, 1, 31]	[0, 1, 32]	[0, 1, 9]	[0, 1, 10]
DCI1:LVDSBIAS	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 11]	[0, 1, 12]
Non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:CCLKPIN	[0, 1, 15]
MISC:DONEPIN	[0, 1, 14]
PULLUP	0
PULLNONE	1

LR.S3E

This tile is used on Spartan 3E.

LR.S3E bittile 0
Row	Column
	0	1
0	-	STARTUP:GSR_SYNC
1	-	STARTUP:GTS_SYNC
2	-	-
3	-	-
4	-	STARTUP:GTS_GSR_ENABLE
5	-	-
6	-	-
7	-	BANK:LVDSBIAS_0[1]
8	-	BANK:LVDSBIAS_1[4]
9	-	BANK:LVDSBIAS_1[3]
10	-	BANK:LVDSBIAS_1[2]
11	-	BANK:LVDSBIAS_1[1]
12	-	BANK:LVDSBIAS_0[0]
13	-	BANK:LVDSBIAS_1[0]
14	-	MISC:DONEPIN
15	-	MISC:CCLKPIN
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	BANK:LVDSBIAS_0[10]
23	-	BANK:LVDSBIAS_0[9]
24	-	BANK:LVDSBIAS_0[8]
25	-	BANK:LVDSBIAS_0[7]
26	-	BANK:LVDSBIAS_0[6]
27	-	BANK:LVDSBIAS_0[5]
28	-	BANK:LVDSBIAS_1[10]
29	-	BANK:LVDSBIAS_1[9]
30	-	BANK:LVDSBIAS_1[8]
31	-	BANK:LVDSBIAS_1[7]
32	-	BANK:LVDSBIAS_1[6]
33	-	BANK:LVDSBIAS_1[5]
34	-	BANK:LVDSBIAS_0[4]
35	-	BANK:LVDSBIAS_0[3]
36	-	BANK:LVDSBIAS_0[2]

STARTUP:GSR_SYNC	[0, 1, 0]
STARTUP:GTS_GSR_ENABLE	[0, 1, 4]
STARTUP:GTS_SYNC	[0, 1, 1]
Non-inverted	[0]

BANK:LVDSBIAS_0	[0, 1, 22]	[0, 1, 23]	[0, 1, 24]	[0, 1, 25]	[0, 1, 26]	[0, 1, 27]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 7]	[0, 1, 12]
BANK:LVDSBIAS_1	[0, 1, 28]	[0, 1, 29]	[0, 1, 30]	[0, 1, 31]	[0, 1, 32]	[0, 1, 33]	[0, 1, 8]	[0, 1, 9]	[0, 1, 10]	[0, 1, 11]	[0, 1, 13]
Non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:CCLKPIN	[0, 1, 15]
MISC:DONEPIN	[0, 1, 14]
PULLUP	0
PULLNONE	1

LR.S3A

This tile is used on Spartan 3A.

LR.S3A bittile 0
Row	Column
	0	1
0	-	STARTUP:GSR_SYNC
1	-	STARTUP:GTS_SYNC
2	-	-
3	-	SPI_ACCESS:ENABLE
4	-	STARTUP:GTS_GSR_ENABLE
5	-	-
6	-	MISC:DONEPIN

SPI_ACCESS:ENABLE	[0, 1, 3]
STARTUP:GSR_SYNC	[0, 1, 0]
STARTUP:GTS_GSR_ENABLE	[0, 1, 4]
STARTUP:GTS_SYNC	[0, 1, 1]
Non-inverted	[0]

MISC:DONEPIN	[0, 1, 6]
PULLUP	0
PULLNONE	1

Upper right

Todo

document

UR.S3

This tile is used on Spartan 3.

UR.S3 bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	-	-
9	-	DCI1:LVDSBIAS[1]
10	DCI0:LVDSBIAS[1]	DCI1:LVDSBIAS[0]
11	DCI0:LVDSBIAS[0]	MISC:DCM_ENABLE
12	-	-
13	MISC:TDOPIN[1]	MISC:TDOPIN[0]
14	MISC:TCKPIN[0]	MISC:TCKPIN[1]
15	MISC:TMSPIN[1]	MISC:TMSPIN[0]
16	BSCAN:TDO_ENABLE[0]	BSCAN:TDO_ENABLE[1]
17	~BSCAN:USERID[31]	~BSCAN:USERID[30]
18	~BSCAN:USERID[28]	~BSCAN:USERID[29]
19	~BSCAN:USERID[27]	~BSCAN:USERID[26]
20	~BSCAN:USERID[24]	~BSCAN:USERID[25]
21	~BSCAN:USERID[23]	~BSCAN:USERID[22]
22	~BSCAN:USERID[21]	~BSCAN:USERID[20]
23	~BSCAN:USERID[19]	~BSCAN:USERID[18]
24	~BSCAN:USERID[17]	~BSCAN:USERID[16]
25	~BSCAN:USERID[15]	~BSCAN:USERID[14]
26	~BSCAN:USERID[13]	~BSCAN:USERID[12]
27	~BSCAN:USERID[11]	~BSCAN:USERID[10]
28	~BSCAN:USERID[9]	~BSCAN:USERID[8]
29	~BSCAN:USERID[7]	~BSCAN:USERID[6]
30	~BSCAN:USERID[5]	~BSCAN:USERID[4]
31	~BSCAN:USERID[3]	~BSCAN:USERID[2]
32	~BSCAN:USERID[1]	~BSCAN:USERID[0]
33	DCI0:LVDSBIAS[12]	DCI1:LVDSBIAS[12]
34	DCI0:LVDSBIAS[11]	DCI1:LVDSBIAS[11]
35	DCI0:LVDSBIAS[10]	DCI1:LVDSBIAS[10]
36	DCI0:LVDSBIAS[9]	DCI1:LVDSBIAS[9]
37	DCI0:LVDSBIAS[8]	DCI1:LVDSBIAS[8]
38	DCI0:LVDSBIAS[7]	DCI1:LVDSBIAS[7]
39	DCI0:LVDSBIAS[6]	DCI1:LVDSBIAS[6]
40	DCI0:LVDSBIAS[5]	DCI1:LVDSBIAS[5]
41	DCI0:LVDSBIAS[4]	DCI1:LVDSBIAS[4]
42	DCI0:LVDSBIAS[3]	DCI1:LVDSBIAS[3]
43	DCI0:LVDSBIAS[2]	DCI1:LVDSBIAS[2]
44	DCI0:ENABLE	DCI1:ENABLE
45	DCI0:QUIET	DCI1:QUIET
46	DCI0:NMASK_TERM_SPLIT[0]	DCI1:NMASK_TERM_SPLIT[0]
47	DCI0:NMASK_TERM_SPLIT[1]	DCI1:NMASK_TERM_SPLIT[1]
48	DCI0:NMASK_TERM_SPLIT[2]	DCI1:NMASK_TERM_SPLIT[2]
49	DCI0:NMASK_TERM_SPLIT[3]	DCI1:NMASK_TERM_SPLIT[3]
50	MISC:DCI_TEST_MUX	-
51	DCI0:PMASK_TERM_VCC[0]	DCI1:PMASK_TERM_VCC[0]
52	DCI0:PMASK_TERM_VCC[1]	DCI1:PMASK_TERM_VCC[1]
53	DCI0:PMASK_TERM_VCC[2]	DCI1:PMASK_TERM_VCC[2]
54	DCI0:PMASK_TERM_VCC[3]	DCI1:PMASK_TERM_VCC[3]
55	-	-
56	DCI0:PMASK_TERM_SPLIT[0]	DCI1:PMASK_TERM_SPLIT[0]
57	DCI0:PMASK_TERM_SPLIT[1]	DCI1:PMASK_TERM_SPLIT[1]
58	DCI0:PMASK_TERM_SPLIT[2]	DCI1:PMASK_TERM_SPLIT[2]
59	DCI0:PMASK_TERM_SPLIT[3]	DCI1:PMASK_TERM_SPLIT[3]
60	-	-
61	DCI0:FORCE_DONE_HIGH	DCI1:FORCE_DONE_HIGH
62	DCI0:TEST_ENABLE	DCI1:TEST_ENABLE
63	DCIRESET0:ENABLE	DCIRESET1:ENABLE

DCI0:LVDSBIAS	[0, 0, 33]	[0, 0, 34]	[0, 0, 35]	[0, 0, 36]	[0, 0, 37]	[0, 0, 38]	[0, 0, 39]	[0, 0, 40]	[0, 0, 41]	[0, 0, 42]	[0, 0, 43]	[0, 0, 10]	[0, 0, 11]
DCI1:LVDSBIAS	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 9]	[0, 1, 10]
Non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:TCKPIN	[0, 1, 14]	[0, 0, 14]
MISC:TDOPIN	[0, 0, 13]	[0, 1, 13]
MISC:TMSPIN	[0, 0, 15]	[0, 1, 15]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

BSCAN:TDO_ENABLE	[0, 1, 16]	[0, 0, 16]
Non-inverted	[1]	[0]

DCI0:ENABLE	[0, 0, 44]
DCI0:FORCE_DONE_HIGH	[0, 0, 61]
DCI0:QUIET	[0, 0, 45]
DCI0:TEST_ENABLE	[0, 0, 62]
DCI1:ENABLE	[0, 1, 44]
DCI1:FORCE_DONE_HIGH	[0, 1, 61]
DCI1:QUIET	[0, 1, 45]
DCI1:TEST_ENABLE	[0, 1, 62]
DCIRESET0:ENABLE	[0, 0, 63]
DCIRESET1:ENABLE	[0, 1, 63]
MISC:DCM_ENABLE	[0, 1, 11]
Non-inverted	[0]

DCI0:NMASK_TERM_SPLIT	[0, 0, 49]	[0, 0, 48]	[0, 0, 47]	[0, 0, 46]
DCI0:PMASK_TERM_SPLIT	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]	[0, 0, 56]
DCI0:PMASK_TERM_VCC	[0, 0, 54]	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
DCI1:NMASK_TERM_SPLIT	[0, 1, 49]	[0, 1, 48]	[0, 1, 47]	[0, 1, 46]
DCI1:PMASK_TERM_SPLIT	[0, 1, 59]	[0, 1, 58]	[0, 1, 57]	[0, 1, 56]
DCI1:PMASK_TERM_VCC	[0, 1, 54]	[0, 1, 53]	[0, 1, 52]	[0, 1, 51]
Non-inverted	[3]	[2]	[1]	[0]

MISC:DCI_TEST_MUX	[0, 0, 50]
DCI0	0
DCI1	1

BSCAN:USERID	[0, 0, 17]	[0, 1, 17]	[0, 1, 18]	[0, 0, 18]	[0, 0, 19]	[0, 1, 19]	[0, 1, 20]	[0, 0, 20]	[0, 0, 21]	[0, 1, 21]	[0, 0, 22]	[0, 1, 22]	[0, 0, 23]	[0, 1, 23]	[0, 0, 24]	[0, 1, 24]	[0, 0, 25]	[0, 1, 25]	[0, 0, 26]	[0, 1, 26]	[0, 0, 27]	[0, 1, 27]	[0, 0, 28]	[0, 1, 28]	[0, 0, 29]	[0, 1, 29]	[0, 0, 30]	[0, 1, 30]	[0, 0, 31]	[0, 1, 31]	[0, 0, 32]	[0, 1, 32]
Inverted	~[31]	~[30]	~[29]	~[28]	~[27]	~[26]	~[25]	~[24]	~[23]	~[22]	~[21]	~[20]	~[19]	~[18]	~[17]	~[16]	~[15]	~[14]	~[13]	~[12]	~[11]	~[10]	~[9]	~[8]	~[7]	~[6]	~[5]	~[4]	~[3]	~[2]	~[1]	~[0]

UR.S3E

This tile is used on Spartan 3E.

UR.S3E bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	-	-
8	-	-
9	-	BANK:LVDSBIAS_1[1]
10	-	BANK:LVDSBIAS_0[0]
11	-	BANK:LVDSBIAS_1[0]
12	-	-
13	MISC:TDOPIN[1]	MISC:TDOPIN[0]
14	MISC:TCKPIN[0]	MISC:TCKPIN[1]
15	MISC:TMSPIN[1]	MISC:TMSPIN[0]
16	BSCAN:TDO_ENABLE[0]	BSCAN:TDO_ENABLE[1]
17	~BSCAN:USERID[31]	~BSCAN:USERID[30]
18	~BSCAN:USERID[28]	~BSCAN:USERID[29]
19	~BSCAN:USERID[27]	~BSCAN:USERID[26]
20	~BSCAN:USERID[24]	~BSCAN:USERID[25]
21	~BSCAN:USERID[23]	~BSCAN:USERID[22]
22	~BSCAN:USERID[21]	~BSCAN:USERID[20]
23	~BSCAN:USERID[19]	~BSCAN:USERID[18]
24	~BSCAN:USERID[17]	~BSCAN:USERID[16]
25	~BSCAN:USERID[15]	~BSCAN:USERID[14]
26	~BSCAN:USERID[13]	~BSCAN:USERID[12]
27	~BSCAN:USERID[11]	~BSCAN:USERID[10]
28	~BSCAN:USERID[9]	~BSCAN:USERID[8]
29	~BSCAN:USERID[7]	~BSCAN:USERID[6]
30	~BSCAN:USERID[5]	~BSCAN:USERID[4]
31	~BSCAN:USERID[3]	~BSCAN:USERID[2]
32	~BSCAN:USERID[1]	~BSCAN:USERID[0]
33	-	BANK:LVDSBIAS_0[10]
34	-	BANK:LVDSBIAS_0[9]
35	-	BANK:LVDSBIAS_0[8]
36	-	BANK:LVDSBIAS_0[7]
37	-	BANK:LVDSBIAS_0[6]
38	-	BANK:LVDSBIAS_0[5]
39	-	BANK:LVDSBIAS_1[10]
40	-	BANK:LVDSBIAS_1[9]
41	-	BANK:LVDSBIAS_1[8]
42	-	BANK:LVDSBIAS_1[7]
43	-	BANK:LVDSBIAS_1[6]
44	-	BANK:LVDSBIAS_1[5]
45	-	BANK:LVDSBIAS_0[4]
46	-	BANK:LVDSBIAS_0[3]
47	-	BANK:LVDSBIAS_0[2]
48	-	BANK:LVDSBIAS_0[1]
49	-	BANK:LVDSBIAS_1[4]
50	-	BANK:LVDSBIAS_1[3]
51	-	BANK:LVDSBIAS_1[2]

MISC:TCKPIN	[0, 1, 14]	[0, 0, 14]
MISC:TDOPIN	[0, 0, 13]	[0, 1, 13]
MISC:TMSPIN	[0, 0, 15]	[0, 1, 15]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

BSCAN:TDO_ENABLE	[0, 1, 16]	[0, 0, 16]
Non-inverted	[1]	[0]

BANK:LVDSBIAS_0	[0, 1, 33]	[0, 1, 34]	[0, 1, 35]	[0, 1, 36]	[0, 1, 37]	[0, 1, 38]	[0, 1, 45]	[0, 1, 46]	[0, 1, 47]	[0, 1, 48]	[0, 1, 10]
BANK:LVDSBIAS_1	[0, 1, 39]	[0, 1, 40]	[0, 1, 41]	[0, 1, 42]	[0, 1, 43]	[0, 1, 44]	[0, 1, 49]	[0, 1, 50]	[0, 1, 51]	[0, 1, 9]	[0, 1, 11]
Non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

BSCAN:USERID	[0, 0, 17]	[0, 1, 17]	[0, 1, 18]	[0, 0, 18]	[0, 0, 19]	[0, 1, 19]	[0, 1, 20]	[0, 0, 20]	[0, 0, 21]	[0, 1, 21]	[0, 0, 22]	[0, 1, 22]	[0, 0, 23]	[0, 1, 23]	[0, 0, 24]	[0, 1, 24]	[0, 0, 25]	[0, 1, 25]	[0, 0, 26]	[0, 1, 26]	[0, 0, 27]	[0, 1, 27]	[0, 0, 28]	[0, 1, 28]	[0, 0, 29]	[0, 1, 29]	[0, 0, 30]	[0, 1, 30]	[0, 0, 31]	[0, 1, 31]	[0, 0, 32]	[0, 1, 32]
Inverted	~[31]	~[30]	~[29]	~[28]	~[27]	~[26]	~[25]	~[24]	~[23]	~[22]	~[21]	~[20]	~[19]	~[18]	~[17]	~[16]	~[15]	~[14]	~[13]	~[12]	~[11]	~[10]	~[9]	~[8]	~[7]	~[6]	~[5]	~[4]	~[3]	~[2]	~[1]	~[0]

UR.S3A

This tile is used on Spartan 3A.

UR.S3A bittile 0
Row	Column
	0	1
0	-	-
1	-	-
2	-	-
3	-	-
4	-	-
5	-	-
6	-	-
7	MISC:TDOPIN[0]	MISC:TDOPIN[1]
8	-	-
9	-	-
10	-	-
11	-	-
12	-	-
13	-	-
14	-	-
15	-	-
16	-	-
17	-	-
18	-	-
19	-	-
20	-	-
21	-	-
22	-	-
23	-	-
24	-	-
25	-	-
26	-	-
27	-	-
28	-	-
29	-	-
30	-	-
31	-	-
32	-	-
33	-	-
34	-	-
35	-	-
36	-	-
37	-	-
38	-	-
39	-	-
40	-	-
41	-	-
42	-	-
43	-	-
44	MISC:TCKPIN[0]	MISC:TCKPIN[1]
45	MISC:MISO2PIN[0]	MISC:MISO2PIN[1]
46	MISC:CSO2PIN[1]	MISC:CSO2PIN[0]
47	~BSCAN:USERID[31]	~BSCAN:USERID[30]
48	~BSCAN:USERID[29]	~BSCAN:USERID[28]
49	~BSCAN:USERID[27]	~BSCAN:USERID[26]
50	~BSCAN:USERID[25]	~BSCAN:USERID[24]
51	~BSCAN:USERID[23]	~BSCAN:USERID[22]
52	~BSCAN:USERID[21]	~BSCAN:USERID[20]
53	~BSCAN:USERID[19]	~BSCAN:USERID[18]
54	~BSCAN:USERID[17]	~BSCAN:USERID[16]
55	~BSCAN:USERID[15]	~BSCAN:USERID[14]
56	~BSCAN:USERID[13]	~BSCAN:USERID[12]
57	~BSCAN:USERID[11]	~BSCAN:USERID[10]
58	~BSCAN:USERID[9]	~BSCAN:USERID[8]
59	~BSCAN:USERID[7]	~BSCAN:USERID[6]
60	~BSCAN:USERID[5]	~BSCAN:USERID[4]
61	~BSCAN:USERID[3]	~BSCAN:USERID[2]
62	~BSCAN:USERID[1]	~BSCAN:USERID[0]
63	BSCAN:TDO_ENABLE[0]	BSCAN:TDO_ENABLE[1]

MISC:CSO2PIN	[0, 0, 46]	[0, 1, 46]
MISC:MISO2PIN	[0, 1, 45]	[0, 0, 45]
MISC:TCKPIN	[0, 1, 44]	[0, 0, 44]
MISC:TDOPIN	[0, 1, 7]	[0, 0, 7]
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

BSCAN:TDO_ENABLE	[0, 1, 63]	[0, 0, 63]
Non-inverted	[1]	[0]

BSCAN:USERID	[0, 0, 47]	[0, 1, 47]	[0, 0, 48]	[0, 1, 48]	[0, 0, 49]	[0, 1, 49]	[0, 0, 50]	[0, 1, 50]	[0, 0, 51]	[0, 1, 51]	[0, 0, 52]	[0, 1, 52]	[0, 0, 53]	[0, 1, 53]	[0, 0, 54]	[0, 1, 54]	[0, 0, 55]	[0, 1, 55]	[0, 0, 56]	[0, 1, 56]	[0, 0, 57]	[0, 1, 57]	[0, 0, 58]	[0, 1, 58]	[0, 0, 59]	[0, 1, 59]	[0, 0, 60]	[0, 1, 60]	[0, 0, 61]	[0, 1, 61]	[0, 0, 62]	[0, 1, 62]
Inverted	~[31]	~[30]	~[29]	~[28]	~[27]	~[26]	~[25]	~[24]	~[23]	~[22]	~[21]	~[20]	~[19]	~[18]	~[17]	~[16]	~[15]	~[14]	~[13]	~[12]	~[11]	~[10]	~[9]	~[8]	~[7]	~[6]	~[5]	~[4]	~[3]	~[2]	~[1]	~[0]

I/O data — Spartan 3

Name	IOSTD:S3:LVDSBIAS
	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
LDT_25	0	0	0	0	0	0	0	0	0	0	1	0	0
LVDSEXT_25	1	1	0	0	0	0	0	0	1	0	1	0	1
LVDSEXT_25_DCI	1	1	0	0	0	0	0	0	1	0	0	0	1
LVDS_25	1	1	0	0	0	0	0	0	1	0	1	0	1
LVDS_25_DCI	1	1	0	0	0	0	0	0	1	0	0	0	1
OFF	0	0	0	0	0	0	0	0	0	0	0	0	0
RSDS_25	1	1	0	0	0	0	0	0	1	0	1	0	1
ULVDS_25	0	0	0	0	0	0	0	0	0	0	1	0	0

Name	IOSTD:S3:PMASK_TERM_SPLIT				IOSTD:S3:NMASK_TERM_SPLIT
	[3]	[2]	[1]	[0]	[3]	[2]	[1]	[0]
HSTL_II_DCI_18	1	0	0	1	0	1	0	0
HSTL_I_DCI	0	0	0	0	0	0	0	0
HSTL_I_DCI_18	0	0	0	0	0	0	0	0
LVDSEXT_25_DCI	0	0	0	0	0	0	0	0
LVDS_25_DCI	0	0	0	0	0	0	0	0
OFF	0	0	0	0	0	0	0	0
SSTL18_I_DCI	0	0	0	0	0	0	0	0
SSTL2_II_DCI	0	0	0	1	0	1	0	1
SSTL2_I_DCI	0	0	0	0	0	0	0	0

Name	IOSTD:S3:PMASK_TERM_VCC
	[3]	[2]	[1]	[0]
GTLP_DCI	0	0	0	0
GTL_DCI	0	0	0	0
HSTL_III_DCI	0	0	0	0
HSTL_III_DCI_18	0	0	0	0
OFF	0	0	0	0

I/O data — Spartan 3E

Name	IOSTD:S3E:LVDSBIAS
	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
LVDS_25	1	1	0	0	0	1	1	0	1	0	1
MINI_LVDS_25	0	1	1	1	1	0	0	1	1	0	1
OFF	0	0	0	0	0	0	1	0	1	0	0
RSDS_25	0	0	0	1	1	0	1	0	1	0	1

I/O data — Spartan 3A

Name	IOSTD:S3A.TB:LVDSBIAS
	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
LVDS_25	1	1	0	0	0	1	1	0	0	0	1	0
LVDS_33	1	1	0	0	0	1	1	0	0	0	1	0
MINI_LVDS_25	0	1	0	0	0	1	0	0	0	0	1	0
MINI_LVDS_33	0	1	0	0	0	1	0	0	0	0	1	0
OFF	0	0	0	0	0	0	0	0	0	0	0	0
PPDS_25	0	0	1	0	0	1	0	0	0	1	1	1
PPDS_33	0	0	1	0	0	1	0	0	0	1	1	1
RSDS_25	0	0	0	1	1	0	1	0	0	0	1	0
RSDS_33	0	0	0	1	1	0	1	0	0	0	1	0
TMDS_33	1	0	1	0	0	1	0	0	1	0	1	0