Project Combine
Contents:
Xilinx FPGAs
XC2000
XC3000
XC3000A
XC4000
XC4000A
XC4000H
XC4000E
XC4000EX
XC4000XLA
XC4000XV
Spartan XL
XC5200
Virtex
Virtex 2
Spartan 3
Introduction
Device geometry
General interconnect
Configurable Logic Block
Block RAM
DSP
Clock interconnect
Input / Output
Digital Clock Managers — Spartan 3
Digital Clock Managers — Spartan 3E, 3A
Corners
Hard PCI logic
Configuration registers — Spartan 3, Spartan 3E
Configuration registers — Spartan 3A and 3A DSP
FPGAcore
Spartan 6
Virtex 4
Virtex 5
Virtex 6
Virtex 7
SiliconBlue FPGAs
Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Xilinx XPLA3 CPLDs
Xilinx Coolrunner II CPLDs
Digilent Adept Programmers
Project Combine
Xilinx FPGAs
Spartan 3
Hard PCI logic
View page source
Hard PCI logic
Todo
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