Input / Output

Todo

document

I/O interface

Todo

document

IOI.S3

IOI.S3 bittile 0
RowColumn
0123
0 ---IOI0:READBACK_I
1 ---IOI0:IFF_DELAY_ENABLE
2 ----
3 ~IOI0:TFF1_SRVAL~IOI0:OFF1_SRVAL~IOI0:IFF1_SRVALIOI0:IFF_TSBYPASS_ENABLE
4 ---IOI0:TSBYPASS_MUX
5 ~IOI0:TFF2_SRVAL~IOI0:OFF2_SRVAL--
6 ----
7 --~IOI0:IFF1_INITIOI0:I_TSBYPASS_ENABLE
8 ~IOI0:TFF_INIT~IOI0:OFF_INITIOI0:IFF_SR_SYNC-
9 IOI0:TFF_REV_ENABLEIOI0:OFF_REV_ENABLEIOI0:IFF_REV_ENABLE-
10 IOI0:TFF_SR_ENABLEIOI0:OFF_SR_ENABLEIOI0:IFF_SR_ENABLEIOI0:I_DELAY_ENABLE
11 IOI0:INV.T2IOI0:INV.O2IOI0:IFF_LATCH~IOI0:INV.REV
12 IOI0:INV.T1IOI0:INV.O1~IOI0:IFF2_INIT~IOI0:INV.ICLK2
13 IOI0:TFF_SR_SYNCIOI0:OFF_SR_SYNC-~IOI0:INV.ICLK1
14 IOI0:TMUX[1]IOI0:OMUX[1]-~IOI0:INV.ICE
15 IOI0:TMUX[3]IOI0:OMUX[3]-~IOI0:INV.OTCLK2
16 IOI0:TMUX[0]IOI0:OMUX[0]~IOI0:IFF2_SRVAL~IOI0:INV.OTCLK1
17 IOI0:TFF1_LATCHIOI0:OFF1_LATCH-~IOI0:INV.TCE
18 IOI0:TFF2_LATCHIOI0:OFF2_LATCH--
19 IOI0:TMUX[2]IOI0:OMUX[2]--
20 IOI1:TMUX[2]IOI1:OMUX[2]--
21 IOI1:TFF2_LATCHIOI1:OFF2_LATCH--
22 IOI1:TFF1_LATCHIOI1:OFF1_LATCH-~IOI1:INV.TCE
23 IOI1:TMUX[0]IOI1:OMUX[0]~IOI1:IFF2_SRVAL~IOI1:INV.OTCLK1
24 IOI1:TMUX[3]IOI1:OMUX[3]-~IOI1:INV.OTCLK2
25 IOI1:TMUX[1]IOI1:OMUX[1]-~IOI1:INV.ICE
26 IOI1:TFF_SR_SYNCIOI1:OFF_SR_SYNC-~IOI1:INV.ICLK1
27 IOI1:INV.T1IOI1:INV.O1~IOI1:IFF2_INIT~IOI1:INV.ICLK2
28 IOI1:INV.T2IOI1:INV.O2IOI1:IFF_LATCH~IOI1:INV.REV
29 IOI1:TFF_SR_ENABLEIOI1:OFF_SR_ENABLEIOI1:IFF_SR_ENABLEIOI1:I_DELAY_ENABLE
30 IOI1:TFF_REV_ENABLEIOI1:OFF_REV_ENABLEIOI1:IFF_REV_ENABLE-
31 ~IOI1:TFF_INIT~IOI1:OFF_INITIOI1:IFF_SR_SYNC-
32 --~IOI1:IFF1_INITIOI1:I_TSBYPASS_ENABLE
33 ----
34 ~IOI1:TFF2_SRVAL~IOI1:OFF2_SRVAL--
35 ---IOI1:TSBYPASS_MUX
36 ~IOI1:TFF1_SRVAL~IOI1:OFF1_SRVAL~IOI1:IFF1_SRVALIOI1:IFF_TSBYPASS_ENABLE
37 ----
38 ---IOI1:IFF_DELAY_ENABLE
39 ---IOI1:READBACK_I
40 ---IOI2:READBACK_I
41 ---IOI2:IFF_DELAY_ENABLE
42 ----
43 ~IOI2:TFF1_SRVAL~IOI2:OFF1_SRVAL~IOI2:IFF1_SRVALIOI2:IFF_TSBYPASS_ENABLE
44 ---IOI2:TSBYPASS_MUX
45 ~IOI2:TFF2_SRVAL~IOI2:OFF2_SRVAL--
46 ----
47 --~IOI2:IFF1_INITIOI2:I_TSBYPASS_ENABLE
48 ~IOI2:TFF_INIT~IOI2:OFF_INITIOI2:IFF_SR_SYNC-
49 IOI2:TFF_REV_ENABLEIOI2:OFF_REV_ENABLEIOI2:IFF_REV_ENABLE-
50 IOI2:TFF_SR_ENABLEIOI2:OFF_SR_ENABLEIOI2:IFF_SR_ENABLEIOI2:I_DELAY_ENABLE
51 IOI2:INV.T2IOI2:INV.O2IOI2:IFF_LATCH~IOI2:INV.REV
52 IOI2:INV.T1IOI2:INV.O1~IOI2:IFF2_INIT~IOI2:INV.ICLK2
53 IOI2:TFF_SR_SYNCIOI2:OFF_SR_SYNC-~IOI2:INV.ICLK1
54 IOI2:TMUX[1]IOI2:OMUX[1]-~IOI2:INV.ICE
55 IOI2:TMUX[3]IOI2:OMUX[3]-~IOI2:INV.OTCLK2
56 IOI2:TMUX[0]IOI2:OMUX[0]~IOI2:IFF2_SRVAL~IOI2:INV.OTCLK1
57 IOI2:TFF1_LATCHIOI2:OFF1_LATCH-~IOI2:INV.TCE
58 IOI2:TFF2_LATCHIOI2:OFF2_LATCH--
59 IOI2:TMUX[2]IOI2:OMUX[2]--
IOI0:IFF1_INIT[0, 2, 7]
IOI0:IFF1_SRVAL[0, 2, 3]
IOI0:IFF2_INIT[0, 2, 12]
IOI0:IFF2_SRVAL[0, 2, 16]
IOI0:INV.ICE[0, 3, 14]
IOI0:INV.ICLK1[0, 3, 13]
IOI0:INV.ICLK2[0, 3, 12]
IOI0:INV.OTCLK1[0, 3, 16]
IOI0:INV.OTCLK2[0, 3, 15]
IOI0:INV.REV[0, 3, 11]
IOI0:INV.TCE[0, 3, 17]
IOI0:OFF1_SRVAL[0, 1, 3]
IOI0:OFF2_SRVAL[0, 1, 5]
IOI0:OFF_INIT[0, 1, 8]
IOI0:TFF1_SRVAL[0, 0, 3]
IOI0:TFF2_SRVAL[0, 0, 5]
IOI0:TFF_INIT[0, 0, 8]
IOI1:IFF1_INIT[0, 2, 32]
IOI1:IFF1_SRVAL[0, 2, 36]
IOI1:IFF2_INIT[0, 2, 27]
IOI1:IFF2_SRVAL[0, 2, 23]
IOI1:INV.ICE[0, 3, 25]
IOI1:INV.ICLK1[0, 3, 26]
IOI1:INV.ICLK2[0, 3, 27]
IOI1:INV.OTCLK1[0, 3, 23]
IOI1:INV.OTCLK2[0, 3, 24]
IOI1:INV.REV[0, 3, 28]
IOI1:INV.TCE[0, 3, 22]
IOI1:OFF1_SRVAL[0, 1, 36]
IOI1:OFF2_SRVAL[0, 1, 34]
IOI1:OFF_INIT[0, 1, 31]
IOI1:TFF1_SRVAL[0, 0, 36]
IOI1:TFF2_SRVAL[0, 0, 34]
IOI1:TFF_INIT[0, 0, 31]
IOI2:IFF1_INIT[0, 2, 47]
IOI2:IFF1_SRVAL[0, 2, 43]
IOI2:IFF2_INIT[0, 2, 52]
IOI2:IFF2_SRVAL[0, 2, 56]
IOI2:INV.ICE[0, 3, 54]
IOI2:INV.ICLK1[0, 3, 53]
IOI2:INV.ICLK2[0, 3, 52]
IOI2:INV.OTCLK1[0, 3, 56]
IOI2:INV.OTCLK2[0, 3, 55]
IOI2:INV.REV[0, 3, 51]
IOI2:INV.TCE[0, 3, 57]
IOI2:OFF1_SRVAL[0, 1, 43]
IOI2:OFF2_SRVAL[0, 1, 45]
IOI2:OFF_INIT[0, 1, 48]
IOI2:TFF1_SRVAL[0, 0, 43]
IOI2:TFF2_SRVAL[0, 0, 45]
IOI2:TFF_INIT[0, 0, 48]
Inverted~[0]
IOI0:IFF_DELAY_ENABLE[0, 3, 1]
IOI0:IFF_LATCH[0, 2, 11]
IOI0:IFF_REV_ENABLE[0, 2, 9]
IOI0:IFF_SR_ENABLE[0, 2, 10]
IOI0:IFF_SR_SYNC[0, 2, 8]
IOI0:IFF_TSBYPASS_ENABLE[0, 3, 3]
IOI0:INV.O1[0, 1, 12]
IOI0:INV.O2[0, 1, 11]
IOI0:INV.T1[0, 0, 12]
IOI0:INV.T2[0, 0, 11]
IOI0:I_DELAY_ENABLE[0, 3, 10]
IOI0:I_TSBYPASS_ENABLE[0, 3, 7]
IOI0:OFF1_LATCH[0, 1, 17]
IOI0:OFF2_LATCH[0, 1, 18]
IOI0:OFF_REV_ENABLE[0, 1, 9]
IOI0:OFF_SR_ENABLE[0, 1, 10]
IOI0:OFF_SR_SYNC[0, 1, 13]
IOI0:READBACK_I[0, 3, 0]
IOI0:TFF1_LATCH[0, 0, 17]
IOI0:TFF2_LATCH[0, 0, 18]
IOI0:TFF_REV_ENABLE[0, 0, 9]
IOI0:TFF_SR_ENABLE[0, 0, 10]
IOI0:TFF_SR_SYNC[0, 0, 13]
IOI1:IFF_DELAY_ENABLE[0, 3, 38]
IOI1:IFF_LATCH[0, 2, 28]
IOI1:IFF_REV_ENABLE[0, 2, 30]
IOI1:IFF_SR_ENABLE[0, 2, 29]
IOI1:IFF_SR_SYNC[0, 2, 31]
IOI1:IFF_TSBYPASS_ENABLE[0, 3, 36]
IOI1:INV.O1[0, 1, 27]
IOI1:INV.O2[0, 1, 28]
IOI1:INV.T1[0, 0, 27]
IOI1:INV.T2[0, 0, 28]
IOI1:I_DELAY_ENABLE[0, 3, 29]
IOI1:I_TSBYPASS_ENABLE[0, 3, 32]
IOI1:OFF1_LATCH[0, 1, 22]
IOI1:OFF2_LATCH[0, 1, 21]
IOI1:OFF_REV_ENABLE[0, 1, 30]
IOI1:OFF_SR_ENABLE[0, 1, 29]
IOI1:OFF_SR_SYNC[0, 1, 26]
IOI1:READBACK_I[0, 3, 39]
IOI1:TFF1_LATCH[0, 0, 22]
IOI1:TFF2_LATCH[0, 0, 21]
IOI1:TFF_REV_ENABLE[0, 0, 30]
IOI1:TFF_SR_ENABLE[0, 0, 29]
IOI1:TFF_SR_SYNC[0, 0, 26]
IOI2:IFF_DELAY_ENABLE[0, 3, 41]
IOI2:IFF_LATCH[0, 2, 51]
IOI2:IFF_REV_ENABLE[0, 2, 49]
IOI2:IFF_SR_ENABLE[0, 2, 50]
IOI2:IFF_SR_SYNC[0, 2, 48]
IOI2:IFF_TSBYPASS_ENABLE[0, 3, 43]
IOI2:INV.O1[0, 1, 52]
IOI2:INV.O2[0, 1, 51]
IOI2:INV.T1[0, 0, 52]
IOI2:INV.T2[0, 0, 51]
IOI2:I_DELAY_ENABLE[0, 3, 50]
IOI2:I_TSBYPASS_ENABLE[0, 3, 47]
IOI2:OFF1_LATCH[0, 1, 57]
IOI2:OFF2_LATCH[0, 1, 58]
IOI2:OFF_REV_ENABLE[0, 1, 49]
IOI2:OFF_SR_ENABLE[0, 1, 50]
IOI2:OFF_SR_SYNC[0, 1, 53]
IOI2:READBACK_I[0, 3, 40]
IOI2:TFF1_LATCH[0, 0, 57]
IOI2:TFF2_LATCH[0, 0, 58]
IOI2:TFF_REV_ENABLE[0, 0, 49]
IOI2:TFF_SR_ENABLE[0, 0, 50]
IOI2:TFF_SR_SYNC[0, 0, 53]
Non-inverted[0]
IOI0:TMUX[0, 0, 15][0, 0, 19][0, 0, 14][0, 0, 16]
IOI1:TMUX[0, 0, 24][0, 0, 20][0, 0, 25][0, 0, 23]
IOI2:TMUX[0, 0, 55][0, 0, 59][0, 0, 54][0, 0, 56]
NONE0000
T10001
T20010
TFF10100
TFF21000
TFFDDR1100
IOI0:OMUX[0, 1, 15][0, 1, 19][0, 1, 14][0, 1, 16]
IOI1:OMUX[0, 1, 24][0, 1, 20][0, 1, 25][0, 1, 23]
IOI2:OMUX[0, 1, 55][0, 1, 59][0, 1, 54][0, 1, 56]
NONE0000
O10001
O20010
OFF10100
OFF21000
OFFDDR1100
IOI0:TSBYPASS_MUX[0, 3, 4]
IOI1:TSBYPASS_MUX[0, 3, 35]
IOI2:TSBYPASS_MUX[0, 3, 44]
TMUX0
GND1

IOI.S3E

IOI.S3E bittile 0
RowColumn
0123
0 IOI0:MISR_CLOCK[0]IOI0:PCICE_MUX[0]IOI0:PCICE_MUX[1]IOI0:READBACK_I
1 IOI0:MISR_CLOCK[1]--IOI0:IFF_DELAY_ENABLE
2 IOI1:O2_DDRMUX--IOI1:IDDRIN_MUX[1]
3 ~IOI0:TFF1_SRVAL~IOI0:OFF1_SRVAL~IOI0:IFF1_SRVALIOI0:IFF_TSBYPASS_ENABLE
4 -IOI1:O1_DDRMUX-IOI0:TSBYPASS_MUX
5 ~IOI0:TFF2_SRVAL~IOI0:OFF2_SRVAL--
6 IOI0:MISR_ENABLE---
7 IOI0:MISR_RESET-~IOI0:IFF1_INITIOI0:I_TSBYPASS_ENABLE
8 ~IOI0:TFF_INIT~IOI0:OFF_INITIOI0:IFF_SR_SYNCIOI0:IDDRIN_MUX[0]
9 IOI0:TFF_REV_ENABLEIOI0:OFF_REV_ENABLEIOI0:IFF_REV_ENABLE-
10 IOI0:TFF_SR_ENABLEIOI0:OFF_SR_ENABLEIOI0:IFF_SR_ENABLEIOI0:I_DELAY_ENABLE
11 IOI0:INV.T2IOI0:INV.O2IOI0:IFF_LATCH~IOI0:INV.REV
12 IOI0:INV.T1IOI0:INV.O1~IOI0:IFF2_INIT~IOI0:INV.ICLK2
13 IOI0:TFF_SR_SYNCIOI0:OFF_SR_SYNC-~IOI0:INV.ICLK1
14 IOI0:TMUX[1]IOI0:OMUX[1]-~IOI0:INV.ICE
15 IOI0:TMUX[3]IOI0:OMUX[3]-~IOI0:INV.OTCLK2
16 IOI0:TMUX[0]IOI0:OMUX[0]~IOI0:IFF2_SRVAL~IOI0:INV.OTCLK1
17 IOI0:TFF1_LATCHIOI0:OFF1_LATCH-~IOI0:INV.TCE
18 IOI0:TFF2_LATCHIOI0:OFF2_LATCH-IOI1:IDDRIN_MUX[2]
19 IOI0:TMUX[2]IOI0:OMUX[2]--
20 IOI1:TMUX[2]IOI1:OMUX[2]--
21 IOI1:TFF2_LATCHIOI1:OFF2_LATCH-IOI0:IDDRIN_MUX[2]
22 IOI1:TFF1_LATCHIOI1:OFF1_LATCH-~IOI1:INV.TCE
23 IOI1:TMUX[0]IOI1:OMUX[0]~IOI1:IFF2_SRVAL~IOI1:INV.OTCLK1
24 IOI1:TMUX[3]IOI1:OMUX[3]-~IOI1:INV.OTCLK2
25 IOI1:TMUX[1]IOI1:OMUX[1]-~IOI1:INV.ICE
26 IOI1:TFF_SR_SYNCIOI1:OFF_SR_SYNC-~IOI1:INV.ICLK1
27 IOI1:INV.T1IOI1:INV.O1~IOI1:IFF2_INIT~IOI1:INV.ICLK2
28 IOI1:INV.T2IOI1:INV.O2IOI1:IFF_LATCH~IOI1:INV.REV
29 IOI1:TFF_SR_ENABLEIOI1:OFF_SR_ENABLEIOI1:IFF_SR_ENABLEIOI1:I_DELAY_ENABLE
30 IOI1:TFF_REV_ENABLEIOI1:OFF_REV_ENABLEIOI1:IFF_REV_ENABLEIOI1:IDDRIN_MUX[0]
31 ~IOI1:TFF_INIT~IOI1:OFF_INITIOI1:IFF_SR_SYNC-
32 IOI1:MISR_RESET-~IOI1:IFF1_INITIOI1:I_TSBYPASS_ENABLE
33 IOI1:MISR_ENABLE---
34 ~IOI1:TFF2_SRVAL~IOI1:OFF2_SRVAL--
35 -IOI0:O1_DDRMUX-IOI1:TSBYPASS_MUX
36 ~IOI1:TFF1_SRVAL~IOI1:OFF1_SRVAL~IOI1:IFF1_SRVALIOI1:IFF_TSBYPASS_ENABLE
37 IOI0:O2_DDRMUX--IOI0:IDDRIN_MUX[1]
38 IOI1:MISR_CLOCK[1]--IOI1:IFF_DELAY_ENABLE
39 IOI1:MISR_CLOCK[0]IOI1:PCICE_MUX[0]IOI1:PCICE_MUX[1]IOI1:READBACK_I
40 IOI2:MISR_CLOCK[0]IOI2:PCICE_MUX[0]IOI2:PCICE_MUX[1]IOI2:READBACK_I
41 IOI2:MISR_CLOCK[1]--IOI2:IFF_DELAY_ENABLE
42 ---IOI2:IDDRIN_MUX[1]
43 ~IOI2:TFF1_SRVAL~IOI2:OFF1_SRVAL~IOI2:IFF1_SRVALIOI2:IFF_TSBYPASS_ENABLE
44 ---IOI2:TSBYPASS_MUX
45 ~IOI2:TFF2_SRVAL~IOI2:OFF2_SRVAL--
46 IOI2:MISR_ENABLE---
47 IOI2:MISR_RESET-~IOI2:IFF1_INITIOI2:I_TSBYPASS_ENABLE
48 ~IOI2:TFF_INIT~IOI2:OFF_INITIOI2:IFF_SR_SYNCIOI2:IDDRIN_MUX[0]
49 IOI2:TFF_REV_ENABLEIOI2:OFF_REV_ENABLEIOI2:IFF_REV_ENABLE-
50 IOI2:TFF_SR_ENABLEIOI2:OFF_SR_ENABLEIOI2:IFF_SR_ENABLEIOI2:I_DELAY_ENABLE
51 IOI2:INV.T2IOI2:INV.O2IOI2:IFF_LATCH~IOI2:INV.REV
52 IOI2:INV.T1IOI2:INV.O1~IOI2:IFF2_INIT~IOI2:INV.ICLK2
53 IOI2:TFF_SR_SYNCIOI2:OFF_SR_SYNC-~IOI2:INV.ICLK1
54 IOI2:TMUX[1]IOI2:OMUX[1]-~IOI2:INV.ICE
55 IOI2:TMUX[3]IOI2:OMUX[3]-~IOI2:INV.OTCLK2
56 IOI2:TMUX[0]IOI2:OMUX[0]~IOI2:IFF2_SRVAL~IOI2:INV.OTCLK1
57 IOI2:TFF1_LATCHIOI2:OFF1_LATCH-~IOI2:INV.TCE
58 IOI2:TFF2_LATCHIOI2:OFF2_LATCH-IOI2:IDDRIN_MUX[2]
59 IOI2:TMUX[2]IOI2:OMUX[2]--
IOI0:MISR_CLOCK[0, 0, 1][0, 0, 0]
IOI1:MISR_CLOCK[0, 0, 38][0, 0, 39]
IOI2:MISR_CLOCK[0, 0, 41][0, 0, 40]
NONE00
OTCLK101
OTCLK210
IOI0:O2_DDRMUX[0, 0, 37]
IOI1:O2_DDRMUX[0, 0, 2]
O20
ODDRIN21
IOI0:IFF1_INIT[0, 2, 7]
IOI0:IFF1_SRVAL[0, 2, 3]
IOI0:IFF2_INIT[0, 2, 12]
IOI0:IFF2_SRVAL[0, 2, 16]
IOI0:INV.ICE[0, 3, 14]
IOI0:INV.ICLK1[0, 3, 13]
IOI0:INV.ICLK2[0, 3, 12]
IOI0:INV.OTCLK1[0, 3, 16]
IOI0:INV.OTCLK2[0, 3, 15]
IOI0:INV.REV[0, 3, 11]
IOI0:INV.TCE[0, 3, 17]
IOI0:OFF1_SRVAL[0, 1, 3]
IOI0:OFF2_SRVAL[0, 1, 5]
IOI0:OFF_INIT[0, 1, 8]
IOI0:TFF1_SRVAL[0, 0, 3]
IOI0:TFF2_SRVAL[0, 0, 5]
IOI0:TFF_INIT[0, 0, 8]
IOI1:IFF1_INIT[0, 2, 32]
IOI1:IFF1_SRVAL[0, 2, 36]
IOI1:IFF2_INIT[0, 2, 27]
IOI1:IFF2_SRVAL[0, 2, 23]
IOI1:INV.ICE[0, 3, 25]
IOI1:INV.ICLK1[0, 3, 26]
IOI1:INV.ICLK2[0, 3, 27]
IOI1:INV.OTCLK1[0, 3, 23]
IOI1:INV.OTCLK2[0, 3, 24]
IOI1:INV.REV[0, 3, 28]
IOI1:INV.TCE[0, 3, 22]
IOI1:OFF1_SRVAL[0, 1, 36]
IOI1:OFF2_SRVAL[0, 1, 34]
IOI1:OFF_INIT[0, 1, 31]
IOI1:TFF1_SRVAL[0, 0, 36]
IOI1:TFF2_SRVAL[0, 0, 34]
IOI1:TFF_INIT[0, 0, 31]
IOI2:IFF1_INIT[0, 2, 47]
IOI2:IFF1_SRVAL[0, 2, 43]
IOI2:IFF2_INIT[0, 2, 52]
IOI2:IFF2_SRVAL[0, 2, 56]
IOI2:INV.ICE[0, 3, 54]
IOI2:INV.ICLK1[0, 3, 53]
IOI2:INV.ICLK2[0, 3, 52]
IOI2:INV.OTCLK1[0, 3, 56]
IOI2:INV.OTCLK2[0, 3, 55]
IOI2:INV.REV[0, 3, 51]
IOI2:INV.TCE[0, 3, 57]
IOI2:OFF1_SRVAL[0, 1, 43]
IOI2:OFF2_SRVAL[0, 1, 45]
IOI2:OFF_INIT[0, 1, 48]
IOI2:TFF1_SRVAL[0, 0, 43]
IOI2:TFF2_SRVAL[0, 0, 45]
IOI2:TFF_INIT[0, 0, 48]
Inverted~[0]
IOI0:IFF_DELAY_ENABLE[0, 3, 1]
IOI0:IFF_LATCH[0, 2, 11]
IOI0:IFF_REV_ENABLE[0, 2, 9]
IOI0:IFF_SR_ENABLE[0, 2, 10]
IOI0:IFF_SR_SYNC[0, 2, 8]
IOI0:IFF_TSBYPASS_ENABLE[0, 3, 3]
IOI0:INV.O1[0, 1, 12]
IOI0:INV.O2[0, 1, 11]
IOI0:INV.T1[0, 0, 12]
IOI0:INV.T2[0, 0, 11]
IOI0:I_DELAY_ENABLE[0, 3, 10]
IOI0:I_TSBYPASS_ENABLE[0, 3, 7]
IOI0:MISR_ENABLE[0, 0, 6]
IOI0:MISR_RESET[0, 0, 7]
IOI0:OFF1_LATCH[0, 1, 17]
IOI0:OFF2_LATCH[0, 1, 18]
IOI0:OFF_REV_ENABLE[0, 1, 9]
IOI0:OFF_SR_ENABLE[0, 1, 10]
IOI0:OFF_SR_SYNC[0, 1, 13]
IOI0:READBACK_I[0, 3, 0]
IOI0:TFF1_LATCH[0, 0, 17]
IOI0:TFF2_LATCH[0, 0, 18]
IOI0:TFF_REV_ENABLE[0, 0, 9]
IOI0:TFF_SR_ENABLE[0, 0, 10]
IOI0:TFF_SR_SYNC[0, 0, 13]
IOI1:IFF_DELAY_ENABLE[0, 3, 38]
IOI1:IFF_LATCH[0, 2, 28]
IOI1:IFF_REV_ENABLE[0, 2, 30]
IOI1:IFF_SR_ENABLE[0, 2, 29]
IOI1:IFF_SR_SYNC[0, 2, 31]
IOI1:IFF_TSBYPASS_ENABLE[0, 3, 36]
IOI1:INV.O1[0, 1, 27]
IOI1:INV.O2[0, 1, 28]
IOI1:INV.T1[0, 0, 27]
IOI1:INV.T2[0, 0, 28]
IOI1:I_DELAY_ENABLE[0, 3, 29]
IOI1:I_TSBYPASS_ENABLE[0, 3, 32]
IOI1:MISR_ENABLE[0, 0, 33]
IOI1:MISR_RESET[0, 0, 32]
IOI1:OFF1_LATCH[0, 1, 22]
IOI1:OFF2_LATCH[0, 1, 21]
IOI1:OFF_REV_ENABLE[0, 1, 30]
IOI1:OFF_SR_ENABLE[0, 1, 29]
IOI1:OFF_SR_SYNC[0, 1, 26]
IOI1:READBACK_I[0, 3, 39]
IOI1:TFF1_LATCH[0, 0, 22]
IOI1:TFF2_LATCH[0, 0, 21]
IOI1:TFF_REV_ENABLE[0, 0, 30]
IOI1:TFF_SR_ENABLE[0, 0, 29]
IOI1:TFF_SR_SYNC[0, 0, 26]
IOI2:IFF_DELAY_ENABLE[0, 3, 41]
IOI2:IFF_LATCH[0, 2, 51]
IOI2:IFF_REV_ENABLE[0, 2, 49]
IOI2:IFF_SR_ENABLE[0, 2, 50]
IOI2:IFF_SR_SYNC[0, 2, 48]
IOI2:IFF_TSBYPASS_ENABLE[0, 3, 43]
IOI2:INV.O1[0, 1, 52]
IOI2:INV.O2[0, 1, 51]
IOI2:INV.T1[0, 0, 52]
IOI2:INV.T2[0, 0, 51]
IOI2:I_DELAY_ENABLE[0, 3, 50]
IOI2:I_TSBYPASS_ENABLE[0, 3, 47]
IOI2:MISR_ENABLE[0, 0, 46]
IOI2:MISR_RESET[0, 0, 47]
IOI2:OFF1_LATCH[0, 1, 57]
IOI2:OFF2_LATCH[0, 1, 58]
IOI2:OFF_REV_ENABLE[0, 1, 49]
IOI2:OFF_SR_ENABLE[0, 1, 50]
IOI2:OFF_SR_SYNC[0, 1, 53]
IOI2:READBACK_I[0, 3, 40]
IOI2:TFF1_LATCH[0, 0, 57]
IOI2:TFF2_LATCH[0, 0, 58]
IOI2:TFF_REV_ENABLE[0, 0, 49]
IOI2:TFF_SR_ENABLE[0, 0, 50]
IOI2:TFF_SR_SYNC[0, 0, 53]
Non-inverted[0]
IOI0:TMUX[0, 0, 15][0, 0, 19][0, 0, 14][0, 0, 16]
IOI1:TMUX[0, 0, 24][0, 0, 20][0, 0, 25][0, 0, 23]
IOI2:TMUX[0, 0, 55][0, 0, 59][0, 0, 54][0, 0, 56]
NONE0000
T10001
T20010
TFF10100
TFF21000
TFFDDR1100
IOI0:PCICE_MUX[0, 2, 0][0, 1, 0]
IOI1:PCICE_MUX[0, 2, 39][0, 1, 39]
IOI2:PCICE_MUX[0, 2, 40][0, 1, 40]
NONE00
OCE01
PCICE10
IOI0:O1_DDRMUX[0, 1, 35]
IOI1:O1_DDRMUX[0, 1, 4]
O10
ODDRIN11
IOI0:OMUX[0, 1, 15][0, 1, 19][0, 1, 14][0, 1, 16]
IOI1:OMUX[0, 1, 24][0, 1, 20][0, 1, 25][0, 1, 23]
IOI2:OMUX[0, 1, 55][0, 1, 59][0, 1, 54][0, 1, 56]
NONE0000
O10001
O20010
OFF10100
OFF21000
OFFDDR1100
IOI0:TSBYPASS_MUX[0, 3, 4]
IOI1:TSBYPASS_MUX[0, 3, 35]
IOI2:TSBYPASS_MUX[0, 3, 44]
TMUX0
GND1
IOI0:IDDRIN_MUX[0, 3, 21][0, 3, 37][0, 3, 8]
IOI1:IDDRIN_MUX[0, 3, 18][0, 3, 2][0, 3, 30]
IOI2:IDDRIN_MUX[0, 3, 58][0, 3, 42][0, 3, 48]
NONE000
IFFDMUX001
IDDRIN1010
IDDRIN2100

IOI.S3A.LR

IOI.S3A.LR bittile 0
RowColumn
0123
0 IOI0:MISR_CLOCK[0]IOI0:PCICE_MUX[0]IOI0:PCICE_MUX[1]IOI0:READBACK_I
1 IOI0:MISR_CLOCK[1]--IOI0:IFF_DELAY_ENABLE
2 IOI1:O2_DDRMUX--IOI1:IDDRIN_MUX[1]
3 ~IOI0:TFF1_SRVAL~IOI0:OFF1_SRVAL~IOI0:IFF1_SRVALIOI0:IFF_TSBYPASS_ENABLE
4 -IOI1:O1_DDRMUX-IOI0:TSBYPASS_MUX
5 ~IOI0:TFF2_SRVAL~IOI0:OFF2_SRVAL--
6 IOI0:MISR_ENABLE---
7 IOI0:MISR_RESET-~IOI0:IFF1_INITIOI0:I_TSBYPASS_ENABLE
8 ~IOI0:TFF_INIT~IOI0:OFF_INITIOI0:IFF_SR_SYNCIOI0:IDDRIN_MUX[0]
9 IOI0:TFF_REV_ENABLEIOI0:OFF_REV_ENABLEIOI0:IFF_REV_ENABLE-
10 IOI0:TFF_SR_ENABLEIOI0:OFF_SR_ENABLEIOI0:IFF_SR_ENABLEIOI0:I_DELAY_ENABLE
11 IOI0:INV.T2IOI0:INV.O2IOI0:IFF_LATCH~IOI0:INV.REV
12 IOI0:INV.T1IOI0:INV.O1~IOI0:IFF2_INIT~IOI0:INV.ICLK2
13 IOI0:TFF_SR_SYNCIOI0:OFF_SR_SYNC-~IOI0:INV.ICLK1
14 IOI0:TMUX[1]IOI0:OMUX[1]-~IOI0:INV.ICE
15 IOI0:TMUX[3]IOI0:OMUX[3]-~IOI0:INV.OTCLK2
16 IOI0:TMUX[0]IOI0:OMUX[0]~IOI0:IFF2_SRVAL~IOI0:INV.OTCLK1
17 IOI0:TFF1_LATCHIOI0:OFF1_LATCH-~IOI0:INV.TCE
18 IOI0:TFF2_LATCHIOI0:OFF2_LATCH-IOI1:IDDRIN_MUX[2]
19 IOI0:TMUX[2]IOI0:OMUX[2]--
20 IOI1:TMUX[2]IOI1:OMUX[2]--
21 IOI1:TFF2_LATCHIOI1:OFF2_LATCH-IOI0:IDDRIN_MUX[2]
22 IOI1:TFF1_LATCHIOI1:OFF1_LATCH-~IOI1:INV.TCE
23 IOI1:TMUX[0]IOI1:OMUX[0]~IOI1:IFF2_SRVAL~IOI1:INV.OTCLK1
24 IOI1:TMUX[3]IOI1:OMUX[3]-~IOI1:INV.OTCLK2
25 IOI1:TMUX[1]IOI1:OMUX[1]-~IOI1:INV.ICE
26 IOI1:TFF_SR_SYNCIOI1:OFF_SR_SYNC-~IOI1:INV.ICLK1
27 IOI1:INV.T1IOI1:INV.O1~IOI1:IFF2_INIT~IOI1:INV.ICLK2
28 IOI1:INV.T2IOI1:INV.O2IOI1:IFF_LATCH~IOI1:INV.REV
29 IOI1:TFF_SR_ENABLEIOI1:OFF_SR_ENABLEIOI1:IFF_SR_ENABLEIOI1:I_DELAY_ENABLE
30 IOI1:TFF_REV_ENABLEIOI1:OFF_REV_ENABLEIOI1:IFF_REV_ENABLEIOI1:IDDRIN_MUX[0]
31 ~IOI1:TFF_INIT~IOI1:OFF_INITIOI1:IFF_SR_SYNC-
32 IOI1:MISR_RESET-~IOI1:IFF1_INITIOI1:I_TSBYPASS_ENABLE
33 IOI1:MISR_ENABLE---
34 ~IOI1:TFF2_SRVAL~IOI1:OFF2_SRVAL--
35 -IOI0:O1_DDRMUX-IOI1:TSBYPASS_MUX
36 ~IOI1:TFF1_SRVAL~IOI1:OFF1_SRVAL~IOI1:IFF1_SRVALIOI1:IFF_TSBYPASS_ENABLE
37 IOI0:O2_DDRMUX--IOI0:IDDRIN_MUX[1]
38 IOI1:MISR_CLOCK[1]--IOI1:IFF_DELAY_ENABLE
39 IOI1:MISR_CLOCK[0]IOI1:PCICE_MUX[0]IOI1:PCICE_MUX[1]IOI1:READBACK_I
40 ----
41 ---~IOI0:DELAY_COMMON
42 ---~IOI1:DELAY_COMMON
43 ----
44 ----
45 ----
46 ----
47 ---~IOI1:IFF_DELAY[0]
48 ---IOI0:DELAY_VARIABLE
49 ---~IOI0:I_DELAY[1]
50 ---~IOI0:I_DELAY[2]
51 ---~IOI0:IFF_DELAY[0]
52 ---~IOI0:I_DELAY[0]
53 ---~IOI0:IFF_DELAY[1]
54 ---~IOI1:I_DELAY[0]
55 ---~IOI1:I_DELAY[1]
56 ---~IOI1:I_DELAY[2]
57 ---IOI1:DELAY_VARIABLE
58 ---~IOI1:IFF_DELAY[1]
IOI0:MISR_CLOCK[0, 0, 1][0, 0, 0]
IOI1:MISR_CLOCK[0, 0, 38][0, 0, 39]
NONE00
OTCLK101
OTCLK210
IOI0:O2_DDRMUX[0, 0, 37]
IOI1:O2_DDRMUX[0, 0, 2]
O20
ODDRIN21
IOI0:DELAY_COMMON[0, 3, 41]
IOI0:IFF1_INIT[0, 2, 7]
IOI0:IFF1_SRVAL[0, 2, 3]
IOI0:IFF2_INIT[0, 2, 12]
IOI0:IFF2_SRVAL[0, 2, 16]
IOI0:INV.ICE[0, 3, 14]
IOI0:INV.ICLK1[0, 3, 13]
IOI0:INV.ICLK2[0, 3, 12]
IOI0:INV.OTCLK1[0, 3, 16]
IOI0:INV.OTCLK2[0, 3, 15]
IOI0:INV.REV[0, 3, 11]
IOI0:INV.TCE[0, 3, 17]
IOI0:OFF1_SRVAL[0, 1, 3]
IOI0:OFF2_SRVAL[0, 1, 5]
IOI0:OFF_INIT[0, 1, 8]
IOI0:TFF1_SRVAL[0, 0, 3]
IOI0:TFF2_SRVAL[0, 0, 5]
IOI0:TFF_INIT[0, 0, 8]
IOI1:DELAY_COMMON[0, 3, 42]
IOI1:IFF1_INIT[0, 2, 32]
IOI1:IFF1_SRVAL[0, 2, 36]
IOI1:IFF2_INIT[0, 2, 27]
IOI1:IFF2_SRVAL[0, 2, 23]
IOI1:INV.ICE[0, 3, 25]
IOI1:INV.ICLK1[0, 3, 26]
IOI1:INV.ICLK2[0, 3, 27]
IOI1:INV.OTCLK1[0, 3, 23]
IOI1:INV.OTCLK2[0, 3, 24]
IOI1:INV.REV[0, 3, 28]
IOI1:INV.TCE[0, 3, 22]
IOI1:OFF1_SRVAL[0, 1, 36]
IOI1:OFF2_SRVAL[0, 1, 34]
IOI1:OFF_INIT[0, 1, 31]
IOI1:TFF1_SRVAL[0, 0, 36]
IOI1:TFF2_SRVAL[0, 0, 34]
IOI1:TFF_INIT[0, 0, 31]
Inverted~[0]
IOI0:DELAY_VARIABLE[0, 3, 48]
IOI0:IFF_DELAY_ENABLE[0, 3, 1]
IOI0:IFF_LATCH[0, 2, 11]
IOI0:IFF_REV_ENABLE[0, 2, 9]
IOI0:IFF_SR_ENABLE[0, 2, 10]
IOI0:IFF_SR_SYNC[0, 2, 8]
IOI0:IFF_TSBYPASS_ENABLE[0, 3, 3]
IOI0:INV.O1[0, 1, 12]
IOI0:INV.O2[0, 1, 11]
IOI0:INV.T1[0, 0, 12]
IOI0:INV.T2[0, 0, 11]
IOI0:I_DELAY_ENABLE[0, 3, 10]
IOI0:I_TSBYPASS_ENABLE[0, 3, 7]
IOI0:MISR_ENABLE[0, 0, 6]
IOI0:MISR_RESET[0, 0, 7]
IOI0:OFF1_LATCH[0, 1, 17]
IOI0:OFF2_LATCH[0, 1, 18]
IOI0:OFF_REV_ENABLE[0, 1, 9]
IOI0:OFF_SR_ENABLE[0, 1, 10]
IOI0:OFF_SR_SYNC[0, 1, 13]
IOI0:READBACK_I[0, 3, 0]
IOI0:TFF1_LATCH[0, 0, 17]
IOI0:TFF2_LATCH[0, 0, 18]
IOI0:TFF_REV_ENABLE[0, 0, 9]
IOI0:TFF_SR_ENABLE[0, 0, 10]
IOI0:TFF_SR_SYNC[0, 0, 13]
IOI1:DELAY_VARIABLE[0, 3, 57]
IOI1:IFF_DELAY_ENABLE[0, 3, 38]
IOI1:IFF_LATCH[0, 2, 28]
IOI1:IFF_REV_ENABLE[0, 2, 30]
IOI1:IFF_SR_ENABLE[0, 2, 29]
IOI1:IFF_SR_SYNC[0, 2, 31]
IOI1:IFF_TSBYPASS_ENABLE[0, 3, 36]
IOI1:INV.O1[0, 1, 27]
IOI1:INV.O2[0, 1, 28]
IOI1:INV.T1[0, 0, 27]
IOI1:INV.T2[0, 0, 28]
IOI1:I_DELAY_ENABLE[0, 3, 29]
IOI1:I_TSBYPASS_ENABLE[0, 3, 32]
IOI1:MISR_ENABLE[0, 0, 33]
IOI1:MISR_RESET[0, 0, 32]
IOI1:OFF1_LATCH[0, 1, 22]
IOI1:OFF2_LATCH[0, 1, 21]
IOI1:OFF_REV_ENABLE[0, 1, 30]
IOI1:OFF_SR_ENABLE[0, 1, 29]
IOI1:OFF_SR_SYNC[0, 1, 26]
IOI1:READBACK_I[0, 3, 39]
IOI1:TFF1_LATCH[0, 0, 22]
IOI1:TFF2_LATCH[0, 0, 21]
IOI1:TFF_REV_ENABLE[0, 0, 30]
IOI1:TFF_SR_ENABLE[0, 0, 29]
IOI1:TFF_SR_SYNC[0, 0, 26]
Non-inverted[0]
IOI0:TMUX[0, 0, 15][0, 0, 19][0, 0, 14][0, 0, 16]
IOI1:TMUX[0, 0, 24][0, 0, 20][0, 0, 25][0, 0, 23]
NONE0000
T10001
T20010
TFF10100
TFF21000
TFFDDR1100
IOI0:PCICE_MUX[0, 2, 0][0, 1, 0]
IOI1:PCICE_MUX[0, 2, 39][0, 1, 39]
NONE00
OCE01
PCICE10
IOI0:O1_DDRMUX[0, 1, 35]
IOI1:O1_DDRMUX[0, 1, 4]
O10
ODDRIN11
IOI0:OMUX[0, 1, 15][0, 1, 19][0, 1, 14][0, 1, 16]
IOI1:OMUX[0, 1, 24][0, 1, 20][0, 1, 25][0, 1, 23]
NONE0000
O10001
O20010
OFF10100
OFF21000
OFFDDR1100
IOI0:TSBYPASS_MUX[0, 3, 4]
IOI1:TSBYPASS_MUX[0, 3, 35]
TMUX0
GND1
IOI0:IDDRIN_MUX[0, 3, 21][0, 3, 37][0, 3, 8]
IOI1:IDDRIN_MUX[0, 3, 18][0, 3, 2][0, 3, 30]
NONE000
IFFDMUX001
IDDRIN1010
IDDRIN2100
IOI0:IFF_DELAY[0, 3, 53][0, 3, 51]
IOI1:IFF_DELAY[0, 3, 58][0, 3, 47]
Inverted~[1]~[0]
IOI0:I_DELAY[0, 3, 50][0, 3, 49][0, 3, 52]
IOI1:I_DELAY[0, 3, 56][0, 3, 55][0, 3, 54]
Inverted~[2]~[1]~[0]

IOI.S3A.B

IOI.S3A.B bittile 0
RowColumn
0123
0 IOI0:MISR_CLOCK[0]IOI0:PCICE_MUX[0]IOI0:PCICE_MUX[1]IOI0:READBACK_I
1 IOI0:MISR_CLOCK[1]--IOI0:IFF_DELAY_ENABLE
2 IOI1:O2_DDRMUX--IOI1:IDDRIN_MUX[1]
3 ~IOI0:TFF1_SRVAL~IOI0:OFF1_SRVAL~IOI0:IFF1_SRVALIOI0:IFF_TSBYPASS_ENABLE
4 -IOI1:O1_DDRMUX-IOI0:TSBYPASS_MUX
5 ~IOI0:TFF2_SRVAL~IOI0:OFF2_SRVAL--
6 IOI0:MISR_ENABLE---
7 IOI0:MISR_RESET-~IOI0:IFF1_INITIOI0:I_TSBYPASS_ENABLE
8 ~IOI0:TFF_INIT~IOI0:OFF_INITIOI0:IFF_SR_SYNCIOI0:IDDRIN_MUX[0]
9 IOI0:TFF_REV_ENABLEIOI0:OFF_REV_ENABLEIOI0:IFF_REV_ENABLE-
10 IOI0:TFF_SR_ENABLEIOI0:OFF_SR_ENABLEIOI0:IFF_SR_ENABLEIOI0:I_DELAY_ENABLE
11 IOI0:INV.T2IOI0:INV.O2IOI0:IFF_LATCH~IOI0:INV.REV
12 IOI0:INV.T1IOI0:INV.O1~IOI0:IFF2_INIT~IOI0:INV.ICLK2
13 IOI0:TFF_SR_SYNCIOI0:OFF_SR_SYNC-~IOI0:INV.ICLK1
14 IOI0:TMUX[1]IOI0:OMUX[1]-~IOI0:INV.ICE
15 IOI0:TMUX[3]IOI0:OMUX[3]-~IOI0:INV.OTCLK2
16 IOI0:TMUX[0]IOI0:OMUX[0]~IOI0:IFF2_SRVAL~IOI0:INV.OTCLK1
17 IOI0:TFF1_LATCHIOI0:OFF1_LATCH-~IOI0:INV.TCE
18 IOI0:TFF2_LATCHIOI0:OFF2_LATCH-IOI1:IDDRIN_MUX[2]
19 IOI0:TMUX[2]IOI0:OMUX[2]--
20 IOI1:TMUX[2]IOI1:OMUX[2]--
21 IOI1:TFF2_LATCHIOI1:OFF2_LATCH-IOI0:IDDRIN_MUX[2]
22 IOI1:TFF1_LATCHIOI1:OFF1_LATCH-~IOI1:INV.TCE
23 IOI1:TMUX[0]IOI1:OMUX[0]~IOI1:IFF2_SRVAL~IOI1:INV.OTCLK1
24 IOI1:TMUX[3]IOI1:OMUX[3]-~IOI1:INV.OTCLK2
25 IOI1:TMUX[1]IOI1:OMUX[1]-~IOI1:INV.ICE
26 IOI1:TFF_SR_SYNCIOI1:OFF_SR_SYNC-~IOI1:INV.ICLK1
27 IOI1:INV.T1IOI1:INV.O1~IOI1:IFF2_INIT~IOI1:INV.ICLK2
28 IOI1:INV.T2IOI1:INV.O2IOI1:IFF_LATCH~IOI1:INV.REV
29 IOI1:TFF_SR_ENABLEIOI1:OFF_SR_ENABLEIOI1:IFF_SR_ENABLEIOI1:I_DELAY_ENABLE
30 IOI1:TFF_REV_ENABLEIOI1:OFF_REV_ENABLEIOI1:IFF_REV_ENABLEIOI1:IDDRIN_MUX[0]
31 ~IOI1:TFF_INIT~IOI1:OFF_INITIOI1:IFF_SR_SYNC-
32 IOI1:MISR_RESET-~IOI1:IFF1_INITIOI1:I_TSBYPASS_ENABLE
33 IOI1:MISR_ENABLE---
34 ~IOI1:TFF2_SRVAL~IOI1:OFF2_SRVAL--
35 -IOI0:O1_DDRMUX-IOI1:TSBYPASS_MUX
36 ~IOI1:TFF1_SRVAL~IOI1:OFF1_SRVAL~IOI1:IFF1_SRVALIOI1:IFF_TSBYPASS_ENABLE
37 IOI0:O2_DDRMUX--IOI0:IDDRIN_MUX[1]
38 IOI1:MISR_CLOCK[1]--IOI1:IFF_DELAY_ENABLE
39 IOI1:MISR_CLOCK[0]IOI1:PCICE_MUX[0]IOI1:PCICE_MUX[1]IOI1:READBACK_I
40 IOI2:MISR_CLOCK[0]IOI2:PCICE_MUX[0]IOI2:PCICE_MUX[1]IOI2:READBACK_I
41 IOI2:MISR_CLOCK[1]--IOI2:IFF_DELAY_ENABLE
42 ---IOI2:IDDRIN_MUX[1]
43 ~IOI2:TFF1_SRVAL~IOI2:OFF1_SRVAL~IOI2:IFF1_SRVALIOI2:IFF_TSBYPASS_ENABLE
44 ---IOI2:TSBYPASS_MUX
45 ~IOI2:TFF2_SRVAL~IOI2:OFF2_SRVAL--
46 IOI2:MISR_ENABLE---
47 IOI2:MISR_RESET-~IOI2:IFF1_INITIOI2:I_TSBYPASS_ENABLE
48 ~IOI2:TFF_INIT~IOI2:OFF_INITIOI2:IFF_SR_SYNCIOI2:IDDRIN_MUX[0]
49 IOI2:TFF_REV_ENABLEIOI2:OFF_REV_ENABLEIOI2:IFF_REV_ENABLE-
50 IOI2:TFF_SR_ENABLEIOI2:OFF_SR_ENABLEIOI2:IFF_SR_ENABLEIOI2:I_DELAY_ENABLE
51 IOI2:INV.T2IOI2:INV.O2IOI2:IFF_LATCH~IOI2:INV.REV
52 IOI2:INV.T1IOI2:INV.O1~IOI2:IFF2_INIT~IOI2:INV.ICLK2
53 IOI2:TFF_SR_SYNCIOI2:OFF_SR_SYNC-~IOI2:INV.ICLK1
54 IOI2:TMUX[1]IOI2:OMUX[1]-~IOI2:INV.ICE
55 IOI2:TMUX[3]IOI2:OMUX[3]-~IOI2:INV.OTCLK2
56 IOI2:TMUX[0]IOI2:OMUX[0]~IOI2:IFF2_SRVAL~IOI2:INV.OTCLK1
57 IOI2:TFF1_LATCHIOI2:OFF1_LATCH-~IOI2:INV.TCE
58 IOI2:TFF2_LATCHIOI2:OFF2_LATCH-IOI2:IDDRIN_MUX[2]
59 IOI2:TMUX[2]IOI2:OMUX[2]--
IOI0:MISR_CLOCK[0, 0, 1][0, 0, 0]
IOI1:MISR_CLOCK[0, 0, 38][0, 0, 39]
IOI2:MISR_CLOCK[0, 0, 41][0, 0, 40]
NONE00
OTCLK101
OTCLK210
IOI0:O2_DDRMUX[0, 0, 37]
IOI1:O2_DDRMUX[0, 0, 2]
O20
ODDRIN21
IOI0:IFF1_INIT[0, 2, 7]
IOI0:IFF1_SRVAL[0, 2, 3]
IOI0:IFF2_INIT[0, 2, 12]
IOI0:IFF2_SRVAL[0, 2, 16]
IOI0:INV.ICE[0, 3, 14]
IOI0:INV.ICLK1[0, 3, 13]
IOI0:INV.ICLK2[0, 3, 12]
IOI0:INV.OTCLK1[0, 3, 16]
IOI0:INV.OTCLK2[0, 3, 15]
IOI0:INV.REV[0, 3, 11]
IOI0:INV.TCE[0, 3, 17]
IOI0:OFF1_SRVAL[0, 1, 3]
IOI0:OFF2_SRVAL[0, 1, 5]
IOI0:OFF_INIT[0, 1, 8]
IOI0:TFF1_SRVAL[0, 0, 3]
IOI0:TFF2_SRVAL[0, 0, 5]
IOI0:TFF_INIT[0, 0, 8]
IOI1:IFF1_INIT[0, 2, 32]
IOI1:IFF1_SRVAL[0, 2, 36]
IOI1:IFF2_INIT[0, 2, 27]
IOI1:IFF2_SRVAL[0, 2, 23]
IOI1:INV.ICE[0, 3, 25]
IOI1:INV.ICLK1[0, 3, 26]
IOI1:INV.ICLK2[0, 3, 27]
IOI1:INV.OTCLK1[0, 3, 23]
IOI1:INV.OTCLK2[0, 3, 24]
IOI1:INV.REV[0, 3, 28]
IOI1:INV.TCE[0, 3, 22]
IOI1:OFF1_SRVAL[0, 1, 36]
IOI1:OFF2_SRVAL[0, 1, 34]
IOI1:OFF_INIT[0, 1, 31]
IOI1:TFF1_SRVAL[0, 0, 36]
IOI1:TFF2_SRVAL[0, 0, 34]
IOI1:TFF_INIT[0, 0, 31]
IOI2:IFF1_INIT[0, 2, 47]
IOI2:IFF1_SRVAL[0, 2, 43]
IOI2:IFF2_INIT[0, 2, 52]
IOI2:IFF2_SRVAL[0, 2, 56]
IOI2:INV.ICE[0, 3, 54]
IOI2:INV.ICLK1[0, 3, 53]
IOI2:INV.ICLK2[0, 3, 52]
IOI2:INV.OTCLK1[0, 3, 56]
IOI2:INV.OTCLK2[0, 3, 55]
IOI2:INV.REV[0, 3, 51]
IOI2:INV.TCE[0, 3, 57]
IOI2:OFF1_SRVAL[0, 1, 43]
IOI2:OFF2_SRVAL[0, 1, 45]
IOI2:OFF_INIT[0, 1, 48]
IOI2:TFF1_SRVAL[0, 0, 43]
IOI2:TFF2_SRVAL[0, 0, 45]
IOI2:TFF_INIT[0, 0, 48]
Inverted~[0]
IOI0:IFF_DELAY_ENABLE[0, 3, 1]
IOI0:IFF_LATCH[0, 2, 11]
IOI0:IFF_REV_ENABLE[0, 2, 9]
IOI0:IFF_SR_ENABLE[0, 2, 10]
IOI0:IFF_SR_SYNC[0, 2, 8]
IOI0:IFF_TSBYPASS_ENABLE[0, 3, 3]
IOI0:INV.O1[0, 1, 12]
IOI0:INV.O2[0, 1, 11]
IOI0:INV.T1[0, 0, 12]
IOI0:INV.T2[0, 0, 11]
IOI0:I_DELAY_ENABLE[0, 3, 10]
IOI0:I_TSBYPASS_ENABLE[0, 3, 7]
IOI0:MISR_ENABLE[0, 0, 6]
IOI0:MISR_RESET[0, 0, 7]
IOI0:OFF1_LATCH[0, 1, 17]
IOI0:OFF2_LATCH[0, 1, 18]
IOI0:OFF_REV_ENABLE[0, 1, 9]
IOI0:OFF_SR_ENABLE[0, 1, 10]
IOI0:OFF_SR_SYNC[0, 1, 13]
IOI0:READBACK_I[0, 3, 0]
IOI0:TFF1_LATCH[0, 0, 17]
IOI0:TFF2_LATCH[0, 0, 18]
IOI0:TFF_REV_ENABLE[0, 0, 9]
IOI0:TFF_SR_ENABLE[0, 0, 10]
IOI0:TFF_SR_SYNC[0, 0, 13]
IOI1:IFF_DELAY_ENABLE[0, 3, 38]
IOI1:IFF_LATCH[0, 2, 28]
IOI1:IFF_REV_ENABLE[0, 2, 30]
IOI1:IFF_SR_ENABLE[0, 2, 29]
IOI1:IFF_SR_SYNC[0, 2, 31]
IOI1:IFF_TSBYPASS_ENABLE[0, 3, 36]
IOI1:INV.O1[0, 1, 27]
IOI1:INV.O2[0, 1, 28]
IOI1:INV.T1[0, 0, 27]
IOI1:INV.T2[0, 0, 28]
IOI1:I_DELAY_ENABLE[0, 3, 29]
IOI1:I_TSBYPASS_ENABLE[0, 3, 32]
IOI1:MISR_ENABLE[0, 0, 33]
IOI1:MISR_RESET[0, 0, 32]
IOI1:OFF1_LATCH[0, 1, 22]
IOI1:OFF2_LATCH[0, 1, 21]
IOI1:OFF_REV_ENABLE[0, 1, 30]
IOI1:OFF_SR_ENABLE[0, 1, 29]
IOI1:OFF_SR_SYNC[0, 1, 26]
IOI1:READBACK_I[0, 3, 39]
IOI1:TFF1_LATCH[0, 0, 22]
IOI1:TFF2_LATCH[0, 0, 21]
IOI1:TFF_REV_ENABLE[0, 0, 30]
IOI1:TFF_SR_ENABLE[0, 0, 29]
IOI1:TFF_SR_SYNC[0, 0, 26]
IOI2:IFF_DELAY_ENABLE[0, 3, 41]
IOI2:IFF_LATCH[0, 2, 51]
IOI2:IFF_REV_ENABLE[0, 2, 49]
IOI2:IFF_SR_ENABLE[0, 2, 50]
IOI2:IFF_SR_SYNC[0, 2, 48]
IOI2:IFF_TSBYPASS_ENABLE[0, 3, 43]
IOI2:INV.O1[0, 1, 52]
IOI2:INV.O2[0, 1, 51]
IOI2:INV.T1[0, 0, 52]
IOI2:INV.T2[0, 0, 51]
IOI2:I_DELAY_ENABLE[0, 3, 50]
IOI2:I_TSBYPASS_ENABLE[0, 3, 47]
IOI2:MISR_ENABLE[0, 0, 46]
IOI2:MISR_RESET[0, 0, 47]
IOI2:OFF1_LATCH[0, 1, 57]
IOI2:OFF2_LATCH[0, 1, 58]
IOI2:OFF_REV_ENABLE[0, 1, 49]
IOI2:OFF_SR_ENABLE[0, 1, 50]
IOI2:OFF_SR_SYNC[0, 1, 53]
IOI2:READBACK_I[0, 3, 40]
IOI2:TFF1_LATCH[0, 0, 57]
IOI2:TFF2_LATCH[0, 0, 58]
IOI2:TFF_REV_ENABLE[0, 0, 49]
IOI2:TFF_SR_ENABLE[0, 0, 50]
IOI2:TFF_SR_SYNC[0, 0, 53]
Non-inverted[0]
IOI0:TMUX[0, 0, 15][0, 0, 19][0, 0, 14][0, 0, 16]
IOI1:TMUX[0, 0, 24][0, 0, 20][0, 0, 25][0, 0, 23]
IOI2:TMUX[0, 0, 55][0, 0, 59][0, 0, 54][0, 0, 56]
NONE0000
T10001
T20010
TFF10100
TFF21000
TFFDDR1100
IOI0:PCICE_MUX[0, 2, 0][0, 1, 0]
IOI1:PCICE_MUX[0, 2, 39][0, 1, 39]
IOI2:PCICE_MUX[0, 2, 40][0, 1, 40]
NONE00
OCE01
PCICE10
IOI0:O1_DDRMUX[0, 1, 35]
IOI1:O1_DDRMUX[0, 1, 4]
O10
ODDRIN11
IOI0:OMUX[0, 1, 15][0, 1, 19][0, 1, 14][0, 1, 16]
IOI1:OMUX[0, 1, 24][0, 1, 20][0, 1, 25][0, 1, 23]
IOI2:OMUX[0, 1, 55][0, 1, 59][0, 1, 54][0, 1, 56]
NONE0000
O10001
O20010
OFF10100
OFF21000
OFFDDR1100
IOI0:TSBYPASS_MUX[0, 3, 4]
IOI1:TSBYPASS_MUX[0, 3, 35]
IOI2:TSBYPASS_MUX[0, 3, 44]
TMUX0
GND1
IOI0:IDDRIN_MUX[0, 3, 21][0, 3, 37][0, 3, 8]
IOI1:IDDRIN_MUX[0, 3, 18][0, 3, 2][0, 3, 30]
IOI2:IDDRIN_MUX[0, 3, 58][0, 3, 42][0, 3, 48]
NONE000
IFFDMUX001
IDDRIN1010
IDDRIN2100

IOI.S3A.T

IOI.S3A.T bittile 0
RowColumn
0123
0 IOI0:MISR_CLOCK[0]IOI0:PCICE_MUX[0]IOI0:PCICE_MUX[1]IOI0:READBACK_I
1 IOI0:MISR_CLOCK[1]--IOI0:IFF_DELAY_ENABLE
2 IOI1:O2_DDRMUX--IOI1:IDDRIN_MUX[1]
3 ~IOI0:TFF1_SRVAL~IOI0:OFF1_SRVAL~IOI0:IFF1_SRVALIOI0:IFF_TSBYPASS_ENABLE
4 -IOI1:O1_DDRMUX-IOI0:TSBYPASS_MUX
5 ~IOI0:TFF2_SRVAL~IOI0:OFF2_SRVAL--
6 IOI0:MISR_ENABLE---
7 IOI0:MISR_RESET-~IOI0:IFF1_INITIOI0:I_TSBYPASS_ENABLE
8 ~IOI0:TFF_INIT~IOI0:OFF_INITIOI0:IFF_SR_SYNCIOI0:IDDRIN_MUX[0]
9 IOI0:TFF_REV_ENABLEIOI0:OFF_REV_ENABLEIOI0:IFF_REV_ENABLE-
10 IOI0:TFF_SR_ENABLEIOI0:OFF_SR_ENABLEIOI0:IFF_SR_ENABLEIOI0:I_DELAY_ENABLE
11 IOI0:INV.T2IOI0:INV.O2IOI0:IFF_LATCH~IOI0:INV.REV
12 IOI0:INV.T1IOI0:INV.O1~IOI0:IFF2_INIT~IOI0:INV.ICLK2
13 IOI0:TFF_SR_SYNCIOI0:OFF_SR_SYNC-~IOI0:INV.ICLK1
14 IOI0:TMUX[1]IOI0:OMUX[1]-~IOI0:INV.ICE
15 IOI0:TMUX[3]IOI0:OMUX[3]-~IOI0:INV.OTCLK2
16 IOI0:TMUX[0]IOI0:OMUX[0]~IOI0:IFF2_SRVAL~IOI0:INV.OTCLK1
17 IOI0:TFF1_LATCHIOI0:OFF1_LATCH-~IOI0:INV.TCE
18 IOI0:TFF2_LATCHIOI0:OFF2_LATCH-IOI1:IDDRIN_MUX[2]
19 IOI0:TMUX[2]IOI0:OMUX[2]--
20 IOI1:TMUX[2]IOI1:OMUX[2]--
21 IOI1:TFF2_LATCHIOI1:OFF2_LATCH-IOI0:IDDRIN_MUX[2]
22 IOI1:TFF1_LATCHIOI1:OFF1_LATCH-~IOI1:INV.TCE
23 IOI1:TMUX[0]IOI1:OMUX[0]~IOI1:IFF2_SRVAL~IOI1:INV.OTCLK1
24 IOI1:TMUX[3]IOI1:OMUX[3]-~IOI1:INV.OTCLK2
25 IOI1:TMUX[1]IOI1:OMUX[1]-~IOI1:INV.ICE
26 IOI1:TFF_SR_SYNCIOI1:OFF_SR_SYNC-~IOI1:INV.ICLK1
27 IOI1:INV.T1IOI1:INV.O1~IOI1:IFF2_INIT~IOI1:INV.ICLK2
28 IOI1:INV.T2IOI1:INV.O2IOI1:IFF_LATCH~IOI1:INV.REV
29 IOI1:TFF_SR_ENABLEIOI1:OFF_SR_ENABLEIOI1:IFF_SR_ENABLEIOI1:I_DELAY_ENABLE
30 IOI1:TFF_REV_ENABLEIOI1:OFF_REV_ENABLEIOI1:IFF_REV_ENABLEIOI1:IDDRIN_MUX[0]
31 ~IOI1:TFF_INIT~IOI1:OFF_INITIOI1:IFF_SR_SYNC-
32 IOI1:MISR_RESET-~IOI1:IFF1_INITIOI1:I_TSBYPASS_ENABLE
33 IOI1:MISR_ENABLE---
34 ~IOI1:TFF2_SRVAL~IOI1:OFF2_SRVAL--
35 -IOI0:O1_DDRMUX-IOI1:TSBYPASS_MUX
36 ~IOI1:TFF1_SRVAL~IOI1:OFF1_SRVAL~IOI1:IFF1_SRVALIOI1:IFF_TSBYPASS_ENABLE
37 IOI0:O2_DDRMUX--IOI0:IDDRIN_MUX[1]
38 IOI1:MISR_CLOCK[1]--IOI1:IFF_DELAY_ENABLE
39 IOI1:MISR_CLOCK[0]IOI1:PCICE_MUX[0]IOI1:PCICE_MUX[1]IOI1:READBACK_I
40 IOI2:MISR_CLOCK[0]IOI2:PCICE_MUX[0]IOI2:PCICE_MUX[1]IOI2:READBACK_I
41 IOI2:MISR_CLOCK[1]--IOI2:IFF_DELAY_ENABLE
42 ---IOI2:IDDRIN_MUX[1]
43 ~IOI2:TFF1_SRVAL~IOI2:OFF1_SRVAL~IOI2:IFF1_SRVALIOI2:IFF_TSBYPASS_ENABLE
44 ---IOI2:TSBYPASS_MUX
45 ~IOI2:TFF2_SRVAL~IOI2:OFF2_SRVAL--
46 IOI2:MISR_ENABLE---
47 IOI2:MISR_RESET-~IOI2:IFF1_INITIOI2:I_TSBYPASS_ENABLE
48 ~IOI2:TFF_INIT~IOI2:OFF_INITIOI2:IFF_SR_SYNCIOI2:IDDRIN_MUX[0]
49 IOI2:TFF_REV_ENABLEIOI2:OFF_REV_ENABLEIOI2:IFF_REV_ENABLE-
50 IOI2:TFF_SR_ENABLEIOI2:OFF_SR_ENABLEIOI2:IFF_SR_ENABLEIOI2:I_DELAY_ENABLE
51 IOI2:INV.T2IOI2:INV.O2IOI2:IFF_LATCH~IOI2:INV.REV
52 IOI2:INV.T1IOI2:INV.O1~IOI2:IFF2_INIT~IOI2:INV.ICLK2
53 IOI2:TFF_SR_SYNCIOI2:OFF_SR_SYNC-~IOI2:INV.ICLK1
54 IOI2:TMUX[1]IOI2:OMUX[1]-~IOI2:INV.ICE
55 IOI2:TMUX[3]IOI2:OMUX[3]-~IOI2:INV.OTCLK2
56 IOI2:TMUX[0]IOI2:OMUX[0]~IOI2:IFF2_SRVAL~IOI2:INV.OTCLK1
57 IOI2:TFF1_LATCHIOI2:OFF1_LATCH-~IOI2:INV.TCE
58 IOI2:TFF2_LATCHIOI2:OFF2_LATCH-IOI2:IDDRIN_MUX[2]
59 IOI2:TMUX[2]IOI2:OMUX[2]--
IOI0:MISR_CLOCK[0, 0, 1][0, 0, 0]
IOI1:MISR_CLOCK[0, 0, 38][0, 0, 39]
IOI2:MISR_CLOCK[0, 0, 41][0, 0, 40]
NONE00
OTCLK101
OTCLK210
IOI0:O2_DDRMUX[0, 0, 37]
IOI1:O2_DDRMUX[0, 0, 2]
O20
ODDRIN21
IOI0:IFF1_INIT[0, 2, 7]
IOI0:IFF1_SRVAL[0, 2, 3]
IOI0:IFF2_INIT[0, 2, 12]
IOI0:IFF2_SRVAL[0, 2, 16]
IOI0:INV.ICE[0, 3, 14]
IOI0:INV.ICLK1[0, 3, 13]
IOI0:INV.ICLK2[0, 3, 12]
IOI0:INV.OTCLK1[0, 3, 16]
IOI0:INV.OTCLK2[0, 3, 15]
IOI0:INV.REV[0, 3, 11]
IOI0:INV.TCE[0, 3, 17]
IOI0:OFF1_SRVAL[0, 1, 3]
IOI0:OFF2_SRVAL[0, 1, 5]
IOI0:OFF_INIT[0, 1, 8]
IOI0:TFF1_SRVAL[0, 0, 3]
IOI0:TFF2_SRVAL[0, 0, 5]
IOI0:TFF_INIT[0, 0, 8]
IOI1:IFF1_INIT[0, 2, 32]
IOI1:IFF1_SRVAL[0, 2, 36]
IOI1:IFF2_INIT[0, 2, 27]
IOI1:IFF2_SRVAL[0, 2, 23]
IOI1:INV.ICE[0, 3, 25]
IOI1:INV.ICLK1[0, 3, 26]
IOI1:INV.ICLK2[0, 3, 27]
IOI1:INV.OTCLK1[0, 3, 23]
IOI1:INV.OTCLK2[0, 3, 24]
IOI1:INV.REV[0, 3, 28]
IOI1:INV.TCE[0, 3, 22]
IOI1:OFF1_SRVAL[0, 1, 36]
IOI1:OFF2_SRVAL[0, 1, 34]
IOI1:OFF_INIT[0, 1, 31]
IOI1:TFF1_SRVAL[0, 0, 36]
IOI1:TFF2_SRVAL[0, 0, 34]
IOI1:TFF_INIT[0, 0, 31]
IOI2:IFF1_INIT[0, 2, 47]
IOI2:IFF1_SRVAL[0, 2, 43]
IOI2:IFF2_INIT[0, 2, 52]
IOI2:IFF2_SRVAL[0, 2, 56]
IOI2:INV.ICE[0, 3, 54]
IOI2:INV.ICLK1[0, 3, 53]
IOI2:INV.ICLK2[0, 3, 52]
IOI2:INV.OTCLK1[0, 3, 56]
IOI2:INV.OTCLK2[0, 3, 55]
IOI2:INV.REV[0, 3, 51]
IOI2:INV.TCE[0, 3, 57]
IOI2:OFF1_SRVAL[0, 1, 43]
IOI2:OFF2_SRVAL[0, 1, 45]
IOI2:OFF_INIT[0, 1, 48]
IOI2:TFF1_SRVAL[0, 0, 43]
IOI2:TFF2_SRVAL[0, 0, 45]
IOI2:TFF_INIT[0, 0, 48]
Inverted~[0]
IOI0:IFF_DELAY_ENABLE[0, 3, 1]
IOI0:IFF_LATCH[0, 2, 11]
IOI0:IFF_REV_ENABLE[0, 2, 9]
IOI0:IFF_SR_ENABLE[0, 2, 10]
IOI0:IFF_SR_SYNC[0, 2, 8]
IOI0:IFF_TSBYPASS_ENABLE[0, 3, 3]
IOI0:INV.O1[0, 1, 12]
IOI0:INV.O2[0, 1, 11]
IOI0:INV.T1[0, 0, 12]
IOI0:INV.T2[0, 0, 11]
IOI0:I_DELAY_ENABLE[0, 3, 10]
IOI0:I_TSBYPASS_ENABLE[0, 3, 7]
IOI0:MISR_ENABLE[0, 0, 6]
IOI0:MISR_RESET[0, 0, 7]
IOI0:OFF1_LATCH[0, 1, 17]
IOI0:OFF2_LATCH[0, 1, 18]
IOI0:OFF_REV_ENABLE[0, 1, 9]
IOI0:OFF_SR_ENABLE[0, 1, 10]
IOI0:OFF_SR_SYNC[0, 1, 13]
IOI0:READBACK_I[0, 3, 0]
IOI0:TFF1_LATCH[0, 0, 17]
IOI0:TFF2_LATCH[0, 0, 18]
IOI0:TFF_REV_ENABLE[0, 0, 9]
IOI0:TFF_SR_ENABLE[0, 0, 10]
IOI0:TFF_SR_SYNC[0, 0, 13]
IOI1:IFF_DELAY_ENABLE[0, 3, 38]
IOI1:IFF_LATCH[0, 2, 28]
IOI1:IFF_REV_ENABLE[0, 2, 30]
IOI1:IFF_SR_ENABLE[0, 2, 29]
IOI1:IFF_SR_SYNC[0, 2, 31]
IOI1:IFF_TSBYPASS_ENABLE[0, 3, 36]
IOI1:INV.O1[0, 1, 27]
IOI1:INV.O2[0, 1, 28]
IOI1:INV.T1[0, 0, 27]
IOI1:INV.T2[0, 0, 28]
IOI1:I_DELAY_ENABLE[0, 3, 29]
IOI1:I_TSBYPASS_ENABLE[0, 3, 32]
IOI1:MISR_ENABLE[0, 0, 33]
IOI1:MISR_RESET[0, 0, 32]
IOI1:OFF1_LATCH[0, 1, 22]
IOI1:OFF2_LATCH[0, 1, 21]
IOI1:OFF_REV_ENABLE[0, 1, 30]
IOI1:OFF_SR_ENABLE[0, 1, 29]
IOI1:OFF_SR_SYNC[0, 1, 26]
IOI1:READBACK_I[0, 3, 39]
IOI1:TFF1_LATCH[0, 0, 22]
IOI1:TFF2_LATCH[0, 0, 21]
IOI1:TFF_REV_ENABLE[0, 0, 30]
IOI1:TFF_SR_ENABLE[0, 0, 29]
IOI1:TFF_SR_SYNC[0, 0, 26]
IOI2:IFF_DELAY_ENABLE[0, 3, 41]
IOI2:IFF_LATCH[0, 2, 51]
IOI2:IFF_REV_ENABLE[0, 2, 49]
IOI2:IFF_SR_ENABLE[0, 2, 50]
IOI2:IFF_SR_SYNC[0, 2, 48]
IOI2:IFF_TSBYPASS_ENABLE[0, 3, 43]
IOI2:INV.O1[0, 1, 52]
IOI2:INV.O2[0, 1, 51]
IOI2:INV.T1[0, 0, 52]
IOI2:INV.T2[0, 0, 51]
IOI2:I_DELAY_ENABLE[0, 3, 50]
IOI2:I_TSBYPASS_ENABLE[0, 3, 47]
IOI2:MISR_ENABLE[0, 0, 46]
IOI2:MISR_RESET[0, 0, 47]
IOI2:OFF1_LATCH[0, 1, 57]
IOI2:OFF2_LATCH[0, 1, 58]
IOI2:OFF_REV_ENABLE[0, 1, 49]
IOI2:OFF_SR_ENABLE[0, 1, 50]
IOI2:OFF_SR_SYNC[0, 1, 53]
IOI2:READBACK_I[0, 3, 40]
IOI2:TFF1_LATCH[0, 0, 57]
IOI2:TFF2_LATCH[0, 0, 58]
IOI2:TFF_REV_ENABLE[0, 0, 49]
IOI2:TFF_SR_ENABLE[0, 0, 50]
IOI2:TFF_SR_SYNC[0, 0, 53]
Non-inverted[0]
IOI0:TMUX[0, 0, 15][0, 0, 19][0, 0, 14][0, 0, 16]
IOI1:TMUX[0, 0, 24][0, 0, 20][0, 0, 25][0, 0, 23]
IOI2:TMUX[0, 0, 55][0, 0, 59][0, 0, 54][0, 0, 56]
NONE0000
T10001
T20010
TFF10100
TFF21000
TFFDDR1100
IOI0:PCICE_MUX[0, 2, 0][0, 1, 0]
IOI1:PCICE_MUX[0, 2, 39][0, 1, 39]
IOI2:PCICE_MUX[0, 2, 40][0, 1, 40]
NONE00
OCE01
PCICE10
IOI0:O1_DDRMUX[0, 1, 35]
IOI1:O1_DDRMUX[0, 1, 4]
O10
ODDRIN11
IOI0:OMUX[0, 1, 15][0, 1, 19][0, 1, 14][0, 1, 16]
IOI1:OMUX[0, 1, 24][0, 1, 20][0, 1, 25][0, 1, 23]
IOI2:OMUX[0, 1, 55][0, 1, 59][0, 1, 54][0, 1, 56]
NONE0000
O10001
O20010
OFF10100
OFF21000
OFFDDR1100
IOI0:TSBYPASS_MUX[0, 3, 4]
IOI1:TSBYPASS_MUX[0, 3, 35]
IOI2:TSBYPASS_MUX[0, 3, 44]
TMUX0
GND1
IOI0:IDDRIN_MUX[0, 3, 21][0, 3, 37][0, 3, 8]
IOI1:IDDRIN_MUX[0, 3, 18][0, 3, 2][0, 3, 30]
IOI2:IDDRIN_MUX[0, 3, 58][0, 3, 42][0, 3, 48]
NONE000
IFFDMUX001
IDDRIN1010
IDDRIN2100

I/O buffers — Spartan 3

Todo

document

NameIOSTD:S3:PDRIVEIOSTD:S3:NDRIVE
[3][2][1][0][3][2][1][0]
BLVDS_2511111111
GTL00001111
GTLP00001110
GTLP_DCI00001110
GTL_DCI00001111
HSTL_I10010100
HSTL_III10011001
HSTL_III_1801111001
HSTL_III_DCI10011001
HSTL_III_DCI_1801111001
HSTL_II_1811010110
HSTL_II_DCI_1811010110
HSTL_I_1801110011
HSTL_I_DCI10010011
HSTL_I_DCI_1801110011
LVCMOS12.201010001
LVCMOS12.410010010
LVCMOS12.611010011
LVCMOS15.1211010101
LVCMOS15.200110001
LVCMOS15.401010010
LVCMOS15.601110011
LVCMOS15.810010100
LVCMOS18.1210100101
LVCMOS18.1611010110
LVCMOS18.200100001
LVCMOS18.401000010
LVCMOS18.601010011
LVCMOS18.801110100
LVCMOS25.1201110101
LVCMOS25.1610010110
LVCMOS25.200100001
LVCMOS25.2411011001
LVCMOS25.400110010
LVCMOS25.601000011
LVCMOS25.801010100
LVCMOS33.1201010101
LVCMOS33.1601110110
LVCMOS33.200010001
LVCMOS33.2410101010
LVCMOS33.400100010
LVCMOS33.600110011
LVCMOS33.801000011
LVPECL_2501101111
LVTTL.1201000101
LVTTL.1601010110
LVTTL.200010001
LVTTL.2401111001
LVTTL.400100010
LVTTL.600100011
LVTTL.800110011
OFF00000000
PCI33_301111100
PCI66_301111100
SSTL18_I01110011
SSTL18_II11111000
SSTL18_I_DCI01010011
SSTL2_I01000011
SSTL2_II10010101
SSTL2_II_DCI01010101
SSTL2_I_DCI00110010
NameIOSTD:S3:SLEW
[4][3][2][1][0]
BLVDS_2500000
GTL11111
GTLP11111
GTLP_DCI11111
GTL_DCI11111
HSLVDCI_1511111
HSLVDCI_1811111
HSLVDCI_2511111
HSLVDCI_3311111
HSTL_I11111
HSTL_III11111
HSTL_III_1811111
HSTL_III_DCI11111
HSTL_III_DCI_1811111
HSTL_II_1811111
HSTL_II_DCI_1811111
HSTL_I_1811111
HSTL_I_DCI11111
HSTL_I_DCI_1811111
LVCMOS12.FAST11111
LVCMOS12.SLOW00000
LVCMOS15.FAST11111
LVCMOS15.SLOW00000
LVCMOS18.FAST11111
LVCMOS18.SLOW00000
LVCMOS25.FAST11111
LVCMOS25.SLOW00000
LVCMOS33.FAST11111
LVCMOS33.SLOW00000
LVDCI_1511111
LVDCI_1811111
LVDCI_2511111
LVDCI_3311111
LVDCI_DV2_1511111
LVDCI_DV2_1811111
LVDCI_DV2_2511111
LVDCI_DV2_3311111
LVPECL_2511111
LVTTL.FAST11111
LVTTL.SLOW00000
PCI33_300000
PCI66_300000
SSTL18_I11111
SSTL18_II11111
SSTL18_I_DCI11111
SSTL2_I11111
SSTL2_II11111
SSTL2_II_DCI11111
SSTL2_I_DCI11111
VR00000
NameIOSTD:S3:OUTPUT_MISC
[1][0]
BLVDS_2501
GTL00
GTLP00
GTLP_DCI00
GTL_DCI00
HSLVDCI_1500
HSLVDCI_1800
HSLVDCI_2500
HSLVDCI_3300
HSTL_I11
HSTL_III11
HSTL_III_1811
HSTL_III_DCI11
HSTL_III_DCI_1811
HSTL_II_1811
HSTL_II_DCI_1811
HSTL_I_1811
HSTL_I_DCI11
HSTL_I_DCI_1811
LVCMOS1201
LVCMOS1501
LVCMOS1801
LVCMOS2501
LVCMOS3301
LVDCI_1500
LVDCI_1800
LVDCI_2500
LVDCI_3300
LVDCI_DV2_1500
LVDCI_DV2_1800
LVDCI_DV2_2500
LVDCI_DV2_3300
LVPECL_2501
LVTTL01
PCI33_300
PCI66_300
SSTL18_I00
SSTL18_II00
SSTL18_I_DCI00
SSTL2_I00
SSTL2_II00
SSTL2_II_DCI00
SSTL2_I_DCI00
NameIOSTD:S3:OUTPUT_DIFF
[2][1][0]
LDT_25101
LVDSEXT_25011
LVDSEXT_25_DCI011
LVDS_25001
LVDS_25_DCI001
OFF000
RSDS_25001
ULVDS_25101

IOBS.S3.T2

IOBS.S3.T2 bittile 0
RowColumn
0123456789101112131415161718
0 --~IOB2:PDRIVE[0]IOB1:IBUF_MODE[1]IOB2:DCI_MODE[2]IOB1:OUTPUT_ENABLE[0]IOB1:DCI_MODE[2]~IOB1:NDRIVE[2]IOB1:DCI_MODE[1]-IOB1:PDRIVE[1]IOB1:DCI_MODE[0]IOB0:PULL[2]IOB0:PULL[1]IOB0:NDRIVE[0]-IOB0:IBUF_MODE[1]IOB0:IBUF_MODE[2]IOB0:SLEW[3]
1 -IOB2:IBUF_MODE[1]IOB2:IBUF_MODE[2]IOB1:VR~IOB2:PDRIVE[2]IOB1:SLEW[0]IOB1:OUTPUT_ENABLE[1]IOB1:SLEW[2]~IOB1:PDRIVE[0]-IOB1:PULL[0]IOB1:PDRIVE[3]IOB0:PDRIVE[3]IOB0:NDRIVE[1]IOB0:DISABLE_GTS--~IOB0:PDRIVE[0]IOB0:DCI_MODE[2]
2 -IOB2:IBUF_MODE[0]~IOB2:NDRIVE[2]IOB1:IBUF_MODE[0]IOB2:SLEW[2]IOB2:OUTPUT_ENABLE[0]IOB2:SLEW[4]IOB1:PULL[2]IOB1:IBUF_MODE[2]~IOB1:DCIUPDATEMODE_ASREQUIREDIOB1:NDRIVE[1]IOB1:VREFIOB0:NDRIVE[3]IOB0:PULL[0]IOB0:OUTPUT_MISC[0]IOB0:OUTPUT_MISC[1]IOB0:SLEW[0]IOB0:DCI_MODE[1]IOB0:OUTPUT_ENABLE[0]
3 -IOB2:VRIOB2:SLEW[0]IOB1:OUTPUT_MISC[1]IOB2:SLEW[3]IOB1:NDRIVE[0]IOB2:OUTPUT_ENABLE[1]IOB1:SLEW[3]~IOB1:PDRIVE[2]IOB1:OUTPUT_MISC[0]-IOB1:PULL[1]IOB0:VREFIOB0:PDRIVE[1]~IOB0:DCIUPDATEMODE_ASREQUIRED-IOB0:SLEW[1]IOB0:SLEW[2]IOB0:SLEW[4]
4 -IOB2:OUTPUT_MISC[1]IOB2:SLEW[1]IOB2:OUTPUT_DIFF[2]IOB2:DCI_MODE[1]IOB1:SLEW[1]IOB1:NDRIVE[3]-IOB1:SLEW[4]IOB1:DISABLE_GTS-IOB1:DCI_MODE[3]IOB0:DCI_MODE[3]IOB0:DCI_MODE[0]-IOB0:IBUF_MODE[0]~IOB0:NDRIVE[2]~IOB0:PDRIVE[2]IOB0:OUTPUT_ENABLE[1]
IOBS.S3.T2 bittile 1
RowColumn
0123456789101112131415161718
0 -IOB4:PDRIVE[1]IOB4:VREF~IOB4:DCIUPDATEMODE_ASREQUIREDIOB4:SLEW[0]IOB4:SLEW[1]IOB4:SLEW[2]IOB4:SLEW[3]IOB3:DCI_MODE[2]~IOB3:PDRIVE[0]IOB4:OUTPUT_DIFF[2]~IOB3:NDRIVE[2]IOB3:PDRIVE[3]IOB3:DISABLE_GTSIOB3:PULL[0]IOB2:NDRIVE[1]IOB2:PDRIVE[3]IOB2:DISABLE_GTSIOB2:OUTPUT_DIFF[0]
1 -IOB4:PULL[0]IOB4:NDRIVE[3]IOB4:OUTPUT_MISC[0]-IOB4:OUTPUT_MISC[1]IOB4:DCI_MODE[1]IOB4:OUTPUT_ENABLE[0]IOB3:OUTPUT_ENABLE[0]IOB3:DCI_MODE[1]IOB3:OUTPUT_MISC[1]IOB3:SLEW[3]IOB3:NDRIVE[3]IOB3:OUTPUT_MISC[0]IOB3:PDRIVE[1]-IOB2:PULL[2]IOB2:NDRIVE[0]-
2 -IOB4:NDRIVE[1]IOB4:PDRIVE[3]IOB4:DISABLE_GTSIOB4:IBUF_MODE[1]IOB4:OUTPUT_DIFF[0]~IOB4:PDRIVE[0]IOB4:DCI_MODE[2]IOB3:SLEW[0]IOB3:SLEW[1]IOB3:VR-IOB3:VREF~IOB3:DCIUPDATEMODE_ASREQUIREDIOB3:NDRIVE[1]IOB2:PULL[1]IOB2:DCI_MODE[0]IOB2:DCI_MODE[3]IOB2:OUTPUT_DIFF[1]
3 -IOB4:PULL[1]IOB4:PULL[2]IOB4:NDRIVE[0]IOB4:IBUF_MODE[0]-IOB4:IBUF_MODE[2]IOB4:SLEW[4]IOB3:OUTPUT_ENABLE[1]~IOB3:PDRIVE[2]IOB3:IBUF_MODE[0]IOB3:SLEW[4]IOB3:DCI_MODE[3]-IOB3:DCI_MODE[0]-IOB2:PDRIVE[1]IOB2:NDRIVE[3]~IOB2:DCIUPDATEMODE_ASREQUIRED
4 --IOB4:DCI_MODE[0]IOB4:DCI_MODE[3]IOB4:VRIOB4:OUTPUT_DIFF[1]~IOB4:NDRIVE[2]~IOB4:PDRIVE[2]IOB4:OUTPUT_ENABLE[1]IOB3:SLEW[2]IOB3:IBUF_MODE[1]IOB3:IBUF_MODE[2]IOB3:NDRIVE[0]-IOB3:PULL[2]IOB3:PULL[1]IOB2:PULL[0]IOB2:VREFIOB2:OUTPUT_MISC[0]
IOB1:IBUF_MODE[0, 8, 2][0, 3, 0][0, 3, 2]
IOB2:IBUF_MODE[0, 2, 1][0, 1, 1][0, 1, 2]
IOB3:IBUF_MODE[1, 11, 4][1, 10, 4][1, 10, 3]
IOB4:IBUF_MODE[1, 6, 3][1, 4, 2][1, 4, 3]
NONE000
VREF011
DIFF101
CMOS111
IOB0:DISABLE_GTS[0, 14, 1]
IOB0:VREF[0, 12, 3]
IOB1:DISABLE_GTS[0, 9, 4]
IOB1:VR[0, 3, 1]
IOB1:VREF[0, 11, 2]
IOB2:DISABLE_GTS[1, 17, 0]
IOB2:VR[0, 1, 3]
IOB2:VREF[1, 17, 4]
IOB3:DISABLE_GTS[1, 13, 0]
IOB3:VR[1, 10, 2]
IOB3:VREF[1, 12, 2]
IOB4:DISABLE_GTS[1, 3, 2]
IOB4:VR[1, 4, 4]
IOB4:VREF[1, 2, 0]
Non-inverted[0]
IOB0:PDRIVE[0, 12, 1][0, 17, 4][0, 13, 3][0, 17, 1]
IOB1:PDRIVE[0, 11, 1][0, 8, 3][0, 10, 0][0, 8, 1]
IOB2:PDRIVE[1, 16, 0][0, 4, 1][1, 16, 3][0, 2, 0]
IOB3:PDRIVE[1, 12, 0][1, 9, 3][1, 14, 1][1, 9, 0]
IOB4:PDRIVE[1, 2, 2][1, 7, 4][1, 1, 0][1, 6, 2]
Mixed inversion[3]~[2][1]~[0]
IOB0:SLEW[0, 18, 3][0, 18, 0][0, 17, 3][0, 16, 3][0, 16, 2]
IOB1:SLEW[0, 8, 4][0, 7, 3][0, 7, 1][0, 5, 4][0, 5, 1]
IOB2:SLEW[0, 6, 2][0, 4, 3][0, 4, 2][0, 2, 4][0, 2, 3]
IOB3:SLEW[1, 11, 3][1, 11, 1][1, 9, 4][1, 9, 2][1, 8, 2]
IOB4:SLEW[1, 7, 3][1, 7, 0][1, 6, 0][1, 5, 0][1, 4, 0]
Non-inverted[4][3][2][1][0]
IOB0:OUTPUT_ENABLE[0, 18, 4][0, 18, 2]
IOB0:OUTPUT_MISC[0, 15, 2][0, 14, 2]
IOB1:OUTPUT_ENABLE[0, 6, 1][0, 5, 0]
IOB1:OUTPUT_MISC[0, 3, 3][0, 9, 3]
IOB2:OUTPUT_ENABLE[0, 6, 3][0, 5, 2]
IOB2:OUTPUT_MISC[0, 1, 4][1, 18, 4]
IOB3:OUTPUT_ENABLE[1, 8, 3][1, 8, 1]
IOB3:OUTPUT_MISC[1, 10, 1][1, 13, 1]
IOB4:OUTPUT_ENABLE[1, 8, 4][1, 7, 1]
IOB4:OUTPUT_MISC[1, 5, 1][1, 3, 1]
Non-inverted[1][0]
IOB0:NDRIVE[0, 12, 2][0, 16, 4][0, 13, 1][0, 14, 0]
IOB1:NDRIVE[0, 6, 4][0, 7, 0][0, 10, 2][0, 5, 3]
IOB2:NDRIVE[1, 17, 3][0, 2, 2][1, 15, 0][1, 17, 1]
IOB3:NDRIVE[1, 12, 1][1, 11, 0][1, 14, 2][1, 12, 4]
IOB4:NDRIVE[1, 2, 1][1, 6, 4][1, 1, 2][1, 3, 3]
Mixed inversion[3]~[2][1][0]
IOB0:DCIUPDATEMODE_ASREQUIRED[0, 14, 3]
IOB1:DCIUPDATEMODE_ASREQUIRED[0, 9, 2]
IOB2:DCIUPDATEMODE_ASREQUIRED[1, 18, 3]
IOB3:DCIUPDATEMODE_ASREQUIRED[1, 13, 2]
IOB4:DCIUPDATEMODE_ASREQUIRED[1, 3, 0]
Inverted~[0]
IOB0:PULL[0, 12, 0][0, 13, 0][0, 13, 2]
IOB1:PULL[0, 7, 2][0, 11, 3][0, 10, 1]
IOB2:PULL[1, 16, 1][1, 15, 2][1, 16, 4]
IOB3:PULL[1, 14, 4][1, 15, 4][1, 14, 0]
IOB4:PULL[1, 2, 3][1, 1, 3][1, 1, 1]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DCI_MODE[0, 12, 4][0, 18, 1][0, 17, 2][0, 13, 4]
IOB1:DCI_MODE[0, 11, 4][0, 6, 0][0, 8, 0][0, 11, 0]
IOB2:DCI_MODE[1, 17, 2][0, 4, 0][0, 4, 4][1, 16, 2]
IOB3:DCI_MODE[1, 12, 3][1, 8, 0][1, 9, 1][1, 14, 3]
IOB4:DCI_MODE[1, 3, 4][1, 7, 2][1, 6, 1][1, 2, 4]
NONE0000
OUTPUT0001
OUTPUT_HALF0010
TERM_SPLIT0100
TERM_VCC1011
IOB0:IBUF_MODE[0, 17, 0][0, 16, 0][0, 15, 4]
NONE000
VREF011
CMOS111
IOB2:OUTPUT_DIFF[0, 3, 4][1, 18, 2][1, 18, 0]
IOB4:OUTPUT_DIFF[1, 10, 0][1, 5, 4][1, 5, 2]
Non-inverted[2][1][0]

IOBS.S3.R1

IOBS.S3.R1 bittile 0
RowColumn
01
0 --
1 -IOB1:PULL[1]
2 -IOB1:NDRIVE[1]
3 -IOB1:PULL[0]
4 -IOB1:PDRIVE[1]
5 -IOB1:DCI_MODE[0]
6 -IOB1:PULL[2]
7 IOB1:PDRIVE[3]IOB1:NDRIVE[3]
8 -IOB1:VREF
9 -IOB1:DCI_MODE[3]
10 -IOB1:NDRIVE[0]
11 -IOB1:DISABLE_GTS
12 -IOB1:OUTPUT_MISC[0]
13 -~IOB1:DCIUPDATEMODE_ASREQUIRED
14 -IOB1:OUTPUT_DIFF[1]
15 -IOB1:OUTPUT_DIFF[0]
16 -IOB1:OUTPUT_MISC[1]
17 -IOB1:VR
18 -IOB1:IBUF_MODE[0]
19 -IOB1:IBUF_MODE[1]
20 IOB1:SLEW[0]~IOB1:NDRIVE[2]
21 -IOB1:SLEW[1]
22 --
23 -IOB1:IBUF_MODE[2]
24 -~IOB1:PDRIVE[0]
25 -IOB1:DCI_MODE[1]
26 ~IOB1:PDRIVE[2]IOB1:SLEW[2]
27 -IOB1:SLEW[3]
28 -IOB1:DCI_MODE[2]
29 -IOB1:OUTPUT_ENABLE[0]
30 -IOB1:SLEW[4]
31 -IOB1:OUTPUT_ENABLE[1]
32 -IOB0:OUTPUT_ENABLE[0]
33 -IOB0:SLEW[0]
34 -IOB0:OUTPUT_ENABLE[1]
35 -IOB0:DCI_MODE[2]
36 -IOB0:SLEW[1]
37 -~IOB0:PDRIVE[2]
38 -IOB0:SLEW[2]
39 IOB0:DCI_MODE[1]~IOB0:PDRIVE[0]
40 -IOB0:IBUF_MODE[2]
41 -~IOB0:NDRIVE[2]
42 -IOB0:SLEW[3]
43 -IOB0:SLEW[4]
44 --
45 -IOB0:IBUF_MODE[1]
46 IOB0:VRIOB0:IBUF_MODE[0]
47 -IOB0:OUTPUT_MISC[1]
48 -IOB1:OUTPUT_DIFF[2]
49 --
50 --
51 -~IOB0:DCIUPDATEMODE_ASREQUIRED
52 IOB0:DISABLE_GTSIOB0:OUTPUT_MISC[0]
53 -IOB0:NDRIVE[0]
54 -IOB0:DCI_MODE[3]
55 -IOB0:VREF
56 -IOB0:NDRIVE[3]
57 -IOB0:PDRIVE[3]
58 IOB0:NDRIVE[1]IOB0:PULL[2]
59 -IOB0:PULL[1]
60 --
61 -IOB0:PDRIVE[1]
62 -IOB0:DCI_MODE[0]
63 -IOB0:PULL[0]
IOB0:SLEW[0, 1, 43][0, 1, 42][0, 1, 38][0, 1, 36][0, 1, 33]
IOB1:SLEW[0, 1, 30][0, 1, 27][0, 1, 26][0, 1, 21][0, 0, 20]
Non-inverted[4][3][2][1][0]
IOB0:DISABLE_GTS[0, 0, 52]
IOB0:VR[0, 0, 46]
IOB0:VREF[0, 1, 55]
IOB1:DISABLE_GTS[0, 1, 11]
IOB1:VR[0, 1, 17]
IOB1:VREF[0, 1, 8]
Non-inverted[0]
IOB0:PULL[0, 1, 58][0, 1, 59][0, 1, 63]
IOB1:PULL[0, 1, 6][0, 1, 1][0, 1, 3]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DCI_MODE[0, 1, 54][0, 1, 35][0, 0, 39][0, 1, 62]
IOB1:DCI_MODE[0, 1, 9][0, 1, 28][0, 1, 25][0, 1, 5]
NONE0000
OUTPUT0001
OUTPUT_HALF0010
TERM_SPLIT0100
TERM_VCC1011
IOB0:NDRIVE[0, 1, 56][0, 1, 41][0, 0, 58][0, 1, 53]
IOB1:NDRIVE[0, 1, 7][0, 1, 20][0, 1, 2][0, 1, 10]
Mixed inversion[3]~[2][1][0]
IOB0:OUTPUT_ENABLE[0, 1, 34][0, 1, 32]
IOB0:OUTPUT_MISC[0, 1, 47][0, 1, 52]
IOB1:OUTPUT_ENABLE[0, 1, 31][0, 1, 29]
IOB1:OUTPUT_MISC[0, 1, 16][0, 1, 12]
Non-inverted[1][0]
IOB0:DCIUPDATEMODE_ASREQUIRED[0, 1, 51]
IOB1:DCIUPDATEMODE_ASREQUIRED[0, 1, 13]
Inverted~[0]
IOB1:OUTPUT_DIFF[0, 1, 48][0, 1, 14][0, 1, 15]
Non-inverted[2][1][0]
IOB0:IBUF_MODE[0, 1, 40][0, 1, 45][0, 1, 46]
IOB1:IBUF_MODE[0, 1, 23][0, 1, 19][0, 1, 18]
NONE000
VREF011
DIFF101
CMOS111
IOB0:PDRIVE[0, 1, 57][0, 1, 37][0, 1, 61][0, 1, 39]
IOB1:PDRIVE[0, 0, 7][0, 0, 26][0, 1, 4][0, 1, 24]
Mixed inversion[3]~[2][1]~[0]

IOBS.S3.B2

IOBS.S3.B2 bittile 0
RowColumn
0123456789101112131415161718
0 -IOB2:OUTPUT_DIFF[0]IOB2:DISABLE_GTSIOB2:PDRIVE[3]IOB2:NDRIVE[1]IOB3:NDRIVE[1]IOB3:PDRIVE[3]IOB3:DISABLE_GTS--IOB3:SLEW[2]~IOB3:PDRIVE[0]IOB4:SLEW[1]IOB3:OUTPUT_ENABLE[1]IOB4:SLEW[3]-IOB4:OUTPUT_MISC[0]IOB4:VREFIOB4:PDRIVE[1]
1 --IOB2:NDRIVE[0]IOB2:PULL[2]IOB2:PULL[1]IOB3:PULL[0]IOB3:NDRIVE[3]IOB3:OUTPUT_MISC[0]IOB3:OUTPUT_MISC[1]IOB3:SLEW[0]IOB3:DCI_MODE[2]IOB3:DCI_MODE[1]IOB4:DCI_MODE[1]IOB4:DCI_MODE[2]-IOB4:OUTPUT_MISC[1]IOB4:DISABLE_GTSIOB4:NDRIVE[3]IOB4:PULL[0]
2 -IOB2:OUTPUT_DIFF[1]IOB2:DCI_MODE[3]IOB2:DCI_MODE[0]-IOB3:PDRIVE[1]IOB3:VREF~IOB3:DCIUPDATEMODE_ASREQUIRED-IOB3:IBUF_MODE[2]IOB3:SLEW[3]~IOB3:PDRIVE[2]~IOB4:PDRIVE[0]IOB4:OUTPUT_ENABLE[1]IOB4:IBUF_MODE[1]IOB4:OUTPUT_DIFF[0]IOB4:NDRIVE[0]IOB4:PDRIVE[3]IOB4:NDRIVE[1]
3 -~IOB2:DCIUPDATEMODE_ASREQUIRED-IOB2:PDRIVE[1]-IOB3:PULL[2]IOB3:DCI_MODE[3]-IOB3:IBUF_MODE[0]IOB3:SLEW[1]IOB4:SLEW[0]IOB3:SLEW[4]IOB4:IBUF_MODE[2]~IOB4:PDRIVE[2]IOB4:IBUF_MODE[0]-IOB4:DCI_MODE[3]IOB4:PULL[2]IOB4:PULL[1]
4 -IOB2:OUTPUT_MISC[0]IOB2:NDRIVE[3]IOB2:PULL[0]IOB3:PULL[1]IOB3:DCI_MODE[0]IOB3:NDRIVE[0]IOB4:OUTPUT_DIFF[2]IOB3:IBUF_MODE[1]~IOB3:NDRIVE[2]IOB4:OUTPUT_ENABLE[0]IOB3:OUTPUT_ENABLE[0]~IOB4:NDRIVE[2]IOB4:SLEW[2]IOB4:SLEW[4]IOB4:OUTPUT_DIFF[1]~IOB4:DCIUPDATEMODE_ASREQUIREDIOB4:DCI_MODE[0]-
IOBS.S3.B2 bittile 1
RowColumn
0123456789101112131415161718
0 -IOB0:OUTPUT_ENABLE[0]~IOB0:PDRIVE[2]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[1]-IOB0:DCI_MODE[3]IOB0:DCI_MODE[0]IOB0:PULL[1]IOB1:PULL[2]~IOB1:DCIUPDATEMODE_ASREQUIRED-IOB1:SLEW[0]IOB1:VRIOB1:SLEW[2]IOB1:SLEW[4]IOB2:DCI_MODE[2]~IOB2:PDRIVE[0]IOB2:IBUF_MODE[1]
1 -IOB0:SLEW[0]IOB0:SLEW[2]IOB0:SLEW[3]-~IOB0:DCIUPDATEMODE_ASREQUIREDIOB0:VREFIOB0:PDRIVE[1]-IOB1:PDRIVE[1]-IOB1:DCI_MODE[3]~IOB1:NDRIVE[2]IOB1:IBUF_MODE[0]~IOB1:PDRIVE[2]IOB2:OUTPUT_ENABLE[0]IOB2:SLEW[1]IOB2:IBUF_MODE[2]IOB2:IBUF_MODE[0]
2 -IOB0:OUTPUT_ENABLE[1]IOB0:DCI_MODE[1]IOB0:SLEW[4]IOB0:OUTPUT_MISC[1]IOB0:OUTPUT_MISC[0]IOB0:NDRIVE[3]IOB0:PULL[0]-IOB1:DCI_MODE[0]-IOB1:NDRIVE[0]IOB1:IBUF_MODE[2]IOB1:IBUF_MODE[1]IOB1:SLEW[3]IOB2:SLEW[0]~IOB2:PDRIVE[2]~IOB2:NDRIVE[2]-
3 -IOB0:DCI_MODE[2]~IOB0:PDRIVE[0]--IOB0:DISABLE_GTSIOB0:PDRIVE[3]IOB1:PULL[0]IOB1:PULL[1]IOB1:PDRIVE[3]IOB2:OUTPUT_DIFF[2]IOB1:DISABLE_GTS~IOB1:PDRIVE[0]-IOB1:DCI_MODE[2]IOB2:OUTPUT_ENABLE[1]IOB2:SLEW[2]IOB2:SLEW[3]IOB2:VR
4 -IOB0:SLEW[1]IOB0:IBUF_MODE[2]IOB0:IBUF_MODE[0]-IOB0:NDRIVE[0]IOB0:PULL[2]IOB0:NDRIVE[1]IOB1:NDRIVE[1]IOB1:NDRIVE[3]IOB1:OUTPUT_MISC[1]IOB1:OUTPUT_MISC[0]IOB1:DCI_MODE[1]IOB1:SLEW[1]IOB1:OUTPUT_ENABLE[0]IOB1:OUTPUT_ENABLE[1]IOB2:DCI_MODE[1]IOB2:SLEW[4]IOB2:OUTPUT_MISC[1]
IOB2:OUTPUT_DIFF[1, 10, 3][0, 1, 2][0, 1, 0]
IOB4:OUTPUT_DIFF[0, 7, 4][0, 15, 4][0, 15, 2]
Non-inverted[2][1][0]
IOB0:DCIUPDATEMODE_ASREQUIRED[1, 5, 1]
IOB1:DCIUPDATEMODE_ASREQUIRED[1, 10, 0]
IOB2:DCIUPDATEMODE_ASREQUIRED[0, 1, 3]
IOB3:DCIUPDATEMODE_ASREQUIRED[0, 7, 2]
IOB4:DCIUPDATEMODE_ASREQUIRED[0, 16, 4]
Inverted~[0]
IOB0:OUTPUT_ENABLE[1, 1, 2][1, 1, 0]
IOB0:OUTPUT_MISC[1, 4, 2][1, 5, 2]
IOB1:OUTPUT_ENABLE[1, 15, 4][1, 14, 4]
IOB1:OUTPUT_MISC[1, 10, 4][1, 11, 4]
IOB2:OUTPUT_ENABLE[1, 15, 3][1, 15, 1]
IOB2:OUTPUT_MISC[1, 18, 4][0, 1, 4]
IOB3:OUTPUT_ENABLE[0, 13, 0][0, 11, 4]
IOB3:OUTPUT_MISC[0, 8, 1][0, 7, 1]
IOB4:OUTPUT_ENABLE[0, 13, 2][0, 10, 4]
IOB4:OUTPUT_MISC[0, 15, 1][0, 16, 0]
Non-inverted[1][0]
IOB0:DISABLE_GTS[1, 5, 3]
IOB0:VREF[1, 6, 1]
IOB1:DISABLE_GTS[1, 11, 3]
IOB1:VR[1, 13, 0]
IOB2:DISABLE_GTS[0, 2, 0]
IOB2:VR[1, 18, 3]
IOB3:DISABLE_GTS[0, 7, 0]
IOB3:VREF[0, 6, 2]
IOB4:DISABLE_GTS[0, 16, 1]
IOB4:VREF[0, 17, 0]
Non-inverted[0]
IOB0:NDRIVE[1, 6, 2][1, 3, 0][1, 7, 4][1, 5, 4]
IOB1:NDRIVE[1, 9, 4][1, 12, 1][1, 8, 4][1, 11, 2]
IOB2:NDRIVE[0, 2, 4][1, 17, 2][0, 4, 0][0, 2, 1]
IOB3:NDRIVE[0, 6, 1][0, 9, 4][0, 5, 0][0, 6, 4]
IOB4:NDRIVE[0, 17, 1][0, 12, 4][0, 18, 2][0, 16, 2]
Mixed inversion[3]~[2][1][0]
IOB0:DCI_MODE[1, 6, 0][1, 1, 3][1, 2, 2][1, 7, 0]
IOB1:DCI_MODE[1, 11, 1][1, 14, 3][1, 12, 4][1, 9, 2]
IOB2:DCI_MODE[0, 2, 2][1, 16, 0][1, 16, 4][0, 3, 2]
IOB3:DCI_MODE[0, 6, 3][0, 10, 1][0, 11, 1][0, 5, 4]
IOB4:DCI_MODE[0, 16, 3][0, 13, 1][0, 12, 1][0, 17, 4]
NONE0000
OUTPUT0001
OUTPUT_HALF0010
TERM_SPLIT0100
TERM_VCC1011
IOB0:PULL[1, 6, 4][1, 8, 0][1, 7, 2]
IOB1:PULL[1, 9, 0][1, 8, 3][1, 7, 3]
IOB2:PULL[0, 3, 1][0, 4, 1][0, 3, 4]
IOB3:PULL[0, 5, 3][0, 4, 4][0, 5, 1]
IOB4:PULL[0, 17, 3][0, 18, 3][0, 18, 1]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB1:IBUF_MODE[1, 12, 2][1, 13, 2][1, 13, 1]
IOB2:IBUF_MODE[1, 17, 1][1, 18, 0][1, 18, 1]
IOB3:IBUF_MODE[0, 9, 2][0, 8, 4][0, 8, 3]
IOB4:IBUF_MODE[0, 12, 3][0, 14, 2][0, 14, 3]
NONE000
VREF011
DIFF101
CMOS111
IOB0:SLEW[1, 3, 2][1, 3, 1][1, 2, 1][1, 1, 4][1, 1, 1]
IOB1:SLEW[1, 15, 0][1, 14, 2][1, 14, 0][1, 13, 4][1, 12, 0]
IOB2:SLEW[1, 17, 4][1, 17, 3][1, 16, 3][1, 16, 1][1, 15, 2]
IOB3:SLEW[0, 11, 3][0, 10, 2][0, 10, 0][0, 9, 3][0, 9, 1]
IOB4:SLEW[0, 14, 4][0, 14, 0][0, 13, 4][0, 12, 0][0, 10, 3]
Non-inverted[4][3][2][1][0]
IOB0:PDRIVE[1, 6, 3][1, 2, 0][1, 7, 1][1, 2, 3]
IOB1:PDRIVE[1, 9, 3][1, 14, 1][1, 9, 1][1, 12, 3]
IOB2:PDRIVE[0, 3, 0][1, 16, 2][0, 3, 3][1, 17, 0]
IOB3:PDRIVE[0, 6, 0][0, 11, 2][0, 5, 2][0, 11, 0]
IOB4:PDRIVE[0, 17, 2][0, 13, 3][0, 18, 0][0, 12, 2]
Mixed inversion[3]~[2][1]~[0]
IOB0:IBUF_MODE[1, 2, 4][1, 4, 0][1, 3, 4]
NONE000
VREF011
CMOS111

IOBS.S3.L1

IOBS.S3.L1 bittile 0
RowColumn
01
0 --
1 IOB0:PULL[1]-
2 IOB0:NDRIVE[1]-
3 IOB0:PULL[0]-
4 IOB0:PDRIVE[1]-
5 IOB0:DCI_MODE[0]-
6 IOB0:PULL[2]-
7 IOB0:NDRIVE[3]IOB0:PDRIVE[3]
8 IOB0:VREF-
9 IOB0:DCI_MODE[3]-
10 IOB0:NDRIVE[0]-
11 IOB0:DISABLE_GTS-
12 IOB0:OUTPUT_MISC[0]-
13 ~IOB0:DCIUPDATEMODE_ASREQUIRED-
14 --
15 IOB1:OUTPUT_DIFF[2]-
16 IOB0:OUTPUT_MISC[1]-
17 IOB0:VR-
18 IOB0:IBUF_MODE[0]-
19 IOB0:IBUF_MODE[1]-
20 ~IOB0:NDRIVE[2]IOB0:SLEW[4]
21 IOB0:SLEW[0]-
22 --
23 IOB0:IBUF_MODE[2]-
24 ~IOB0:PDRIVE[0]-
25 IOB0:DCI_MODE[1]-
26 IOB0:SLEW[1]~IOB0:PDRIVE[2]
27 IOB0:SLEW[2]-
28 IOB0:DCI_MODE[2]-
29 IOB0:OUTPUT_ENABLE[0]-
30 IOB0:SLEW[3]-
31 IOB0:OUTPUT_ENABLE[1]-
32 IOB1:OUTPUT_ENABLE[0]-
33 IOB1:SLEW[0]-
34 IOB1:OUTPUT_ENABLE[1]-
35 IOB1:DCI_MODE[2]-
36 IOB1:SLEW[1]-
37 ~IOB1:PDRIVE[2]-
38 IOB1:SLEW[2]-
39 ~IOB1:PDRIVE[0]IOB1:DCI_MODE[1]
40 IOB1:IBUF_MODE[2]-
41 ~IOB1:NDRIVE[2]-
42 IOB1:SLEW[3]-
43 IOB1:SLEW[4]-
44 --
45 IOB1:IBUF_MODE[1]-
46 IOB1:IBUF_MODE[0]IOB1:VR
47 IOB1:OUTPUT_MISC[1]-
48 IOB1:OUTPUT_DIFF[0]-
49 --
50 IOB1:OUTPUT_DIFF[1]-
51 ~IOB1:DCIUPDATEMODE_ASREQUIRED-
52 IOB1:OUTPUT_MISC[0]IOB1:DISABLE_GTS
53 IOB1:NDRIVE[0]-
54 IOB1:DCI_MODE[3]-
55 IOB1:VREF-
56 IOB1:NDRIVE[3]-
57 IOB1:PDRIVE[3]-
58 IOB1:PULL[2]IOB1:NDRIVE[1]
59 IOB1:PULL[1]-
60 --
61 IOB1:PDRIVE[1]-
62 IOB1:DCI_MODE[0]-
63 IOB1:PULL[0]-
IOB0:PULL[0, 0, 6][0, 0, 1][0, 0, 3]
IOB1:PULL[0, 0, 58][0, 0, 59][0, 0, 63]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DCI_MODE[0, 0, 9][0, 0, 28][0, 0, 25][0, 0, 5]
IOB1:DCI_MODE[0, 0, 54][0, 0, 35][0, 1, 39][0, 0, 62]
NONE0000
OUTPUT0001
OUTPUT_HALF0010
TERM_SPLIT0100
TERM_VCC1011
IOB0:DISABLE_GTS[0, 0, 11]
IOB0:VR[0, 0, 17]
IOB0:VREF[0, 0, 8]
IOB1:DISABLE_GTS[0, 1, 52]
IOB1:VR[0, 1, 46]
IOB1:VREF[0, 0, 55]
Non-inverted[0]
IOB0:NDRIVE[0, 0, 7][0, 0, 20][0, 0, 2][0, 0, 10]
IOB1:NDRIVE[0, 0, 56][0, 0, 41][0, 1, 58][0, 0, 53]
Mixed inversion[3]~[2][1][0]
IOB0:OUTPUT_ENABLE[0, 0, 31][0, 0, 29]
IOB0:OUTPUT_MISC[0, 0, 16][0, 0, 12]
IOB1:OUTPUT_ENABLE[0, 0, 34][0, 0, 32]
IOB1:OUTPUT_MISC[0, 0, 47][0, 0, 52]
Non-inverted[1][0]
IOB0:DCIUPDATEMODE_ASREQUIRED[0, 0, 13]
IOB1:DCIUPDATEMODE_ASREQUIRED[0, 0, 51]
Inverted~[0]
IOB0:IBUF_MODE[0, 0, 23][0, 0, 19][0, 0, 18]
IOB1:IBUF_MODE[0, 0, 40][0, 0, 45][0, 0, 46]
NONE000
VREF011
DIFF101
CMOS111
IOB0:SLEW[0, 1, 20][0, 0, 30][0, 0, 27][0, 0, 26][0, 0, 21]
IOB1:SLEW[0, 0, 43][0, 0, 42][0, 0, 38][0, 0, 36][0, 0, 33]
Non-inverted[4][3][2][1][0]
IOB0:PDRIVE[0, 1, 7][0, 1, 26][0, 0, 4][0, 0, 24]
IOB1:PDRIVE[0, 0, 57][0, 0, 37][0, 0, 61][0, 0, 39]
Mixed inversion[3]~[2][1]~[0]
IOB1:OUTPUT_DIFF[0, 0, 15][0, 0, 50][0, 0, 48]
Non-inverted[2][1][0]

I/O buffers — Spartan 3E

Todo

document

NameIOSTD:S3E:PDRIVEIOSTD:S3E:NDRIVE
[3][2][1][0][3][2][1][0]
BLVDS_2511111111
HSTL_III_1811111100
HSTL_I_1811110100
LVCMOS12.211000001
LVCMOS15.201110001
LVCMOS15.410100010
LVCMOS15.611110011
LVCMOS18.201000001
LVCMOS18.410000010
LVCMOS18.610110011
LVCMOS18.811110100
LVCMOS25.1211100110
LVCMOS25.200110001
LVCMOS25.401010010
LVCMOS25.610000011
LVCMOS25.810100100
LVCMOS33.1210110110
LVCMOS33.1611101000
LVCMOS33.200100001
LVCMOS33.401000010
LVCMOS33.601100011
LVCMOS33.810000100
LVTTL.1210000110
LVTTL.1610101000
LVTTL.200100001
LVTTL.400110010
LVTTL.601000011
LVTTL.801110100
OFF00000000
PCI33_311001001
PCI66_311001001
PCIX11111111
SSTL18_I11110100
SSTL2_I01110011
NameIOSTD:S3E:SLEW
[5][4][3][2][1][0]
BLVDS_25000000
HSTL_III_18111111
HSTL_I_18111111
LVCMOS12.FAST111111
LVCMOS12.SLOW000000
LVCMOS15.FAST111111
LVCMOS15.SLOW000000
LVCMOS18.FAST111111
LVCMOS18.SLOW000000
LVCMOS25.FAST111111
LVCMOS25.SLOW000000
LVCMOS33.FAST111111
LVCMOS33.SLOW000000
LVTTL.FAST111111
LVTTL.SLOW000000
PCI33_3000001
PCI66_3000001
PCIX000001
SSTL18_I111111
SSTL2_I111111
NameIOSTD:S3E:OUTPUT_MISC
[0]
BLVDS_250
HSTL_III_181
HSTL_I_181
LVCMOS120
LVCMOS150
LVCMOS180
LVCMOS250
LVCMOS330
LVTTL0
PCI33_30
PCI66_30
PCIX0
SSTL18_I0
SSTL2_I0
NameIOSTD:S3E:OUTPUT_DIFF
[1][0]
LVDS_2511
MINI_LVDS_2511
OFF00
RSDS_2511
TERM01

IOBS.S3E.T1

IOBS.S3E.T1 bittile 0
RowColumn
0123456789101112131415161718
0 ----------IOB0:DELAY_COMMON-IOB0:SLEW[1]IOB0:OUTPUT_ENABLE[1]IOB0:OUTPUT_MISC---~IOB0:PDRIVE[1]
1 ----------IOB0:I_DELAY[2]--IOB0:SLEW[3]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[0]-IOB0:NDRIVE[3]IOB0:PULL[0]
2 ----------IOB0:I_DELAY[1]-IOB0:PDRIVE[0]-IOB0:IBUF_MODE[1]-IOB0:NDRIVE[0]IOB0:PULL[2]IOB0:NDRIVE[1]
3 ----------IOB0:IFF_DELAY[0]IOB0:I_DELAY[0]IOB0:IBUF_MODE[2]IOB0:SLEW[4]---~IOB0:PDRIVE[3]IOB0:PULL[1]
4 ----------IOB0:OUTPUT_ENABLE[0]IOB0:IFF_DELAY[1]IOB0:SLEW[2]IOB0:PDRIVE[2]IOB0:SLEW[5]-IOB0:SLEW[0]--
IOB0:DELAY_COMMON[0, 10, 0]
IOB0:OUTPUT_MISC[0, 14, 0]
Non-inverted[0]
IOB0:IFF_DELAY[0, 11, 4][0, 10, 3]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:OUTPUT_ENABLE[0, 13, 0][0, 10, 4]
Non-inverted[1][0]
IOB0:I_DELAY[0, 10, 1][0, 10, 2][0, 11, 3]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:PDRIVE[0, 17, 3][0, 13, 4][0, 18, 0][0, 12, 2]
Mixed inversion~[3][2]~[1][0]
IOB0:IBUF_MODE[0, 12, 3][0, 14, 2][0, 15, 1]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB0:NDRIVE[0, 17, 1][0, 14, 1][0, 18, 2][0, 16, 2]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[0, 14, 4][0, 13, 3][0, 13, 1][0, 12, 4][0, 12, 0][0, 16, 4]
Non-inverted[5][4][3][2][1][0]
IOB0:PULL[0, 17, 2][0, 18, 3][0, 18, 1]
PULLDOWN000
NONE001
PULLUP011
KEEPER101

IOBS.S3E.T2

IOBS.S3E.T2 bittile 0
RowColumn
0123456789101112131415161718
0 ---IOB1:IFF_DELAY[1]-------IOB0:I_DELAY[0]IOB0:SLEW[1]IOB0:OUTPUT_ENABLE[1]IOB0:OUTPUT_MISC---~IOB0:PDRIVE[1]
1 ---IOB1:I_DELAY[0]-------IOB0:I_DELAY[2]-IOB0:SLEW[3]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[0]IOB1:OUTPUT_DIFF_GROUP[0]IOB0:NDRIVE[3]IOB0:PULL[0]
2 ---IOB1:I_DELAY[2]-------IOB0:IFF_DELAY[1]IOB0:PDRIVE[0]-IOB0:IBUF_MODE[1]-IOB0:NDRIVE[0]IOB0:PULL[2]IOB0:NDRIVE[1]
3 ---IOB1:IFF_DELAY[0]-----IOB0:I_DELAY[1]--IOB0:IBUF_MODE[2]IOB0:SLEW[4]---~IOB0:PDRIVE[3]IOB0:PULL[1]
4 ---IOB1:I_DELAY[1]--IOB1:DELAY_COMMONIOB0:DELAY_COMMON-IOB0:IFF_DELAY[0]IOB0:OUTPUT_ENABLE[0]-IOB0:SLEW[2]IOB0:PDRIVE[2]IOB0:SLEW[5]-IOB0:SLEW[0]--
IOBS.S3E.T2 bittile 1
RowColumn
0123456789101112131415161718
0 ----------IOB2:I_DELAY[0]IOB2:PULL[2]-IOB2:I_DELAY[2]IOB1:OUTPUT_DIFF_GROUP[1]IOB1:OUTPUT_MISCIOB1:IBUF_MODE[1]IOB1:PDRIVE[0]IOB1:SLEW[4]
1 ---------IOB2:IBUF_MODE[1]IOB2:PULL[1]IOB2:ENABLEIOB1:PULL[2]IOB1:NDRIVE[1]IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF[1]~IOB1:NDRIVE[2]IOB1:IBUF_MODE[2]IOB1:OUTPUT_ENABLE[0]
2 -------IOB2:DELAY_COMMON--IOB1:PULL[1]--~IOB1:PDRIVE[1]-IOB1:IBUF_MODE[0]--IOB1:SLEW[5]
3 -------IOB2:I_DELAY[1]IOB2:IFF_DELAY[0]IOB2:IBUF_MODE[0]-IOB2:PULL[0]~IOB1:PDRIVE[3]-IOB1:SLEW[0]IOB1:OUTPUT_DIFF[0]IOB1:SLEW[1]IOB1:SLEW[3]-
4 ---------IOB2:IBUF_MODE[2]-IOB2:IFF_DELAY[1]IOB1:NDRIVE[3]IOB1:PULL[0]--IOB1:SLEW[2]IOB1:PDRIVE[2]IOB1:OUTPUT_ENABLE[1]
IOB0:I_DELAY[0, 11, 1][0, 9, 3][0, 11, 0]
IOB1:I_DELAY[0, 3, 2][0, 3, 4][0, 3, 1]
IOB2:I_DELAY[1, 13, 0][1, 7, 3][1, 10, 0]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:IFF_DELAY[0, 11, 2][0, 9, 4]
IOB1:IFF_DELAY[0, 3, 0][0, 3, 3]
IOB2:IFF_DELAY[1, 11, 4][1, 8, 3]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:DELAY_COMMON[0, 7, 4]
IOB0:OUTPUT_MISC[0, 14, 0]
IOB1:DELAY_COMMON[0, 6, 4]
IOB1:OUTPUT_MISC[1, 15, 0]
IOB2:DELAY_COMMON[1, 7, 2]
IOB2:ENABLE[1, 11, 1]
Non-inverted[0]
IOB0:OUTPUT_ENABLE[0, 13, 0][0, 10, 4]
IOB1:OUTPUT_DIFF[1, 15, 1][1, 15, 3]
IOB1:OUTPUT_DIFF_GROUP[1, 14, 0][0, 16, 1]
IOB1:OUTPUT_ENABLE[1, 18, 4][1, 18, 1]
Non-inverted[1][0]
IOB0:PDRIVE[0, 17, 3][0, 13, 4][0, 18, 0][0, 12, 2]
IOB1:PDRIVE[1, 12, 3][1, 17, 4][1, 13, 2][1, 17, 0]
Mixed inversion~[3][2]~[1][0]
IOB0:IBUF_MODE[0, 12, 3][0, 14, 2][0, 15, 1]
IOB1:IBUF_MODE[1, 17, 1][1, 16, 0][1, 15, 2]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:NDRIVE[0, 17, 1][0, 14, 1][0, 18, 2][0, 16, 2]
IOB1:NDRIVE[1, 12, 4][1, 16, 1][1, 13, 1][1, 14, 1]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[0, 14, 4][0, 13, 3][0, 13, 1][0, 12, 4][0, 12, 0][0, 16, 4]
IOB1:SLEW[1, 18, 2][1, 18, 0][1, 17, 3][1, 16, 4][1, 16, 3][1, 14, 3]
Non-inverted[5][4][3][2][1][0]
IOB0:PULL[0, 17, 2][0, 18, 3][0, 18, 1]
IOB1:PULL[1, 12, 1][1, 10, 2][1, 13, 4]
IOB2:PULL[1, 11, 0][1, 10, 1][1, 11, 3]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[1, 9, 4][1, 9, 1][1, 9, 3]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.T3

IOBS.S3E.T3 bittile 0
RowColumn
0123456789101112131415161718
0 ---IOB1:IFF_DELAY[1]-------IOB0:I_DELAY[0]IOB0:SLEW[1]IOB0:OUTPUT_ENABLE[1]IOB0:OUTPUT_MISC---~IOB0:PDRIVE[1]
1 ---IOB1:I_DELAY[0]-------IOB0:I_DELAY[2]-IOB0:SLEW[3]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[0]IOB1:OUTPUT_DIFF_GROUP[0]IOB0:NDRIVE[3]IOB0:PULL[0]
2 ---IOB1:I_DELAY[2]-------IOB0:IFF_DELAY[1]IOB0:PDRIVE[0]-IOB0:IBUF_MODE[1]-IOB0:NDRIVE[0]IOB0:PULL[2]IOB0:NDRIVE[1]
3 ---IOB1:IFF_DELAY[0]-----IOB0:I_DELAY[1]--IOB0:IBUF_MODE[2]IOB0:SLEW[4]---~IOB0:PDRIVE[3]IOB0:PULL[1]
4 ---IOB1:I_DELAY[1]--IOB1:DELAY_COMMONIOB0:DELAY_COMMON-IOB0:IFF_DELAY[0]IOB0:OUTPUT_ENABLE[0]-IOB0:SLEW[2]IOB0:PDRIVE[2]IOB0:SLEW[5]-IOB0:SLEW[0]--
IOBS.S3E.T3 bittile 1
RowColumn
0123456789101112131415161718
0 ----------IOB2:I_DELAY[0]IOB2:PULL[2]-IOB2:I_DELAY[2]IOB1:OUTPUT_DIFF_GROUP[1]IOB1:OUTPUT_MISCIOB1:IBUF_MODE[1]IOB1:PDRIVE[0]IOB1:SLEW[4]
1 ---------IOB2:IBUF_MODE[1]IOB2:PULL[1]IOB2:ENABLEIOB1:PULL[2]IOB1:NDRIVE[1]IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF[1]~IOB1:NDRIVE[2]IOB1:IBUF_MODE[2]IOB1:OUTPUT_ENABLE[0]
2 -------IOB2:DELAY_COMMON--IOB1:PULL[1]--~IOB1:PDRIVE[1]-IOB1:IBUF_MODE[0]--IOB1:SLEW[5]
3 -------IOB2:I_DELAY[1]IOB2:IFF_DELAY[0]IOB2:IBUF_MODE[0]-IOB2:PULL[0]~IOB1:PDRIVE[3]-IOB1:SLEW[0]IOB1:OUTPUT_DIFF[0]IOB1:SLEW[1]IOB1:SLEW[3]-
4 ---------IOB2:IBUF_MODE[2]-IOB2:IFF_DELAY[1]IOB1:NDRIVE[3]IOB1:PULL[0]--IOB1:SLEW[2]IOB1:PDRIVE[2]IOB1:OUTPUT_ENABLE[1]
IOBS.S3E.T3 bittile 2
RowColumn
0123456789101112131415161718
0 -IOB4:PULL[1]-IOB4:SLEW[0]-IOB4:SLEW[1]IOB4:SLEW[2]IOB4:SLEW[5]IOB4:IFF_DELAY[0]IOB4:IFF_DELAY[1]IOB3:OUTPUT_ENABLE[0]-IOB3:SLEW[1]-IOB3:OUTPUT_MISC-IOB3:SLEW[0]IOB3:PULL[1]-
1 -IOB4:PULL[0]IOB4:NDRIVE[1]---IOB4:PDRIVE[0]IOB4:IBUF_MODE[2]IOB4:I_DELAY[2]IOB4:DELAY_COMMON--IOB3:IBUF_MODE[2]IOB3:SLEW[3]~IOB3:NDRIVE[2]--IOB3:PULL[0]IOB3:NDRIVE[1]
2 --~IOB4:PDRIVE[1]IOB4:OUTPUT_DIFF_GROUP[0]-IOB4:IBUF_MODE[1]IOB4:SLEW[3]-IOB4:I_DELAY[1]IOB3:DELAY_COMMON-IOB3:I_DELAY[0]IOB3:PDRIVE[0]IOB3:OUTPUT_ENABLE[1]IOB3:IBUF_MODE[1]-IOB3:NDRIVE[0]-~IOB3:PDRIVE[1]
3 -~IOB4:PDRIVE[3]IOB4:PULL[2]IOB4:OUTPUT_DIFF[0]IOB4:IBUF_MODE[0]IOB4:OUTPUT_ENABLE[0]~IOB4:NDRIVE[2]-IOB4:I_DELAY[0]IOB3:IFF_DELAY[1]-IOB3:I_DELAY[1]-IOB3:SLEW[4]-IOB3:IBUF_MODE[0]IOB4:OUTPUT_DIFF_GROUP[1]~IOB3:PDRIVE[3]IOB3:PULL[2]
4 --IOB4:NDRIVE[3]IOB4:OUTPUT_DIFF[1]IOB4:NDRIVE[0]IOB4:OUTPUT_ENABLE[1]IOB4:SLEW[4]IOB4:PDRIVE[2]IOB4:OUTPUT_MISCIOB3:IFF_DELAY[0]-IOB3:I_DELAY[2]IOB3:SLEW[2]IOB3:PDRIVE[2]IOB3:SLEW[5]--IOB3:VREFIOB3:NDRIVE[3]
IOB0:I_DELAY[0, 11, 1][0, 9, 3][0, 11, 0]
IOB1:I_DELAY[0, 3, 2][0, 3, 4][0, 3, 1]
IOB2:I_DELAY[1, 13, 0][1, 7, 3][1, 10, 0]
IOB3:I_DELAY[2, 11, 4][2, 11, 3][2, 11, 2]
IOB4:I_DELAY[2, 8, 1][2, 8, 2][2, 8, 3]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:IFF_DELAY[0, 11, 2][0, 9, 4]
IOB1:IFF_DELAY[0, 3, 0][0, 3, 3]
IOB2:IFF_DELAY[1, 11, 4][1, 8, 3]
IOB3:IFF_DELAY[2, 9, 3][2, 9, 4]
IOB4:IFF_DELAY[2, 9, 0][2, 8, 0]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:DELAY_COMMON[0, 7, 4]
IOB0:OUTPUT_MISC[0, 14, 0]
IOB1:DELAY_COMMON[0, 6, 4]
IOB1:OUTPUT_MISC[1, 15, 0]
IOB2:DELAY_COMMON[1, 7, 2]
IOB2:ENABLE[1, 11, 1]
IOB3:DELAY_COMMON[2, 9, 2]
IOB3:OUTPUT_MISC[2, 14, 0]
IOB3:VREF[2, 17, 4]
IOB4:DELAY_COMMON[2, 9, 1]
IOB4:OUTPUT_MISC[2, 8, 4]
Non-inverted[0]
IOB0:OUTPUT_ENABLE[0, 13, 0][0, 10, 4]
IOB1:OUTPUT_DIFF[1, 15, 1][1, 15, 3]
IOB1:OUTPUT_DIFF_GROUP[1, 14, 0][0, 16, 1]
IOB1:OUTPUT_ENABLE[1, 18, 4][1, 18, 1]
IOB3:OUTPUT_ENABLE[2, 13, 2][2, 10, 0]
IOB4:OUTPUT_DIFF[2, 3, 4][2, 3, 3]
IOB4:OUTPUT_DIFF_GROUP[2, 16, 3][2, 3, 2]
IOB4:OUTPUT_ENABLE[2, 5, 4][2, 5, 3]
Non-inverted[1][0]
IOB0:PDRIVE[0, 17, 3][0, 13, 4][0, 18, 0][0, 12, 2]
IOB1:PDRIVE[1, 12, 3][1, 17, 4][1, 13, 2][1, 17, 0]
IOB3:PDRIVE[2, 17, 3][2, 13, 4][2, 18, 2][2, 12, 2]
IOB4:PDRIVE[2, 1, 3][2, 7, 4][2, 2, 2][2, 6, 1]
Mixed inversion~[3][2]~[1][0]
IOB0:IBUF_MODE[0, 12, 3][0, 14, 2][0, 15, 1]
IOB1:IBUF_MODE[1, 17, 1][1, 16, 0][1, 15, 2]
IOB3:IBUF_MODE[2, 12, 1][2, 14, 2][2, 15, 3]
IOB4:IBUF_MODE[2, 7, 1][2, 5, 2][2, 4, 3]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:NDRIVE[0, 17, 1][0, 14, 1][0, 18, 2][0, 16, 2]
IOB1:NDRIVE[1, 12, 4][1, 16, 1][1, 13, 1][1, 14, 1]
IOB3:NDRIVE[2, 18, 4][2, 14, 1][2, 18, 1][2, 16, 2]
IOB4:NDRIVE[2, 2, 4][2, 6, 3][2, 2, 1][2, 4, 4]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[0, 14, 4][0, 13, 3][0, 13, 1][0, 12, 4][0, 12, 0][0, 16, 4]
IOB1:SLEW[1, 18, 2][1, 18, 0][1, 17, 3][1, 16, 4][1, 16, 3][1, 14, 3]
IOB3:SLEW[2, 14, 4][2, 13, 3][2, 13, 1][2, 12, 4][2, 12, 0][2, 16, 0]
IOB4:SLEW[2, 7, 0][2, 6, 4][2, 6, 2][2, 6, 0][2, 5, 0][2, 3, 0]
Non-inverted[5][4][3][2][1][0]
IOB0:PULL[0, 17, 2][0, 18, 3][0, 18, 1]
IOB1:PULL[1, 12, 1][1, 10, 2][1, 13, 4]
IOB2:PULL[1, 11, 0][1, 10, 1][1, 11, 3]
IOB3:PULL[2, 18, 3][2, 17, 0][2, 17, 1]
IOB4:PULL[2, 2, 3][2, 1, 0][2, 1, 1]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[1, 9, 4][1, 9, 1][1, 9, 3]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.T4

IOBS.S3E.T4 bittile 0
RowColumn
0123456789101112131415161718
0 -IOB1:I_DELAY[0]IOB1:IFF_DELAY[1]---IOB0:DELAY_COMMONIOB0:IFF_DELAY[0]---IOB0:OUTPUT_ENABLE[0]IOB0:SLEW[1]-IOB0:OUTPUT_MISC--IOB0:VREF~IOB0:PDRIVE[1]
1 -IOB1:DELAY_COMMON-----IOB0:I_DELAY[1]-----IOB0:SLEW[3]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[0]IOB1:OUTPUT_DIFF_GROUP[0]IOB0:NDRIVE[3]IOB0:PULL[0]
2 -IOB1:I_DELAY[2]-----IOB0:IFF_DELAY[1]----IOB0:PDRIVE[0]-IOB0:IBUF_MODE[1]-IOB0:NDRIVE[0]IOB0:PULL[2]IOB0:NDRIVE[1]
3 -IOB1:IFF_DELAY[0]-----IOB0:I_DELAY[0]----IOB0:IBUF_MODE[2]IOB0:SLEW[4]---~IOB0:PDRIVE[3]IOB0:PULL[1]
4 -IOB1:I_DELAY[1]-----IOB0:I_DELAY[2]---IOB0:OUTPUT_ENABLE[1]IOB0:SLEW[2]IOB0:PDRIVE[2]IOB0:SLEW[5]-IOB0:SLEW[0]--
IOBS.S3E.T4 bittile 1
RowColumn
0123456789101112131415161718
0 ---IOB2:SLEW[2]IOB2:IBUF_MODE[2]~IOB2:NDRIVE[2]--IOB2:I_DELAY[0]~IOB2:PDRIVE[3]IOB2:DELAY_COMMON~IOB2:PDRIVE[1]-IOB2:I_DELAY[2]IOB1:OUTPUT_DIFF_GROUP[1]IOB1:OUTPUT_MISCIOB1:IBUF_MODE[1]IOB1:PDRIVE[0]IOB1:SLEW[4]
1 --IOB2:OUTPUT_ENABLE[0]IOB2:PDRIVE[2]IOB2:SLEW[4]IOB2:OUTPUT_MISCIOB2:SLEW[0]-IOB2:IFF_DELAY[1]IOB2:NDRIVE[3]IOB2:I_DELAY[1]IOB2:PULL[0]IOB1:PULL[2]IOB1:NDRIVE[1]IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF[1]~IOB1:NDRIVE[2]IOB1:IBUF_MODE[2]IOB1:OUTPUT_ENABLE[0]
2 ---IOB2:SLEW[3]IOB2:SLEW[5]----IOB2:VREFIOB1:PULL[1]IOB2:NDRIVE[1]-~IOB1:PDRIVE[1]-IOB1:IBUF_MODE[0]--IOB1:SLEW[5]
3 --IOB2:SLEW[1]--IOB2:IBUF_MODE[0]IOB2:NDRIVE[0]--IOB2:PULL[2]-IOB2:PULL[1]~IOB1:PDRIVE[3]-IOB1:SLEW[0]IOB1:OUTPUT_DIFF[0]IOB1:SLEW[1]IOB1:SLEW[3]-
4 --IOB2:OUTPUT_ENABLE[1]IOB2:PDRIVE[0]IOB2:IBUF_MODE[1]-----IOB2:IFF_DELAY[0]-IOB1:NDRIVE[3]IOB1:PULL[0]--IOB1:SLEW[2]IOB1:PDRIVE[2]IOB1:OUTPUT_ENABLE[1]
IOBS.S3E.T4 bittile 2
RowColumn
0123456789101112131415161718
0 ---IOB4:IFF_DELAY[1]---IOB3:IFF_DELAY[0]----IOB3:SLEW[1]IOB3:OUTPUT_ENABLE[1]IOB3:OUTPUT_MISC--IOB3:VREF~IOB3:PDRIVE[1]
1 ---IOB4:I_DELAY[0]---IOB3:I_DELAY[1]-----IOB3:SLEW[3]~IOB3:NDRIVE[2]IOB3:IBUF_MODE[0]IOB4:OUTPUT_DIFF_GROUP[0]IOB3:NDRIVE[3]IOB3:PULL[0]
2 ---IOB4:I_DELAY[2]---IOB3:IFF_DELAY[1]----IOB3:PDRIVE[0]-IOB3:IBUF_MODE[1]-IOB3:NDRIVE[0]IOB3:PULL[2]IOB3:NDRIVE[1]
3 ---IOB4:IFF_DELAY[0]--IOB3:DELAY_COMMONIOB3:I_DELAY[0]----IOB3:IBUF_MODE[2]IOB3:SLEW[4]---~IOB3:PDRIVE[3]IOB3:PULL[1]
4 ---IOB4:I_DELAY[1]--IOB4:DELAY_COMMONIOB3:I_DELAY[2]--IOB3:OUTPUT_ENABLE[0]-IOB3:SLEW[2]IOB3:PDRIVE[2]IOB3:SLEW[5]-IOB3:SLEW[0]--
IOBS.S3E.T4 bittile 3
RowColumn
0123456789101112131415161718
0 -IOB6:PULL[2]IOB6:IBUF_MODE[2]IOB6:IFF_DELAY[1]---IOB5:IFF_DELAY[0]------IOB4:OUTPUT_DIFF_GROUP[1]IOB4:OUTPUT_MISCIOB4:IBUF_MODE[1]IOB4:PDRIVE[0]IOB4:SLEW[4]
1 -IOB6:ENABLEIOB6:IBUF_MODE[1]IOB6:I_DELAY[0]---IOB5:I_DELAY[1]---IOB5:PULL[2]IOB4:PULL[2]IOB4:NDRIVE[1]IOB4:NDRIVE[0]IOB4:OUTPUT_DIFF[1]~IOB4:NDRIVE[2]IOB4:IBUF_MODE[2]IOB4:OUTPUT_ENABLE[0]
2 ---IOB6:I_DELAY[2]-IOB5:IBUF_MODE[2]-IOB5:IFF_DELAY[1]--IOB4:PULL[1]IOB5:PULL[0]-~IOB4:PDRIVE[1]-IOB4:IBUF_MODE[0]--IOB4:SLEW[5]
3 --IOB6:PULL[1]IOB6:IFF_DELAY[0]-IOB5:IBUF_MODE[1]IOB5:DELAY_COMMONIOB5:I_DELAY[0]---IOB5:PULL[1]~IOB4:PDRIVE[3]-IOB4:SLEW[0]IOB4:OUTPUT_DIFF[0]IOB4:SLEW[1]IOB4:SLEW[3]-
4 -IOB6:IBUF_MODE[0]IOB6:PULL[0]IOB6:I_DELAY[1]-IOB5:IBUF_MODE[0]IOB6:DELAY_COMMONIOB5:I_DELAY[2]-IOB5:ENABLE--IOB4:NDRIVE[3]IOB4:PULL[0]--IOB4:SLEW[2]IOB4:PDRIVE[2]IOB4:OUTPUT_ENABLE[1]
IOB0:I_DELAY[0, 7, 4][0, 7, 1][0, 7, 3]
IOB1:I_DELAY[0, 1, 2][0, 1, 4][0, 1, 0]
IOB2:I_DELAY[1, 13, 0][1, 10, 1][1, 8, 0]
IOB3:I_DELAY[2, 7, 4][2, 7, 1][2, 7, 3]
IOB4:I_DELAY[2, 3, 2][2, 3, 4][2, 3, 1]
IOB5:I_DELAY[3, 7, 4][3, 7, 1][3, 7, 3]
IOB6:I_DELAY[3, 3, 2][3, 3, 4][3, 3, 1]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:DELAY_COMMON[0, 6, 0]
IOB0:OUTPUT_MISC[0, 14, 0]
IOB0:VREF[0, 17, 0]
IOB1:DELAY_COMMON[0, 1, 1]
IOB1:OUTPUT_MISC[1, 15, 0]
IOB2:DELAY_COMMON[1, 10, 0]
IOB2:OUTPUT_MISC[1, 5, 1]
IOB2:VREF[1, 9, 2]
IOB3:DELAY_COMMON[2, 6, 3]
IOB3:OUTPUT_MISC[2, 14, 0]
IOB3:VREF[2, 17, 0]
IOB4:DELAY_COMMON[2, 6, 4]
IOB4:OUTPUT_MISC[3, 15, 0]
IOB5:DELAY_COMMON[3, 6, 3]
IOB5:ENABLE[3, 9, 4]
IOB6:DELAY_COMMON[3, 6, 4]
IOB6:ENABLE[3, 1, 1]
Non-inverted[0]
IOB0:IFF_DELAY[0, 7, 2][0, 7, 0]
IOB1:IFF_DELAY[0, 2, 0][0, 1, 3]
IOB2:IFF_DELAY[1, 8, 1][1, 10, 4]
IOB3:IFF_DELAY[2, 7, 2][2, 7, 0]
IOB4:IFF_DELAY[2, 3, 0][2, 3, 3]
IOB5:IFF_DELAY[3, 7, 2][3, 7, 0]
IOB6:IFF_DELAY[3, 3, 0][3, 3, 3]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:OUTPUT_ENABLE[0, 11, 4][0, 11, 0]
IOB1:OUTPUT_DIFF[1, 15, 1][1, 15, 3]
IOB1:OUTPUT_DIFF_GROUP[1, 14, 0][0, 16, 1]
IOB1:OUTPUT_ENABLE[1, 18, 4][1, 18, 1]
IOB2:OUTPUT_ENABLE[1, 2, 4][1, 2, 1]
IOB3:OUTPUT_ENABLE[2, 13, 0][2, 10, 4]
IOB4:OUTPUT_DIFF[3, 15, 1][3, 15, 3]
IOB4:OUTPUT_DIFF_GROUP[3, 14, 0][2, 16, 1]
IOB4:OUTPUT_ENABLE[3, 18, 4][3, 18, 1]
Non-inverted[1][0]
IOB0:PDRIVE[0, 17, 3][0, 13, 4][0, 18, 0][0, 12, 2]
IOB1:PDRIVE[1, 12, 3][1, 17, 4][1, 13, 2][1, 17, 0]
IOB2:PDRIVE[1, 9, 0][1, 3, 1][1, 11, 0][1, 3, 4]
IOB3:PDRIVE[2, 17, 3][2, 13, 4][2, 18, 0][2, 12, 2]
IOB4:PDRIVE[3, 12, 3][3, 17, 4][3, 13, 2][3, 17, 0]
Mixed inversion~[3][2]~[1][0]
IOB0:IBUF_MODE[0, 12, 3][0, 14, 2][0, 15, 1]
IOB1:IBUF_MODE[1, 17, 1][1, 16, 0][1, 15, 2]
IOB3:IBUF_MODE[2, 12, 3][2, 14, 2][2, 15, 1]
IOB4:IBUF_MODE[3, 17, 1][3, 16, 0][3, 15, 2]
IOB5:IBUF_MODE[3, 5, 2][3, 5, 3][3, 5, 4]
IOB6:IBUF_MODE[3, 2, 0][3, 2, 1][3, 1, 4]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:NDRIVE[0, 17, 1][0, 14, 1][0, 18, 2][0, 16, 2]
IOB1:NDRIVE[1, 12, 4][1, 16, 1][1, 13, 1][1, 14, 1]
IOB2:NDRIVE[1, 9, 1][1, 5, 0][1, 11, 2][1, 6, 3]
IOB3:NDRIVE[2, 17, 1][2, 14, 1][2, 18, 2][2, 16, 2]
IOB4:NDRIVE[3, 12, 4][3, 16, 1][3, 13, 1][3, 14, 1]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[0, 14, 4][0, 13, 3][0, 13, 1][0, 12, 4][0, 12, 0][0, 16, 4]
IOB1:SLEW[1, 18, 2][1, 18, 0][1, 17, 3][1, 16, 4][1, 16, 3][1, 14, 3]
IOB2:SLEW[1, 4, 2][1, 4, 1][1, 3, 2][1, 3, 0][1, 2, 3][1, 6, 1]
IOB3:SLEW[2, 14, 4][2, 13, 3][2, 13, 1][2, 12, 4][2, 12, 0][2, 16, 4]
IOB4:SLEW[3, 18, 2][3, 18, 0][3, 17, 3][3, 16, 4][3, 16, 3][3, 14, 3]
Non-inverted[5][4][3][2][1][0]
IOB0:PULL[0, 17, 2][0, 18, 3][0, 18, 1]
IOB1:PULL[1, 12, 1][1, 10, 2][1, 13, 4]
IOB2:PULL[1, 9, 3][1, 11, 3][1, 11, 1]
IOB3:PULL[2, 17, 2][2, 18, 3][2, 18, 1]
IOB4:PULL[3, 12, 1][3, 10, 2][3, 13, 4]
IOB5:PULL[3, 11, 1][3, 11, 3][3, 11, 2]
IOB6:PULL[3, 1, 0][3, 2, 3][3, 2, 4]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[1, 4, 0][1, 4, 4][1, 5, 3]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.R1

IOBS.S3E.R1 bittile 0
RowColumn
01
0 -IOB0:DELAY_COMMON
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 -IOB0:I_DELAY[1]
10 -IOB0:IFF_DELAY[0]
11 -IOB0:I_DELAY[2]
12 -IOB0:I_DELAY[0]
13 -IOB0:IFF_DELAY[1]
14 --
15 --
16 --
17 --
18 --
19 --
20 -IOB0:OUTPUT_ENABLE[1]
21 --
22 --
23 --
24 --
25 --
26 --
27 --
28 IOB0:SLEW[1]-
29 --
30 IOB0:SLEW[2]-
31 IOB0:PDRIVE[2]-
32 IOB0:PDRIVE[0]-
33 IOB0:SLEW[3]-
34 IOB0:NDRIVE[0]-
35 IOB0:IBUF_MODE[2]-
36 IOB0:SLEW[4]-
37 IOB0:SLEW[5]-
38 IOB0:OUTPUT_ENABLE[0]-
39 -IOB0:PULL[0]
40 --
41 IOB0:NDRIVE[3]-
42 --
43 --
44 --
45 IOB0:IBUF_MODE[0]-
46 --
47 --
48 IOB0:SLEW[0]-
49 IOB0:OUTPUT_MISC-
50 --
51 IOB0:PULL[2]-
52 ~IOB0:PDRIVE[3]-
53 --
54 IOB0:VREF-
55 ~IOB0:NDRIVE[2]-
56 --
57 --
58 IOB0:PULL[1]IOB0:NDRIVE[1]
59 --
60 --
61 ~IOB0:PDRIVE[1]-
62 --
63 IOB0:IBUF_MODE[1]-
IOB0:PDRIVE[0, 0, 52][0, 0, 31][0, 0, 61][0, 0, 32]
Mixed inversion~[3][2]~[1][0]
IOB0:NDRIVE[0, 0, 41][0, 0, 55][0, 1, 58][0, 0, 34]
Mixed inversion[3]~[2][1][0]
IOB0:OUTPUT_ENABLE[0, 1, 20][0, 0, 38]
Non-inverted[1][0]
IOB0:IBUF_MODE[0, 0, 35][0, 0, 63][0, 0, 45]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB0:SLEW[0, 0, 37][0, 0, 36][0, 0, 33][0, 0, 30][0, 0, 28][0, 0, 48]
Non-inverted[5][4][3][2][1][0]
IOB0:DELAY_COMMON[0, 1, 0]
IOB0:OUTPUT_MISC[0, 0, 49]
IOB0:VREF[0, 0, 54]
Non-inverted[0]
IOB0:IFF_DELAY[0, 1, 13][0, 1, 10]
SDLY3_LDLY600
SDLY2_LDLY501
SDLY1_LDLY410
IOB0:I_DELAY[0, 1, 11][0, 1, 9][0, 1, 12]
LDLY12000
SDLY5_LDLY11001
SDLY4_LDLY10010
SDLY3_LDLY9011
SDLY2_LDLY8100
SDLY1_LDLY7101
LDLY6110
IOB0:PULL[0, 0, 51][0, 0, 58][0, 1, 39]
PULLDOWN000
NONE001
PULLUP011
KEEPER101

IOBS.S3E.R2

IOBS.S3E.R2 bittile 0
RowColumn
01
0 IOB1:PULL[1]IOB1:DELAY_COMMON
1 IOB1:NDRIVE[1]-
2 --
3 ~IOB1:PDRIVE[1]-
4 IOB1:PULL[0]-
5 --
6 IOB1:PULL[2]-
7 IOB1:NDRIVE[3]~IOB1:PDRIVE[3]
8 --
9 -IOB1:I_DELAY[1]
10 -IOB1:IFF_DELAY[0]
11 IOB1:NDRIVE[0]IOB1:I_DELAY[2]
12 IOB1:SLEW[0]IOB1:I_DELAY[0]
13 -IOB1:IFF_DELAY[1]
14 IOB1:OUTPUT_DIFF_GROUP[0]-
15 IOB1:OUTPUT_DIFF[0]-
16 IOB1:OUTPUT_DIFF[1]-
17 --
18 IOB1:IBUF_MODE[0]-
19 --
20 IOB1:OUTPUT_MISC~IOB1:NDRIVE[2]
21 IOB1:SLEW[1]-
22 IOB1:SLEW[2]-
23 IOB1:IBUF_MODE[2]-
24 IOB1:IBUF_MODE[1]-
25 --
26 -IOB1:SLEW[5]
27 IOB1:SLEW[3]-
28 --
29 -IOB0:IFF_DELAY[1]
30 IOB1:SLEW[4]IOB0:I_DELAY[0]
31 -IOB0:I_DELAY[2]
32 -IOB0:IFF_DELAY[0]
33 IOB1:PDRIVE[0]IOB0:I_DELAY[1]
34 --
35 --
36 IOB1:PDRIVE[2]-
37 --
38 IOB1:OUTPUT_ENABLE[0]-
39 -IOB1:OUTPUT_ENABLE[1]
40 --
41 -IOB0:DELAY_COMMON
42 ~IOB0:NDRIVE[2]-
43 --
44 IOB0:OUTPUT_ENABLE[0]-
IOBS.S3E.R2 bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 --
10 --
11 --
12 IOB0:SLEW[1]-
13 --
14 --
15 IOB0:SLEW[2]-
16 IOB0:SLEW[3]-
17 --
18 --
19 IOB0:IBUF_MODE[2]-
20 -IOB0:SLEW[5]
21 --
22 IOB0:SLEW[4]-
23 IOB0:IBUF_MODE[1]-
24 IOB0:OUTPUT_MISC-
25 --
26 IOB0:IBUF_MODE[0]-
27 --
28 IOB0:NDRIVE[0]-
29 --
30 IOB0:SLEW[0]-
31 IOB1:OUTPUT_DIFF_GROUP[1]-
32 --
33 --
34 --
35 --
36 --
37 IOB0:VREF-
38 IOB0:NDRIVE[3]-
39 IOB0:PULL[2]~IOB0:PDRIVE[3]
40 --
41 IOB0:OUTPUT_ENABLE[1]-
42 ~IOB0:PDRIVE[1]-
43 IOB0:NDRIVE[1]-
44 IOB0:PULL[0]-
45 IOB0:PULL[1]-
46 IOB0:PDRIVE[2]-
47 --
48 --
49 IOB0:PDRIVE[0]-
IOB0:PULL[1, 0, 39][1, 0, 45][1, 0, 44]
IOB1:PULL[0, 0, 6][0, 0, 0][0, 0, 4]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:NDRIVE[1, 0, 38][0, 0, 42][1, 0, 43][1, 0, 28]
IOB1:NDRIVE[0, 0, 7][0, 1, 20][0, 0, 1][0, 0, 11]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[1, 1, 20][1, 0, 22][1, 0, 16][1, 0, 15][1, 0, 12][1, 0, 30]
IOB1:SLEW[0, 1, 26][0, 0, 30][0, 0, 27][0, 0, 22][0, 0, 21][0, 0, 12]
Non-inverted[5][4][3][2][1][0]
IOB0:OUTPUT_ENABLE[1, 0, 41][0, 0, 44]
IOB1:OUTPUT_DIFF[0, 0, 16][0, 0, 15]
IOB1:OUTPUT_DIFF_GROUP[1, 0, 31][0, 0, 14]
IOB1:OUTPUT_ENABLE[0, 1, 39][0, 0, 38]
Non-inverted[1][0]
IOB0:IBUF_MODE[1, 0, 19][1, 0, 23][1, 0, 26]
IOB1:IBUF_MODE[0, 0, 23][0, 0, 24][0, 0, 18]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:DELAY_COMMON[0, 1, 41]
IOB0:OUTPUT_MISC[1, 0, 24]
IOB0:VREF[1, 0, 37]
IOB1:DELAY_COMMON[0, 1, 0]
IOB1:OUTPUT_MISC[0, 0, 20]
Non-inverted[0]
IOB0:PDRIVE[1, 1, 39][1, 0, 46][1, 0, 42][1, 0, 49]
IOB1:PDRIVE[0, 1, 7][0, 0, 36][0, 0, 3][0, 0, 33]
Mixed inversion~[3][2]~[1][0]
IOB0:IFF_DELAY[0, 1, 29][0, 1, 32]
IOB1:IFF_DELAY[0, 1, 13][0, 1, 10]
SDLY3_LDLY600
SDLY2_LDLY501
SDLY1_LDLY410
IOB0:I_DELAY[0, 1, 31][0, 1, 33][0, 1, 30]
IOB1:I_DELAY[0, 1, 11][0, 1, 9][0, 1, 12]
LDLY12000
SDLY5_LDLY11001
SDLY4_LDLY10010
SDLY3_LDLY9011
SDLY2_LDLY8100
SDLY1_LDLY7101
LDLY6110

IOBS.S3E.R3

IOBS.S3E.R3 bittile 0
RowColumn
01
0 IOB3:PULL[1]IOB3:DELAY_COMMON
1 IOB3:NDRIVE[1]-
2 --
3 ~IOB3:PDRIVE[1]-
4 IOB3:PULL[0]-
5 --
6 IOB3:PULL[2]-
7 IOB3:NDRIVE[3]~IOB3:PDRIVE[3]
8 --
9 -IOB3:I_DELAY[1]
10 -IOB3:IFF_DELAY[0]
11 IOB3:NDRIVE[0]IOB3:I_DELAY[2]
12 IOB3:SLEW[0]IOB3:I_DELAY[0]
13 -IOB3:IFF_DELAY[1]
14 IOB3:OUTPUT_DIFF_GROUP[0]-
15 IOB3:OUTPUT_DIFF[0]-
16 IOB3:OUTPUT_DIFF[1]-
17 --
18 IOB3:IBUF_MODE[0]-
19 --
20 IOB3:OUTPUT_MISC~IOB3:NDRIVE[2]
21 IOB3:SLEW[1]-
22 IOB3:SLEW[2]-
23 IOB3:IBUF_MODE[2]-
24 IOB3:IBUF_MODE[1]-
25 --
26 -IOB3:SLEW[5]
27 IOB3:SLEW[3]-
28 --
29 -IOB2:IFF_DELAY[1]
30 IOB3:SLEW[4]IOB2:I_DELAY[0]
31 -IOB2:I_DELAY[2]
32 -IOB2:IFF_DELAY[0]
33 IOB3:PDRIVE[0]IOB2:I_DELAY[1]
34 --
35 --
36 IOB3:PDRIVE[2]-
37 --
38 IOB3:OUTPUT_ENABLE[0]-
39 -IOB3:OUTPUT_ENABLE[1]
40 --
41 -IOB2:DELAY_COMMON
42 ~IOB2:NDRIVE[2]-
43 --
44 IOB2:OUTPUT_ENABLE[0]-
IOBS.S3E.R3 bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 --
10 --
11 --
12 IOB2:SLEW[1]-
13 --
14 --
15 IOB2:SLEW[2]-
16 IOB2:SLEW[3]-
17 --
18 --
19 IOB2:IBUF_MODE[2]-
20 -IOB2:SLEW[5]
21 --
22 IOB2:SLEW[4]-
23 IOB2:IBUF_MODE[1]-
24 IOB2:OUTPUT_MISC-
25 --
26 IOB2:IBUF_MODE[0]-
27 --
28 IOB2:NDRIVE[0]-
29 --
30 IOB2:SLEW[0]-
31 IOB3:OUTPUT_DIFF_GROUP[1]-
32 --
33 --
34 --
35 --
36 --
37 IOB2:VREF-
38 IOB2:NDRIVE[3]-
39 IOB2:PULL[2]~IOB2:PDRIVE[3]
40 --
41 IOB2:OUTPUT_ENABLE[1]-
42 ~IOB2:PDRIVE[1]-
43 IOB2:NDRIVE[1]IOB1:DELAY_COMMON
44 IOB2:PULL[0]-
45 IOB2:PULL[1]-
46 IOB2:PDRIVE[2]-
47 --
48 --
49 IOB2:PDRIVE[0]-
50 --
51 -IOB1:I_DELAY[1]
52 --
53 -IOB1:IFF_DELAY[0]
54 -IOB1:I_DELAY[2]
55 -IOB1:I_DELAY[0]
56 -IOB1:IFF_DELAY[1]
IOBS.S3E.R3 bittile 2
RowColumn
01
0 IOB1:PDRIVE[2]-
1 --
2 --
3 IOB1:PDRIVE[0]-
4 IOB1:SLEW[1]-
5 --
6 --
7 IOB1:SLEW[2]IOB1:SLEW[5]
8 --
9 IOB1:IBUF_MODE[2]-
10 IOB1:SLEW[3]-
11 IOB1:OUTPUT_ENABLE[0]-
12 --
13 IOB1:IBUF_MODE[1]-
14 IOB1:SLEW[4]IOB1:OUTPUT_MISC
15 IOB1:IBUF_MODE[0]-
16 --
17 --
18 --
19 --
20 -IOB1:NDRIVE[0]
21 --
22 IOB1:SLEW[0]-
23 --
24 --
25 IOB1:VREF-
26 IOB1:NDRIVE[3]~IOB1:PDRIVE[3]
27 IOB1:PULL[2]-
28 --
29 ~IOB1:PDRIVE[1]-
30 IOB1:OUTPUT_ENABLE[1]-
31 IOB1:NDRIVE[1]-
32 --
33 --
34 --
35 IOB1:PULL[1]-
36 ~IOB1:NDRIVE[2]-
37 --
38 --
39 --
40 --
41 --
42 --
43 -IOB0:DELAY_COMMON
44 --
45 IOB1:PULL[0]-
46 --
47 --
48 IOB0:IBUF_MODE[2]-
49 --
50 --
51 IOB0:IBUF_MODE[1]IOB0:I_DELAY[1]
52 IOB0:IBUF_MODE[0]IOB0:VREF
53 -IOB0:IFF_DELAY[0]
54 -IOB0:I_DELAY[2]
55 -IOB0:I_DELAY[0]
56 -IOB0:IFF_DELAY[1]
57 IOB0:ENABLE-
58 IOB0:PULL[0]-
59 IOB0:PULL[1]-
60 --
61 --
62 IOB0:PULL[2]-
IOB0:PULL[2, 0, 62][2, 0, 59][2, 0, 58]
IOB1:PULL[2, 0, 27][2, 0, 35][2, 0, 45]
IOB2:PULL[1, 0, 39][1, 0, 45][1, 0, 44]
IOB3:PULL[0, 0, 6][0, 0, 0][0, 0, 4]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB1:NDRIVE[2, 0, 26][2, 0, 36][2, 0, 31][2, 1, 20]
IOB2:NDRIVE[1, 0, 38][0, 0, 42][1, 0, 43][1, 0, 28]
IOB3:NDRIVE[0, 0, 7][0, 1, 20][0, 0, 1][0, 0, 11]
Mixed inversion[3]~[2][1][0]
IOB1:SLEW[2, 1, 7][2, 0, 14][2, 0, 10][2, 0, 7][2, 0, 4][2, 0, 22]
IOB2:SLEW[1, 1, 20][1, 0, 22][1, 0, 16][1, 0, 15][1, 0, 12][1, 0, 30]
IOB3:SLEW[0, 1, 26][0, 0, 30][0, 0, 27][0, 0, 22][0, 0, 21][0, 0, 12]
Non-inverted[5][4][3][2][1][0]
IOB1:OUTPUT_ENABLE[2, 0, 30][2, 0, 11]
IOB2:OUTPUT_ENABLE[1, 0, 41][0, 0, 44]
IOB3:OUTPUT_DIFF[0, 0, 16][0, 0, 15]
IOB3:OUTPUT_DIFF_GROUP[1, 0, 31][0, 0, 14]
IOB3:OUTPUT_ENABLE[0, 1, 39][0, 0, 38]
Non-inverted[1][0]
IOB2:IBUF_MODE[1, 0, 19][1, 0, 23][1, 0, 26]
IOB3:IBUF_MODE[0, 0, 23][0, 0, 24][0, 0, 18]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:DELAY_COMMON[2, 1, 43]
IOB0:ENABLE[2, 0, 57]
IOB0:VREF[2, 1, 52]
IOB1:DELAY_COMMON[1, 1, 43]
IOB1:OUTPUT_MISC[2, 1, 14]
IOB1:VREF[2, 0, 25]
IOB2:DELAY_COMMON[0, 1, 41]
IOB2:OUTPUT_MISC[1, 0, 24]
IOB2:VREF[1, 0, 37]
IOB3:DELAY_COMMON[0, 1, 0]
IOB3:OUTPUT_MISC[0, 0, 20]
Non-inverted[0]
IOB1:PDRIVE[2, 1, 26][2, 0, 0][2, 0, 29][2, 0, 3]
IOB2:PDRIVE[1, 1, 39][1, 0, 46][1, 0, 42][1, 0, 49]
IOB3:PDRIVE[0, 1, 7][0, 0, 36][0, 0, 3][0, 0, 33]
Mixed inversion~[3][2]~[1][0]
IOB0:IFF_DELAY[2, 1, 56][2, 1, 53]
IOB1:IFF_DELAY[1, 1, 56][1, 1, 53]
IOB2:IFF_DELAY[0, 1, 29][0, 1, 32]
IOB3:IFF_DELAY[0, 1, 13][0, 1, 10]
SDLY3_LDLY600
SDLY2_LDLY501
SDLY1_LDLY410
IOB0:I_DELAY[2, 1, 54][2, 1, 51][2, 1, 55]
IOB1:I_DELAY[1, 1, 54][1, 1, 51][1, 1, 55]
IOB2:I_DELAY[0, 1, 31][0, 1, 33][0, 1, 30]
IOB3:I_DELAY[0, 1, 11][0, 1, 9][0, 1, 12]
LDLY12000
SDLY5_LDLY11001
SDLY4_LDLY10010
SDLY3_LDLY9011
SDLY2_LDLY8100
SDLY1_LDLY7101
LDLY6110
IOB0:IBUF_MODE[2, 0, 48][2, 0, 51][2, 0, 52]
IOB1:IBUF_MODE[2, 0, 9][2, 0, 13][2, 0, 15]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.R4

IOBS.S3E.R4 bittile 0
RowColumn
01
0 -IOB4:DELAY_COMMON
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 IOB4:NDRIVE[0]-
9 ~IOB4:PDRIVE[3]IOB4:I_DELAY[1]
10 IOB4:NDRIVE[1]IOB4:IFF_DELAY[0]
11 -IOB4:I_DELAY[2]
12 ~IOB4:PDRIVE[1]IOB4:I_DELAY[0]
13 -IOB4:IFF_DELAY[1]
14 IOB4:PULL[0]IOB4:PULL[1]
15 --
16 --
17 IOB4:PULL[2]-
18 IOB4:NDRIVE[3]-
19 IOB4:OUTPUT_DIFF_GROUP[0]-
20 --
21 IOB4:SLEW[0]-
22 --
23 IOB4:OUTPUT_DIFF[0]-
24 --
25 --
26 ~IOB4:NDRIVE[2]IOB4:IBUF_MODE[0]
27 IOB4:OUTPUT_DIFF[1]-
28 IOB4:PDRIVE[0]-
29 -IOB3:IFF_DELAY[1]
30 IOB4:OUTPUT_MISCIOB3:I_DELAY[0]
31 IOB4:IBUF_MODE[1]IOB3:I_DELAY[2]
32 -IOB3:IFF_DELAY[0]
33 IOB4:IBUF_MODE[2]IOB3:I_DELAY[1]
34 IOB4:SLEW[1]-
35 --
36 IOB4:SLEW[2]-
37 IOB4:SLEW[3]-
38 IOB4:SLEW[4]-
39 -IOB4:PDRIVE[2]
40 IOB4:SLEW[5]-
41 -IOB3:DELAY_COMMON
42 IOB4:OUTPUT_ENABLE[0]-
43 --
44 --
45 --
46 --
47 --
48 --
49 --
50 --
51 --
52 -IOB4:OUTPUT_ENABLE[1]
53 --
54 --
55 IOB3:OUTPUT_ENABLE[0]-
IOBS.S3E.R4 bittile 1
RowColumn
01
0 --
1 --
2 IOB3:OUTPUT_ENABLE[1]-
3 --
4 IOB3:PDRIVE[2]-
5 --
6 --
7 --
8 --
9 --
10 IOB3:PDRIVE[0]-
11 --
12 --
13 --
14 --
15 --
16 --
17 --
18 --
19 --
20 -IOB3:PULL[0]
21 --
22 --
23 IOB3:SLEW[1]-
24 --
25 IOB3:SLEW[2]-
26 -IOB3:SLEW[5]
27 --
28 IOB3:SLEW[3]-
29 IOB3:OUTPUT_MISC-
30 IOB3:IBUF_MODE[2]-
31 IOB3:IBUF_MODE[0]-
32 IOB3:SLEW[4]-
33 --
34 IOB3:IBUF_MODE[1]-
35 IOB4:OUTPUT_DIFF_GROUP[1]-
36 --
37 --
38 IOB2:PULL[0]-
39 --
40 --
41 IOB3:SLEW[0]-
42 --
43 IOB3:NDRIVE[0]-
44 ~IOB2:NDRIVE[2]-
45 --
46 ~IOB3:NDRIVE[2]-
47 --
48 IOB3:VREF-
49 IOB3:NDRIVE[3]-
50 IOB3:PULL[2]-
51 --
52 ~IOB3:PDRIVE[1]IOB2:NDRIVE[1]
53 IOB3:NDRIVE[1]-
54 IOB3:PULL[1]-
55 ~IOB3:PDRIVE[3]-
56 ~IOB2:PDRIVE[1]-
57 --
58 IOB2:PULL[2]-
59 --
60 IOB2:PULL[1]-
61 ~IOB2:PDRIVE[3]-
62 --
63 IOB2:NDRIVE[3]-
IOBS.S3E.R4 bittile 2
RowColumn
01
0 IOB2:OUTPUT_DIFF_GROUP[0]IOB2:DELAY_COMMON
1 IOB2:NDRIVE[0]-
2 IOB2:SLEW[0]-
3 --
4 --
5 --
6 IOB2:OUTPUT_DIFF[0]-
7 IOB2:OUTPUT_DIFF[1]IOB2:IBUF_MODE[0]
8 IOB2:OUTPUT_MISC-
9 -IOB2:I_DELAY[1]
10 -IOB2:IFF_DELAY[0]
11 IOB2:SLEW[1]IOB2:I_DELAY[2]
12 IOB2:SLEW[2]IOB2:I_DELAY[0]
13 IOB2:IBUF_MODE[2]IOB2:IFF_DELAY[1]
14 IOB2:IBUF_MODE[1]-
15 IOB2:SLEW[3]-
16 --
17 --
18 --
19 IOB2:SLEW[4]-
20 IOB2:SLEW[5]-
21 --
22 --
23 --
24 --
25 --
26 --
27 --
28 --
29 -IOB1:IFF_DELAY[1]
30 -IOB1:I_DELAY[0]
31 -IOB1:I_DELAY[2]
32 -IOB1:IFF_DELAY[0]
33 -IOB1:I_DELAY[1]
34 --
35 --
36 --
37 --
38 --
39 --
40 --
41 -IOB1:DELAY_COMMON
42 --
43 --
44 IOB2:PDRIVE[0]-
45 --
46 IOB2:PDRIVE[2]-
47 --
48 --
49 IOB2:OUTPUT_ENABLE[0]-
50 --
51 --
52 -IOB2:OUTPUT_ENABLE[1]
53 --
54 --
55 --
56 --
57 --
58 --
59 --
60 --
61 --
62 --
63 IOB1:PDRIVE[2]-
IOBS.S3E.R4 bittile 3
RowColumn
01
0 IOB1:OUTPUT_ENABLE[0]-
1 IOB1:OUTPUT_MISC-
2 IOB1:IBUF_MODE[2]-
3 IOB1:OUTPUT_ENABLE[1]-
4 IOB1:SLEW[1]-
5 --
6 IOB1:SLEW[2]-
7 -IOB1:SLEW[5]
8 IOB1:SLEW[3]-
9 --
10 IOB1:SLEW[4]-
11 --
12 --
13 IOB1:IBUF_MODE[1]-
14 ~IOB1:PDRIVE[1]-
15 --
16 --
17 --
18 IOB1:IBUF_MODE[0]-
19 IOB1:SLEW[0]-
20 -IOB1:NDRIVE[0]
21 IOB2:OUTPUT_DIFF_GROUP[1]-
22 --
23 --
24 --
25 IOB1:VREF-
26 IOB1:NDRIVE[3]~IOB1:PDRIVE[3]
27 IOB1:PULL[2]-
28 IOB1:PULL[0]-
29 --
30 IOB1:PDRIVE[0]-
31 --
32 IOB1:NDRIVE[1]-
33 IOB1:PULL[1]-
34 --
35 --
36 --
37 --
38 --
39 --
40 IOB0:IBUF_MODE[2]-
41 --
42 --
43 -IOB0:DELAY_COMMON
44 --
45 ~IOB1:NDRIVE[2]-
46 IOB0:IBUF_MODE[1]-
47 IOB0:IBUF_MODE[0]-
48 --
49 --
50 --
51 -IOB0:I_DELAY[1]
52 -IOB0:VREF
53 -IOB0:IFF_DELAY[0]
54 -IOB0:I_DELAY[2]
55 -IOB0:I_DELAY[0]
56 -IOB0:IFF_DELAY[1]
57 IOB0:ENABLE-
58 IOB0:PULL[0]-
59 IOB0:PULL[1]-
60 --
61 --
62 IOB0:PULL[2]-
IOB1:NDRIVE[3, 0, 26][3, 0, 45][3, 0, 32][3, 1, 20]
IOB2:NDRIVE[1, 0, 63][1, 0, 44][1, 1, 52][2, 0, 1]
IOB3:NDRIVE[1, 0, 49][1, 0, 46][1, 0, 53][1, 0, 43]
IOB4:NDRIVE[0, 0, 18][0, 0, 26][0, 0, 10][0, 0, 8]
Mixed inversion[3]~[2][1][0]
IOB0:PULL[3, 0, 62][3, 0, 59][3, 0, 58]
IOB1:PULL[3, 0, 27][3, 0, 33][3, 0, 28]
IOB2:PULL[1, 0, 58][1, 0, 60][1, 0, 38]
IOB3:PULL[1, 0, 50][1, 0, 54][1, 1, 20]
IOB4:PULL[0, 0, 17][0, 1, 14][0, 0, 14]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB1:OUTPUT_ENABLE[3, 0, 3][3, 0, 0]
IOB2:OUTPUT_DIFF[2, 0, 7][2, 0, 6]
IOB2:OUTPUT_DIFF_GROUP[3, 0, 21][2, 0, 0]
IOB2:OUTPUT_ENABLE[2, 1, 52][2, 0, 49]
IOB3:OUTPUT_ENABLE[1, 0, 2][0, 0, 55]
IOB4:OUTPUT_DIFF[0, 0, 27][0, 0, 23]
IOB4:OUTPUT_DIFF_GROUP[1, 0, 35][0, 0, 19]
IOB4:OUTPUT_ENABLE[0, 1, 52][0, 0, 42]
Non-inverted[1][0]
IOB1:SLEW[3, 1, 7][3, 0, 10][3, 0, 8][3, 0, 6][3, 0, 4][3, 0, 19]
IOB2:SLEW[2, 0, 20][2, 0, 19][2, 0, 15][2, 0, 12][2, 0, 11][2, 0, 2]
IOB3:SLEW[1, 1, 26][1, 0, 32][1, 0, 28][1, 0, 25][1, 0, 23][1, 0, 41]
IOB4:SLEW[0, 0, 40][0, 0, 38][0, 0, 37][0, 0, 36][0, 0, 34][0, 0, 21]
Non-inverted[5][4][3][2][1][0]
IOB1:PDRIVE[3, 1, 26][2, 0, 63][3, 0, 14][3, 0, 30]
IOB2:PDRIVE[1, 0, 61][2, 0, 46][1, 0, 56][2, 0, 44]
IOB3:PDRIVE[1, 0, 55][1, 0, 4][1, 0, 52][1, 0, 10]
IOB4:PDRIVE[0, 0, 9][0, 1, 39][0, 0, 12][0, 0, 28]
Mixed inversion~[3][2]~[1][0]
IOB0:DELAY_COMMON[3, 1, 43]
IOB0:ENABLE[3, 0, 57]
IOB0:VREF[3, 1, 52]
IOB1:DELAY_COMMON[2, 1, 41]
IOB1:OUTPUT_MISC[3, 0, 1]
IOB1:VREF[3, 0, 25]
IOB2:DELAY_COMMON[2, 1, 0]
IOB2:OUTPUT_MISC[2, 0, 8]
IOB3:DELAY_COMMON[0, 1, 41]
IOB3:OUTPUT_MISC[1, 0, 29]
IOB3:VREF[1, 0, 48]
IOB4:DELAY_COMMON[0, 1, 0]
IOB4:OUTPUT_MISC[0, 0, 30]
Non-inverted[0]
IOB0:IFF_DELAY[3, 1, 56][3, 1, 53]
IOB1:IFF_DELAY[2, 1, 29][2, 1, 32]
IOB2:IFF_DELAY[2, 1, 13][2, 1, 10]
IOB3:IFF_DELAY[0, 1, 29][0, 1, 32]
IOB4:IFF_DELAY[0, 1, 13][0, 1, 10]
SDLY3_LDLY600
SDLY2_LDLY501
SDLY1_LDLY410
IOB0:I_DELAY[3, 1, 54][3, 1, 51][3, 1, 55]
IOB1:I_DELAY[2, 1, 31][2, 1, 33][2, 1, 30]
IOB2:I_DELAY[2, 1, 11][2, 1, 9][2, 1, 12]
IOB3:I_DELAY[0, 1, 31][0, 1, 33][0, 1, 30]
IOB4:I_DELAY[0, 1, 11][0, 1, 9][0, 1, 12]
LDLY12000
SDLY5_LDLY11001
SDLY4_LDLY10010
SDLY3_LDLY9011
SDLY2_LDLY8100
SDLY1_LDLY7101
LDLY6110
IOB1:IBUF_MODE[3, 0, 2][3, 0, 13][3, 0, 18]
IOB2:IBUF_MODE[2, 0, 13][2, 0, 14][2, 1, 7]
IOB3:IBUF_MODE[1, 0, 30][1, 0, 34][1, 0, 31]
IOB4:IBUF_MODE[0, 0, 33][0, 0, 31][0, 1, 26]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:IBUF_MODE[3, 0, 40][3, 0, 46][3, 0, 47]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.B1

IOBS.S3E.B1 bittile 0
RowColumn
012345678
0 IOB0:PULL[1]--IOB0:OUTPUT_ENABLE[0]IOB0:SLEW[2]IOB0:SLEW[4]IOB0:IBUF_MODE[2]-IOB0:OUTPUT_ENABLE[1]
1 -IOB0:SLEW[0]IOB0:IBUF_MODE[1]IOB0:SLEW[1]IOB0:PDRIVE[2]~IOB0:NDRIVE[2]IOB0:SLEW[5]--
2 IOB0:NDRIVE[1]-IOB0:NDRIVE[3]-IOB0:SLEW[3]-IOB0:OUTPUT_MISCIOB0:IBUF_MODE[0]-
3 IOB0:PULL[0]IOB0:NDRIVE[0]-IOB0:PDRIVE[0]IOB0:I_DELAY[0]--IOB0:DELAY_COMMON-
4 ~IOB0:PDRIVE[1]-IOB0:PULL[2]IOB0:I_DELAY[2]IOB0:I_DELAY[1]~IOB0:PDRIVE[3]IOB0:IFF_DELAY[0]IOB0:IFF_DELAY[1]-
IOB0:PULL[0, 2, 4][0, 0, 0][0, 0, 3]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:SLEW[0, 6, 1][0, 5, 0][0, 4, 2][0, 4, 0][0, 3, 1][0, 1, 1]
Non-inverted[5][4][3][2][1][0]
IOB0:NDRIVE[0, 2, 2][0, 5, 1][0, 0, 2][0, 1, 3]
Mixed inversion[3]~[2][1][0]
IOB0:OUTPUT_ENABLE[0, 8, 0][0, 3, 0]
Non-inverted[1][0]
IOB0:PDRIVE[0, 5, 4][0, 4, 1][0, 0, 4][0, 3, 3]
Mixed inversion~[3][2]~[1][0]
IOB0:I_DELAY[0, 3, 4][0, 4, 4][0, 4, 3]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:DELAY_COMMON[0, 7, 3]
IOB0:OUTPUT_MISC[0, 6, 2]
Non-inverted[0]
IOB0:IFF_DELAY[0, 7, 4][0, 6, 4]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:IBUF_MODE[0, 6, 0][0, 2, 1][0, 7, 2]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.B2

IOBS.S3E.B2 bittile 0
RowColumn
01234567891011
0 IOB1:SLEW[1]--~IOB1:PDRIVE[3]IOB2:I_DELAY[0]IOB1:PULL[1]-IOB2:IBUF_MODE[1]IOB2:IBUF_MODE[0]--IOB2:ENABLE
1 IOB1:SLEW[2]IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF_GROUP[0]IOB1:NDRIVE[3]IOB2:I_DELAY[2]~IOB1:PDRIVE[1]IOB1:NDRIVE[1]IOB2:IBUF_MODE[2]-IOB2:VREF--
2 -IOB1:SLEW[0]----IOB1:PULL[0]--IOB2:PULL[2]-IOB2:PULL[0]
3 IOB1:IBUF_MODE[1]--IOB2:DELAY_COMMONIOB2:IFF_DELAY[1]IOB1:PULL[2]IOB1:OUTPUT_DIFF[1]----IOB2:PULL[1]
4 ~IOB1:NDRIVE[2]IOB1:OUTPUT_DIFF[0]IOB1:IBUF_MODE[0]IOB2:I_DELAY[1]IOB2:IFF_DELAY[0]-------
IOBS.S3E.B2 bittile 1
RowColumn
0123456789101112131415161718
0 IOB0:PULL[1]--IOB0:OUTPUT_ENABLE[0]IOB0:SLEW[2]IOB0:SLEW[4]IOB0:IBUF_MODE[2]-IOB0:OUTPUT_ENABLE[1]IOB0:I_DELAY[2]IOB0:IFF_DELAY[0]IOB0:I_DELAY[1]-IOB0:DELAY_COMMONIOB1:DELAY_COMMONIOB1:I_DELAY[1]IOB1:IFF_DELAY[0]IOB1:OUTPUT_ENABLE[0]IOB1:IBUF_MODE[2]
1 -IOB0:SLEW[0]IOB0:IBUF_MODE[1]IOB0:SLEW[1]IOB0:PDRIVE[2]~IOB0:NDRIVE[2]IOB0:SLEW[5]--IOB0:I_DELAY[0]------IOB1:I_DELAY[2]-IOB1:SLEW[5]
2 IOB0:NDRIVE[1]-IOB0:NDRIVE[3]-IOB0:SLEW[3]-IOB0:OUTPUT_MISCIOB0:IBUF_MODE[0]-IOB0:IFF_DELAY[1]------IOB1:OUTPUT_MISCIOB1:SLEW[3]IOB1:OUTPUT_ENABLE[1]
3 IOB0:PULL[0]IOB0:NDRIVE[0]-IOB0:PDRIVE[0]------------IOB1:I_DELAY[0]IOB1:SLEW[4]IOB1:PDRIVE[2]
4 ~IOB0:PDRIVE[1]IOB1:OUTPUT_DIFF_GROUP[1]IOB0:PULL[2]--~IOB0:PDRIVE[3]----------IOB1:IFF_DELAY[1]-IOB1:PDRIVE[0]
IOB0:NDRIVE[1, 2, 2][1, 5, 1][1, 0, 2][1, 1, 3]
IOB1:NDRIVE[0, 3, 1][0, 0, 4][0, 6, 1][0, 1, 1]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[1, 6, 1][1, 5, 0][1, 4, 2][1, 4, 0][1, 3, 1][1, 1, 1]
IOB1:SLEW[1, 18, 1][1, 17, 3][1, 17, 2][0, 0, 1][0, 0, 0][0, 1, 2]
Non-inverted[5][4][3][2][1][0]
IOB0:OUTPUT_ENABLE[1, 8, 0][1, 3, 0]
IOB1:OUTPUT_DIFF[0, 6, 3][0, 1, 4]
IOB1:OUTPUT_DIFF_GROUP[1, 1, 4][0, 2, 1]
IOB1:OUTPUT_ENABLE[1, 18, 2][1, 17, 0]
Non-inverted[1][0]
IOB0:IBUF_MODE[1, 6, 0][1, 2, 1][1, 7, 2]
IOB1:IBUF_MODE[1, 18, 0][0, 0, 3][0, 2, 4]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:DELAY_COMMON[1, 13, 0]
IOB0:OUTPUT_MISC[1, 6, 2]
IOB1:DELAY_COMMON[1, 14, 0]
IOB1:OUTPUT_MISC[1, 16, 2]
IOB2:DELAY_COMMON[0, 3, 3]
IOB2:ENABLE[0, 11, 0]
IOB2:VREF[0, 9, 1]
Non-inverted[0]
IOB0:I_DELAY[1, 9, 0][1, 11, 0][1, 9, 1]
IOB1:I_DELAY[1, 16, 1][1, 15, 0][1, 16, 3]
IOB2:I_DELAY[0, 4, 1][0, 3, 4][0, 4, 0]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:IFF_DELAY[1, 9, 2][1, 10, 0]
IOB1:IFF_DELAY[1, 16, 4][1, 16, 0]
IOB2:IFF_DELAY[0, 4, 3][0, 4, 4]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:PULL[1, 2, 4][1, 0, 0][1, 0, 3]
IOB1:PULL[0, 5, 3][0, 5, 0][0, 6, 2]
IOB2:PULL[0, 9, 2][0, 11, 3][0, 11, 2]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[0, 7, 1][0, 7, 0][0, 8, 0]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB0:PDRIVE[1, 5, 4][1, 4, 1][1, 0, 4][1, 3, 3]
IOB1:PDRIVE[0, 3, 0][1, 18, 3][0, 5, 1][1, 18, 4]
Mixed inversion~[3][2]~[1][0]

IOBS.S3E.B3

IOBS.S3E.B3 bittile 0
RowColumn
0123456789101112131415161718
0 ------IOB4:I_DELAY[1]IOB4:DELAY_COMMONIOB3:DELAY_COMMONIOB3:IFF_DELAY[0]IOB4:SLEW[1]-IOB4:IBUF_MODE[2]IOB4:OUTPUT_ENABLE[0]~IOB4:NDRIVE[2]-IOB4:OUTPUT_DIFF_GROUP[0]-IOB4:PULL[0]
1 ------IOB4:IFF_DELAY[0]--IOB3:I_DELAY[1]--IOB4:SLEW[2]-IOB4:OUTPUT_MISCIOB4:OUTPUT_DIFF[1]IOB4:NDRIVE[0]IOB4:PULL[2]~IOB4:PDRIVE[1]
2 ------IOB4:I_DELAY[2]----IOB3:IFF_DELAY[1]IOB4:PDRIVE[0]IOB4:OUTPUT_ENABLE[1]IOB4:SLEW[5]IOB4:IBUF_MODE[0]-~IOB4:PDRIVE[3]IOB4:NDRIVE[1]
3 ------IOB4:I_DELAY[0]----IOB3:I_DELAY[2]-IOB4:PDRIVE[2]-IOB4:OUTPUT_DIFF[0]IOB4:SLEW[0]-IOB4:PULL[1]
4 ------IOB4:IFF_DELAY[1]----IOB3:I_DELAY[0]IOB4:SLEW[3]IOB4:SLEW[4]IOB4:IBUF_MODE[1]--IOB4:NDRIVE[3]-
IOBS.S3E.B3 bittile 1
RowColumn
0123456789101112131415161718
0 ----IOB2:PULL[0]-IOB2:IBUF_MODE[1]---IOB2:IFF_DELAY[1]--IOB4:OUTPUT_DIFF_GROUP[1]-IOB3:OUTPUT_MISCIOB3:SLEW[1]IOB3:IBUF_MODE[2]IOB3:OUTPUT_ENABLE[0]
1 ----IOB2:PULL[1]IOB2:IBUF_MODE[0]IOB2:IBUF_MODE[2]---IOB2:IFF_DELAY[0]IOB2:I_DELAY[1]~IOB3:PDRIVE[1]---IOB3:SLEW[2]IOB3:PDRIVE[0]-
2 -----------IOB2:DELAY_COMMONIOB3:PULL[0]IOB3:NDRIVE[0]IOB3:NDRIVE[3]IOB3:IBUF_MODE[0]--IOB3:SLEW[4]
3 -----IOB2:ENABLE---IOB2:I_DELAY[2]--IOB3:NDRIVE[1]-~IOB3:PDRIVE[3]-IOB3:IBUF_MODE[1]IOB3:SLEW[3]IOB3:OUTPUT_ENABLE[1]
4 -----IOB2:PULL[2]---IOB2:I_DELAY[0]IOB3:PULL[1]--IOB3:SLEW[0]IOB3:PULL[2]-~IOB3:NDRIVE[2]IOB3:PDRIVE[2]IOB3:SLEW[5]
IOBS.S3E.B3 bittile 2
RowColumn
0123456789101112131415161718
0 ---IOB0:SLEW[1]IOB0:SLEW[2]IOB0:OUTPUT_ENABLE[0]---IOB0:I_DELAY[2]IOB1:I_DELAY[0]IOB0:I_DELAY[1]--IOB1:NDRIVE[3]IOB1:NDRIVE[1]-IOB1:PDRIVE[2]IOB1:SLEW[4]
1 IOB0:PULL[1]IOB0:PULL[2]IOB1:OUTPUT_DIFF_GROUP[0]-IOB0:IBUF_MODE[2]IOB0:PDRIVE[2]IOB0:OUTPUT_ENABLE[1]--IOB0:IFF_DELAY[0]IOB1:I_DELAY[1]IOB0:I_DELAY[0]IOB1:IBUF_MODE[0]IOB1:SLEW[0]-IOB1:PULL[1]-IOB1:SLEW[2]IOB1:OUTPUT_ENABLE[0]
2 IOB0:NDRIVE[1]~IOB0:PDRIVE[3]IOB0:SLEW[0]~IOB0:NDRIVE[2]IOB0:IBUF_MODE[1]IOB0:SLEW[3]IOB0:SLEW[5]--IOB0:IFF_DELAY[1]IOB1:I_DELAY[2]IOB1:DELAY_COMMON~IOB1:NDRIVE[2]-~IOB1:PDRIVE[3]IOB1:PULL[0]IOB1:IBUF_MODE[2]IOB1:PDRIVE[0]IOB1:SLEW[5]
3 IOB0:PULL[0]IOB0:NDRIVE[3]-IOB0:IBUF_MODE[0]IOB0:OUTPUT_MISCIOB0:SLEW[4]---IOB0:DELAY_COMMONIOB1:IFF_DELAY[0]IOB1:IFF_DELAY[1]IOB1:OUTPUT_DIFF[1]IOB1:OUTPUT_DIFF[0]IOB1:PULL[2]-IOB1:SLEW[1]IOB1:SLEW[3]-
4 ~IOB0:PDRIVE[1]-IOB0:NDRIVE[0]----IOB0:PDRIVE[0]--IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF_GROUP[1]IOB1:OUTPUT_MISC--~IOB1:PDRIVE[1]-IOB1:IBUF_MODE[1]IOB1:OUTPUT_ENABLE[1]
IOB0:IFF_DELAY[2, 9, 2][2, 9, 1]
IOB1:IFF_DELAY[2, 11, 3][2, 10, 3]
IOB2:IFF_DELAY[1, 10, 0][1, 10, 1]
IOB3:IFF_DELAY[0, 11, 2][0, 9, 0]
IOB4:IFF_DELAY[0, 6, 4][0, 6, 1]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:I_DELAY[2, 9, 0][2, 11, 0][2, 11, 1]
IOB1:I_DELAY[2, 10, 2][2, 10, 1][2, 10, 0]
IOB2:I_DELAY[1, 9, 3][1, 11, 1][1, 9, 4]
IOB3:I_DELAY[0, 11, 3][0, 9, 1][0, 11, 4]
IOB4:I_DELAY[0, 6, 2][0, 6, 0][0, 6, 3]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:DELAY_COMMON[2, 9, 3]
IOB0:OUTPUT_MISC[2, 4, 3]
IOB1:DELAY_COMMON[2, 11, 2]
IOB1:OUTPUT_MISC[2, 12, 4]
IOB2:DELAY_COMMON[1, 11, 2]
IOB2:ENABLE[1, 5, 3]
IOB3:DELAY_COMMON[0, 8, 0]
IOB3:OUTPUT_MISC[1, 15, 0]
IOB4:DELAY_COMMON[0, 7, 0]
IOB4:OUTPUT_MISC[0, 14, 1]
Non-inverted[0]
IOB0:PDRIVE[2, 1, 2][2, 5, 1][2, 0, 4][2, 7, 4]
IOB1:PDRIVE[2, 14, 2][2, 17, 0][2, 15, 4][2, 17, 2]
IOB3:PDRIVE[1, 14, 3][1, 17, 4][1, 12, 1][1, 17, 1]
IOB4:PDRIVE[0, 17, 2][0, 13, 3][0, 18, 1][0, 12, 2]
Mixed inversion~[3][2]~[1][0]
IOB0:OUTPUT_ENABLE[2, 6, 1][2, 5, 0]
IOB1:OUTPUT_DIFF[2, 12, 3][2, 13, 3]
IOB1:OUTPUT_DIFF_GROUP[2, 11, 4][2, 2, 1]
IOB1:OUTPUT_ENABLE[2, 18, 4][2, 18, 1]
IOB3:OUTPUT_ENABLE[1, 18, 3][1, 18, 0]
IOB4:OUTPUT_DIFF[0, 15, 1][0, 15, 3]
IOB4:OUTPUT_DIFF_GROUP[1, 13, 0][0, 16, 0]
IOB4:OUTPUT_ENABLE[0, 13, 2][0, 13, 0]
Non-inverted[1][0]
IOB0:IBUF_MODE[2, 4, 1][2, 4, 2][2, 3, 3]
IOB1:IBUF_MODE[2, 16, 2][2, 17, 4][2, 12, 1]
IOB3:IBUF_MODE[1, 17, 0][1, 16, 3][1, 15, 2]
IOB4:IBUF_MODE[0, 12, 0][0, 14, 4][0, 15, 2]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:NDRIVE[2, 1, 3][2, 3, 2][2, 0, 2][2, 2, 4]
IOB1:NDRIVE[2, 14, 0][2, 12, 2][2, 15, 0][2, 10, 4]
IOB3:NDRIVE[1, 14, 2][1, 16, 4][1, 12, 3][1, 13, 2]
IOB4:NDRIVE[0, 17, 4][0, 14, 0][0, 18, 2][0, 16, 1]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[2, 6, 2][2, 5, 3][2, 5, 2][2, 4, 0][2, 3, 0][2, 2, 2]
IOB1:SLEW[2, 18, 2][2, 18, 0][2, 17, 3][2, 17, 1][2, 16, 3][2, 13, 1]
IOB3:SLEW[1, 18, 4][1, 18, 2][1, 17, 3][1, 16, 1][1, 16, 0][1, 13, 4]
IOB4:SLEW[0, 14, 2][0, 13, 4][0, 12, 4][0, 12, 1][0, 10, 0][0, 16, 3]
Non-inverted[5][4][3][2][1][0]
IOB0:PULL[2, 1, 1][2, 0, 1][2, 0, 3]
IOB1:PULL[2, 14, 3][2, 15, 1][2, 15, 2]
IOB2:PULL[1, 5, 4][1, 4, 1][1, 4, 0]
IOB3:PULL[1, 14, 4][1, 10, 4][1, 12, 2]
IOB4:PULL[0, 17, 1][0, 18, 3][0, 18, 0]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[1, 6, 1][1, 6, 0][1, 5, 1]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.B4

IOBS.S3E.B4 bittile 0
RowColumn
0123456789101112131415161718
0 IOB4:SLEW[1]--~IOB4:PDRIVE[3]-IOB4:PULL[1]-IOB5:PULL[2]-IOB5:IBUF_MODE[0]IOB5:IBUF_MODE[2]IOB5:IBUF_MODE[1]--IOB5:DELAY_COMMONIOB6:IBUF_MODE[0]-IOB6:PULL[2]IOB6:PULL[0]
1 IOB4:SLEW[2]IOB4:NDRIVE[0]IOB4:OUTPUT_DIFF_GROUP[0]IOB4:NDRIVE[3]IOB5:PULL[1]~IOB4:PDRIVE[1]IOB4:NDRIVE[1]-IOB5:VREFIOB5:I_DELAY[0]-IOB5:IFF_DELAY[0]--IOB6:DELAY_COMMONIOB6:ENABLE--IOB6:PULL[1]
2 -IOB4:SLEW[0]-IOB5:PULL[0]IOB5:ENABLE-IOB4:PULL[0]--IOB5:IFF_DELAY[1]IOB6:IBUF_MODE[2]IOB5:I_DELAY[1]-------
3 IOB4:IBUF_MODE[1]----IOB4:PULL[2]IOB4:OUTPUT_DIFF[1]--IOB5:I_DELAY[2]-----IOB6:I_DELAY[1]IOB6:I_DELAY[0]--
4 ~IOB4:NDRIVE[2]IOB4:OUTPUT_DIFF[0]IOB4:IBUF_MODE[0]----------IOB6:IBUF_MODE[1]-IOB6:IFF_DELAY[0]IOB6:I_DELAY[2]IOB6:IFF_DELAY[1]-
IOBS.S3E.B4 bittile 1
RowColumn
0123456789101112131415161718
0 IOB3:PULL[1]--IOB3:OUTPUT_ENABLE[0]IOB3:SLEW[2]IOB3:SLEW[4]IOB3:IBUF_MODE[2]-IOB3:OUTPUT_ENABLE[1]-----IOB3:DELAY_COMMON--IOB4:OUTPUT_ENABLE[0]IOB4:IBUF_MODE[2]
1 -IOB3:SLEW[0]IOB3:IBUF_MODE[1]IOB3:SLEW[1]IOB3:PDRIVE[2]~IOB3:NDRIVE[2]IOB3:SLEW[5]--IOB3:I_DELAY[0]-IOB3:IFF_DELAY[0]--IOB4:DELAY_COMMON---IOB4:SLEW[5]
2 IOB3:NDRIVE[1]-IOB3:NDRIVE[3]-IOB3:SLEW[3]-IOB3:OUTPUT_MISCIOB3:IBUF_MODE[0]-IOB3:IFF_DELAY[1]-IOB3:I_DELAY[1]----IOB4:OUTPUT_MISCIOB4:SLEW[3]IOB4:OUTPUT_ENABLE[1]
3 IOB3:PULL[0]IOB3:NDRIVE[0]-IOB3:PDRIVE[0]-IOB3:VREF---IOB3:I_DELAY[2]-----IOB4:I_DELAY[1]IOB4:I_DELAY[0]IOB4:SLEW[4]IOB4:PDRIVE[2]
4 ~IOB3:PDRIVE[1]IOB4:OUTPUT_DIFF_GROUP[1]IOB3:PULL[2]--~IOB3:PDRIVE[3]---------IOB4:IFF_DELAY[0]IOB4:I_DELAY[2]IOB4:IFF_DELAY[1]IOB4:PDRIVE[0]
IOBS.S3E.B4 bittile 2
RowColumn
012345678910111213
0 IOB1:SLEW[1]--~IOB1:PDRIVE[3]-IOB1:PULL[1]-~IOB2:PDRIVE[1]IOB2:PULL[2]IOB2:IBUF_MODE[0]IOB2:IBUF_MODE[2]IOB2:SLEW[2]IOB2:SLEW[4]-
1 IOB1:SLEW[2]IOB1:NDRIVE[0]IOB1:OUTPUT_DIFF_GROUP[0]IOB1:NDRIVE[3]IOB2:PULL[1]~IOB1:PDRIVE[1]IOB1:NDRIVE[1]-IOB2:VREF-IOB2:PDRIVE[0]~IOB2:NDRIVE[2]IOB2:OUTPUT_ENABLE[0]IOB2:SLEW[5]
2 -IOB1:SLEW[0]-IOB2:PULL[0]IOB2:NDRIVE[1]-IOB1:PULL[0]---IOB2:SLEW[1]IOB2:IBUF_MODE[1]-IOB2:PDRIVE[2]
3 IOB1:IBUF_MODE[1]--~IOB2:PDRIVE[3]IOB2:NDRIVE[3]IOB1:PULL[2]IOB1:OUTPUT_DIFF[1]IOB2:NDRIVE[0]--IOB2:IFF_DELAY[1]---
4 ~IOB1:NDRIVE[2]IOB1:OUTPUT_DIFF[0]IOB1:IBUF_MODE[0]IOB2:I_DELAY[1]IOB2:IFF_DELAY[0]-IOB2:I_DELAY[2]-IOB2:SLEW[0]IOB2:OUTPUT_MISCIOB2:I_DELAY[0]IOB2:SLEW[3]IOB2:DELAY_COMMONIOB2:OUTPUT_ENABLE[1]
IOBS.S3E.B4 bittile 3
RowColumn
0123456789101112131415161718
0 IOB0:PULL[1]--IOB0:OUTPUT_ENABLE[0]IOB0:SLEW[2]IOB0:SLEW[4]IOB0:IBUF_MODE[2]-IOB0:OUTPUT_ENABLE[1]-----IOB0:I_DELAY[2]IOB1:DELAY_COMMON-IOB1:OUTPUT_ENABLE[0]IOB1:IBUF_MODE[2]
1 -IOB0:SLEW[0]IOB0:IBUF_MODE[1]IOB0:SLEW[1]IOB0:PDRIVE[2]~IOB0:NDRIVE[2]IOB0:SLEW[5]-------IOB0:IFF_DELAY[0]---IOB1:SLEW[5]
2 IOB0:NDRIVE[1]-IOB0:NDRIVE[3]-IOB0:SLEW[3]-IOB0:OUTPUT_MISCIOB0:IBUF_MODE[0]----IOB0:I_DELAY[0]-IOB0:I_DELAY[1]-IOB1:OUTPUT_MISCIOB1:SLEW[3]IOB1:OUTPUT_ENABLE[1]
3 IOB0:PULL[0]IOB0:NDRIVE[0]-IOB0:PDRIVE[0]-IOB0:VREF--------IOB0:IFF_DELAY[1]IOB1:I_DELAY[1]IOB1:I_DELAY[0]IOB1:SLEW[4]IOB1:PDRIVE[2]
4 ~IOB0:PDRIVE[1]IOB1:OUTPUT_DIFF_GROUP[1]IOB0:PULL[2]--~IOB0:PDRIVE[3]--------IOB0:DELAY_COMMONIOB1:IFF_DELAY[0]IOB1:I_DELAY[2]IOB1:IFF_DELAY[1]IOB1:PDRIVE[0]
IOB0:NDRIVE[3, 2, 2][3, 5, 1][3, 0, 2][3, 1, 3]
IOB1:NDRIVE[2, 3, 1][2, 0, 4][2, 6, 1][2, 1, 1]
IOB2:NDRIVE[2, 4, 3][2, 11, 1][2, 4, 2][2, 7, 3]
IOB3:NDRIVE[1, 2, 2][1, 5, 1][1, 0, 2][1, 1, 3]
IOB4:NDRIVE[0, 3, 1][0, 0, 4][0, 6, 1][0, 1, 1]
Mixed inversion[3]~[2][1][0]
IOB0:SLEW[3, 6, 1][3, 5, 0][3, 4, 2][3, 4, 0][3, 3, 1][3, 1, 1]
IOB1:SLEW[3, 18, 1][3, 17, 3][3, 17, 2][2, 0, 1][2, 0, 0][2, 1, 2]
IOB2:SLEW[2, 13, 1][2, 12, 0][2, 11, 4][2, 11, 0][2, 10, 2][2, 8, 4]
IOB3:SLEW[1, 6, 1][1, 5, 0][1, 4, 2][1, 4, 0][1, 3, 1][1, 1, 1]
IOB4:SLEW[1, 18, 1][1, 17, 3][1, 17, 2][0, 0, 1][0, 0, 0][0, 1, 2]
Non-inverted[5][4][3][2][1][0]
IOB0:OUTPUT_ENABLE[3, 8, 0][3, 3, 0]
IOB1:OUTPUT_DIFF[2, 6, 3][2, 1, 4]
IOB1:OUTPUT_DIFF_GROUP[3, 1, 4][2, 2, 1]
IOB1:OUTPUT_ENABLE[3, 18, 2][3, 17, 0]
IOB2:OUTPUT_ENABLE[2, 13, 4][2, 12, 1]
IOB3:OUTPUT_ENABLE[1, 8, 0][1, 3, 0]
IOB4:OUTPUT_DIFF[0, 6, 3][0, 1, 4]
IOB4:OUTPUT_DIFF_GROUP[1, 1, 4][0, 2, 1]
IOB4:OUTPUT_ENABLE[1, 18, 2][1, 17, 0]
Non-inverted[1][0]
IOB0:IBUF_MODE[3, 6, 0][3, 2, 1][3, 7, 2]
IOB1:IBUF_MODE[3, 18, 0][2, 0, 3][2, 2, 4]
IOB3:IBUF_MODE[1, 6, 0][1, 2, 1][1, 7, 2]
IOB4:IBUF_MODE[1, 18, 0][0, 0, 3][0, 2, 4]
IOB5:IBUF_MODE[0, 10, 0][0, 11, 0][0, 9, 0]
IOB6:IBUF_MODE[0, 10, 2][0, 13, 4][0, 15, 0]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:PULL[3, 2, 4][3, 0, 0][3, 0, 3]
IOB1:PULL[2, 5, 3][2, 5, 0][2, 6, 2]
IOB2:PULL[2, 8, 0][2, 4, 1][2, 3, 2]
IOB3:PULL[1, 2, 4][1, 0, 0][1, 0, 3]
IOB4:PULL[0, 5, 3][0, 5, 0][0, 6, 2]
IOB5:PULL[0, 7, 0][0, 4, 1][0, 3, 2]
IOB6:PULL[0, 17, 0][0, 18, 1][0, 18, 0]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DELAY_COMMON[3, 14, 4]
IOB0:OUTPUT_MISC[3, 6, 2]
IOB0:VREF[3, 5, 3]
IOB1:DELAY_COMMON[3, 15, 0]
IOB1:OUTPUT_MISC[3, 16, 2]
IOB2:DELAY_COMMON[2, 12, 4]
IOB2:OUTPUT_MISC[2, 9, 4]
IOB2:VREF[2, 8, 1]
IOB3:DELAY_COMMON[1, 14, 0]
IOB3:OUTPUT_MISC[1, 6, 2]
IOB3:VREF[1, 5, 3]
IOB4:DELAY_COMMON[1, 14, 1]
IOB4:OUTPUT_MISC[1, 16, 2]
IOB5:DELAY_COMMON[0, 14, 0]
IOB5:ENABLE[0, 4, 2]
IOB5:VREF[0, 8, 1]
IOB6:DELAY_COMMON[0, 14, 1]
IOB6:ENABLE[0, 15, 1]
Non-inverted[0]
IOB0:I_DELAY[3, 14, 0][3, 14, 2][3, 12, 2]
IOB1:I_DELAY[3, 16, 4][3, 15, 3][3, 16, 3]
IOB2:I_DELAY[2, 6, 4][2, 3, 4][2, 10, 4]
IOB3:I_DELAY[1, 9, 3][1, 11, 2][1, 9, 1]
IOB4:I_DELAY[1, 16, 4][1, 15, 3][1, 16, 3]
IOB5:I_DELAY[0, 9, 3][0, 11, 2][0, 9, 1]
IOB6:I_DELAY[0, 16, 4][0, 15, 3][0, 16, 3]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB0:IFF_DELAY[3, 14, 3][3, 14, 1]
IOB1:IFF_DELAY[3, 17, 4][3, 15, 4]
IOB2:IFF_DELAY[2, 10, 3][2, 4, 4]
IOB3:IFF_DELAY[1, 9, 2][1, 11, 1]
IOB4:IFF_DELAY[1, 17, 4][1, 15, 4]
IOB5:IFF_DELAY[0, 9, 2][0, 11, 1]
IOB6:IFF_DELAY[0, 17, 4][0, 15, 4]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:PDRIVE[3, 5, 4][3, 4, 1][3, 0, 4][3, 3, 3]
IOB1:PDRIVE[2, 3, 0][3, 18, 3][2, 5, 1][3, 18, 4]
IOB2:PDRIVE[2, 3, 3][2, 13, 2][2, 7, 0][2, 10, 1]
IOB3:PDRIVE[1, 5, 4][1, 4, 1][1, 0, 4][1, 3, 3]
IOB4:PDRIVE[0, 3, 0][1, 18, 3][0, 5, 1][1, 18, 4]
Mixed inversion~[3][2]~[1][0]
IOB2:IBUF_MODE[2, 10, 0][2, 11, 2][2, 9, 0]
NONE000
CMOS_LV001
VREF011
CMOS_HV111

IOBS.S3E.L1

IOBS.S3E.L1 bittile 0
RowColumn
01
0 IOB0:IBUF_MODE[0]-
1 IOB0:PULL[1]-
2 --
3 IOB0:PULL[0]-
4 ~IOB0:PDRIVE[1]-
5 --
6 IOB0:PULL[2]-
7 IOB0:NDRIVE[3]IOB0:NDRIVE[0]
8 --
9 --
10 ~IOB0:PDRIVE[3]-
11 IOB0:VREF-
12 IOB0:OUTPUT_ENABLE[0]-
13 --
14 -IOB0:OUTPUT_ENABLE[1]
15 --
16 --
17 --
18 --
19 --
20 -~IOB0:NDRIVE[2]
21 IOB0:IBUF_MODE[1]-
22 IOB0:OUTPUT_MISC-
23 --
24 IOB0:SLEW[1]-
25 IOB0:SLEW[2]-
26 IOB0:IBUF_MODE[2]-
27 IOB0:PDRIVE[0]-
28 --
29 IOB0:SLEW[3]-
30 IOB0:PDRIVE[2]-
31 IOB0:SLEW[4]-
32 IOB0:SLEW[0]-
33 --
34 IOB0:SLEW[5]-
35 --
36 IOB0:NDRIVE[1]-
37 --
38 --
39 --
40 --
41 --
42 --
43 -IOB0:DELAY_COMMON
44 --
45 --
46 --
47 --
48 --
49 --
50 --
51 -IOB0:I_DELAY[1]
52 --
53 -IOB0:IFF_DELAY[0]
54 -IOB0:I_DELAY[2]
55 -IOB0:I_DELAY[0]
56 -IOB0:IFF_DELAY[1]
IOB0:IBUF_MODE[0, 0, 26][0, 0, 21][0, 0, 0]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB0:PULL[0, 0, 6][0, 0, 1][0, 0, 3]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DELAY_COMMON[0, 1, 43]
IOB0:OUTPUT_MISC[0, 0, 22]
IOB0:VREF[0, 0, 11]
Non-inverted[0]
IOB0:OUTPUT_ENABLE[0, 1, 14][0, 0, 12]
Non-inverted[1][0]
IOB0:PDRIVE[0, 0, 10][0, 0, 30][0, 0, 4][0, 0, 27]
Mixed inversion~[3][2]~[1][0]
IOB0:SLEW[0, 0, 34][0, 0, 31][0, 0, 29][0, 0, 25][0, 0, 24][0, 0, 32]
Non-inverted[5][4][3][2][1][0]
IOB0:NDRIVE[0, 0, 7][0, 1, 20][0, 0, 36][0, 1, 7]
Mixed inversion[3]~[2][1][0]
IOB0:IFF_DELAY[0, 1, 56][0, 1, 53]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:I_DELAY[0, 1, 54][0, 1, 51][0, 1, 55]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111

IOBS.S3E.L2

IOBS.S3E.L2 bittile 0
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 --
10 --
11 --
12 --
13 --
14 --
15 --
16 --
17 --
18 --
19 --
20 --
21 --
22 --
23 --
24 --
25 --
26 --
27 --
28 --
29 --
30 --
31 --
32 --
33 --
34 --
35 --
36 --
37 --
38 --
39 --
40 --
41 IOB0:PDRIVE[0]-
42 IOB0:SLEW[1]-
43 --
44 IOB0:OUTPUT_ENABLE[0]-
45 --
46 IOB0:OUTPUT_ENABLE[1]IOB0:SLEW[5]
47 IOB0:SLEW[2]-
48 IOB0:IBUF_MODE[2]-
49 IOB0:PDRIVE[2]-
50 IOB0:SLEW[3]-
51 IOB0:SLEW[4]-
52 -~IOB0:NDRIVE[2]
53 IOB0:OUTPUT_MISC-
54 --
55 IOB0:IBUF_MODE[1]-
56 IOB0:IBUF_MODE[0]-
57 --
58 -IOB0:NDRIVE[0]
59 IOB1:OUTPUT_DIFF_GROUP[0]-
60 --
61 IOB0:SLEW[0]-
IOBS.S3E.L2 bittile 1
RowColumn
01
0 -IOB1:DELAY_COMMON
1 IOB0:NDRIVE[1]-
2 IOB0:PULL[0]-
3 ~IOB0:PDRIVE[1]-
4 --
5 IOB0:PULL[1]-
6 --
7 IOB0:NDRIVE[3]IOB0:VREF
8 ~IOB0:PDRIVE[3]-
9 IOB0:PULL[2]IOB1:I_DELAY[1]
10 IOB1:PULL[0]IOB1:IFF_DELAY[0]
11 -IOB1:I_DELAY[2]
12 ~IOB1:PDRIVE[1]IOB1:I_DELAY[0]
13 -IOB1:IFF_DELAY[1]
14 IOB1:NDRIVE[1]~IOB1:PDRIVE[3]
15 --
16 --
17 IOB1:PULL[2]-
18 IOB1:NDRIVE[3]-
19 --
20 --
21 IOB1:SLEW[0]-
22 IOB1:NDRIVE[0]-
23 --
24 --
25 IOB1:OUTPUT_DIFF[0]-
26 IOB1:IBUF_MODE[0]IOB1:OUTPUT_DIFF[1]
27 IOB1:OUTPUT_MISC-
28 IOB1:SLEW[1]-
29 -IOB0:IFF_DELAY[1]
30 IOB1:SLEW[2]IOB0:I_DELAY[0]
31 IOB1:IBUF_MODE[1]IOB0:I_DELAY[2]
32 IOB1:IBUF_MODE[2]IOB0:IFF_DELAY[0]
33 -IOB0:I_DELAY[1]
34 --
35 IOB1:SLEW[3]-
36 IOB1:PDRIVE[2]-
37 IOB1:SLEW[4]-
38 --
39 IOB1:PULL[1]IOB1:OUTPUT_ENABLE[1]
40 IOB1:SLEW[5]-
41 -IOB0:DELAY_COMMON
42 IOB1:OUTPUT_ENABLE[0]-
43 IOB1:OUTPUT_DIFF_GROUP[1]-
44 ~IOB1:NDRIVE[2]-
45 --
46 IOB1:PDRIVE[0]-
IOB0:PDRIVE[1, 0, 8][0, 0, 49][1, 0, 3][0, 0, 41]
IOB1:PDRIVE[1, 1, 14][1, 0, 36][1, 0, 12][1, 0, 46]
Mixed inversion~[3][2]~[1][0]
IOB0:OUTPUT_ENABLE[0, 0, 46][0, 0, 44]
IOB1:OUTPUT_DIFF[1, 1, 26][1, 0, 25]
IOB1:OUTPUT_DIFF_GROUP[1, 0, 43][0, 0, 59]
IOB1:OUTPUT_ENABLE[1, 1, 39][1, 0, 42]
Non-inverted[1][0]
IOB0:DELAY_COMMON[1, 1, 41]
IOB0:OUTPUT_MISC[0, 0, 53]
IOB0:VREF[1, 1, 7]
IOB1:DELAY_COMMON[1, 1, 0]
IOB1:OUTPUT_MISC[1, 0, 27]
Non-inverted[0]
IOB0:IBUF_MODE[0, 0, 48][0, 0, 55][0, 0, 56]
IOB1:IBUF_MODE[1, 0, 32][1, 0, 31][1, 0, 26]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB0:SLEW[0, 1, 46][0, 0, 51][0, 0, 50][0, 0, 47][0, 0, 42][0, 0, 61]
IOB1:SLEW[1, 0, 40][1, 0, 37][1, 0, 35][1, 0, 30][1, 0, 28][1, 0, 21]
Non-inverted[5][4][3][2][1][0]
IOB0:NDRIVE[1, 0, 7][0, 1, 52][1, 0, 1][0, 1, 58]
IOB1:NDRIVE[1, 0, 18][1, 0, 44][1, 0, 14][1, 0, 22]
Mixed inversion[3]~[2][1][0]
IOB0:PULL[1, 0, 9][1, 0, 5][1, 0, 2]
IOB1:PULL[1, 0, 17][1, 0, 39][1, 0, 10]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:IFF_DELAY[1, 1, 29][1, 1, 32]
IOB1:IFF_DELAY[1, 1, 13][1, 1, 10]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:I_DELAY[1, 1, 31][1, 1, 33][1, 1, 30]
IOB1:I_DELAY[1, 1, 11][1, 1, 9][1, 1, 12]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111

IOBS.S3E.L3

IOBS.S3E.L3 bittile 0
RowColumn
01
0 --
1 IOB0:PULL[1]-
2 --
3 IOB0:PULL[0]-
4 --
5 --
6 IOB0:PULL[2]-
7 IOB0:ENABLE-
8 IOB0:VREF-
9 --
10 --
11 --
12 --
13 --
14 --
15 --
16 --
17 --
18 IOB0:IBUF_MODE[0]-
19 IOB0:IBUF_MODE[1]-
20 --
21 --
22 --
23 IOB0:IBUF_MODE[2]-
24 --
25 --
26 --
27 IOB1:NDRIVE[1]-
28 --
29 ~IOB1:PDRIVE[1]-
30 IOB1:PULL[0]-
31 IOB1:PULL[1]-
32 --
33 IOB1:PULL[2]-
34 IOB1:OUTPUT_MISC-
35 ~IOB1:PDRIVE[3]-
36 ~IOB1:NDRIVE[2]-
37 IOB1:NDRIVE[3]-
38 IOB1:VREF-
39 IOB1:SLEW[1]-
40 --
41 --
42 --
43 -IOB0:DELAY_COMMON
44 IOB1:NDRIVE[0]-
45 --
46 IOB1:SLEW[0]-
47 --
48 --
49 IOB1:IBUF_MODE[0]-
50 --
51 IOB1:SLEW[2]IOB0:I_DELAY[1]
52 IOB1:IBUF_MODE[2]IOB1:IBUF_MODE[1]
53 IOB1:PDRIVE[0]IOB0:IFF_DELAY[0]
54 -IOB0:I_DELAY[2]
55 IOB1:SLEW[3]IOB0:I_DELAY[0]
56 IOB1:PDRIVE[2]IOB0:IFF_DELAY[1]
57 IOB1:SLEW[4]-
58 IOB1:OUTPUT_ENABLE[0]IOB1:OUTPUT_ENABLE[1]
59 --
60 --
61 --
62 IOB1:SLEW[5]-
IOBS.S3E.L3 bittile 1
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 --
10 --
11 --
12 --
13 --
14 --
15 --
16 --
17 --
18 --
19 --
20 --
21 --
22 --
23 --
24 --
25 --
26 --
27 --
28 --
29 --
30 --
31 --
32 --
33 --
34 --
35 --
36 --
37 --
38 --
39 --
40 --
41 IOB2:PDRIVE[0]-
42 IOB2:SLEW[1]-
43 -IOB1:DELAY_COMMON
44 IOB2:OUTPUT_ENABLE[0]-
45 --
46 IOB2:OUTPUT_ENABLE[1]IOB2:SLEW[5]
47 IOB2:SLEW[2]-
48 IOB2:IBUF_MODE[2]-
49 IOB2:PDRIVE[2]-
50 IOB2:SLEW[3]-
51 IOB2:SLEW[4]IOB1:I_DELAY[1]
52 -~IOB2:NDRIVE[2]
53 IOB2:OUTPUT_MISCIOB1:IFF_DELAY[0]
54 -IOB1:I_DELAY[2]
55 IOB2:IBUF_MODE[1]IOB1:I_DELAY[0]
56 IOB2:IBUF_MODE[0]IOB1:IFF_DELAY[1]
57 --
58 -IOB2:NDRIVE[0]
59 IOB3:OUTPUT_DIFF_GROUP[0]-
60 --
61 IOB2:SLEW[0]-
IOBS.S3E.L3 bittile 2
RowColumn
01
0 -IOB3:DELAY_COMMON
1 IOB2:NDRIVE[1]-
2 IOB2:PULL[0]-
3 ~IOB2:PDRIVE[1]-
4 --
5 IOB2:PULL[1]-
6 --
7 IOB2:NDRIVE[3]-
8 ~IOB2:PDRIVE[3]-
9 IOB2:PULL[2]IOB3:I_DELAY[1]
10 IOB3:PULL[0]IOB3:IFF_DELAY[0]
11 -IOB3:I_DELAY[2]
12 ~IOB3:PDRIVE[1]IOB3:I_DELAY[0]
13 -IOB3:IFF_DELAY[1]
14 IOB3:NDRIVE[1]~IOB3:PDRIVE[3]
15 --
16 --
17 IOB3:PULL[2]-
18 IOB3:NDRIVE[3]-
19 --
20 --
21 IOB3:SLEW[0]-
22 IOB3:NDRIVE[0]-
23 --
24 --
25 IOB3:OUTPUT_DIFF[0]-
26 IOB3:IBUF_MODE[0]IOB3:OUTPUT_DIFF[1]
27 IOB3:OUTPUT_MISC-
28 IOB3:SLEW[1]-
29 -IOB2:IFF_DELAY[1]
30 IOB3:SLEW[2]IOB2:I_DELAY[0]
31 IOB3:IBUF_MODE[1]IOB2:I_DELAY[2]
32 IOB3:IBUF_MODE[2]IOB2:IFF_DELAY[0]
33 -IOB2:I_DELAY[1]
34 --
35 IOB3:SLEW[3]-
36 IOB3:PDRIVE[2]-
37 IOB3:SLEW[4]-
38 --
39 IOB3:PULL[1]IOB3:OUTPUT_ENABLE[1]
40 IOB3:SLEW[5]-
41 -IOB2:DELAY_COMMON
42 IOB3:OUTPUT_ENABLE[0]-
43 IOB3:OUTPUT_DIFF_GROUP[1]-
44 ~IOB3:NDRIVE[2]-
45 --
46 IOB3:PDRIVE[0]-
IOB0:PULL[0, 0, 6][0, 0, 1][0, 0, 3]
IOB1:PULL[0, 0, 33][0, 0, 31][0, 0, 30]
IOB2:PULL[2, 0, 9][2, 0, 5][2, 0, 2]
IOB3:PULL[2, 0, 17][2, 0, 39][2, 0, 10]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DELAY_COMMON[0, 1, 43]
IOB0:ENABLE[0, 0, 7]
IOB0:VREF[0, 0, 8]
IOB1:DELAY_COMMON[1, 1, 43]
IOB1:OUTPUT_MISC[0, 0, 34]
IOB1:VREF[0, 0, 38]
IOB2:DELAY_COMMON[2, 1, 41]
IOB2:OUTPUT_MISC[1, 0, 53]
IOB3:DELAY_COMMON[2, 1, 0]
IOB3:OUTPUT_MISC[2, 0, 27]
Non-inverted[0]
IOB0:IBUF_MODE[0, 0, 23][0, 0, 19][0, 0, 18]
IOB1:IBUF_MODE[0, 0, 52][0, 1, 52][0, 0, 49]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB1:NDRIVE[0, 0, 37][0, 0, 36][0, 0, 27][0, 0, 44]
IOB2:NDRIVE[2, 0, 7][1, 1, 52][2, 0, 1][1, 1, 58]
IOB3:NDRIVE[2, 0, 18][2, 0, 44][2, 0, 14][2, 0, 22]
Mixed inversion[3]~[2][1][0]
IOB1:SLEW[0, 0, 62][0, 0, 57][0, 0, 55][0, 0, 51][0, 0, 39][0, 0, 46]
IOB2:SLEW[1, 1, 46][1, 0, 51][1, 0, 50][1, 0, 47][1, 0, 42][1, 0, 61]
IOB3:SLEW[2, 0, 40][2, 0, 37][2, 0, 35][2, 0, 30][2, 0, 28][2, 0, 21]
Non-inverted[5][4][3][2][1][0]
IOB1:PDRIVE[0, 0, 35][0, 0, 56][0, 0, 29][0, 0, 53]
IOB2:PDRIVE[2, 0, 8][1, 0, 49][2, 0, 3][1, 0, 41]
IOB3:PDRIVE[2, 1, 14][2, 0, 36][2, 0, 12][2, 0, 46]
Mixed inversion~[3][2]~[1][0]
IOB1:OUTPUT_ENABLE[0, 1, 58][0, 0, 58]
IOB2:OUTPUT_ENABLE[1, 0, 46][1, 0, 44]
IOB3:OUTPUT_DIFF[2, 1, 26][2, 0, 25]
IOB3:OUTPUT_DIFF_GROUP[2, 0, 43][1, 0, 59]
IOB3:OUTPUT_ENABLE[2, 1, 39][2, 0, 42]
Non-inverted[1][0]
IOB0:IFF_DELAY[0, 1, 56][0, 1, 53]
IOB1:IFF_DELAY[1, 1, 56][1, 1, 53]
IOB2:IFF_DELAY[2, 1, 29][2, 1, 32]
IOB3:IFF_DELAY[2, 1, 13][2, 1, 10]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:I_DELAY[0, 1, 54][0, 1, 51][0, 1, 55]
IOB1:I_DELAY[1, 1, 54][1, 1, 51][1, 1, 55]
IOB2:I_DELAY[2, 1, 31][2, 1, 33][2, 1, 30]
IOB3:I_DELAY[2, 1, 11][2, 1, 9][2, 1, 12]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111
IOB2:IBUF_MODE[1, 0, 48][1, 0, 55][1, 0, 56]
IOB3:IBUF_MODE[2, 0, 32][2, 0, 31][2, 0, 26]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111

IOBS.S3E.L4

IOBS.S3E.L4 bittile 0
RowColumn
01
0 --
1 IOB0:PULL[1]-
2 --
3 IOB0:PULL[0]-
4 --
5 --
6 IOB0:PULL[2]-
7 IOB0:ENABLE-
8 IOB0:VREF-
9 --
10 --
11 --
12 --
13 --
14 --
15 --
16 --
17 --
18 IOB0:IBUF_MODE[0]-
19 IOB0:IBUF_MODE[1]-
20 --
21 --
22 --
23 IOB0:IBUF_MODE[2]-
24 --
25 --
26 --
27 IOB1:NDRIVE[1]-
28 --
29 ~IOB1:PDRIVE[1]-
30 IOB1:PULL[0]-
31 IOB1:PULL[1]-
32 --
33 IOB1:PULL[2]-
34 IOB1:OUTPUT_MISC-
35 ~IOB1:PDRIVE[3]-
36 ~IOB1:NDRIVE[2]-
37 IOB1:NDRIVE[3]-
38 IOB1:VREF-
39 IOB1:SLEW[1]-
40 --
41 --
42 --
43 IOB2:OUTPUT_DIFF_GROUP[0]IOB0:DELAY_COMMON
44 IOB1:NDRIVE[0]-
45 --
46 IOB1:SLEW[0]-
47 --
48 --
49 IOB1:IBUF_MODE[0]-
50 --
51 IOB1:SLEW[2]IOB0:I_DELAY[1]
52 IOB1:IBUF_MODE[2]IOB1:IBUF_MODE[1]
53 IOB1:PDRIVE[0]IOB0:IFF_DELAY[0]
54 -IOB0:I_DELAY[2]
55 IOB1:SLEW[3]IOB0:I_DELAY[0]
56 IOB1:PDRIVE[2]IOB0:IFF_DELAY[1]
57 IOB1:SLEW[4]-
58 IOB1:OUTPUT_ENABLE[0]IOB1:OUTPUT_ENABLE[1]
59 --
60 --
61 --
62 IOB1:SLEW[5]-
IOBS.S3E.L4 bittile 1
RowColumn
01
0 -IOB2:DELAY_COMMON
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 -IOB2:I_DELAY[1]
10 -IOB2:IFF_DELAY[0]
11 -IOB2:I_DELAY[2]
12 -IOB2:I_DELAY[0]
13 -IOB2:IFF_DELAY[1]
14 --
15 --
16 --
17 --
18 --
19 --
20 --
21 --
22 --
23 --
24 --
25 --
26 --
27 --
28 --
29 -IOB1:IFF_DELAY[1]
30 -IOB1:I_DELAY[0]
31 -IOB1:I_DELAY[2]
32 -IOB1:IFF_DELAY[0]
33 -IOB1:I_DELAY[1]
34 --
35 --
36 --
37 --
38 --
39 --
40 --
41 IOB2:PDRIVE[0]IOB1:DELAY_COMMON
42 IOB2:SLEW[1]-
43 --
44 IOB2:OUTPUT_ENABLE[0]-
45 --
46 IOB2:OUTPUT_ENABLE[1]IOB2:SLEW[5]
47 IOB2:SLEW[2]-
48 IOB2:IBUF_MODE[2]-
49 IOB2:PDRIVE[2]-
50 IOB2:SLEW[3]-
51 IOB2:SLEW[4]-
52 IOB2:OUTPUT_DIFF[1]~IOB2:NDRIVE[2]
53 IOB2:OUTPUT_MISC-
54 --
55 IOB2:IBUF_MODE[1]-
56 IOB2:IBUF_MODE[0]-
57 IOB2:OUTPUT_DIFF[0]-
58 -IOB2:NDRIVE[0]
59 IOB2:OUTPUT_DIFF_GROUP[1]-
60 --
61 IOB2:SLEW[0]-
IOBS.S3E.L4 bittile 2
RowColumn
01
0 --
1 IOB2:NDRIVE[1]-
2 IOB2:PULL[0]-
3 ~IOB2:PDRIVE[1]-
4 --
5 IOB2:PULL[1]-
6 --
7 IOB2:NDRIVE[3]-
8 ~IOB2:PDRIVE[3]-
9 IOB2:PULL[2]-
10 IOB3:PULL[0]-
11 --
12 ~IOB3:PDRIVE[1]-
13 --
14 IOB3:NDRIVE[1]~IOB3:PDRIVE[3]
15 IOB3:VREF-
16 --
17 IOB3:PULL[2]-
18 IOB3:NDRIVE[3]-
19 --
20 --
21 IOB3:SLEW[0]-
22 IOB3:NDRIVE[0]-
23 --
24 --
25 --
26 IOB3:IBUF_MODE[0]-
27 IOB3:OUTPUT_MISC-
28 IOB3:SLEW[1]-
29 --
30 IOB3:SLEW[2]-
31 IOB3:IBUF_MODE[1]-
32 IOB3:IBUF_MODE[2]-
33 IOB3:PDRIVE[0]-
34 --
35 IOB3:SLEW[3]-
36 IOB3:PDRIVE[2]-
37 IOB3:SLEW[4]-
38 --
39 IOB3:PULL[1]IOB3:OUTPUT_ENABLE[1]
40 IOB3:SLEW[5]-
41 --
42 IOB3:OUTPUT_ENABLE[0]-
43 IOB4:OUTPUT_DIFF_GROUP[0]-
44 ~IOB3:NDRIVE[2]-
IOBS.S3E.L4 bittile 3
RowColumn
01
0 -IOB4:DELAY_COMMON
1 --
2 --
3 --
4 --
5 --
6 --
7 --
8 --
9 -IOB4:I_DELAY[1]
10 -IOB4:IFF_DELAY[0]
11 -IOB4:I_DELAY[2]
12 -IOB4:I_DELAY[0]
13 -IOB4:IFF_DELAY[1]
14 --
15 --
16 --
17 --
18 --
19 --
20 --
21 IOB4:SLEW[1]-
22 IOB4:OUTPUT_ENABLE[0]-
23 --
24 IOB4:SLEW[2]-
25 IOB4:OUTPUT_ENABLE[1]-
26 IOB4:PDRIVE[2]IOB4:SLEW[5]
27 --
28 IOB4:PDRIVE[0]-
29 -IOB3:IFF_DELAY[1]
30 IOB4:IBUF_MODE[2]IOB3:I_DELAY[0]
31 IOB4:SLEW[3]IOB3:I_DELAY[2]
32 IOB4:SLEW[4]IOB3:IFF_DELAY[0]
33 IOB4:OUTPUT_MISCIOB3:I_DELAY[1]
34 IOB4:IBUF_MODE[1]-
35 --
36 IOB4:OUTPUT_DIFF[1]-
37 IOB4:IBUF_MODE[0]-
38 IOB4:OUTPUT_DIFF[0]-
39 -~IOB4:NDRIVE[2]
40 --
41 IOB4:SLEW[0]IOB3:DELAY_COMMON
42 --
43 IOB4:NDRIVE[0]-
44 IOB4:OUTPUT_DIFF_GROUP[1]-
45 --
46 -IOB4:NDRIVE[3]
47 --
48 --
49 ~IOB4:PDRIVE[3]-
50 IOB4:PULL[2]-
51 --
52 ~IOB4:PDRIVE[1]IOB4:PULL[0]
53 IOB4:NDRIVE[1]-
54 IOB4:PULL[1]-
IOB0:PULL[0, 0, 6][0, 0, 1][0, 0, 3]
IOB1:PULL[0, 0, 33][0, 0, 31][0, 0, 30]
IOB2:PULL[2, 0, 9][2, 0, 5][2, 0, 2]
IOB3:PULL[2, 0, 17][2, 0, 39][2, 0, 10]
IOB4:PULL[3, 0, 50][3, 0, 54][3, 1, 52]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:DELAY_COMMON[0, 1, 43]
IOB0:ENABLE[0, 0, 7]
IOB0:VREF[0, 0, 8]
IOB1:DELAY_COMMON[1, 1, 41]
IOB1:OUTPUT_MISC[0, 0, 34]
IOB1:VREF[0, 0, 38]
IOB2:DELAY_COMMON[1, 1, 0]
IOB2:OUTPUT_MISC[1, 0, 53]
IOB3:DELAY_COMMON[3, 1, 41]
IOB3:OUTPUT_MISC[2, 0, 27]
IOB3:VREF[2, 0, 15]
IOB4:DELAY_COMMON[3, 1, 0]
IOB4:OUTPUT_MISC[3, 0, 33]
Non-inverted[0]
IOB0:IBUF_MODE[0, 0, 23][0, 0, 19][0, 0, 18]
NONE000
CMOS_LV001
VREF011
CMOS_HV111
IOB1:OUTPUT_ENABLE[0, 1, 58][0, 0, 58]
IOB2:OUTPUT_DIFF[1, 0, 52][1, 0, 57]
IOB2:OUTPUT_DIFF_GROUP[1, 0, 59][0, 0, 43]
IOB2:OUTPUT_ENABLE[1, 0, 46][1, 0, 44]
IOB3:OUTPUT_ENABLE[2, 1, 39][2, 0, 42]
IOB4:OUTPUT_DIFF[3, 0, 36][3, 0, 38]
IOB4:OUTPUT_DIFF_GROUP[3, 0, 44][2, 0, 43]
IOB4:OUTPUT_ENABLE[3, 0, 25][3, 0, 22]
Non-inverted[1][0]
IOB1:NDRIVE[0, 0, 37][0, 0, 36][0, 0, 27][0, 0, 44]
IOB2:NDRIVE[2, 0, 7][1, 1, 52][2, 0, 1][1, 1, 58]
IOB3:NDRIVE[2, 0, 18][2, 0, 44][2, 0, 14][2, 0, 22]
IOB4:NDRIVE[3, 1, 46][3, 1, 39][3, 0, 53][3, 0, 43]
Mixed inversion[3]~[2][1][0]
IOB1:SLEW[0, 0, 62][0, 0, 57][0, 0, 55][0, 0, 51][0, 0, 39][0, 0, 46]
IOB2:SLEW[1, 1, 46][1, 0, 51][1, 0, 50][1, 0, 47][1, 0, 42][1, 0, 61]
IOB3:SLEW[2, 0, 40][2, 0, 37][2, 0, 35][2, 0, 30][2, 0, 28][2, 0, 21]
IOB4:SLEW[3, 1, 26][3, 0, 32][3, 0, 31][3, 0, 24][3, 0, 21][3, 0, 41]
Non-inverted[5][4][3][2][1][0]
IOB1:IBUF_MODE[0, 0, 52][0, 1, 52][0, 0, 49]
IOB2:IBUF_MODE[1, 0, 48][1, 0, 55][1, 0, 56]
IOB3:IBUF_MODE[2, 0, 32][2, 0, 31][2, 0, 26]
IOB4:IBUF_MODE[3, 0, 30][3, 0, 34][3, 0, 37]
NONE000
CMOS_LV001
VREF011
DIFF101
CMOS_HV111
IOB1:PDRIVE[0, 0, 35][0, 0, 56][0, 0, 29][0, 0, 53]
IOB2:PDRIVE[2, 0, 8][1, 0, 49][2, 0, 3][1, 0, 41]
IOB3:PDRIVE[2, 1, 14][2, 0, 36][2, 0, 12][2, 0, 33]
IOB4:PDRIVE[3, 0, 49][3, 0, 26][3, 0, 52][3, 0, 28]
Mixed inversion~[3][2]~[1][0]
IOB0:IFF_DELAY[0, 1, 56][0, 1, 53]
IOB1:IFF_DELAY[1, 1, 29][1, 1, 32]
IOB2:IFF_DELAY[1, 1, 13][1, 1, 10]
IOB3:IFF_DELAY[3, 1, 29][3, 1, 32]
IOB4:IFF_DELAY[3, 1, 13][3, 1, 10]
SDLY4_LDLY700
SDLY3_LDLY601
SDLY2_LDLY510
SDLY111
IOB0:I_DELAY[0, 1, 54][0, 1, 51][0, 1, 55]
IOB1:I_DELAY[1, 1, 31][1, 1, 33][1, 1, 30]
IOB2:I_DELAY[1, 1, 11][1, 1, 9][1, 1, 12]
IOB3:I_DELAY[3, 1, 31][3, 1, 33][3, 1, 30]
IOB4:I_DELAY[3, 1, 11][3, 1, 9][3, 1, 12]
LDLY13000
SDLY7001
SDLY6_LDLY12010
SDLY5_LDLY11011
SDLY4_LDLY10100
SDLY3_LDLY9101
SDLY2_LDLY8110
SDLY1111

I/O buffers — Spartan 3A

Todo

document

NameIOSTD:S3A.TB:PDRIVEIOSTD:S3A.TB:NDRIVE
[2][1][0][2][1][0]
BLVDS_25111111
HSTL_III_18111101
HSTL_I_18111010
LVCMOS12.2011001
LVCMOS15.2010001
LVCMOS15.4101001
LVCMOS15.6111001
LVCMOS18.2010001
LVCMOS18.4011001
LVCMOS18.6101001
LVCMOS18.8111010
LVCMOS25.12111010
LVCMOS25.2001001
LVCMOS25.4010001
LVCMOS25.6011001
LVCMOS25.8101010
LVCMOS33.12110011
LVCMOS33.16111011
LVCMOS33.2001001
LVCMOS33.4010001
LVCMOS33.6011001
LVCMOS33.8011010
LVTTL.12101010
LVTTL.16110011
LVTTL.2001001
LVTTL.24111101
LVTTL.4010001
LVTTL.6010001
LVTTL.8011010
OFF000000
PCI33_3111110
PCI66_3111110
PCIX111110
SSTL18_I111010
SSTL2_I011001
SSTL3_I010001
SSTL3_II011011
NameIOSTD:S3A.TB:PSLEWIOSTD:S3A.TB:NSLEW
[3][2][1][0][3][2][1][0]
BLVDS_25.2.511001100
BLVDS_25.3.311001100
HSTL_III_18.2.511001100
HSTL_III_18.3.311001100
HSTL_I_18.2.511001100
HSTL_I_18.3.311001100
LVCMOS12.FAST.2.511001100
LVCMOS12.FAST.3.311001100
LVCMOS12.QUIETIO.2.501100110
LVCMOS12.QUIETIO.3.301100110
LVCMOS12.SLOW.2.500000000
LVCMOS12.SLOW.3.300000101
LVCMOS15.FAST.2.511001100
LVCMOS15.FAST.3.311001100
LVCMOS15.QUIETIO.2.501100110
LVCMOS15.QUIETIO.3.301100110
LVCMOS15.SLOW.2.500000000
LVCMOS15.SLOW.3.300000101
LVCMOS18.FAST.2.511001100
LVCMOS18.FAST.3.311001100
LVCMOS18.QUIETIO.2.501100110
LVCMOS18.QUIETIO.3.301100110
LVCMOS18.SLOW.2.500000000
LVCMOS18.SLOW.3.300000101
LVCMOS25.FAST.2.511001100
LVCMOS25.FAST.3.311001100
LVCMOS25.QUIETIO.2.501100110
LVCMOS25.QUIETIO.3.301100110
LVCMOS25.SLOW.2.500000000
LVCMOS25.SLOW.3.300000101
LVCMOS33.FAST.2.511001100
LVCMOS33.FAST.3.311001100
LVCMOS33.QUIETIO.2.501100110
LVCMOS33.QUIETIO.3.301100110
LVCMOS33.SLOW.2.501010000
LVCMOS33.SLOW.3.301010101
LVTTL.FAST.2.511001100
LVTTL.FAST.3.311001100
LVTTL.QUIETIO.2.501100110
LVTTL.QUIETIO.3.301100110
LVTTL.SLOW.2.501010000
LVTTL.SLOW.3.301010101
PCI33_3.2.501010000
PCI33_3.3.301010101
PCI66_3.2.500001100
PCI66_3.3.300000000
PCIX.2.501010000
PCIX.3.301010101
SSTL18_I.2.511001100
SSTL18_I.3.311001100
SSTL2_I.2.511001100
SSTL2_I.3.311001100
SSTL3_I.2.511001100
SSTL3_I.3.311001100
SSTL3_II.2.511001100
SSTL3_II.3.311001100
NameIOSTD:S3A.TB:OUTPUT_DIFF
[3][2][1][0]
LVDS_250111
LVDS_330111
MINI_LVDS_250111
MINI_LVDS_330111
OFF0000
PPDS_250111
PPDS_330111
RSDS_250111
RSDS_330111
TERM0001
TMDS_331110
NameIOSTD:S3A.LR:PDRIVEIOSTD:S3A.LR:NDRIVE
[2][1][0][2][1][0]
BLVDS_25100111
HSTL_I101010
HSTL_III101101
HSTL_III_18011101
HSTL_II_18111011
HSTL_I_18011010
LVCMOS12.2010001
LVCMOS12.4011001
LVCMOS12.6110001
LVCMOS15.12111010
LVCMOS15.2001001
LVCMOS15.4010001
LVCMOS15.6011001
LVCMOS15.8101010
LVCMOS18.12101010
LVCMOS18.16111011
LVCMOS18.2001001
LVCMOS18.4010001
LVCMOS18.6010001
LVCMOS18.8011010
LVCMOS25.12011010
LVCMOS25.16101011
LVCMOS25.2001001
LVCMOS25.24111101
LVCMOS25.4001001
LVCMOS25.6010001
LVCMOS25.8010010
LVCMOS33.12011011
LVCMOS33.16011011
LVCMOS33.2001001
LVCMOS33.24110101
LVCMOS33.4001001
LVCMOS33.6010001
LVCMOS33.8010010
LVTTL.12010010
LVTTL.16011011
LVTTL.2001001
LVTTL.24101101
LVTTL.4001001
LVTTL.6001001
LVTTL.8010010
OFF000000
PCI33_3100110
PCI66_3100110
PCIX100110
SSTL18_I100010
SSTL18_II111011
SSTL2_I010001
SSTL2_II110011
SSTL3_I001001
SSTL3_II010011
NameIOSTD:S3A.LR:PSLEWIOSTD:S3A.LR:NSLEW
[3][2][1][0][3][2][1][0]
BLVDS_25.2.511001100
BLVDS_25.3.311001100
HSTL_I.2.511001100
HSTL_I.3.311001100
HSTL_III.2.511001100
HSTL_III.3.311001100
HSTL_III_18.2.511001100
HSTL_III_18.3.311001100
HSTL_II_18.2.511001100
HSTL_II_18.3.311001100
HSTL_I_18.2.511001100
HSTL_I_18.3.311001100
LVCMOS12.FAST.2.511001100
LVCMOS12.FAST.3.311001100
LVCMOS12.QUIETIO.2.501100110
LVCMOS12.QUIETIO.3.301100110
LVCMOS12.SLOW.2.500000000
LVCMOS12.SLOW.3.300000101
LVCMOS15.FAST.2.511001100
LVCMOS15.FAST.3.311001100
LVCMOS15.QUIETIO.2.501100110
LVCMOS15.QUIETIO.3.301100110
LVCMOS15.SLOW.2.500000000
LVCMOS15.SLOW.3.300000101
LVCMOS18.FAST.2.511001100
LVCMOS18.FAST.3.311001100
LVCMOS18.QUIETIO.2.501100110
LVCMOS18.QUIETIO.3.301100110
LVCMOS18.SLOW.2.500000000
LVCMOS18.SLOW.3.300000101
LVCMOS25.FAST.2.511001100
LVCMOS25.FAST.3.311001100
LVCMOS25.QUIETIO.2.501100110
LVCMOS25.QUIETIO.3.301100110
LVCMOS25.SLOW.2.500000000
LVCMOS25.SLOW.3.300000101
LVCMOS33.FAST.2.511001100
LVCMOS33.FAST.3.311001100
LVCMOS33.QUIETIO.2.501100110
LVCMOS33.QUIETIO.3.301100110
LVCMOS33.SLOW.2.501010000
LVCMOS33.SLOW.3.301010101
LVTTL.FAST.2.511001100
LVTTL.FAST.3.311001100
LVTTL.QUIETIO.2.501100110
LVTTL.QUIETIO.3.301100110
LVTTL.SLOW.2.501010000
LVTTL.SLOW.3.301010101
PCI33_3.2.501010000
PCI33_3.3.301010101
PCI66_3.2.500001100
PCI66_3.3.300000000
PCIX.2.501010000
PCIX.3.301010101
SSTL18_I.2.511001100
SSTL18_I.3.311001100
SSTL18_II.2.511001100
SSTL18_II.3.311001100
SSTL2_I.2.511001100
SSTL2_I.3.311001100
SSTL2_II.2.511001100
SSTL2_II.3.311001100
SSTL3_I.2.511001100
SSTL3_I.3.311001100
SSTL3_II.2.511001100
SSTL3_II.3.311001100

IOBS.S3A.T2

IOBS.S3A.T2 bittile 0
RowColumn
0123456789101112131415161718
0 -IOB1:PSLEW[2]IOB1:NSLEW[2]~IOB2:I_DELAY[0]IOB2:DELAY_VARIABLE~IOB1:I_DELAY[1]IOB1:PCI_CLAMPIOB1:PULL[1]~IOB1:I_DELAY[2]-----IOB0:SUSPEND[3]IOB0:VREF---
1 -IOB1:PSLEW[0]~IOB2:I_DELAY[2]IOB1:OUTPUT_ENABLE[1]IOB1:IBUF_MODE[0]IOB1:PULL[2]~IOB2:I_DELAY[1]-IOB1:OUTPUT_DIFF[0]-IOB2:PULL[0]IOB0:PULL[1]IOB0:IBUF_MODE[2]~IOB0:PDRIVE[1]IOB0:IBUF_MODE[0]~IOB0:I_DELAY[0]IOB0:OUTPUT_ENABLE[1]IOB0:PSLEW[0]IOB0:PSLEW[3]
2 -IOB1:PSLEW[1]IOB1:NSLEW[1]IOB1:VREFIOB1:SUSPEND[1]IOB1:SUSPEND[0]~IOB1:PDRIVE[1]IOB1:PDRIVE[2]IOB1:OUTPUT_DIFF[3]-IOB2:PULL[1]IOB1:OUTPUT_DIFF_GROUP[1]IOB0:NDRIVE[0]IOB0:PDRIVE[0]IOB0:SUSPEND[1]-IOB0:NSLEW[1]IOB0:NSLEW[2]IOB0:PSLEW[1]
3 -IOB1:PCI_INPUTIOB1:DELAY_VARIABLEIOB1:SUSPEND[2]IOB1:IBUF_MODE[1]IOB1:NDRIVE[0]IOB1:PDRIVE[0]IOB1:OUTPUT_DIFF[1]IOB1:PULL[0]IOB0:PULL[0]-IOB0:PDRIVE[2]IOB0:PCI_CLAMPIOB0:NDRIVE[2]IOB0:IBUF_MODE[1]IOB0:DELAY_VARIABLEIOB0:NSLEW[0]-IOB0:PCI_INPUT
4 -IOB1:PSLEW[3]IOB1:OUTPUT_ENABLE[0]-IOB1:SUSPEND[3]IOB1:IBUF_MODE[2]IOB1:NDRIVE[2]~IOB1:NDRIVE[1]IOB1:OUTPUT_DIFF_GROUP[0]--IOB1:OUTPUT_DIFF[2]IOB0:SUSPEND[0]~IOB0:NDRIVE[1]~IOB0:I_DELAY[1]IOB0:OUTPUT_ENABLE[0]IOB0:SUSPEND[2]IOB0:NSLEW[3]IOB0:PSLEW[2]
5 -IOB1:NSLEW[3]~IOB1:I_DELAY[0]~IOB2:IFF_DELAY[0]~IOB2:IFF_DELAY[1]IOB1:NSLEW[0]~IOB2:DELAY_COMMON~IOB1:DELAY_COMMON-~IOB1:IFF_DELAY[0]-~IOB1:IFF_DELAY[1]IOB0:PULL[2]-~IOB0:I_DELAY[2]~IOB0:IFF_DELAY[1]~IOB0:IFF_DELAY[0]-~IOB0:DELAY_COMMON
IOBS.S3A.T2 bittile 1
RowColumn
0123456789101112131415161718
0 -IOB4:NSLEW[3]--IOB4:PULL[0]IOB4:OUTPUT_DIFF[3]IOB4:NDRIVE[0]-~IOB3:NDRIVE[1]IOB3:PULL[2]IOB4:PSLEW[3]--IOB4:SUSPEND[1]~IOB3:I_DELAY[0]~IOB3:I_DELAY[1]--IOB2:VREF
1 -IOB4:NSLEW[2]-IOB4:NDRIVE[2]IOB4:PDRIVE[0]--IOB3:PULL[1]~IOB3:PDRIVE[1]IOB3:IBUF_MODE[2]IOB4:PCI_INPUT--IOB4:PULL[2]IOB3:NSLEW[0]IOB3:NSLEW[3]IOB3:PCI_INPUT-IOB2:IBUF_MODE[0]
2 -IOB4:NSLEW[1]IOB4:OUTPUT_ENABLE[1]~IOB4:NDRIVE[1]~IOB4:PDRIVE[1]--IOB3:PULL[0]IOB3:PDRIVE[0]IOB3:NDRIVE[0]IOB4:PSLEW[1]IOB3:SUSPEND[3]~IOB4:I_DELAY[0]IOB4:SUSPEND[0]IOB3:OUTPUT_ENABLE[1]IOB3:NSLEW[2]IOB3:PSLEW[1]-IOB2:IBUF_MODE[1]
3 -IOB4:NSLEW[0]IOB4:DELAY_VARIABLEIOB4:PDRIVE[2]IOB4:PULL[1]IOB4:OUTPUT_DIFF[0]IOB4:PCI_CLAMPIOB4:OUTPUT_DIFF_GROUP[1]IOB3:PDRIVE[2]IOB3:PCI_CLAMPIOB4:PSLEW[0]IOB3:NDRIVE[2]~IOB4:I_DELAY[1]IOB3:SUSPEND[1]IOB3:NSLEW[1]IOB3:PSLEW[0]IOB3:PSLEW[3]-IOB2:IBUF_MODE[2]
4 -IOB4:SUSPEND[2]IOB4:SUSPEND[3]-IOB4:OUTPUT_DIFF[1]IOB4:OUTPUT_DIFF_GROUP[0]-IOB4:OUTPUT_DIFF[2]IOB3:SUSPEND[0]IOB3:IBUF_MODE[0]IOB4:PSLEW[2]IOB3:IBUF_MODE[1]IOB3:OUTPUT_ENABLE[0]IOB4:IBUF_MODE[0]IOB3:SUSPEND[2]IOB3:DELAY_VARIABLEIOB3:PSLEW[2]IOB2:PCI_INPUTIOB2:PULL[2]
5 -IOB4:OUTPUT_ENABLE[0]---IOB4:IBUF_MODE[1]-~IOB4:DELAY_COMMONIOB4:IBUF_MODE[2]~IOB4:IFF_DELAY[0]-~IOB4:IFF_DELAY[1]~IOB4:I_DELAY[2]-~IOB3:I_DELAY[2]-~IOB3:IFF_DELAY[1]~IOB3:IFF_DELAY[0]~IOB3:DELAY_COMMON
IOB0:NSLEW[0, 17, 4][0, 17, 2][0, 16, 2][0, 16, 3]
IOB0:PSLEW[0, 18, 1][0, 18, 4][0, 18, 2][0, 17, 1]
IOB1:NSLEW[0, 1, 5][0, 2, 0][0, 2, 2][0, 5, 5]
IOB1:OUTPUT_DIFF[0, 8, 2][0, 11, 4][0, 7, 3][0, 8, 1]
IOB1:PSLEW[0, 1, 4][0, 1, 0][0, 1, 2][0, 1, 1]
IOB3:NSLEW[1, 15, 1][1, 15, 2][1, 14, 3][1, 14, 1]
IOB3:PSLEW[1, 16, 3][1, 16, 4][1, 16, 2][1, 15, 3]
IOB4:NSLEW[1, 1, 0][1, 1, 1][1, 1, 2][1, 1, 3]
IOB4:OUTPUT_DIFF[1, 5, 0][1, 7, 4][1, 4, 4][1, 5, 3]
IOB4:PSLEW[1, 10, 0][1, 10, 4][1, 10, 2][1, 10, 3]
Non-inverted[3][2][1][0]
IOB0:DELAY_VARIABLE[0, 15, 3]
IOB0:PCI_CLAMP[0, 12, 3]
IOB0:PCI_INPUT[0, 18, 3]
IOB0:VREF[0, 15, 0]
IOB1:DELAY_VARIABLE[0, 2, 3]
IOB1:PCI_CLAMP[0, 6, 0]
IOB1:PCI_INPUT[0, 1, 3]
IOB1:VREF[0, 3, 2]
IOB2:DELAY_VARIABLE[0, 4, 0]
IOB2:PCI_INPUT[1, 17, 4]
IOB2:VREF[1, 18, 0]
IOB3:DELAY_VARIABLE[1, 15, 4]
IOB3:PCI_CLAMP[1, 9, 3]
IOB3:PCI_INPUT[1, 16, 1]
IOB4:DELAY_VARIABLE[1, 2, 3]
IOB4:PCI_CLAMP[1, 6, 3]
IOB4:PCI_INPUT[1, 10, 1]
Non-inverted[0]
IOB0:OUTPUT_ENABLE[0, 16, 1][0, 15, 4]
IOB1:OUTPUT_DIFF_GROUP[0, 11, 2][0, 8, 4]
IOB1:OUTPUT_ENABLE[0, 3, 1][0, 2, 4]
IOB3:OUTPUT_ENABLE[1, 14, 2][1, 12, 4]
IOB4:OUTPUT_DIFF_GROUP[1, 7, 3][1, 5, 4]
IOB4:OUTPUT_ENABLE[1, 2, 2][1, 1, 5]
Non-inverted[1][0]
IOB0:I_DELAY[0, 14, 5][0, 14, 4][0, 15, 1]
IOB1:I_DELAY[0, 8, 0][0, 5, 0][0, 2, 5]
IOB2:I_DELAY[0, 2, 1][0, 6, 1][0, 3, 0]
IOB3:I_DELAY[1, 14, 5][1, 15, 0][1, 14, 0]
IOB4:I_DELAY[1, 12, 5][1, 12, 3][1, 12, 2]
Inverted~[2]~[1]~[0]
IOB0:IFF_DELAY[0, 15, 5][0, 16, 5]
IOB1:IFF_DELAY[0, 11, 5][0, 9, 5]
IOB2:IFF_DELAY[0, 4, 5][0, 3, 5]
IOB3:IFF_DELAY[1, 16, 5][1, 17, 5]
IOB4:IFF_DELAY[1, 11, 5][1, 9, 5]
Inverted~[1]~[0]
IOB0:IBUF_MODE[0, 12, 1][0, 14, 3][0, 14, 1]
IOB1:IBUF_MODE[0, 5, 4][0, 4, 3][0, 4, 1]
IOB3:IBUF_MODE[1, 9, 1][1, 11, 4][1, 9, 4]
IOB4:IBUF_MODE[1, 8, 5][1, 5, 5][1, 13, 4]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
DIFF110
CMOS_VCCAUX111
IOB0:SUSPEND[0, 14, 0][0, 16, 4][0, 14, 2][0, 12, 4]
IOB1:SUSPEND[0, 4, 4][0, 3, 3][0, 4, 2][0, 5, 2]
IOB3:SUSPEND[1, 11, 2][1, 14, 4][1, 13, 3][1, 8, 4]
IOB4:SUSPEND[1, 2, 4][1, 1, 4][1, 13, 0][1, 13, 2]
3STATE0000
DRIVE_LAST_VALUE0001
3STATE_PULLUP0010
3STATE_PULLDOWN0100
3STATE_KEEPER1000
IOB0:NDRIVE[0, 13, 3][0, 13, 4][0, 12, 2]
IOB0:PDRIVE[0, 11, 3][0, 13, 1][0, 13, 2]
IOB1:NDRIVE[0, 6, 4][0, 7, 4][0, 5, 3]
IOB1:PDRIVE[0, 7, 2][0, 6, 2][0, 6, 3]
IOB3:NDRIVE[1, 11, 3][1, 8, 0][1, 9, 2]
IOB3:PDRIVE[1, 8, 3][1, 8, 1][1, 8, 2]
IOB4:NDRIVE[1, 3, 1][1, 3, 2][1, 6, 0]
IOB4:PDRIVE[1, 3, 3][1, 4, 2][1, 4, 1]
Mixed inversion[2]~[1][0]
IOB0:DELAY_COMMON[0, 18, 5]
IOB1:DELAY_COMMON[0, 7, 5]
IOB2:DELAY_COMMON[0, 6, 5]
IOB3:DELAY_COMMON[1, 18, 5]
IOB4:DELAY_COMMON[1, 7, 5]
Inverted~[0]
IOB0:PULL[0, 12, 5][0, 11, 1][0, 9, 3]
IOB1:PULL[0, 5, 1][0, 7, 0][0, 8, 3]
IOB2:PULL[1, 18, 4][0, 10, 2][0, 10, 1]
IOB3:PULL[1, 9, 0][1, 7, 1][1, 7, 2]
IOB4:PULL[1, 13, 1][1, 4, 3][1, 4, 0]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[1, 18, 3][1, 18, 2][1, 18, 1]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
CMOS_VCCAUX111

IOBS.S3A.R4

IOBS.S3A.R4 bittile 0
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 IOB7:PSLEW[3]-
7 IOB7:PSLEW[0]-
8 IOB7:PCI_INPUT-
9 IOB7:PSLEW[2]-
10 IOB7:NSLEW[3]-
11 IOB7:PSLEW[1]IOB7:NSLEW[2]
12 IOB7:NSLEW[1]-
13 IOB7:NSLEW[0]-
14 IOB7:SUSPEND[2]-
15 IOB7:OUTPUT_ENABLE[0]-
16 IOB7:PULL[2]-
17 -IOB7:OUTPUT_ENABLE[1]
18 IOB7:SUSPEND[3]-
19 --
20 IOB7:SUSPEND[1]-
21 IOB7:IBUF_MODE[1]-
22 IOB7:IBUF_MODE[0]-
23 IOB7:NDRIVE[0]-
24 IOB7:SUSPEND[0]IOB7:PCI_CLAMP
25 IOB7:IBUF_MODE[2]-
26 ~IOB7:NDRIVE[1]-
27 IOB7:PDRIVE[0]-
28 ~IOB7:PDRIVE[1]-
29 IOB7:NDRIVE[2]-
30 IOB7:PDRIVE[2]-
31 --
32 --
33 --
34 --
35 --
36 --
37 --
38 --
39 --
40 IOB6:PDRIVE[2]-
41 --
42 ~IOB6:PDRIVE[1]-
43 IOB6:PDRIVE[0]IOB6:NDRIVE[2]
44 ~IOB6:NDRIVE[1]-
45 IOB6:IBUF_MODE[2]-
46 IOB6:PULL[2]-
47 IOB6:NDRIVE[0]-
48 IOB6:PCI_CLAMP-
49 IOB6:IBUF_MODE[1]IOB6:IBUF_MODE[0]
50 IOB6:SUSPEND[1]-
51 IOB6:VREF-
52 IOB6:SUSPEND[3]-
53 --
54 IOB6:SUSPEND[0]-
55 IOB6:OUTPUT_ENABLE[0]-
56 IOB6:OUTPUT_ENABLE[1]IOB6:SUSPEND[2]
57 IOB6:NSLEW[0]-
58 IOB7:PULL[1]-
59 --
60 IOB6:NSLEW[2]-
61 IOB6:NSLEW[3]-
62 IOB7:PULL[0]-
63 IOB6:PULL[1]-
IOBS.S3A.R4 bittile 1
RowColumn
01
0 IOB6:PULL[0]-
1 --
2 IOB6:PSLEW[0]-
3 IOB6:PSLEW[1]-
4 IOB6:PCI_INPUT-
5 IOB6:PSLEW[3]IOB6:PSLEW[2]
6 --
7 --
8 IOB6:NSLEW[1]-
9 --
10 IOB5:PSLEW[3]-
11 IOB5:PCI_INPUTIOB5:PSLEW[2]
12 IOB5:PSLEW[1]-
13 IOB5:PSLEW[0]-
14 --
15 ~IOB5:NDRIVE[1]-
16 --
17 IOB5:NSLEW[3]-
18 IOB5:NSLEW[2]-
19 IOB5:NSLEW[1]-
20 IOB5:SUSPEND[0]-
21 IOB5:NSLEW[0]-
22 IOB5:SUSPEND[2]-
23 IOB5:OUTPUT_ENABLE[0]-
24 IOB5:OUTPUT_ENABLE[1]IOB5:SUSPEND[3]
25 --
26 --
27 --
28 IOB5:SUSPEND[1]-
29 IOB5:IBUF_MODE[0]-
30 IOB5:IBUF_MODE[1]-
31 IOB5:NDRIVE[0]-
32 IOB5:PULL[2]-
33 IOB5:PCI_CLAMP-
34 IOB5:IBUF_MODE[2]-
35 IOB5:NDRIVE[2]-
36 ~IOB5:PDRIVE[1]-
37 IOB5:PDRIVE[2]IOB5:PDRIVE[0]
38 --
39 --
40 --
41 --
42 --
43 -IOB5:PULL[1]
44 --
45 --
46 --
47 --
48 --
49 IOB4:NDRIVE[2]IOB4:PDRIVE[2]
50 ~IOB4:PDRIVE[1]-
51 IOB4:PDRIVE[0]-
52 ~IOB4:NDRIVE[1]-
53 IOB4:NDRIVE[0]-
54 IOB4:PCI_CLAMP-
55 IOB4:PULL[2]-
56 IOB4:IBUF_MODE[1]IOB4:IBUF_MODE[2]
57 IOB4:IBUF_MODE[0]-
58 IOB4:SUSPEND[1]-
59 --
60 --
61 IOB4:SUSPEND[3]-
62 IOB5:PULL[0]-
63 IOB4:OUTPUT_ENABLE[0]-
IOBS.S3A.R4 bittile 2
RowColumn
01
0 IOB4:OUTPUT_ENABLE[1]-
1 IOB4:SUSPEND[2]-
2 IOB4:NSLEW[0]-
3 IOB4:NSLEW[1]-
4 --
5 IOB4:NSLEW[3]IOB4:NSLEW[2]
6 --
7 IOB4:PULL[1]-
8 IOB4:PULL[0]-
9 IOB4:PSLEW[1]-
10 IOB4:PSLEW[0]-
11 IOB4:PCI_INPUTIOB4:SUSPEND[0]
12 IOB4:PSLEW[2]-
13 IOB4:PSLEW[3]-
14 --
15 --
16 --
17 IOB3:PSLEW[3]IOB3:SUSPEND[0]
18 IOB3:PSLEW[2]-
19 IOB3:PCI_INPUT-
20 IOB3:PSLEW[1]-
21 IOB3:PSLEW[0]-
22 IOB3:PULL[0]-
23 IOB3:PULL[1]-
24 --
25 IOB3:NSLEW[3]-
26 IOB3:NSLEW[2]-
27 --
28 IOB3:NSLEW[1]-
29 IOB3:NSLEW[0]-
30 IOB3:SUSPEND[2]-
31 IOB3:OUTPUT_ENABLE[0]-
32 --
33 IOB3:OUTPUT_ENABLE[1]-
34 IOB3:NDRIVE[0]-
35 IOB3:VREF-
36 --
37 IOB3:SUSPEND[3]IOB3:SUSPEND[1]
38 IOB3:IBUF_MODE[0]-
39 IOB3:IBUF_MODE[1]-
40 IOB3:PULL[2]-
41 IOB3:PCI_CLAMP-
42 IOB3:IBUF_MODE[2]-
43 IOB3:PDRIVE[0]~IOB3:NDRIVE[1]
44 ~IOB3:PDRIVE[1]-
45 IOB3:NDRIVE[2]-
46 IOB3:PDRIVE[2]-
47 --
48 --
49 --
50 --
51 ~IOB2:PDRIVE[1]-
52 IOB2:PULL[0]-
53 --
54 --
55 --
56 -IOB2:PDRIVE[2]
57 IOB2:IBUF_MODE[2]-
58 IOB2:NDRIVE[2]-
59 IOB2:PDRIVE[0]-
60 ~IOB2:NDRIVE[1]-
61 IOB2:NDRIVE[0]-
62 IOB2:PCI_CLAMP-
63 IOB2:PULL[2]-
IOBS.S3A.R4 bittile 3
RowColumn
01
0 IOB2:IBUF_MODE[1]-
1 IOB2:IBUF_MODE[0]-
2 IOB2:SUSPEND[3]-
3 IOB2:SUSPEND[1]-
4 IOB2:VREF-
5 --
6 --
7 IOB2:OUTPUT_ENABLE[0]-
8 IOB2:OUTPUT_ENABLE[1]-
9 IOB2:SUSPEND[2]-
10 IOB2:NSLEW[0]-
11 -IOB2:NSLEW[1]
12 IOB2:NSLEW[2]-
13 IOB2:NSLEW[3]-
14 --
15 IOB2:PULL[1]-
16 --
17 IOB2:PSLEW[0]IOB2:SUSPEND[0]
18 IOB2:PSLEW[1]-
19 IOB2:PCI_INPUT-
20 IOB2:PSLEW[2]-
21 IOB2:PSLEW[3]-
22 --
23 --
24 --
25 IOB1:PULL[0]-
26 --
27 IOB1:PULL[1]-
28 --
29 --
30 --
31 IOB1:PULL[2]-
32 IOB1:IBUF_MODE[0]-
33 IOB1:IBUF_MODE[1]-
34 IOB1:VREF-
35 --
36 IOB1:IBUF_MODE[2]-
37 --
38 IOB1:PCI_INPUT-
39 --
40 --
41 --
42 --
43 --
44 --
45 --
46 IOB0:PCI_INPUT-
47 --
48 --
49 IOB0:VREF-
50 IOB0:IBUF_MODE[2]-
51 IOB0:IBUF_MODE[1]-
52 IOB0:IBUF_MODE[0]IOB0:PULL[2]
53 --
54 --
55 IOB0:PULL[1]-
56 IOB0:PULL[0]-
IOB2:NSLEW[3, 0, 13][3, 0, 12][3, 1, 11][3, 0, 10]
IOB2:PSLEW[3, 0, 21][3, 0, 20][3, 0, 18][3, 0, 17]
IOB3:NSLEW[2, 0, 25][2, 0, 26][2, 0, 28][2, 0, 29]
IOB3:PSLEW[2, 0, 17][2, 0, 18][2, 0, 20][2, 0, 21]
IOB4:NSLEW[2, 0, 5][2, 1, 5][2, 0, 3][2, 0, 2]
IOB4:PSLEW[2, 0, 13][2, 0, 12][2, 0, 9][2, 0, 10]
IOB5:NSLEW[1, 0, 17][1, 0, 18][1, 0, 19][1, 0, 21]
IOB5:PSLEW[1, 0, 10][1, 1, 11][1, 0, 12][1, 0, 13]
IOB6:NSLEW[0, 0, 61][0, 0, 60][1, 0, 8][0, 0, 57]
IOB6:PSLEW[1, 0, 5][1, 1, 5][1, 0, 3][1, 0, 2]
IOB7:NSLEW[0, 0, 10][0, 1, 11][0, 0, 12][0, 0, 13]
IOB7:PSLEW[0, 0, 6][0, 0, 9][0, 0, 11][0, 0, 7]
Non-inverted[3][2][1][0]
IOB0:PCI_INPUT[3, 0, 46]
IOB0:VREF[3, 0, 49]
IOB1:PCI_INPUT[3, 0, 38]
IOB1:VREF[3, 0, 34]
IOB2:PCI_CLAMP[2, 0, 62]
IOB2:PCI_INPUT[3, 0, 19]
IOB2:VREF[3, 0, 4]
IOB3:PCI_CLAMP[2, 0, 41]
IOB3:PCI_INPUT[2, 0, 19]
IOB3:VREF[2, 0, 35]
IOB4:PCI_CLAMP[1, 0, 54]
IOB4:PCI_INPUT[2, 0, 11]
IOB5:PCI_CLAMP[1, 0, 33]
IOB5:PCI_INPUT[1, 0, 11]
IOB6:PCI_CLAMP[0, 0, 48]
IOB6:PCI_INPUT[1, 0, 4]
IOB6:VREF[0, 0, 51]
IOB7:PCI_CLAMP[0, 1, 24]
IOB7:PCI_INPUT[0, 0, 8]
Non-inverted[0]
IOB2:OUTPUT_ENABLE[3, 0, 8][3, 0, 7]
IOB3:OUTPUT_ENABLE[2, 0, 33][2, 0, 31]
IOB4:OUTPUT_ENABLE[2, 0, 0][1, 0, 63]
IOB5:OUTPUT_ENABLE[1, 0, 24][1, 0, 23]
IOB6:OUTPUT_ENABLE[0, 0, 56][0, 0, 55]
IOB7:OUTPUT_ENABLE[0, 1, 17][0, 0, 15]
Non-inverted[1][0]
IOB0:IBUF_MODE[3, 0, 50][3, 0, 51][3, 0, 52]
IOB1:IBUF_MODE[3, 0, 36][3, 0, 33][3, 0, 32]
IOB2:IBUF_MODE[2, 0, 57][3, 0, 0][3, 0, 1]
IOB3:IBUF_MODE[2, 0, 42][2, 0, 39][2, 0, 38]
IOB4:IBUF_MODE[1, 1, 56][1, 0, 56][1, 0, 57]
IOB5:IBUF_MODE[1, 0, 34][1, 0, 30][1, 0, 29]
IOB6:IBUF_MODE[0, 0, 45][0, 0, 49][0, 1, 49]
IOB7:IBUF_MODE[0, 0, 25][0, 0, 21][0, 0, 22]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
DIFF110
CMOS_VCCAUX111
IOB2:NDRIVE[2, 0, 58][2, 0, 60][2, 0, 61]
IOB2:PDRIVE[2, 1, 56][2, 0, 51][2, 0, 59]
IOB3:NDRIVE[2, 0, 45][2, 1, 43][2, 0, 34]
IOB3:PDRIVE[2, 0, 46][2, 0, 44][2, 0, 43]
IOB4:NDRIVE[1, 0, 49][1, 0, 52][1, 0, 53]
IOB4:PDRIVE[1, 1, 49][1, 0, 50][1, 0, 51]
IOB5:NDRIVE[1, 0, 35][1, 0, 15][1, 0, 31]
IOB5:PDRIVE[1, 0, 37][1, 0, 36][1, 1, 37]
IOB6:NDRIVE[0, 1, 43][0, 0, 44][0, 0, 47]
IOB6:PDRIVE[0, 0, 40][0, 0, 42][0, 0, 43]
IOB7:NDRIVE[0, 0, 29][0, 0, 26][0, 0, 23]
IOB7:PDRIVE[0, 0, 30][0, 0, 28][0, 0, 27]
Mixed inversion[2]~[1][0]
IOB2:SUSPEND[3, 0, 2][3, 0, 9][3, 0, 3][3, 1, 17]
IOB3:SUSPEND[2, 0, 37][2, 0, 30][2, 1, 37][2, 1, 17]
IOB4:SUSPEND[1, 0, 61][2, 0, 1][1, 0, 58][2, 1, 11]
IOB5:SUSPEND[1, 1, 24][1, 0, 22][1, 0, 28][1, 0, 20]
IOB6:SUSPEND[0, 0, 52][0, 1, 56][0, 0, 50][0, 0, 54]
IOB7:SUSPEND[0, 0, 18][0, 0, 14][0, 0, 20][0, 0, 24]
3STATE0000
DRIVE_LAST_VALUE0001
3STATE_PULLUP0010
3STATE_PULLDOWN0100
3STATE_KEEPER1000
IOB0:PULL[3, 1, 52][3, 0, 55][3, 0, 56]
IOB1:PULL[3, 0, 31][3, 0, 27][3, 0, 25]
IOB2:PULL[2, 0, 63][3, 0, 15][2, 0, 52]
IOB3:PULL[2, 0, 40][2, 0, 23][2, 0, 22]
IOB4:PULL[1, 0, 55][2, 0, 7][2, 0, 8]
IOB5:PULL[1, 0, 32][1, 1, 43][1, 0, 62]
IOB6:PULL[0, 0, 46][0, 0, 63][1, 0, 0]
IOB7:PULL[0, 0, 16][0, 0, 58][0, 0, 62]
PULLDOWN000
NONE001
PULLUP011
KEEPER101

IOBS.S3A.B2

IOBS.S3A.B2 bittile 0
RowColumn
0123456789101112131415161718
0 -IOB3:PCI_INPUT~IOB2:DELAY_COMMON~IOB2:IFF_DELAY[1]~IOB2:IFF_DELAY[0]-IOB3:IBUF_MODE[2]-~IOB3:IFF_DELAY[1]~IOB3:IFF_DELAY[0]-~IOB3:DELAY_COMMONIOB4:PULL[2]IOB4:NDRIVE[2]IOB4:SUSPEND[1]~IOB4:IFF_DELAY[0]~IOB4:DELAY_COMMON~IOB4:IFF_DELAY[1]IOB2:VREF
1 -IOB3:PSLEW[2]~IOB2:I_DELAY[0]-IOB3:OUTPUT_ENABLE[0]-IOB3:NDRIVE[2]~IOB3:PDRIVE[1]-~IOB3:I_DELAY[0]--IOB4:SUSPEND[0]IOB4:PDRIVE[0]IOB4:SUSPEND[3]IOB4:OUTPUT_ENABLE[0]-~IOB4:I_DELAY[0]IOB2:IBUF_MODE[2]
2 -IOB3:PSLEW[3]~IOB2:I_DELAY[1]IOB2:DELAY_VARIABLEIOB3:OUTPUT_ENABLE[1]IOB3:SUSPEND[1]~IOB3:NDRIVE[1]IOB3:PDRIVE[0]IOB3:DELAY_VARIABLE~IOB3:I_DELAY[1]~IOB4:PDRIVE[1]IOB4:OUTPUT_DIFF[0]IOB4:NDRIVE[0]~IOB4:NDRIVE[1]IOB4:IBUF_MODE[1]IOB4:NSLEW[0]IOB4:DELAY_VARIABLE~IOB4:I_DELAY[1]IOB2:IBUF_MODE[1]
3 -IOB2:PCI_INPUTIOB3:PSLEW[0]IOB3:NSLEW[2]IOB3:SUSPEND[2]IOB3:IBUF_MODE[0]IOB3:NDRIVE[0]IOB3:PULL[1]IOB4:OUTPUT_DIFF_GROUP[0]--IOB4:PULL[0]IOB4:OUTPUT_DIFF_GROUP[1]IOB4:PSLEW[1]IOB4:IBUF_MODE[0]IOB4:NSLEW[1]IOB4:NSLEW[2]IOB4:PCI_INPUTIOB2:IBUF_MODE[0]
4 --IOB3:PSLEW[1]IOB3:NSLEW[3]IOB3:NSLEW[0]IOB3:IBUF_MODE[1]IOB3:PCI_CLAMPIOB3:PDRIVE[2]IOB4:OUTPUT_DIFF[1]IOB3:PULL[0]IOB4:PDRIVE[2]IOB4:OUTPUT_DIFF[2]IOB4:PULL[1]IOB4:PSLEW[2]-IOB4:SUSPEND[2]IOB4:NSLEW[3]IOB4:PSLEW[0]IOB2:PULL[2]
5 --~IOB2:I_DELAY[2]-IOB3:NSLEW[1]IOB3:SUSPEND[3]IOB3:SUSPEND[0]IOB3:PULL[2]-~IOB3:I_DELAY[2]-IOB4:OUTPUT_DIFF[3]IOB4:PCI_CLAMPIOB4:IBUF_MODE[2]-IOB4:OUTPUT_ENABLE[1]IOB4:PSLEW[3]~IOB4:I_DELAY[2]-
IOBS.S3A.B2 bittile 1
RowColumn
0123456789101112131415161718
0 -IOB0:OUTPUT_ENABLE[0]---IOB0:NDRIVE[2]IOB0:PULL[1]-~IOB0:IFF_DELAY[1]~IOB0:IFF_DELAY[0]IOB1:SUSPEND[0]~IOB0:DELAY_COMMONIOB1:OUTPUT_ENABLE[0]-IOB1:NSLEW[2]~IOB1:IFF_DELAY[0]~IOB1:DELAY_COMMON~IOB1:IFF_DELAY[1]IOB0:PSLEW[2]
1 -IOB0:OUTPUT_ENABLE[1]--IOB0:PCI_CLAMP~IOB0:NDRIVE[1]---~IOB0:I_DELAY[0]IOB1:NDRIVE[0]IOB1:PCI_CLAMPIOB1:OUTPUT_ENABLE[1]-IOB1:NSLEW[3]IOB1:PSLEW[3]IOB2:PULL[1]~IOB1:I_DELAY[0]IOB0:PCI_INPUT
2 -IOB0:SUSPEND[2]--IOB0:SUSPEND[0]IOB0:IBUF_MODE[2]IOB0:PDRIVE[2]-IOB0:DELAY_VARIABLE~IOB0:I_DELAY[1]IOB1:PULL[2]~IOB1:PDRIVE[1]IOB1:SUSPEND[2]IOB1:SUSPEND[1]-IOB1:PSLEW[2]IOB1:DELAY_VARIABLE~IOB1:I_DELAY[1]IOB0:PSLEW[1]
3 -IOB0:NSLEW[2]-IOB0:SUSPEND[1]IOB1:OUTPUT_DIFF[1]~IOB0:PDRIVE[1]IOB0:PULL[2]IOB1:OUTPUT_DIFF[0]IOB1:PULL[0]IOB1:PULL[1]IOB1:IBUF_MODE[2]IOB1:PDRIVE[0]IOB1:NSLEW[0]IOB1:SUSPEND[3]-IOB1:PSLEW[0]IOB1:PCI_INPUT-IOB0:NSLEW[3]
4 -IOB0:NSLEW[1]-IOB0:SUSPEND[3]IOB1:OUTPUT_DIFF_GROUP[0]IOB0:PDRIVE[0]IOB0:IBUF_MODE[0]IOB1:OUTPUT_DIFF[3]IOB1:OUTPUT_DIFF_GROUP[1]IOB1:OUTPUT_DIFF[2]~IOB1:NDRIVE[1]IOB1:PDRIVE[2]IOB1:NSLEW[1]IOB1:IBUF_MODE[0]-IOB1:PSLEW[1]--IOB0:PSLEW[0]
5 -IOB0:NSLEW[0]--IOB0:PULL[0]IOB0:NDRIVE[0]IOB0:IBUF_MODE[1]--~IOB0:I_DELAY[2]IOB1:NDRIVE[2]--IOB1:IBUF_MODE[1]--IOB2:PULL[0]~IOB1:I_DELAY[2]IOB0:PSLEW[3]
IOB0:DELAY_VARIABLE[1, 8, 2]
IOB0:PCI_CLAMP[1, 4, 1]
IOB0:PCI_INPUT[1, 18, 1]
IOB1:DELAY_VARIABLE[1, 16, 2]
IOB1:PCI_CLAMP[1, 11, 1]
IOB1:PCI_INPUT[1, 16, 3]
IOB2:DELAY_VARIABLE[0, 3, 2]
IOB2:PCI_INPUT[0, 1, 3]
IOB2:VREF[0, 18, 0]
IOB3:DELAY_VARIABLE[0, 8, 2]
IOB3:PCI_CLAMP[0, 6, 4]
IOB3:PCI_INPUT[0, 1, 0]
IOB4:DELAY_VARIABLE[0, 16, 2]
IOB4:PCI_CLAMP[0, 12, 5]
IOB4:PCI_INPUT[0, 17, 3]
Non-inverted[0]
IOB0:DELAY_COMMON[1, 11, 0]
IOB1:DELAY_COMMON[1, 16, 0]
IOB2:DELAY_COMMON[0, 2, 0]
IOB3:DELAY_COMMON[0, 11, 0]
IOB4:DELAY_COMMON[0, 16, 0]
Inverted~[0]
IOB0:I_DELAY[1, 9, 5][1, 9, 2][1, 9, 1]
IOB1:I_DELAY[1, 17, 5][1, 17, 2][1, 17, 1]
IOB2:I_DELAY[0, 2, 5][0, 2, 2][0, 2, 1]
IOB3:I_DELAY[0, 9, 5][0, 9, 2][0, 9, 1]
IOB4:I_DELAY[0, 17, 5][0, 17, 2][0, 17, 1]
Inverted~[2]~[1]~[0]
IOB0:NSLEW[1, 18, 3][1, 1, 3][1, 1, 4][1, 1, 5]
IOB0:PSLEW[1, 18, 5][1, 18, 0][1, 18, 2][1, 18, 4]
IOB1:NSLEW[1, 14, 1][1, 14, 0][1, 12, 4][1, 12, 3]
IOB1:OUTPUT_DIFF[1, 7, 4][1, 9, 4][1, 4, 3][1, 7, 3]
IOB1:PSLEW[1, 15, 1][1, 15, 2][1, 15, 4][1, 15, 3]
IOB3:NSLEW[0, 3, 4][0, 3, 3][0, 4, 5][0, 4, 4]
IOB3:PSLEW[0, 1, 2][0, 1, 1][0, 2, 4][0, 2, 3]
IOB4:NSLEW[0, 16, 4][0, 16, 3][0, 15, 3][0, 15, 2]
IOB4:OUTPUT_DIFF[0, 11, 5][0, 11, 4][0, 8, 4][0, 11, 2]
IOB4:PSLEW[0, 16, 5][0, 13, 4][0, 13, 3][0, 17, 4]
Non-inverted[3][2][1][0]
IOB0:IFF_DELAY[1, 8, 0][1, 9, 0]
IOB1:IFF_DELAY[1, 17, 0][1, 15, 0]
IOB2:IFF_DELAY[0, 3, 0][0, 4, 0]
IOB3:IFF_DELAY[0, 8, 0][0, 9, 0]
IOB4:IFF_DELAY[0, 17, 0][0, 15, 0]
Inverted~[1]~[0]
IOB0:OUTPUT_ENABLE[1, 1, 1][1, 1, 0]
IOB1:OUTPUT_DIFF_GROUP[1, 8, 4][1, 4, 4]
IOB1:OUTPUT_ENABLE[1, 12, 1][1, 12, 0]
IOB3:OUTPUT_ENABLE[0, 4, 2][0, 4, 1]
IOB4:OUTPUT_DIFF_GROUP[0, 12, 3][0, 8, 3]
IOB4:OUTPUT_ENABLE[0, 15, 5][0, 15, 1]
Non-inverted[1][0]
IOB0:IBUF_MODE[1, 5, 2][1, 6, 5][1, 6, 4]
IOB1:IBUF_MODE[1, 10, 3][1, 13, 5][1, 13, 4]
IOB3:IBUF_MODE[0, 6, 0][0, 5, 4][0, 5, 3]
IOB4:IBUF_MODE[0, 13, 5][0, 14, 2][0, 14, 3]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
DIFF110
CMOS_VCCAUX111
IOB0:NDRIVE[1, 5, 0][1, 5, 1][1, 5, 5]
IOB0:PDRIVE[1, 6, 2][1, 5, 3][1, 5, 4]
IOB1:NDRIVE[1, 10, 5][1, 10, 4][1, 10, 1]
IOB1:PDRIVE[1, 11, 4][1, 11, 2][1, 11, 3]
IOB3:NDRIVE[0, 6, 1][0, 6, 2][0, 6, 3]
IOB3:PDRIVE[0, 7, 4][0, 7, 1][0, 7, 2]
IOB4:NDRIVE[0, 13, 0][0, 13, 2][0, 12, 2]
IOB4:PDRIVE[0, 10, 4][0, 10, 2][0, 13, 1]
Mixed inversion[2]~[1][0]
IOB0:SUSPEND[1, 3, 4][1, 1, 2][1, 3, 3][1, 4, 2]
IOB1:SUSPEND[1, 13, 3][1, 12, 2][1, 13, 2][1, 10, 0]
IOB3:SUSPEND[0, 5, 5][0, 4, 3][0, 5, 2][0, 6, 5]
IOB4:SUSPEND[0, 14, 1][0, 15, 4][0, 14, 0][0, 12, 1]
3STATE0000
DRIVE_LAST_VALUE0001
3STATE_PULLUP0010
3STATE_PULLDOWN0100
3STATE_KEEPER1000
IOB0:PULL[1, 6, 3][1, 6, 0][1, 4, 5]
IOB1:PULL[1, 10, 2][1, 9, 3][1, 8, 3]
IOB2:PULL[0, 18, 4][1, 16, 1][1, 16, 5]
IOB3:PULL[0, 7, 5][0, 7, 3][0, 9, 4]
IOB4:PULL[0, 12, 0][0, 12, 4][0, 11, 3]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB2:IBUF_MODE[0, 18, 1][0, 18, 2][0, 18, 3]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
CMOS_VCCAUX111

IOBS.S3A.L4

IOBS.S3A.L4 bittile 0
RowColumn
01
0 --
1 --
2 --
3 --
4 --
5 --
6 --
7 IOB0:PULL[0]-
8 IOB0:PULL[1]-
9 --
10 --
11 IOB0:IBUF_MODE[0]IOB0:PULL[2]
12 IOB0:IBUF_MODE[1]-
13 IOB0:IBUF_MODE[2]-
14 IOB0:VREF-
15 --
16 --
17 IOB0:PCI_INPUT-
18 --
19 --
20 --
21 --
22 --
23 --
24 --
25 IOB1:PCI_INPUT-
26 --
27 IOB1:IBUF_MODE[2]-
28 --
29 --
30 IOB1:IBUF_MODE[1]-
31 IOB1:IBUF_MODE[0]-
32 IOB1:PULL[2]-
33 --
34 --
35 --
36 IOB1:PULL[1]-
37 --
38 IOB1:PULL[0]-
39 --
40 --
41 --
42 IOB2:PSLEW[3]-
43 IOB2:PSLEW[2]-
44 IOB2:PCI_INPUT-
45 IOB2:PSLEW[1]-
46 IOB2:PSLEW[0]IOB2:SUSPEND[0]
47 --
48 IOB2:PULL[1]-
49 --
50 IOB2:NSLEW[3]-
51 IOB2:NSLEW[2]-
52 -IOB2:NSLEW[1]
53 IOB2:NSLEW[0]-
54 IOB2:SUSPEND[2]-
55 IOB2:OUTPUT_ENABLE[0]-
56 IOB2:OUTPUT_ENABLE[1]-
57 --
58 --
59 --
60 IOB2:SUSPEND[1]-
61 IOB2:SUSPEND[3]-
62 IOB2:IBUF_MODE[0]-
63 IOB2:IBUF_MODE[1]-
IOBS.S3A.L4 bittile 1
RowColumn
01
0 IOB2:PULL[2]-
1 IOB2:PCI_CLAMP-
2 IOB2:NDRIVE[0]-
3 ~IOB2:NDRIVE[1]-
4 IOB2:PDRIVE[0]-
5 IOB2:NDRIVE[2]-
6 IOB2:IBUF_MODE[2]-
7 -IOB2:PDRIVE[2]
8 --
9 --
10 --
11 IOB2:PULL[0]-
12 ~IOB2:PDRIVE[1]-
13 --
14 --
15 --
16 --
17 IOB3:PDRIVE[2]-
18 IOB3:NDRIVE[2]-
19 ~IOB3:PDRIVE[1]-
20 IOB3:PDRIVE[0]~IOB3:NDRIVE[1]
21 IOB3:IBUF_MODE[2]-
22 IOB3:PCI_CLAMP-
23 IOB3:PULL[2]-
24 IOB3:IBUF_MODE[1]-
25 IOB3:IBUF_MODE[0]-
26 IOB3:SUSPEND[3]IOB3:SUSPEND[1]
27 --
28 IOB3:VREF-
29 IOB3:NDRIVE[0]-
30 IOB3:OUTPUT_ENABLE[0]-
31 --
32 IOB3:OUTPUT_ENABLE[1]-
33 IOB3:SUSPEND[2]-
34 IOB3:NSLEW[0]-
35 IOB3:NSLEW[1]-
36 --
37 IOB3:NSLEW[2]-
38 IOB3:NSLEW[3]-
39 --
40 IOB3:PULL[1]-
41 IOB3:PULL[0]-
42 IOB3:PSLEW[0]-
43 IOB3:PSLEW[1]-
44 IOB3:PCI_INPUT-
45 IOB3:PSLEW[2]-
46 IOB3:PSLEW[3]IOB3:SUSPEND[0]
47 --
48 --
49 --
50 IOB4:PSLEW[3]-
51 IOB4:PSLEW[2]-
52 IOB4:PCI_INPUTIOB4:SUSPEND[0]
53 IOB4:PSLEW[0]-
54 IOB4:PSLEW[1]-
55 IOB4:PULL[0]-
56 IOB4:PULL[1]-
57 --
58 IOB4:NSLEW[3]IOB4:NSLEW[2]
59 --
60 IOB4:NSLEW[1]-
61 IOB4:NSLEW[0]-
62 IOB4:SUSPEND[2]-
63 IOB4:OUTPUT_ENABLE[0]-
IOBS.S3A.L4 bittile 2
RowColumn
01
0 IOB4:OUTPUT_ENABLE[1]-
1 IOB5:PULL[0]-
2 IOB4:SUSPEND[3]-
3 IOB4:VREF-
4 --
5 IOB4:SUSPEND[1]-
6 IOB4:IBUF_MODE[0]-
7 IOB4:IBUF_MODE[1]IOB4:IBUF_MODE[2]
8 IOB4:PULL[2]-
9 IOB4:PCI_CLAMP-
10 IOB4:NDRIVE[0]-
11 ~IOB4:NDRIVE[1]-
12 IOB4:PDRIVE[0]-
13 ~IOB4:PDRIVE[1]-
14 IOB4:NDRIVE[2]IOB4:PDRIVE[2]
15 --
16 --
17 --
18 --
19 --
20 -IOB5:PULL[1]
21 --
22 --
23 --
24 --
25 --
26 IOB5:PDRIVE[2]IOB5:PDRIVE[0]
27 ~IOB5:PDRIVE[1]-
28 IOB5:NDRIVE[2]-
29 IOB5:IBUF_MODE[2]-
30 IOB5:PCI_CLAMP-
31 IOB5:PULL[2]-
32 IOB5:NDRIVE[0]-
33 IOB5:IBUF_MODE[1]-
34 IOB5:IBUF_MODE[0]-
35 IOB5:SUSPEND[1]-
36 --
37 --
38 --
39 IOB5:OUTPUT_ENABLE[0]IOB5:SUSPEND[3]
40 IOB5:OUTPUT_ENABLE[1]-
41 IOB5:SUSPEND[2]-
42 IOB5:NSLEW[0]-
43 IOB5:SUSPEND[0]-
44 IOB5:NSLEW[1]-
45 IOB5:NSLEW[2]-
46 IOB5:NSLEW[3]-
47 --
48 ~IOB5:NDRIVE[1]-
49 --
50 IOB5:PSLEW[0]-
51 IOB5:PSLEW[1]-
52 IOB5:PCI_INPUTIOB5:PSLEW[2]
53 IOB5:PSLEW[3]-
54 --
55 IOB6:NSLEW[1]-
56 --
57 --
58 IOB6:PSLEW[3]IOB6:PSLEW[2]
59 IOB6:PCI_INPUT-
60 IOB6:PSLEW[1]-
61 IOB6:PSLEW[0]-
62 --
63 IOB6:PULL[0]-
IOBS.S3A.L4 bittile 3
RowColumn
01
0 IOB6:PULL[1]-
1 IOB7:PULL[0]-
2 IOB6:NSLEW[3]-
3 IOB6:NSLEW[2]-
4 --
5 IOB7:PULL[1]-
6 IOB6:NSLEW[0]-
7 IOB6:OUTPUT_ENABLE[0]IOB6:SUSPEND[2]
8 IOB6:OUTPUT_ENABLE[1]-
9 IOB6:SUSPEND[0]-
10 --
11 IOB6:SUSPEND[3]-
12 IOB6:VREF-
13 IOB6:SUSPEND[1]-
14 IOB6:IBUF_MODE[1]IOB6:IBUF_MODE[0]
15 IOB6:PCI_CLAMP-
16 IOB6:NDRIVE[0]-
17 IOB6:PULL[2]-
18 IOB6:IBUF_MODE[2]-
19 ~IOB6:NDRIVE[1]-
20 IOB6:PDRIVE[0]IOB6:NDRIVE[2]
21 ~IOB6:PDRIVE[1]-
22 --
23 IOB6:PDRIVE[2]-
24 --
25 --
26 --
27 --
28 --
29 --
30 --
31 --
32 --
33 IOB7:PDRIVE[2]-
34 IOB7:NDRIVE[2]-
35 ~IOB7:PDRIVE[1]-
36 IOB7:PDRIVE[0]-
37 ~IOB7:NDRIVE[1]-
38 IOB7:IBUF_MODE[2]-
39 IOB7:SUSPEND[0]IOB7:PCI_CLAMP
40 IOB7:NDRIVE[0]-
41 IOB7:IBUF_MODE[0]-
42 IOB7:IBUF_MODE[1]-
43 IOB7:SUSPEND[1]-
44 IOB7:VREF-
45 IOB7:SUSPEND[3]-
46 -IOB7:OUTPUT_ENABLE[1]
47 IOB7:PULL[2]-
48 IOB7:OUTPUT_ENABLE[0]-
49 IOB7:SUSPEND[2]-
50 IOB7:NSLEW[0]-
51 IOB7:NSLEW[1]-
52 IOB7:PSLEW[1]IOB7:NSLEW[2]
53 IOB7:NSLEW[3]-
54 IOB7:PSLEW[2]-
55 IOB7:PCI_INPUT-
56 IOB7:PSLEW[0]-
57 IOB7:PSLEW[3]-
IOB0:PULL[0, 1, 11][0, 0, 8][0, 0, 7]
IOB1:PULL[0, 0, 32][0, 0, 36][0, 0, 38]
IOB2:PULL[1, 0, 0][0, 0, 48][1, 0, 11]
IOB3:PULL[1, 0, 23][1, 0, 40][1, 0, 41]
IOB4:PULL[2, 0, 8][1, 0, 56][1, 0, 55]
IOB5:PULL[2, 0, 31][2, 1, 20][2, 0, 1]
IOB6:PULL[3, 0, 17][3, 0, 0][2, 0, 63]
IOB7:PULL[3, 0, 47][3, 0, 5][3, 0, 1]
PULLDOWN000
NONE001
PULLUP011
KEEPER101
IOB0:IBUF_MODE[0, 0, 13][0, 0, 12][0, 0, 11]
IOB1:IBUF_MODE[0, 0, 27][0, 0, 30][0, 0, 31]
IOB2:IBUF_MODE[1, 0, 6][0, 0, 63][0, 0, 62]
IOB3:IBUF_MODE[1, 0, 21][1, 0, 24][1, 0, 25]
IOB4:IBUF_MODE[2, 1, 7][2, 0, 7][2, 0, 6]
IOB5:IBUF_MODE[2, 0, 29][2, 0, 33][2, 0, 34]
IOB6:IBUF_MODE[3, 0, 18][3, 0, 14][3, 1, 14]
IOB7:IBUF_MODE[3, 0, 38][3, 0, 42][3, 0, 41]
NONE000
TMUX001
OMUX010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
DIFF110
CMOS_VCCAUX111
IOB0:PCI_INPUT[0, 0, 17]
IOB0:VREF[0, 0, 14]
IOB1:PCI_INPUT[0, 0, 25]
IOB2:PCI_CLAMP[1, 0, 1]
IOB2:PCI_INPUT[0, 0, 44]
IOB3:PCI_CLAMP[1, 0, 22]
IOB3:PCI_INPUT[1, 0, 44]
IOB3:VREF[1, 0, 28]
IOB4:PCI_CLAMP[2, 0, 9]
IOB4:PCI_INPUT[1, 0, 52]
IOB4:VREF[2, 0, 3]
IOB5:PCI_CLAMP[2, 0, 30]
IOB5:PCI_INPUT[2, 0, 52]
IOB6:PCI_CLAMP[3, 0, 15]
IOB6:PCI_INPUT[2, 0, 59]
IOB6:VREF[3, 0, 12]
IOB7:PCI_CLAMP[3, 1, 39]
IOB7:PCI_INPUT[3, 0, 55]
IOB7:VREF[3, 0, 44]
Non-inverted[0]
IOB2:NSLEW[0, 0, 50][0, 0, 51][0, 1, 52][0, 0, 53]
IOB2:PSLEW[0, 0, 42][0, 0, 43][0, 0, 45][0, 0, 46]
IOB3:NSLEW[1, 0, 38][1, 0, 37][1, 0, 35][1, 0, 34]
IOB3:PSLEW[1, 0, 46][1, 0, 45][1, 0, 43][1, 0, 42]
IOB4:NSLEW[1, 0, 58][1, 1, 58][1, 0, 60][1, 0, 61]
IOB4:PSLEW[1, 0, 50][1, 0, 51][1, 0, 54][1, 0, 53]
IOB5:NSLEW[2, 0, 46][2, 0, 45][2, 0, 44][2, 0, 42]
IOB5:PSLEW[2, 0, 53][2, 1, 52][2, 0, 51][2, 0, 50]
IOB6:NSLEW[3, 0, 2][3, 0, 3][2, 0, 55][3, 0, 6]
IOB6:PSLEW[2, 0, 58][2, 1, 58][2, 0, 60][2, 0, 61]
IOB7:NSLEW[3, 0, 53][3, 1, 52][3, 0, 51][3, 0, 50]
IOB7:PSLEW[3, 0, 57][3, 0, 54][3, 0, 52][3, 0, 56]
Non-inverted[3][2][1][0]
IOB2:OUTPUT_ENABLE[0, 0, 56][0, 0, 55]
IOB3:OUTPUT_ENABLE[1, 0, 32][1, 0, 30]
IOB4:OUTPUT_ENABLE[2, 0, 0][1, 0, 63]
IOB5:OUTPUT_ENABLE[2, 0, 40][2, 0, 39]
IOB6:OUTPUT_ENABLE[3, 0, 8][3, 0, 7]
IOB7:OUTPUT_ENABLE[3, 1, 46][3, 0, 48]
Non-inverted[1][0]
IOB2:SUSPEND[0, 0, 61][0, 0, 54][0, 0, 60][0, 1, 46]
IOB3:SUSPEND[1, 0, 26][1, 0, 33][1, 1, 26][1, 1, 46]
IOB4:SUSPEND[2, 0, 2][1, 0, 62][2, 0, 5][1, 1, 52]
IOB5:SUSPEND[2, 1, 39][2, 0, 41][2, 0, 35][2, 0, 43]
IOB6:SUSPEND[3, 0, 11][3, 1, 7][3, 0, 13][3, 0, 9]
IOB7:SUSPEND[3, 0, 45][3, 0, 49][3, 0, 43][3, 0, 39]
3STATE0000
DRIVE_LAST_VALUE0001
3STATE_PULLUP0010
3STATE_PULLDOWN0100
3STATE_KEEPER1000
IOB2:NDRIVE[1, 0, 5][1, 0, 3][1, 0, 2]
IOB2:PDRIVE[1, 1, 7][1, 0, 12][1, 0, 4]
IOB3:NDRIVE[1, 0, 18][1, 1, 20][1, 0, 29]
IOB3:PDRIVE[1, 0, 17][1, 0, 19][1, 0, 20]
IOB4:NDRIVE[2, 0, 14][2, 0, 11][2, 0, 10]
IOB4:PDRIVE[2, 1, 14][2, 0, 13][2, 0, 12]
IOB5:NDRIVE[2, 0, 28][2, 0, 48][2, 0, 32]
IOB5:PDRIVE[2, 0, 26][2, 0, 27][2, 1, 26]
IOB6:NDRIVE[3, 1, 20][3, 0, 19][3, 0, 16]
IOB6:PDRIVE[3, 0, 23][3, 0, 21][3, 0, 20]
IOB7:NDRIVE[3, 0, 34][3, 0, 37][3, 0, 40]
IOB7:PDRIVE[3, 0, 33][3, 0, 35][3, 0, 36]
Mixed inversion[2]~[1][0]