Clock interconnect

Bitstream — bottom tile

REG_B bittile 0
Row	Column
	0
0	BUFIO2_6:I[0]
1	BUFIO2_6:I[1]
2	BUFIO2_6:I[2]
3	BUFIO2_6:IB[0]
4	BUFIO2_6:IB[1]
5	BUFIO2_6:IB[2]
6	BUFIO2_6:FB_I[0]
7	BUFIO2_6:FB_I[1]
8	BUFIO2_6:FB_I[2]
9	BUFIO2_6:POS_EDGE[0]
10	BUFIO2_6:POS_EDGE[1]
11	BUFIO2_6:POS_EDGE[2]
12	BUFIO2_6:NEG_EDGE[0]
13	BUFIO2_6:NEG_EDGE[1]
14	-
15	BUFIO2_6:DIVIDE[0]
16	BUFIO2_6:DIVIDE[1]
17	BUFIO2_6:DIVIDE[2]
18	BUFIO2_6:R_EDGE
19	BUFIO2_6:ENABLE
20	BUFIO2_6:ENABLE_2CLK
21	-
22	-
23	-
24	-
25	-
26	-
27	~BUFIO2_6:FB_DIVIDE_BYPASS[0]
28	~BUFIO2_6:FB_DIVIDE_BYPASS[1]
29	~BUFIO2_6:FB_DIVIDE_BYPASS[2]
30	-
31	BUFIO2_6:FB_ENABLE
32	-
33	~BUFIO2_6:DIVIDE_BYPASS
34	~BUFIO2_6:FB_DIVIDE_BYPASS[3]
35	BUFIO2_6:CKPIN[1]
36	BUFIO2_6:IOCLK_ENABLE
37	BUFIO2_6:CKPIN[0]
38	BUFIO2_6:CMT_ENABLE
39	INT:MUX.IMUX.REGB.GCLK1[4]
40	INT:MUX.IMUX.REGB.GCLK1[5]
41	INT:MUX.IMUX.REGB.GCLK1[6]
42	INT:MUX.IMUX.REGB.GCLK1[7]
43	INT:MUX.IMUX.REGB.GCLK1[0]
44	INT:MUX.IMUX.REGB.GCLK1[1]
45	INT:MUX.IMUX.REGB.GCLK1[2]
46	INT:MUX.IMUX.REGB.GCLK1[3]
47	INT:MUX.IMUX.REGB.GCLK0[3]
48	BUFIO2_7:I[0]
49	BUFIO2_7:I[1]
50	BUFIO2_7:I[2]
51	BUFIO2_7:IB[0]
52	BUFIO2_7:IB[1]
53	BUFIO2_7:IB[2]
54	BUFIO2_7:FB_I[0]
55	BUFIO2_7:FB_I[1]
56	BUFIO2_7:FB_I[2]
57	BUFIO2_7:POS_EDGE[0]
58	BUFIO2_7:POS_EDGE[1]
59	BUFIO2_7:POS_EDGE[2]
60	BUFIO2_7:NEG_EDGE[0]
61	BUFIO2_7:NEG_EDGE[1]
62	-
63	BUFIO2_7:DIVIDE[0]
64	BUFIO2_7:DIVIDE[1]
65	BUFIO2_7:DIVIDE[2]
66	BUFIO2_7:R_EDGE
67	BUFIO2_7:ENABLE
68	BUFIO2_7:ENABLE_2CLK
69	-
70	-
71	-
72	-
73	-
74	-
75	~BUFIO2_7:FB_DIVIDE_BYPASS[0]
76	~BUFIO2_7:FB_DIVIDE_BYPASS[1]
77	~BUFIO2_7:FB_DIVIDE_BYPASS[2]
78	-
79	BUFIO2_7:FB_ENABLE
80	-
81	~BUFIO2_7:DIVIDE_BYPASS
82	~BUFIO2_7:FB_DIVIDE_BYPASS[3]
83	BUFIO2_7:CKPIN[1]
84	BUFIO2_7:IOCLK_ENABLE
85	BUFIO2_7:CKPIN[0]
86	BUFIO2_7:CMT_ENABLE
87	INT:MUX.IMUX.REGB.GCLK0[2]
88	INT:MUX.IMUX.REGB.GCLK0[1]
89	INT:MUX.IMUX.REGB.GCLK0[0]
90	INT:MUX.IMUX.REGB.GCLK0[7]
91	INT:MUX.IMUX.REGB.GCLK0[6]
92	INT:MUX.IMUX.REGB.GCLK0[5]
93	INT:MUX.IMUX.REGB.GCLK0[4]
94	-
95	-
96	BUFIO2_4:I[0]
97	BUFIO2_4:I[1]
98	BUFIO2_4:I[2]
99	BUFIO2_4:IB[0]
100	BUFIO2_4:IB[1]
101	BUFIO2_4:IB[2]
102	BUFIO2_4:FB_I[0]
103	BUFIO2_4:FB_I[1]
104	BUFIO2_4:FB_I[2]
105	BUFIO2_4:POS_EDGE[0]
106	BUFIO2_4:POS_EDGE[1]
107	BUFIO2_4:POS_EDGE[2]
108	BUFIO2_4:NEG_EDGE[0]
109	BUFIO2_4:NEG_EDGE[1]
110	-
111	BUFIO2_4:DIVIDE[0]
112	BUFIO2_4:DIVIDE[1]
113	BUFIO2_4:DIVIDE[2]
114	BUFIO2_4:R_EDGE
115	BUFIO2_4:ENABLE
116	BUFIO2_4:ENABLE_2CLK
117	-
118	-
119	-
120	-
121	-
122	-
123	~BUFIO2_4:FB_DIVIDE_BYPASS[0]
124	~BUFIO2_4:FB_DIVIDE_BYPASS[1]
125	~BUFIO2_4:FB_DIVIDE_BYPASS[2]
126	-
127	BUFIO2_4:FB_ENABLE
128	-
129	~BUFIO2_4:DIVIDE_BYPASS
130	~BUFIO2_4:FB_DIVIDE_BYPASS[3]
131	BUFIO2_4:CKPIN[1]
132	BUFIO2_4:IOCLK_ENABLE
133	BUFIO2_4:CKPIN[0]
134	BUFIO2_4:CMT_ENABLE
135	BUFPLL_COMMON:ENABLE
136	BUFPLL0:DIVIDE[0]
137	BUFPLL0:DIVIDE[1]
138	BUFPLL0:DIVIDE[2]
139	BUFPLL_MCB:LOCK_SRC[1]
140	~BUFPLL0:ENABLE_SYNC
141	BUFPLL0:DATA_RATE
142	BUFPLL1:DIVIDE[0]
143	BUFPLL1:DIVIDE[1]
144	BUFIO2_5:I[0]
145	BUFIO2_5:I[1]
146	BUFIO2_5:I[2]
147	BUFIO2_5:IB[0]
148	BUFIO2_5:IB[1]
149	BUFIO2_5:IB[2]
150	BUFIO2_5:FB_I[0]
151	BUFIO2_5:FB_I[1]
152	BUFIO2_5:FB_I[2]
153	BUFIO2_5:POS_EDGE[0]
154	BUFIO2_5:POS_EDGE[1]
155	BUFIO2_5:POS_EDGE[2]
156	BUFIO2_5:NEG_EDGE[0]
157	BUFIO2_5:NEG_EDGE[1]
158	-
159	BUFIO2_5:DIVIDE[0]
160	BUFIO2_5:DIVIDE[1]
161	BUFIO2_5:DIVIDE[2]
162	BUFIO2_5:R_EDGE
163	BUFIO2_5:ENABLE
164	BUFIO2_5:ENABLE_2CLK
165	-
166	-
167	-
168	-
169	-
170	-
171	~BUFIO2_5:FB_DIVIDE_BYPASS[0]
172	~BUFIO2_5:FB_DIVIDE_BYPASS[1]
173	~BUFIO2_5:FB_DIVIDE_BYPASS[2]
174	-
175	BUFIO2_5:FB_ENABLE
176	-
177	~BUFIO2_5:DIVIDE_BYPASS
178	~BUFIO2_5:FB_DIVIDE_BYPASS[3]
179	BUFIO2_5:CKPIN[1]
180	BUFIO2_5:IOCLK_ENABLE
181	BUFIO2_5:CKPIN[0]
182	BUFIO2_5:CMT_ENABLE
183	BUFPLL1:DIVIDE[2]
184	BUFPLL_MCB:LOCK_SRC[0]
185	~BUFPLL1:ENABLE_SYNC
186	BUFPLL1:DATA_RATE
187	BUFPLL0:DIVIDE[3]
188	-
189	BUFPLL0:DIVIDE[4]
190	BUFPLL0:DIVIDE[5]
191	BUFPLL1:DIVIDE[3]
192	BUFIO2_2:I[0]
193	BUFIO2_2:I[1]
194	BUFIO2_2:I[2]
195	BUFIO2_2:IB[0]
196	BUFIO2_2:IB[1]
197	BUFIO2_2:IB[2]
198	BUFIO2_2:FB_I[0]
199	BUFIO2_2:FB_I[1]
200	BUFIO2_2:FB_I[2]
201	BUFIO2_2:POS_EDGE[0]
202	BUFIO2_2:POS_EDGE[1]
203	BUFIO2_2:POS_EDGE[2]
204	BUFIO2_2:NEG_EDGE[0]
205	BUFIO2_2:NEG_EDGE[1]
206	-
207	BUFIO2_2:DIVIDE[0]
208	BUFIO2_2:DIVIDE[1]
209	BUFIO2_2:DIVIDE[2]
210	BUFIO2_2:R_EDGE
211	BUFIO2_2:ENABLE
212	BUFIO2_2:ENABLE_2CLK
213	-
214	-
215	-
216	-
217	-
218	-
219	~BUFIO2_2:FB_DIVIDE_BYPASS[0]
220	~BUFIO2_2:FB_DIVIDE_BYPASS[1]
221	~BUFIO2_2:FB_DIVIDE_BYPASS[2]
222	-
223	BUFIO2_2:FB_ENABLE
224	-
225	~BUFIO2_2:DIVIDE_BYPASS
226	~BUFIO2_2:FB_DIVIDE_BYPASS[3]
227	BUFIO2_2:CKPIN[1]
228	BUFIO2_2:IOCLK_ENABLE
229	BUFIO2_2:CKPIN[0]
230	BUFIO2_2:CMT_ENABLE
231	-
232	BUFPLL1:DIVIDE[4]
233	BUFPLL1:DIVIDE[5]
234	BUFPLL0:ENABLE_BOTH_SYNC[0]
235	-
236	-
237	BUFPLL1:ENABLE_BOTH_SYNC[0]
238	-
239	-
240	BUFIO2_3:I[0]
241	BUFIO2_3:I[1]
242	BUFIO2_3:I[2]
243	BUFIO2_3:IB[0]
244	BUFIO2_3:IB[1]
245	BUFIO2_3:IB[2]
246	BUFIO2_3:FB_I[0]
247	BUFIO2_3:FB_I[1]
248	BUFIO2_3:FB_I[2]
249	BUFIO2_3:POS_EDGE[0]
250	BUFIO2_3:POS_EDGE[1]
251	BUFIO2_3:POS_EDGE[2]
252	BUFIO2_3:NEG_EDGE[0]
253	BUFIO2_3:NEG_EDGE[1]
254	-
255	BUFIO2_3:DIVIDE[0]
256	BUFIO2_3:DIVIDE[1]
257	BUFIO2_3:DIVIDE[2]
258	BUFIO2_3:R_EDGE
259	BUFIO2_3:ENABLE
260	BUFIO2_3:ENABLE_2CLK
261	-
262	-
263	-
264	-
265	-
266	-
267	~BUFIO2_3:FB_DIVIDE_BYPASS[0]
268	~BUFIO2_3:FB_DIVIDE_BYPASS[1]
269	~BUFIO2_3:FB_DIVIDE_BYPASS[2]
270	-
271	BUFIO2_3:FB_ENABLE
272	-
273	~BUFIO2_3:DIVIDE_BYPASS
274	~BUFIO2_3:FB_DIVIDE_BYPASS[3]
275	BUFIO2_3:CKPIN[1]
276	BUFIO2_3:IOCLK_ENABLE
277	BUFIO2_3:CKPIN[0]
278	BUFIO2_3:CMT_ENABLE
279	BUFPLL0:ENABLE_NONE_SYNC[0]
280	BUFPLL0:ENABLE_BOTH_SYNC[1]
281	BUFPLL1:ENABLE_NONE_SYNC[0]
282	BUFPLL1:ENABLE_BOTH_SYNC[1]
283	-
284	-
285	BUFPLL0:ENABLE_NONE_SYNC[1]
286	BUFPLL0:ENABLE_BOTH_SYNC[2]
287	-
288	BUFIO2_0:I[0]
289	BUFIO2_0:I[1]
290	BUFIO2_0:I[2]
291	BUFIO2_0:IB[0]
292	BUFIO2_0:IB[1]
293	BUFIO2_0:IB[2]
294	BUFIO2_0:FB_I[0]
295	BUFIO2_0:FB_I[1]
296	BUFIO2_0:FB_I[2]
297	BUFIO2_0:POS_EDGE[0]
298	BUFIO2_0:POS_EDGE[1]
299	BUFIO2_0:POS_EDGE[2]
300	BUFIO2_0:NEG_EDGE[0]
301	BUFIO2_0:NEG_EDGE[1]
302	-
303	BUFIO2_0:DIVIDE[0]
304	BUFIO2_0:DIVIDE[1]
305	BUFIO2_0:DIVIDE[2]
306	BUFIO2_0:R_EDGE
307	BUFIO2_0:ENABLE
308	BUFIO2_0:ENABLE_2CLK
309	-
310	-
311	-
312	-
313	-
314	-
315	~BUFIO2_0:FB_DIVIDE_BYPASS[0]
316	~BUFIO2_0:FB_DIVIDE_BYPASS[1]
317	~BUFIO2_0:FB_DIVIDE_BYPASS[2]
318	-
319	BUFIO2_0:FB_ENABLE
320	-
321	~BUFIO2_0:DIVIDE_BYPASS
322	~BUFIO2_0:FB_DIVIDE_BYPASS[3]
323	BUFIO2_0:CKPIN[1]
324	BUFIO2_0:IOCLK_ENABLE
325	BUFIO2_0:CKPIN[0]
326	BUFIO2_0:CMT_ENABLE
327	-
328	BUFPLL1:ENABLE_NONE_SYNC[1]
329	BUFPLL1:ENABLE_BOTH_SYNC[2]
330	BUFPLL0:PLLIN[0]
331	BUFPLL0:PLLIN[1]
332	BUFPLL0:PLLIN[2]
333	BUFPLL1:PLLIN[0]
334	BUFPLL1:PLLIN[1]
335	BUFPLL1:PLLIN[2]
336	BUFIO2_1:I[0]
337	BUFIO2_1:I[1]
338	BUFIO2_1:I[2]
339	BUFIO2_1:IB[0]
340	BUFIO2_1:IB[1]
341	BUFIO2_1:IB[2]
342	BUFIO2_1:FB_I[0]
343	BUFIO2_1:FB_I[1]
344	BUFIO2_1:FB_I[2]
345	BUFIO2_1:POS_EDGE[0]
346	BUFIO2_1:POS_EDGE[1]
347	BUFIO2_1:POS_EDGE[2]
348	BUFIO2_1:NEG_EDGE[0]
349	BUFIO2_1:NEG_EDGE[1]
350	-
351	BUFIO2_1:DIVIDE[0]
352	BUFIO2_1:DIVIDE[1]
353	BUFIO2_1:DIVIDE[2]
354	BUFIO2_1:R_EDGE
355	BUFIO2_1:ENABLE
356	BUFIO2_1:ENABLE_2CLK
357	-
358	-
359	-
360	-
361	-
362	-
363	~BUFIO2_1:FB_DIVIDE_BYPASS[0]
364	~BUFIO2_1:FB_DIVIDE_BYPASS[1]
365	~BUFIO2_1:FB_DIVIDE_BYPASS[2]
366	-
367	BUFIO2_1:FB_ENABLE
368	-
369	~BUFIO2_1:DIVIDE_BYPASS
370	~BUFIO2_1:FB_DIVIDE_BYPASS[3]
371	BUFIO2_1:CKPIN[1]
372	BUFIO2_1:IOCLK_ENABLE
373	BUFIO2_1:CKPIN[0]
374	BUFIO2_1:CMT_ENABLE
375	BUFPLL0:LOCKED[0]
376	BUFPLL0:LOCKED[1]
377	BUFPLL1:LOCKED[0]
378	BUFPLL1:LOCKED[1]
379	MISC:MISR_ENABLE
380	MISC:MISR_RESET

BUFIO2_0:I	[0, 0, 290]	[0, 0, 289]	[0, 0, 288]
BUFIO2_1:I	[0, 0, 338]	[0, 0, 337]	[0, 0, 336]
BUFIO2_2:I	[0, 0, 194]	[0, 0, 193]	[0, 0, 192]
BUFIO2_3:I	[0, 0, 242]	[0, 0, 241]	[0, 0, 240]
BUFIO2_4:I	[0, 0, 98]	[0, 0, 97]	[0, 0, 96]
BUFIO2_5:I	[0, 0, 146]	[0, 0, 145]	[0, 0, 144]
BUFIO2_6:I	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
BUFIO2_7:I	[0, 0, 50]	[0, 0, 49]	[0, 0, 48]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2_0:IB	[0, 0, 293]	[0, 0, 292]	[0, 0, 291]
BUFIO2_1:IB	[0, 0, 341]	[0, 0, 340]	[0, 0, 339]
BUFIO2_2:IB	[0, 0, 197]	[0, 0, 196]	[0, 0, 195]
BUFIO2_3:IB	[0, 0, 245]	[0, 0, 244]	[0, 0, 243]
BUFIO2_4:IB	[0, 0, 101]	[0, 0, 100]	[0, 0, 99]
BUFIO2_5:IB	[0, 0, 149]	[0, 0, 148]	[0, 0, 147]
BUFIO2_6:IB	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
BUFIO2_7:IB	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2_0:FB_I	[0, 0, 296]	[0, 0, 295]	[0, 0, 294]
BUFIO2_1:FB_I	[0, 0, 344]	[0, 0, 343]	[0, 0, 342]
BUFIO2_2:FB_I	[0, 0, 200]	[0, 0, 199]	[0, 0, 198]
BUFIO2_3:FB_I	[0, 0, 248]	[0, 0, 247]	[0, 0, 246]
BUFIO2_4:FB_I	[0, 0, 104]	[0, 0, 103]	[0, 0, 102]
BUFIO2_5:FB_I	[0, 0, 152]	[0, 0, 151]	[0, 0, 150]
BUFIO2_6:FB_I	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
BUFIO2_7:FB_I	[0, 0, 56]	[0, 0, 55]	[0, 0, 54]
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2_0:POS_EDGE	[0, 0, 299]	[0, 0, 298]	[0, 0, 297]
BUFIO2_1:POS_EDGE	[0, 0, 347]	[0, 0, 346]	[0, 0, 345]
BUFIO2_2:POS_EDGE	[0, 0, 203]	[0, 0, 202]	[0, 0, 201]
BUFIO2_3:POS_EDGE	[0, 0, 251]	[0, 0, 250]	[0, 0, 249]
BUFIO2_4:POS_EDGE	[0, 0, 107]	[0, 0, 106]	[0, 0, 105]
BUFIO2_5:POS_EDGE	[0, 0, 155]	[0, 0, 154]	[0, 0, 153]
BUFIO2_6:POS_EDGE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
BUFIO2_7:POS_EDGE	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2_0:NEG_EDGE	[0, 0, 301]	[0, 0, 300]
BUFIO2_1:NEG_EDGE	[0, 0, 349]	[0, 0, 348]
BUFIO2_2:NEG_EDGE	[0, 0, 205]	[0, 0, 204]
BUFIO2_3:NEG_EDGE	[0, 0, 253]	[0, 0, 252]
BUFIO2_4:NEG_EDGE	[0, 0, 109]	[0, 0, 108]
BUFIO2_5:NEG_EDGE	[0, 0, 157]	[0, 0, 156]
BUFIO2_6:NEG_EDGE	[0, 0, 13]	[0, 0, 12]
BUFIO2_7:NEG_EDGE	[0, 0, 61]	[0, 0, 60]
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2_0:DIVIDE	[0, 0, 305]	[0, 0, 304]	[0, 0, 303]
BUFIO2_1:DIVIDE	[0, 0, 353]	[0, 0, 352]	[0, 0, 351]
BUFIO2_2:DIVIDE	[0, 0, 209]	[0, 0, 208]	[0, 0, 207]
BUFIO2_3:DIVIDE	[0, 0, 257]	[0, 0, 256]	[0, 0, 255]
BUFIO2_4:DIVIDE	[0, 0, 113]	[0, 0, 112]	[0, 0, 111]
BUFIO2_5:DIVIDE	[0, 0, 161]	[0, 0, 160]	[0, 0, 159]
BUFIO2_6:DIVIDE	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]
BUFIO2_7:DIVIDE	[0, 0, 65]	[0, 0, 64]	[0, 0, 63]
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2_0:CMT_ENABLE	[0, 0, 326]
BUFIO2_0:ENABLE	[0, 0, 307]
BUFIO2_0:ENABLE_2CLK	[0, 0, 308]
BUFIO2_0:FB_ENABLE	[0, 0, 319]
BUFIO2_0:IOCLK_ENABLE	[0, 0, 324]
BUFIO2_0:R_EDGE	[0, 0, 306]
BUFIO2_1:CMT_ENABLE	[0, 0, 374]
BUFIO2_1:ENABLE	[0, 0, 355]
BUFIO2_1:ENABLE_2CLK	[0, 0, 356]
BUFIO2_1:FB_ENABLE	[0, 0, 367]
BUFIO2_1:IOCLK_ENABLE	[0, 0, 372]
BUFIO2_1:R_EDGE	[0, 0, 354]
BUFIO2_2:CMT_ENABLE	[0, 0, 230]
BUFIO2_2:ENABLE	[0, 0, 211]
BUFIO2_2:ENABLE_2CLK	[0, 0, 212]
BUFIO2_2:FB_ENABLE	[0, 0, 223]
BUFIO2_2:IOCLK_ENABLE	[0, 0, 228]
BUFIO2_2:R_EDGE	[0, 0, 210]
BUFIO2_3:CMT_ENABLE	[0, 0, 278]
BUFIO2_3:ENABLE	[0, 0, 259]
BUFIO2_3:ENABLE_2CLK	[0, 0, 260]
BUFIO2_3:FB_ENABLE	[0, 0, 271]
BUFIO2_3:IOCLK_ENABLE	[0, 0, 276]
BUFIO2_3:R_EDGE	[0, 0, 258]
BUFIO2_4:CMT_ENABLE	[0, 0, 134]
BUFIO2_4:ENABLE	[0, 0, 115]
BUFIO2_4:ENABLE_2CLK	[0, 0, 116]
BUFIO2_4:FB_ENABLE	[0, 0, 127]
BUFIO2_4:IOCLK_ENABLE	[0, 0, 132]
BUFIO2_4:R_EDGE	[0, 0, 114]
BUFIO2_5:CMT_ENABLE	[0, 0, 182]
BUFIO2_5:ENABLE	[0, 0, 163]
BUFIO2_5:ENABLE_2CLK	[0, 0, 164]
BUFIO2_5:FB_ENABLE	[0, 0, 175]
BUFIO2_5:IOCLK_ENABLE	[0, 0, 180]
BUFIO2_5:R_EDGE	[0, 0, 162]
BUFIO2_6:CMT_ENABLE	[0, 0, 38]
BUFIO2_6:ENABLE	[0, 0, 19]
BUFIO2_6:ENABLE_2CLK	[0, 0, 20]
BUFIO2_6:FB_ENABLE	[0, 0, 31]
BUFIO2_6:IOCLK_ENABLE	[0, 0, 36]
BUFIO2_6:R_EDGE	[0, 0, 18]
BUFIO2_7:CMT_ENABLE	[0, 0, 86]
BUFIO2_7:ENABLE	[0, 0, 67]
BUFIO2_7:ENABLE_2CLK	[0, 0, 68]
BUFIO2_7:FB_ENABLE	[0, 0, 79]
BUFIO2_7:IOCLK_ENABLE	[0, 0, 84]
BUFIO2_7:R_EDGE	[0, 0, 66]
BUFPLL_COMMON:ENABLE	[0, 0, 135]
MISC:MISR_ENABLE	[0, 0, 379]
MISC:MISR_RESET	[0, 0, 380]
Non-inverted	[0]

BUFIO2_0:FB_DIVIDE_BYPASS	[0, 0, 322]	[0, 0, 317]	[0, 0, 316]	[0, 0, 315]
BUFIO2_1:FB_DIVIDE_BYPASS	[0, 0, 370]	[0, 0, 365]	[0, 0, 364]	[0, 0, 363]
BUFIO2_2:FB_DIVIDE_BYPASS	[0, 0, 226]	[0, 0, 221]	[0, 0, 220]	[0, 0, 219]
BUFIO2_3:FB_DIVIDE_BYPASS	[0, 0, 274]	[0, 0, 269]	[0, 0, 268]	[0, 0, 267]
BUFIO2_4:FB_DIVIDE_BYPASS	[0, 0, 130]	[0, 0, 125]	[0, 0, 124]	[0, 0, 123]
BUFIO2_5:FB_DIVIDE_BYPASS	[0, 0, 178]	[0, 0, 173]	[0, 0, 172]	[0, 0, 171]
BUFIO2_6:FB_DIVIDE_BYPASS	[0, 0, 34]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]
BUFIO2_7:FB_DIVIDE_BYPASS	[0, 0, 82]	[0, 0, 77]	[0, 0, 76]	[0, 0, 75]
Inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2_0:DIVIDE_BYPASS	[0, 0, 321]
BUFIO2_1:DIVIDE_BYPASS	[0, 0, 369]
BUFIO2_2:DIVIDE_BYPASS	[0, 0, 225]
BUFIO2_3:DIVIDE_BYPASS	[0, 0, 273]
BUFIO2_4:DIVIDE_BYPASS	[0, 0, 129]
BUFIO2_5:DIVIDE_BYPASS	[0, 0, 177]
BUFIO2_6:DIVIDE_BYPASS	[0, 0, 33]
BUFIO2_7:DIVIDE_BYPASS	[0, 0, 81]
BUFPLL0:ENABLE_SYNC	[0, 0, 140]
BUFPLL1:ENABLE_SYNC	[0, 0, 185]
Inverted	~[0]

BUFIO2_0:CKPIN	[0, 0, 323]	[0, 0, 325]
BUFIO2_1:CKPIN	[0, 0, 371]	[0, 0, 373]
BUFIO2_2:CKPIN	[0, 0, 227]	[0, 0, 229]
BUFIO2_3:CKPIN	[0, 0, 275]	[0, 0, 277]
BUFIO2_4:CKPIN	[0, 0, 131]	[0, 0, 133]
BUFIO2_5:CKPIN	[0, 0, 179]	[0, 0, 181]
BUFIO2_6:CKPIN	[0, 0, 35]	[0, 0, 37]
BUFIO2_7:CKPIN	[0, 0, 83]	[0, 0, 85]
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

INT:MUX.IMUX.REGB.GCLK0	[0, 0, 90]	[0, 0, 91]	[0, 0, 92]	[0, 0, 93]	[0, 0, 47]	[0, 0, 87]	[0, 0, 88]	[0, 0, 89]
INT:MUX.IMUX.REGB.GCLK1	[0, 0, 42]	[0, 0, 41]	[0, 0, 40]	[0, 0, 39]	[0, 0, 46]	[0, 0, 45]	[0, 0, 44]	[0, 0, 43]
NONE	0	0	0	0	0	0	0	0
GCLK0	0	1	0	1	0	0	0	1
GCLK1	0	1	0	1	0	0	1	0
GCLK2	0	1	0	1	0	1	0	0
GCLK3	0	1	0	1	1	0	0	0
GCLK8	0	1	1	0	0	0	0	1
GCLK9	0	1	1	0	0	0	1	0
GCLK10	0	1	1	0	0	1	0	0
GCLK11	0	1	1	0	1	0	0	0
GCLK4	1	0	0	1	0	0	0	1
GCLK5	1	0	0	1	0	0	1	0
GCLK6	1	0	0	1	0	1	0	0
GCLK7	1	0	0	1	1	0	0	0
GCLK12	1	0	1	0	0	0	0	1
GCLK13	1	0	1	0	0	0	1	0
GCLK14	1	0	1	0	0	1	0	0
GCLK15	1	0	1	0	1	0	0	0

BUFPLL0:DIVIDE	[0, 0, 190]	[0, 0, 189]	[0, 0, 187]	[0, 0, 138]	[0, 0, 137]	[0, 0, 136]
BUFPLL1:DIVIDE	[0, 0, 233]	[0, 0, 232]	[0, 0, 191]	[0, 0, 183]	[0, 0, 143]	[0, 0, 142]
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL0:DATA_RATE	[0, 0, 141]
BUFPLL1:DATA_RATE	[0, 0, 186]
SDR	0
DDR	1

BUFPLL_MCB:LOCK_SRC	[0, 0, 139]	[0, 0, 184]
LOCK_TO_0	0	1
LOCK_TO_1	1	0

BUFPLL0:ENABLE_BOTH_SYNC	[0, 0, 286]	[0, 0, 280]	[0, 0, 234]
BUFPLL1:ENABLE_BOTH_SYNC	[0, 0, 329]	[0, 0, 282]	[0, 0, 237]
Non-inverted	[2]	[1]	[0]

BUFPLL0:ENABLE_NONE_SYNC	[0, 0, 285]	[0, 0, 279]
BUFPLL1:ENABLE_NONE_SYNC	[0, 0, 328]	[0, 0, 281]
Non-inverted	[1]	[0]

BUFPLL0:PLLIN	[0, 0, 332]	[0, 0, 331]	[0, 0, 330]
BUFPLL1:PLLIN	[0, 0, 335]	[0, 0, 334]	[0, 0, 333]
PLLIN0	0	0	0
PLLIN1	0	0	1
PLLIN2	0	1	0
PLLIN3	0	1	1
PLLIN4	1	0	0
PLLIN5	1	0	1

BUFPLL0:LOCKED	[0, 0, 376]	[0, 0, 375]
BUFPLL1:LOCKED	[0, 0, 378]	[0, 0, 377]
LOCKED0	0	0
LOCKED1	0	1
LOCKED2	1	0

Bitstream — top tile

REG_T bittile 0
Row	Column
	0
0	BUFIO2_6:I[0]
1	BUFIO2_6:I[1]
2	BUFIO2_6:I[2]
3	BUFIO2_6:IB[0]
4	BUFIO2_6:IB[1]
5	BUFIO2_6:IB[2]
6	BUFIO2_6:FB_I[0]
7	BUFIO2_6:FB_I[1]
8	BUFIO2_6:FB_I[2]
9	BUFIO2_6:POS_EDGE[0]
10	BUFIO2_6:POS_EDGE[1]
11	BUFIO2_6:POS_EDGE[2]
12	BUFIO2_6:NEG_EDGE[0]
13	BUFIO2_6:NEG_EDGE[1]
14	-
15	BUFIO2_6:DIVIDE[0]
16	BUFIO2_6:DIVIDE[1]
17	BUFIO2_6:DIVIDE[2]
18	BUFIO2_6:R_EDGE
19	BUFIO2_6:ENABLE
20	BUFIO2_6:ENABLE_2CLK
21	-
22	-
23	-
24	-
25	-
26	-
27	~BUFIO2_6:FB_DIVIDE_BYPASS[0]
28	~BUFIO2_6:FB_DIVIDE_BYPASS[1]
29	~BUFIO2_6:FB_DIVIDE_BYPASS[2]
30	-
31	BUFIO2_6:FB_ENABLE
32	-
33	~BUFIO2_6:DIVIDE_BYPASS
34	~BUFIO2_6:FB_DIVIDE_BYPASS[3]
35	BUFIO2_6:CKPIN[1]
36	BUFIO2_6:IOCLK_ENABLE
37	BUFIO2_6:CKPIN[0]
38	BUFIO2_6:CMT_ENABLE
39	INT:MUX.IMUX.REGT.GCLK1[4]
40	INT:MUX.IMUX.REGT.GCLK1[5]
41	INT:MUX.IMUX.REGT.GCLK1[6]
42	INT:MUX.IMUX.REGT.GCLK1[7]
43	INT:MUX.IMUX.REGT.GCLK1[0]
44	INT:MUX.IMUX.REGT.GCLK1[1]
45	INT:MUX.IMUX.REGT.GCLK1[2]
46	INT:MUX.IMUX.REGT.GCLK1[3]
47	INT:MUX.IMUX.REGT.GCLK0[3]
48	BUFIO2_7:I[0]
49	BUFIO2_7:I[1]
50	BUFIO2_7:I[2]
51	BUFIO2_7:IB[0]
52	BUFIO2_7:IB[1]
53	BUFIO2_7:IB[2]
54	BUFIO2_7:FB_I[0]
55	BUFIO2_7:FB_I[1]
56	BUFIO2_7:FB_I[2]
57	BUFIO2_7:POS_EDGE[0]
58	BUFIO2_7:POS_EDGE[1]
59	BUFIO2_7:POS_EDGE[2]
60	BUFIO2_7:NEG_EDGE[0]
61	BUFIO2_7:NEG_EDGE[1]
62	-
63	BUFIO2_7:DIVIDE[0]
64	BUFIO2_7:DIVIDE[1]
65	BUFIO2_7:DIVIDE[2]
66	BUFIO2_7:R_EDGE
67	BUFIO2_7:ENABLE
68	BUFIO2_7:ENABLE_2CLK
69	-
70	-
71	-
72	-
73	-
74	-
75	~BUFIO2_7:FB_DIVIDE_BYPASS[0]
76	~BUFIO2_7:FB_DIVIDE_BYPASS[1]
77	~BUFIO2_7:FB_DIVIDE_BYPASS[2]
78	-
79	BUFIO2_7:FB_ENABLE
80	-
81	~BUFIO2_7:DIVIDE_BYPASS
82	~BUFIO2_7:FB_DIVIDE_BYPASS[3]
83	BUFIO2_7:CKPIN[1]
84	BUFIO2_7:IOCLK_ENABLE
85	BUFIO2_7:CKPIN[0]
86	BUFIO2_7:CMT_ENABLE
87	INT:MUX.IMUX.REGT.GCLK0[2]
88	INT:MUX.IMUX.REGT.GCLK0[1]
89	INT:MUX.IMUX.REGT.GCLK0[0]
90	INT:MUX.IMUX.REGT.GCLK0[7]
91	INT:MUX.IMUX.REGT.GCLK0[6]
92	INT:MUX.IMUX.REGT.GCLK0[5]
93	INT:MUX.IMUX.REGT.GCLK0[4]
94	-
95	-
96	BUFIO2_4:I[0]
97	BUFIO2_4:I[1]
98	BUFIO2_4:I[2]
99	BUFIO2_4:IB[0]
100	BUFIO2_4:IB[1]
101	BUFIO2_4:IB[2]
102	BUFIO2_4:FB_I[0]
103	BUFIO2_4:FB_I[1]
104	BUFIO2_4:FB_I[2]
105	BUFIO2_4:POS_EDGE[0]
106	BUFIO2_4:POS_EDGE[1]
107	BUFIO2_4:POS_EDGE[2]
108	BUFIO2_4:NEG_EDGE[0]
109	BUFIO2_4:NEG_EDGE[1]
110	-
111	BUFIO2_4:DIVIDE[0]
112	BUFIO2_4:DIVIDE[1]
113	BUFIO2_4:DIVIDE[2]
114	BUFIO2_4:R_EDGE
115	BUFIO2_4:ENABLE
116	BUFIO2_4:ENABLE_2CLK
117	-
118	-
119	-
120	-
121	-
122	-
123	~BUFIO2_4:FB_DIVIDE_BYPASS[0]
124	~BUFIO2_4:FB_DIVIDE_BYPASS[1]
125	~BUFIO2_4:FB_DIVIDE_BYPASS[2]
126	-
127	BUFIO2_4:FB_ENABLE
128	-
129	~BUFIO2_4:DIVIDE_BYPASS
130	~BUFIO2_4:FB_DIVIDE_BYPASS[3]
131	BUFIO2_4:CKPIN[1]
132	BUFIO2_4:IOCLK_ENABLE
133	BUFIO2_4:CKPIN[0]
134	BUFIO2_4:CMT_ENABLE
135	BUFPLL_COMMON:ENABLE
136	BUFPLL0:DIVIDE[0]
137	BUFPLL0:DIVIDE[1]
138	BUFPLL0:DIVIDE[2]
139	BUFPLL_MCB:LOCK_SRC[1]
140	~BUFPLL0:ENABLE_SYNC
141	BUFPLL0:DATA_RATE
142	BUFPLL1:DIVIDE[0]
143	BUFPLL1:DIVIDE[1]
144	BUFIO2_5:I[0]
145	BUFIO2_5:I[1]
146	BUFIO2_5:I[2]
147	BUFIO2_5:IB[0]
148	BUFIO2_5:IB[1]
149	BUFIO2_5:IB[2]
150	BUFIO2_5:FB_I[0]
151	BUFIO2_5:FB_I[1]
152	BUFIO2_5:FB_I[2]
153	BUFIO2_5:POS_EDGE[0]
154	BUFIO2_5:POS_EDGE[1]
155	BUFIO2_5:POS_EDGE[2]
156	BUFIO2_5:NEG_EDGE[0]
157	BUFIO2_5:NEG_EDGE[1]
158	-
159	BUFIO2_5:DIVIDE[0]
160	BUFIO2_5:DIVIDE[1]
161	BUFIO2_5:DIVIDE[2]
162	BUFIO2_5:R_EDGE
163	BUFIO2_5:ENABLE
164	BUFIO2_5:ENABLE_2CLK
165	-
166	-
167	-
168	-
169	-
170	-
171	~BUFIO2_5:FB_DIVIDE_BYPASS[0]
172	~BUFIO2_5:FB_DIVIDE_BYPASS[1]
173	~BUFIO2_5:FB_DIVIDE_BYPASS[2]
174	-
175	BUFIO2_5:FB_ENABLE
176	-
177	~BUFIO2_5:DIVIDE_BYPASS
178	~BUFIO2_5:FB_DIVIDE_BYPASS[3]
179	BUFIO2_5:CKPIN[1]
180	BUFIO2_5:IOCLK_ENABLE
181	BUFIO2_5:CKPIN[0]
182	BUFIO2_5:CMT_ENABLE
183	BUFPLL1:DIVIDE[2]
184	BUFPLL_MCB:LOCK_SRC[0]
185	~BUFPLL1:ENABLE_SYNC
186	BUFPLL1:DATA_RATE
187	BUFPLL0:DIVIDE[3]
188	-
189	BUFPLL0:DIVIDE[4]
190	BUFPLL0:DIVIDE[5]
191	BUFPLL1:DIVIDE[3]
192	BUFIO2_2:I[0]
193	BUFIO2_2:I[1]
194	BUFIO2_2:I[2]
195	BUFIO2_2:IB[0]
196	BUFIO2_2:IB[1]
197	BUFIO2_2:IB[2]
198	BUFIO2_2:FB_I[0]
199	BUFIO2_2:FB_I[1]
200	BUFIO2_2:FB_I[2]
201	BUFIO2_2:POS_EDGE[0]
202	BUFIO2_2:POS_EDGE[1]
203	BUFIO2_2:POS_EDGE[2]
204	BUFIO2_2:NEG_EDGE[0]
205	BUFIO2_2:NEG_EDGE[1]
206	-
207	BUFIO2_2:DIVIDE[0]
208	BUFIO2_2:DIVIDE[1]
209	BUFIO2_2:DIVIDE[2]
210	BUFIO2_2:R_EDGE
211	BUFIO2_2:ENABLE
212	BUFIO2_2:ENABLE_2CLK
213	-
214	-
215	-
216	-
217	-
218	-
219	~BUFIO2_2:FB_DIVIDE_BYPASS[0]
220	~BUFIO2_2:FB_DIVIDE_BYPASS[1]
221	~BUFIO2_2:FB_DIVIDE_BYPASS[2]
222	-
223	BUFIO2_2:FB_ENABLE
224	-
225	~BUFIO2_2:DIVIDE_BYPASS
226	~BUFIO2_2:FB_DIVIDE_BYPASS[3]
227	BUFIO2_2:CKPIN[1]
228	BUFIO2_2:IOCLK_ENABLE
229	BUFIO2_2:CKPIN[0]
230	BUFIO2_2:CMT_ENABLE
231	-
232	BUFPLL1:DIVIDE[4]
233	BUFPLL1:DIVIDE[5]
234	BUFPLL0:ENABLE_BOTH_SYNC[0]
235	-
236	-
237	BUFPLL1:ENABLE_BOTH_SYNC[0]
238	-
239	-
240	BUFIO2_3:I[0]
241	BUFIO2_3:I[1]
242	BUFIO2_3:I[2]
243	BUFIO2_3:IB[0]
244	BUFIO2_3:IB[1]
245	BUFIO2_3:IB[2]
246	BUFIO2_3:FB_I[0]
247	BUFIO2_3:FB_I[1]
248	BUFIO2_3:FB_I[2]
249	BUFIO2_3:POS_EDGE[0]
250	BUFIO2_3:POS_EDGE[1]
251	BUFIO2_3:POS_EDGE[2]
252	BUFIO2_3:NEG_EDGE[0]
253	BUFIO2_3:NEG_EDGE[1]
254	-
255	BUFIO2_3:DIVIDE[0]
256	BUFIO2_3:DIVIDE[1]
257	BUFIO2_3:DIVIDE[2]
258	BUFIO2_3:R_EDGE
259	BUFIO2_3:ENABLE
260	BUFIO2_3:ENABLE_2CLK
261	-
262	-
263	-
264	-
265	-
266	-
267	~BUFIO2_3:FB_DIVIDE_BYPASS[0]
268	~BUFIO2_3:FB_DIVIDE_BYPASS[1]
269	~BUFIO2_3:FB_DIVIDE_BYPASS[2]
270	-
271	BUFIO2_3:FB_ENABLE
272	-
273	~BUFIO2_3:DIVIDE_BYPASS
274	~BUFIO2_3:FB_DIVIDE_BYPASS[3]
275	BUFIO2_3:CKPIN[1]
276	BUFIO2_3:IOCLK_ENABLE
277	BUFIO2_3:CKPIN[0]
278	BUFIO2_3:CMT_ENABLE
279	BUFPLL0:ENABLE_NONE_SYNC[0]
280	BUFPLL0:ENABLE_BOTH_SYNC[1]
281	BUFPLL1:ENABLE_NONE_SYNC[0]
282	BUFPLL1:ENABLE_BOTH_SYNC[1]
283	-
284	-
285	BUFPLL0:ENABLE_NONE_SYNC[1]
286	BUFPLL0:ENABLE_BOTH_SYNC[2]
287	-
288	BUFIO2_0:I[0]
289	BUFIO2_0:I[1]
290	BUFIO2_0:I[2]
291	BUFIO2_0:IB[0]
292	BUFIO2_0:IB[1]
293	BUFIO2_0:IB[2]
294	BUFIO2_0:FB_I[0]
295	BUFIO2_0:FB_I[1]
296	BUFIO2_0:FB_I[2]
297	BUFIO2_0:POS_EDGE[0]
298	BUFIO2_0:POS_EDGE[1]
299	BUFIO2_0:POS_EDGE[2]
300	BUFIO2_0:NEG_EDGE[0]
301	BUFIO2_0:NEG_EDGE[1]
302	-
303	BUFIO2_0:DIVIDE[0]
304	BUFIO2_0:DIVIDE[1]
305	BUFIO2_0:DIVIDE[2]
306	BUFIO2_0:R_EDGE
307	BUFIO2_0:ENABLE
308	BUFIO2_0:ENABLE_2CLK
309	-
310	-
311	-
312	-
313	-
314	-
315	~BUFIO2_0:FB_DIVIDE_BYPASS[0]
316	~BUFIO2_0:FB_DIVIDE_BYPASS[1]
317	~BUFIO2_0:FB_DIVIDE_BYPASS[2]
318	-
319	BUFIO2_0:FB_ENABLE
320	-
321	~BUFIO2_0:DIVIDE_BYPASS
322	~BUFIO2_0:FB_DIVIDE_BYPASS[3]
323	BUFIO2_0:CKPIN[1]
324	BUFIO2_0:IOCLK_ENABLE
325	BUFIO2_0:CKPIN[0]
326	BUFIO2_0:CMT_ENABLE
327	-
328	BUFPLL1:ENABLE_NONE_SYNC[1]
329	BUFPLL1:ENABLE_BOTH_SYNC[2]
330	BUFPLL0:PLLIN[0]
331	BUFPLL0:PLLIN[1]
332	BUFPLL0:PLLIN[2]
333	BUFPLL1:PLLIN[0]
334	BUFPLL1:PLLIN[1]
335	BUFPLL1:PLLIN[2]
336	BUFIO2_1:I[0]
337	BUFIO2_1:I[1]
338	BUFIO2_1:I[2]
339	BUFIO2_1:IB[0]
340	BUFIO2_1:IB[1]
341	BUFIO2_1:IB[2]
342	BUFIO2_1:FB_I[0]
343	BUFIO2_1:FB_I[1]
344	BUFIO2_1:FB_I[2]
345	BUFIO2_1:POS_EDGE[0]
346	BUFIO2_1:POS_EDGE[1]
347	BUFIO2_1:POS_EDGE[2]
348	BUFIO2_1:NEG_EDGE[0]
349	BUFIO2_1:NEG_EDGE[1]
350	-
351	BUFIO2_1:DIVIDE[0]
352	BUFIO2_1:DIVIDE[1]
353	BUFIO2_1:DIVIDE[2]
354	BUFIO2_1:R_EDGE
355	BUFIO2_1:ENABLE
356	BUFIO2_1:ENABLE_2CLK
357	-
358	-
359	-
360	-
361	-
362	-
363	~BUFIO2_1:FB_DIVIDE_BYPASS[0]
364	~BUFIO2_1:FB_DIVIDE_BYPASS[1]
365	~BUFIO2_1:FB_DIVIDE_BYPASS[2]
366	-
367	BUFIO2_1:FB_ENABLE
368	-
369	~BUFIO2_1:DIVIDE_BYPASS
370	~BUFIO2_1:FB_DIVIDE_BYPASS[3]
371	BUFIO2_1:CKPIN[1]
372	BUFIO2_1:IOCLK_ENABLE
373	BUFIO2_1:CKPIN[0]
374	BUFIO2_1:CMT_ENABLE
375	BUFPLL0:LOCKED[0]
376	BUFPLL0:LOCKED[1]
377	BUFPLL1:LOCKED[0]
378	BUFPLL1:LOCKED[1]
379	MISC:MISR_ENABLE
380	MISC:MISR_RESET

BUFIO2_0:I	[0, 0, 290]	[0, 0, 289]	[0, 0, 288]
BUFIO2_1:I	[0, 0, 338]	[0, 0, 337]	[0, 0, 336]
BUFIO2_2:I	[0, 0, 194]	[0, 0, 193]	[0, 0, 192]
BUFIO2_3:I	[0, 0, 242]	[0, 0, 241]	[0, 0, 240]
BUFIO2_4:I	[0, 0, 98]	[0, 0, 97]	[0, 0, 96]
BUFIO2_5:I	[0, 0, 146]	[0, 0, 145]	[0, 0, 144]
BUFIO2_6:I	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
BUFIO2_7:I	[0, 0, 50]	[0, 0, 49]	[0, 0, 48]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2_0:IB	[0, 0, 293]	[0, 0, 292]	[0, 0, 291]
BUFIO2_1:IB	[0, 0, 341]	[0, 0, 340]	[0, 0, 339]
BUFIO2_2:IB	[0, 0, 197]	[0, 0, 196]	[0, 0, 195]
BUFIO2_3:IB	[0, 0, 245]	[0, 0, 244]	[0, 0, 243]
BUFIO2_4:IB	[0, 0, 101]	[0, 0, 100]	[0, 0, 99]
BUFIO2_5:IB	[0, 0, 149]	[0, 0, 148]	[0, 0, 147]
BUFIO2_6:IB	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
BUFIO2_7:IB	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2_0:FB_I	[0, 0, 296]	[0, 0, 295]	[0, 0, 294]
BUFIO2_1:FB_I	[0, 0, 344]	[0, 0, 343]	[0, 0, 342]
BUFIO2_2:FB_I	[0, 0, 200]	[0, 0, 199]	[0, 0, 198]
BUFIO2_3:FB_I	[0, 0, 248]	[0, 0, 247]	[0, 0, 246]
BUFIO2_4:FB_I	[0, 0, 104]	[0, 0, 103]	[0, 0, 102]
BUFIO2_5:FB_I	[0, 0, 152]	[0, 0, 151]	[0, 0, 150]
BUFIO2_6:FB_I	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
BUFIO2_7:FB_I	[0, 0, 56]	[0, 0, 55]	[0, 0, 54]
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2_0:POS_EDGE	[0, 0, 299]	[0, 0, 298]	[0, 0, 297]
BUFIO2_1:POS_EDGE	[0, 0, 347]	[0, 0, 346]	[0, 0, 345]
BUFIO2_2:POS_EDGE	[0, 0, 203]	[0, 0, 202]	[0, 0, 201]
BUFIO2_3:POS_EDGE	[0, 0, 251]	[0, 0, 250]	[0, 0, 249]
BUFIO2_4:POS_EDGE	[0, 0, 107]	[0, 0, 106]	[0, 0, 105]
BUFIO2_5:POS_EDGE	[0, 0, 155]	[0, 0, 154]	[0, 0, 153]
BUFIO2_6:POS_EDGE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
BUFIO2_7:POS_EDGE	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2_0:NEG_EDGE	[0, 0, 301]	[0, 0, 300]
BUFIO2_1:NEG_EDGE	[0, 0, 349]	[0, 0, 348]
BUFIO2_2:NEG_EDGE	[0, 0, 205]	[0, 0, 204]
BUFIO2_3:NEG_EDGE	[0, 0, 253]	[0, 0, 252]
BUFIO2_4:NEG_EDGE	[0, 0, 109]	[0, 0, 108]
BUFIO2_5:NEG_EDGE	[0, 0, 157]	[0, 0, 156]
BUFIO2_6:NEG_EDGE	[0, 0, 13]	[0, 0, 12]
BUFIO2_7:NEG_EDGE	[0, 0, 61]	[0, 0, 60]
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2_0:DIVIDE	[0, 0, 305]	[0, 0, 304]	[0, 0, 303]
BUFIO2_1:DIVIDE	[0, 0, 353]	[0, 0, 352]	[0, 0, 351]
BUFIO2_2:DIVIDE	[0, 0, 209]	[0, 0, 208]	[0, 0, 207]
BUFIO2_3:DIVIDE	[0, 0, 257]	[0, 0, 256]	[0, 0, 255]
BUFIO2_4:DIVIDE	[0, 0, 113]	[0, 0, 112]	[0, 0, 111]
BUFIO2_5:DIVIDE	[0, 0, 161]	[0, 0, 160]	[0, 0, 159]
BUFIO2_6:DIVIDE	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]
BUFIO2_7:DIVIDE	[0, 0, 65]	[0, 0, 64]	[0, 0, 63]
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2_0:CMT_ENABLE	[0, 0, 326]
BUFIO2_0:ENABLE	[0, 0, 307]
BUFIO2_0:ENABLE_2CLK	[0, 0, 308]
BUFIO2_0:FB_ENABLE	[0, 0, 319]
BUFIO2_0:IOCLK_ENABLE	[0, 0, 324]
BUFIO2_0:R_EDGE	[0, 0, 306]
BUFIO2_1:CMT_ENABLE	[0, 0, 374]
BUFIO2_1:ENABLE	[0, 0, 355]
BUFIO2_1:ENABLE_2CLK	[0, 0, 356]
BUFIO2_1:FB_ENABLE	[0, 0, 367]
BUFIO2_1:IOCLK_ENABLE	[0, 0, 372]
BUFIO2_1:R_EDGE	[0, 0, 354]
BUFIO2_2:CMT_ENABLE	[0, 0, 230]
BUFIO2_2:ENABLE	[0, 0, 211]
BUFIO2_2:ENABLE_2CLK	[0, 0, 212]
BUFIO2_2:FB_ENABLE	[0, 0, 223]
BUFIO2_2:IOCLK_ENABLE	[0, 0, 228]
BUFIO2_2:R_EDGE	[0, 0, 210]
BUFIO2_3:CMT_ENABLE	[0, 0, 278]
BUFIO2_3:ENABLE	[0, 0, 259]
BUFIO2_3:ENABLE_2CLK	[0, 0, 260]
BUFIO2_3:FB_ENABLE	[0, 0, 271]
BUFIO2_3:IOCLK_ENABLE	[0, 0, 276]
BUFIO2_3:R_EDGE	[0, 0, 258]
BUFIO2_4:CMT_ENABLE	[0, 0, 134]
BUFIO2_4:ENABLE	[0, 0, 115]
BUFIO2_4:ENABLE_2CLK	[0, 0, 116]
BUFIO2_4:FB_ENABLE	[0, 0, 127]
BUFIO2_4:IOCLK_ENABLE	[0, 0, 132]
BUFIO2_4:R_EDGE	[0, 0, 114]
BUFIO2_5:CMT_ENABLE	[0, 0, 182]
BUFIO2_5:ENABLE	[0, 0, 163]
BUFIO2_5:ENABLE_2CLK	[0, 0, 164]
BUFIO2_5:FB_ENABLE	[0, 0, 175]
BUFIO2_5:IOCLK_ENABLE	[0, 0, 180]
BUFIO2_5:R_EDGE	[0, 0, 162]
BUFIO2_6:CMT_ENABLE	[0, 0, 38]
BUFIO2_6:ENABLE	[0, 0, 19]
BUFIO2_6:ENABLE_2CLK	[0, 0, 20]
BUFIO2_6:FB_ENABLE	[0, 0, 31]
BUFIO2_6:IOCLK_ENABLE	[0, 0, 36]
BUFIO2_6:R_EDGE	[0, 0, 18]
BUFIO2_7:CMT_ENABLE	[0, 0, 86]
BUFIO2_7:ENABLE	[0, 0, 67]
BUFIO2_7:ENABLE_2CLK	[0, 0, 68]
BUFIO2_7:FB_ENABLE	[0, 0, 79]
BUFIO2_7:IOCLK_ENABLE	[0, 0, 84]
BUFIO2_7:R_EDGE	[0, 0, 66]
BUFPLL_COMMON:ENABLE	[0, 0, 135]
MISC:MISR_ENABLE	[0, 0, 379]
MISC:MISR_RESET	[0, 0, 380]
Non-inverted	[0]

BUFIO2_0:FB_DIVIDE_BYPASS	[0, 0, 322]	[0, 0, 317]	[0, 0, 316]	[0, 0, 315]
BUFIO2_1:FB_DIVIDE_BYPASS	[0, 0, 370]	[0, 0, 365]	[0, 0, 364]	[0, 0, 363]
BUFIO2_2:FB_DIVIDE_BYPASS	[0, 0, 226]	[0, 0, 221]	[0, 0, 220]	[0, 0, 219]
BUFIO2_3:FB_DIVIDE_BYPASS	[0, 0, 274]	[0, 0, 269]	[0, 0, 268]	[0, 0, 267]
BUFIO2_4:FB_DIVIDE_BYPASS	[0, 0, 130]	[0, 0, 125]	[0, 0, 124]	[0, 0, 123]
BUFIO2_5:FB_DIVIDE_BYPASS	[0, 0, 178]	[0, 0, 173]	[0, 0, 172]	[0, 0, 171]
BUFIO2_6:FB_DIVIDE_BYPASS	[0, 0, 34]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]
BUFIO2_7:FB_DIVIDE_BYPASS	[0, 0, 82]	[0, 0, 77]	[0, 0, 76]	[0, 0, 75]
Inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2_0:DIVIDE_BYPASS	[0, 0, 321]
BUFIO2_1:DIVIDE_BYPASS	[0, 0, 369]
BUFIO2_2:DIVIDE_BYPASS	[0, 0, 225]
BUFIO2_3:DIVIDE_BYPASS	[0, 0, 273]
BUFIO2_4:DIVIDE_BYPASS	[0, 0, 129]
BUFIO2_5:DIVIDE_BYPASS	[0, 0, 177]
BUFIO2_6:DIVIDE_BYPASS	[0, 0, 33]
BUFIO2_7:DIVIDE_BYPASS	[0, 0, 81]
BUFPLL0:ENABLE_SYNC	[0, 0, 140]
BUFPLL1:ENABLE_SYNC	[0, 0, 185]
Inverted	~[0]

BUFIO2_0:CKPIN	[0, 0, 323]	[0, 0, 325]
BUFIO2_1:CKPIN	[0, 0, 371]	[0, 0, 373]
BUFIO2_2:CKPIN	[0, 0, 227]	[0, 0, 229]
BUFIO2_3:CKPIN	[0, 0, 275]	[0, 0, 277]
BUFIO2_4:CKPIN	[0, 0, 131]	[0, 0, 133]
BUFIO2_5:CKPIN	[0, 0, 179]	[0, 0, 181]
BUFIO2_6:CKPIN	[0, 0, 35]	[0, 0, 37]
BUFIO2_7:CKPIN	[0, 0, 83]	[0, 0, 85]
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

INT:MUX.IMUX.REGT.GCLK0	[0, 0, 90]	[0, 0, 91]	[0, 0, 92]	[0, 0, 93]	[0, 0, 47]	[0, 0, 87]	[0, 0, 88]	[0, 0, 89]
INT:MUX.IMUX.REGT.GCLK1	[0, 0, 42]	[0, 0, 41]	[0, 0, 40]	[0, 0, 39]	[0, 0, 46]	[0, 0, 45]	[0, 0, 44]	[0, 0, 43]
NONE	0	0	0	0	0	0	0	0
GCLK0	0	1	0	1	0	0	0	1
GCLK1	0	1	0	1	0	0	1	0
GCLK2	0	1	0	1	0	1	0	0
GCLK3	0	1	0	1	1	0	0	0
GCLK8	0	1	1	0	0	0	0	1
GCLK9	0	1	1	0	0	0	1	0
GCLK10	0	1	1	0	0	1	0	0
GCLK11	0	1	1	0	1	0	0	0
GCLK4	1	0	0	1	0	0	0	1
GCLK5	1	0	0	1	0	0	1	0
GCLK6	1	0	0	1	0	1	0	0
GCLK7	1	0	0	1	1	0	0	0
GCLK12	1	0	1	0	0	0	0	1
GCLK13	1	0	1	0	0	0	1	0
GCLK14	1	0	1	0	0	1	0	0
GCLK15	1	0	1	0	1	0	0	0

BUFPLL0:DIVIDE	[0, 0, 190]	[0, 0, 189]	[0, 0, 187]	[0, 0, 138]	[0, 0, 137]	[0, 0, 136]
BUFPLL1:DIVIDE	[0, 0, 233]	[0, 0, 232]	[0, 0, 191]	[0, 0, 183]	[0, 0, 143]	[0, 0, 142]
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL0:DATA_RATE	[0, 0, 141]
BUFPLL1:DATA_RATE	[0, 0, 186]
SDR	0
DDR	1

BUFPLL_MCB:LOCK_SRC	[0, 0, 139]	[0, 0, 184]
LOCK_TO_0	0	1
LOCK_TO_1	1	0

BUFPLL0:ENABLE_BOTH_SYNC	[0, 0, 286]	[0, 0, 280]	[0, 0, 234]
BUFPLL1:ENABLE_BOTH_SYNC	[0, 0, 329]	[0, 0, 282]	[0, 0, 237]
Non-inverted	[2]	[1]	[0]

BUFPLL0:ENABLE_NONE_SYNC	[0, 0, 285]	[0, 0, 279]
BUFPLL1:ENABLE_NONE_SYNC	[0, 0, 328]	[0, 0, 281]
Non-inverted	[1]	[0]

BUFPLL0:PLLIN	[0, 0, 332]	[0, 0, 331]	[0, 0, 330]
BUFPLL1:PLLIN	[0, 0, 335]	[0, 0, 334]	[0, 0, 333]
PLLIN0	0	0	0
PLLIN1	0	0	1
PLLIN2	0	1	0
PLLIN3	0	1	1
PLLIN4	1	0	0
PLLIN5	1	0	1

BUFPLL0:LOCKED	[0, 0, 376]	[0, 0, 375]
BUFPLL1:LOCKED	[0, 0, 378]	[0, 0, 377]
LOCKED0	0	0
LOCKED1	0	1
LOCKED2	1	0

Bitstream — left tile

REG_L bittile 0
Row	Column
	0
0	BUFIO2_6:I[0]
1	BUFIO2_6:I[1]
2	BUFIO2_6:I[2]
3	BUFIO2_6:IB[0]
4	BUFIO2_6:IB[1]
5	BUFIO2_6:IB[2]
6	BUFIO2_6:FB_I[0]
7	BUFIO2_6:FB_I[1]
8	BUFIO2_6:FB_I[2]
9	BUFIO2_6:POS_EDGE[0]
10	BUFIO2_6:POS_EDGE[1]
11	BUFIO2_6:POS_EDGE[2]
12	BUFIO2_6:NEG_EDGE[0]
13	BUFIO2_6:NEG_EDGE[1]
14	-
15	BUFIO2_6:DIVIDE[0]
16	BUFIO2_6:DIVIDE[1]
17	BUFIO2_6:DIVIDE[2]
18	BUFIO2_6:R_EDGE
19	BUFIO2_6:ENABLE
20	BUFIO2_6:ENABLE_2CLK
21	-
22	-
23	-
24	-
25	-
26	-
27	~BUFIO2_6:FB_DIVIDE_BYPASS[0]
28	~BUFIO2_6:FB_DIVIDE_BYPASS[1]
29	~BUFIO2_6:FB_DIVIDE_BYPASS[2]
30	-
31	BUFIO2_6:FB_ENABLE
32	-
33	~BUFIO2_6:DIVIDE_BYPASS
34	~BUFIO2_6:FB_DIVIDE_BYPASS[3]
35	BUFIO2_6:CKPIN[1]
36	BUFIO2_6:IOCLK_ENABLE
37	BUFIO2_6:CKPIN[0]
38	BUFIO2_6:CMT_ENABLE
39	-
40	-
41	-
42	-
43	-
44	-
45	-
46	-
47	-
48	BUFIO2_7:I[0]
49	BUFIO2_7:I[1]
50	BUFIO2_7:I[2]
51	BUFIO2_7:IB[0]
52	BUFIO2_7:IB[1]
53	BUFIO2_7:IB[2]
54	BUFIO2_7:FB_I[0]
55	BUFIO2_7:FB_I[1]
56	BUFIO2_7:FB_I[2]
57	BUFIO2_7:POS_EDGE[0]
58	BUFIO2_7:POS_EDGE[1]
59	BUFIO2_7:POS_EDGE[2]
60	BUFIO2_7:NEG_EDGE[0]
61	BUFIO2_7:NEG_EDGE[1]
62	-
63	BUFIO2_7:DIVIDE[0]
64	BUFIO2_7:DIVIDE[1]
65	BUFIO2_7:DIVIDE[2]
66	BUFIO2_7:R_EDGE
67	BUFIO2_7:ENABLE
68	BUFIO2_7:ENABLE_2CLK
69	-
70	-
71	-
72	-
73	-
74	-
75	~BUFIO2_7:FB_DIVIDE_BYPASS[0]
76	~BUFIO2_7:FB_DIVIDE_BYPASS[1]
77	~BUFIO2_7:FB_DIVIDE_BYPASS[2]
78	-
79	BUFIO2_7:FB_ENABLE
80	-
81	~BUFIO2_7:DIVIDE_BYPASS
82	~BUFIO2_7:FB_DIVIDE_BYPASS[3]
83	BUFIO2_7:CKPIN[1]
84	BUFIO2_7:IOCLK_ENABLE
85	BUFIO2_7:CKPIN[0]
86	BUFIO2_7:CMT_ENABLE
87	-
88	-
89	-
90	-
91	-
92	-
93	-
94	-
95	-
96	BUFIO2_4:I[0]
97	BUFIO2_4:I[1]
98	BUFIO2_4:I[2]
99	BUFIO2_4:IB[0]
100	BUFIO2_4:IB[1]
101	BUFIO2_4:IB[2]
102	BUFIO2_4:FB_I[0]
103	BUFIO2_4:FB_I[1]
104	BUFIO2_4:FB_I[2]
105	BUFIO2_4:POS_EDGE[0]
106	BUFIO2_4:POS_EDGE[1]
107	BUFIO2_4:POS_EDGE[2]
108	BUFIO2_4:NEG_EDGE[0]
109	BUFIO2_4:NEG_EDGE[1]
110	-
111	BUFIO2_4:DIVIDE[0]
112	BUFIO2_4:DIVIDE[1]
113	BUFIO2_4:DIVIDE[2]
114	BUFIO2_4:R_EDGE
115	BUFIO2_4:ENABLE
116	BUFIO2_4:ENABLE_2CLK
117	-
118	-
119	-
120	-
121	-
122	-
123	~BUFIO2_4:FB_DIVIDE_BYPASS[0]
124	~BUFIO2_4:FB_DIVIDE_BYPASS[1]
125	~BUFIO2_4:FB_DIVIDE_BYPASS[2]
126	-
127	BUFIO2_4:FB_ENABLE
128	-
129	~BUFIO2_4:DIVIDE_BYPASS
130	~BUFIO2_4:FB_DIVIDE_BYPASS[3]
131	BUFIO2_4:CKPIN[1]
132	BUFIO2_4:IOCLK_ENABLE
133	BUFIO2_4:CKPIN[0]
134	BUFIO2_4:CMT_ENABLE
135	BUFPLL_COMMON:ENABLE
136	BUFPLL0:DIVIDE[0]
137	BUFPLL0:DIVIDE[1]
138	BUFPLL0:DIVIDE[2]
139	BUFPLL_MCB:LOCK_SRC[1]
140	~BUFPLL0:ENABLE_SYNC
141	BUFPLL0:DATA_RATE
142	BUFPLL1:DIVIDE[0]
143	BUFPLL1:DIVIDE[1]
144	BUFIO2_5:I[0]
145	BUFIO2_5:I[1]
146	BUFIO2_5:I[2]
147	BUFIO2_5:IB[0]
148	BUFIO2_5:IB[1]
149	BUFIO2_5:IB[2]
150	BUFIO2_5:FB_I[0]
151	BUFIO2_5:FB_I[1]
152	BUFIO2_5:FB_I[2]
153	BUFIO2_5:POS_EDGE[0]
154	BUFIO2_5:POS_EDGE[1]
155	BUFIO2_5:POS_EDGE[2]
156	BUFIO2_5:NEG_EDGE[0]
157	BUFIO2_5:NEG_EDGE[1]
158	-
159	BUFIO2_5:DIVIDE[0]
160	BUFIO2_5:DIVIDE[1]
161	BUFIO2_5:DIVIDE[2]
162	BUFIO2_5:R_EDGE
163	BUFIO2_5:ENABLE
164	BUFIO2_5:ENABLE_2CLK
165	-
166	-
167	-
168	-
169	-
170	-
171	~BUFIO2_5:FB_DIVIDE_BYPASS[0]
172	~BUFIO2_5:FB_DIVIDE_BYPASS[1]
173	~BUFIO2_5:FB_DIVIDE_BYPASS[2]
174	-
175	BUFIO2_5:FB_ENABLE
176	-
177	~BUFIO2_5:DIVIDE_BYPASS
178	~BUFIO2_5:FB_DIVIDE_BYPASS[3]
179	BUFIO2_5:CKPIN[1]
180	BUFIO2_5:IOCLK_ENABLE
181	BUFIO2_5:CKPIN[0]
182	BUFIO2_5:CMT_ENABLE
183	BUFPLL1:DIVIDE[2]
184	BUFPLL_MCB:LOCK_SRC[0]
185	~BUFPLL1:ENABLE_SYNC
186	BUFPLL1:DATA_RATE
187	BUFPLL0:DIVIDE[3]
188	-
189	BUFPLL0:DIVIDE[4]
190	BUFPLL0:DIVIDE[5]
191	BUFPLL1:DIVIDE[3]
192	BUFIO2_2:I[0]
193	BUFIO2_2:I[1]
194	BUFIO2_2:I[2]
195	BUFIO2_2:IB[0]
196	BUFIO2_2:IB[1]
197	BUFIO2_2:IB[2]
198	BUFIO2_2:FB_I[0]
199	BUFIO2_2:FB_I[1]
200	BUFIO2_2:FB_I[2]
201	BUFIO2_2:POS_EDGE[0]
202	BUFIO2_2:POS_EDGE[1]
203	BUFIO2_2:POS_EDGE[2]
204	BUFIO2_2:NEG_EDGE[0]
205	BUFIO2_2:NEG_EDGE[1]
206	-
207	BUFIO2_2:DIVIDE[0]
208	BUFIO2_2:DIVIDE[1]
209	BUFIO2_2:DIVIDE[2]
210	BUFIO2_2:R_EDGE
211	BUFIO2_2:ENABLE
212	BUFIO2_2:ENABLE_2CLK
213	-
214	-
215	-
216	-
217	-
218	-
219	~BUFIO2_2:FB_DIVIDE_BYPASS[0]
220	~BUFIO2_2:FB_DIVIDE_BYPASS[1]
221	~BUFIO2_2:FB_DIVIDE_BYPASS[2]
222	-
223	BUFIO2_2:FB_ENABLE
224	-
225	~BUFIO2_2:DIVIDE_BYPASS
226	~BUFIO2_2:FB_DIVIDE_BYPASS[3]
227	BUFIO2_2:CKPIN[1]
228	BUFIO2_2:IOCLK_ENABLE
229	BUFIO2_2:CKPIN[0]
230	BUFIO2_2:CMT_ENABLE
231	-
232	BUFPLL1:DIVIDE[4]
233	BUFPLL1:DIVIDE[5]
234	BUFPLL0:ENABLE_BOTH_SYNC[0]
235	-
236	-
237	BUFPLL1:ENABLE_BOTH_SYNC[0]
238	-
239	-
240	BUFIO2_3:I[0]
241	BUFIO2_3:I[1]
242	BUFIO2_3:I[2]
243	BUFIO2_3:IB[0]
244	BUFIO2_3:IB[1]
245	BUFIO2_3:IB[2]
246	BUFIO2_3:FB_I[0]
247	BUFIO2_3:FB_I[1]
248	BUFIO2_3:FB_I[2]
249	BUFIO2_3:POS_EDGE[0]
250	BUFIO2_3:POS_EDGE[1]
251	BUFIO2_3:POS_EDGE[2]
252	BUFIO2_3:NEG_EDGE[0]
253	BUFIO2_3:NEG_EDGE[1]
254	-
255	BUFIO2_3:DIVIDE[0]
256	BUFIO2_3:DIVIDE[1]
257	BUFIO2_3:DIVIDE[2]
258	BUFIO2_3:R_EDGE
259	BUFIO2_3:ENABLE
260	BUFIO2_3:ENABLE_2CLK
261	-
262	-
263	-
264	-
265	-
266	-
267	~BUFIO2_3:FB_DIVIDE_BYPASS[0]
268	~BUFIO2_3:FB_DIVIDE_BYPASS[1]
269	~BUFIO2_3:FB_DIVIDE_BYPASS[2]
270	-
271	BUFIO2_3:FB_ENABLE
272	-
273	~BUFIO2_3:DIVIDE_BYPASS
274	~BUFIO2_3:FB_DIVIDE_BYPASS[3]
275	BUFIO2_3:CKPIN[1]
276	BUFIO2_3:IOCLK_ENABLE
277	BUFIO2_3:CKPIN[0]
278	BUFIO2_3:CMT_ENABLE
279	BUFPLL0:ENABLE_NONE_SYNC[0]
280	BUFPLL0:ENABLE_BOTH_SYNC[1]
281	BUFPLL1:ENABLE_NONE_SYNC[0]
282	BUFPLL1:ENABLE_BOTH_SYNC[1]
283	-
284	-
285	BUFPLL0:ENABLE_NONE_SYNC[1]
286	BUFPLL0:ENABLE_BOTH_SYNC[2]
287	-
288	BUFIO2_0:I[0]
289	BUFIO2_0:I[1]
290	BUFIO2_0:I[2]
291	BUFIO2_0:IB[0]
292	BUFIO2_0:IB[1]
293	BUFIO2_0:IB[2]
294	BUFIO2_0:FB_I[0]
295	BUFIO2_0:FB_I[1]
296	BUFIO2_0:FB_I[2]
297	BUFIO2_0:POS_EDGE[0]
298	BUFIO2_0:POS_EDGE[1]
299	BUFIO2_0:POS_EDGE[2]
300	BUFIO2_0:NEG_EDGE[0]
301	BUFIO2_0:NEG_EDGE[1]
302	-
303	BUFIO2_0:DIVIDE[0]
304	BUFIO2_0:DIVIDE[1]
305	BUFIO2_0:DIVIDE[2]
306	BUFIO2_0:R_EDGE
307	BUFIO2_0:ENABLE
308	BUFIO2_0:ENABLE_2CLK
309	-
310	-
311	-
312	-
313	-
314	-
315	~BUFIO2_0:FB_DIVIDE_BYPASS[0]
316	~BUFIO2_0:FB_DIVIDE_BYPASS[1]
317	~BUFIO2_0:FB_DIVIDE_BYPASS[2]
318	-
319	BUFIO2_0:FB_ENABLE
320	-
321	~BUFIO2_0:DIVIDE_BYPASS
322	~BUFIO2_0:FB_DIVIDE_BYPASS[3]
323	BUFIO2_0:CKPIN[1]
324	BUFIO2_0:IOCLK_ENABLE
325	BUFIO2_0:CKPIN[0]
326	BUFIO2_0:CMT_ENABLE
327	-
328	BUFPLL1:ENABLE_NONE_SYNC[1]
329	BUFPLL1:ENABLE_BOTH_SYNC[2]
330	BUFPLL_COMMON:PLLIN
331	-
332	-
333	-
334	-
335	-
336	BUFIO2_1:I[0]
337	BUFIO2_1:I[1]
338	BUFIO2_1:I[2]
339	BUFIO2_1:IB[0]
340	BUFIO2_1:IB[1]
341	BUFIO2_1:IB[2]
342	BUFIO2_1:FB_I[0]
343	BUFIO2_1:FB_I[1]
344	BUFIO2_1:FB_I[2]
345	BUFIO2_1:POS_EDGE[0]
346	BUFIO2_1:POS_EDGE[1]
347	BUFIO2_1:POS_EDGE[2]
348	BUFIO2_1:NEG_EDGE[0]
349	BUFIO2_1:NEG_EDGE[1]
350	-
351	BUFIO2_1:DIVIDE[0]
352	BUFIO2_1:DIVIDE[1]
353	BUFIO2_1:DIVIDE[2]
354	BUFIO2_1:R_EDGE
355	BUFIO2_1:ENABLE
356	BUFIO2_1:ENABLE_2CLK
357	-
358	-
359	-
360	-
361	-
362	-
363	~BUFIO2_1:FB_DIVIDE_BYPASS[0]
364	~BUFIO2_1:FB_DIVIDE_BYPASS[1]
365	~BUFIO2_1:FB_DIVIDE_BYPASS[2]
366	-
367	BUFIO2_1:FB_ENABLE
368	-
369	~BUFIO2_1:DIVIDE_BYPASS
370	~BUFIO2_1:FB_DIVIDE_BYPASS[3]
371	BUFIO2_1:CKPIN[1]
372	BUFIO2_1:IOCLK_ENABLE
373	BUFIO2_1:CKPIN[0]
374	BUFIO2_1:CMT_ENABLE

BUFIO2_0:I	[0, 0, 290]	[0, 0, 289]	[0, 0, 288]
BUFIO2_2:I	[0, 0, 194]	[0, 0, 193]	[0, 0, 192]
BUFIO2_4:I	[0, 0, 98]	[0, 0, 97]	[0, 0, 96]
BUFIO2_5:I	[0, 0, 146]	[0, 0, 145]	[0, 0, 144]
BUFIO2_6:I	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
BUFIO2_7:I	[0, 0, 50]	[0, 0, 49]	[0, 0, 48]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2_0:IB	[0, 0, 293]	[0, 0, 292]	[0, 0, 291]
BUFIO2_1:IB	[0, 0, 341]	[0, 0, 340]	[0, 0, 339]
BUFIO2_2:IB	[0, 0, 197]	[0, 0, 196]	[0, 0, 195]
BUFIO2_3:IB	[0, 0, 245]	[0, 0, 244]	[0, 0, 243]
BUFIO2_4:IB	[0, 0, 101]	[0, 0, 100]	[0, 0, 99]
BUFIO2_5:IB	[0, 0, 149]	[0, 0, 148]	[0, 0, 147]
BUFIO2_6:IB	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
BUFIO2_7:IB	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2_0:FB_I	[0, 0, 296]	[0, 0, 295]	[0, 0, 294]
BUFIO2_1:FB_I	[0, 0, 344]	[0, 0, 343]	[0, 0, 342]
BUFIO2_2:FB_I	[0, 0, 200]	[0, 0, 199]	[0, 0, 198]
BUFIO2_3:FB_I	[0, 0, 248]	[0, 0, 247]	[0, 0, 246]
BUFIO2_4:FB_I	[0, 0, 104]	[0, 0, 103]	[0, 0, 102]
BUFIO2_5:FB_I	[0, 0, 152]	[0, 0, 151]	[0, 0, 150]
BUFIO2_6:FB_I	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
BUFIO2_7:FB_I	[0, 0, 56]	[0, 0, 55]	[0, 0, 54]
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2_0:POS_EDGE	[0, 0, 299]	[0, 0, 298]	[0, 0, 297]
BUFIO2_1:POS_EDGE	[0, 0, 347]	[0, 0, 346]	[0, 0, 345]
BUFIO2_2:POS_EDGE	[0, 0, 203]	[0, 0, 202]	[0, 0, 201]
BUFIO2_3:POS_EDGE	[0, 0, 251]	[0, 0, 250]	[0, 0, 249]
BUFIO2_4:POS_EDGE	[0, 0, 107]	[0, 0, 106]	[0, 0, 105]
BUFIO2_5:POS_EDGE	[0, 0, 155]	[0, 0, 154]	[0, 0, 153]
BUFIO2_6:POS_EDGE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
BUFIO2_7:POS_EDGE	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2_0:NEG_EDGE	[0, 0, 301]	[0, 0, 300]
BUFIO2_1:NEG_EDGE	[0, 0, 349]	[0, 0, 348]
BUFIO2_2:NEG_EDGE	[0, 0, 205]	[0, 0, 204]
BUFIO2_3:NEG_EDGE	[0, 0, 253]	[0, 0, 252]
BUFIO2_4:NEG_EDGE	[0, 0, 109]	[0, 0, 108]
BUFIO2_5:NEG_EDGE	[0, 0, 157]	[0, 0, 156]
BUFIO2_6:NEG_EDGE	[0, 0, 13]	[0, 0, 12]
BUFIO2_7:NEG_EDGE	[0, 0, 61]	[0, 0, 60]
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2_0:DIVIDE	[0, 0, 305]	[0, 0, 304]	[0, 0, 303]
BUFIO2_1:DIVIDE	[0, 0, 353]	[0, 0, 352]	[0, 0, 351]
BUFIO2_2:DIVIDE	[0, 0, 209]	[0, 0, 208]	[0, 0, 207]
BUFIO2_3:DIVIDE	[0, 0, 257]	[0, 0, 256]	[0, 0, 255]
BUFIO2_4:DIVIDE	[0, 0, 113]	[0, 0, 112]	[0, 0, 111]
BUFIO2_5:DIVIDE	[0, 0, 161]	[0, 0, 160]	[0, 0, 159]
BUFIO2_6:DIVIDE	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]
BUFIO2_7:DIVIDE	[0, 0, 65]	[0, 0, 64]	[0, 0, 63]
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2_0:CMT_ENABLE	[0, 0, 326]
BUFIO2_0:ENABLE	[0, 0, 307]
BUFIO2_0:ENABLE_2CLK	[0, 0, 308]
BUFIO2_0:FB_ENABLE	[0, 0, 319]
BUFIO2_0:IOCLK_ENABLE	[0, 0, 324]
BUFIO2_0:R_EDGE	[0, 0, 306]
BUFIO2_1:CMT_ENABLE	[0, 0, 374]
BUFIO2_1:ENABLE	[0, 0, 355]
BUFIO2_1:ENABLE_2CLK	[0, 0, 356]
BUFIO2_1:FB_ENABLE	[0, 0, 367]
BUFIO2_1:IOCLK_ENABLE	[0, 0, 372]
BUFIO2_1:R_EDGE	[0, 0, 354]
BUFIO2_2:CMT_ENABLE	[0, 0, 230]
BUFIO2_2:ENABLE	[0, 0, 211]
BUFIO2_2:ENABLE_2CLK	[0, 0, 212]
BUFIO2_2:FB_ENABLE	[0, 0, 223]
BUFIO2_2:IOCLK_ENABLE	[0, 0, 228]
BUFIO2_2:R_EDGE	[0, 0, 210]
BUFIO2_3:CMT_ENABLE	[0, 0, 278]
BUFIO2_3:ENABLE	[0, 0, 259]
BUFIO2_3:ENABLE_2CLK	[0, 0, 260]
BUFIO2_3:FB_ENABLE	[0, 0, 271]
BUFIO2_3:IOCLK_ENABLE	[0, 0, 276]
BUFIO2_3:R_EDGE	[0, 0, 258]
BUFIO2_4:CMT_ENABLE	[0, 0, 134]
BUFIO2_4:ENABLE	[0, 0, 115]
BUFIO2_4:ENABLE_2CLK	[0, 0, 116]
BUFIO2_4:FB_ENABLE	[0, 0, 127]
BUFIO2_4:IOCLK_ENABLE	[0, 0, 132]
BUFIO2_4:R_EDGE	[0, 0, 114]
BUFIO2_5:CMT_ENABLE	[0, 0, 182]
BUFIO2_5:ENABLE	[0, 0, 163]
BUFIO2_5:ENABLE_2CLK	[0, 0, 164]
BUFIO2_5:FB_ENABLE	[0, 0, 175]
BUFIO2_5:IOCLK_ENABLE	[0, 0, 180]
BUFIO2_5:R_EDGE	[0, 0, 162]
BUFIO2_6:CMT_ENABLE	[0, 0, 38]
BUFIO2_6:ENABLE	[0, 0, 19]
BUFIO2_6:ENABLE_2CLK	[0, 0, 20]
BUFIO2_6:FB_ENABLE	[0, 0, 31]
BUFIO2_6:IOCLK_ENABLE	[0, 0, 36]
BUFIO2_6:R_EDGE	[0, 0, 18]
BUFIO2_7:CMT_ENABLE	[0, 0, 86]
BUFIO2_7:ENABLE	[0, 0, 67]
BUFIO2_7:ENABLE_2CLK	[0, 0, 68]
BUFIO2_7:FB_ENABLE	[0, 0, 79]
BUFIO2_7:IOCLK_ENABLE	[0, 0, 84]
BUFIO2_7:R_EDGE	[0, 0, 66]
BUFPLL_COMMON:ENABLE	[0, 0, 135]
Non-inverted	[0]

BUFIO2_0:FB_DIVIDE_BYPASS	[0, 0, 322]	[0, 0, 317]	[0, 0, 316]	[0, 0, 315]
BUFIO2_1:FB_DIVIDE_BYPASS	[0, 0, 370]	[0, 0, 365]	[0, 0, 364]	[0, 0, 363]
BUFIO2_2:FB_DIVIDE_BYPASS	[0, 0, 226]	[0, 0, 221]	[0, 0, 220]	[0, 0, 219]
BUFIO2_3:FB_DIVIDE_BYPASS	[0, 0, 274]	[0, 0, 269]	[0, 0, 268]	[0, 0, 267]
BUFIO2_4:FB_DIVIDE_BYPASS	[0, 0, 130]	[0, 0, 125]	[0, 0, 124]	[0, 0, 123]
BUFIO2_5:FB_DIVIDE_BYPASS	[0, 0, 178]	[0, 0, 173]	[0, 0, 172]	[0, 0, 171]
BUFIO2_6:FB_DIVIDE_BYPASS	[0, 0, 34]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]
BUFIO2_7:FB_DIVIDE_BYPASS	[0, 0, 82]	[0, 0, 77]	[0, 0, 76]	[0, 0, 75]
Inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2_0:DIVIDE_BYPASS	[0, 0, 321]
BUFIO2_1:DIVIDE_BYPASS	[0, 0, 369]
BUFIO2_2:DIVIDE_BYPASS	[0, 0, 225]
BUFIO2_3:DIVIDE_BYPASS	[0, 0, 273]
BUFIO2_4:DIVIDE_BYPASS	[0, 0, 129]
BUFIO2_5:DIVIDE_BYPASS	[0, 0, 177]
BUFIO2_6:DIVIDE_BYPASS	[0, 0, 33]
BUFIO2_7:DIVIDE_BYPASS	[0, 0, 81]
BUFPLL0:ENABLE_SYNC	[0, 0, 140]
BUFPLL1:ENABLE_SYNC	[0, 0, 185]
Inverted	~[0]

BUFIO2_0:CKPIN	[0, 0, 323]	[0, 0, 325]
BUFIO2_1:CKPIN	[0, 0, 371]	[0, 0, 373]
BUFIO2_2:CKPIN	[0, 0, 227]	[0, 0, 229]
BUFIO2_3:CKPIN	[0, 0, 275]	[0, 0, 277]
BUFIO2_4:CKPIN	[0, 0, 131]	[0, 0, 133]
BUFIO2_5:CKPIN	[0, 0, 179]	[0, 0, 181]
BUFIO2_6:CKPIN	[0, 0, 35]	[0, 0, 37]
BUFIO2_7:CKPIN	[0, 0, 83]	[0, 0, 85]
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFPLL0:DIVIDE	[0, 0, 190]	[0, 0, 189]	[0, 0, 187]	[0, 0, 138]	[0, 0, 137]	[0, 0, 136]
BUFPLL1:DIVIDE	[0, 0, 233]	[0, 0, 232]	[0, 0, 191]	[0, 0, 183]	[0, 0, 143]	[0, 0, 142]
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL0:DATA_RATE	[0, 0, 141]
BUFPLL1:DATA_RATE	[0, 0, 186]
SDR	0
DDR	1

BUFPLL_MCB:LOCK_SRC	[0, 0, 139]	[0, 0, 184]
LOCK_TO_0	0	1
LOCK_TO_1	1	0

BUFPLL0:ENABLE_BOTH_SYNC	[0, 0, 286]	[0, 0, 280]	[0, 0, 234]
BUFPLL1:ENABLE_BOTH_SYNC	[0, 0, 329]	[0, 0, 282]	[0, 0, 237]
Non-inverted	[2]	[1]	[0]

BUFIO2_1:I	[0, 0, 338]	[0, 0, 337]	[0, 0, 336]
BUFIO2_3:I	[0, 0, 242]	[0, 0, 241]	[0, 0, 240]
CLKPIN0	0	0	0
GTPCLK	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFPLL0:ENABLE_NONE_SYNC	[0, 0, 285]	[0, 0, 279]
BUFPLL1:ENABLE_NONE_SYNC	[0, 0, 328]	[0, 0, 281]
Non-inverted	[1]	[0]

BUFPLL_COMMON:PLLIN	[0, 0, 330]
CMT	0
GCLK	1

Bitstream — right tile

REG_R bittile 0
Row	Column
	0
0	BUFIO2_6:I[0]
1	BUFIO2_6:I[1]
2	BUFIO2_6:I[2]
3	BUFIO2_6:IB[0]
4	BUFIO2_6:IB[1]
5	BUFIO2_6:IB[2]
6	BUFIO2_6:FB_I[0]
7	BUFIO2_6:FB_I[1]
8	BUFIO2_6:FB_I[2]
9	BUFIO2_6:POS_EDGE[0]
10	BUFIO2_6:POS_EDGE[1]
11	BUFIO2_6:POS_EDGE[2]
12	BUFIO2_6:NEG_EDGE[0]
13	BUFIO2_6:NEG_EDGE[1]
14	-
15	BUFIO2_6:DIVIDE[0]
16	BUFIO2_6:DIVIDE[1]
17	BUFIO2_6:DIVIDE[2]
18	BUFIO2_6:R_EDGE
19	BUFIO2_6:ENABLE
20	BUFIO2_6:ENABLE_2CLK
21	-
22	-
23	-
24	-
25	-
26	-
27	~BUFIO2_6:FB_DIVIDE_BYPASS[0]
28	~BUFIO2_6:FB_DIVIDE_BYPASS[1]
29	~BUFIO2_6:FB_DIVIDE_BYPASS[2]
30	-
31	BUFIO2_6:FB_ENABLE
32	-
33	~BUFIO2_6:DIVIDE_BYPASS
34	~BUFIO2_6:FB_DIVIDE_BYPASS[3]
35	BUFIO2_6:CKPIN[1]
36	BUFIO2_6:IOCLK_ENABLE
37	BUFIO2_6:CKPIN[0]
38	BUFIO2_6:CMT_ENABLE
39	-
40	-
41	-
42	-
43	-
44	-
45	-
46	-
47	-
48	BUFIO2_7:I[0]
49	BUFIO2_7:I[1]
50	BUFIO2_7:I[2]
51	BUFIO2_7:IB[0]
52	BUFIO2_7:IB[1]
53	BUFIO2_7:IB[2]
54	BUFIO2_7:FB_I[0]
55	BUFIO2_7:FB_I[1]
56	BUFIO2_7:FB_I[2]
57	BUFIO2_7:POS_EDGE[0]
58	BUFIO2_7:POS_EDGE[1]
59	BUFIO2_7:POS_EDGE[2]
60	BUFIO2_7:NEG_EDGE[0]
61	BUFIO2_7:NEG_EDGE[1]
62	-
63	BUFIO2_7:DIVIDE[0]
64	BUFIO2_7:DIVIDE[1]
65	BUFIO2_7:DIVIDE[2]
66	BUFIO2_7:R_EDGE
67	BUFIO2_7:ENABLE
68	BUFIO2_7:ENABLE_2CLK
69	-
70	-
71	-
72	-
73	-
74	-
75	~BUFIO2_7:FB_DIVIDE_BYPASS[0]
76	~BUFIO2_7:FB_DIVIDE_BYPASS[1]
77	~BUFIO2_7:FB_DIVIDE_BYPASS[2]
78	-
79	BUFIO2_7:FB_ENABLE
80	-
81	~BUFIO2_7:DIVIDE_BYPASS
82	~BUFIO2_7:FB_DIVIDE_BYPASS[3]
83	BUFIO2_7:CKPIN[1]
84	BUFIO2_7:IOCLK_ENABLE
85	BUFIO2_7:CKPIN[0]
86	BUFIO2_7:CMT_ENABLE
87	-
88	-
89	-
90	-
91	-
92	-
93	-
94	-
95	-
96	BUFIO2_4:I[0]
97	BUFIO2_4:I[1]
98	BUFIO2_4:I[2]
99	BUFIO2_4:IB[0]
100	BUFIO2_4:IB[1]
101	BUFIO2_4:IB[2]
102	BUFIO2_4:FB_I[0]
103	BUFIO2_4:FB_I[1]
104	BUFIO2_4:FB_I[2]
105	BUFIO2_4:POS_EDGE[0]
106	BUFIO2_4:POS_EDGE[1]
107	BUFIO2_4:POS_EDGE[2]
108	BUFIO2_4:NEG_EDGE[0]
109	BUFIO2_4:NEG_EDGE[1]
110	-
111	BUFIO2_4:DIVIDE[0]
112	BUFIO2_4:DIVIDE[1]
113	BUFIO2_4:DIVIDE[2]
114	BUFIO2_4:R_EDGE
115	BUFIO2_4:ENABLE
116	BUFIO2_4:ENABLE_2CLK
117	-
118	-
119	-
120	-
121	-
122	-
123	~BUFIO2_4:FB_DIVIDE_BYPASS[0]
124	~BUFIO2_4:FB_DIVIDE_BYPASS[1]
125	~BUFIO2_4:FB_DIVIDE_BYPASS[2]
126	-
127	BUFIO2_4:FB_ENABLE
128	-
129	~BUFIO2_4:DIVIDE_BYPASS
130	~BUFIO2_4:FB_DIVIDE_BYPASS[3]
131	BUFIO2_4:CKPIN[1]
132	BUFIO2_4:IOCLK_ENABLE
133	BUFIO2_4:CKPIN[0]
134	BUFIO2_4:CMT_ENABLE
135	BUFPLL_COMMON:ENABLE
136	BUFPLL0:DIVIDE[0]
137	BUFPLL0:DIVIDE[1]
138	BUFPLL0:DIVIDE[2]
139	BUFPLL_MCB:LOCK_SRC[1]
140	~BUFPLL0:ENABLE_SYNC
141	BUFPLL0:DATA_RATE
142	BUFPLL1:DIVIDE[0]
143	BUFPLL1:DIVIDE[1]
144	BUFIO2_5:I[0]
145	BUFIO2_5:I[1]
146	BUFIO2_5:I[2]
147	BUFIO2_5:IB[0]
148	BUFIO2_5:IB[1]
149	BUFIO2_5:IB[2]
150	BUFIO2_5:FB_I[0]
151	BUFIO2_5:FB_I[1]
152	BUFIO2_5:FB_I[2]
153	BUFIO2_5:POS_EDGE[0]
154	BUFIO2_5:POS_EDGE[1]
155	BUFIO2_5:POS_EDGE[2]
156	BUFIO2_5:NEG_EDGE[0]
157	BUFIO2_5:NEG_EDGE[1]
158	-
159	BUFIO2_5:DIVIDE[0]
160	BUFIO2_5:DIVIDE[1]
161	BUFIO2_5:DIVIDE[2]
162	BUFIO2_5:R_EDGE
163	BUFIO2_5:ENABLE
164	BUFIO2_5:ENABLE_2CLK
165	-
166	-
167	-
168	-
169	-
170	-
171	~BUFIO2_5:FB_DIVIDE_BYPASS[0]
172	~BUFIO2_5:FB_DIVIDE_BYPASS[1]
173	~BUFIO2_5:FB_DIVIDE_BYPASS[2]
174	-
175	BUFIO2_5:FB_ENABLE
176	-
177	~BUFIO2_5:DIVIDE_BYPASS
178	~BUFIO2_5:FB_DIVIDE_BYPASS[3]
179	BUFIO2_5:CKPIN[1]
180	BUFIO2_5:IOCLK_ENABLE
181	BUFIO2_5:CKPIN[0]
182	BUFIO2_5:CMT_ENABLE
183	BUFPLL1:DIVIDE[2]
184	BUFPLL_MCB:LOCK_SRC[0]
185	~BUFPLL1:ENABLE_SYNC
186	BUFPLL1:DATA_RATE
187	BUFPLL0:DIVIDE[3]
188	-
189	BUFPLL0:DIVIDE[4]
190	BUFPLL0:DIVIDE[5]
191	BUFPLL1:DIVIDE[3]
192	BUFIO2_2:I[0]
193	BUFIO2_2:I[1]
194	BUFIO2_2:I[2]
195	BUFIO2_2:IB[0]
196	BUFIO2_2:IB[1]
197	BUFIO2_2:IB[2]
198	BUFIO2_2:FB_I[0]
199	BUFIO2_2:FB_I[1]
200	BUFIO2_2:FB_I[2]
201	BUFIO2_2:POS_EDGE[0]
202	BUFIO2_2:POS_EDGE[1]
203	BUFIO2_2:POS_EDGE[2]
204	BUFIO2_2:NEG_EDGE[0]
205	BUFIO2_2:NEG_EDGE[1]
206	-
207	BUFIO2_2:DIVIDE[0]
208	BUFIO2_2:DIVIDE[1]
209	BUFIO2_2:DIVIDE[2]
210	BUFIO2_2:R_EDGE
211	BUFIO2_2:ENABLE
212	BUFIO2_2:ENABLE_2CLK
213	-
214	-
215	-
216	-
217	-
218	-
219	~BUFIO2_2:FB_DIVIDE_BYPASS[0]
220	~BUFIO2_2:FB_DIVIDE_BYPASS[1]
221	~BUFIO2_2:FB_DIVIDE_BYPASS[2]
222	-
223	BUFIO2_2:FB_ENABLE
224	-
225	~BUFIO2_2:DIVIDE_BYPASS
226	~BUFIO2_2:FB_DIVIDE_BYPASS[3]
227	BUFIO2_2:CKPIN[1]
228	BUFIO2_2:IOCLK_ENABLE
229	BUFIO2_2:CKPIN[0]
230	BUFIO2_2:CMT_ENABLE
231	-
232	BUFPLL1:DIVIDE[4]
233	BUFPLL1:DIVIDE[5]
234	BUFPLL0:ENABLE_BOTH_SYNC[0]
235	-
236	-
237	BUFPLL1:ENABLE_BOTH_SYNC[0]
238	-
239	-
240	BUFIO2_3:I[0]
241	BUFIO2_3:I[1]
242	BUFIO2_3:I[2]
243	BUFIO2_3:IB[0]
244	BUFIO2_3:IB[1]
245	BUFIO2_3:IB[2]
246	BUFIO2_3:FB_I[0]
247	BUFIO2_3:FB_I[1]
248	BUFIO2_3:FB_I[2]
249	BUFIO2_3:POS_EDGE[0]
250	BUFIO2_3:POS_EDGE[1]
251	BUFIO2_3:POS_EDGE[2]
252	BUFIO2_3:NEG_EDGE[0]
253	BUFIO2_3:NEG_EDGE[1]
254	-
255	BUFIO2_3:DIVIDE[0]
256	BUFIO2_3:DIVIDE[1]
257	BUFIO2_3:DIVIDE[2]
258	BUFIO2_3:R_EDGE
259	BUFIO2_3:ENABLE
260	BUFIO2_3:ENABLE_2CLK
261	-
262	-
263	-
264	-
265	-
266	-
267	~BUFIO2_3:FB_DIVIDE_BYPASS[0]
268	~BUFIO2_3:FB_DIVIDE_BYPASS[1]
269	~BUFIO2_3:FB_DIVIDE_BYPASS[2]
270	-
271	BUFIO2_3:FB_ENABLE
272	-
273	~BUFIO2_3:DIVIDE_BYPASS
274	~BUFIO2_3:FB_DIVIDE_BYPASS[3]
275	BUFIO2_3:CKPIN[1]
276	BUFIO2_3:IOCLK_ENABLE
277	BUFIO2_3:CKPIN[0]
278	BUFIO2_3:CMT_ENABLE
279	BUFPLL0:ENABLE_NONE_SYNC[0]
280	BUFPLL0:ENABLE_BOTH_SYNC[1]
281	BUFPLL1:ENABLE_NONE_SYNC[0]
282	BUFPLL1:ENABLE_BOTH_SYNC[1]
283	-
284	-
285	BUFPLL0:ENABLE_NONE_SYNC[1]
286	BUFPLL0:ENABLE_BOTH_SYNC[2]
287	-
288	BUFIO2_0:I[0]
289	BUFIO2_0:I[1]
290	BUFIO2_0:I[2]
291	BUFIO2_0:IB[0]
292	BUFIO2_0:IB[1]
293	BUFIO2_0:IB[2]
294	BUFIO2_0:FB_I[0]
295	BUFIO2_0:FB_I[1]
296	BUFIO2_0:FB_I[2]
297	BUFIO2_0:POS_EDGE[0]
298	BUFIO2_0:POS_EDGE[1]
299	BUFIO2_0:POS_EDGE[2]
300	BUFIO2_0:NEG_EDGE[0]
301	BUFIO2_0:NEG_EDGE[1]
302	-
303	BUFIO2_0:DIVIDE[0]
304	BUFIO2_0:DIVIDE[1]
305	BUFIO2_0:DIVIDE[2]
306	BUFIO2_0:R_EDGE
307	BUFIO2_0:ENABLE
308	BUFIO2_0:ENABLE_2CLK
309	-
310	-
311	-
312	-
313	-
314	-
315	~BUFIO2_0:FB_DIVIDE_BYPASS[0]
316	~BUFIO2_0:FB_DIVIDE_BYPASS[1]
317	~BUFIO2_0:FB_DIVIDE_BYPASS[2]
318	-
319	BUFIO2_0:FB_ENABLE
320	-
321	~BUFIO2_0:DIVIDE_BYPASS
322	~BUFIO2_0:FB_DIVIDE_BYPASS[3]
323	BUFIO2_0:CKPIN[1]
324	BUFIO2_0:IOCLK_ENABLE
325	BUFIO2_0:CKPIN[0]
326	BUFIO2_0:CMT_ENABLE
327	-
328	BUFPLL1:ENABLE_NONE_SYNC[1]
329	BUFPLL1:ENABLE_BOTH_SYNC[2]
330	BUFPLL_COMMON:PLLIN
331	-
332	-
333	-
334	-
335	-
336	BUFIO2_1:I[0]
337	BUFIO2_1:I[1]
338	BUFIO2_1:I[2]
339	BUFIO2_1:IB[0]
340	BUFIO2_1:IB[1]
341	BUFIO2_1:IB[2]
342	BUFIO2_1:FB_I[0]
343	BUFIO2_1:FB_I[1]
344	BUFIO2_1:FB_I[2]
345	BUFIO2_1:POS_EDGE[0]
346	BUFIO2_1:POS_EDGE[1]
347	BUFIO2_1:POS_EDGE[2]
348	BUFIO2_1:NEG_EDGE[0]
349	BUFIO2_1:NEG_EDGE[1]
350	-
351	BUFIO2_1:DIVIDE[0]
352	BUFIO2_1:DIVIDE[1]
353	BUFIO2_1:DIVIDE[2]
354	BUFIO2_1:R_EDGE
355	BUFIO2_1:ENABLE
356	BUFIO2_1:ENABLE_2CLK
357	-
358	-
359	-
360	-
361	-
362	-
363	~BUFIO2_1:FB_DIVIDE_BYPASS[0]
364	~BUFIO2_1:FB_DIVIDE_BYPASS[1]
365	~BUFIO2_1:FB_DIVIDE_BYPASS[2]
366	-
367	BUFIO2_1:FB_ENABLE
368	-
369	~BUFIO2_1:DIVIDE_BYPASS
370	~BUFIO2_1:FB_DIVIDE_BYPASS[3]
371	BUFIO2_1:CKPIN[1]
372	BUFIO2_1:IOCLK_ENABLE
373	BUFIO2_1:CKPIN[0]
374	BUFIO2_1:CMT_ENABLE

BUFIO2_0:I	[0, 0, 290]	[0, 0, 289]	[0, 0, 288]
BUFIO2_2:I	[0, 0, 194]	[0, 0, 193]	[0, 0, 192]
BUFIO2_4:I	[0, 0, 98]	[0, 0, 97]	[0, 0, 96]
BUFIO2_5:I	[0, 0, 146]	[0, 0, 145]	[0, 0, 144]
BUFIO2_6:I	[0, 0, 2]	[0, 0, 1]	[0, 0, 0]
BUFIO2_7:I	[0, 0, 50]	[0, 0, 49]	[0, 0, 48]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2_0:IB	[0, 0, 293]	[0, 0, 292]	[0, 0, 291]
BUFIO2_1:IB	[0, 0, 341]	[0, 0, 340]	[0, 0, 339]
BUFIO2_2:IB	[0, 0, 197]	[0, 0, 196]	[0, 0, 195]
BUFIO2_3:IB	[0, 0, 245]	[0, 0, 244]	[0, 0, 243]
BUFIO2_4:IB	[0, 0, 101]	[0, 0, 100]	[0, 0, 99]
BUFIO2_5:IB	[0, 0, 149]	[0, 0, 148]	[0, 0, 147]
BUFIO2_6:IB	[0, 0, 5]	[0, 0, 4]	[0, 0, 3]
BUFIO2_7:IB	[0, 0, 53]	[0, 0, 52]	[0, 0, 51]
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2_0:FB_I	[0, 0, 296]	[0, 0, 295]	[0, 0, 294]
BUFIO2_1:FB_I	[0, 0, 344]	[0, 0, 343]	[0, 0, 342]
BUFIO2_2:FB_I	[0, 0, 200]	[0, 0, 199]	[0, 0, 198]
BUFIO2_3:FB_I	[0, 0, 248]	[0, 0, 247]	[0, 0, 246]
BUFIO2_4:FB_I	[0, 0, 104]	[0, 0, 103]	[0, 0, 102]
BUFIO2_5:FB_I	[0, 0, 152]	[0, 0, 151]	[0, 0, 150]
BUFIO2_6:FB_I	[0, 0, 8]	[0, 0, 7]	[0, 0, 6]
BUFIO2_7:FB_I	[0, 0, 56]	[0, 0, 55]	[0, 0, 54]
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2_0:POS_EDGE	[0, 0, 299]	[0, 0, 298]	[0, 0, 297]
BUFIO2_1:POS_EDGE	[0, 0, 347]	[0, 0, 346]	[0, 0, 345]
BUFIO2_2:POS_EDGE	[0, 0, 203]	[0, 0, 202]	[0, 0, 201]
BUFIO2_3:POS_EDGE	[0, 0, 251]	[0, 0, 250]	[0, 0, 249]
BUFIO2_4:POS_EDGE	[0, 0, 107]	[0, 0, 106]	[0, 0, 105]
BUFIO2_5:POS_EDGE	[0, 0, 155]	[0, 0, 154]	[0, 0, 153]
BUFIO2_6:POS_EDGE	[0, 0, 11]	[0, 0, 10]	[0, 0, 9]
BUFIO2_7:POS_EDGE	[0, 0, 59]	[0, 0, 58]	[0, 0, 57]
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2_0:NEG_EDGE	[0, 0, 301]	[0, 0, 300]
BUFIO2_1:NEG_EDGE	[0, 0, 349]	[0, 0, 348]
BUFIO2_2:NEG_EDGE	[0, 0, 205]	[0, 0, 204]
BUFIO2_3:NEG_EDGE	[0, 0, 253]	[0, 0, 252]
BUFIO2_4:NEG_EDGE	[0, 0, 109]	[0, 0, 108]
BUFIO2_5:NEG_EDGE	[0, 0, 157]	[0, 0, 156]
BUFIO2_6:NEG_EDGE	[0, 0, 13]	[0, 0, 12]
BUFIO2_7:NEG_EDGE	[0, 0, 61]	[0, 0, 60]
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2_0:DIVIDE	[0, 0, 305]	[0, 0, 304]	[0, 0, 303]
BUFIO2_1:DIVIDE	[0, 0, 353]	[0, 0, 352]	[0, 0, 351]
BUFIO2_2:DIVIDE	[0, 0, 209]	[0, 0, 208]	[0, 0, 207]
BUFIO2_3:DIVIDE	[0, 0, 257]	[0, 0, 256]	[0, 0, 255]
BUFIO2_4:DIVIDE	[0, 0, 113]	[0, 0, 112]	[0, 0, 111]
BUFIO2_5:DIVIDE	[0, 0, 161]	[0, 0, 160]	[0, 0, 159]
BUFIO2_6:DIVIDE	[0, 0, 17]	[0, 0, 16]	[0, 0, 15]
BUFIO2_7:DIVIDE	[0, 0, 65]	[0, 0, 64]	[0, 0, 63]
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2_0:CMT_ENABLE	[0, 0, 326]
BUFIO2_0:ENABLE	[0, 0, 307]
BUFIO2_0:ENABLE_2CLK	[0, 0, 308]
BUFIO2_0:FB_ENABLE	[0, 0, 319]
BUFIO2_0:IOCLK_ENABLE	[0, 0, 324]
BUFIO2_0:R_EDGE	[0, 0, 306]
BUFIO2_1:CMT_ENABLE	[0, 0, 374]
BUFIO2_1:ENABLE	[0, 0, 355]
BUFIO2_1:ENABLE_2CLK	[0, 0, 356]
BUFIO2_1:FB_ENABLE	[0, 0, 367]
BUFIO2_1:IOCLK_ENABLE	[0, 0, 372]
BUFIO2_1:R_EDGE	[0, 0, 354]
BUFIO2_2:CMT_ENABLE	[0, 0, 230]
BUFIO2_2:ENABLE	[0, 0, 211]
BUFIO2_2:ENABLE_2CLK	[0, 0, 212]
BUFIO2_2:FB_ENABLE	[0, 0, 223]
BUFIO2_2:IOCLK_ENABLE	[0, 0, 228]
BUFIO2_2:R_EDGE	[0, 0, 210]
BUFIO2_3:CMT_ENABLE	[0, 0, 278]
BUFIO2_3:ENABLE	[0, 0, 259]
BUFIO2_3:ENABLE_2CLK	[0, 0, 260]
BUFIO2_3:FB_ENABLE	[0, 0, 271]
BUFIO2_3:IOCLK_ENABLE	[0, 0, 276]
BUFIO2_3:R_EDGE	[0, 0, 258]
BUFIO2_4:CMT_ENABLE	[0, 0, 134]
BUFIO2_4:ENABLE	[0, 0, 115]
BUFIO2_4:ENABLE_2CLK	[0, 0, 116]
BUFIO2_4:FB_ENABLE	[0, 0, 127]
BUFIO2_4:IOCLK_ENABLE	[0, 0, 132]
BUFIO2_4:R_EDGE	[0, 0, 114]
BUFIO2_5:CMT_ENABLE	[0, 0, 182]
BUFIO2_5:ENABLE	[0, 0, 163]
BUFIO2_5:ENABLE_2CLK	[0, 0, 164]
BUFIO2_5:FB_ENABLE	[0, 0, 175]
BUFIO2_5:IOCLK_ENABLE	[0, 0, 180]
BUFIO2_5:R_EDGE	[0, 0, 162]
BUFIO2_6:CMT_ENABLE	[0, 0, 38]
BUFIO2_6:ENABLE	[0, 0, 19]
BUFIO2_6:ENABLE_2CLK	[0, 0, 20]
BUFIO2_6:FB_ENABLE	[0, 0, 31]
BUFIO2_6:IOCLK_ENABLE	[0, 0, 36]
BUFIO2_6:R_EDGE	[0, 0, 18]
BUFIO2_7:CMT_ENABLE	[0, 0, 86]
BUFIO2_7:ENABLE	[0, 0, 67]
BUFIO2_7:ENABLE_2CLK	[0, 0, 68]
BUFIO2_7:FB_ENABLE	[0, 0, 79]
BUFIO2_7:IOCLK_ENABLE	[0, 0, 84]
BUFIO2_7:R_EDGE	[0, 0, 66]
BUFPLL_COMMON:ENABLE	[0, 0, 135]
Non-inverted	[0]

BUFIO2_0:FB_DIVIDE_BYPASS	[0, 0, 322]	[0, 0, 317]	[0, 0, 316]	[0, 0, 315]
BUFIO2_1:FB_DIVIDE_BYPASS	[0, 0, 370]	[0, 0, 365]	[0, 0, 364]	[0, 0, 363]
BUFIO2_2:FB_DIVIDE_BYPASS	[0, 0, 226]	[0, 0, 221]	[0, 0, 220]	[0, 0, 219]
BUFIO2_3:FB_DIVIDE_BYPASS	[0, 0, 274]	[0, 0, 269]	[0, 0, 268]	[0, 0, 267]
BUFIO2_4:FB_DIVIDE_BYPASS	[0, 0, 130]	[0, 0, 125]	[0, 0, 124]	[0, 0, 123]
BUFIO2_5:FB_DIVIDE_BYPASS	[0, 0, 178]	[0, 0, 173]	[0, 0, 172]	[0, 0, 171]
BUFIO2_6:FB_DIVIDE_BYPASS	[0, 0, 34]	[0, 0, 29]	[0, 0, 28]	[0, 0, 27]
BUFIO2_7:FB_DIVIDE_BYPASS	[0, 0, 82]	[0, 0, 77]	[0, 0, 76]	[0, 0, 75]
Inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2_0:DIVIDE_BYPASS	[0, 0, 321]
BUFIO2_1:DIVIDE_BYPASS	[0, 0, 369]
BUFIO2_2:DIVIDE_BYPASS	[0, 0, 225]
BUFIO2_3:DIVIDE_BYPASS	[0, 0, 273]
BUFIO2_4:DIVIDE_BYPASS	[0, 0, 129]
BUFIO2_5:DIVIDE_BYPASS	[0, 0, 177]
BUFIO2_6:DIVIDE_BYPASS	[0, 0, 33]
BUFIO2_7:DIVIDE_BYPASS	[0, 0, 81]
BUFPLL0:ENABLE_SYNC	[0, 0, 140]
BUFPLL1:ENABLE_SYNC	[0, 0, 185]
Inverted	~[0]

BUFIO2_0:CKPIN	[0, 0, 323]	[0, 0, 325]
BUFIO2_1:CKPIN	[0, 0, 371]	[0, 0, 373]
BUFIO2_2:CKPIN	[0, 0, 227]	[0, 0, 229]
BUFIO2_3:CKPIN	[0, 0, 275]	[0, 0, 277]
BUFIO2_4:CKPIN	[0, 0, 131]	[0, 0, 133]
BUFIO2_5:CKPIN	[0, 0, 179]	[0, 0, 181]
BUFIO2_6:CKPIN	[0, 0, 35]	[0, 0, 37]
BUFIO2_7:CKPIN	[0, 0, 83]	[0, 0, 85]
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFPLL0:DIVIDE	[0, 0, 190]	[0, 0, 189]	[0, 0, 187]	[0, 0, 138]	[0, 0, 137]	[0, 0, 136]
BUFPLL1:DIVIDE	[0, 0, 233]	[0, 0, 232]	[0, 0, 191]	[0, 0, 183]	[0, 0, 143]	[0, 0, 142]
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL0:DATA_RATE	[0, 0, 141]
BUFPLL1:DATA_RATE	[0, 0, 186]
SDR	0
DDR	1

BUFPLL_MCB:LOCK_SRC	[0, 0, 139]	[0, 0, 184]
LOCK_TO_0	0	1
LOCK_TO_1	1	0

BUFPLL0:ENABLE_BOTH_SYNC	[0, 0, 286]	[0, 0, 280]	[0, 0, 234]
BUFPLL1:ENABLE_BOTH_SYNC	[0, 0, 329]	[0, 0, 282]	[0, 0, 237]
Non-inverted	[2]	[1]	[0]

BUFIO2_1:I	[0, 0, 338]	[0, 0, 337]	[0, 0, 336]
BUFIO2_3:I	[0, 0, 242]	[0, 0, 241]	[0, 0, 240]
CLKPIN0	0	0	0
GTPCLK	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFPLL0:ENABLE_NONE_SYNC	[0, 0, 285]	[0, 0, 279]
BUFPLL1:ENABLE_NONE_SYNC	[0, 0, 328]	[0, 0, 281]
Non-inverted	[1]	[0]

BUFPLL_COMMON:PLLIN	[0, 0, 330]
CMT	0
GCLK	1

Bitstream — HCLK

HCLK bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
0	HCLK:GCLK0_O_U	HCLK:GCLK1_O_U	HCLK:GCLK2_O_U	HCLK:GCLK3_O_U	HCLK:GCLK4_O_U	HCLK:GCLK5_O_U	HCLK:GCLK6_O_U	HCLK:GCLK7_O_U	HCLK:GCLK8_O_U	HCLK:GCLK9_O_U	HCLK:GCLK10_O_U	HCLK:GCLK11_O_U	HCLK:GCLK12_O_U	HCLK:GCLK13_O_U	HCLK:GCLK14_O_U	HCLK:GCLK15_O_U
1	HCLK:GCLK0_O_D	HCLK:GCLK1_O_D	HCLK:GCLK2_O_D	HCLK:GCLK3_O_D	HCLK:GCLK4_O_D	HCLK:GCLK5_O_D	HCLK:GCLK6_O_D	HCLK:GCLK7_O_D	HCLK:GCLK8_O_D	HCLK:GCLK9_O_D	HCLK:GCLK10_O_D	HCLK:GCLK11_O_D	HCLK:GCLK12_O_D	HCLK:GCLK13_O_D	HCLK:GCLK14_O_D	HCLK:GCLK15_O_D

HCLK:GCLK0_O_D	[0, 0, 1]
HCLK:GCLK0_O_U	[0, 0, 0]
HCLK:GCLK10_O_D	[0, 10, 1]
HCLK:GCLK10_O_U	[0, 10, 0]
HCLK:GCLK11_O_D	[0, 11, 1]
HCLK:GCLK11_O_U	[0, 11, 0]
HCLK:GCLK12_O_D	[0, 12, 1]
HCLK:GCLK12_O_U	[0, 12, 0]
HCLK:GCLK13_O_D	[0, 13, 1]
HCLK:GCLK13_O_U	[0, 13, 0]
HCLK:GCLK14_O_D	[0, 14, 1]
HCLK:GCLK14_O_U	[0, 14, 0]
HCLK:GCLK15_O_D	[0, 15, 1]
HCLK:GCLK15_O_U	[0, 15, 0]
HCLK:GCLK1_O_D	[0, 1, 1]
HCLK:GCLK1_O_U	[0, 1, 0]
HCLK:GCLK2_O_D	[0, 2, 1]
HCLK:GCLK2_O_U	[0, 2, 0]
HCLK:GCLK3_O_D	[0, 3, 1]
HCLK:GCLK3_O_U	[0, 3, 0]
HCLK:GCLK4_O_D	[0, 4, 1]
HCLK:GCLK4_O_U	[0, 4, 0]
HCLK:GCLK5_O_D	[0, 5, 1]
HCLK:GCLK5_O_U	[0, 5, 0]
HCLK:GCLK6_O_D	[0, 6, 1]
HCLK:GCLK6_O_U	[0, 6, 0]
HCLK:GCLK7_O_D	[0, 7, 1]
HCLK:GCLK7_O_U	[0, 7, 0]
HCLK:GCLK8_O_D	[0, 8, 1]
HCLK:GCLK8_O_U	[0, 8, 0]
HCLK:GCLK9_O_D	[0, 9, 1]
HCLK:GCLK9_O_U	[0, 9, 0]
Non-inverted	[0]

Bitstream — HCLK_CLEXL

HCLK_CLEXL bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME21	GLUTMASK:FRAME22	GLUTMASK:FRAME23	GLUTMASK:FRAME24
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME26	GLUTMASK:FRAME27	GLUTMASK:FRAME28	GLUTMASK:FRAME29

GLUTMASK:FRAME21	[0, 16, 0]
GLUTMASK:FRAME22	[0, 17, 0]
GLUTMASK:FRAME23	[0, 18, 0]
GLUTMASK:FRAME24	[0, 19, 0]
GLUTMASK:FRAME26	[0, 16, 1]
GLUTMASK:FRAME27	[0, 17, 1]
GLUTMASK:FRAME28	[0, 18, 1]
GLUTMASK:FRAME29	[0, 19, 1]
Non-inverted	[0]

Bitstream — HCLK_CLEXM

HCLK_CLEXM bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME21	GLUTMASK:FRAME22	GLUTMASK:FRAME24	GLUTMASK:FRAME25
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME27	GLUTMASK:FRAME28	GLUTMASK:FRAME29	GLUTMASK:FRAME30

GLUTMASK:FRAME21	[0, 16, 0]
GLUTMASK:FRAME22	[0, 17, 0]
GLUTMASK:FRAME24	[0, 18, 0]
GLUTMASK:FRAME25	[0, 19, 0]
GLUTMASK:FRAME27	[0, 16, 1]
GLUTMASK:FRAME28	[0, 17, 1]
GLUTMASK:FRAME29	[0, 18, 1]
GLUTMASK:FRAME30	[0, 19, 1]
Non-inverted	[0]

Bitstream — HCLK_IOI

HCLK_IOI bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME25	-	GLUTMASK:FRAME23	GLUTMASK:FRAME24
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME21	GLUTMASK:FRAME27	GLUTMASK:FRAME28	GLUTMASK:FRAME29

GLUTMASK:FRAME21	[0, 16, 1]
GLUTMASK:FRAME23	[0, 18, 0]
GLUTMASK:FRAME24	[0, 19, 0]
GLUTMASK:FRAME25	[0, 16, 0]
GLUTMASK:FRAME27	[0, 17, 1]
GLUTMASK:FRAME28	[0, 18, 1]
GLUTMASK:FRAME29	[0, 19, 1]
Non-inverted	[0]

Bitstream — HCLK_GTP

HCLK_GTP bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GLUTMASK:FRAME25	GLUTMASK:FRAME22	GLUTMASK:FRAME23	GLUTMASK:FRAME24

GLUTMASK:FRAME22	[0, 17, 0]
GLUTMASK:FRAME23	[0, 18, 0]
GLUTMASK:FRAME24	[0, 19, 0]
GLUTMASK:FRAME25	[0, 16, 0]
Non-inverted	[0]

Bitstream — HCLK_ROW

HCLK_ROW bittile 0
Row	Column
	0	1	2
0	BUFH_R0:I[1]	-	-
1	-	BUFH_R1:I[1]	-
2	-	-	BUFH_R2:I[1]
3	BUFH_R3:I[1]	-	-
4	-	BUFH_R4:I[1]	-
5	-	-	BUFH_R5:I[1]
6	BUFH_R6:I[1]	-	-
7	-	BUFH_R7:I[1]	-
8	-	-	BUFH_R8:I[1]
9	BUFH_R9:I[1]	-	-
10	-	BUFH_R10:I[1]	-
11	-	-	BUFH_R11:I[1]
12	BUFH_R12:I[1]	-	-
13	-	BUFH_R13:I[1]	-
14	-	-	BUFH_R14:I[1]
15	BUFH_R15:I[1]	-	-
16	BUFH_R0:I[0]	-	-
17	-	BUFH_R1:I[0]	-
18	-	-	BUFH_R2:I[0]
19	BUFH_R3:I[0]	-	-
20	-	BUFH_R4:I[0]	-
21	-	-	BUFH_R5:I[0]
22	BUFH_R6:I[0]	-	-
23	-	BUFH_R7:I[0]	-
24	-	-	BUFH_R8:I[0]
25	BUFH_R9:I[0]	-	-
26	-	BUFH_R10:I[0]	-
27	-	-	BUFH_R11:I[0]
28	BUFH_R12:I[0]	-	-
29	-	BUFH_R13:I[0]	-
30	-	-	BUFH_R14:I[0]
31	BUFH_R15:I[0]	-	-
32	BUFH_L0:I[1]	-	-
33	-	BUFH_L1:I[1]	-
34	-	-	BUFH_L2:I[1]
35	BUFH_L3:I[1]	-	-
36	-	BUFH_L4:I[1]	-
37	-	-	BUFH_L5:I[1]
38	BUFH_L6:I[1]	-	-
39	-	BUFH_L7:I[1]	-
40	-	-	BUFH_L8:I[1]
41	BUFH_L9:I[1]	-	-
42	-	BUFH_L10:I[1]	-
43	-	-	BUFH_L11:I[1]
44	BUFH_L12:I[1]	-	-
45	-	BUFH_L13:I[1]	-
46	-	-	BUFH_L14:I[1]
47	BUFH_L15:I[1]	-	-
48	BUFH_L0:I[0]	-	-
49	-	BUFH_L1:I[0]	-
50	-	-	BUFH_L2:I[0]
51	BUFH_L3:I[0]	-	-
52	-	BUFH_L4:I[0]	-
53	-	-	BUFH_L5:I[0]
54	BUFH_L6:I[0]	-	-
55	-	BUFH_L7:I[0]	-
56	-	-	BUFH_L8:I[0]
57	BUFH_L9:I[0]	-	-
58	-	BUFH_L10:I[0]	-
59	-	-	BUFH_L11:I[0]
60	BUFH_L12:I[0]	-	-
61	-	BUFH_L13:I[0]	-
62	-	-	BUFH_L14:I[0]
63	BUFH_L15:I[0]	-	-

BUFH_L0:I	[0, 0, 32]	[0, 0, 48]
BUFH_L10:I	[0, 1, 42]	[0, 1, 58]
BUFH_L11:I	[0, 2, 43]	[0, 2, 59]
BUFH_L12:I	[0, 0, 44]	[0, 0, 60]
BUFH_L13:I	[0, 1, 45]	[0, 1, 61]
BUFH_L14:I	[0, 2, 46]	[0, 2, 62]
BUFH_L15:I	[0, 0, 47]	[0, 0, 63]
BUFH_L1:I	[0, 1, 33]	[0, 1, 49]
BUFH_L2:I	[0, 2, 34]	[0, 2, 50]
BUFH_L3:I	[0, 0, 35]	[0, 0, 51]
BUFH_L4:I	[0, 1, 36]	[0, 1, 52]
BUFH_L5:I	[0, 2, 37]	[0, 2, 53]
BUFH_L6:I	[0, 0, 38]	[0, 0, 54]
BUFH_L7:I	[0, 1, 39]	[0, 1, 55]
BUFH_L8:I	[0, 2, 40]	[0, 2, 56]
BUFH_L9:I	[0, 0, 41]	[0, 0, 57]
BUFH_R0:I	[0, 0, 0]	[0, 0, 16]
BUFH_R10:I	[0, 1, 10]	[0, 1, 26]
BUFH_R11:I	[0, 2, 11]	[0, 2, 27]
BUFH_R12:I	[0, 0, 12]	[0, 0, 28]
BUFH_R13:I	[0, 1, 13]	[0, 1, 29]
BUFH_R14:I	[0, 2, 14]	[0, 2, 30]
BUFH_R15:I	[0, 0, 15]	[0, 0, 31]
BUFH_R1:I	[0, 1, 1]	[0, 1, 17]
BUFH_R2:I	[0, 2, 2]	[0, 2, 18]
BUFH_R3:I	[0, 0, 3]	[0, 0, 19]
BUFH_R4:I	[0, 1, 4]	[0, 1, 20]
BUFH_R5:I	[0, 2, 5]	[0, 2, 21]
BUFH_R6:I	[0, 0, 6]	[0, 0, 22]
BUFH_R7:I	[0, 1, 7]	[0, 1, 23]
BUFH_R8:I	[0, 2, 8]	[0, 2, 24]
BUFH_R9:I	[0, 0, 9]	[0, 0, 25]
NONE	0	0
BUFG	0	1
CMT	1	0

Bitstream — CLKC

CLKC bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT0[0]	-	-	CLKC:IMUX0[3]	BUFGMUX0:CLK_SEL_TYPE	-	~BUFGMUX0:INV.S
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT0[1]	-	-	CLKC:IMUX1[3]	BUFGMUX1:CLK_SEL_TYPE	-	~BUFGMUX1:INV.S
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT0[2]	-	-	CLKC:IMUX2[3]	BUFGMUX2:CLK_SEL_TYPE	-	~BUFGMUX2:INV.S
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT1[0]	-	-	CLKC:IMUX3[3]	BUFGMUX3:CLK_SEL_TYPE	-	~BUFGMUX3:INV.S
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT1[1]	-	-	CLKC:IMUX4[3]	BUFGMUX4:CLK_SEL_TYPE	-	~BUFGMUX4:INV.S
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_CLKOUT1[2]	-	-	CLKC:IMUX5[3]	BUFGMUX5:CLK_SEL_TYPE	-	~BUFGMUX5:INV.S
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX6[3]	BUFGMUX6:CLK_SEL_TYPE	-	~BUFGMUX6:INV.S
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX7[3]	BUFGMUX7:CLK_SEL_TYPE	-	~BUFGMUX7:INV.S
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT0[0]	-	-	CLKC:IMUX8[3]	BUFGMUX8:CLK_SEL_TYPE	-	~BUFGMUX8:INV.S
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT0[1]	-	-	CLKC:IMUX9[3]	BUFGMUX9:CLK_SEL_TYPE	-	~BUFGMUX9:INV.S
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT0[2]	-	-	CLKC:IMUX10[3]	BUFGMUX10:CLK_SEL_TYPE	-	~BUFGMUX10:INV.S
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT1[0]	-	-	CLKC:IMUX11[3]	BUFGMUX11:CLK_SEL_TYPE	-	~BUFGMUX11:INV.S
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT1[1]	-	-	CLKC:IMUX12[3]	BUFGMUX12:CLK_SEL_TYPE	-	~BUFGMUX12:INV.S
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_CLKOUT1[2]	-	-	CLKC:IMUX13[3]	BUFGMUX13:CLK_SEL_TYPE	-	~BUFGMUX13:INV.S
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX14[3]	BUFGMUX14:CLK_SEL_TYPE	-	~BUFGMUX14:INV.S
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX15[3]	BUFGMUX15:CLK_SEL_TYPE	-	~BUFGMUX15:INV.S
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTU_CLKOUT0[0]	-	-	CLKC:IMUX0[2]	-	BUFGMUX0:DISABLE_ATTR	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTU_CLKOUT0[1]	-	-	CLKC:IMUX1[2]	-	BUFGMUX1:DISABLE_ATTR	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTU_CLKOUT1[0]	-	-	CLKC:IMUX2[2]	-	BUFGMUX2:DISABLE_ATTR	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTU_CLKOUT1[1]	-	-	CLKC:IMUX3[2]	-	BUFGMUX3:DISABLE_ATTR	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTD_CLKOUT1[0]	-	-	CLKC:IMUX4[2]	-	BUFGMUX4:DISABLE_ATTR	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTD_CLKOUT1[1]	-	-	CLKC:IMUX5[2]	-	BUFGMUX5:DISABLE_ATTR	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTD_CLKOUT0[0]	-	-	CLKC:IMUX6[2]	-	BUFGMUX6:DISABLE_ATTR	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTD_CLKOUT0[1]	-	-	CLKC:IMUX7[2]	-	BUFGMUX7:DISABLE_ATTR	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_LOCKED1[0]	-	-	CLKC:IMUX8[2]	-	BUFGMUX8:DISABLE_ATTR	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_LOCKED1[1]	-	-	CLKC:IMUX9[2]	-	BUFGMUX9:DISABLE_ATTR	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_LOCKED0[0]	-	-	CLKC:IMUX10[2]	-	BUFGMUX10:DISABLE_ATTR	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTL_LOCKED0[1]	-	-	CLKC:IMUX11[2]	-	BUFGMUX11:DISABLE_ATTR	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_LOCKED1[0]	-	-	CLKC:IMUX12[2]	-	BUFGMUX12:DISABLE_ATTR	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_LOCKED1[1]	-	-	CLKC:IMUX13[2]	-	BUFGMUX13:DISABLE_ATTR	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_LOCKED0[0]	-	-	CLKC:IMUX14[2]	-	BUFGMUX14:DISABLE_ATTR	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTR_LOCKED0[1]	-	-	CLKC:IMUX15[2]	-	BUFGMUX15:DISABLE_ATTR	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTD_LOCKED	-	-	CLKC:IMUX0[1]	-	-	-
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:OUTU_LOCKED	-	-	CLKC:IMUX1[1]	-	-	-
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX2[1]	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX3[1]	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX4[1]	-	-	-
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX5[1]	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX6[1]	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX7[1]	-	-	-
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX8[1]	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX9[1]	-	-	-
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX10[1]	-	-	-
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX11[1]	-	-	-
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX12[1]	-	-	-
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX13[1]	-	-	-
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX14[1]	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX15[1]	-	-	-
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX0[0]	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX1[0]	-	-	-
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX2[0]	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX3[0]	-	-	-
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX4[0]	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX5[0]	-	-	-
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX6[0]	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX7[0]	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX8[0]	-	-	-
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX9[0]	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX10[0]	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX11[0]	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX12[0]	-	-	-
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX13[0]	-	-	-
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX14[0]	-	-	-
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CLKC:IMUX15[0]	-	-	-

CLKC:OUTL_CLKOUT0	[0, 22, 2]	[0, 22, 1]	[0, 22, 0]
CLKC:OUTL_CLKOUT1	[0, 22, 5]	[0, 22, 4]	[0, 22, 3]
CLKC:OUTR_CLKOUT0	[0, 22, 10]	[0, 22, 9]	[0, 22, 8]
CLKC:OUTR_CLKOUT1	[0, 22, 13]	[0, 22, 12]	[0, 22, 11]
PLL0U_CLKOUT0	0	0	0
PLL0U_CLKOUT1	0	0	1
PLL1U_CLKOUT0	0	1	0
PLL1U_CLKOUT1	0	1	1
PLL1D_CLKOUT1	1	0	0
PLL1D_CLKOUT0	1	0	1
PLL0D_CLKOUT1	1	1	0
PLL0D_CLKOUT0	1	1	1

CLKC:OUTU_CLKOUT0	[0, 22, 17]	[0, 22, 16]
CLKC:OUTU_CLKOUT1	[0, 22, 19]	[0, 22, 18]
PLL0D_CLKOUT0	0	0
PLL0D_CLKOUT1	0	1
PLL1D_CLKOUT0	1	0
PLL1D_CLKOUT1	1	1

CLKC:OUTD_CLKOUT0	[0, 22, 23]	[0, 22, 22]
CLKC:OUTD_CLKOUT1	[0, 22, 21]	[0, 22, 20]
PLL0U_CLKOUT1	0	0
PLL0U_CLKOUT0	0	1
PLL1U_CLKOUT1	1	0
PLL1U_CLKOUT0	1	1

CLKC:OUTL_LOCKED0	[0, 22, 27]	[0, 22, 26]
CLKC:OUTL_LOCKED1	[0, 22, 25]	[0, 22, 24]
CLKC:OUTR_LOCKED0	[0, 22, 31]	[0, 22, 30]
CLKC:OUTR_LOCKED1	[0, 22, 29]	[0, 22, 28]
PLL0D_LOCKED	0	0
PLL1D_LOCKED	0	1
PLL1U_LOCKED	1	0
PLL0U_LOCKED	1	1

CLKC:OUTD_LOCKED	[0, 22, 32]
PLL1U_LOCKED	0
PLL0U_LOCKED	1

CLKC:OUTU_LOCKED	[0, 22, 33]
PLL1D_LOCKED	0
PLL0D_LOCKED	1

CLKC:IMUX0	[0, 25, 0]	[0, 25, 16]	[0, 25, 32]	[0, 25, 48]
NONE	0	0	0	0
CKPIN_H0	0	0	0	1
CKPIN_V0	0	0	1	0
CMT_D0	0	1	0	0
CMT_U0	1	0	0	0

CLKC:IMUX1	[0, 25, 1]	[0, 25, 17]	[0, 25, 33]	[0, 25, 49]
NONE	0	0	0	0
CKPIN_H1	0	0	0	1
CKPIN_V1	0	0	1	0
CMT_D1	0	1	0	0
CMT_U1	1	0	0	0

CLKC:IMUX2	[0, 25, 2]	[0, 25, 18]	[0, 25, 34]	[0, 25, 50]
NONE	0	0	0	0
CKPIN_H2	0	0	0	1
CKPIN_V2	0	0	1	0
CMT_D2	0	1	0	0
CMT_U2	1	0	0	0

CLKC:IMUX3	[0, 25, 3]	[0, 25, 19]	[0, 25, 35]	[0, 25, 51]
NONE	0	0	0	0
CKPIN_H3	0	0	0	1
CKPIN_V3	0	0	1	0
CMT_D3	0	1	0	0
CMT_U3	1	0	0	0

CLKC:IMUX4	[0, 25, 4]	[0, 25, 20]	[0, 25, 36]	[0, 25, 52]
NONE	0	0	0	0
CKPIN_H4	0	0	0	1
CKPIN_V4	0	0	1	0
CMT_D4	0	1	0	0
CMT_U4	1	0	0	0

CLKC:IMUX5	[0, 25, 5]	[0, 25, 21]	[0, 25, 37]	[0, 25, 53]
NONE	0	0	0	0
CKPIN_H5	0	0	0	1
CKPIN_V5	0	0	1	0
CMT_D5	0	1	0	0
CMT_U5	1	0	0	0

CLKC:IMUX6	[0, 25, 6]	[0, 25, 22]	[0, 25, 38]	[0, 25, 54]
NONE	0	0	0	0
CKPIN_H6	0	0	0	1
CKPIN_V6	0	0	1	0
CMT_D6	0	1	0	0
CMT_U6	1	0	0	0

CLKC:IMUX7	[0, 25, 7]	[0, 25, 23]	[0, 25, 39]	[0, 25, 55]
NONE	0	0	0	0
CKPIN_H7	0	0	0	1
CKPIN_V7	0	0	1	0
CMT_D7	0	1	0	0
CMT_U7	1	0	0	0

CLKC:IMUX8	[0, 25, 8]	[0, 25, 24]	[0, 25, 40]	[0, 25, 56]
NONE	0	0	0	0
CKPIN_H8	0	0	0	1
CKPIN_V8	0	0	1	0
CMT_D8	0	1	0	0
CMT_U8	1	0	0	0

CLKC:IMUX9	[0, 25, 9]	[0, 25, 25]	[0, 25, 41]	[0, 25, 57]
NONE	0	0	0	0
CKPIN_H9	0	0	0	1
CKPIN_V9	0	0	1	0
CMT_D9	0	1	0	0
CMT_U9	1	0	0	0

CLKC:IMUX10	[0, 25, 10]	[0, 25, 26]	[0, 25, 42]	[0, 25, 58]
NONE	0	0	0	0
CKPIN_H10	0	0	0	1
CKPIN_V10	0	0	1	0
CMT_D10	0	1	0	0
CMT_U10	1	0	0	0

CLKC:IMUX11	[0, 25, 11]	[0, 25, 27]	[0, 25, 43]	[0, 25, 59]
NONE	0	0	0	0
CKPIN_H11	0	0	0	1
CKPIN_V11	0	0	1	0
CMT_D11	0	1	0	0
CMT_U11	1	0	0	0

CLKC:IMUX12	[0, 25, 12]	[0, 25, 28]	[0, 25, 44]	[0, 25, 60]
NONE	0	0	0	0
CKPIN_H12	0	0	0	1
CKPIN_V12	0	0	1	0
CMT_D12	0	1	0	0
CMT_U12	1	0	0	0

CLKC:IMUX13	[0, 25, 13]	[0, 25, 29]	[0, 25, 45]	[0, 25, 61]
NONE	0	0	0	0
CKPIN_H13	0	0	0	1
CKPIN_V13	0	0	1	0
CMT_D13	0	1	0	0
CMT_U13	1	0	0	0

CLKC:IMUX14	[0, 25, 14]	[0, 25, 30]	[0, 25, 46]	[0, 25, 62]
NONE	0	0	0	0
CKPIN_H14	0	0	0	1
CKPIN_V14	0	0	1	0
CMT_D14	0	1	0	0
CMT_U14	1	0	0	0

CLKC:IMUX15	[0, 25, 15]	[0, 25, 31]	[0, 25, 47]	[0, 25, 63]
NONE	0	0	0	0
CKPIN_H15	0	0	0	1
CKPIN_V15	0	0	1	0
CMT_D15	0	1	0	0
CMT_U15	1	0	0	0

BUFGMUX0:CLK_SEL_TYPE	[0, 26, 0]
BUFGMUX10:CLK_SEL_TYPE	[0, 26, 10]
BUFGMUX11:CLK_SEL_TYPE	[0, 26, 11]
BUFGMUX12:CLK_SEL_TYPE	[0, 26, 12]
BUFGMUX13:CLK_SEL_TYPE	[0, 26, 13]
BUFGMUX14:CLK_SEL_TYPE	[0, 26, 14]
BUFGMUX15:CLK_SEL_TYPE	[0, 26, 15]
BUFGMUX1:CLK_SEL_TYPE	[0, 26, 1]
BUFGMUX2:CLK_SEL_TYPE	[0, 26, 2]
BUFGMUX3:CLK_SEL_TYPE	[0, 26, 3]
BUFGMUX4:CLK_SEL_TYPE	[0, 26, 4]
BUFGMUX5:CLK_SEL_TYPE	[0, 26, 5]
BUFGMUX6:CLK_SEL_TYPE	[0, 26, 6]
BUFGMUX7:CLK_SEL_TYPE	[0, 26, 7]
BUFGMUX8:CLK_SEL_TYPE	[0, 26, 8]
BUFGMUX9:CLK_SEL_TYPE	[0, 26, 9]
SYNC	0
ASYNC	1

BUFGMUX0:DISABLE_ATTR	[0, 27, 16]
BUFGMUX10:DISABLE_ATTR	[0, 27, 26]
BUFGMUX11:DISABLE_ATTR	[0, 27, 27]
BUFGMUX12:DISABLE_ATTR	[0, 27, 28]
BUFGMUX13:DISABLE_ATTR	[0, 27, 29]
BUFGMUX14:DISABLE_ATTR	[0, 27, 30]
BUFGMUX15:DISABLE_ATTR	[0, 27, 31]
BUFGMUX1:DISABLE_ATTR	[0, 27, 17]
BUFGMUX2:DISABLE_ATTR	[0, 27, 18]
BUFGMUX3:DISABLE_ATTR	[0, 27, 19]
BUFGMUX4:DISABLE_ATTR	[0, 27, 20]
BUFGMUX5:DISABLE_ATTR	[0, 27, 21]
BUFGMUX6:DISABLE_ATTR	[0, 27, 22]
BUFGMUX7:DISABLE_ATTR	[0, 27, 23]
BUFGMUX8:DISABLE_ATTR	[0, 27, 24]
BUFGMUX9:DISABLE_ATTR	[0, 27, 25]
Non-inverted	[0]

BUFGMUX0:INV.S	[0, 28, 0]
BUFGMUX10:INV.S	[0, 28, 10]
BUFGMUX11:INV.S	[0, 28, 11]
BUFGMUX12:INV.S	[0, 28, 12]
BUFGMUX13:INV.S	[0, 28, 13]
BUFGMUX14:INV.S	[0, 28, 14]
BUFGMUX15:INV.S	[0, 28, 15]
BUFGMUX1:INV.S	[0, 28, 1]
BUFGMUX2:INV.S	[0, 28, 2]
BUFGMUX3:INV.S	[0, 28, 3]
BUFGMUX4:INV.S	[0, 28, 4]
BUFGMUX5:INV.S	[0, 28, 5]
BUFGMUX6:INV.S	[0, 28, 6]
BUFGMUX7:INV.S	[0, 28, 7]
BUFGMUX8:INV.S	[0, 28, 8]
BUFGMUX9:INV.S	[0, 28, 9]
Inverted	~[0]

Bitstream — DCM_BUFPLL

DCM_BUFPLL bittile 0
Row	Column
	0	1	2	3
0	-	-	-	DCM_BUFPLL:PLL0_CLKOUT0
1	-	-	-	DCM_BUFPLL:PLL0_CLKOUT1
2	-	-	-	-
3	-	-	-	-
4	-	-	-	DCM_BUFPLL:PLL1_CLKOUT0
5	-	-	-	DCM_BUFPLL:PLL1_CLKOUT1
6	-	-	-	DCM_BUFPLL:CLKC_CLKOUT0
7	-	-	-	DCM_BUFPLL:CLKC_CLKOUT1

DCM_BUFPLL:CLKC_CLKOUT0	[0, 3, 6]
DCM_BUFPLL:CLKC_CLKOUT1	[0, 3, 7]
DCM_BUFPLL:PLL0_CLKOUT0	[0, 3, 0]
DCM_BUFPLL:PLL0_CLKOUT1	[0, 3, 1]
DCM_BUFPLL:PLL1_CLKOUT0	[0, 3, 4]
DCM_BUFPLL:PLL1_CLKOUT1	[0, 3, 5]
Non-inverted	[0]

Bitstream — PLL_BUFPLL_OUT0

PLL_BUFPLL_OUT0 bittile 0
Row	Column
	0	1	2	3
0	-	-	-	PLL_BUFPLL:PLL0_CLKOUT0_U
1	-	-	-	PLL_BUFPLL:PLL0_CLKOUT0_D
2	-	-	-	PLL_BUFPLL:PLL0_CLKOUT1_U
3	-	-	-	PLL_BUFPLL:PLL0_CLKOUT1_D
4	-	-	-	PLL_BUFPLL:CLKC_CLKOUT0
5	-	-	-	PLL_BUFPLL:CLKC_CLKOUT1
6	-	-	-	PLL_BUFPLL:PLL1_CLKOUT0
7	-	-	-	PLL_BUFPLL:PLL1_CLKOUT1

PLL_BUFPLL:CLKC_CLKOUT0	[0, 3, 4]
PLL_BUFPLL:CLKC_CLKOUT1	[0, 3, 5]
PLL_BUFPLL:PLL0_CLKOUT0_D	[0, 3, 1]
PLL_BUFPLL:PLL0_CLKOUT0_U	[0, 3, 0]
PLL_BUFPLL:PLL0_CLKOUT1_D	[0, 3, 3]
PLL_BUFPLL:PLL0_CLKOUT1_U	[0, 3, 2]
PLL_BUFPLL:PLL1_CLKOUT0	[0, 3, 6]
PLL_BUFPLL:PLL1_CLKOUT1	[0, 3, 7]
Non-inverted	[0]

Bitstream — PLL_BUFPLL_OUT1

PLL_BUFPLL_OUT1 bittile 0
Row	Column
	0	1	2	3
0	-	-	-	PLL_BUFPLL:PLL0_CLKOUT0
1	-	-	-	PLL_BUFPLL:PLL0_CLKOUT1
2	-	-	-	PLL_BUFPLL:PLL1_CLKOUT0_U
3	-	-	-	PLL_BUFPLL:PLL1_CLKOUT0_D
4	-	-	-	PLL_BUFPLL:CLKC_CLKOUT0
5	-	-	-	PLL_BUFPLL:CLKC_CLKOUT1
6	-	-	-	PLL_BUFPLL:PLL1_CLKOUT1_U
7	-	-	-	PLL_BUFPLL:PLL1_CLKOUT1_D

PLL_BUFPLL:CLKC_CLKOUT0	[0, 3, 4]
PLL_BUFPLL:CLKC_CLKOUT1	[0, 3, 5]
PLL_BUFPLL:PLL0_CLKOUT0	[0, 3, 0]
PLL_BUFPLL:PLL0_CLKOUT1	[0, 3, 1]
PLL_BUFPLL:PLL1_CLKOUT0_D	[0, 3, 3]
PLL_BUFPLL:PLL1_CLKOUT0_U	[0, 3, 2]
PLL_BUFPLL:PLL1_CLKOUT1_D	[0, 3, 7]
PLL_BUFPLL:PLL1_CLKOUT1_U	[0, 3, 6]
Non-inverted	[0]

Bitstream — PLL_BUFPLL_B

PLL_BUFPLL_B bittile 0
Row	Column
	0	1	2	3
0	-	-	-	-
1	-	-	-	PLL_BUFPLL:PLL0_CLKOUT0
2	-	-	-	-
3	-	-	-	PLL_BUFPLL:PLL0_CLKOUT1
4	-	-	-	PLL_BUFPLL:CLKC_CLKOUT0
5	-	-	-	PLL_BUFPLL:CLKC_CLKOUT1
6	-	-	-	PLL_BUFPLL:PLL1_CLKOUT0
7	-	-	-	PLL_BUFPLL:PLL1_CLKOUT1

PLL_BUFPLL:CLKC_CLKOUT0	[0, 3, 4]
PLL_BUFPLL:CLKC_CLKOUT1	[0, 3, 5]
PLL_BUFPLL:PLL0_CLKOUT0	[0, 3, 1]
PLL_BUFPLL:PLL0_CLKOUT1	[0, 3, 3]
PLL_BUFPLL:PLL1_CLKOUT0	[0, 3, 6]
PLL_BUFPLL:PLL1_CLKOUT1	[0, 3, 7]
Non-inverted	[0]

Bitstream — PLL_BUFPLL_T

PLL_BUFPLL_T bittile 0
Row	Column
	0	1	2	3
0	-	-	-	PLL_BUFPLL:PLL0_CLKOUT0
1	-	-	-	-
2	-	-	-	PLL_BUFPLL:PLL0_CLKOUT1
3	-	-	-	-
4	-	-	-	PLL_BUFPLL:CLKC_CLKOUT0
5	-	-	-	PLL_BUFPLL:CLKC_CLKOUT1
6	-	-	-	PLL_BUFPLL:PLL1_CLKOUT0
7	-	-	-	PLL_BUFPLL:PLL1_CLKOUT1

PLL_BUFPLL:CLKC_CLKOUT0	[0, 3, 4]
PLL_BUFPLL:CLKC_CLKOUT1	[0, 3, 5]
PLL_BUFPLL:PLL0_CLKOUT0	[0, 3, 0]
PLL_BUFPLL:PLL0_CLKOUT1	[0, 3, 2]
PLL_BUFPLL:PLL1_CLKOUT0	[0, 3, 6]
PLL_BUFPLL:PLL1_CLKOUT1	[0, 3, 7]
Non-inverted	[0]

Bitstream — PCILOGICSE

PCILOGICSE bittile 0
Row	Column
	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:PCI_CE_DELAY[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:PCI_CE_DELAY[1]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:PCI_CE_DELAY[2]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:PCI_CE_DELAY[3]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:PCI_CE_DELAY[4]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PCILOGICSE:ENABLE

PCILOGICSE:PCI_CE_DELAY	[0, 22, 4]	[0, 22, 3]	[0, 22, 2]	[0, 22, 1]	[0, 22, 0]
TAP31	0	0	0	0	1
TAP30	0	0	0	1	0
TAP29	0	0	0	1	1
TAP28	0	0	1	0	0
TAP27	0	0	1	0	1
TAP26	0	0	1	1	0
TAP25	0	0	1	1	1
TAP24	0	1	0	0	0
TAP23	0	1	0	0	1
TAP22	0	1	0	1	0
TAP21	0	1	0	1	1
TAP20	0	1	1	0	0
TAP19	0	1	1	0	1
TAP18	0	1	1	1	0
TAP17	0	1	1	1	1
TAP16	1	0	0	0	0
TAP15	1	0	0	0	1
TAP14	1	0	0	1	0
TAP13	1	0	0	1	1
TAP12	1	0	1	0	0
TAP11	1	0	1	0	1
TAP10	1	0	1	1	0
TAP9	1	0	1	1	1
TAP8	1	1	0	0	0
TAP7	1	1	0	0	1
TAP6	1	1	0	1	0
TAP5	1	1	0	1	1
TAP4	1	1	1	0	0
TAP3	1	1	1	0	1
TAP2	1	1	1	1	0

PCILOGICSE:ENABLE	[0, 22, 5]
Non-inverted	[0]

PCI_CE_DELAY

Device	Value
xa6slx100	TAP9
xa6slx16	TAP6
xa6slx25	TAP6
xa6slx25t	TAP6
xa6slx4	TAP6
xa6slx45	TAP6
xa6slx45t	TAP6
xa6slx75	TAP9
xa6slx75t	TAP9
xa6slx9	TAP6
xc6slx100	TAP9
xc6slx100l	TAP9
xc6slx100t	TAP9
xc6slx150	TAP9
xc6slx150l	TAP9
xc6slx150t	TAP9
xc6slx16	TAP6
xc6slx16l	TAP6
xc6slx25	TAP6
xc6slx25l	TAP6
xc6slx25t	TAP6
xc6slx4	TAP6
xc6slx45	TAP6
xc6slx45l	TAP6
xc6slx45t	TAP6
xc6slx4l	TAP6
xc6slx75	TAP9
xc6slx75l	TAP9
xc6slx75t	TAP9
xc6slx9	TAP6
xc6slx9l	TAP6
xq6slx150	TAP9
xq6slx150l	TAP9
xq6slx150t	TAP9
xq6slx75	TAP9
xq6slx75l	TAP9
xq6slx75t	TAP9