DSP

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document

Bitstream

The data for a DSP is spread across the 4 bitstream tiles belonging to the corresponding INT tiles, in order from the bottom row.

DSP bittile 0
RowColumn
DSP bittile 1
RowColumn
DSP bittile 2
RowColumn
01234567891011121314151617181920212223
0 ------------------------
1 ------------------------
2 ------------------------
3 ------------------------
4 ------------------------
5 ------------------------
6 ------------------------
7 ------------------------
8 ------------------------
9 ------------------------
10 ------------------------
11 ------------------------
12 ------------------------
13 ------------------------
14 ------------------------
15 ------------------------
16 ------------------------
17 ------------------------
18 ------------------------
19 ------------------------
20 ------------------------
21 ------------------------
22 ------------------------
23 ------------------------
24 ------------------------
25 ------------------------
26 ------------------------
27 ------------------------
28 ------------------------
29 ------------------------
30 ------------------------
31 ------------------------
32 ------------------------
33 ------------------------
34 ------------------------
35 ------------------------
36 ------------------------
37 ------------------------
38 ------------------------
39 ------------------------
40 ------------------------
41 ------------------------
42 ------------------------
43 ------------------------
44 ------------------------
45 ------------------------
46 ------------------------
47 ------------------------
48 ------------------------
49 ------------------------
50 ------------------------
51 ------------------------
52 ------------------------
53 ------------------------
54 ------------------------
55 ------------------------
56 ------------------------
57 ------------------------
58 ------------------------
59 ------------------------
60 ------------------------
61 ----------------------DSP:OPMODEREGDSP:A1REG
62 ----------------------DSP:CREGDSP:MREG
DSP bittile 3
RowColumn
01234567891011121314151617181920212223
0 ----------------------DSP:DREGDSP:RSTTYPE
1 ------------------------
2 ------------------------
3 ----------------------DSP:B_INPUTDSP:B1REG
4 ----------------------DSP:CARRYINSELDSP:A0REG
5 ----------------------DSP:PREGDSP:B0REG
6 ------------------------
7 ------------------------
8 ------------------------
9 ------------------------
10 ------------------------
11 ------------------------
12 ----------------------DSP:CARRYOUTREGDSP:INV.CEOPMODE
13 ----------------------DSP:CARRYINREGDSP:INV.CEC
14 ----------------------DSP:INV.CEDDSP:INV.RSTC
15 ----------------------DSP:INV.CECARRYINDSP:INV.CEB
16 ------------------------
17 ----------------------DSP:INV.RSTCARRYINDSP:INV.CEA
18 ----------------------DSP:INV.RSTDDSP:INV.CEM
19 ----------------------DSP:INV.RSTPDSP:INV.CLK
20 ----------------------DSP:INV.CEPDSP:INV.RSTB
21 ----------------------DSP:INV.RSTMDSP:INV.RSTA
22 ------------------------
23 ----------------------DSP:INV.RSTOPMODE-
DSP:A0REG[3, 23, 4]
DSP:A1REG[2, 23, 61]
DSP:B0REG[3, 23, 5]
DSP:B1REG[3, 23, 3]
DSP:CARRYINREG[3, 22, 13]
DSP:CARRYOUTREG[3, 22, 12]
DSP:CREG[2, 22, 62]
DSP:DREG[3, 22, 0]
DSP:MREG[2, 23, 62]
DSP:OPMODEREG[2, 22, 61]
DSP:PREG[3, 22, 5]
00
11
DSP:B_INPUT[3, 22, 3]
DIRECT0
CASCADE1
DSP:CARRYINSEL[3, 22, 4]
CARRYIN0
OPMODE51
DSP:INV.CEA[3, 23, 17]
DSP:INV.CEB[3, 23, 15]
DSP:INV.CEC[3, 23, 13]
DSP:INV.CECARRYIN[3, 22, 15]
DSP:INV.CED[3, 22, 14]
DSP:INV.CEM[3, 23, 18]
DSP:INV.CEOPMODE[3, 23, 12]
DSP:INV.CEP[3, 22, 20]
DSP:INV.CLK[3, 23, 19]
DSP:INV.RSTA[3, 23, 21]
DSP:INV.RSTB[3, 23, 20]
DSP:INV.RSTC[3, 23, 14]
DSP:INV.RSTCARRYIN[3, 22, 17]
DSP:INV.RSTD[3, 22, 18]
DSP:INV.RSTM[3, 22, 21]
DSP:INV.RSTOPMODE[3, 22, 23]
DSP:INV.RSTP[3, 22, 19]
Non-inverted[0]
DSP:RSTTYPE[3, 23, 0]
SYNC0
ASYNC1