Memory Controller Block

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document

Bitstream

MCB bittile 0
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_11[0]
1 ----------------------MCB:ARB_TIME_SLOT_11[1]
2 ----------------------MCB:ARB_TIME_SLOT_11[2]
3 ----------------------MCB:ARB_TIME_SLOT_11[3]
4 ----------------------MCB:ARB_TIME_SLOT_11[4]
5 ----------------------MCB:ARB_TIME_SLOT_11[5]
6 ----------------------MCB:ARB_TIME_SLOT_11[6]
7 ----------------------MCB:ARB_TIME_SLOT_11[7]
8 ----------------------MCB:ARB_TIME_SLOT_11[8]
9 ----------------------MCB:ARB_TIME_SLOT_11[9]
10 ----------------------MCB:ARB_TIME_SLOT_11[10]
11 ----------------------MCB:ARB_TIME_SLOT_11[11]
12 ----------------------MCB:ARB_TIME_SLOT_11[12]
13 ----------------------MCB:ARB_TIME_SLOT_11[13]
14 ----------------------MCB:ARB_TIME_SLOT_11[14]
15 ----------------------MCB:ARB_TIME_SLOT_11[15]
16 ----------------------MCB:ARB_TIME_SLOT_11[16]
17 ----------------------MCB:ARB_TIME_SLOT_11[17]
18 ----------------------MCB:CAL_CLK_DIV[0]
19 ----------------------MCB:CAL_CLK_DIV[1]
20 -----------------------
21 ----------------------MCB:CAL_CALIBRATION_MODE
22 ----------------------MCB:CAL_DELAY[0]
23 ----------------------MCB:CAL_DELAY[1]
MCB bittile 1
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_10[0]
1 ----------------------MCB:ARB_TIME_SLOT_10[1]
2 ----------------------MCB:ARB_TIME_SLOT_10[2]
3 ----------------------MCB:ARB_TIME_SLOT_10[3]
4 ----------------------MCB:ARB_TIME_SLOT_10[4]
5 ----------------------MCB:ARB_TIME_SLOT_10[5]
6 ----------------------MCB:ARB_TIME_SLOT_10[6]
7 ----------------------MCB:ARB_TIME_SLOT_10[7]
8 ----------------------MCB:ARB_TIME_SLOT_10[8]
9 ----------------------MCB:ARB_TIME_SLOT_10[9]
10 ----------------------MCB:ARB_TIME_SLOT_10[10]
11 ----------------------MCB:ARB_TIME_SLOT_10[11]
12 ----------------------MCB:ARB_TIME_SLOT_10[12]
13 ----------------------MCB:ARB_TIME_SLOT_10[13]
14 ----------------------MCB:ARB_TIME_SLOT_10[14]
15 ----------------------MCB:ARB_TIME_SLOT_10[15]
16 ----------------------MCB:ARB_TIME_SLOT_10[16]
17 ----------------------MCB:ARB_TIME_SLOT_10[17]
18 ----------------------MCB:CAL_CA[0]
19 ----------------------MCB:CAL_CA[1]
20 ----------------------MCB:CAL_CA[2]
21 ----------------------MCB:CAL_CA[3]
22 ----------------------MCB:CAL_CA[4]
23 ----------------------MCB:CAL_CA[5]
24 ----------------------MCB:CAL_CA[6]
25 ----------------------MCB:CAL_CA[7]
26 ----------------------MCB:CAL_CA[8]
27 ----------------------MCB:CAL_CA[9]
28 ----------------------MCB:CAL_CA[10]
29 ----------------------MCB:CAL_CA[11]
30 ----------------------~MCB:INV.P5CMDCLK
31 ----------------------MCB:INV.P5CMDEN
MCB bittile 2
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_9[0]
1 ----------------------MCB:ARB_TIME_SLOT_9[1]
2 ----------------------MCB:ARB_TIME_SLOT_9[2]
3 ----------------------MCB:ARB_TIME_SLOT_9[3]
4 ----------------------MCB:ARB_TIME_SLOT_9[4]
5 ----------------------MCB:ARB_TIME_SLOT_9[5]
6 ----------------------MCB:ARB_TIME_SLOT_9[6]
7 ----------------------MCB:ARB_TIME_SLOT_9[7]
8 ----------------------MCB:ARB_TIME_SLOT_9[8]
9 ----------------------MCB:ARB_TIME_SLOT_9[9]
10 ----------------------MCB:ARB_TIME_SLOT_9[10]
11 ----------------------MCB:ARB_TIME_SLOT_9[11]
12 ----------------------MCB:ARB_TIME_SLOT_9[12]
13 ----------------------MCB:ARB_TIME_SLOT_9[13]
14 ----------------------MCB:ARB_TIME_SLOT_9[14]
15 ----------------------MCB:ARB_TIME_SLOT_9[15]
16 ----------------------MCB:ARB_TIME_SLOT_9[16]
17 ----------------------MCB:ARB_TIME_SLOT_9[17]
18 ----------------------MCB:CAL_RA[0]
19 ----------------------MCB:CAL_RA[1]
20 ----------------------MCB:CAL_RA[2]
21 ----------------------MCB:CAL_RA[3]
22 ----------------------MCB:CAL_RA[4]
23 ----------------------MCB:CAL_RA[5]
24 ----------------------MCB:CAL_RA[6]
25 ----------------------MCB:CAL_RA[7]
26 ----------------------MCB:CAL_RA[8]
27 ----------------------MCB:CAL_RA[9]
28 ----------------------MCB:CAL_RA[10]
29 ----------------------MCB:CAL_RA[11]
30 ----------------------MCB:CAL_RA[12]
31 ----------------------MCB:CAL_RA[13]
32 ----------------------MCB:CAL_RA[14]
MCB bittile 3
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_8[0]
1 ----------------------MCB:ARB_TIME_SLOT_8[1]
2 ----------------------MCB:ARB_TIME_SLOT_8[2]
3 ----------------------MCB:ARB_TIME_SLOT_8[3]
4 ----------------------MCB:ARB_TIME_SLOT_8[4]
5 ----------------------MCB:ARB_TIME_SLOT_8[5]
6 ----------------------MCB:ARB_TIME_SLOT_8[6]
7 ----------------------MCB:ARB_TIME_SLOT_8[7]
8 ----------------------MCB:ARB_TIME_SLOT_8[8]
9 ----------------------MCB:ARB_TIME_SLOT_8[9]
10 ----------------------MCB:ARB_TIME_SLOT_8[10]
11 ----------------------MCB:ARB_TIME_SLOT_8[11]
12 ----------------------MCB:ARB_TIME_SLOT_8[12]
13 ----------------------MCB:ARB_TIME_SLOT_8[13]
14 ----------------------MCB:ARB_TIME_SLOT_8[14]
15 ----------------------MCB:ARB_TIME_SLOT_8[15]
16 ----------------------MCB:ARB_TIME_SLOT_8[16]
17 ----------------------MCB:ARB_TIME_SLOT_8[17]
18 -----------------------
19 ----------------------MCB:CAL_BYPASS
20 ----------------------MCB:CAL_BA[0]
21 ----------------------MCB:CAL_BA[1]
22 ----------------------MCB:CAL_BA[2]
23 ----------------------~MCB:INV.P4CMDCLK
24 ----------------------MCB:INV.P4CMDEN
MCB bittile 4
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_7[0]
1 ----------------------MCB:ARB_TIME_SLOT_7[1]
2 ----------------------MCB:ARB_TIME_SLOT_7[2]
3 ----------------------MCB:ARB_TIME_SLOT_7[3]
4 ----------------------MCB:ARB_TIME_SLOT_7[4]
5 ----------------------MCB:ARB_TIME_SLOT_7[5]
6 ----------------------MCB:ARB_TIME_SLOT_7[6]
7 ----------------------MCB:ARB_TIME_SLOT_7[7]
8 ----------------------MCB:ARB_TIME_SLOT_7[8]
9 ----------------------MCB:ARB_TIME_SLOT_7[9]
10 ----------------------MCB:ARB_TIME_SLOT_7[10]
11 ----------------------MCB:ARB_TIME_SLOT_7[11]
12 ----------------------MCB:ARB_TIME_SLOT_7[12]
13 ----------------------MCB:ARB_TIME_SLOT_7[13]
14 ----------------------MCB:ARB_TIME_SLOT_7[14]
15 ----------------------MCB:ARB_TIME_SLOT_7[15]
16 ----------------------MCB:ARB_TIME_SLOT_7[16]
17 ----------------------MCB:ARB_TIME_SLOT_7[17]
18 ----------------------MCB:EMR3[0]
19 ----------------------MCB:EMR3[1]
20 ----------------------MCB:EMR3[2]
21 ----------------------MCB:EMR3[3]
22 ----------------------MCB:EMR3[4]
23 ----------------------MCB:EMR3[5]
24 ----------------------MCB:EMR3[6]
25 ----------------------MCB:EMR3[7]
26 ----------------------MCB:EMR3[8]
27 ----------------------MCB:EMR3[9]
28 ----------------------MCB:EMR3[10]
29 ----------------------MCB:EMR3[11]
30 ----------------------MCB:EMR3[12]
31 ----------------------MCB:EMR3[13]
MCB bittile 5
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_6[0]
1 ----------------------MCB:ARB_TIME_SLOT_6[1]
2 ----------------------MCB:ARB_TIME_SLOT_6[2]
3 ----------------------MCB:ARB_TIME_SLOT_6[3]
4 ----------------------MCB:ARB_TIME_SLOT_6[4]
5 ----------------------MCB:ARB_TIME_SLOT_6[5]
6 ----------------------MCB:ARB_TIME_SLOT_6[6]
7 ----------------------MCB:ARB_TIME_SLOT_6[7]
8 ----------------------MCB:ARB_TIME_SLOT_6[8]
9 ----------------------MCB:ARB_TIME_SLOT_6[9]
10 ----------------------MCB:ARB_TIME_SLOT_6[10]
11 ----------------------MCB:ARB_TIME_SLOT_6[11]
12 ----------------------MCB:ARB_TIME_SLOT_6[12]
13 ----------------------MCB:ARB_TIME_SLOT_6[13]
14 ----------------------MCB:ARB_TIME_SLOT_6[14]
15 ----------------------MCB:ARB_TIME_SLOT_6[15]
16 ----------------------MCB:ARB_TIME_SLOT_6[16]
17 ----------------------MCB:ARB_TIME_SLOT_6[17]
18 ----------------------MCB:EMR2[0]
MCB:MEM_DDR2_3_PA_SR[0]
19 ----------------------MCB:EMR2[1]
MCB:MEM_DDR2_3_PA_SR[1]
20 ----------------------MCB:EMR2[2]
MCB:MEM_DDR2_3_PA_SR[2]
21 ----------------------MCB:EMR2[3]
MCB:MEM_DDR3_CAS_WR_LATENCY[0]
22 ----------------------MCB:EMR2[4]
MCB:MEM_DDR3_CAS_WR_LATENCY[1]
23 ----------------------MCB:EMR2[5]
24 ----------------------MCB:EMR2[6]
MCB:MEM_DDR3_AUTO_SR
25 ----------------------MCB:EMR2[7]
MCB:MEM_DDR2_3_HIGH_TEMP_SR
26 ----------------------MCB:EMR2[8]
27 ----------------------MCB:EMR2[9]
MCB:MEM_DDR3_DYN_WRT_ODT[0]
28 ----------------------MCB:EMR2[10]
MCB:MEM_DDR3_DYN_WRT_ODT[1]
29 ----------------------MCB:EMR2[11]
30 ----------------------MCB:EMR2[12]
31 ----------------------MCB:EMR2[13]
32 ----------------------~MCB:INV.P3CMDCLK
33 ----------------------MCB:INV.P3CMDEN
MCB bittile 6
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_5[0]
1 ----------------------MCB:ARB_TIME_SLOT_5[1]
2 ----------------------MCB:ARB_TIME_SLOT_5[2]
3 ----------------------MCB:ARB_TIME_SLOT_5[3]
4 ----------------------MCB:ARB_TIME_SLOT_5[4]
5 ----------------------MCB:ARB_TIME_SLOT_5[5]
6 ----------------------MCB:ARB_TIME_SLOT_5[6]
7 ----------------------MCB:ARB_TIME_SLOT_5[7]
8 ----------------------MCB:ARB_TIME_SLOT_5[8]
9 ----------------------MCB:ARB_TIME_SLOT_5[9]
10 ----------------------MCB:ARB_TIME_SLOT_5[10]
11 ----------------------MCB:ARB_TIME_SLOT_5[11]
12 ----------------------MCB:ARB_TIME_SLOT_5[12]
13 ----------------------MCB:ARB_TIME_SLOT_5[13]
14 ----------------------MCB:ARB_TIME_SLOT_5[14]
15 ----------------------MCB:ARB_TIME_SLOT_5[15]
16 ----------------------MCB:ARB_TIME_SLOT_5[16]
17 ----------------------MCB:ARB_TIME_SLOT_5[17]
18 ----------------------MCB:EMR1[0]
MCB:MEM_MOBILE_PA_SR
19 ----------------------MCB:EMR1[1]
MCB:MEM_DDR1_2_ODS
MCB:MEM_DDR3_ODS
20 ----------------------MCB:EMR1[2]
MCB:MEM_DDR2_RTT[0]
MCB:MEM_DDR3_RTT[1]
21 ----------------------MCB:EMR1[3]
MCB:MEM_DDR2_ADD_LATENCY[0]
MCB:MEM_DDR3_ADD_LATENCY[0]
MCB:MEM_MOBILE_TC_SR[0]
22 ----------------------MCB:EMR1[4]
MCB:MEM_DDR2_ADD_LATENCY[1]
MCB:MEM_DDR3_ADD_LATENCY[1]
MCB:MEM_MOBILE_TC_SR[1]
23 ----------------------MCB:EMR1[5]
MCB:MEM_DDR2_ADD_LATENCY[2]
MCB:MEM_MDDR_ODS[1]
24 ----------------------MCB:EMR1[6]
MCB:MEM_DDR2_RTT[1]
MCB:MEM_DDR3_RTT[0]
MCB:MEM_MDDR_ODS[0]
25 ----------------------MCB:EMR1[7]
MCB:MEM_MDDR_ODS[2]
26 ----------------------MCB:EMR1[8]
27 ----------------------MCB:EMR1[9]
MCB:MEM_DDR3_RTT[2]
28 ----------------------MCB:EMR1[10]
MCB:MEM_DDR2_DIFF_DQS_EN
29 ----------------------MCB:EMR1[11]
30 ----------------------MCB:EMR1[12]
31 ----------------------MCB:EMR1[13]
MCB bittile 7
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_4[0]
1 ----------------------MCB:ARB_TIME_SLOT_4[1]
2 ----------------------MCB:ARB_TIME_SLOT_4[2]
3 ----------------------MCB:ARB_TIME_SLOT_4[3]
4 ----------------------MCB:ARB_TIME_SLOT_4[4]
5 ----------------------MCB:ARB_TIME_SLOT_4[5]
6 ----------------------MCB:ARB_TIME_SLOT_4[6]
7 ----------------------MCB:ARB_TIME_SLOT_4[7]
8 ----------------------MCB:ARB_TIME_SLOT_4[8]
9 ----------------------MCB:ARB_TIME_SLOT_4[9]
10 ----------------------MCB:ARB_TIME_SLOT_4[10]
11 ----------------------MCB:ARB_TIME_SLOT_4[11]
12 ----------------------MCB:ARB_TIME_SLOT_4[12]
13 ----------------------MCB:ARB_TIME_SLOT_4[13]
14 ----------------------MCB:ARB_TIME_SLOT_4[14]
15 ----------------------MCB:ARB_TIME_SLOT_4[15]
16 ----------------------MCB:ARB_TIME_SLOT_4[16]
17 ----------------------MCB:ARB_TIME_SLOT_4[17]
18 ----------------------MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[1]
MCB:MR[0]
19 ----------------------MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[0]
MCB:MR[1]
20 ----------------------MCB:MR[2]
21 ----------------------MCB:MR[3]
22 ----------------------MCB:MEM_CAS_LATENCY[0]
MCB:MEM_DDR3_CAS_LATENCY[0]
MCB:MR[4]
23 ----------------------MCB:MEM_CAS_LATENCY[1]
MCB:MEM_DDR3_CAS_LATENCY[1]
MCB:MR[5]
24 ----------------------MCB:MEM_CAS_LATENCY[2]
MCB:MEM_DDR3_CAS_LATENCY[2]
MCB:MR[6]
25 ----------------------MCB:MR[7]
26 ----------------------MCB:MR[8]
27 ----------------------MCB:MEM_DDR2_WRT_RECOVERY[0]
MCB:MEM_DDR3_WRT_RECOVERY[0]
MCB:MR[9]
28 ----------------------MCB:MEM_DDR2_WRT_RECOVERY[1]
MCB:MEM_DDR3_WRT_RECOVERY[1]
MCB:MR[10]
29 ----------------------MCB:MEM_DDR2_WRT_RECOVERY[2]
MCB:MEM_DDR3_WRT_RECOVERY[2]
MCB:MR[11]
30 ----------------------MCB:MR[12]
31 ----------------------MCB:MR[13]
32 ----------------------~MCB:INV.P2CMDCLK
33 ----------------------MCB:INV.P2CMDEN
MCB bittile 8
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_3[0]
1 ----------------------MCB:ARB_TIME_SLOT_3[1]
2 ----------------------MCB:ARB_TIME_SLOT_3[2]
3 ----------------------MCB:ARB_TIME_SLOT_3[3]
4 ----------------------MCB:ARB_TIME_SLOT_3[4]
5 ----------------------MCB:ARB_TIME_SLOT_3[5]
6 ----------------------MCB:ARB_TIME_SLOT_3[6]
7 ----------------------MCB:ARB_TIME_SLOT_3[7]
8 ----------------------MCB:ARB_TIME_SLOT_3[8]
9 ----------------------MCB:ARB_TIME_SLOT_3[9]
10 ----------------------MCB:ARB_TIME_SLOT_3[10]
11 ----------------------MCB:ARB_TIME_SLOT_3[11]
12 ----------------------MCB:ARB_TIME_SLOT_3[12]
13 ----------------------MCB:ARB_TIME_SLOT_3[13]
14 ----------------------MCB:ARB_TIME_SLOT_3[14]
15 ----------------------MCB:ARB_TIME_SLOT_3[15]
16 ----------------------MCB:ARB_TIME_SLOT_3[16]
17 ----------------------MCB:ARB_TIME_SLOT_3[17]
18 -----------------------
19 -----------------------
20 -----------------------
21 -----------------------
22 ----------------------MCB:MEM_PLL_POL_SEL
23 ----------------------MCB:MEM_PLL_DIV_EN
24 -----------------------
25 -----------------------
26 ----------------------MCB:ARB_NUM_TIME_SLOTS
27 ----------------------MCB:MEM_BA_SIZE
28 ----------------------MCB:MEM_RA_SIZE[0]
29 ----------------------MCB:MEM_RA_SIZE[1]
30 ----------------------MCB:MEM_CA_SIZE[0]
31 ----------------------MCB:MEM_CA_SIZE[1]
32 ----------------------MCB:MEM_ADDR_ORDER
MCB bittile 9
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_2[0]
1 ----------------------MCB:ARB_TIME_SLOT_2[1]
2 ----------------------MCB:ARB_TIME_SLOT_2[2]
3 ----------------------MCB:ARB_TIME_SLOT_2[3]
4 ----------------------MCB:ARB_TIME_SLOT_2[4]
5 ----------------------MCB:ARB_TIME_SLOT_2[5]
6 ----------------------MCB:ARB_TIME_SLOT_2[6]
7 ----------------------MCB:ARB_TIME_SLOT_2[7]
8 ----------------------MCB:ARB_TIME_SLOT_2[8]
9 ----------------------MCB:ARB_TIME_SLOT_2[9]
10 ----------------------MCB:ARB_TIME_SLOT_2[10]
11 ----------------------MCB:ARB_TIME_SLOT_2[11]
12 ----------------------MCB:ARB_TIME_SLOT_2[12]
13 ----------------------MCB:ARB_TIME_SLOT_2[13]
14 ----------------------MCB:ARB_TIME_SLOT_2[14]
15 ----------------------MCB:ARB_TIME_SLOT_2[15]
16 ----------------------MCB:ARB_TIME_SLOT_2[16]
17 ----------------------MCB:ARB_TIME_SLOT_2[17]
18 ----------------------MCB:MEM_RFC_VAL[0]
19 ----------------------MCB:MEM_RFC_VAL[1]
20 ----------------------MCB:MEM_RFC_VAL[2]
21 ----------------------MCB:MEM_RFC_VAL[3]
22 ----------------------MCB:MEM_RFC_VAL[4]
23 ----------------------MCB:MEM_RFC_VAL[5]
24 ----------------------MCB:MEM_RFC_VAL[6]
25 ----------------------MCB:MEM_RFC_VAL[7]
26 ----------------------MCB:MEM_RP_VAL[0]
27 ----------------------MCB:MEM_RP_VAL[1]
28 ----------------------MCB:MEM_RP_VAL[2]
29 ----------------------MCB:MEM_RP_VAL[3]
30 ----------------------MCB:MEM_WR_VAL[0]
31 ----------------------MCB:MEM_WR_VAL[1]
32 ----------------------MCB:MEM_WR_VAL[2]
33 ----------------------MCB:MEM_RTP_VAL[0]
34 ----------------------MCB:MEM_RTP_VAL[1]
35 ----------------------MCB:MEM_RTP_VAL[2]
36 ----------------------MCB:MEM_WTR_VAL[0]
37 ----------------------MCB:MEM_WTR_VAL[1]
38 ----------------------MCB:MEM_WTR_VAL[2]
39 ----------------------~MCB:INV.P1CMDCLK
40 ----------------------MCB:INV.P1CMDEN
MCB bittile 10
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_1[0]
1 ----------------------MCB:ARB_TIME_SLOT_1[1]
2 ----------------------MCB:ARB_TIME_SLOT_1[2]
3 ----------------------MCB:ARB_TIME_SLOT_1[3]
4 ----------------------MCB:ARB_TIME_SLOT_1[4]
5 ----------------------MCB:ARB_TIME_SLOT_1[5]
6 ----------------------MCB:ARB_TIME_SLOT_1[6]
7 ----------------------MCB:ARB_TIME_SLOT_1[7]
8 ----------------------MCB:ARB_TIME_SLOT_1[8]
9 ----------------------MCB:ARB_TIME_SLOT_1[9]
10 ----------------------MCB:ARB_TIME_SLOT_1[10]
11 ----------------------MCB:ARB_TIME_SLOT_1[11]
12 ----------------------MCB:ARB_TIME_SLOT_1[12]
13 ----------------------MCB:ARB_TIME_SLOT_1[13]
14 ----------------------MCB:ARB_TIME_SLOT_1[14]
15 ----------------------MCB:ARB_TIME_SLOT_1[15]
16 ----------------------MCB:ARB_TIME_SLOT_1[16]
17 ----------------------MCB:ARB_TIME_SLOT_1[17]
18 ----------------------MCB:MEM_RAS_VAL[0]
19 ----------------------MCB:MEM_RAS_VAL[1]
20 ----------------------MCB:MEM_RAS_VAL[2]
21 ----------------------MCB:MEM_RAS_VAL[3]
22 ----------------------MCB:MEM_RAS_VAL[4]
23 ----------------------MCB:MEM_RCD_VAL[0]
24 ----------------------MCB:MEM_RCD_VAL[1]
25 ----------------------MCB:MEM_RCD_VAL[2]
26 -----------------------
27 ----------------------MCB:MEM_REFI_VAL[0]
28 ----------------------MCB:MEM_REFI_VAL[1]
29 ----------------------MCB:MEM_REFI_VAL[2]
30 ----------------------MCB:MEM_REFI_VAL[3]
31 ----------------------MCB:MEM_REFI_VAL[4]
32 ----------------------MCB:MEM_REFI_VAL[5]
33 ----------------------MCB:MEM_REFI_VAL[6]
34 ----------------------MCB:MEM_REFI_VAL[7]
35 ----------------------MCB:MEM_REFI_VAL[8]
36 ----------------------MCB:MEM_REFI_VAL[9]
37 ----------------------MCB:MEM_REFI_VAL[10]
38 ----------------------MCB:MEM_REFI_VAL[11]
MCB bittile 11
RowColumn
012345678910111213141516171819202122
0 ----------------------MCB:ARB_TIME_SLOT_0[0]
1 ----------------------MCB:ARB_TIME_SLOT_0[1]
2 ----------------------MCB:ARB_TIME_SLOT_0[2]
3 ----------------------MCB:ARB_TIME_SLOT_0[3]
4 ----------------------MCB:ARB_TIME_SLOT_0[4]
5 ----------------------MCB:ARB_TIME_SLOT_0[5]
6 ----------------------MCB:ARB_TIME_SLOT_0[6]
7 ----------------------MCB:ARB_TIME_SLOT_0[7]
8 ----------------------MCB:ARB_TIME_SLOT_0[8]
9 ----------------------MCB:ARB_TIME_SLOT_0[9]
10 ----------------------MCB:ARB_TIME_SLOT_0[10]
11 ----------------------MCB:ARB_TIME_SLOT_0[11]
12 ----------------------MCB:ARB_TIME_SLOT_0[12]
13 ----------------------MCB:ARB_TIME_SLOT_0[13]
14 ----------------------MCB:ARB_TIME_SLOT_0[14]
15 ----------------------MCB:ARB_TIME_SLOT_0[15]
16 ----------------------MCB:ARB_TIME_SLOT_0[16]
17 ----------------------MCB:ARB_TIME_SLOT_0[17]
18 ----------------------MCB:MEM_WIDTH[0]
19 ----------------------MCB:MEM_WIDTH[1]
20 ----------------------MCB:MEM_TYPE[1]
21 ----------------------MCB:MEM_TYPE[0]
22 -----------------------
23 ----------------------MCB:MEM_BURST_LEN[1]
24 ----------------------MCB:MEM_BURST_LEN[0]
25 ----------------------MCB:PORT_CONFIG[0]
26 ----------------------MCB:PORT_CONFIG[1]
27 ----------------------MCB:PORT_CONFIG[2]
28 -----------------------
29 -----------------------
30 ----------------------~MCB:INV.P0CMDCLK
31 ----------------------MCB:INV.P0CMDEN
MCB bittile 12
RowColumn
MCB bittile 13
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI0R_PORT_CONFIG
1 -------------------------MCB:MUI0R.MEM_WIDTH[0]
2 -------------------------MCB:MUI0R.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI0R.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P0RDEN
7 -------------------------~MCB:INV.P0RDCLK
8 -------------------------MCB:MUI0R.MEM_PLL_POL_SEL
MCB bittile 14
RowColumn
MCB bittile 15
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI0W_PORT_CONFIG
1 -------------------------MCB:MUI0W.MEM_WIDTH[0]
2 -------------------------MCB:MUI0W.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI0W.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P0WREN
7 -------------------------~MCB:INV.P0WRCLK
8 -------------------------MCB:MUI0W.MEM_PLL_POL_SEL
MCB bittile 16
RowColumn
MCB bittile 17
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI1R_PORT_CONFIG
1 -------------------------MCB:MUI1R.MEM_WIDTH[0]
2 -------------------------MCB:MUI1R.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI1R.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P1RDEN
7 -------------------------~MCB:INV.P1RDCLK
8 -------------------------MCB:MUI1R.MEM_PLL_POL_SEL
MCB bittile 18
RowColumn
MCB bittile 19
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI1W_PORT_CONFIG
1 -------------------------MCB:MUI1W.MEM_WIDTH[0]
2 -------------------------MCB:MUI1W.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI1W.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P1WREN
7 -------------------------~MCB:INV.P1WRCLK
8 -------------------------MCB:MUI1W.MEM_PLL_POL_SEL
MCB bittile 20
RowColumn
MCB bittile 21
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI2_PORT_CONFIG
1 -------------------------MCB:MUI0.MEM_WIDTH[0]
2 -------------------------MCB:MUI0.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI0.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P2EN
7 -------------------------~MCB:INV.P2CLK
8 -------------------------MCB:MUI0.MEM_PLL_POL_SEL
MCB bittile 22
RowColumn
MCB bittile 23
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI3_PORT_CONFIG
1 -------------------------MCB:MUI1.MEM_WIDTH[0]
2 -------------------------MCB:MUI1.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI1.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P3EN
7 -------------------------~MCB:INV.P3CLK
8 -------------------------MCB:MUI1.MEM_PLL_POL_SEL
MCB bittile 24
RowColumn
MCB bittile 25
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI4_PORT_CONFIG
1 -------------------------MCB:MUI2.MEM_WIDTH[0]
2 -------------------------MCB:MUI2.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI2.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P4EN
7 -------------------------~MCB:INV.P4CLK
8 -------------------------MCB:MUI2.MEM_PLL_POL_SEL
MCB bittile 26
RowColumn
MCB bittile 27
RowColumn
012345678910111213141516171819202122232425
0 -------------------------MCB:MUI5_PORT_CONFIG
1 -------------------------MCB:MUI3.MEM_WIDTH[0]
2 -------------------------MCB:MUI3.MEM_WIDTH[1]
3 --------------------------
4 --------------------------
5 -------------------------MCB:MUI3.MEM_PLL_DIV_EN
6 -------------------------~MCB:INV.P5EN
7 -------------------------~MCB:INV.P5CLK
8 -------------------------MCB:MUI3.MEM_PLL_POL_SEL
MCB:ARB_TIME_SLOT_0[11, 22, 17][11, 22, 16][11, 22, 15][11, 22, 14][11, 22, 13][11, 22, 12][11, 22, 11][11, 22, 10][11, 22, 9][11, 22, 8][11, 22, 7][11, 22, 6][11, 22, 5][11, 22, 4][11, 22, 3][11, 22, 2][11, 22, 1][11, 22, 0]
MCB:ARB_TIME_SLOT_1[10, 22, 17][10, 22, 16][10, 22, 15][10, 22, 14][10, 22, 13][10, 22, 12][10, 22, 11][10, 22, 10][10, 22, 9][10, 22, 8][10, 22, 7][10, 22, 6][10, 22, 5][10, 22, 4][10, 22, 3][10, 22, 2][10, 22, 1][10, 22, 0]
MCB:ARB_TIME_SLOT_10[1, 22, 17][1, 22, 16][1, 22, 15][1, 22, 14][1, 22, 13][1, 22, 12][1, 22, 11][1, 22, 10][1, 22, 9][1, 22, 8][1, 22, 7][1, 22, 6][1, 22, 5][1, 22, 4][1, 22, 3][1, 22, 2][1, 22, 1][1, 22, 0]
MCB:ARB_TIME_SLOT_11[0, 22, 17][0, 22, 16][0, 22, 15][0, 22, 14][0, 22, 13][0, 22, 12][0, 22, 11][0, 22, 10][0, 22, 9][0, 22, 8][0, 22, 7][0, 22, 6][0, 22, 5][0, 22, 4][0, 22, 3][0, 22, 2][0, 22, 1][0, 22, 0]
MCB:ARB_TIME_SLOT_2[9, 22, 17][9, 22, 16][9, 22, 15][9, 22, 14][9, 22, 13][9, 22, 12][9, 22, 11][9, 22, 10][9, 22, 9][9, 22, 8][9, 22, 7][9, 22, 6][9, 22, 5][9, 22, 4][9, 22, 3][9, 22, 2][9, 22, 1][9, 22, 0]
MCB:ARB_TIME_SLOT_3[8, 22, 17][8, 22, 16][8, 22, 15][8, 22, 14][8, 22, 13][8, 22, 12][8, 22, 11][8, 22, 10][8, 22, 9][8, 22, 8][8, 22, 7][8, 22, 6][8, 22, 5][8, 22, 4][8, 22, 3][8, 22, 2][8, 22, 1][8, 22, 0]
MCB:ARB_TIME_SLOT_4[7, 22, 17][7, 22, 16][7, 22, 15][7, 22, 14][7, 22, 13][7, 22, 12][7, 22, 11][7, 22, 10][7, 22, 9][7, 22, 8][7, 22, 7][7, 22, 6][7, 22, 5][7, 22, 4][7, 22, 3][7, 22, 2][7, 22, 1][7, 22, 0]
MCB:ARB_TIME_SLOT_5[6, 22, 17][6, 22, 16][6, 22, 15][6, 22, 14][6, 22, 13][6, 22, 12][6, 22, 11][6, 22, 10][6, 22, 9][6, 22, 8][6, 22, 7][6, 22, 6][6, 22, 5][6, 22, 4][6, 22, 3][6, 22, 2][6, 22, 1][6, 22, 0]
MCB:ARB_TIME_SLOT_6[5, 22, 17][5, 22, 16][5, 22, 15][5, 22, 14][5, 22, 13][5, 22, 12][5, 22, 11][5, 22, 10][5, 22, 9][5, 22, 8][5, 22, 7][5, 22, 6][5, 22, 5][5, 22, 4][5, 22, 3][5, 22, 2][5, 22, 1][5, 22, 0]
MCB:ARB_TIME_SLOT_7[4, 22, 17][4, 22, 16][4, 22, 15][4, 22, 14][4, 22, 13][4, 22, 12][4, 22, 11][4, 22, 10][4, 22, 9][4, 22, 8][4, 22, 7][4, 22, 6][4, 22, 5][4, 22, 4][4, 22, 3][4, 22, 2][4, 22, 1][4, 22, 0]
MCB:ARB_TIME_SLOT_8[3, 22, 17][3, 22, 16][3, 22, 15][3, 22, 14][3, 22, 13][3, 22, 12][3, 22, 11][3, 22, 10][3, 22, 9][3, 22, 8][3, 22, 7][3, 22, 6][3, 22, 5][3, 22, 4][3, 22, 3][3, 22, 2][3, 22, 1][3, 22, 0]
MCB:ARB_TIME_SLOT_9[2, 22, 17][2, 22, 16][2, 22, 15][2, 22, 14][2, 22, 13][2, 22, 12][2, 22, 11][2, 22, 10][2, 22, 9][2, 22, 8][2, 22, 7][2, 22, 6][2, 22, 5][2, 22, 4][2, 22, 3][2, 22, 2][2, 22, 1][2, 22, 0]
Non-inverted[17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
MCB:CAL_CLK_DIV[0, 22, 19][0, 22, 18]
100
201
410
811
MCB:CAL_CALIBRATION_MODE[0, 22, 21]
CALIBRATION0
NOCALIBRATION1
MCB:CAL_DELAY[0, 22, 23][0, 22, 22]
QUARTER00
HALF01
THREEQUARTER10
FULL11
MCB:CAL_CA[1, 22, 29][1, 22, 28][1, 22, 27][1, 22, 26][1, 22, 25][1, 22, 24][1, 22, 23][1, 22, 22][1, 22, 21][1, 22, 20][1, 22, 19][1, 22, 18]
MCB:MEM_REFI_VAL[10, 22, 38][10, 22, 37][10, 22, 36][10, 22, 35][10, 22, 34][10, 22, 33][10, 22, 32][10, 22, 31][10, 22, 30][10, 22, 29][10, 22, 28][10, 22, 27]
Non-inverted[11][10][9][8][7][6][5][4][3][2][1][0]
MCB:INV.P0CMDCLK[11, 22, 30]
MCB:INV.P0RDCLK[13, 25, 7]
MCB:INV.P0RDEN[13, 25, 6]
MCB:INV.P0WRCLK[15, 25, 7]
MCB:INV.P0WREN[15, 25, 6]
MCB:INV.P1CMDCLK[9, 22, 39]
MCB:INV.P1RDCLK[17, 25, 7]
MCB:INV.P1RDEN[17, 25, 6]
MCB:INV.P1WRCLK[19, 25, 7]
MCB:INV.P1WREN[19, 25, 6]
MCB:INV.P2CLK[21, 25, 7]
MCB:INV.P2CMDCLK[7, 22, 32]
MCB:INV.P2EN[21, 25, 6]
MCB:INV.P3CLK[23, 25, 7]
MCB:INV.P3CMDCLK[5, 22, 32]
MCB:INV.P3EN[23, 25, 6]
MCB:INV.P4CLK[25, 25, 7]
MCB:INV.P4CMDCLK[3, 22, 23]
MCB:INV.P4EN[25, 25, 6]
MCB:INV.P5CLK[27, 25, 7]
MCB:INV.P5CMDCLK[1, 22, 30]
MCB:INV.P5EN[27, 25, 6]
Inverted~[0]
MCB:CAL_BYPASS[3, 22, 19]
MCB:INV.P0CMDEN[11, 22, 31]
MCB:INV.P1CMDEN[9, 22, 40]
MCB:INV.P2CMDEN[7, 22, 33]
MCB:INV.P3CMDEN[5, 22, 33]
MCB:INV.P4CMDEN[3, 22, 24]
MCB:INV.P5CMDEN[1, 22, 31]
MCB:MEM_PLL_DIV_EN[8, 22, 23]
MCB:MUI0.MEM_PLL_DIV_EN[21, 25, 5]
MCB:MUI0R.MEM_PLL_DIV_EN[13, 25, 5]
MCB:MUI0W.MEM_PLL_DIV_EN[15, 25, 5]
MCB:MUI1.MEM_PLL_DIV_EN[23, 25, 5]
MCB:MUI1R.MEM_PLL_DIV_EN[17, 25, 5]
MCB:MUI1W.MEM_PLL_DIV_EN[19, 25, 5]
MCB:MUI2.MEM_PLL_DIV_EN[25, 25, 5]
MCB:MUI3.MEM_PLL_DIV_EN[27, 25, 5]
Non-inverted[0]
MCB:CAL_RA[2, 22, 32][2, 22, 31][2, 22, 30][2, 22, 29][2, 22, 28][2, 22, 27][2, 22, 26][2, 22, 25][2, 22, 24][2, 22, 23][2, 22, 22][2, 22, 21][2, 22, 20][2, 22, 19][2, 22, 18]
Non-inverted[14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
MCB:CAL_BA[3, 22, 22][3, 22, 21][3, 22, 20]
MCB:MEM_RCD_VAL[10, 22, 25][10, 22, 24][10, 22, 23]
MCB:MEM_RTP_VAL[9, 22, 35][9, 22, 34][9, 22, 33]
MCB:MEM_WR_VAL[9, 22, 32][9, 22, 31][9, 22, 30]
MCB:MEM_WTR_VAL[9, 22, 38][9, 22, 37][9, 22, 36]
Non-inverted[2][1][0]
MCB:EMR1[6, 22, 31][6, 22, 30][6, 22, 29][6, 22, 28][6, 22, 27][6, 22, 26][6, 22, 25][6, 22, 24][6, 22, 23][6, 22, 22][6, 22, 21][6, 22, 20][6, 22, 19][6, 22, 18]
MCB:EMR2[5, 22, 31][5, 22, 30][5, 22, 29][5, 22, 28][5, 22, 27][5, 22, 26][5, 22, 25][5, 22, 24][5, 22, 23][5, 22, 22][5, 22, 21][5, 22, 20][5, 22, 19][5, 22, 18]
MCB:EMR3[4, 22, 31][4, 22, 30][4, 22, 29][4, 22, 28][4, 22, 27][4, 22, 26][4, 22, 25][4, 22, 24][4, 22, 23][4, 22, 22][4, 22, 21][4, 22, 20][4, 22, 19][4, 22, 18]
MCB:MR[7, 22, 31][7, 22, 30][7, 22, 29][7, 22, 28][7, 22, 27][7, 22, 26][7, 22, 25][7, 22, 24][7, 22, 23][7, 22, 22][7, 22, 21][7, 22, 20][7, 22, 19][7, 22, 18]
Non-inverted[13][12][11][10][9][8][7][6][5][4][3][2][1][0]
MCB:MEM_DDR2_3_PA_SR[5, 22, 20][5, 22, 19][5, 22, 18]
FULL000
HALF1001
QUARTER1010
EIGHTH1011
THREEQUARTER100
HALF2101
QUARTER2110
EIGHTH2111
MCB:MEM_DDR3_CAS_WR_LATENCY[5, 22, 22][5, 22, 21]
500
601
710
811
MCB:MEM_DDR3_AUTO_SR[5, 22, 24]
MANUAL0
ENABLED1
MCB:MEM_DDR2_3_HIGH_TEMP_SR[5, 22, 25]
NORMAL0
EXTENDED1
MCB:MEM_DDR3_DYN_WRT_ODT[5, 22, 28][5, 22, 27]
NONE00
DIV201
DIV410
MCB:MEM_MOBILE_PA_SR[6, 22, 18]
FULL0
HALF1
MCB:MEM_DDR1_2_ODS[6, 22, 19]
FULL0
REDUCED1
MCB:MEM_DDR3_ODS[6, 22, 19]
DIV60
DIV71
MCB:MEM_DDR2_RTT[6, 22, 24][6, 22, 20]
NONE00
75OHMS01
150OHMS10
50OHMS11
MCB:MEM_DDR3_ADD_LATENCY[6, 22, 22][6, 22, 21]
NONE00
CL101
CL210
MCB:MEM_MOBILE_TC_SR[6, 22, 22][6, 22, 21]
000
101
210
311
MCB:MEM_DDR2_ADD_LATENCY[6, 22, 23][6, 22, 22][6, 22, 21]
0000
1001
2010
3011
4100
5101
MCB:MEM_DDR3_RTT[6, 22, 27][6, 22, 20][6, 22, 24]
NONE000
DIV2001
DIV4010
DIV6011
DIV8100
DIV12110
MCB:MEM_MDDR_ODS[6, 22, 25][6, 22, 23][6, 22, 24]
FULL000
QUARTER001
HALF010
THREEQUARTERS100
MCB:MEM_DDR2_DIFF_DQS_EN[6, 22, 28]
YES0
NO1
MCB:MEM_BURST_LEN[11, 22, 23][11, 22, 24]
MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[7, 22, 18][7, 22, 19]
401
811
MCB:MEM_CAS_LATENCY[7, 22, 24][7, 22, 23][7, 22, 22]
1001
2010
3011
4100
5101
6110
MCB:MEM_DDR3_CAS_LATENCY[7, 22, 24][7, 22, 23][7, 22, 22]
5001
6010
7011
8100
9101
10110
MCB:MEM_DDR2_WRT_RECOVERY[7, 22, 29][7, 22, 28][7, 22, 27]
2001
3010
4011
5100
6101
MCB:MEM_DDR3_WRT_RECOVERY[7, 22, 29][7, 22, 28][7, 22, 27]
5001
6010
7011
8100
10101
12110
MCB:MEM_PLL_POL_SEL[8, 22, 22]
MCB:MUI0.MEM_PLL_POL_SEL[21, 25, 8]
MCB:MUI0R.MEM_PLL_POL_SEL[13, 25, 8]
MCB:MUI0W.MEM_PLL_POL_SEL[15, 25, 8]
MCB:MUI1.MEM_PLL_POL_SEL[23, 25, 8]
MCB:MUI1R.MEM_PLL_POL_SEL[17, 25, 8]
MCB:MUI1W.MEM_PLL_POL_SEL[19, 25, 8]
MCB:MUI2.MEM_PLL_POL_SEL[25, 25, 8]
MCB:MUI3.MEM_PLL_POL_SEL[27, 25, 8]
INVERTED0
NOTINVERTED1
MCB:ARB_NUM_TIME_SLOTS[8, 22, 26]
100
121
MCB:MEM_BA_SIZE[8, 22, 27]
20
31
MCB:MEM_RA_SIZE[8, 22, 29][8, 22, 28]
1200
1301
1410
1511
MCB:MEM_CA_SIZE[8, 22, 31][8, 22, 30]
900
1001
1110
1211
MCB:MEM_ADDR_ORDER[8, 22, 32]
BANK_ROW_COLUMN0
ROW_BANK_COLUMN1
MCB:MEM_RFC_VAL[9, 22, 25][9, 22, 24][9, 22, 23][9, 22, 22][9, 22, 21][9, 22, 20][9, 22, 19][9, 22, 18]
Non-inverted[7][6][5][4][3][2][1][0]
MCB:MEM_RP_VAL[9, 22, 29][9, 22, 28][9, 22, 27][9, 22, 26]
Non-inverted[3][2][1][0]
MCB:MEM_RAS_VAL[10, 22, 22][10, 22, 21][10, 22, 20][10, 22, 19][10, 22, 18]
Non-inverted[4][3][2][1][0]
MCB:MEM_WIDTH[11, 22, 19][11, 22, 18]
MCB:MUI0.MEM_WIDTH[21, 25, 2][21, 25, 1]
MCB:MUI0R.MEM_WIDTH[13, 25, 2][13, 25, 1]
MCB:MUI0W.MEM_WIDTH[15, 25, 2][15, 25, 1]
MCB:MUI1.MEM_WIDTH[23, 25, 2][23, 25, 1]
MCB:MUI1R.MEM_WIDTH[17, 25, 2][17, 25, 1]
MCB:MUI1W.MEM_WIDTH[19, 25, 2][19, 25, 1]
MCB:MUI2.MEM_WIDTH[25, 25, 2][25, 25, 1]
MCB:MUI3.MEM_WIDTH[27, 25, 2][27, 25, 1]
401
810
1611
MCB:MEM_TYPE[11, 22, 20][11, 22, 21]
DDR300
DDR01
DDR210
MDDR11
MCB:PORT_CONFIG[11, 22, 27][11, 22, 26][11, 22, 25]
B32_B32_X32_X32_X32_X32000
B32_B32_B32_B32001
B64_B32_B32010
B64_B64011
B128100
MCB:MUI0R_PORT_CONFIG[13, 25, 0]
MCB:MUI0W_PORT_CONFIG[15, 25, 0]
MCB:MUI1R_PORT_CONFIG[17, 25, 0]
MCB:MUI1W_PORT_CONFIG[19, 25, 0]
MCB:MUI2_PORT_CONFIG[21, 25, 0]
MCB:MUI3_PORT_CONFIG[23, 25, 0]
MCB:MUI4_PORT_CONFIG[25, 25, 0]
MCB:MUI5_PORT_CONFIG[27, 25, 0]
WRITE0
READ1